[llvm-branch-commits] [llvm] 884d89a - Revert "[memprof] Introduce FrameIdConverter and CallStackIdConverter (#90307)"
Author: Vitaly Buka
Date: 2024-04-27T00:09:08-07:00
New Revision: 884d89aab141a3016d8d5b42ed163e649a969ad4
URL:
https://github.com/llvm/llvm-project/commit/884d89aab141a3016d8d5b42ed163e649a969ad4
DIFF:
https://github.com/llvm/llvm-project/commit/884d89aab141a3016d8d5b42ed163e649a969ad4.diff
LOG: Revert "[memprof] Introduce FrameIdConverter and CallStackIdConverter
(#90307)"
This reverts commit e04df693bf5b38099ef1d7ab8e6ce6a1469597e2.
Added:
Modified:
llvm/include/llvm/ProfileData/MemProf.h
llvm/include/llvm/ProfileData/MemProfReader.h
llvm/lib/ProfileData/InstrProfReader.cpp
llvm/unittests/ProfileData/InstrProfTest.cpp
llvm/unittests/ProfileData/MemProfTest.cpp
Removed:
diff --git a/llvm/include/llvm/ProfileData/MemProf.h
b/llvm/include/llvm/ProfileData/MemProf.h
index 8b00faf2a219df..d378c3696f8d0b 100644
--- a/llvm/include/llvm/ProfileData/MemProf.h
+++ b/llvm/include/llvm/ProfileData/MemProf.h
@@ -737,64 +737,6 @@ class CallStackLookupTrait {
// Compute a CallStackId for a given call stack.
CallStackId hashCallStack(ArrayRef CS);
-namespace detail {
-// "Dereference" the iterator from DenseMap or OnDiskChainedHashTable. We have
-// to do so in one of two
diff erent ways depending on the type of the hash
-// table.
-template
-value_type DerefIterator(IterTy Iter) {
- using deref_type = llvm::remove_cvref_t;
- if constexpr (std::is_same_v)
-return *Iter;
- else
-return Iter->second;
-}
-} // namespace detail
-
-// A function object that returns a frame for a given FrameId.
-template struct FrameIdConverter {
- std::optional LastUnmappedId;
- MapTy
-
- FrameIdConverter() = delete;
- FrameIdConverter(MapTy ) : Map(Map) {}
-
- Frame operator()(FrameId Id) {
-auto Iter = Map.find(Id);
-if (Iter == Map.end()) {
- LastUnmappedId = Id;
- return Frame(0, 0, 0, false);
-}
-return detail::DerefIterator(Iter);
- }
-};
-
-// A function object that returns a call stack for a given CallStackId.
-template struct CallStackIdConverter {
- std::optional LastUnmappedId;
- MapTy
- std::function FrameIdToFrame;
-
- CallStackIdConverter() = delete;
- CallStackIdConverter(MapTy , std::function
FrameIdToFrame)
- : Map(Map), FrameIdToFrame(FrameIdToFrame) {}
-
- llvm::SmallVector operator()(CallStackId CSId) {
-llvm::SmallVector Frames;
-auto CSIter = Map.find(CSId);
-if (CSIter == Map.end()) {
- LastUnmappedId = CSId;
-} else {
- llvm::SmallVector CS =
- detail::DerefIterator>(CSIter);
- Frames.reserve(CS.size());
- for (FrameId Id : CS)
-Frames.push_back(FrameIdToFrame(Id));
-}
-return Frames;
- }
-};
-
// Verify that each CallStackId is computed with hashCallStack. This function
// is intended to help transition from CallStack to CSId in
// IndexedAllocationInfo.
diff --git a/llvm/include/llvm/ProfileData/MemProfReader.h
b/llvm/include/llvm/ProfileData/MemProfReader.h
index b42e4f59777409..444c58e8bdc8bc 100644
--- a/llvm/include/llvm/ProfileData/MemProfReader.h
+++ b/llvm/include/llvm/ProfileData/MemProfReader.h
@@ -76,16 +76,20 @@ class MemProfReader {
Callback =
std::bind(::idToFrame, this, std::placeholders::_1);
-memprof::CallStackIdConverter CSIdConv(
-CSIdToCallStack, Callback);
+auto CallStackCallback = [&](CallStackId CSId) {
+ llvm::SmallVector CallStack;
+ auto Iter = CSIdToCallStack.find(CSId);
+ assert(Iter != CSIdToCallStack.end());
+ for (FrameId Id : Iter->second)
+CallStack.push_back(Callback(Id));
+ return CallStack;
+};
const IndexedMemProfRecord = Iter->second;
GuidRecord = {
Iter->first,
-IndexedRecord.toMemProfRecord(CSIdConv),
+IndexedRecord.toMemProfRecord(CallStackCallback),
};
-if (CSIdConv.LastUnmappedId)
- return make_error(instrprof_error::hash_mismatch);
Iter++;
return Error::success();
}
diff --git a/llvm/lib/ProfileData/InstrProfReader.cpp
b/llvm/lib/ProfileData/InstrProfReader.cpp
index 440be2f255d392..cefb6af12d0021 100644
--- a/llvm/lib/ProfileData/InstrProfReader.cpp
+++ b/llvm/lib/ProfileData/InstrProfReader.cpp
@@ -1520,35 +1520,53 @@ IndexedMemProfReader::getMemProfRecord(const uint64_t
FuncNameHash) const {
// Setup a callback to convert from frame ids to frame using the on-disk
// FrameData hash table.
- memprof::FrameIdConverter FrameIdConv(
- *MemProfFrameTable.get());
+ std::optional LastUnmappedFrameId;
+ auto IdToFrameCallback = [&](const memprof::FrameId Id) {
+auto FrIter = MemProfFrameTable->find(Id);
+if (FrIter == MemProfFrameTable->end()) {
+ LastUnmappedFrameId = Id;
+ return memprof::Frame(0, 0, 0, false);
+}
+return *FrIter;
+ };
// Setup a callback to convert call stack ids to call stacks using the
on-disk
// hash table.
[llvm-branch-commits] [clang] [CIR] Add options to emit ClangIR and enable the ClangIR pipeline (PR #89030)
https://github.com/lanza updated https://github.com/llvm/llvm-project/pull/89030 >From 21d80d2c5e2d67d54bfb450eb53b1fa73ffb635a Mon Sep 17 00:00:00 2001 From: Nathan Lanza Date: Wed, 17 Apr 2024 07:26:49 + Subject: [PATCH] fix options.td Created using spr 1.3.5 --- clang/include/clang/Driver/Options.td | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 659650baf218f8..3c64ad45c1f86a 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -2876,18 +2876,21 @@ def flax_vector_conversions : Flag<["-"], "flax-vector-conversions">, Group, Group, HelpText<"Force linking the clang builtins runtime library">; -def flto_EQ : Joined<["-"], "flto=">, - Visibility<[ClangOption, CLOption, CC1Option, FC1Option, FlangOption]>, - Group, - HelpText<"Set LTO mode">, Values<"thin,full">; -def flto_EQ_jobserver : Flag<["-"], "flto=jobserver">, Visibility<[ClangOption, FlangOption]>, Group, - Alias, AliasArgs<["full"]>, HelpText<"Enable LTO in 'full' mode">; + /// ClangIR-specific options - BEGIN def fclangir_enable : Flag<["-"], "fclangir-enable">, Visibility<[ClangOption, CC1Option]>, Group, HelpText<"Use ClangIR pipeline to compile">, MarshallingInfoFlag>; def emit_cir : Flag<["-"], "emit-cir">, Visibility<[ClangOption, CC1Option]>, Group, HelpText<"Build ASTs and then lower to ClangIR, emit the .cir file">; +/// ClangIR-specific options - END + +def flto_EQ : Joined<["-"], "flto=">, + Visibility<[ClangOption, CLOption, CC1Option, FC1Option, FlangOption]>, + Group, + HelpText<"Set LTO mode">, Values<"thin,full">; +def flto_EQ_jobserver : Flag<["-"], "flto=jobserver">, Visibility<[ClangOption, FlangOption]>, Group, + Alias, AliasArgs<["full"]>, HelpText<"Enable LTO in 'full' mode">; def flto_EQ_auto : Flag<["-"], "flto=auto">, Visibility<[ClangOption, FlangOption]>, Group, Alias, AliasArgs<["full"]>, HelpText<"Enable LTO in 'full' mode">; def flto : Flag<["-"], "flto">, ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [CIR] Add options to emit ClangIR and enable the ClangIR pipeline (PR #89030)
https://github.com/lanza updated https://github.com/llvm/llvm-project/pull/89030 >From 21d80d2c5e2d67d54bfb450eb53b1fa73ffb635a Mon Sep 17 00:00:00 2001 From: Nathan Lanza Date: Wed, 17 Apr 2024 07:26:49 + Subject: [PATCH] fix options.td Created using spr 1.3.5 --- clang/include/clang/Driver/Options.td | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 659650baf218f8..3c64ad45c1f86a 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -2876,18 +2876,21 @@ def flax_vector_conversions : Flag<["-"], "flax-vector-conversions">, Group, Group, HelpText<"Force linking the clang builtins runtime library">; -def flto_EQ : Joined<["-"], "flto=">, - Visibility<[ClangOption, CLOption, CC1Option, FC1Option, FlangOption]>, - Group, - HelpText<"Set LTO mode">, Values<"thin,full">; -def flto_EQ_jobserver : Flag<["-"], "flto=jobserver">, Visibility<[ClangOption, FlangOption]>, Group, - Alias, AliasArgs<["full"]>, HelpText<"Enable LTO in 'full' mode">; + /// ClangIR-specific options - BEGIN def fclangir_enable : Flag<["-"], "fclangir-enable">, Visibility<[ClangOption, CC1Option]>, Group, HelpText<"Use ClangIR pipeline to compile">, MarshallingInfoFlag>; def emit_cir : Flag<["-"], "emit-cir">, Visibility<[ClangOption, CC1Option]>, Group, HelpText<"Build ASTs and then lower to ClangIR, emit the .cir file">; +/// ClangIR-specific options - END + +def flto_EQ : Joined<["-"], "flto=">, + Visibility<[ClangOption, CLOption, CC1Option, FC1Option, FlangOption]>, + Group, + HelpText<"Set LTO mode">, Values<"thin,full">; +def flto_EQ_jobserver : Flag<["-"], "flto=jobserver">, Visibility<[ClangOption, FlangOption]>, Group, + Alias, AliasArgs<["full"]>, HelpText<"Enable LTO in 'full' mode">; def flto_EQ_auto : Flag<["-"], "flto=auto">, Visibility<[ClangOption, FlangOption]>, Group, Alias, AliasArgs<["full"]>, HelpText<"Enable LTO in 'full' mode">; def flto : Flag<["-"], "flto">, ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] b95e62b - Revert "[WebAssembly] remove instruction after builtin trap (#90207)"
Author: Mehdi Amini
Date: 2024-04-27T21:12:47+02:00
New Revision: b95e62ba350fedcf01b3220279c007fb75723106
URL:
https://github.com/llvm/llvm-project/commit/b95e62ba350fedcf01b3220279c007fb75723106
DIFF:
https://github.com/llvm/llvm-project/commit/b95e62ba350fedcf01b3220279c007fb75723106.diff
LOG: Revert "[WebAssembly] remove instruction after builtin trap (#90207)"
This reverts commit ff03f23be8bc6df701efd9e1093779fbcf382d87.
Added:
Modified:
llvm/lib/Target/WebAssembly/CMakeLists.txt
llvm/lib/Target/WebAssembly/WebAssembly.h
llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
llvm/test/CodeGen/WebAssembly/unreachable.ll
llvm/test/MC/WebAssembly/global-ctor-dtor.ll
Removed:
llvm/lib/Target/WebAssembly/WebAssemblyCleanCodeAfterTrap.cpp
diff --git a/llvm/lib/Target/WebAssembly/CMakeLists.txt
b/llvm/lib/Target/WebAssembly/CMakeLists.txt
index 1e83cbeac50d6d..f430be2653b4ee 100644
--- a/llvm/lib/Target/WebAssembly/CMakeLists.txt
+++ b/llvm/lib/Target/WebAssembly/CMakeLists.txt
@@ -19,7 +19,6 @@ add_llvm_target(WebAssemblyCodeGen
WebAssemblyArgumentMove.cpp
WebAssemblyAsmPrinter.cpp
WebAssemblyCFGStackify.cpp
- WebAssemblyCleanCodeAfterTrap.cpp
WebAssemblyCFGSort.cpp
WebAssemblyDebugFixup.cpp
WebAssemblyDebugValueManager.cpp
diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.h
b/llvm/lib/Target/WebAssembly/WebAssembly.h
index 7fc8546248f164..1c40addb6d6f78 100644
--- a/llvm/lib/Target/WebAssembly/WebAssembly.h
+++ b/llvm/lib/Target/WebAssembly/WebAssembly.h
@@ -37,7 +37,6 @@ FunctionPass
*createWebAssemblyISelDag(WebAssemblyTargetMachine ,
CodeGenOptLevel OptLevel);
FunctionPass *createWebAssemblyArgumentMove();
FunctionPass *createWebAssemblySetP2AlignOperands();
-FunctionPass *createWebAssemblyCleanCodeAfterTrap();
// Late passes.
FunctionPass *createWebAssemblyReplacePhysRegs();
@@ -64,7 +63,6 @@ void initializeOptimizeReturnedPass(PassRegistry &);
void initializeWebAssemblyRefTypeMem2LocalPass(PassRegistry &);
void initializeWebAssemblyAddMissingPrototypesPass(PassRegistry &);
void initializeWebAssemblyArgumentMovePass(PassRegistry &);
-void initializeWebAssemblyCleanCodeAfterTrapPass(PassRegistry &);
void initializeWebAssemblyCFGSortPass(PassRegistry &);
void initializeWebAssemblyCFGStackifyPass(PassRegistry &);
void initializeWebAssemblyDAGToDAGISelPass(PassRegistry &);
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCleanCodeAfterTrap.cpp
b/llvm/lib/Target/WebAssembly/WebAssemblyCleanCodeAfterTrap.cpp
deleted file mode 100644
index e5cba3c485473c..00
--- a/llvm/lib/Target/WebAssembly/WebAssemblyCleanCodeAfterTrap.cpp
+++ /dev/null
@@ -1,80 +0,0 @@
-//===-- WebAssemblyCleanCodeAfterTrap.cpp - Clean Code After Trap
-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===--===//
-///
-/// \file
-/// This file remove instruction after trap.
-/// ``llvm.trap`` will be convert as ``unreachable`` which is terminator.
-/// Instruction after terminator will cause validation failed.
-///
-//===--===//
-
-#include "WebAssembly.h"
-#include "WebAssemblyUtilities.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/MC/MCInstrDesc.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/raw_ostream.h"
-using namespace llvm;
-
-#define DEBUG_TYPE "wasm-clean-code-after-trap"
-
-namespace {
-class WebAssemblyCleanCodeAfterTrap final : public MachineFunctionPass {
-public:
- static char ID; // Pass identification, replacement for typeid
- WebAssemblyCleanCodeAfterTrap() : MachineFunctionPass(ID) {}
-
- StringRef getPassName() const override {
-return "WebAssembly Clean Code After Trap";
- }
-
- bool runOnMachineFunction(MachineFunction ) override;
-};
-} // end anonymous namespace
-
-char WebAssemblyCleanCodeAfterTrap::ID = 0;
-INITIALIZE_PASS(WebAssemblyCleanCodeAfterTrap, DEBUG_TYPE,
-"WebAssembly Clean Code After Trap", false, false)
-
-FunctionPass *llvm::createWebAssemblyCleanCodeAfterTrap() {
- return new WebAssemblyCleanCodeAfterTrap();
-}
-
-bool WebAssemblyCleanCodeAfterTrap::runOnMachineFunction(MachineFunction ) {
- LLVM_DEBUG({
-dbgs() << "** CleanCodeAfterTrap **\n"
- << "** Function: " << MF.getName() << '\n';
- });
-
- bool Changed = false;
-
- for (MachineBasicBlock : MF) {
-bool HasTerminator = false;
-llvm::SmallVector RemoveMI{};
-for (MachineInstr : BB) {
- if (HasTerminator)
-
[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/7] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?UTF-8?q?itial=20version?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.4 --- clang/test/Driver/riscv-cpus.c| 319 ++ clang/test/Misc/target-invalid-cpu-note.c | 8 +- llvm/lib/Target/RISCV/RISCVProcessors.td | 224 ++- 3 files changed, 539 insertions(+), 12 deletions(-) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index ff2bd6f7c8ba34..a285f0f9c41f54 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -302,3 +302,322 @@ // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64 + +// Check profile CPUs + +// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 | FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s +// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f" +// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m" +// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 | FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s +// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-a" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-c" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-d" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-f" +// MCPU-GENERIC-RVI20U64: "-target-feature" "-m" +// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 | FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s +// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+m" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+a" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+f" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+d" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+c" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs" +// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 | FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s +// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade" +// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare" +// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 | FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s +// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop" +// MCPU-GENERIC-RVA22U64-SAME: "-target-feature"
[llvm-branch-commits] [RISCV] Make fixed-point instructions commutable (PR #90372)
llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
Author: Pengcheng Wang (wangpc-pp)
Changes
This PR includes:
* vsadd.vv/vsaddu.vv
* vaadd.vv/vaaddu.vv
* vsmul.vv
---
Full diff: https://github.com/llvm/llvm-project/pull/90372.diff
3 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+5)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td (+16-13)
- (modified) llvm/test/CodeGen/RISCV/rvv/commutable.ll (+6-8)
``diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 3efd09aeae879d..8cb9a40a98bcd8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3132,6 +3132,11 @@ bool RISCVInstrInfo::findCommutedOpIndices(const
MachineInstr ,
case CASE_RVV_OPCODE_WIDEN(VWMACC_VV):
case CASE_RVV_OPCODE_WIDEN(VWMACCU_VV):
case CASE_RVV_OPCODE_UNMASK(VADC_VVM):
+ case CASE_RVV_OPCODE(VSADD_VV):
+ case CASE_RVV_OPCODE(VSADDU_VV):
+ case CASE_RVV_OPCODE(VAADD_VV):
+ case CASE_RVV_OPCODE(VAADDU_VV):
+ case CASE_RVV_OPCODE(VSMUL_VV):
// Operands 2 and 3 are commutable.
return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
case CASE_VFMA_SPLATS(FMADD):
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index e9715b40adc079..fc60a9cc7cd30e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -2146,8 +2146,9 @@ multiclass VPseudoBinaryRoundingMode {
- let VLMul = MInfo.value, SEW=sew in {
+ int TargetConstraintType = 1,
+ bit Commutable = 0> {
+ let VLMul = MInfo.value, SEW=sew, isCommutable = Commutable in {
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
def suffix : VPseudoBinaryNoMaskRoundingMode;
}
-multiclass VPseudoBinaryV_VV_RM {
- defm _VV : VPseudoBinaryRoundingMode;
+multiclass VPseudoBinaryV_VV_RM {
+ defm _VV : VPseudoBinaryRoundingMode;
}
// Similar to VPseudoBinaryV_VV, but uses MxListF.
@@ -2715,10 +2717,11 @@ multiclass VPseudoVGTR_VV_VX_VI
}
}
-multiclass VPseudoVSALU_VV_VX_VI {
+multiclass VPseudoVSALU_VV_VX_VI {
foreach m = MxList in {
defvar mx = m.MX;
-defm "" : VPseudoBinaryV_VV,
+defm "" : VPseudoBinaryV_VV,
SchedBinary<"WriteVSALUV", "ReadVSALUV", "ReadVSALUX", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_VX,
@@ -2788,7 +2791,7 @@ multiclass VPseudoVSALU_VV_VX {
multiclass VPseudoVSMUL_VV_VX_RM {
foreach m = MxList in {
defvar mx = m.MX;
-defm "" : VPseudoBinaryV_VV_RM,
+defm "" : VPseudoBinaryV_VV_RM,
SchedBinary<"WriteVSMulV", "ReadVSMulV", "ReadVSMulV", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_VX_RM,
@@ -2797,10 +2800,10 @@ multiclass VPseudoVSMUL_VV_VX_RM {
}
}
-multiclass VPseudoVAALU_VV_VX_RM {
+multiclass VPseudoVAALU_VV_VX_RM {
foreach m = MxList in {
defvar mx = m.MX;
-defm "" : VPseudoBinaryV_VV_RM,
+defm "" : VPseudoBinaryV_VV_RM,
SchedBinary<"WriteVAALUV", "ReadVAALUV", "ReadVAALUV", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_VX_RM,
@@ -6448,8 +6451,8 @@ defm PseudoVMV_V : VPseudoUnaryVMV_V_X_I;
// 12.1. Vector Single-Width Saturating Add and Subtract
//===--===//
let Defs = [VXSAT], hasSideEffects = 1 in {
- defm PseudoVSADDU : VPseudoVSALU_VV_VX_VI;
- defm PseudoVSADD : VPseudoVSALU_VV_VX_VI;
+ defm PseudoVSADDU : VPseudoVSALU_VV_VX_VI;
+ defm PseudoVSADD : VPseudoVSALU_VV_VX_VI;
defm PseudoVSSUBU : VPseudoVSALU_VV_VX;
defm PseudoVSSUB : VPseudoVSALU_VV_VX;
}
@@ -6457,8 +6460,8 @@ let Defs = [VXSAT], hasSideEffects = 1 in {
//===--===//
// 12.2. Vector Single-Width Averaging Add and Subtract
//===--===//
-defm PseudoVAADDU : VPseudoVAALU_VV_VX_RM;
-defm PseudoVAADD : VPseudoVAALU_VV_VX_RM;
+defm PseudoVAADDU : VPseudoVAALU_VV_VX_RM;
+defm PseudoVAADD : VPseudoVAALU_VV_VX_RM;
defm PseudoVASUBU : VPseudoVAALU_VV_VX_RM;
defm PseudoVASUB : VPseudoVAALU_VV_VX_RM;
diff --git a/llvm/test/CodeGen/RISCV/rvv/commutable.ll
b/llvm/test/CodeGen/RISCV/rvv/commutable.ll
index e383c1b477c45d..06a6327d3892b6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/commutable.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/commutable.ll
@@ -724,10 +724,9 @@ define @commutable_vaadd_vv( %0, @llvm.riscv.vaadd.nxv1i64.nxv1i64( undef, %0, %1, iXLen 0, iXLen %2)
@@ -743,7 +742,7 @@ define
@commutable_vaadd_vv_masked( %0, @commutable_vaaddu_vv( %0, @llvm.riscv.vaaddu.nxv1i64.nxv1i64( undef, %0, %1, iXLen 0, iXLen %2)
@@ -779,7 +777,7 @@ define
[llvm-branch-commits] [RISCV] Make fixed-point instructions commutable (PR #90372)
https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/90372 This PR includes: * vsadd.vv/vsaddu.vv * vaadd.vv/vaaddu.vv * vsmul.vv ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
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https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/90372 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/90187 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/90187 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)
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[llvm-branch-commits] [clang] release/18.x: [clang][CoverageMapping] do not emit a gap region when either end doesn't have valid source locations (#89564) (PR #90369)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/90369
Backport c1b6cca1214e7a9c14a30b81585dd8b81baeaa77
Requested by: @whentojump
>From 71dd393acd7948b8290e65d082c509fd2df4c02f Mon Sep 17 00:00:00 2001
From: Wentao Zhang <35722712+whentoj...@users.noreply.github.com>
Date: Mon, 22 Apr 2024 12:37:38 -0500
Subject: [PATCH] [clang][CoverageMapping] do not emit a gap region when either
end doesn't have valid source locations (#89564)
Fixes #86998
(cherry picked from commit c1b6cca1214e7a9c14a30b81585dd8b81baeaa77)
---
clang/lib/CodeGen/CoverageMappingGen.cpp | 11 --
.../CoverageMapping/statement-expression.c| 36 +++
2 files changed, 44 insertions(+), 3 deletions(-)
create mode 100644 clang/test/CoverageMapping/statement-expression.c
diff --git a/clang/lib/CodeGen/CoverageMappingGen.cpp
b/clang/lib/CodeGen/CoverageMappingGen.cpp
index 0c43317642bca4..ae4e6d4c88c02d 100644
--- a/clang/lib/CodeGen/CoverageMappingGen.cpp
+++ b/clang/lib/CodeGen/CoverageMappingGen.cpp
@@ -1207,6 +1207,12 @@ struct CounterCoverageMappingBuilder
/// Find a valid gap range between \p AfterLoc and \p BeforeLoc.
std::optional findGapAreaBetween(SourceLocation AfterLoc,
SourceLocation BeforeLoc) {
+// Some statements (like AttributedStmt and ImplicitValueInitExpr) don't
+// have valid source locations. Do not emit a gap region if this is the
case
+// in either AfterLoc end or BeforeLoc end.
+if (AfterLoc.isInvalid() || BeforeLoc.isInvalid())
+ return std::nullopt;
+
// If AfterLoc is in function-like macro, use the right parenthesis
// location.
if (AfterLoc.isMacroID()) {
@@ -1370,9 +1376,8 @@ struct CounterCoverageMappingBuilder
for (const Stmt *Child : S->children())
if (Child) {
// If last statement contains terminate statements, add a gap area
-// between the two statements. Skipping attributed statements, because
-// they don't have valid start location.
-if (LastStmt && HasTerminateStmt && !isa(Child)) {
+// between the two statements.
+if (LastStmt && HasTerminateStmt) {
auto Gap = findGapAreaBetween(getEnd(LastStmt), getStart(Child));
if (Gap)
fillGapAreaWithCount(Gap->getBegin(), Gap->getEnd(),
diff --git a/clang/test/CoverageMapping/statement-expression.c
b/clang/test/CoverageMapping/statement-expression.c
new file mode 100644
index 00..5f9ab5838af342
--- /dev/null
+++ b/clang/test/CoverageMapping/statement-expression.c
@@ -0,0 +1,36 @@
+// RUN: %clang_cc1 -mllvm -emptyline-comment-coverage=false
-fprofile-instrument=clang -fcoverage-mapping -dump-coverage-mapping
-emit-llvm-only -main-file-name statement-expression.c %s
+
+// No crash for the following examples, where GNU Statement Expression
extension
+// could introduce region terminators (break, goto etc) before implicit
+// initializers in a struct or an array.
+// See https://github.com/llvm/llvm-project/pull/89564
+
+struct Foo {
+ int field1;
+ int field2;
+};
+
+void f1(void) {
+ struct Foo foo = {
+.field1 = ({
+ switch (0) {
+ case 0:
+break; // A region terminator
+ }
+ 0;
+}),
+// ImplicitValueInitExpr introduced here for .field2
+ };
+}
+
+void f2(void) {
+ int arr[3] = {
+[0] = ({
+goto L0; // A region terminator
+L0:
+ 0;
+}),
+// ImplicitValueInitExpr introduced here for subscript [1]
+[2] = 0,
+ };
+}
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[llvm-branch-commits] [clang] release/18.x: [clang][CoverageMapping] do not emit a gap region when either end doesn't have valid source locations (#89564) (PR #90369)
llvmbot wrote:
@llvm/pr-subscribers-clang-codegen
Author: None (llvmbot)
Changes
Backport c1b6cca1214e7a9c14a30b81585dd8b81baeaa77
Requested by: @whentojump
---
Full diff: https://github.com/llvm/llvm-project/pull/90369.diff
2 Files Affected:
- (modified) clang/lib/CodeGen/CoverageMappingGen.cpp (+8-3)
- (added) clang/test/CoverageMapping/statement-expression.c (+36)
``diff
diff --git a/clang/lib/CodeGen/CoverageMappingGen.cpp
b/clang/lib/CodeGen/CoverageMappingGen.cpp
index 0c43317642bca4..ae4e6d4c88c02d 100644
--- a/clang/lib/CodeGen/CoverageMappingGen.cpp
+++ b/clang/lib/CodeGen/CoverageMappingGen.cpp
@@ -1207,6 +1207,12 @@ struct CounterCoverageMappingBuilder
/// Find a valid gap range between \p AfterLoc and \p BeforeLoc.
std::optional findGapAreaBetween(SourceLocation AfterLoc,
SourceLocation BeforeLoc) {
+// Some statements (like AttributedStmt and ImplicitValueInitExpr) don't
+// have valid source locations. Do not emit a gap region if this is the
case
+// in either AfterLoc end or BeforeLoc end.
+if (AfterLoc.isInvalid() || BeforeLoc.isInvalid())
+ return std::nullopt;
+
// If AfterLoc is in function-like macro, use the right parenthesis
// location.
if (AfterLoc.isMacroID()) {
@@ -1370,9 +1376,8 @@ struct CounterCoverageMappingBuilder
for (const Stmt *Child : S->children())
if (Child) {
// If last statement contains terminate statements, add a gap area
-// between the two statements. Skipping attributed statements, because
-// they don't have valid start location.
-if (LastStmt && HasTerminateStmt && !isa(Child)) {
+// between the two statements.
+if (LastStmt && HasTerminateStmt) {
auto Gap = findGapAreaBetween(getEnd(LastStmt), getStart(Child));
if (Gap)
fillGapAreaWithCount(Gap->getBegin(), Gap->getEnd(),
diff --git a/clang/test/CoverageMapping/statement-expression.c
b/clang/test/CoverageMapping/statement-expression.c
new file mode 100644
index 00..5f9ab5838af342
--- /dev/null
+++ b/clang/test/CoverageMapping/statement-expression.c
@@ -0,0 +1,36 @@
+// RUN: %clang_cc1 -mllvm -emptyline-comment-coverage=false
-fprofile-instrument=clang -fcoverage-mapping -dump-coverage-mapping
-emit-llvm-only -main-file-name statement-expression.c %s
+
+// No crash for the following examples, where GNU Statement Expression
extension
+// could introduce region terminators (break, goto etc) before implicit
+// initializers in a struct or an array.
+// See https://github.com/llvm/llvm-project/pull/89564
+
+struct Foo {
+ int field1;
+ int field2;
+};
+
+void f1(void) {
+ struct Foo foo = {
+.field1 = ({
+ switch (0) {
+ case 0:
+break; // A region terminator
+ }
+ 0;
+}),
+// ImplicitValueInitExpr introduced here for .field2
+ };
+}
+
+void f2(void) {
+ int arr[3] = {
+[0] = ({
+goto L0; // A region terminator
+L0:
+ 0;
+}),
+// ImplicitValueInitExpr introduced here for subscript [1]
+[2] = 0,
+ };
+}
``
https://github.com/llvm/llvm-project/pull/90369
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[llvm-branch-commits] [clang] release/18.x: [clang][CoverageMapping] do not emit a gap region when either end doesn't have valid source locations (#89564) (PR #90369)
llvmbot wrote: @ZequanWu What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/90369 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/18.x: [clang][CoverageMapping] do not emit a gap region when either end doesn't have valid source locations (#89564) (PR #90369)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/90369 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
