[llvm-branch-commits] [llvm] release/20.x: [gtest] Fix building on OpenBSD/sparc64 (#145225) (PR #146155)
llvmbot wrote: @AaronBallman What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/146155 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [gtest] Fix building on OpenBSD/sparc64 (#145225) (PR #146155)
https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/146155 Backport 68239b76f139e44d24f3949383e3fd4bf389e1c9 Requested by: @brad0 >From d13980a5da3b60db55ad33303a7e78b964b91ff6 Mon Sep 17 00:00:00 2001 From: Brad Smith Date: Fri, 27 Jun 2025 16:56:17 -0400 Subject: [PATCH] [gtest] Fix building on OpenBSD/sparc64 (#145225) Cherry pick a patch from 1.15.0 Add missing include for raise(3) https://github.com/google/googletest/commit/7f036c5563af7d0329f20e8bb42effb04629f0c0 (cherry picked from commit 68239b76f139e44d24f3949383e3fd4bf389e1c9) --- third-party/unittest/googletest/src/gtest.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/third-party/unittest/googletest/src/gtest.cc b/third-party/unittest/googletest/src/gtest.cc index 30a5cc3f83a7e..37d380a789831 100644 --- a/third-party/unittest/googletest/src/gtest.cc +++ b/third-party/unittest/googletest/src/gtest.cc @@ -43,6 +43,7 @@ #include #include // NOLINT #include +#include #include #include #include ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [gtest] Fix building on OpenBSD/sparc64 (#145225) (PR #146155)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/146155 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-tools-extra] [clang-doc] serialize friends (PR #146165)
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff HEAD~1 HEAD --extensions h,cpp --
clang-tools-extra/clang-doc/BitcodeReader.cpp
clang-tools-extra/clang-doc/BitcodeWriter.cpp
clang-tools-extra/clang-doc/BitcodeWriter.h
clang-tools-extra/clang-doc/HTMLGenerator.cpp
clang-tools-extra/clang-doc/HTMLMustacheGenerator.cpp
clang-tools-extra/clang-doc/JSONGenerator.cpp
clang-tools-extra/clang-doc/MDGenerator.cpp
clang-tools-extra/clang-doc/Representation.cpp
clang-tools-extra/clang-doc/Representation.h
clang-tools-extra/clang-doc/Serialize.cpp
clang-tools-extra/clang-doc/YAMLGenerator.cpp
clang-tools-extra/test/clang-doc/json/class.cpp
clang-tools-extra/unittests/clang-doc/BitcodeTest.cpp
``
View the diff from clang-format here.
``diff
diff --git a/clang-tools-extra/clang-doc/Representation.cpp
b/clang-tools-extra/clang-doc/Representation.cpp
index ba53329a4..422a76d99 100644
--- a/clang-tools-extra/clang-doc/Representation.cpp
+++ b/clang-tools-extra/clang-doc/Representation.cpp
@@ -435,7 +435,7 @@ llvm::SmallString<16> Info::extractName() const {
case InfoType::IT_variable:
return llvm::SmallString<16>("@nonymous_variable_" +
toHex(llvm::toStringRef(USR)));
- case InfoType::IT_friend:
+ case InfoType::IT_friend:
return llvm::SmallString<16>("@nonymous_friend_" +
toHex(llvm::toStringRef(USR)));
case InfoType::IT_default:
``
https://github.com/llvm/llvm-project/pull/146165
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[llvm-branch-commits] [clang-tools-extra] [clang-doc] Precommit friends test (PR #146164)
https://github.com/evelez7 created
https://github.com/llvm/llvm-project/pull/146164
None
>From bf66a99ae2cb8ae90be8b905fedc60d4e10d3c5e Mon Sep 17 00:00:00 2001
From: Erick Velez
Date: Thu, 26 Jun 2025 20:51:33 -0700
Subject: [PATCH] [clang-doc] Precommit friends test
---
.../test/clang-doc/json/class.cpp | 41 +++
1 file changed, 41 insertions(+)
diff --git a/clang-tools-extra/test/clang-doc/json/class.cpp
b/clang-tools-extra/test/clang-doc/json/class.cpp
index bd82b8159e2f9..0715fcefbb785 100644
--- a/clang-tools-extra/test/clang-doc/json/class.cpp
+++ b/clang-tools-extra/test/clang-doc/json/class.cpp
@@ -23,6 +23,9 @@ struct MyClass {
typedef int MyTypedef;
class NestedClass;
+
+ friend struct Foo;
+ template friend void friendFunction(int);
protected:
int protectedMethod();
@@ -86,6 +89,44 @@ struct MyClass {
// CHECK-NEXT:"USR": "{{[0-9A-F]*}}"
// CHECK-NEXT: }
// CHECK-NEXT:],
+// CHECK-NOT: "Friends": [
+// CHECK-NOT: {
+// CHECK-NOT: "IsClass": false,
+// CHECK-NOT: "Params": [
+// CHECK-NOT: {
+// CHECK-NOT: "Name": "",
+// CHECK-NOT: "Type": "int"
+// CHECK-NOT: }
+// CHECK-NOT: ],
+// CHECK-NOT: "Reference": {
+// CHECK-NOT: "Name": "friendFunction",
+// CHECK-NOT: "Path": "",
+// CHECK-NOT: "QualName": "friendFunction",
+// CHECK-NOT: "USR": "{{[0-9A-F]*}}"
+// CHECK-NOT: },
+// CHECK-NOT: "ReturnType": {
+// CHECK-NOT: "IsBuiltIn": true,
+// CHECK-NOT: "IsTemplate": false,
+// CHECK-NOT: "Name": "void",
+// CHECK-NOT: "QualName": "void",
+// CHECK-NOT: "USR": ""
+// CHECK-NOT: },
+// CHECK-NOT: "Template": {
+// CHECK-NOT: "Parameters": [
+// CHECK-NOT: "typename T"
+// CHECK-NOT: ]
+// CHECK-NOT: }
+// CHECK-NOT: },
+// CHECK-NOT: {
+// CHECK-NOT: "IsClass": true,
+// CHECK-NOT: "Reference": {
+// CHECK-NOT: "Name": "Foo",
+// CHECK-NOT: "Path": "GlobalNamespace",
+// CHECK-NOT: "QualName": "Foo",
+// CHECK-NOT: "USR": "{{[0-9A-F]*}}"
+// CHECK-NOT: },
+// CHECK-NOT: },
+// CHECK-NOT:],
// COM: FIXME: FullName is not emitted correctly.
// CHECK-NEXT:"FullName": "",
// CHECK-NEXT:"IsTypedef": false,
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[llvm-branch-commits] [clang-tools-extra] [clang-doc] serialize friends (PR #146165)
https://github.com/evelez7 created
https://github.com/llvm/llvm-project/pull/146165
None
>From a373ecb94c6137fb8de62226b9cfbfe8c8840564 Mon Sep 17 00:00:00 2001
From: Erick Velez
Date: Thu, 26 Jun 2025 20:54:03 -0700
Subject: [PATCH] [clang-doc] serialize friends
---
clang-tools-extra/clang-doc/BitcodeReader.cpp | 46 +++
clang-tools-extra/clang-doc/BitcodeWriter.cpp | 27 ++-
clang-tools-extra/clang-doc/BitcodeWriter.h | 6 +-
clang-tools-extra/clang-doc/HTMLGenerator.cpp | 3 +
.../clang-doc/HTMLMustacheGenerator.cpp | 1 +
clang-tools-extra/clang-doc/JSONGenerator.cpp | 23 +-
clang-tools-extra/clang-doc/MDGenerator.cpp | 4 +
.../clang-doc/Representation.cpp | 16
clang-tools-extra/clang-doc/Representation.h | 21 -
clang-tools-extra/clang-doc/Serialize.cpp | 53 +
clang-tools-extra/clang-doc/YAMLGenerator.cpp | 1 +
.../test/clang-doc/json/class.cpp | 76 +--
.../unittests/clang-doc/BitcodeTest.cpp | 2 +
13 files changed, 234 insertions(+), 45 deletions(-)
diff --git a/clang-tools-extra/clang-doc/BitcodeReader.cpp
b/clang-tools-extra/clang-doc/BitcodeReader.cpp
index fd6f40cff1a4e..2cbf8bf6b2879 100644
--- a/clang-tools-extra/clang-doc/BitcodeReader.cpp
+++ b/clang-tools-extra/clang-doc/BitcodeReader.cpp
@@ -94,6 +94,7 @@ static llvm::Error decodeRecord(const Record &R, InfoType
&Field,
case InfoType::IT_typedef:
case InfoType::IT_concept:
case InfoType::IT_variable:
+ case InfoType::IT_friend:
Field = IT;
return llvm::Error::success();
}
@@ -111,6 +112,7 @@ static llvm::Error decodeRecord(const Record &R, FieldId
&Field,
case FieldId::F_child_namespace:
case FieldId::F_child_record:
case FieldId::F_concept:
+ case FieldId::F_friend:
case FieldId::F_default:
Field = F;
return llvm::Error::success();
@@ -450,6 +452,15 @@ static llvm::Error parseRecord(const Record &R, unsigned
ID,
}
}
+static llvm::Error parseRecord(const Record &R, unsigned ID, StringRef Blob,
+ FriendInfo *F) {
+ if (ID == FRIEND_IS_CLASS) {
+return decodeRecord(R, F->IsClass, Blob);
+ }
+ return llvm::createStringError(llvm::inconvertibleErrorCode(),
+ "invalid field for Friend");
+}
+
template static llvm::Expected getCommentInfo(T I)
{
return llvm::createStringError(llvm::inconvertibleErrorCode(),
"invalid type cannot contain CommentInfo");
@@ -525,6 +536,18 @@ template <> llvm::Error addTypeInfo(FunctionInfo *I,
FieldTypeInfo &&T) {
return llvm::Error::success();
}
+template <> llvm::Error addTypeInfo(FriendInfo *I, FieldTypeInfo &&T) {
+ if (!I->Params)
+I->Params.emplace();
+ I->Params->emplace_back(std::move(T));
+ return llvm::Error::success();
+}
+
+template <> llvm::Error addTypeInfo(FriendInfo *I, TypeInfo &&T) {
+ I->ReturnType.emplace(std::move(T));
+ return llvm::Error::success();
+}
+
template <> llvm::Error addTypeInfo(EnumInfo *I, TypeInfo &&T) {
I->BaseType = std::move(T);
return llvm::Error::success();
@@ -667,6 +690,16 @@ llvm::Error addReference(ConstraintInfo *I, Reference &&R,
FieldId F) {
"ConstraintInfo cannot contain this Reference");
}
+template <>
+llvm::Error addReference(FriendInfo *Friend, Reference &&R, FieldId F) {
+ if (F == FieldId::F_friend) {
+Friend->Ref = std::move(R);
+return llvm::Error::success();
+ }
+ return llvm::createStringError(llvm::inconvertibleErrorCode(),
+ "Friend cannot contain this Reference");
+}
+
template
static void addChild(T I, ChildInfoType &&R) {
llvm::errs() << "invalid child type for info";
@@ -700,6 +733,9 @@ template <> void addChild(RecordInfo *I, EnumInfo &&R) {
template <> void addChild(RecordInfo *I, TypedefInfo &&R) {
I->Children.Typedefs.emplace_back(std::move(R));
}
+template <> void addChild(RecordInfo *I, FriendInfo &&R) {
+ I->Friends.emplace_back(std::move(R));
+}
// Other types of children:
template <> void addChild(EnumInfo *I, EnumValueInfo &&R) {
@@ -741,6 +777,9 @@ template <> void addTemplate(FunctionInfo *I, TemplateInfo
&&P) {
template <> void addTemplate(ConceptInfo *I, TemplateInfo &&P) {
I->Template = std::move(P);
}
+template <> void addTemplate(FriendInfo *I, TemplateInfo &&P) {
+ I->Template.emplace(std::move(P));
+}
// Template specializations go only into template records.
template
@@ -921,6 +960,10 @@ llvm::Error ClangDocBitcodeReader::readSubBlock(unsigned
ID, T I) {
case BI_VAR_BLOCK_ID: {
return handleSubBlock(ID, I, CreateAddFunc(addChild));
}
+ case BI_FRIEND_BLOCK_ID: {
+return handleSubBlock(ID, I,
+ CreateAddFunc(addChild));
+ }
default:
return llvm::createStringError(llvm::inconvertibleErrorCode(),
"invalid subblock type");
@@ -1032,6 +1075,8 @@ ClangDocBitc
[llvm-branch-commits] [clang-tools-extra] [clang-doc] Precommit friends test (PR #146164)
evelez7 wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146164?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#146165** https://app.graphite.dev/github/pr/llvm/llvm-project/146165?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#146164** https://app.graphite.dev/github/pr/llvm/llvm-project/146164?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/146164?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#146149** https://app.graphite.dev/github/pr/llvm/llvm-project/146149?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/146164 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-tools-extra] [clang-doc] serialize friends (PR #146165)
evelez7 wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146165?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#146165** https://app.graphite.dev/github/pr/llvm/llvm-project/146165?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/146165?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#146164** https://app.graphite.dev/github/pr/llvm/llvm-project/146164?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#146149** https://app.graphite.dev/github/pr/llvm/llvm-project/146149?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/146165 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-tools-extra] [clang-doc] serialize friends (PR #146165)
@@ -947,6 +952,53 @@ emitInfo(const NamespaceDecl *D, const FullComment *FC,
Location Loc,
return {std::move(NSI), makeAndInsertIntoParent(*NSI)};
}
+static void parseFriends(RecordInfo &RI, const CXXRecordDecl *D) {
+ if (D->hasDefinition() && D->hasFriends())
ilovepi wrote:
I think if you invert the condition you can use early return to avoid a level
of nesting.
https://github.com/llvm/llvm-project/pull/146165
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[llvm-branch-commits] [clang-tools-extra] [clang-doc] Precommit friends test (PR #146164)
https://github.com/ilovepi approved this pull request. https://github.com/llvm/llvm-project/pull/146164 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-tools-extra] [clang-doc] serialize friends (PR #146165)
https://github.com/ilovepi edited https://github.com/llvm/llvm-project/pull/146165 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-tools-extra] [clang-doc] serialize friends (PR #146165)
https://github.com/ilovepi approved this pull request. LGTM, modulo formatting and 1 small suggestion. https://github.com/llvm/llvm-project/pull/146165 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-tools-extra] [clang-doc] serialize friends (PR #146165)
https://github.com/evelez7 updated
https://github.com/llvm/llvm-project/pull/146165
>From 8dd16ca8d38692a5d60227bd5a4a133972dac9f6 Mon Sep 17 00:00:00 2001
From: Erick Velez
Date: Thu, 26 Jun 2025 20:54:03 -0700
Subject: [PATCH] [clang-doc] serialize friends
---
clang-tools-extra/clang-doc/BitcodeReader.cpp | 46 +++
clang-tools-extra/clang-doc/BitcodeWriter.cpp | 27 ++-
clang-tools-extra/clang-doc/BitcodeWriter.h | 6 +-
clang-tools-extra/clang-doc/HTMLGenerator.cpp | 3 +
.../clang-doc/HTMLMustacheGenerator.cpp | 1 +
clang-tools-extra/clang-doc/JSONGenerator.cpp | 23 +-
clang-tools-extra/clang-doc/MDGenerator.cpp | 4 +
.../clang-doc/Representation.cpp | 16
clang-tools-extra/clang-doc/Representation.h | 21 -
clang-tools-extra/clang-doc/Serialize.cpp | 53 +
clang-tools-extra/clang-doc/YAMLGenerator.cpp | 1 +
.../test/clang-doc/json/class.cpp | 76 +--
.../unittests/clang-doc/BitcodeTest.cpp | 2 +
13 files changed, 234 insertions(+), 45 deletions(-)
diff --git a/clang-tools-extra/clang-doc/BitcodeReader.cpp
b/clang-tools-extra/clang-doc/BitcodeReader.cpp
index fd6f40cff1a4e..2cbf8bf6b2879 100644
--- a/clang-tools-extra/clang-doc/BitcodeReader.cpp
+++ b/clang-tools-extra/clang-doc/BitcodeReader.cpp
@@ -94,6 +94,7 @@ static llvm::Error decodeRecord(const Record &R, InfoType
&Field,
case InfoType::IT_typedef:
case InfoType::IT_concept:
case InfoType::IT_variable:
+ case InfoType::IT_friend:
Field = IT;
return llvm::Error::success();
}
@@ -111,6 +112,7 @@ static llvm::Error decodeRecord(const Record &R, FieldId
&Field,
case FieldId::F_child_namespace:
case FieldId::F_child_record:
case FieldId::F_concept:
+ case FieldId::F_friend:
case FieldId::F_default:
Field = F;
return llvm::Error::success();
@@ -450,6 +452,15 @@ static llvm::Error parseRecord(const Record &R, unsigned
ID,
}
}
+static llvm::Error parseRecord(const Record &R, unsigned ID, StringRef Blob,
+ FriendInfo *F) {
+ if (ID == FRIEND_IS_CLASS) {
+return decodeRecord(R, F->IsClass, Blob);
+ }
+ return llvm::createStringError(llvm::inconvertibleErrorCode(),
+ "invalid field for Friend");
+}
+
template static llvm::Expected getCommentInfo(T I)
{
return llvm::createStringError(llvm::inconvertibleErrorCode(),
"invalid type cannot contain CommentInfo");
@@ -525,6 +536,18 @@ template <> llvm::Error addTypeInfo(FunctionInfo *I,
FieldTypeInfo &&T) {
return llvm::Error::success();
}
+template <> llvm::Error addTypeInfo(FriendInfo *I, FieldTypeInfo &&T) {
+ if (!I->Params)
+I->Params.emplace();
+ I->Params->emplace_back(std::move(T));
+ return llvm::Error::success();
+}
+
+template <> llvm::Error addTypeInfo(FriendInfo *I, TypeInfo &&T) {
+ I->ReturnType.emplace(std::move(T));
+ return llvm::Error::success();
+}
+
template <> llvm::Error addTypeInfo(EnumInfo *I, TypeInfo &&T) {
I->BaseType = std::move(T);
return llvm::Error::success();
@@ -667,6 +690,16 @@ llvm::Error addReference(ConstraintInfo *I, Reference &&R,
FieldId F) {
"ConstraintInfo cannot contain this Reference");
}
+template <>
+llvm::Error addReference(FriendInfo *Friend, Reference &&R, FieldId F) {
+ if (F == FieldId::F_friend) {
+Friend->Ref = std::move(R);
+return llvm::Error::success();
+ }
+ return llvm::createStringError(llvm::inconvertibleErrorCode(),
+ "Friend cannot contain this Reference");
+}
+
template
static void addChild(T I, ChildInfoType &&R) {
llvm::errs() << "invalid child type for info";
@@ -700,6 +733,9 @@ template <> void addChild(RecordInfo *I, EnumInfo &&R) {
template <> void addChild(RecordInfo *I, TypedefInfo &&R) {
I->Children.Typedefs.emplace_back(std::move(R));
}
+template <> void addChild(RecordInfo *I, FriendInfo &&R) {
+ I->Friends.emplace_back(std::move(R));
+}
// Other types of children:
template <> void addChild(EnumInfo *I, EnumValueInfo &&R) {
@@ -741,6 +777,9 @@ template <> void addTemplate(FunctionInfo *I, TemplateInfo
&&P) {
template <> void addTemplate(ConceptInfo *I, TemplateInfo &&P) {
I->Template = std::move(P);
}
+template <> void addTemplate(FriendInfo *I, TemplateInfo &&P) {
+ I->Template.emplace(std::move(P));
+}
// Template specializations go only into template records.
template
@@ -921,6 +960,10 @@ llvm::Error ClangDocBitcodeReader::readSubBlock(unsigned
ID, T I) {
case BI_VAR_BLOCK_ID: {
return handleSubBlock(ID, I, CreateAddFunc(addChild));
}
+ case BI_FRIEND_BLOCK_ID: {
+return handleSubBlock(ID, I,
+ CreateAddFunc(addChild));
+ }
default:
return llvm::createStringError(llvm::inconvertibleErrorCode(),
"invalid subblock type");
@@ -1032,6 +1075,8 @@ ClangDocBitcodeRea
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (PR #145912)
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https://github.com/nhaehnle approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/145912 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (PR #145912)
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[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (PR #145912)
@@ -57,6 +57,224 @@ void
RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
lower(MI, Mapping, WaterfallSgprs);
}
+bool RegBankLegalizeHelper::executeInWaterfallLoop(
+MachineIRBuilder &B, iterator_range Range,
+SmallSet &SGPROperandRegs) {
+ // Track use registers which have already been expanded with a readfirstlane
+ // sequence. This may have multiple uses if moving a sequence.
+ DenseMap WaterfalledRegMap;
+
+ MachineBasicBlock &MBB = B.getMBB();
+ MachineFunction &MF = B.getMF();
+
+ const SIRegisterInfo *TRI = ST.getRegisterInfo();
+ const TargetRegisterClass *WaveRC = TRI->getWaveMaskRegClass();
+ unsigned MovExecOpc, MovExecTermOpc, XorTermOpc, AndSaveExecOpc, ExecReg;
+ if (IsWave32) {
nhaehnle wrote:
Long ago, I actually thought it would be nice to have a "LaneMaskHelper" class
that does this setup, since it's duplicated in a bunch of places. But I don't
feel particularly strongly about it -- not for this PR.
https://github.com/llvm/llvm-project/pull/145912
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[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Improve readanylane combines in regbanklegalize (PR #145911)
@@ -115,126 +117,233 @@ class AMDGPURegBankLegalizeCombiner {
VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)),
VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {};
- bool isLaneMask(Register Reg) {
-const RegisterBank *RB = MRI.getRegBankOrNull(Reg);
-if (RB && RB->getID() == AMDGPU::VCCRegBankID)
- return true;
+ bool isLaneMask(Register Reg);
+ std::pair tryMatch(Register Src, unsigned Opcode);
+ std::pair tryMatchRALFromUnmerge(Register Src);
+ Register getReadAnyLaneSrc(Register Src);
+ void replaceRegWithOrBuildCopy(Register Dst, Register Src);
-const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
-return RC && TRI.isSGPRClass(RC) && MRI.getType(Reg) == LLT::scalar(1);
- }
+ bool tryEliminateReadAnyLane(MachineInstr &Copy);
+ void tryCombineCopy(MachineInstr &MI);
+ void tryCombineS1AnyExt(MachineInstr &MI);
+};
- void cleanUpAfterCombine(MachineInstr &MI, MachineInstr *Optional0) {
-MI.eraseFromParent();
-if (Optional0 && isTriviallyDead(*Optional0, MRI))
- Optional0->eraseFromParent();
- }
+bool AMDGPURegBankLegalizeCombiner::isLaneMask(Register Reg) {
+ const RegisterBank *RB = MRI.getRegBankOrNull(Reg);
+ if (RB && RB->getID() == AMDGPU::VCCRegBankID)
+return true;
- std::pair tryMatch(Register Src, unsigned Opcode) {
-MachineInstr *MatchMI = MRI.getVRegDef(Src);
-if (MatchMI->getOpcode() != Opcode)
- return {nullptr, Register()};
-return {MatchMI, MatchMI->getOperand(1).getReg()};
- }
+ const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
+ return RC && TRI.isSGPRClass(RC) && MRI.getType(Reg) == LLT::scalar(1);
+}
- void tryCombineCopy(MachineInstr &MI) {
-Register Dst = MI.getOperand(0).getReg();
-Register Src = MI.getOperand(1).getReg();
-// Skip copies of physical registers.
-if (!Dst.isVirtual() || !Src.isVirtual())
- return;
-
-// This is a cross bank copy, sgpr S1 to lane mask.
-//
-// %Src:sgpr(s1) = G_TRUNC %TruncS32Src:sgpr(s32)
-// %Dst:lane-mask(s1) = COPY %Src:sgpr(s1)
-// ->
-// %Dst:lane-mask(s1) = G_AMDGPU_COPY_VCC_SCC %TruncS32Src:sgpr(s32)
-if (isLaneMask(Dst) && MRI.getRegBankOrNull(Src) == SgprRB) {
- auto [Trunc, TruncS32Src] = tryMatch(Src, AMDGPU::G_TRUNC);
- assert(Trunc && MRI.getType(TruncS32Src) == S32 &&
- "sgpr S1 must be result of G_TRUNC of sgpr S32");
-
- B.setInstr(MI);
- // Ensure that truncated bits in BoolSrc are 0.
- auto One = B.buildConstant({SgprRB, S32}, 1);
- auto BoolSrc = B.buildAnd({SgprRB, S32}, TruncS32Src, One);
- B.buildInstr(AMDGPU::G_AMDGPU_COPY_VCC_SCC, {Dst}, {BoolSrc});
- cleanUpAfterCombine(MI, Trunc);
- return;
-}
+std::pair
+AMDGPURegBankLegalizeCombiner::tryMatch(Register Src, unsigned Opcode) {
+ MachineInstr *MatchMI = MRI.getVRegDef(Src);
+ if (MatchMI->getOpcode() != Opcode)
+return {nullptr, Register()};
+ return {MatchMI, MatchMI->getOperand(1).getReg()};
+}
nhaehnle wrote:
Is there a better name for this than `tryMatch`? Come to think of it, can the
generic matching infrastructure be used for this?
https://github.com/llvm/llvm-project/pull/145911
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[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Improve readanylane combines in regbanklegalize (PR #145911)
@@ -115,126 +117,233 @@ class AMDGPURegBankLegalizeCombiner {
VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)),
VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {};
- bool isLaneMask(Register Reg) {
-const RegisterBank *RB = MRI.getRegBankOrNull(Reg);
-if (RB && RB->getID() == AMDGPU::VCCRegBankID)
- return true;
+ bool isLaneMask(Register Reg);
+ std::pair tryMatch(Register Src, unsigned Opcode);
+ std::pair tryMatchRALFromUnmerge(Register Src);
+ Register getReadAnyLaneSrc(Register Src);
+ void replaceRegWithOrBuildCopy(Register Dst, Register Src);
-const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
-return RC && TRI.isSGPRClass(RC) && MRI.getType(Reg) == LLT::scalar(1);
- }
+ bool tryEliminateReadAnyLane(MachineInstr &Copy);
+ void tryCombineCopy(MachineInstr &MI);
+ void tryCombineS1AnyExt(MachineInstr &MI);
+};
- void cleanUpAfterCombine(MachineInstr &MI, MachineInstr *Optional0) {
-MI.eraseFromParent();
-if (Optional0 && isTriviallyDead(*Optional0, MRI))
- Optional0->eraseFromParent();
- }
+bool AMDGPURegBankLegalizeCombiner::isLaneMask(Register Reg) {
+ const RegisterBank *RB = MRI.getRegBankOrNull(Reg);
+ if (RB && RB->getID() == AMDGPU::VCCRegBankID)
+return true;
- std::pair tryMatch(Register Src, unsigned Opcode) {
-MachineInstr *MatchMI = MRI.getVRegDef(Src);
-if (MatchMI->getOpcode() != Opcode)
- return {nullptr, Register()};
-return {MatchMI, MatchMI->getOperand(1).getReg()};
- }
+ const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
+ return RC && TRI.isSGPRClass(RC) && MRI.getType(Reg) == LLT::scalar(1);
+}
- void tryCombineCopy(MachineInstr &MI) {
-Register Dst = MI.getOperand(0).getReg();
-Register Src = MI.getOperand(1).getReg();
-// Skip copies of physical registers.
-if (!Dst.isVirtual() || !Src.isVirtual())
- return;
-
-// This is a cross bank copy, sgpr S1 to lane mask.
-//
-// %Src:sgpr(s1) = G_TRUNC %TruncS32Src:sgpr(s32)
-// %Dst:lane-mask(s1) = COPY %Src:sgpr(s1)
-// ->
-// %Dst:lane-mask(s1) = G_AMDGPU_COPY_VCC_SCC %TruncS32Src:sgpr(s32)
-if (isLaneMask(Dst) && MRI.getRegBankOrNull(Src) == SgprRB) {
- auto [Trunc, TruncS32Src] = tryMatch(Src, AMDGPU::G_TRUNC);
- assert(Trunc && MRI.getType(TruncS32Src) == S32 &&
- "sgpr S1 must be result of G_TRUNC of sgpr S32");
-
- B.setInstr(MI);
- // Ensure that truncated bits in BoolSrc are 0.
- auto One = B.buildConstant({SgprRB, S32}, 1);
- auto BoolSrc = B.buildAnd({SgprRB, S32}, TruncS32Src, One);
- B.buildInstr(AMDGPU::G_AMDGPU_COPY_VCC_SCC, {Dst}, {BoolSrc});
- cleanUpAfterCombine(MI, Trunc);
- return;
-}
+std::pair
+AMDGPURegBankLegalizeCombiner::tryMatch(Register Src, unsigned Opcode) {
+ MachineInstr *MatchMI = MRI.getVRegDef(Src);
+ if (MatchMI->getOpcode() != Opcode)
+return {nullptr, Register()};
+ return {MatchMI, MatchMI->getOperand(1).getReg()};
+}
+
+std::pair
+AMDGPURegBankLegalizeCombiner::tryMatchRALFromUnmerge(Register Src) {
+ MachineInstr *ReadAnyLane = MRI.getVRegDef(Src);
+ if (ReadAnyLane->getOpcode() != AMDGPU::G_AMDGPU_READANYLANE)
+return {nullptr, -1};
+
+ Register RALSrc = ReadAnyLane->getOperand(1).getReg();
+ if (auto *UnMerge = getOpcodeDef(RALSrc, MRI))
+return {UnMerge, UnMerge->findRegisterDefOperandIdx(RALSrc, nullptr)};
-// Src = G_AMDGPU_READANYLANE RALSrc
-// Dst = COPY Src
-// ->
-// Dst = RALSrc
-if (MRI.getRegBankOrNull(Dst) == VgprRB &&
-MRI.getRegBankOrNull(Src) == SgprRB) {
- auto [RAL, RALSrc] = tryMatch(Src, AMDGPU::G_AMDGPU_READANYLANE);
- if (!RAL)
-return;
-
- assert(MRI.getRegBank(RALSrc) == VgprRB);
- MRI.replaceRegWith(Dst, RALSrc);
- cleanUpAfterCombine(MI, RAL);
- return;
+ return {nullptr, -1};
+}
+
+Register AMDGPURegBankLegalizeCombiner::getReadAnyLaneSrc(Register Src) {
+ // Src = G_AMDGPU_READANYLANE RALSrc
+ auto [RAL, RALSrc] = tryMatch(Src, AMDGPU::G_AMDGPU_READANYLANE);
+ if (RAL)
+return RALSrc;
+
+ // LoVgpr, HiVgpr = G_UNMERGE_VALUES UnmergeSrc
+ // LoSgpr = G_AMDGPU_READANYLANE LoVgpr
+ // HiSgpr = G_AMDGPU_READANYLANE HiVgpr
+ // Src G_MERGE_VALUES LoSgpr, HiSgpr
+ auto *Merge = getOpcodeDef(Src, MRI);
+ if (Merge) {
+unsigned NumElts = Merge->getNumSources();
+auto [Unmerge, Idx] = tryMatchRALFromUnmerge(Merge->getSourceReg(0));
+if (!Unmerge || Unmerge->getNumDefs() != NumElts || Idx != 0)
+ return {};
+
+// Check if all elements are from same unmerge and there is no shuffling.
+for (unsigned i = 1; i < NumElts; ++i) {
+ auto [UnmergeI, IdxI] = tryMatchRALFromUnmerge(Merge->getSourceReg(i));
+ if (UnmergeI != Unmerge || (unsigned)IdxI != i)
+return {};
}
+return Unmerge->getSourceReg();
}
- void tryCombineS1AnyExt(MachineInstr &MI) {
-// %Src:sgpr(S1) = G_TRUNC %TruncSrc
-
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Improve readanylane combines in regbanklegalize (PR #145911)
@@ -115,126 +117,233 @@ class AMDGPURegBankLegalizeCombiner {
VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)),
VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {};
- bool isLaneMask(Register Reg) {
-const RegisterBank *RB = MRI.getRegBankOrNull(Reg);
-if (RB && RB->getID() == AMDGPU::VCCRegBankID)
- return true;
+ bool isLaneMask(Register Reg);
+ std::pair tryMatch(Register Src, unsigned Opcode);
+ std::pair tryMatchRALFromUnmerge(Register Src);
+ Register getReadAnyLaneSrc(Register Src);
+ void replaceRegWithOrBuildCopy(Register Dst, Register Src);
-const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
-return RC && TRI.isSGPRClass(RC) && MRI.getType(Reg) == LLT::scalar(1);
- }
+ bool tryEliminateReadAnyLane(MachineInstr &Copy);
+ void tryCombineCopy(MachineInstr &MI);
+ void tryCombineS1AnyExt(MachineInstr &MI);
+};
- void cleanUpAfterCombine(MachineInstr &MI, MachineInstr *Optional0) {
-MI.eraseFromParent();
-if (Optional0 && isTriviallyDead(*Optional0, MRI))
- Optional0->eraseFromParent();
- }
+bool AMDGPURegBankLegalizeCombiner::isLaneMask(Register Reg) {
+ const RegisterBank *RB = MRI.getRegBankOrNull(Reg);
+ if (RB && RB->getID() == AMDGPU::VCCRegBankID)
+return true;
- std::pair tryMatch(Register Src, unsigned Opcode) {
-MachineInstr *MatchMI = MRI.getVRegDef(Src);
-if (MatchMI->getOpcode() != Opcode)
- return {nullptr, Register()};
-return {MatchMI, MatchMI->getOperand(1).getReg()};
- }
+ const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
+ return RC && TRI.isSGPRClass(RC) && MRI.getType(Reg) == LLT::scalar(1);
+}
- void tryCombineCopy(MachineInstr &MI) {
-Register Dst = MI.getOperand(0).getReg();
-Register Src = MI.getOperand(1).getReg();
-// Skip copies of physical registers.
-if (!Dst.isVirtual() || !Src.isVirtual())
- return;
-
-// This is a cross bank copy, sgpr S1 to lane mask.
-//
-// %Src:sgpr(s1) = G_TRUNC %TruncS32Src:sgpr(s32)
-// %Dst:lane-mask(s1) = COPY %Src:sgpr(s1)
-// ->
-// %Dst:lane-mask(s1) = G_AMDGPU_COPY_VCC_SCC %TruncS32Src:sgpr(s32)
-if (isLaneMask(Dst) && MRI.getRegBankOrNull(Src) == SgprRB) {
- auto [Trunc, TruncS32Src] = tryMatch(Src, AMDGPU::G_TRUNC);
- assert(Trunc && MRI.getType(TruncS32Src) == S32 &&
- "sgpr S1 must be result of G_TRUNC of sgpr S32");
-
- B.setInstr(MI);
- // Ensure that truncated bits in BoolSrc are 0.
- auto One = B.buildConstant({SgprRB, S32}, 1);
- auto BoolSrc = B.buildAnd({SgprRB, S32}, TruncS32Src, One);
- B.buildInstr(AMDGPU::G_AMDGPU_COPY_VCC_SCC, {Dst}, {BoolSrc});
- cleanUpAfterCombine(MI, Trunc);
- return;
-}
+std::pair
+AMDGPURegBankLegalizeCombiner::tryMatch(Register Src, unsigned Opcode) {
+ MachineInstr *MatchMI = MRI.getVRegDef(Src);
+ if (MatchMI->getOpcode() != Opcode)
+return {nullptr, Register()};
+ return {MatchMI, MatchMI->getOperand(1).getReg()};
+}
+
+std::pair
+AMDGPURegBankLegalizeCombiner::tryMatchRALFromUnmerge(Register Src) {
+ MachineInstr *ReadAnyLane = MRI.getVRegDef(Src);
+ if (ReadAnyLane->getOpcode() != AMDGPU::G_AMDGPU_READANYLANE)
+return {nullptr, -1};
+
+ Register RALSrc = ReadAnyLane->getOperand(1).getReg();
+ if (auto *UnMerge = getOpcodeDef(RALSrc, MRI))
+return {UnMerge, UnMerge->findRegisterDefOperandIdx(RALSrc, nullptr)};
-// Src = G_AMDGPU_READANYLANE RALSrc
-// Dst = COPY Src
-// ->
-// Dst = RALSrc
-if (MRI.getRegBankOrNull(Dst) == VgprRB &&
-MRI.getRegBankOrNull(Src) == SgprRB) {
- auto [RAL, RALSrc] = tryMatch(Src, AMDGPU::G_AMDGPU_READANYLANE);
- if (!RAL)
-return;
-
- assert(MRI.getRegBank(RALSrc) == VgprRB);
- MRI.replaceRegWith(Dst, RALSrc);
- cleanUpAfterCombine(MI, RAL);
- return;
+ return {nullptr, -1};
+}
+
+Register AMDGPURegBankLegalizeCombiner::getReadAnyLaneSrc(Register Src) {
+ // Src = G_AMDGPU_READANYLANE RALSrc
+ auto [RAL, RALSrc] = tryMatch(Src, AMDGPU::G_AMDGPU_READANYLANE);
+ if (RAL)
+return RALSrc;
+
+ // LoVgpr, HiVgpr = G_UNMERGE_VALUES UnmergeSrc
+ // LoSgpr = G_AMDGPU_READANYLANE LoVgpr
+ // HiSgpr = G_AMDGPU_READANYLANE HiVgpr
+ // Src G_MERGE_VALUES LoSgpr, HiSgpr
+ auto *Merge = getOpcodeDef(Src, MRI);
+ if (Merge) {
+unsigned NumElts = Merge->getNumSources();
+auto [Unmerge, Idx] = tryMatchRALFromUnmerge(Merge->getSourceReg(0));
+if (!Unmerge || Unmerge->getNumDefs() != NumElts || Idx != 0)
+ return {};
+
+// Check if all elements are from same unmerge and there is no shuffling.
+for (unsigned i = 1; i < NumElts; ++i) {
+ auto [UnmergeI, IdxI] = tryMatchRALFromUnmerge(Merge->getSourceReg(i));
+ if (UnmergeI != Unmerge || (unsigned)IdxI != i)
+return {};
}
+return Unmerge->getSourceReg();
}
- void tryCombineS1AnyExt(MachineInstr &MI) {
-// %Src:sgpr(S1) = G_TRUNC %TruncSrc
-
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Improve readanylane combines in regbanklegalize (PR #145911)
@@ -115,126 +117,233 @@ class AMDGPURegBankLegalizeCombiner {
VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)),
VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {};
- bool isLaneMask(Register Reg) {
-const RegisterBank *RB = MRI.getRegBankOrNull(Reg);
-if (RB && RB->getID() == AMDGPU::VCCRegBankID)
- return true;
+ bool isLaneMask(Register Reg);
+ std::pair tryMatch(Register Src, unsigned Opcode);
+ std::pair tryMatchRALFromUnmerge(Register Src);
+ Register getReadAnyLaneSrc(Register Src);
+ void replaceRegWithOrBuildCopy(Register Dst, Register Src);
-const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
-return RC && TRI.isSGPRClass(RC) && MRI.getType(Reg) == LLT::scalar(1);
- }
+ bool tryEliminateReadAnyLane(MachineInstr &Copy);
+ void tryCombineCopy(MachineInstr &MI);
+ void tryCombineS1AnyExt(MachineInstr &MI);
+};
- void cleanUpAfterCombine(MachineInstr &MI, MachineInstr *Optional0) {
-MI.eraseFromParent();
-if (Optional0 && isTriviallyDead(*Optional0, MRI))
- Optional0->eraseFromParent();
- }
+bool AMDGPURegBankLegalizeCombiner::isLaneMask(Register Reg) {
+ const RegisterBank *RB = MRI.getRegBankOrNull(Reg);
+ if (RB && RB->getID() == AMDGPU::VCCRegBankID)
+return true;
- std::pair tryMatch(Register Src, unsigned Opcode) {
-MachineInstr *MatchMI = MRI.getVRegDef(Src);
-if (MatchMI->getOpcode() != Opcode)
- return {nullptr, Register()};
-return {MatchMI, MatchMI->getOperand(1).getReg()};
- }
+ const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
+ return RC && TRI.isSGPRClass(RC) && MRI.getType(Reg) == LLT::scalar(1);
+}
- void tryCombineCopy(MachineInstr &MI) {
-Register Dst = MI.getOperand(0).getReg();
-Register Src = MI.getOperand(1).getReg();
-// Skip copies of physical registers.
-if (!Dst.isVirtual() || !Src.isVirtual())
- return;
-
-// This is a cross bank copy, sgpr S1 to lane mask.
-//
-// %Src:sgpr(s1) = G_TRUNC %TruncS32Src:sgpr(s32)
-// %Dst:lane-mask(s1) = COPY %Src:sgpr(s1)
-// ->
-// %Dst:lane-mask(s1) = G_AMDGPU_COPY_VCC_SCC %TruncS32Src:sgpr(s32)
-if (isLaneMask(Dst) && MRI.getRegBankOrNull(Src) == SgprRB) {
- auto [Trunc, TruncS32Src] = tryMatch(Src, AMDGPU::G_TRUNC);
- assert(Trunc && MRI.getType(TruncS32Src) == S32 &&
- "sgpr S1 must be result of G_TRUNC of sgpr S32");
-
- B.setInstr(MI);
- // Ensure that truncated bits in BoolSrc are 0.
- auto One = B.buildConstant({SgprRB, S32}, 1);
- auto BoolSrc = B.buildAnd({SgprRB, S32}, TruncS32Src, One);
- B.buildInstr(AMDGPU::G_AMDGPU_COPY_VCC_SCC, {Dst}, {BoolSrc});
- cleanUpAfterCombine(MI, Trunc);
- return;
-}
+std::pair
+AMDGPURegBankLegalizeCombiner::tryMatch(Register Src, unsigned Opcode) {
+ MachineInstr *MatchMI = MRI.getVRegDef(Src);
+ if (MatchMI->getOpcode() != Opcode)
+return {nullptr, Register()};
+ return {MatchMI, MatchMI->getOperand(1).getReg()};
+}
+
+std::pair
+AMDGPURegBankLegalizeCombiner::tryMatchRALFromUnmerge(Register Src) {
+ MachineInstr *ReadAnyLane = MRI.getVRegDef(Src);
+ if (ReadAnyLane->getOpcode() != AMDGPU::G_AMDGPU_READANYLANE)
+return {nullptr, -1};
+
+ Register RALSrc = ReadAnyLane->getOperand(1).getReg();
+ if (auto *UnMerge = getOpcodeDef(RALSrc, MRI))
+return {UnMerge, UnMerge->findRegisterDefOperandIdx(RALSrc, nullptr)};
-// Src = G_AMDGPU_READANYLANE RALSrc
-// Dst = COPY Src
-// ->
-// Dst = RALSrc
-if (MRI.getRegBankOrNull(Dst) == VgprRB &&
-MRI.getRegBankOrNull(Src) == SgprRB) {
- auto [RAL, RALSrc] = tryMatch(Src, AMDGPU::G_AMDGPU_READANYLANE);
- if (!RAL)
-return;
-
- assert(MRI.getRegBank(RALSrc) == VgprRB);
- MRI.replaceRegWith(Dst, RALSrc);
- cleanUpAfterCombine(MI, RAL);
- return;
+ return {nullptr, -1};
+}
+
+Register AMDGPURegBankLegalizeCombiner::getReadAnyLaneSrc(Register Src) {
+ // Src = G_AMDGPU_READANYLANE RALSrc
+ auto [RAL, RALSrc] = tryMatch(Src, AMDGPU::G_AMDGPU_READANYLANE);
+ if (RAL)
+return RALSrc;
+
+ // LoVgpr, HiVgpr = G_UNMERGE_VALUES UnmergeSrc
+ // LoSgpr = G_AMDGPU_READANYLANE LoVgpr
+ // HiSgpr = G_AMDGPU_READANYLANE HiVgpr
+ // Src G_MERGE_VALUES LoSgpr, HiSgpr
+ auto *Merge = getOpcodeDef(Src, MRI);
+ if (Merge) {
+unsigned NumElts = Merge->getNumSources();
+auto [Unmerge, Idx] = tryMatchRALFromUnmerge(Merge->getSourceReg(0));
+if (!Unmerge || Unmerge->getNumDefs() != NumElts || Idx != 0)
+ return {};
+
+// Check if all elements are from same unmerge and there is no shuffling.
+for (unsigned i = 1; i < NumElts; ++i) {
+ auto [UnmergeI, IdxI] = tryMatchRALFromUnmerge(Merge->getSourceReg(i));
+ if (UnmergeI != Unmerge || (unsigned)IdxI != i)
+return {};
}
+return Unmerge->getSourceReg();
}
- void tryCombineS1AnyExt(MachineInstr &MI) {
-// %Src:sgpr(S1) = G_TRUNC %TruncSrc
-
[llvm-branch-commits] [llvm] RuntimeLibcalls: Associate calling convention with libcall impls (PR #144979)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144979
>From 4f26f1eec65c05c1b6f3e4f6a8bba929549e3e76 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 17 Jun 2025 16:25:50 +0900
Subject: [PATCH] RuntimeLibcalls: Associate calling convention with libcall
impls
Instead of associating the libcall with the RTLIB::Libcall, put it
into a table indexed by the RTLIB::LibcallImpl. The LibcallImpls
should contain all ABI details for a particular implementation, not
the abstract Libcall. In the future the wrappers in terms of the
RTLIB::Libcall should be removed.
---
llvm/include/llvm/CodeGen/TargetLowering.h| 16 -
llvm/include/llvm/IR/RuntimeLibcalls.h| 32 ++---
llvm/lib/IR/RuntimeLibcalls.cpp | 70 +++
llvm/lib/Target/ARM/ARMISelLowering.cpp | 18 ++---
llvm/lib/Target/Lanai/LanaiISelLowering.cpp | 4 +-
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp | 3 +-
6 files changed, 92 insertions(+), 51 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h
b/llvm/include/llvm/CodeGen/TargetLowering.h
index 69ae4f80297d5..fa08eb64642de 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -3562,6 +3562,11 @@ class LLVM_ABI TargetLoweringBase {
Libcalls.setLibcallImpl(Call, Impl);
}
+ /// Get the libcall impl routine name for the specified libcall.
+ RTLIB::LibcallImpl getLibcallImpl(RTLIB::Libcall Call) const {
+return Libcalls.getLibcallImpl(Call);
+ }
+
/// Get the libcall routine name for the specified libcall.
const char *getLibcallName(RTLIB::Libcall Call) const {
return Libcalls.getLibcallName(Call);
@@ -3584,11 +3589,18 @@ class LLVM_ABI TargetLoweringBase {
}
/// Set the CallingConv that should be used for the specified libcall.
- void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
-Libcalls.setLibcallCallingConv(Call, CC);
+ void setLibcallImplCallingConv(RTLIB::LibcallImpl Call, CallingConv::ID CC) {
+Libcalls.setLibcallImplCallingConv(Call, CC);
+ }
+
+ /// Get the CallingConv that should be used for the specified libcall
+ /// implementation.
+ CallingConv::ID getLibcallImplCallingConv(RTLIB::LibcallImpl Call) const {
+return Libcalls.getLibcallImplCallingConv(Call);
}
/// Get the CallingConv that should be used for the specified libcall.
+ // FIXME: Remove this wrapper and directly use the used LibcallImpl
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
return Libcalls.getLibcallCallingConv(Call);
}
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.h
b/llvm/include/llvm/IR/RuntimeLibcalls.h
index 811a9893abde2..8c11ce9ed2920 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.h
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.h
@@ -37,6 +37,10 @@ template <> struct enum_iteration_traits {
static constexpr bool is_iterable = true;
};
+template <> struct enum_iteration_traits {
+ static constexpr bool is_iterable = true;
+};
+
namespace RTLIB {
// Return an iterator over all Libcall values.
@@ -44,6 +48,10 @@ static inline auto libcalls() {
return enum_seq(static_cast(0), RTLIB::UNKNOWN_LIBCALL);
}
+static inline auto libcall_impls() {
+ return enum_seq(static_cast(1), RTLIB::NumLibcallImpls);
+}
+
/// A simple container for information about the supported runtime calls.
struct RuntimeLibcallsInfo {
explicit RuntimeLibcallsInfo(
@@ -76,16 +84,21 @@ struct RuntimeLibcallsInfo {
return LibcallImpls[Call];
}
- /// Set the CallingConv that should be used for the specified libcall.
- // FIXME: This should be a function of RTLIB::LibcallImpl
- void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
-LibcallCallingConvs[Call] = CC;
+ /// Set the CallingConv that should be used for the specified libcall
+ /// implementation
+ void setLibcallImplCallingConv(RTLIB::LibcallImpl Call, CallingConv::ID CC) {
+LibcallImplCallingConvs[Call] = CC;
}
- /// Get the CallingConv that should be used for the specified libcall.
- // FIXME: This should be a function of RTLIB::LibcallImpl
+ // FIXME: Remove this wrapper in favor of directly using
+ // getLibcallImplCallingConv
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
-return LibcallCallingConvs[Call];
+return LibcallImplCallingConvs[LibcallImpls[Call]];
+ }
+
+ /// Get the CallingConv that should be used for the specified libcall.
+ CallingConv::ID getLibcallImplCallingConv(RTLIB::LibcallImpl Call) const {
+return LibcallImplCallingConvs[Call];
}
ArrayRef getLibcallImpls() const {
@@ -130,8 +143,9 @@ struct RuntimeLibcallsInfo {
static_assert(static_cast(CallingConv::C) == 0,
"default calling conv should be encoded as 0");
- /// Stores the CallingConv that should be used for each libcall.
- CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL] = {};
+ /// Stores th
[llvm-branch-commits] [llvm] TableGen: Handle setting runtime libcall calling conventions (PR #144980)
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/144980 >From 9b48b7a4c39b626db5a454a89abb4bbfa4d91a4c Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 13 Jun 2025 15:54:41 +0900 Subject: [PATCH] TableGen: Handle setting runtime libcall calling conventions Allow associating a non-default CallingConv with a set of library functions, and applying a default for a SystemLibrary. I also wanted to be able to apply a default calling conv to a RuntimeLibcallImpl, but that turned out to be annoying so leave it for later. --- llvm/include/llvm/IR/RuntimeLibcalls.td | 140 +-- llvm/include/llvm/IR/RuntimeLibcallsImpl.td | 27 ++- llvm/lib/IR/RuntimeLibcalls.cpp | 141 --- .../RuntimeLibcallEmitter-calling-conv.td | 128 ++ llvm/test/TableGen/RuntimeLibcallEmitter.td | 19 +- .../TableGen/Basic/RuntimeLibcallsEmitter.cpp | 165 ++ 6 files changed, 429 insertions(+), 191 deletions(-) create mode 100644 llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.td b/llvm/include/llvm/IR/RuntimeLibcalls.td index 61031140e105e..59e9481201de4 100644 --- a/llvm/include/llvm/IR/RuntimeLibcalls.td +++ b/llvm/include/llvm/IR/RuntimeLibcalls.td @@ -1282,11 +1282,12 @@ def __gnu_h2f_ieee : RuntimeLibcallImpl; //===--===// // Several of the runtime library functions use a special calling conv -def __divmodqi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN -def __divmodhi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN +def __divmodqi4 : RuntimeLibcallImpl; +def __divmodhi4 : RuntimeLibcallImpl; +def __udivmodqi4 : RuntimeLibcallImpl; +def __udivmodhi4 : RuntimeLibcallImpl; + //def __divmodsi4 : RuntimeLibcallImpl; -def __udivmodqi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN -def __udivmodhi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN //def __udivmodsi4 : RuntimeLibcallImpl; // Standard sinf/cosf name replaced with "sin" and "cos". Define a @@ -1312,9 +1313,12 @@ def AVRSystemLibrary // Standard f64 names are replaced sin, cos, sinf, cosf), - __divmodqi4, __divmodhi4, __divmodsi4, __udivmodqi4, __udivmodhi4, - __udivmodsi4, - + // Several of the runtime library functions use a special calling + // conv + LibcallsWithCC<(add __divmodqi4, __divmodhi4, __udivmodqi4, + __udivmodhi4), + AVR_BUILTIN>, + __divmodsi4, __udivmodsi4, // Trigonometric rtlib functions avr_sin, avr_cos)>; @@ -1537,6 +1541,117 @@ def __mspabi_mpyll : RuntimeLibcallImpl; // setLibcallCallingConv(MUL_I64, CallingConv::MSP430_BUILTIN); +def isMSP430 : RuntimeLibcallPredicate<"TT.getArch() == Triple::msp430">; + +defvar MSP430DefaultOptOut = [ + __addsf3, __divsf3, __extendsfdf2, __truncdfsf2, __fixsfsi, + __fixsfdi, __fixunssfsi, __mulsf3, __eqsf2, __gesf2, __gtsf2, + __divhi3, __divsi3, __ashlsi3, __floatsidf, __floatsisf, + __ashrsi3, __modhi3, __udivsi3, __fixdfsi, __fixunssfdi, + __udivhi3, __umodsi3, __nesf2, __lesf2, __floatundisf, + __fixdfdi, __fixunsdfsi, __modsi3, __floatunsisf, + __fixunsdfdi, __ltsf2, __floatdisf, __floatdidf, + __lshrsi3, __subsf3, __umodhi3, __floatunsidf, + __floatundidf +]; + +// EABI Libcalls - EABI Section 6.2 +def MSP430SystemLibrary +: SystemRuntimeLibrary, + __mspabi_cmpf__oeq, + __mspabi_cmpf__une, + __mspabi_cmpf__oge, + __mspabi_cmpf__olt, + __mspabi_cmpf__ole, + __mspabi_cmpf__ogt, + + // Floating point arithmetic - EABI Table 8 + LibcallsWithCC<(add __mspabi_addd, + __mspabi_subd, + __mspabi_mpyd, + __mspabi_divd), MSP430_BUILTIN>, + + __mspabi_addf, + __mspabi_subf, + __mspabi_mpyf, + __mspabi_divf, + + // The following are NOT implemented in libgcc + // __mspabi_negd, + // __mspabi_negf, + + // Universal Integer Operations - EABI Table 9 + __mspabi_divi, + __mspabi_divli, + LibcallsWithCC<(add __mspabi_divlli), MSP430_BUILTIN>, + __mspabi_divu, + __mspabi_divul, + LibcallsWithCC<(add __mspabi_divull), MSP430_BUILTIN>, + __mspabi_remi, + __mspabi_remli, + LibcallsWithCC<(add __mspabi_remlli), MSP430_BUILTIN>, + __mspabi_remu, + __mspabi_remul, + LibcallsWithCC<(add __mspabi_remull), MSP430_BUILTIN>, + + // Bitwise Operations - EABI Table 10 + // TODO: __mspabi_[srli/srai/slli] ARE implemented in libgcc + __mspabi_srll, + __mspabi_sral, + __mspabi_slll + // __mspabi_[srlll/srall/s/rlli/rlll] are NOT implemented in libgcc + ) +>; + //===--===// // NVPTX Runtime Libcalls //===---
[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Handle ISD::PTRADD in various special cases (PR #145330)
@@ -615,8 +615,14 @@ bool TargetLowering::ShrinkDemandedOp(SDValue Op, unsigned
BitWidth,
// operands on the new node are also disjoint.
SDNodeFlags Flags(Op->getFlags().hasDisjoint() ? SDNodeFlags::Disjoint
: SDNodeFlags::None);
+ unsigned Opcode = Op.getOpcode();
+ if (Opcode == ISD::PTRADD) {
+// It isn't a ptradd anymore if it doesn't operate on the entire
+// pointer.
ritter-x2a wrote:
You could make a PTRADD here work mechanically for AMDGPU by adding support of
32-bit PTRADDs (which requires more DAGCombines and is not on the critical path
for me at the moment), but I'd still argue that this shouldn't be a PTRADD even
then. As I see it, the point of having the PTRADD node is being able to tell
that the left operand is an address, which it isn't if you chop off the leading
bits (unless the chopping is done to implement an address space cast).
https://github.com/llvm/llvm-project/pull/145330
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[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (PR #145912)
@@ -32,6 +32,7 @@ class RegBankLegalizeHelper {
const MachineUniformityInfo &MUI;
const RegisterBankInfo &RBI;
const RegBankLegalizeRules &RBLRules;
+ const bool IsWave32;
petar-avramovic wrote:
you mean this?
https://github.com/llvm/llvm-project/pull/145912
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[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (PR #145912)
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145912
>From 811ddee3f53fd10f72efa647629d2ab2e34d577b Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 26 Jun 2025 16:03:56 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize
Add rules for G_AMDGPU_BUFFER_LOAD and implement waterfall lowering
for divergent operands that must be sgpr.
---
.../Target/AMDGPU/AMDGPUGlobalISelUtils.cpp | 61 +++--
.../lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h | 2 +
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp| 239 +-
.../AMDGPU/AMDGPURegBankLegalizeHelper.h | 1 +
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 22 +-
.../AMDGPU/AMDGPURegBankLegalizeRules.h | 6 +-
.../AMDGPU/GlobalISel/buffer-schedule.ll | 2 +-
.../llvm.amdgcn.make.buffer.rsrc.ll | 2 +-
.../regbankselect-amdgcn.raw.buffer.load.ll | 59 ++---
...egbankselect-amdgcn.raw.ptr.buffer.load.ll | 59 ++---
...regbankselect-amdgcn.struct.buffer.load.ll | 59 ++---
...ankselect-amdgcn.struct.ptr.buffer.load.ll | 59 ++---
.../llvm.amdgcn.buffer.load-last-use.ll | 2 +-
.../llvm.amdgcn.raw.atomic.buffer.load.ll | 42 +--
.../llvm.amdgcn.raw.ptr.atomic.buffer.load.ll | 42 +--
.../llvm.amdgcn.struct.atomic.buffer.load.ll | 48 ++--
...vm.amdgcn.struct.ptr.atomic.buffer.load.ll | 48 ++--
.../CodeGen/AMDGPU/swizzle.bit.extract.ll | 4 +-
18 files changed, 514 insertions(+), 243 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
index 00979f44f9d34..f36935d8c0e8f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
@@ -117,45 +117,72 @@ static LLT getReadAnyLaneSplitTy(LLT Ty) {
return LLT::scalar(32);
}
-static Register buildReadAnyLane(MachineIRBuilder &B, Register VgprSrc,
- const RegisterBankInfo &RBI);
-
-static void unmergeReadAnyLane(MachineIRBuilder &B,
- SmallVectorImpl &SgprDstParts,
- LLT UnmergeTy, Register VgprSrc,
- const RegisterBankInfo &RBI) {
+template
+static Register buildReadLane(MachineIRBuilder &, Register,
+ const RegisterBankInfo &, ReadLaneFnTy);
+
+template
+static void
+unmergeReadAnyLane(MachineIRBuilder &B, SmallVectorImpl
&SgprDstParts,
+ LLT UnmergeTy, Register VgprSrc, const RegisterBankInfo
&RBI,
+ ReadLaneFnTy BuildRL) {
const RegisterBank *VgprRB = &RBI.getRegBank(AMDGPU::VGPRRegBankID);
auto Unmerge = B.buildUnmerge({VgprRB, UnmergeTy}, VgprSrc);
for (unsigned i = 0; i < Unmerge->getNumOperands() - 1; ++i) {
-SgprDstParts.push_back(buildReadAnyLane(B, Unmerge.getReg(i), RBI));
+SgprDstParts.push_back(buildReadLane(B, Unmerge.getReg(i), RBI, BuildRL));
}
}
-static Register buildReadAnyLane(MachineIRBuilder &B, Register VgprSrc,
- const RegisterBankInfo &RBI) {
+template
+static Register buildReadLane(MachineIRBuilder &B, Register VgprSrc,
+ const RegisterBankInfo &RBI,
+ ReadLaneFnTy BuildRL) {
LLT Ty = B.getMRI()->getType(VgprSrc);
const RegisterBank *SgprRB = &RBI.getRegBank(AMDGPU::SGPRRegBankID);
if (Ty.getSizeInBits() == 32) {
-return B.buildInstr(AMDGPU::G_AMDGPU_READANYLANE, {{SgprRB, Ty}},
{VgprSrc})
-.getReg(0);
+Register SgprDst = B.getMRI()->createVirtualRegister({SgprRB, Ty});
+return BuildRL(B, SgprDst, VgprSrc).getReg(0);
}
SmallVector SgprDstParts;
- unmergeReadAnyLane(B, SgprDstParts, getReadAnyLaneSplitTy(Ty), VgprSrc, RBI);
+ unmergeReadAnyLane(B, SgprDstParts, getReadAnyLaneSplitTy(Ty), VgprSrc, RBI,
+ BuildRL);
return B.buildMergeLikeInstr({SgprRB, Ty}, SgprDstParts).getReg(0);
}
-void AMDGPU::buildReadAnyLane(MachineIRBuilder &B, Register SgprDst,
- Register VgprSrc, const RegisterBankInfo &RBI) {
+template
+static void buildReadLane(MachineIRBuilder &B, Register SgprDst,
+ Register VgprSrc, const RegisterBankInfo &RBI,
+ ReadLaneFnTy BuildReadLane) {
LLT Ty = B.getMRI()->getType(VgprSrc);
if (Ty.getSizeInBits() == 32) {
-B.buildInstr(AMDGPU::G_AMDGPU_READANYLANE, {SgprDst}, {VgprSrc});
+BuildReadLane(B, SgprDst, VgprSrc);
return;
}
SmallVector SgprDstParts;
- unmergeReadAnyLane(B, SgprDstParts, getReadAnyLaneSplitTy(Ty), VgprSrc, RBI);
+ unmergeReadAnyLane(B, SgprDstParts, getReadAnyLaneSplitTy(Ty), VgprSrc, RBI,
+ BuildReadLane);
B.buildMergeLikeInstr(SgprDst, SgprDstParts).getReg(0);
}
+
+void AMDGPU::buildReadAnyLane(MachineIRBuilder &B, Register SgprDst,
+ Register VgprSrc
[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Handle ISD::PTRADD in various special cases (PR #145330)
@@ -2230,7 +2230,7 @@ bool AMDGPUDAGToDAGISel::SelectSMRDBaseOffset(SDValue
Addr, SDValue &SBase,
SDValue N0, N1;
// Extract the base and offset if possible.
- if (CurDAG->isBaseWithConstantOffset(Addr) || Addr.getOpcode() == ISD::ADD) {
+ if (CurDAG->isBaseWithConstantOffset(Addr) || Addr->isAnyAdd()) {
ritter-x2a wrote:
I think the code here isn't interested in the `Constant` part of
`isBaseWithConstantOffset`; that's checked in `SelectSMRDOffset`. It should be
fine (even better, in some hypothetical cases) to replace this call with an
`isADDLike` call (which catches disjoint ors and an xor special case whereas
`isAnyAdd` only checks for `ISD::ADD` or `ISD::PTRADD`). I'll try that and
update the PR.
Ultimately, it would probably be nice to select offsets for the different
addressing mode variants more consistently, but I don't see that in the scope
of this PR.
https://github.com/llvm/llvm-project/pull/145330
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[llvm-branch-commits] [llvm] AMDGPU: Introduce a pass to replace VGPR MFMAs with AGPR (PR #145024)
arsenm wrote: ### Merge activity * **Jun 27, 11:58 AM UTC**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/145024). https://github.com/llvm/llvm-project/pull/145024 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] 4dbe04a - Revert "[flang] add option to generate runtime type info as external (#145901)"
Author: jeanPerier
Date: 2025-06-27T14:04:51+02:00
New Revision: 4dbe04a551fe7ab7668a0351ef39cf8bbfe13798
URL:
https://github.com/llvm/llvm-project/commit/4dbe04a551fe7ab7668a0351ef39cf8bbfe13798
DIFF:
https://github.com/llvm/llvm-project/commit/4dbe04a551fe7ab7668a0351ef39cf8bbfe13798.diff
LOG: Revert "[flang] add option to generate runtime type info as external
(#145901)"
This reverts commit e816817bbb2889a42d8d984736971635d77816f3.
Added:
Modified:
flang/include/flang/Evaluate/tools.h
flang/include/flang/Optimizer/CodeGen/CodeGen.h
flang/include/flang/Optimizer/Passes/CommandLineOpts.h
flang/include/flang/Optimizer/Support/Utils.h
flang/include/flang/Semantics/runtime-type-info.h
flang/lib/Evaluate/tools.cpp
flang/lib/Lower/Bridge.cpp
flang/lib/Lower/ConvertVariable.cpp
flang/lib/Optimizer/CodeGen/CodeGen.cpp
flang/lib/Optimizer/Passes/CommandLineOpts.cpp
flang/lib/Optimizer/Passes/Pipelines.cpp
flang/lib/Optimizer/Transforms/PolymorphicOpConversion.cpp
flang/test/Lower/select-type-2.f90
flang/test/Lower/select-type.f90
Removed:
flang/test/Integration/skip-external-rtti-definition.F90
diff --git a/flang/include/flang/Evaluate/tools.h
b/flang/include/flang/Evaluate/tools.h
index cad1b634f8924..d26a477ddded1 100644
--- a/flang/include/flang/Evaluate/tools.h
+++ b/flang/include/flang/Evaluate/tools.h
@@ -1585,7 +1585,6 @@ bool IsExtensibleType(const DerivedTypeSpec *);
bool IsSequenceOrBindCType(const DerivedTypeSpec *);
bool IsBuiltinDerivedType(const DerivedTypeSpec *derived, const char *name);
bool IsBuiltinCPtr(const Symbol &);
-bool IsFromBuiltinModule(const Symbol &);
bool IsEventType(const DerivedTypeSpec *);
bool IsLockType(const DerivedTypeSpec *);
bool IsNotifyType(const DerivedTypeSpec *);
diff --git a/flang/include/flang/Optimizer/CodeGen/CodeGen.h
b/flang/include/flang/Optimizer/CodeGen/CodeGen.h
index 93f07d8d5d4d9..0398d0f248e08 100644
--- a/flang/include/flang/Optimizer/CodeGen/CodeGen.h
+++ b/flang/include/flang/Optimizer/CodeGen/CodeGen.h
@@ -39,9 +39,6 @@ struct FIRToLLVMPassOptions {
// that such programs would crash at runtime if the derived type descriptors
// are required by the runtime, so this is only an option to help debugging.
bool ignoreMissingTypeDescriptors = false;
- // Similar to ignoreMissingTypeDescriptors, but generate external declaration
- // for the missing type descriptor globals instead.
- bool skipExternalRttiDefinition = false;
// Generate TBAA information for FIR types and memory accessing operations.
bool applyTBAA = false;
diff --git a/flang/include/flang/Optimizer/Passes/CommandLineOpts.h
b/flang/include/flang/Optimizer/Passes/CommandLineOpts.h
index 76ac9d0622d2b..1cfaf285e75e6 100644
--- a/flang/include/flang/Optimizer/Passes/CommandLineOpts.h
+++ b/flang/include/flang/Optimizer/Passes/CommandLineOpts.h
@@ -32,19 +32,6 @@ extern llvm::cl::opt
arrayStackAllocationThreshold;
/// generated by the frontend.
extern llvm::cl::opt ignoreMissingTypeDescriptors;
-/// Shared option in tools to only generate rtti static object definitions for
-/// derived types defined in the current compilation unit. Derived type
-/// descriptor object for types defined in other objects will only be declared
-/// as external. This also changes the linkage of rtti objects defined in the
-/// current compilation unit from linkonce_odr to external so that unused rtti
-/// objects are retained and can be accessed from other compilation units. This
-/// is an experimental option to explore compilation speed improvements and is
-/// an ABI breaking change because of the linkage change.
-/// It will also require linking against module file objects of modules
defining
-/// only types (even for trivial types without type bound procedures, which
-///
diff ers from most compilers).
-extern llvm::cl::opt skipExternalRttiDefinition;
-
/// Default optimization level used to create Flang pass pipeline is O0.
extern llvm::OptimizationLevel defaultOptLevel;
diff --git a/flang/include/flang/Optimizer/Support/Utils.h
b/flang/include/flang/Optimizer/Support/Utils.h
index 83c936b7dcada..ec73af6ec72e9 100644
--- a/flang/include/flang/Optimizer/Support/Utils.h
+++ b/flang/include/flang/Optimizer/Support/Utils.h
@@ -35,6 +35,32 @@ inline std::int64_t toInt(mlir::arith::ConstantOp cop) {
.getSExtValue();
}
+// Reconstruct binding tables for dynamic dispatch.
+using BindingTable = llvm::DenseMap;
+using BindingTables = llvm::DenseMap;
+
+inline void buildBindingTables(BindingTables &bindingTables,
+ mlir::ModuleOp mod) {
+
+ // The binding tables are defined in FIR after lowering inside fir.type_info
+ // operations. Go through each binding tables and store the procedure name
and
+ // binding index for later use by the fir.dispatch conversion pattern.
+ for (au
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (PR #145912)
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145912
>From 9cebe6bb5d44a630235a8cce4233e53f68f7bd0c Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 26 Jun 2025 16:03:56 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize
Add rules for G_AMDGPU_BUFFER_LOAD and implement waterfall lowering
for divergent operands that must be sgpr.
---
.../Target/AMDGPU/AMDGPUGlobalISelUtils.cpp | 61 +++--
.../lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h | 2 +
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp| 239 +-
.../AMDGPU/AMDGPURegBankLegalizeHelper.h | 1 +
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 22 +-
.../AMDGPU/AMDGPURegBankLegalizeRules.h | 6 +-
.../AMDGPU/GlobalISel/buffer-schedule.ll | 2 +-
.../llvm.amdgcn.make.buffer.rsrc.ll | 2 +-
.../regbankselect-amdgcn.raw.buffer.load.ll | 59 ++---
...egbankselect-amdgcn.raw.ptr.buffer.load.ll | 59 ++---
...regbankselect-amdgcn.struct.buffer.load.ll | 59 ++---
...ankselect-amdgcn.struct.ptr.buffer.load.ll | 59 ++---
.../llvm.amdgcn.buffer.load-last-use.ll | 2 +-
.../llvm.amdgcn.raw.atomic.buffer.load.ll | 42 +--
.../llvm.amdgcn.raw.ptr.atomic.buffer.load.ll | 42 +--
.../llvm.amdgcn.struct.atomic.buffer.load.ll | 48 ++--
...vm.amdgcn.struct.ptr.atomic.buffer.load.ll | 48 ++--
.../CodeGen/AMDGPU/swizzle.bit.extract.ll | 4 +-
18 files changed, 514 insertions(+), 243 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
index 00979f44f9d34..f36935d8c0e8f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
@@ -117,45 +117,72 @@ static LLT getReadAnyLaneSplitTy(LLT Ty) {
return LLT::scalar(32);
}
-static Register buildReadAnyLane(MachineIRBuilder &B, Register VgprSrc,
- const RegisterBankInfo &RBI);
-
-static void unmergeReadAnyLane(MachineIRBuilder &B,
- SmallVectorImpl &SgprDstParts,
- LLT UnmergeTy, Register VgprSrc,
- const RegisterBankInfo &RBI) {
+template
+static Register buildReadLane(MachineIRBuilder &, Register,
+ const RegisterBankInfo &, ReadLaneFnTy);
+
+template
+static void
+unmergeReadAnyLane(MachineIRBuilder &B, SmallVectorImpl
&SgprDstParts,
+ LLT UnmergeTy, Register VgprSrc, const RegisterBankInfo
&RBI,
+ ReadLaneFnTy BuildRL) {
const RegisterBank *VgprRB = &RBI.getRegBank(AMDGPU::VGPRRegBankID);
auto Unmerge = B.buildUnmerge({VgprRB, UnmergeTy}, VgprSrc);
for (unsigned i = 0; i < Unmerge->getNumOperands() - 1; ++i) {
-SgprDstParts.push_back(buildReadAnyLane(B, Unmerge.getReg(i), RBI));
+SgprDstParts.push_back(buildReadLane(B, Unmerge.getReg(i), RBI, BuildRL));
}
}
-static Register buildReadAnyLane(MachineIRBuilder &B, Register VgprSrc,
- const RegisterBankInfo &RBI) {
+template
+static Register buildReadLane(MachineIRBuilder &B, Register VgprSrc,
+ const RegisterBankInfo &RBI,
+ ReadLaneFnTy BuildRL) {
LLT Ty = B.getMRI()->getType(VgprSrc);
const RegisterBank *SgprRB = &RBI.getRegBank(AMDGPU::SGPRRegBankID);
if (Ty.getSizeInBits() == 32) {
-return B.buildInstr(AMDGPU::G_AMDGPU_READANYLANE, {{SgprRB, Ty}},
{VgprSrc})
-.getReg(0);
+Register SgprDst = B.getMRI()->createVirtualRegister({SgprRB, Ty});
+return BuildRL(B, SgprDst, VgprSrc).getReg(0);
}
SmallVector SgprDstParts;
- unmergeReadAnyLane(B, SgprDstParts, getReadAnyLaneSplitTy(Ty), VgprSrc, RBI);
+ unmergeReadAnyLane(B, SgprDstParts, getReadAnyLaneSplitTy(Ty), VgprSrc, RBI,
+ BuildRL);
return B.buildMergeLikeInstr({SgprRB, Ty}, SgprDstParts).getReg(0);
}
-void AMDGPU::buildReadAnyLane(MachineIRBuilder &B, Register SgprDst,
- Register VgprSrc, const RegisterBankInfo &RBI) {
+template
+static void buildReadLane(MachineIRBuilder &B, Register SgprDst,
+ Register VgprSrc, const RegisterBankInfo &RBI,
+ ReadLaneFnTy BuildReadLane) {
LLT Ty = B.getMRI()->getType(VgprSrc);
if (Ty.getSizeInBits() == 32) {
-B.buildInstr(AMDGPU::G_AMDGPU_READANYLANE, {SgprDst}, {VgprSrc});
+BuildReadLane(B, SgprDst, VgprSrc);
return;
}
SmallVector SgprDstParts;
- unmergeReadAnyLane(B, SgprDstParts, getReadAnyLaneSplitTy(Ty), VgprSrc, RBI);
+ unmergeReadAnyLane(B, SgprDstParts, getReadAnyLaneSplitTy(Ty), VgprSrc, RBI,
+ BuildReadLane);
B.buildMergeLikeInstr(SgprDst, SgprDstParts).getReg(0);
}
+
+void AMDGPU::buildReadAnyLane(MachineIRBuilder &B, Register SgprDst,
+ Register VgprSrc
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Add tests for missing readanylane combines (PR #145910)
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145910
>From 7f9708fb95ab169e1c449dbfccbcbdd049518c9e Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 4 Jun 2025 17:11:48 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add tests for missing readanylane combines
---
.../AMDGPU/GlobalISel/readanylane-combines.ll | 166
.../GlobalISel/readanylane-combines.mir | 393 ++
2 files changed, 559 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.ll
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.ll
b/llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.ll
new file mode 100644
index 0..51b473f2d8994
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.ll
@@ -0,0 +1,166 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010
-new-reg-bank-select < %s | FileCheck %s
+
+define amdgpu_ps void @readanylane_to_virtual_vgpr(ptr addrspace(1) inreg
%ptr0, ptr addrspace(1) inreg %ptr1) {
+; CHECK-LABEL: readanylane_to_virtual_vgpr:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:v_mov_b32_e32 v0, 0
+; CHECK-NEXT:global_load_dword v1, v0, s[0:1] glc dlc
+; CHECK-NEXT:s_waitcnt vmcnt(0)
+; CHECK-NEXT:global_store_dword v0, v1, s[2:3]
+; CHECK-NEXT:s_endpgm
+ %load = load volatile float, ptr addrspace(1) %ptr0
+ store float %load, ptr addrspace(1) %ptr1
+ ret void
+}
+
+define amdgpu_ps float @readanylane_to_physical_vgpr(ptr addrspace(1) inreg
%ptr) {
+; CHECK-LABEL: readanylane_to_physical_vgpr:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:v_mov_b32_e32 v0, 0
+; CHECK-NEXT:global_load_dword v0, v0, s[0:1] glc dlc
+; CHECK-NEXT:s_waitcnt vmcnt(0)
+; CHECK-NEXT:v_readfirstlane_b32 s0, v0
+; CHECK-NEXT:v_mov_b32_e32 v0, s0
+; CHECK-NEXT:; return to shader part epilog
+ %load = load volatile float, ptr addrspace(1) %ptr
+ ret float %load
+}
+
+define amdgpu_ps void @readanylane_to_bitcast_to_virtual_vgpr(ptr addrspace(1)
inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
+; CHECK-LABEL: readanylane_to_bitcast_to_virtual_vgpr:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:v_mov_b32_e32 v0, 0
+; CHECK-NEXT:global_load_dword v1, v0, s[0:1] glc dlc
+; CHECK-NEXT:s_waitcnt vmcnt(0)
+; CHECK-NEXT:v_readfirstlane_b32 s0, v1
+; CHECK-NEXT:v_mov_b32_e32 v1, s0
+; CHECK-NEXT:global_store_dword v0, v1, s[2:3]
+; CHECK-NEXT:s_endpgm
+ %load = load volatile <2 x i16>, ptr addrspace(1) %ptr0
+ %bitcast = bitcast <2 x i16> %load to i32
+ store i32 %bitcast, ptr addrspace(1) %ptr1
+ ret void
+}
+
+define amdgpu_ps float @readanylane_to_bitcast_to_physical_vgpr(ptr
addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
+; CHECK-LABEL: readanylane_to_bitcast_to_physical_vgpr:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:v_mov_b32_e32 v0, 0
+; CHECK-NEXT:global_load_dword v0, v0, s[0:1] glc dlc
+; CHECK-NEXT:s_waitcnt vmcnt(0)
+; CHECK-NEXT:v_readfirstlane_b32 s0, v0
+; CHECK-NEXT:v_mov_b32_e32 v0, s0
+; CHECK-NEXT:; return to shader part epilog
+ %load = load volatile <2 x i16>, ptr addrspace(1) %ptr0
+ %bitcast = bitcast <2 x i16> %load to float
+ ret float %bitcast
+}
+
+define amdgpu_ps void @unmerge_readanylane_merge_to_virtual_vgpr(ptr
addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
+; CHECK-LABEL: unmerge_readanylane_merge_to_virtual_vgpr:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:v_mov_b32_e32 v2, 0
+; CHECK-NEXT:global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc
+; CHECK-NEXT:s_waitcnt vmcnt(0)
+; CHECK-NEXT:v_readfirstlane_b32 s0, v0
+; CHECK-NEXT:v_readfirstlane_b32 s1, v1
+; CHECK-NEXT:v_mov_b32_e32 v0, s0
+; CHECK-NEXT:v_mov_b32_e32 v1, s1
+; CHECK-NEXT:global_store_dwordx2 v2, v[0:1], s[2:3]
+; CHECK-NEXT:s_endpgm
+ %load = load volatile i64, ptr addrspace(1) %ptr0
+ store i64 %load, ptr addrspace(1) %ptr1
+ ret void
+}
+
+;define amdgpu_ps double @unmerge_readanylane_merge_to_physical_vgpr(ptr
addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
+; %load = load volatile double, ptr addrspace(1) %ptr0
+; ret double %load
+;}
+
+define amdgpu_ps void @unmerge_readanylane_merge_bitcast_to_virtual_vgpr(ptr
addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
+; CHECK-LABEL: unmerge_readanylane_merge_bitcast_to_virtual_vgpr:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:v_mov_b32_e32 v2, 0
+; CHECK-NEXT:global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc
+; CHECK-NEXT:s_waitcnt vmcnt(0)
+; CHECK-NEXT:v_readfirstlane_b32 s0, v0
+; CHECK-NEXT:v_readfirstlane_b32 s1, v1
+; CHECK-NEXT:v_mov_b32_e32 v0, s0
+; CHECK-NEXT:v_mov_b32_e32 v1, s1
+; CHECK-NEXT:global_store_dwordx2 v2, v[0:1], s[2:3]
+; CHECK-NEXT:s_endpg
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Improve readanylane combines in regbanklegalize (PR #145911)
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145911
>From 871140020cf7f3fc5f7fe4cbb657d754ed8ecc2f Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines in
regbanklegalize
---
.../Target/AMDGPU/AMDGPURegBankLegalize.cpp | 317 --
.../AMDGPU/GlobalISel/readanylane-combines.ll | 25 +-
.../GlobalISel/readanylane-combines.mir | 78 ++---
.../GlobalISel/regbankselect-and-s1.mir | 6 +
.../GlobalISel/regbankselect-anyext.mir | 4 +
.../AMDGPU/GlobalISel/regbankselect-trunc.mir | 2 +
6 files changed, 246 insertions(+), 186 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
index ba661348ca5b5..733b5d0865d7c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
@@ -23,6 +23,8 @@
#include "GCNSubtarget.h"
#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
#include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h"
+#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
+#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineUniformityAnalysis.h"
#include "llvm/CodeGen/TargetPassConfig.h"
@@ -115,126 +117,233 @@ class AMDGPURegBankLegalizeCombiner {
VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)),
VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {};
- bool isLaneMask(Register Reg) {
-const RegisterBank *RB = MRI.getRegBankOrNull(Reg);
-if (RB && RB->getID() == AMDGPU::VCCRegBankID)
- return true;
+ bool isLaneMask(Register Reg);
+ std::pair tryMatch(Register Src, unsigned Opcode);
+ std::pair tryMatchRALFromUnmerge(Register Src);
+ Register getReadAnyLaneSrc(Register Src);
+ void replaceRegWithOrBuildCopy(Register Dst, Register Src);
-const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
-return RC && TRI.isSGPRClass(RC) && MRI.getType(Reg) == LLT::scalar(1);
- }
+ bool tryEliminateReadAnyLane(MachineInstr &Copy);
+ void tryCombineCopy(MachineInstr &MI);
+ void tryCombineS1AnyExt(MachineInstr &MI);
+};
- void cleanUpAfterCombine(MachineInstr &MI, MachineInstr *Optional0) {
-MI.eraseFromParent();
-if (Optional0 && isTriviallyDead(*Optional0, MRI))
- Optional0->eraseFromParent();
- }
+bool AMDGPURegBankLegalizeCombiner::isLaneMask(Register Reg) {
+ const RegisterBank *RB = MRI.getRegBankOrNull(Reg);
+ if (RB && RB->getID() == AMDGPU::VCCRegBankID)
+return true;
- std::pair tryMatch(Register Src, unsigned Opcode) {
-MachineInstr *MatchMI = MRI.getVRegDef(Src);
-if (MatchMI->getOpcode() != Opcode)
- return {nullptr, Register()};
-return {MatchMI, MatchMI->getOperand(1).getReg()};
- }
+ const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
+ return RC && TRI.isSGPRClass(RC) && MRI.getType(Reg) == LLT::scalar(1);
+}
- void tryCombineCopy(MachineInstr &MI) {
-Register Dst = MI.getOperand(0).getReg();
-Register Src = MI.getOperand(1).getReg();
-// Skip copies of physical registers.
-if (!Dst.isVirtual() || !Src.isVirtual())
- return;
-
-// This is a cross bank copy, sgpr S1 to lane mask.
-//
-// %Src:sgpr(s1) = G_TRUNC %TruncS32Src:sgpr(s32)
-// %Dst:lane-mask(s1) = COPY %Src:sgpr(s1)
-// ->
-// %Dst:lane-mask(s1) = G_AMDGPU_COPY_VCC_SCC %TruncS32Src:sgpr(s32)
-if (isLaneMask(Dst) && MRI.getRegBankOrNull(Src) == SgprRB) {
- auto [Trunc, TruncS32Src] = tryMatch(Src, AMDGPU::G_TRUNC);
- assert(Trunc && MRI.getType(TruncS32Src) == S32 &&
- "sgpr S1 must be result of G_TRUNC of sgpr S32");
-
- B.setInstr(MI);
- // Ensure that truncated bits in BoolSrc are 0.
- auto One = B.buildConstant({SgprRB, S32}, 1);
- auto BoolSrc = B.buildAnd({SgprRB, S32}, TruncS32Src, One);
- B.buildInstr(AMDGPU::G_AMDGPU_COPY_VCC_SCC, {Dst}, {BoolSrc});
- cleanUpAfterCombine(MI, Trunc);
- return;
-}
+std::pair
+AMDGPURegBankLegalizeCombiner::tryMatch(Register Src, unsigned Opcode) {
+ MachineInstr *MatchMI = MRI.getVRegDef(Src);
+ if (MatchMI->getOpcode() != Opcode)
+return {nullptr, Register()};
+ return {MatchMI, MatchMI->getOperand(1).getReg()};
+}
+
+std::pair
+AMDGPURegBankLegalizeCombiner::tryMatchRALFromUnmerge(Register Src) {
+ MachineInstr *ReadAnyLane = MRI.getVRegDef(Src);
+ if (ReadAnyLane->getOpcode() != AMDGPU::G_AMDGPU_READANYLANE)
+return {nullptr, -1};
+
+ Register RALSrc = ReadAnyLane->getOperand(1).getReg();
+ if (auto *UnMerge = getOpcodeDef(RALSrc, MRI))
+return {UnMerge, UnMerge->findRegisterDefOperandIdx(RALSrc, nullptr)};
-// Src = G_AMDGPU_READANYLANE RALSrc
-// Dst = COPY Src
-// ->
-// Dst = RALSrc
-if (MRI.getRegBankOrNull(Dst) == VgprRB &&
-MRI.getRegBankOrNull(Src) == SgprRB) {
-
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Improve readanylane combines in regbanklegalize (PR #145911)
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145911
>From 871140020cf7f3fc5f7fe4cbb657d754ed8ecc2f Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines in
regbanklegalize
---
.../Target/AMDGPU/AMDGPURegBankLegalize.cpp | 317 --
.../AMDGPU/GlobalISel/readanylane-combines.ll | 25 +-
.../GlobalISel/readanylane-combines.mir | 78 ++---
.../GlobalISel/regbankselect-and-s1.mir | 6 +
.../GlobalISel/regbankselect-anyext.mir | 4 +
.../AMDGPU/GlobalISel/regbankselect-trunc.mir | 2 +
6 files changed, 246 insertions(+), 186 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
index ba661348ca5b5..733b5d0865d7c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
@@ -23,6 +23,8 @@
#include "GCNSubtarget.h"
#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
#include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h"
+#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
+#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineUniformityAnalysis.h"
#include "llvm/CodeGen/TargetPassConfig.h"
@@ -115,126 +117,233 @@ class AMDGPURegBankLegalizeCombiner {
VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)),
VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {};
- bool isLaneMask(Register Reg) {
-const RegisterBank *RB = MRI.getRegBankOrNull(Reg);
-if (RB && RB->getID() == AMDGPU::VCCRegBankID)
- return true;
+ bool isLaneMask(Register Reg);
+ std::pair tryMatch(Register Src, unsigned Opcode);
+ std::pair tryMatchRALFromUnmerge(Register Src);
+ Register getReadAnyLaneSrc(Register Src);
+ void replaceRegWithOrBuildCopy(Register Dst, Register Src);
-const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
-return RC && TRI.isSGPRClass(RC) && MRI.getType(Reg) == LLT::scalar(1);
- }
+ bool tryEliminateReadAnyLane(MachineInstr &Copy);
+ void tryCombineCopy(MachineInstr &MI);
+ void tryCombineS1AnyExt(MachineInstr &MI);
+};
- void cleanUpAfterCombine(MachineInstr &MI, MachineInstr *Optional0) {
-MI.eraseFromParent();
-if (Optional0 && isTriviallyDead(*Optional0, MRI))
- Optional0->eraseFromParent();
- }
+bool AMDGPURegBankLegalizeCombiner::isLaneMask(Register Reg) {
+ const RegisterBank *RB = MRI.getRegBankOrNull(Reg);
+ if (RB && RB->getID() == AMDGPU::VCCRegBankID)
+return true;
- std::pair tryMatch(Register Src, unsigned Opcode) {
-MachineInstr *MatchMI = MRI.getVRegDef(Src);
-if (MatchMI->getOpcode() != Opcode)
- return {nullptr, Register()};
-return {MatchMI, MatchMI->getOperand(1).getReg()};
- }
+ const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
+ return RC && TRI.isSGPRClass(RC) && MRI.getType(Reg) == LLT::scalar(1);
+}
- void tryCombineCopy(MachineInstr &MI) {
-Register Dst = MI.getOperand(0).getReg();
-Register Src = MI.getOperand(1).getReg();
-// Skip copies of physical registers.
-if (!Dst.isVirtual() || !Src.isVirtual())
- return;
-
-// This is a cross bank copy, sgpr S1 to lane mask.
-//
-// %Src:sgpr(s1) = G_TRUNC %TruncS32Src:sgpr(s32)
-// %Dst:lane-mask(s1) = COPY %Src:sgpr(s1)
-// ->
-// %Dst:lane-mask(s1) = G_AMDGPU_COPY_VCC_SCC %TruncS32Src:sgpr(s32)
-if (isLaneMask(Dst) && MRI.getRegBankOrNull(Src) == SgprRB) {
- auto [Trunc, TruncS32Src] = tryMatch(Src, AMDGPU::G_TRUNC);
- assert(Trunc && MRI.getType(TruncS32Src) == S32 &&
- "sgpr S1 must be result of G_TRUNC of sgpr S32");
-
- B.setInstr(MI);
- // Ensure that truncated bits in BoolSrc are 0.
- auto One = B.buildConstant({SgprRB, S32}, 1);
- auto BoolSrc = B.buildAnd({SgprRB, S32}, TruncS32Src, One);
- B.buildInstr(AMDGPU::G_AMDGPU_COPY_VCC_SCC, {Dst}, {BoolSrc});
- cleanUpAfterCombine(MI, Trunc);
- return;
-}
+std::pair
+AMDGPURegBankLegalizeCombiner::tryMatch(Register Src, unsigned Opcode) {
+ MachineInstr *MatchMI = MRI.getVRegDef(Src);
+ if (MatchMI->getOpcode() != Opcode)
+return {nullptr, Register()};
+ return {MatchMI, MatchMI->getOperand(1).getReg()};
+}
+
+std::pair
+AMDGPURegBankLegalizeCombiner::tryMatchRALFromUnmerge(Register Src) {
+ MachineInstr *ReadAnyLane = MRI.getVRegDef(Src);
+ if (ReadAnyLane->getOpcode() != AMDGPU::G_AMDGPU_READANYLANE)
+return {nullptr, -1};
+
+ Register RALSrc = ReadAnyLane->getOperand(1).getReg();
+ if (auto *UnMerge = getOpcodeDef(RALSrc, MRI))
+return {UnMerge, UnMerge->findRegisterDefOperandIdx(RALSrc, nullptr)};
-// Src = G_AMDGPU_READANYLANE RALSrc
-// Dst = COPY Src
-// ->
-// Dst = RALSrc
-if (MRI.getRegBankOrNull(Dst) == VgprRB &&
-MRI.getRegBankOrNull(Src) == SgprRB) {
-
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Add tests for missing readanylane combines (PR #145910)
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145910
>From 7f9708fb95ab169e1c449dbfccbcbdd049518c9e Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 4 Jun 2025 17:11:48 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add tests for missing readanylane combines
---
.../AMDGPU/GlobalISel/readanylane-combines.ll | 166
.../GlobalISel/readanylane-combines.mir | 393 ++
2 files changed, 559 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.ll
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.ll
b/llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.ll
new file mode 100644
index 0..51b473f2d8994
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.ll
@@ -0,0 +1,166 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010
-new-reg-bank-select < %s | FileCheck %s
+
+define amdgpu_ps void @readanylane_to_virtual_vgpr(ptr addrspace(1) inreg
%ptr0, ptr addrspace(1) inreg %ptr1) {
+; CHECK-LABEL: readanylane_to_virtual_vgpr:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:v_mov_b32_e32 v0, 0
+; CHECK-NEXT:global_load_dword v1, v0, s[0:1] glc dlc
+; CHECK-NEXT:s_waitcnt vmcnt(0)
+; CHECK-NEXT:global_store_dword v0, v1, s[2:3]
+; CHECK-NEXT:s_endpgm
+ %load = load volatile float, ptr addrspace(1) %ptr0
+ store float %load, ptr addrspace(1) %ptr1
+ ret void
+}
+
+define amdgpu_ps float @readanylane_to_physical_vgpr(ptr addrspace(1) inreg
%ptr) {
+; CHECK-LABEL: readanylane_to_physical_vgpr:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:v_mov_b32_e32 v0, 0
+; CHECK-NEXT:global_load_dword v0, v0, s[0:1] glc dlc
+; CHECK-NEXT:s_waitcnt vmcnt(0)
+; CHECK-NEXT:v_readfirstlane_b32 s0, v0
+; CHECK-NEXT:v_mov_b32_e32 v0, s0
+; CHECK-NEXT:; return to shader part epilog
+ %load = load volatile float, ptr addrspace(1) %ptr
+ ret float %load
+}
+
+define amdgpu_ps void @readanylane_to_bitcast_to_virtual_vgpr(ptr addrspace(1)
inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
+; CHECK-LABEL: readanylane_to_bitcast_to_virtual_vgpr:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:v_mov_b32_e32 v0, 0
+; CHECK-NEXT:global_load_dword v1, v0, s[0:1] glc dlc
+; CHECK-NEXT:s_waitcnt vmcnt(0)
+; CHECK-NEXT:v_readfirstlane_b32 s0, v1
+; CHECK-NEXT:v_mov_b32_e32 v1, s0
+; CHECK-NEXT:global_store_dword v0, v1, s[2:3]
+; CHECK-NEXT:s_endpgm
+ %load = load volatile <2 x i16>, ptr addrspace(1) %ptr0
+ %bitcast = bitcast <2 x i16> %load to i32
+ store i32 %bitcast, ptr addrspace(1) %ptr1
+ ret void
+}
+
+define amdgpu_ps float @readanylane_to_bitcast_to_physical_vgpr(ptr
addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
+; CHECK-LABEL: readanylane_to_bitcast_to_physical_vgpr:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:v_mov_b32_e32 v0, 0
+; CHECK-NEXT:global_load_dword v0, v0, s[0:1] glc dlc
+; CHECK-NEXT:s_waitcnt vmcnt(0)
+; CHECK-NEXT:v_readfirstlane_b32 s0, v0
+; CHECK-NEXT:v_mov_b32_e32 v0, s0
+; CHECK-NEXT:; return to shader part epilog
+ %load = load volatile <2 x i16>, ptr addrspace(1) %ptr0
+ %bitcast = bitcast <2 x i16> %load to float
+ ret float %bitcast
+}
+
+define amdgpu_ps void @unmerge_readanylane_merge_to_virtual_vgpr(ptr
addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
+; CHECK-LABEL: unmerge_readanylane_merge_to_virtual_vgpr:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:v_mov_b32_e32 v2, 0
+; CHECK-NEXT:global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc
+; CHECK-NEXT:s_waitcnt vmcnt(0)
+; CHECK-NEXT:v_readfirstlane_b32 s0, v0
+; CHECK-NEXT:v_readfirstlane_b32 s1, v1
+; CHECK-NEXT:v_mov_b32_e32 v0, s0
+; CHECK-NEXT:v_mov_b32_e32 v1, s1
+; CHECK-NEXT:global_store_dwordx2 v2, v[0:1], s[2:3]
+; CHECK-NEXT:s_endpgm
+ %load = load volatile i64, ptr addrspace(1) %ptr0
+ store i64 %load, ptr addrspace(1) %ptr1
+ ret void
+}
+
+;define amdgpu_ps double @unmerge_readanylane_merge_to_physical_vgpr(ptr
addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
+; %load = load volatile double, ptr addrspace(1) %ptr0
+; ret double %load
+;}
+
+define amdgpu_ps void @unmerge_readanylane_merge_bitcast_to_virtual_vgpr(ptr
addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
+; CHECK-LABEL: unmerge_readanylane_merge_bitcast_to_virtual_vgpr:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:v_mov_b32_e32 v2, 0
+; CHECK-NEXT:global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc
+; CHECK-NEXT:s_waitcnt vmcnt(0)
+; CHECK-NEXT:v_readfirstlane_b32 s0, v0
+; CHECK-NEXT:v_readfirstlane_b32 s1, v1
+; CHECK-NEXT:v_mov_b32_e32 v0, s0
+; CHECK-NEXT:v_mov_b32_e32 v1, s1
+; CHECK-NEXT:global_store_dwordx2 v2, v[0:1], s[2:3]
+; CHECK-NEXT:s_endpg
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (PR #145912)
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145912
>From 9cebe6bb5d44a630235a8cce4233e53f68f7bd0c Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 26 Jun 2025 16:03:56 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize
Add rules for G_AMDGPU_BUFFER_LOAD and implement waterfall lowering
for divergent operands that must be sgpr.
---
.../Target/AMDGPU/AMDGPUGlobalISelUtils.cpp | 61 +++--
.../lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h | 2 +
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp| 239 +-
.../AMDGPU/AMDGPURegBankLegalizeHelper.h | 1 +
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 22 +-
.../AMDGPU/AMDGPURegBankLegalizeRules.h | 6 +-
.../AMDGPU/GlobalISel/buffer-schedule.ll | 2 +-
.../llvm.amdgcn.make.buffer.rsrc.ll | 2 +-
.../regbankselect-amdgcn.raw.buffer.load.ll | 59 ++---
...egbankselect-amdgcn.raw.ptr.buffer.load.ll | 59 ++---
...regbankselect-amdgcn.struct.buffer.load.ll | 59 ++---
...ankselect-amdgcn.struct.ptr.buffer.load.ll | 59 ++---
.../llvm.amdgcn.buffer.load-last-use.ll | 2 +-
.../llvm.amdgcn.raw.atomic.buffer.load.ll | 42 +--
.../llvm.amdgcn.raw.ptr.atomic.buffer.load.ll | 42 +--
.../llvm.amdgcn.struct.atomic.buffer.load.ll | 48 ++--
...vm.amdgcn.struct.ptr.atomic.buffer.load.ll | 48 ++--
.../CodeGen/AMDGPU/swizzle.bit.extract.ll | 4 +-
18 files changed, 514 insertions(+), 243 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
index 00979f44f9d34..f36935d8c0e8f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
@@ -117,45 +117,72 @@ static LLT getReadAnyLaneSplitTy(LLT Ty) {
return LLT::scalar(32);
}
-static Register buildReadAnyLane(MachineIRBuilder &B, Register VgprSrc,
- const RegisterBankInfo &RBI);
-
-static void unmergeReadAnyLane(MachineIRBuilder &B,
- SmallVectorImpl &SgprDstParts,
- LLT UnmergeTy, Register VgprSrc,
- const RegisterBankInfo &RBI) {
+template
+static Register buildReadLane(MachineIRBuilder &, Register,
+ const RegisterBankInfo &, ReadLaneFnTy);
+
+template
+static void
+unmergeReadAnyLane(MachineIRBuilder &B, SmallVectorImpl
&SgprDstParts,
+ LLT UnmergeTy, Register VgprSrc, const RegisterBankInfo
&RBI,
+ ReadLaneFnTy BuildRL) {
const RegisterBank *VgprRB = &RBI.getRegBank(AMDGPU::VGPRRegBankID);
auto Unmerge = B.buildUnmerge({VgprRB, UnmergeTy}, VgprSrc);
for (unsigned i = 0; i < Unmerge->getNumOperands() - 1; ++i) {
-SgprDstParts.push_back(buildReadAnyLane(B, Unmerge.getReg(i), RBI));
+SgprDstParts.push_back(buildReadLane(B, Unmerge.getReg(i), RBI, BuildRL));
}
}
-static Register buildReadAnyLane(MachineIRBuilder &B, Register VgprSrc,
- const RegisterBankInfo &RBI) {
+template
+static Register buildReadLane(MachineIRBuilder &B, Register VgprSrc,
+ const RegisterBankInfo &RBI,
+ ReadLaneFnTy BuildRL) {
LLT Ty = B.getMRI()->getType(VgprSrc);
const RegisterBank *SgprRB = &RBI.getRegBank(AMDGPU::SGPRRegBankID);
if (Ty.getSizeInBits() == 32) {
-return B.buildInstr(AMDGPU::G_AMDGPU_READANYLANE, {{SgprRB, Ty}},
{VgprSrc})
-.getReg(0);
+Register SgprDst = B.getMRI()->createVirtualRegister({SgprRB, Ty});
+return BuildRL(B, SgprDst, VgprSrc).getReg(0);
}
SmallVector SgprDstParts;
- unmergeReadAnyLane(B, SgprDstParts, getReadAnyLaneSplitTy(Ty), VgprSrc, RBI);
+ unmergeReadAnyLane(B, SgprDstParts, getReadAnyLaneSplitTy(Ty), VgprSrc, RBI,
+ BuildRL);
return B.buildMergeLikeInstr({SgprRB, Ty}, SgprDstParts).getReg(0);
}
-void AMDGPU::buildReadAnyLane(MachineIRBuilder &B, Register SgprDst,
- Register VgprSrc, const RegisterBankInfo &RBI) {
+template
+static void buildReadLane(MachineIRBuilder &B, Register SgprDst,
+ Register VgprSrc, const RegisterBankInfo &RBI,
+ ReadLaneFnTy BuildReadLane) {
LLT Ty = B.getMRI()->getType(VgprSrc);
if (Ty.getSizeInBits() == 32) {
-B.buildInstr(AMDGPU::G_AMDGPU_READANYLANE, {SgprDst}, {VgprSrc});
+BuildReadLane(B, SgprDst, VgprSrc);
return;
}
SmallVector SgprDstParts;
- unmergeReadAnyLane(B, SgprDstParts, getReadAnyLaneSplitTy(Ty), VgprSrc, RBI);
+ unmergeReadAnyLane(B, SgprDstParts, getReadAnyLaneSplitTy(Ty), VgprSrc, RBI,
+ BuildReadLane);
B.buildMergeLikeInstr(SgprDst, SgprDstParts).getReg(0);
}
+
+void AMDGPU::buildReadAnyLane(MachineIRBuilder &B, Register SgprDst,
+ Register VgprSrc
[llvm-branch-commits] [llvm] TableGen: Handle setting runtime libcall calling conventions (PR #144980)
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/144980 >From 370182a91bbee541956ff153044a82ca929846cd Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 13 Jun 2025 15:54:41 +0900 Subject: [PATCH] TableGen: Handle setting runtime libcall calling conventions Allow associating a non-default CallingConv with a set of library functions, and applying a default for a SystemLibrary. I also wanted to be able to apply a default calling conv to a RuntimeLibcallImpl, but that turned out to be annoying so leave it for later. --- llvm/include/llvm/IR/RuntimeLibcalls.td | 140 +-- llvm/include/llvm/IR/RuntimeLibcallsImpl.td | 27 ++- llvm/lib/IR/RuntimeLibcalls.cpp | 141 --- .../RuntimeLibcallEmitter-calling-conv.td | 128 ++ llvm/test/TableGen/RuntimeLibcallEmitter.td | 19 +- .../TableGen/Basic/RuntimeLibcallsEmitter.cpp | 163 ++ 6 files changed, 429 insertions(+), 189 deletions(-) create mode 100644 llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.td b/llvm/include/llvm/IR/RuntimeLibcalls.td index 82e9d27959391..d7a1ef1cf524f 100644 --- a/llvm/include/llvm/IR/RuntimeLibcalls.td +++ b/llvm/include/llvm/IR/RuntimeLibcalls.td @@ -1282,11 +1282,12 @@ def __gnu_h2f_ieee : RuntimeLibcallImpl; //===--===// // Several of the runtime library functions use a special calling conv -def __divmodqi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN -def __divmodhi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN +def __divmodqi4 : RuntimeLibcallImpl; +def __divmodhi4 : RuntimeLibcallImpl; +def __udivmodqi4 : RuntimeLibcallImpl; +def __udivmodhi4 : RuntimeLibcallImpl; + //def __divmodsi4 : RuntimeLibcallImpl; -def __udivmodqi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN -def __udivmodhi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN //def __udivmodsi4 : RuntimeLibcallImpl; // Standard sinf/cosf name replaced with "sin" and "cos". Define a @@ -1312,9 +1313,12 @@ def AVRSystemLibrary // Standard f64 names are replaced sin, cos, sinf, cosf), - __divmodqi4, __divmodhi4, __divmodsi4, __udivmodqi4, __udivmodhi4, - __udivmodsi4, - + // Several of the runtime library functions use a special calling + // conv + LibcallsWithCC<(add __divmodqi4, __divmodhi4, __udivmodqi4, + __udivmodhi4), + AVR_BUILTIN>, + __divmodsi4, __udivmodsi4, // Trigonometric rtlib functions avr_sin, avr_cos)>; @@ -1537,6 +1541,117 @@ def __mspabi_mpyll : RuntimeLibcallImpl; // setLibcallCallingConv(MUL_I64, CallingConv::MSP430_BUILTIN); +def isMSP430 : RuntimeLibcallPredicate<"TT.getArch() == Triple::msp430">; + +defvar MSP430DefaultOptOut = [ + __addsf3, __divsf3, __extendsfdf2, __truncdfsf2, __fixsfsi, + __fixsfdi, __fixunssfsi, __mulsf3, __eqsf2, __gesf2, __gtsf2, + __divhi3, __divsi3, __ashlsi3, __floatsidf, __floatsisf, + __ashrsi3, __modhi3, __udivsi3, __fixdfsi, __fixunssfdi, + __udivhi3, __umodsi3, __nesf2, __lesf2, __floatundisf, + __fixdfdi, __fixunsdfsi, __modsi3, __floatunsisf, + __fixunsdfdi, __ltsf2, __floatdisf, __floatdidf, + __lshrsi3, __subsf3, __umodhi3, __floatunsidf, + __floatundidf +]; + +// EABI Libcalls - EABI Section 6.2 +def MSP430SystemLibrary +: SystemRuntimeLibrary, + __mspabi_cmpf__oeq, + __mspabi_cmpf__une, + __mspabi_cmpf__oge, + __mspabi_cmpf__olt, + __mspabi_cmpf__ole, + __mspabi_cmpf__ogt, + + // Floating point arithmetic - EABI Table 8 + LibcallsWithCC<(add __mspabi_addd, + __mspabi_subd, + __mspabi_mpyd, + __mspabi_divd), MSP430_BUILTIN>, + + __mspabi_addf, + __mspabi_subf, + __mspabi_mpyf, + __mspabi_divf, + + // The following are NOT implemented in libgcc + // __mspabi_negd, + // __mspabi_negf, + + // Universal Integer Operations - EABI Table 9 + __mspabi_divi, + __mspabi_divli, + LibcallsWithCC<(add __mspabi_divlli), MSP430_BUILTIN>, + __mspabi_divu, + __mspabi_divul, + LibcallsWithCC<(add __mspabi_divull), MSP430_BUILTIN>, + __mspabi_remi, + __mspabi_remli, + LibcallsWithCC<(add __mspabi_remlli), MSP430_BUILTIN>, + __mspabi_remu, + __mspabi_remul, + LibcallsWithCC<(add __mspabi_remull), MSP430_BUILTIN>, + + // Bitwise Operations - EABI Table 10 + // TODO: __mspabi_[srli/srai/slli] ARE implemented in libgcc + __mspabi_srll, + __mspabi_sral, + __mspabi_slll + // __mspabi_[srlll/srall/s/rlli/rlll] are NOT implemented in libgcc + ) +>; + //===--===// // NVPTX Runtime Libcalls //===---
[llvm-branch-commits] [llvm] ARM: Unconditionally set eabi libcall calling convs in RuntimeLibcalls (PR #146083)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/146083
>From 91dd754b1d7fd2bf763a9dc1ed85e99b03e1a2d5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 20:14:11 +0900
Subject: [PATCH] ARM: Unconditionally set eabi libcall calling convs in
RuntimeLibcalls
This fully consolidates all the calling convention configuration into
RuntimeLibcallInfo. I'm assuming that __aeabi functions have a universal
calling convention, and on other ABIs just don't use them. This will
enable splitting of RuntimeLibcallInfo into the ABI and lowering component.
---
llvm/lib/IR/RuntimeLibcalls.cpp | 39 ++
llvm/lib/Target/ARM/ARMISelLowering.cpp | 159 +++-
2 files changed, 110 insertions(+), 88 deletions(-)
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index b08ee16791dfd..9f24e9d1fc4b1 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -98,6 +98,45 @@ static void setARMLibcallNames(RuntimeLibcallsInfo &Info,
const Triple &TT,
Info.setLibcallImpl(RTLIB::SDIVREM_I32, RTLIB::__divmodsi4);
Info.setLibcallImpl(RTLIB::UDIVREM_I32, RTLIB::__udivmodsi4);
}
+
+ static const RTLIB::LibcallImpl AAPCS_Libcalls[] = {
+ RTLIB::__aeabi_dadd, RTLIB::__aeabi_ddiv,
+ RTLIB::__aeabi_dmul, RTLIB::__aeabi_dsub,
+ RTLIB::__aeabi_dcmpeq__ne, RTLIB::__aeabi_dcmpeq__eq,
+ RTLIB::__aeabi_dcmplt, RTLIB::__aeabi_dcmple,
+ RTLIB::__aeabi_dcmpge, RTLIB::__aeabi_dcmpgt,
+ RTLIB::__aeabi_dcmpun, RTLIB::__aeabi_fadd,
+ RTLIB::__aeabi_fdiv, RTLIB::__aeabi_fmul,
+ RTLIB::__aeabi_fsub, RTLIB::__aeabi_fcmpeq__ne,
+ RTLIB::__aeabi_fcmpeq__eq, RTLIB::__aeabi_fcmplt,
+ RTLIB::__aeabi_fcmple, RTLIB::__aeabi_fcmpge,
+ RTLIB::__aeabi_fcmpgt, RTLIB::__aeabi_fcmpun,
+ RTLIB::__aeabi_d2iz, RTLIB::__aeabi_d2uiz,
+ RTLIB::__aeabi_d2lz, RTLIB::__aeabi_d2ulz,
+ RTLIB::__aeabi_f2iz, RTLIB::__aeabi_f2uiz,
+ RTLIB::__aeabi_f2lz, RTLIB::__aeabi_f2ulz,
+ RTLIB::__aeabi_d2f,RTLIB::__aeabi_d2h,
+ RTLIB::__aeabi_f2d,RTLIB::__aeabi_i2d,
+ RTLIB::__aeabi_ui2d, RTLIB::__aeabi_l2d,
+ RTLIB::__aeabi_ul2d, RTLIB::__aeabi_i2f,
+ RTLIB::__aeabi_ui2f, RTLIB::__aeabi_l2f,
+ RTLIB::__aeabi_ul2f, RTLIB::__aeabi_lmul,
+ RTLIB::__aeabi_llsl, RTLIB::__aeabi_llsr,
+ RTLIB::__aeabi_lasr, RTLIB::__aeabi_idiv__i8,
+ RTLIB::__aeabi_idiv__i16, RTLIB::__aeabi_idiv__i32,
+ RTLIB::__aeabi_ldivmod,RTLIB::__aeabi_uidiv__i8,
+ RTLIB::__aeabi_uidiv__i16, RTLIB::__aeabi_uidiv__i32,
+ RTLIB::__aeabi_uldivmod, RTLIB::__aeabi_f2h,
+ RTLIB::__aeabi_d2h,RTLIB::__aeabi_h2f,
+ RTLIB::__aeabi_memcpy, RTLIB::__aeabi_memmove,
+ RTLIB::__aeabi_memset, RTLIB::__aeabi_memcpy4,
+ RTLIB::__aeabi_memcpy8,RTLIB::__aeabi_memmove4,
+ RTLIB::__aeabi_memmove8, RTLIB::__aeabi_memset4,
+ RTLIB::__aeabi_memset8,RTLIB::__aeabi_memclr,
+ RTLIB::__aeabi_memclr4,RTLIB::__aeabi_memclr8};
+
+ for (RTLIB::LibcallImpl Impl : AAPCS_Libcalls)
+Info.setLibcallImplCallingConv(Impl, CallingConv::ARM_AAPCS);
}
static void setLongDoubleIsF128Libm(RuntimeLibcallsInfo &Info,
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp
b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 78ef3c23e8423..2ece698df264b 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -578,9 +578,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
};
// clang-format on
- for (const auto &LC : LibraryCalls) {
+ for (const auto &LC : LibraryCalls)
setLibcallImpl(LC.Op, LC.Impl);
- }
}
}
@@ -594,94 +593,91 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
static const struct {
const RTLIB::Libcall Op;
const RTLIB::LibcallImpl Impl;
- const CallingConv::ID CC;
} LibraryCalls[] = {
// Double-precision floating-point arithmetic helper functions
// RTABI chapter 4.1.2, Table 2
- { RTLIB::ADD_F64, RTLIB::__aeabi_dadd, CallingConv::ARM_AAPCS },
- { RTLIB::DIV_F64, RTLIB::__aeabi_ddiv, CallingConv::ARM_AAPCS },
- { RTLIB::MUL_F64, RTLIB::__aeabi_dmul, CallingConv::ARM_AAPCS },
- { RTLIB::SUB_F64, RTLIB::__aeabi_dsub, CallingConv::ARM_AAPCS },
+ { RTLIB::ADD_F64, RTLIB::__aeabi_dadd },
+ { RTLIB::DIV_F64, RTLIB::__aeabi_ddiv },
+ { RTLIB::MUL_F64, RTLIB::__aeabi_dmul },
+ { RTLIB::SUB_F64, RTLIB::__aeabi_dsub },
// Double-precision floating-point comparison helper functions
// RTABI chapter 4.1.2, Table 3
- { RTLIB::OEQ_F64, RTLIB::__aeabi_dcmpeq__ne, CallingConv::ARM_AAPCS },
- { RTLIB::UNE_F64, RTLIB::__aeabi_dcmpeq__eq, CallingConv::ARM_AAPCS },
- { RTL
[llvm-branch-commits] [llvm] RuntimeLibcalls: Remove table of soft float compare cond codes (PR #146082)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/146082
>From c76b2c4a2b11717d8c4b1607cbcd57de6e2da39b Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 19:10:30 +0900
Subject: [PATCH] RuntimeLibcalls: Remove table of soft float compare cond
codes
Previously we had a table of entries for every Libcall for
the comparison to use against an integer 0 if it was a soft
float compare function. This was only relevant to a handful of
opcodes, so it was wasteful. Now that we can distinguish the
abstract libcall for the compare with the concrete implementation,
we can just directly hardcode the comparison against the libcall
impl without this configuration system.
---
.../include/llvm/CodeGen/RuntimeLibcallUtil.h | 3 -
llvm/include/llvm/CodeGen/TargetLowering.h| 17 +-
llvm/include/llvm/IR/RuntimeLibcalls.h| 32 +---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 16 +-
llvm/lib/CodeGen/TargetLoweringBase.cpp | 107 +++
llvm/lib/IR/RuntimeLibcalls.cpp | 31 ---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 176 +-
7 files changed, 182 insertions(+), 200 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
b/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
index 7481ed5b80b3f..09a8151e9ec9c 100644
--- a/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
+++ b/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
@@ -105,9 +105,6 @@ LLVM_ABI Libcall
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize);
/// UNKNOW_LIBCALL if there is none.
LLVM_ABI Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize);
-/// Initialize the default condition code on the libcalls.
-LLVM_ABI void initCmpLibcallCCs(ISD::CondCode *CmpLibcallCCs);
-
} // namespace RTLIB
} // namespace llvm
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h
b/llvm/include/llvm/CodeGen/TargetLowering.h
index 8e05c53dc513d..31bd0887e1b14 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -3574,19 +3574,10 @@ class LLVM_ABI TargetLoweringBase {
const char *getMemcpyName() const { return Libcalls.getMemcpyName(); }
- /// Override the default CondCode to be used to test the result of the
- /// comparison libcall against zero.
- /// FIXME: This should be removed
- void setCmpLibcallCC(RTLIB::Libcall Call, CmpInst::Predicate Pred) {
-Libcalls.setSoftFloatCmpLibcallPredicate(Call, Pred);
- }
-
- /// Get the CondCode that's to be used to test the result of the comparison
- /// libcall against zero.
- CmpInst::Predicate
- getSoftFloatCmpLibcallPredicate(RTLIB::Libcall Call) const {
-return Libcalls.getSoftFloatCmpLibcallPredicate(Call);
- }
+ /// Get the comparison predicate that's to be used to test the result of the
+ /// comparison libcall against zero. This should only be used with
+ /// floating-point compare libcalls.
+ ISD::CondCode getSoftFloatCmpLibcallPredicate(RTLIB::LibcallImpl Call) const;
/// Set the CallingConv that should be used for the specified libcall.
void setLibcallImplCallingConv(RTLIB::LibcallImpl Call, CallingConv::ID CC) {
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.h
b/llvm/include/llvm/IR/RuntimeLibcalls.h
index 8c11ce9ed2920..ecf20cbfd09f2 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.h
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.h
@@ -59,7 +59,6 @@ struct RuntimeLibcallsInfo {
ExceptionHandling ExceptionModel = ExceptionHandling::None,
FloatABI::ABIType FloatABI = FloatABI::Default,
EABI EABIVersion = EABI::Default, StringRef ABIName = "") {
-initSoftFloatCmpLibcallPredicates();
initLibcalls(TT, ExceptionModel, FloatABI, EABIVersion, ABIName);
}
@@ -106,22 +105,6 @@ struct RuntimeLibcallsInfo {
return ArrayRef(LibcallImpls).drop_front();
}
- /// Get the comparison predicate that's to be used to test the result of the
- /// comparison libcall against zero. This should only be used with
- /// floating-point compare libcalls.
- // FIXME: This should be a function of RTLIB::LibcallImpl
- CmpInst::Predicate
- getSoftFloatCmpLibcallPredicate(RTLIB::Libcall Call) const {
-return SoftFloatCompareLibcallPredicates[Call];
- }
-
- // FIXME: This should be removed. This should be private constant.
- // FIXME: This should be a function of RTLIB::LibcallImpl
- void setSoftFloatCmpLibcallPredicate(RTLIB::Libcall Call,
- CmpInst::Predicate Pred) {
-SoftFloatCompareLibcallPredicates[Call] = Pred;
- }
-
/// Return a function name compatible with RTLIB::MEMCPY, or nullptr if fully
/// unsupported.
const char *getMemcpyName() const {
@@ -132,6 +115,11 @@ struct RuntimeLibcallsInfo {
return getLibcallName(RTLIB::MEMMOVE);
}
+ /// Return the libcall provided by \p Impl
+ static RTLIB::Libcall getLibcallFromImpl(RTLIB::LibcallImpl Impl) {
+return ImplToLibcall[Impl];
+ }
+
priva
[llvm-branch-commits] [llvm] RuntimeLibcalls: Associate calling convention with libcall impls (PR #144979)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144979
>From 5a8dc27dbdd4be0d14efeeca516376306de87ce0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 17 Jun 2025 16:25:50 +0900
Subject: [PATCH] RuntimeLibcalls: Associate calling convention with libcall
impls
Instead of associating the libcall with the RTLIB::Libcall, put it
into a table indexed by the RTLIB::LibcallImpl. The LibcallImpls
should contain all ABI details for a particular implementation, not
the abstract Libcall. In the future the wrappers in terms of the
RTLIB::Libcall should be removed.
---
llvm/include/llvm/CodeGen/TargetLowering.h| 16 -
llvm/include/llvm/IR/RuntimeLibcalls.h| 32 ++---
llvm/lib/IR/RuntimeLibcalls.cpp | 70 +++
llvm/lib/Target/ARM/ARMISelLowering.cpp | 18 ++---
llvm/lib/Target/Lanai/LanaiISelLowering.cpp | 4 +-
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp | 3 +-
6 files changed, 92 insertions(+), 51 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h
b/llvm/include/llvm/CodeGen/TargetLowering.h
index 84c53e1e45452..8e05c53dc513d 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -3562,6 +3562,11 @@ class LLVM_ABI TargetLoweringBase {
Libcalls.setLibcallImpl(Call, Impl);
}
+ /// Get the libcall impl routine name for the specified libcall.
+ RTLIB::LibcallImpl getLibcallImpl(RTLIB::Libcall Call) const {
+return Libcalls.getLibcallImpl(Call);
+ }
+
/// Get the libcall routine name for the specified libcall.
const char *getLibcallName(RTLIB::Libcall Call) const {
return Libcalls.getLibcallName(Call);
@@ -3584,11 +3589,18 @@ class LLVM_ABI TargetLoweringBase {
}
/// Set the CallingConv that should be used for the specified libcall.
- void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
-Libcalls.setLibcallCallingConv(Call, CC);
+ void setLibcallImplCallingConv(RTLIB::LibcallImpl Call, CallingConv::ID CC) {
+Libcalls.setLibcallImplCallingConv(Call, CC);
+ }
+
+ /// Get the CallingConv that should be used for the specified libcall
+ /// implementation.
+ CallingConv::ID getLibcallImplCallingConv(RTLIB::LibcallImpl Call) const {
+return Libcalls.getLibcallImplCallingConv(Call);
}
/// Get the CallingConv that should be used for the specified libcall.
+ // FIXME: Remove this wrapper and directly use the used LibcallImpl
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
return Libcalls.getLibcallCallingConv(Call);
}
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.h
b/llvm/include/llvm/IR/RuntimeLibcalls.h
index 811a9893abde2..8c11ce9ed2920 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.h
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.h
@@ -37,6 +37,10 @@ template <> struct enum_iteration_traits {
static constexpr bool is_iterable = true;
};
+template <> struct enum_iteration_traits {
+ static constexpr bool is_iterable = true;
+};
+
namespace RTLIB {
// Return an iterator over all Libcall values.
@@ -44,6 +48,10 @@ static inline auto libcalls() {
return enum_seq(static_cast(0), RTLIB::UNKNOWN_LIBCALL);
}
+static inline auto libcall_impls() {
+ return enum_seq(static_cast(1), RTLIB::NumLibcallImpls);
+}
+
/// A simple container for information about the supported runtime calls.
struct RuntimeLibcallsInfo {
explicit RuntimeLibcallsInfo(
@@ -76,16 +84,21 @@ struct RuntimeLibcallsInfo {
return LibcallImpls[Call];
}
- /// Set the CallingConv that should be used for the specified libcall.
- // FIXME: This should be a function of RTLIB::LibcallImpl
- void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
-LibcallCallingConvs[Call] = CC;
+ /// Set the CallingConv that should be used for the specified libcall
+ /// implementation
+ void setLibcallImplCallingConv(RTLIB::LibcallImpl Call, CallingConv::ID CC) {
+LibcallImplCallingConvs[Call] = CC;
}
- /// Get the CallingConv that should be used for the specified libcall.
- // FIXME: This should be a function of RTLIB::LibcallImpl
+ // FIXME: Remove this wrapper in favor of directly using
+ // getLibcallImplCallingConv
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
-return LibcallCallingConvs[Call];
+return LibcallImplCallingConvs[LibcallImpls[Call]];
+ }
+
+ /// Get the CallingConv that should be used for the specified libcall.
+ CallingConv::ID getLibcallImplCallingConv(RTLIB::LibcallImpl Call) const {
+return LibcallImplCallingConvs[Call];
}
ArrayRef getLibcallImpls() const {
@@ -130,8 +143,9 @@ struct RuntimeLibcallsInfo {
static_assert(static_cast(CallingConv::C) == 0,
"default calling conv should be encoded as 0");
- /// Stores the CallingConv that should be used for each libcall.
- CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL] = {};
+ /// Stores th
[llvm-branch-commits] [clang] 038de66 - Revert "[Hexagon] NFC: Reduce the amount of version-specific code (#145812)"
Author: Brian Cain
Date: 2025-06-27T21:52:11-05:00
New Revision: 038de66cab523ad7719882a96fa51afcd8c9
URL:
https://github.com/llvm/llvm-project/commit/038de66cab523ad7719882a96fa51afcd8c9
DIFF:
https://github.com/llvm/llvm-project/commit/038de66cab523ad7719882a96fa51afcd8c9.diff
LOG: Revert "[Hexagon] NFC: Reduce the amount of version-specific code
(#145812)"
This reverts commit e9c9adcefed10fa07910aae8f2074aedf7bd8b7e.
Added:
Modified:
clang/lib/Basic/Targets/Hexagon.cpp
clang/lib/Basic/Targets/Hexagon.h
llvm/lib/Target/Hexagon/HexagonDepArch.h
llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
Removed:
diff --git a/clang/lib/Basic/Targets/Hexagon.cpp
b/clang/lib/Basic/Targets/Hexagon.cpp
index 9fff20bf0f417..06dcac03baa5b 100644
--- a/clang/lib/Basic/Targets/Hexagon.cpp
+++ b/clang/lib/Basic/Targets/Hexagon.cpp
@@ -18,19 +18,6 @@
using namespace clang;
using namespace clang::targets;
-namespace {
-
-constexpr llvm::StringLiteral CpuValsTextArray[] = {
-"hexagonv5", "hexagonv55", "hexagonv60", "hexagonv62", "hexagonv65",
-"hexagonv66", "hexagonv67", "hexagonv67t", "hexagonv68", "hexagonv69",
-"hexagonv71", "hexagonv71t", "hexagonv73", "hexagonv75", "hexagonv79",
-};
-
-} // namespace
-
-const llvm::ArrayRef
-HexagonTargetInfo::CpuValsText(CpuValsTextArray);
-
void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
Builder.defineMacro("__qdsp6__", "1");
@@ -252,6 +239,22 @@ bool HexagonTargetInfo::hasFeature(StringRef Feature)
const {
.Default(false);
}
+struct CPUSuffix {
+ llvm::StringLiteral Name;
+ llvm::StringLiteral Suffix;
+};
+
+static constexpr CPUSuffix Suffixes[] = {
+{{"hexagonv5"}, {"5"}}, {{"hexagonv55"}, {"55"}},
+{{"hexagonv60"}, {"60"}}, {{"hexagonv62"}, {"62"}},
+{{"hexagonv65"}, {"65"}}, {{"hexagonv66"}, {"66"}},
+{{"hexagonv67"}, {"67"}}, {{"hexagonv67t"}, {"67t"}},
+{{"hexagonv68"}, {"68"}}, {{"hexagonv69"}, {"69"}},
+{{"hexagonv71"}, {"71"}}, {{"hexagonv71t"}, {"71t"}},
+{{"hexagonv73"}, {"73"}}, {{"hexagonv75"}, {"75"}},
+{{"hexagonv79"}, {"79"}},
+};
+
std::optional HexagonTargetInfo::getHexagonCPURev(StringRef Name) {
StringRef Arch = Name;
Arch.consume_front("hexagonv");
@@ -264,10 +267,18 @@ std::optional
HexagonTargetInfo::getHexagonCPURev(StringRef Name) {
return std::nullopt;
}
+const char *HexagonTargetInfo::getHexagonCPUSuffix(StringRef Name) {
+ const CPUSuffix *Item = llvm::find_if(
+ Suffixes, [Name](const CPUSuffix &S) { return S.Name == Name; });
+ if (Item == std::end(Suffixes))
+return nullptr;
+ return Item->Suffix.data();
+}
+
void HexagonTargetInfo::fillValidCPUList(
SmallVectorImpl &Values) const {
- for (const llvm::StringLiteral &I : CpuValsText)
-Values.push_back(I);
+ for (const CPUSuffix &Suffix : Suffixes)
+Values.push_back(Suffix.Name);
}
llvm::SmallVector
diff --git a/clang/lib/Basic/Targets/Hexagon.h
b/clang/lib/Basic/Targets/Hexagon.h
index 8aebbe157d6c1..a65663ca09eee 100644
--- a/clang/lib/Basic/Targets/Hexagon.h
+++ b/clang/lib/Basic/Targets/Hexagon.h
@@ -25,7 +25,6 @@ namespace targets {
// Hexagon abstract base class
class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public TargetInfo {
- static const llvm::ArrayRef CpuValsText;
static const char *const GCCRegNames[];
static const TargetInfo::GCCRegAlias GCCRegAliases[];
std::string CPU;
@@ -116,11 +115,11 @@ class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public
TargetInfo {
std::string_view getClobbers() const override { return ""; }
+ static const char *getHexagonCPUSuffix(StringRef Name);
static std::optional getHexagonCPURev(StringRef Name);
bool isValidCPUName(StringRef Name) const override {
-return std::any_of(std::begin(CpuValsText), std::end(CpuValsText),
- [Name](StringRef V) { return V == Name; });
+return getHexagonCPUSuffix(Name);
}
void fillValidCPUList(SmallVectorImpl &Values) const override;
diff --git a/llvm/lib/Target/Hexagon/HexagonDepArch.h
b/llvm/lib/Target/Hexagon/HexagonDepArch.h
index 6f851a042ca20..89845348a9e31 100644
--- a/llvm/lib/Target/Hexagon/HexagonDepArch.h
+++ b/llvm/lib/Target/Hexagon/HexagonDepArch.h
@@ -32,6 +32,26 @@ enum class ArchEnum {
V79
};
+inline std::optional getCpu(StringRef CPU) {
+ return StringSwitch>(CPU)
+ .Case("generic", Hexagon::ArchEnum::V5)
+ .Case("hexagonv5", Hexagon::ArchEnum::V5)
+ .Case("hexagonv55", Hexagon::ArchEnum::V55)
+ .Case("hexagonv60", Hexagon::ArchEnum::V60)
+ .Case("hexagonv62", Hexagon::ArchEnum::V62
[llvm-branch-commits] [llvm] MSP430: Move libcall CC setting to RuntimeLibcallsInfo (PR #146081)
https://github.com/asl approved this pull request. https://github.com/llvm/llvm-project/pull/146081 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Lanai: Use TableGen to set libcall calling conventions (PR #146080)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/146080
>From c7f71df65704b30f20e86a9f26c561e55129114e Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 16:17:26 +0900
Subject: [PATCH] Lanai: Use TableGen to set libcall calling conventions
---
llvm/include/llvm/IR/RuntimeLibcalls.td | 12
llvm/lib/Target/Lanai/LanaiISelLowering.cpp | 4
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.td
b/llvm/include/llvm/IR/RuntimeLibcalls.td
index d7a1ef1cf524f..d9ee8ff6839b3 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.td
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.td
@@ -1360,6 +1360,18 @@ def __hexagon_fast2_sqrtdf2 :
RuntimeLibcallImpl;
def __hexagon_memcpy_likely_aligned_min32bytes_mult8bytes
: RuntimeLibcallImpl;
+//===--===//
+// Lanai Runtime Libcalls
+//===--===//
+
+def isLanai : RuntimeLibcallPredicate<"TT.getArch() == Triple::lanai">;
+
+// Use fast calling convention for library functions.
+def LanaiSystemLibrary
+: SystemRuntimeLibrary {
+ let DefaultLibcallCallingConv = FASTCC;
+}
+
//===--===//
// Mips16 Runtime Libcalls
//===--===//
diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
index ec668ebaeab0d..272c7bc1a8db6 100644
--- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
+++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
@@ -150,10 +150,6 @@ LanaiTargetLowering::LanaiTargetLowering(const
TargetMachine &TM,
// statements. Re-evaluate this on new benchmarks.
setMinimumJumpTableEntries(100);
- // Use fast calling convention for library functions.
- for (RTLIB::LibcallImpl LC : RTLIB::libcall_impls())
-setLibcallImplCallingConv(LC, CallingConv::Fast);
-
MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
MaxStoresPerMemsetOptSize = 8;
MaxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
___
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[llvm-branch-commits] [llvm] MSP430: Move libcall CC setting to RuntimeLibcallsInfo (PR #146081)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/146081
>From 78df65066d4209ace408942be82107681bd135ec Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 16:35:14 +0900
Subject: [PATCH] MSP430: Move libcall CC setting to RuntimeLibcallsInfo
As a temporary step configure the calling convention here. This
can't be moved into tablegen until RuntimeLibcallsInfo is split
into a separate lowering component.
---
llvm/lib/IR/RuntimeLibcalls.cpp | 5 +
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp | 2 --
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index 6f1f7014249c7..a5605329c7d28 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -365,6 +365,11 @@ void RuntimeLibcallsInfo::initLibcalls(const Triple &TT,
RTLIB::HEXAGON_MEMCPY_LIKELY_ALIGNED_MIN32BYTES_MULT8BYTES,
RTLIB::__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes);
}
+
+ if (TT.getArch() == Triple::ArchType::msp430) {
+setLibcallImplCallingConv(RTLIB::__mspabi_mpyll,
+ CallingConv::MSP430_BUILTIN);
+ }
}
bool RuntimeLibcallsInfo::darwinHasExp10(const Triple &TT) {
diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
index d558dd253dc46..0d7c7b5c7a813 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -208,8 +208,6 @@ MSP430TargetLowering::MSP430TargetLowering(const
TargetMachine &TM,
for (const auto &LC : LibraryCalls) {
setLibcallImpl(LC.Op, LC.Impl);
}
-setLibcallImplCallingConv(RTLIB::__mspabi_mpyll,
- CallingConv::MSP430_BUILTIN);
}
setMinFunctionAlignment(Align(2));
___
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[llvm-branch-commits] [llvm] Lanai: Use TableGen to set libcall calling conventions (PR #146080)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/146080
>From c7f71df65704b30f20e86a9f26c561e55129114e Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 16:17:26 +0900
Subject: [PATCH] Lanai: Use TableGen to set libcall calling conventions
---
llvm/include/llvm/IR/RuntimeLibcalls.td | 12
llvm/lib/Target/Lanai/LanaiISelLowering.cpp | 4
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.td
b/llvm/include/llvm/IR/RuntimeLibcalls.td
index d7a1ef1cf524f..d9ee8ff6839b3 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.td
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.td
@@ -1360,6 +1360,18 @@ def __hexagon_fast2_sqrtdf2 :
RuntimeLibcallImpl;
def __hexagon_memcpy_likely_aligned_min32bytes_mult8bytes
: RuntimeLibcallImpl;
+//===--===//
+// Lanai Runtime Libcalls
+//===--===//
+
+def isLanai : RuntimeLibcallPredicate<"TT.getArch() == Triple::lanai">;
+
+// Use fast calling convention for library functions.
+def LanaiSystemLibrary
+: SystemRuntimeLibrary {
+ let DefaultLibcallCallingConv = FASTCC;
+}
+
//===--===//
// Mips16 Runtime Libcalls
//===--===//
diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
index ec668ebaeab0d..272c7bc1a8db6 100644
--- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
+++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
@@ -150,10 +150,6 @@ LanaiTargetLowering::LanaiTargetLowering(const
TargetMachine &TM,
// statements. Re-evaluate this on new benchmarks.
setMinimumJumpTableEntries(100);
- // Use fast calling convention for library functions.
- for (RTLIB::LibcallImpl LC : RTLIB::libcall_impls())
-setLibcallImplCallingConv(LC, CallingConv::Fast);
-
MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
MaxStoresPerMemsetOptSize = 8;
MaxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
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[llvm-branch-commits] [llvm] RuntimeLibcalls: Remove table of soft float compare cond codes (PR #146082)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/146082
>From c76b2c4a2b11717d8c4b1607cbcd57de6e2da39b Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 19:10:30 +0900
Subject: [PATCH] RuntimeLibcalls: Remove table of soft float compare cond
codes
Previously we had a table of entries for every Libcall for
the comparison to use against an integer 0 if it was a soft
float compare function. This was only relevant to a handful of
opcodes, so it was wasteful. Now that we can distinguish the
abstract libcall for the compare with the concrete implementation,
we can just directly hardcode the comparison against the libcall
impl without this configuration system.
---
.../include/llvm/CodeGen/RuntimeLibcallUtil.h | 3 -
llvm/include/llvm/CodeGen/TargetLowering.h| 17 +-
llvm/include/llvm/IR/RuntimeLibcalls.h| 32 +---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 16 +-
llvm/lib/CodeGen/TargetLoweringBase.cpp | 107 +++
llvm/lib/IR/RuntimeLibcalls.cpp | 31 ---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 176 +-
7 files changed, 182 insertions(+), 200 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
b/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
index 7481ed5b80b3f..09a8151e9ec9c 100644
--- a/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
+++ b/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
@@ -105,9 +105,6 @@ LLVM_ABI Libcall
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize);
/// UNKNOW_LIBCALL if there is none.
LLVM_ABI Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize);
-/// Initialize the default condition code on the libcalls.
-LLVM_ABI void initCmpLibcallCCs(ISD::CondCode *CmpLibcallCCs);
-
} // namespace RTLIB
} // namespace llvm
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h
b/llvm/include/llvm/CodeGen/TargetLowering.h
index 8e05c53dc513d..31bd0887e1b14 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -3574,19 +3574,10 @@ class LLVM_ABI TargetLoweringBase {
const char *getMemcpyName() const { return Libcalls.getMemcpyName(); }
- /// Override the default CondCode to be used to test the result of the
- /// comparison libcall against zero.
- /// FIXME: This should be removed
- void setCmpLibcallCC(RTLIB::Libcall Call, CmpInst::Predicate Pred) {
-Libcalls.setSoftFloatCmpLibcallPredicate(Call, Pred);
- }
-
- /// Get the CondCode that's to be used to test the result of the comparison
- /// libcall against zero.
- CmpInst::Predicate
- getSoftFloatCmpLibcallPredicate(RTLIB::Libcall Call) const {
-return Libcalls.getSoftFloatCmpLibcallPredicate(Call);
- }
+ /// Get the comparison predicate that's to be used to test the result of the
+ /// comparison libcall against zero. This should only be used with
+ /// floating-point compare libcalls.
+ ISD::CondCode getSoftFloatCmpLibcallPredicate(RTLIB::LibcallImpl Call) const;
/// Set the CallingConv that should be used for the specified libcall.
void setLibcallImplCallingConv(RTLIB::LibcallImpl Call, CallingConv::ID CC) {
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.h
b/llvm/include/llvm/IR/RuntimeLibcalls.h
index 8c11ce9ed2920..ecf20cbfd09f2 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.h
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.h
@@ -59,7 +59,6 @@ struct RuntimeLibcallsInfo {
ExceptionHandling ExceptionModel = ExceptionHandling::None,
FloatABI::ABIType FloatABI = FloatABI::Default,
EABI EABIVersion = EABI::Default, StringRef ABIName = "") {
-initSoftFloatCmpLibcallPredicates();
initLibcalls(TT, ExceptionModel, FloatABI, EABIVersion, ABIName);
}
@@ -106,22 +105,6 @@ struct RuntimeLibcallsInfo {
return ArrayRef(LibcallImpls).drop_front();
}
- /// Get the comparison predicate that's to be used to test the result of the
- /// comparison libcall against zero. This should only be used with
- /// floating-point compare libcalls.
- // FIXME: This should be a function of RTLIB::LibcallImpl
- CmpInst::Predicate
- getSoftFloatCmpLibcallPredicate(RTLIB::Libcall Call) const {
-return SoftFloatCompareLibcallPredicates[Call];
- }
-
- // FIXME: This should be removed. This should be private constant.
- // FIXME: This should be a function of RTLIB::LibcallImpl
- void setSoftFloatCmpLibcallPredicate(RTLIB::Libcall Call,
- CmpInst::Predicate Pred) {
-SoftFloatCompareLibcallPredicates[Call] = Pred;
- }
-
/// Return a function name compatible with RTLIB::MEMCPY, or nullptr if fully
/// unsupported.
const char *getMemcpyName() const {
@@ -132,6 +115,11 @@ struct RuntimeLibcallsInfo {
return getLibcallName(RTLIB::MEMMOVE);
}
+ /// Return the libcall provided by \p Impl
+ static RTLIB::Libcall getLibcallFromImpl(RTLIB::LibcallImpl Impl) {
+return ImplToLibcall[Impl];
+ }
+
priva
[llvm-branch-commits] [llvm] ARM: Unconditionally set eabi libcall calling convs in RuntimeLibcalls (PR #146083)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/146083
>From 91dd754b1d7fd2bf763a9dc1ed85e99b03e1a2d5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 20:14:11 +0900
Subject: [PATCH] ARM: Unconditionally set eabi libcall calling convs in
RuntimeLibcalls
This fully consolidates all the calling convention configuration into
RuntimeLibcallInfo. I'm assuming that __aeabi functions have a universal
calling convention, and on other ABIs just don't use them. This will
enable splitting of RuntimeLibcallInfo into the ABI and lowering component.
---
llvm/lib/IR/RuntimeLibcalls.cpp | 39 ++
llvm/lib/Target/ARM/ARMISelLowering.cpp | 159 +++-
2 files changed, 110 insertions(+), 88 deletions(-)
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index b08ee16791dfd..9f24e9d1fc4b1 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -98,6 +98,45 @@ static void setARMLibcallNames(RuntimeLibcallsInfo &Info,
const Triple &TT,
Info.setLibcallImpl(RTLIB::SDIVREM_I32, RTLIB::__divmodsi4);
Info.setLibcallImpl(RTLIB::UDIVREM_I32, RTLIB::__udivmodsi4);
}
+
+ static const RTLIB::LibcallImpl AAPCS_Libcalls[] = {
+ RTLIB::__aeabi_dadd, RTLIB::__aeabi_ddiv,
+ RTLIB::__aeabi_dmul, RTLIB::__aeabi_dsub,
+ RTLIB::__aeabi_dcmpeq__ne, RTLIB::__aeabi_dcmpeq__eq,
+ RTLIB::__aeabi_dcmplt, RTLIB::__aeabi_dcmple,
+ RTLIB::__aeabi_dcmpge, RTLIB::__aeabi_dcmpgt,
+ RTLIB::__aeabi_dcmpun, RTLIB::__aeabi_fadd,
+ RTLIB::__aeabi_fdiv, RTLIB::__aeabi_fmul,
+ RTLIB::__aeabi_fsub, RTLIB::__aeabi_fcmpeq__ne,
+ RTLIB::__aeabi_fcmpeq__eq, RTLIB::__aeabi_fcmplt,
+ RTLIB::__aeabi_fcmple, RTLIB::__aeabi_fcmpge,
+ RTLIB::__aeabi_fcmpgt, RTLIB::__aeabi_fcmpun,
+ RTLIB::__aeabi_d2iz, RTLIB::__aeabi_d2uiz,
+ RTLIB::__aeabi_d2lz, RTLIB::__aeabi_d2ulz,
+ RTLIB::__aeabi_f2iz, RTLIB::__aeabi_f2uiz,
+ RTLIB::__aeabi_f2lz, RTLIB::__aeabi_f2ulz,
+ RTLIB::__aeabi_d2f,RTLIB::__aeabi_d2h,
+ RTLIB::__aeabi_f2d,RTLIB::__aeabi_i2d,
+ RTLIB::__aeabi_ui2d, RTLIB::__aeabi_l2d,
+ RTLIB::__aeabi_ul2d, RTLIB::__aeabi_i2f,
+ RTLIB::__aeabi_ui2f, RTLIB::__aeabi_l2f,
+ RTLIB::__aeabi_ul2f, RTLIB::__aeabi_lmul,
+ RTLIB::__aeabi_llsl, RTLIB::__aeabi_llsr,
+ RTLIB::__aeabi_lasr, RTLIB::__aeabi_idiv__i8,
+ RTLIB::__aeabi_idiv__i16, RTLIB::__aeabi_idiv__i32,
+ RTLIB::__aeabi_ldivmod,RTLIB::__aeabi_uidiv__i8,
+ RTLIB::__aeabi_uidiv__i16, RTLIB::__aeabi_uidiv__i32,
+ RTLIB::__aeabi_uldivmod, RTLIB::__aeabi_f2h,
+ RTLIB::__aeabi_d2h,RTLIB::__aeabi_h2f,
+ RTLIB::__aeabi_memcpy, RTLIB::__aeabi_memmove,
+ RTLIB::__aeabi_memset, RTLIB::__aeabi_memcpy4,
+ RTLIB::__aeabi_memcpy8,RTLIB::__aeabi_memmove4,
+ RTLIB::__aeabi_memmove8, RTLIB::__aeabi_memset4,
+ RTLIB::__aeabi_memset8,RTLIB::__aeabi_memclr,
+ RTLIB::__aeabi_memclr4,RTLIB::__aeabi_memclr8};
+
+ for (RTLIB::LibcallImpl Impl : AAPCS_Libcalls)
+Info.setLibcallImplCallingConv(Impl, CallingConv::ARM_AAPCS);
}
static void setLongDoubleIsF128Libm(RuntimeLibcallsInfo &Info,
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp
b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 78ef3c23e8423..2ece698df264b 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -578,9 +578,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
};
// clang-format on
- for (const auto &LC : LibraryCalls) {
+ for (const auto &LC : LibraryCalls)
setLibcallImpl(LC.Op, LC.Impl);
- }
}
}
@@ -594,94 +593,91 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
static const struct {
const RTLIB::Libcall Op;
const RTLIB::LibcallImpl Impl;
- const CallingConv::ID CC;
} LibraryCalls[] = {
// Double-precision floating-point arithmetic helper functions
// RTABI chapter 4.1.2, Table 2
- { RTLIB::ADD_F64, RTLIB::__aeabi_dadd, CallingConv::ARM_AAPCS },
- { RTLIB::DIV_F64, RTLIB::__aeabi_ddiv, CallingConv::ARM_AAPCS },
- { RTLIB::MUL_F64, RTLIB::__aeabi_dmul, CallingConv::ARM_AAPCS },
- { RTLIB::SUB_F64, RTLIB::__aeabi_dsub, CallingConv::ARM_AAPCS },
+ { RTLIB::ADD_F64, RTLIB::__aeabi_dadd },
+ { RTLIB::DIV_F64, RTLIB::__aeabi_ddiv },
+ { RTLIB::MUL_F64, RTLIB::__aeabi_dmul },
+ { RTLIB::SUB_F64, RTLIB::__aeabi_dsub },
// Double-precision floating-point comparison helper functions
// RTABI chapter 4.1.2, Table 3
- { RTLIB::OEQ_F64, RTLIB::__aeabi_dcmpeq__ne, CallingConv::ARM_AAPCS },
- { RTLIB::UNE_F64, RTLIB::__aeabi_dcmpeq__eq, CallingConv::ARM_AAPCS },
- { RTL
[llvm-branch-commits] [llvm] ARM: Start moving runtime libcalls into tablegen (PR #146084)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/146084
>From 4e563f6e7a85e1feae98edafc527bb773a7abcca Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 23:23:01 +0900
Subject: [PATCH] ARM: Start moving runtime libcalls into tablegen
We still need to manually set the calling conventions of
some libcalls until the lowering is separated out.
---
llvm/include/llvm/IR/RuntimeLibcalls.h| 2 +-
llvm/include/llvm/IR/RuntimeLibcalls.td | 48
llvm/lib/IR/RuntimeLibcalls.cpp | 76 +--
.../TableGen/Basic/RuntimeLibcallsEmitter.cpp | 2 +-
4 files changed, 51 insertions(+), 77 deletions(-)
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.h
b/llvm/include/llvm/IR/RuntimeLibcalls.h
index ecf20cbfd09f2..7fb6b503daa22 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.h
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.h
@@ -168,7 +168,7 @@ struct RuntimeLibcallsInfo {
void initDefaultLibCallImpls();
/// Generated by tablegen.
- void setTargetRuntimeLibcallSets(const Triple &TT);
+ void setTargetRuntimeLibcallSets(const Triple &TT, FloatABI::ABIType
FloatABI);
/// Set default libcall names. If a target wants to opt-out of a libcall it
/// should be placed here.
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.td
b/llvm/include/llvm/IR/RuntimeLibcalls.td
index d9ee8ff6839b3..d584a2c1196f7 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.td
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.td
@@ -15,6 +15,9 @@ include "llvm/IR/RuntimeLibcallsImpl.td"
class DuplicateLibcallImplWithPrefix
: RuntimeLibcallImpl;
+/// Libcall Predicates
+def isOSWindows : RuntimeLibcallPredicate<"TT.isOSWindows()">;
+
//
// Declare all kinds of used libcalls
//
@@ -1243,6 +1246,7 @@ def __aeabi_memclr4 : RuntimeLibcallImpl;
def __aeabi_memclr8 : RuntimeLibcallImpl;
// isTargetWindows()
+defset list WindowsFPIntCastLibcalls = {
def __stoi64 : RuntimeLibcallImpl; //
CallingConv::ARM_AAPCS_VFP
def __dtoi64 : RuntimeLibcallImpl; //
CallingConv::ARM_AAPCS_VFP
def __stou64 : RuntimeLibcallImpl; //
CallingConv::ARM_AAPCS_VFP
@@ -1251,6 +1255,7 @@ def __i64tos : RuntimeLibcallImpl; //
CallingConv::ARM_AAPCS_V
def __i64tod : RuntimeLibcallImpl; //
CallingConv::ARM_AAPCS_VFP
def __u64tos : RuntimeLibcallImpl; //
CallingConv::ARM_AAPCS_VFP
def __u64tod : RuntimeLibcallImpl; //
CallingConv::ARM_AAPCS_VFP
+}
def __rt_sdiv : RuntimeLibcallImpl; // CallingConv::ARM_AAPCS
def __rt_sdiv64 : RuntimeLibcallImpl; // CallingConv::ARM_AAPCS
@@ -1277,6 +1282,49 @@ def __aeabi_h2f : RuntimeLibcallImpl; //
CallingConv::ARM_AAPCS
def __gnu_f2h_ieee : RuntimeLibcallImpl;
def __gnu_h2f_ieee : RuntimeLibcallImpl;
+
+def WindowARMDivRemCalls : LibcallImpls<
+ (add __rt_sdiv, __rt_sdiv64, __rt_udiv, __rt_udiv64),
+ isOSWindows> {
+ let CallingConv = ARM_AAPCS;
+}
+
+def WindowARMFPIntCasts : LibcallImpls<
+ (add WindowsFPIntCastLibcalls),
+ isOSWindows> {
+ let CallingConv = ARM_AAPCS_VFP;
+}
+
+
+// Register based DivRem for AEABI (RTABI 4.2)
+def AEABIDivRemCalls : LibcallImpls<
+ (add __aeabi_idivmod, __aeabi_ldivmod,
+ __aeabi_uidivmod, __aeabi_uldivmod),
+ RuntimeLibcallPredicate<[{TT.isTargetAEABI() || TT.isAndroid() ||
TT.isTargetGNUAEABI() ||
+TT.isTargetMuslAEABI()}]>> {
+ let CallingConv = ARM_AAPCS;
+}
+
+def isARMOrThumb : RuntimeLibcallPredicate<"TT.isARM() || TT.isThumb()">;
+
+def ARMSystemLibrary
+: SystemRuntimeLibrary>)> {
+ let DefaultLibcallCallingConv = LibcallCallingConv<[{
+ (!TT.isOSDarwin() && !TT.isiOS() && !TT.isWatchOS() && !TT.isDriverKit())
?
+(FloatABI == FloatABI::Hard ? CallingConv::ARM_AAPCS_VFP
+: CallingConv::ARM_AAPCS) :
+ CallingConv::C
+ }]>;
+}
+
//===--===//
// AVR Runtime Libcalls
//===--===//
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index 9f24e9d1fc4b1..46b4acde922e2 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -25,80 +25,6 @@ static cl::opt
static void setARMLibcallNames(RuntimeLibcallsInfo &Info, const Triple &TT,
FloatABI::ABIType FloatABIType,
EABI EABIVersion) {
- if (!TT.isOSDarwin() && !TT.isiOS() && !TT.isWatchOS() && !TT.isDriverKit())
{
-CallingConv::ID DefaultCC = FloatABIType == FloatABI::Hard
-? CallingConv::ARM_AAPCS_VFP
-: CallingConv::ARM_AAPCS;
-for (RTLIB::LibcallImpl LC : RTLIB::libcall_impls())
- Info.setLibcallImplCallingConv(LC, DefaultCC);
- }
-
-
[llvm-branch-commits] [llvm] MSP430: Move libcall CC setting to RuntimeLibcallsInfo (PR #146081)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/146081
>From 78df65066d4209ace408942be82107681bd135ec Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 16:35:14 +0900
Subject: [PATCH] MSP430: Move libcall CC setting to RuntimeLibcallsInfo
As a temporary step configure the calling convention here. This
can't be moved into tablegen until RuntimeLibcallsInfo is split
into a separate lowering component.
---
llvm/lib/IR/RuntimeLibcalls.cpp | 5 +
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp | 2 --
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index 6f1f7014249c7..a5605329c7d28 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -365,6 +365,11 @@ void RuntimeLibcallsInfo::initLibcalls(const Triple &TT,
RTLIB::HEXAGON_MEMCPY_LIKELY_ALIGNED_MIN32BYTES_MULT8BYTES,
RTLIB::__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes);
}
+
+ if (TT.getArch() == Triple::ArchType::msp430) {
+setLibcallImplCallingConv(RTLIB::__mspabi_mpyll,
+ CallingConv::MSP430_BUILTIN);
+ }
}
bool RuntimeLibcallsInfo::darwinHasExp10(const Triple &TT) {
diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
index d558dd253dc46..0d7c7b5c7a813 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -208,8 +208,6 @@ MSP430TargetLowering::MSP430TargetLowering(const
TargetMachine &TM,
for (const auto &LC : LibraryCalls) {
setLibcallImpl(LC.Op, LC.Impl);
}
-setLibcallImplCallingConv(RTLIB::__mspabi_mpyll,
- CallingConv::MSP430_BUILTIN);
}
setMinFunctionAlignment(Align(2));
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[llvm-branch-commits] [llvm] TableGen: Handle setting runtime libcall calling conventions (PR #144980)
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/144980 >From 370182a91bbee541956ff153044a82ca929846cd Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 13 Jun 2025 15:54:41 +0900 Subject: [PATCH] TableGen: Handle setting runtime libcall calling conventions Allow associating a non-default CallingConv with a set of library functions, and applying a default for a SystemLibrary. I also wanted to be able to apply a default calling conv to a RuntimeLibcallImpl, but that turned out to be annoying so leave it for later. --- llvm/include/llvm/IR/RuntimeLibcalls.td | 140 +-- llvm/include/llvm/IR/RuntimeLibcallsImpl.td | 27 ++- llvm/lib/IR/RuntimeLibcalls.cpp | 141 --- .../RuntimeLibcallEmitter-calling-conv.td | 128 ++ llvm/test/TableGen/RuntimeLibcallEmitter.td | 19 +- .../TableGen/Basic/RuntimeLibcallsEmitter.cpp | 163 ++ 6 files changed, 429 insertions(+), 189 deletions(-) create mode 100644 llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.td b/llvm/include/llvm/IR/RuntimeLibcalls.td index 82e9d27959391..d7a1ef1cf524f 100644 --- a/llvm/include/llvm/IR/RuntimeLibcalls.td +++ b/llvm/include/llvm/IR/RuntimeLibcalls.td @@ -1282,11 +1282,12 @@ def __gnu_h2f_ieee : RuntimeLibcallImpl; //===--===// // Several of the runtime library functions use a special calling conv -def __divmodqi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN -def __divmodhi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN +def __divmodqi4 : RuntimeLibcallImpl; +def __divmodhi4 : RuntimeLibcallImpl; +def __udivmodqi4 : RuntimeLibcallImpl; +def __udivmodhi4 : RuntimeLibcallImpl; + //def __divmodsi4 : RuntimeLibcallImpl; -def __udivmodqi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN -def __udivmodhi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN //def __udivmodsi4 : RuntimeLibcallImpl; // Standard sinf/cosf name replaced with "sin" and "cos". Define a @@ -1312,9 +1313,12 @@ def AVRSystemLibrary // Standard f64 names are replaced sin, cos, sinf, cosf), - __divmodqi4, __divmodhi4, __divmodsi4, __udivmodqi4, __udivmodhi4, - __udivmodsi4, - + // Several of the runtime library functions use a special calling + // conv + LibcallsWithCC<(add __divmodqi4, __divmodhi4, __udivmodqi4, + __udivmodhi4), + AVR_BUILTIN>, + __divmodsi4, __udivmodsi4, // Trigonometric rtlib functions avr_sin, avr_cos)>; @@ -1537,6 +1541,117 @@ def __mspabi_mpyll : RuntimeLibcallImpl; // setLibcallCallingConv(MUL_I64, CallingConv::MSP430_BUILTIN); +def isMSP430 : RuntimeLibcallPredicate<"TT.getArch() == Triple::msp430">; + +defvar MSP430DefaultOptOut = [ + __addsf3, __divsf3, __extendsfdf2, __truncdfsf2, __fixsfsi, + __fixsfdi, __fixunssfsi, __mulsf3, __eqsf2, __gesf2, __gtsf2, + __divhi3, __divsi3, __ashlsi3, __floatsidf, __floatsisf, + __ashrsi3, __modhi3, __udivsi3, __fixdfsi, __fixunssfdi, + __udivhi3, __umodsi3, __nesf2, __lesf2, __floatundisf, + __fixdfdi, __fixunsdfsi, __modsi3, __floatunsisf, + __fixunsdfdi, __ltsf2, __floatdisf, __floatdidf, + __lshrsi3, __subsf3, __umodhi3, __floatunsidf, + __floatundidf +]; + +// EABI Libcalls - EABI Section 6.2 +def MSP430SystemLibrary +: SystemRuntimeLibrary, + __mspabi_cmpf__oeq, + __mspabi_cmpf__une, + __mspabi_cmpf__oge, + __mspabi_cmpf__olt, + __mspabi_cmpf__ole, + __mspabi_cmpf__ogt, + + // Floating point arithmetic - EABI Table 8 + LibcallsWithCC<(add __mspabi_addd, + __mspabi_subd, + __mspabi_mpyd, + __mspabi_divd), MSP430_BUILTIN>, + + __mspabi_addf, + __mspabi_subf, + __mspabi_mpyf, + __mspabi_divf, + + // The following are NOT implemented in libgcc + // __mspabi_negd, + // __mspabi_negf, + + // Universal Integer Operations - EABI Table 9 + __mspabi_divi, + __mspabi_divli, + LibcallsWithCC<(add __mspabi_divlli), MSP430_BUILTIN>, + __mspabi_divu, + __mspabi_divul, + LibcallsWithCC<(add __mspabi_divull), MSP430_BUILTIN>, + __mspabi_remi, + __mspabi_remli, + LibcallsWithCC<(add __mspabi_remlli), MSP430_BUILTIN>, + __mspabi_remu, + __mspabi_remul, + LibcallsWithCC<(add __mspabi_remull), MSP430_BUILTIN>, + + // Bitwise Operations - EABI Table 10 + // TODO: __mspabi_[srli/srai/slli] ARE implemented in libgcc + __mspabi_srll, + __mspabi_sral, + __mspabi_slll + // __mspabi_[srlll/srall/s/rlli/rlll] are NOT implemented in libgcc + ) +>; + //===--===// // NVPTX Runtime Libcalls //===---
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (PR #145912)
@@ -57,6 +57,224 @@ void
RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
lower(MI, Mapping, WaterfallSgprs);
}
+bool RegBankLegalizeHelper::executeInWaterfallLoop(
+MachineIRBuilder &B, iterator_range Range,
+SmallSet &SGPROperandRegs) {
+ // Track use registers which have already been expanded with a readfirstlane
+ // sequence. This may have multiple uses if moving a sequence.
+ DenseMap WaterfalledRegMap;
+
+ MachineBasicBlock &MBB = B.getMBB();
+ MachineFunction &MF = B.getMF();
+
+ const SIRegisterInfo *TRI = ST.getRegisterInfo();
+ const TargetRegisterClass *WaveRC = TRI->getWaveMaskRegClass();
+ unsigned MovExecOpc, MovExecTermOpc, XorTermOpc, AndSaveExecOpc, ExecReg;
+ if (IsWave32) {
Pierre-vh wrote:
I know I already asked but I lost track of it; why can't we put those as fields
in the class?
https://github.com/llvm/llvm-project/pull/145912
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[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Add waterfall lowering in regbanklegalize (PR #145912)
@@ -188,7 +188,11 @@ enum RegBankLLTMappingApplyID {
Sgpr32Trunc,
- // Src only modifiers: waterfalls, extends
+ // Src only modifiers: execute in waterfall loop if divergent
+ Sgpr32_W,
Pierre-vh wrote:
nit: use a suffix like `_WF` for WaterFall?
I keep thinking this is meant to say "wide" for some reason; maybe it's just me
https://github.com/llvm/llvm-project/pull/145912
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[llvm-branch-commits] [llvm] [DAG] Fold (setcc ((x | x >> c0 | ...) & mask)) sequences (PR #146054)
@@ -28909,13 +28909,97 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc
&DL, SDValue N0, SDValue N1,
return SDValue();
}
+static SDValue matchMergedBFX(SDValue Root, SelectionDAG &DAG,
+ const TargetLowering &TLI) {
+ // Match a pattern such as:
+ // (X | (X >> C0) | (X >> C1) | ...) & Mask
+ // This extracts contiguous parts of X and ORs them together before
comparing.
+ // We can optimize this so that we directly check (X & SomeMask) instead,
+ // eliminating the shifts.
+
+ EVT VT = Root.getValueType();
+
+ if (Root.getOpcode() != ISD::AND)
+return SDValue();
+
+ SDValue N0 = Root.getOperand(0);
+ SDValue N1 = Root.getOperand(1);
+
+ if (N0.getOpcode() != ISD::OR || !isa(N1))
+return SDValue();
+
+ APInt RootMask = cast(N1)->getAsAPIntVal();
+ if (!RootMask.isMask())
+return SDValue();
+
+ SDValue Src;
+ const auto IsSrc = [&](SDValue V) {
+if (!Src) {
+ Src = V;
+ return true;
+}
+
+return Src == V;
+ };
+
+ SmallVector Worklist = {N0};
+ APInt PartsMask(VT.getSizeInBits(), 0);
+ while (!Worklist.empty()) {
+SDValue V = Worklist.pop_back_val();
+if (!V.hasOneUse() && Src != V)
+ return SDValue();
+
+if (V.getOpcode() == ISD::OR) {
+ Worklist.push_back(V.getOperand(0));
+ Worklist.push_back(V.getOperand(1));
+ continue;
+}
+
+if (V.getOpcode() == ISD::SRL) {
+ SDValue ShiftSrc = V.getOperand(0);
+ SDValue ShiftAmt = V.getOperand(1);
+
+ if (!IsSrc(ShiftSrc) || !isa(ShiftAmt))
+return SDValue();
+
+ PartsMask |= (RootMask <<
cast(ShiftAmt)->getAsZExtVal());
jayfoad wrote:
Probably need to protect against out of range shift amounts causing an
assertion failure here.
https://github.com/llvm/llvm-project/pull/146054
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[llvm-branch-commits] [llvm] [DAG] Fold (setcc ((x | x >> c0 | ...) & mask)) sequences (PR #146054)
@@ -28909,13 +28909,97 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc
&DL, SDValue N0, SDValue N1,
return SDValue();
}
+static SDValue matchMergedBFX(SDValue Root, SelectionDAG &DAG,
+ const TargetLowering &TLI) {
+ // Match a pattern such as:
+ // (X | (X >> C0) | (X >> C1) | ...) & Mask
+ // This extracts contiguous parts of X and ORs them together before
comparing.
+ // We can optimize this so that we directly check (X & SomeMask) instead,
+ // eliminating the shifts.
+
+ EVT VT = Root.getValueType();
+
+ if (Root.getOpcode() != ISD::AND)
+return SDValue();
+
+ SDValue N0 = Root.getOperand(0);
+ SDValue N1 = Root.getOperand(1);
+
+ if (N0.getOpcode() != ISD::OR || !isa(N1))
+return SDValue();
+
+ APInt RootMask = cast(N1)->getAsAPIntVal();
+ if (!RootMask.isMask())
+return SDValue();
+
+ SDValue Src;
+ const auto IsSrc = [&](SDValue V) {
+if (!Src) {
+ Src = V;
+ return true;
+}
+
+return Src == V;
+ };
+
+ SmallVector Worklist = {N0};
+ APInt PartsMask(VT.getSizeInBits(), 0);
+ while (!Worklist.empty()) {
+SDValue V = Worklist.pop_back_val();
+if (!V.hasOneUse() && Src != V)
+ return SDValue();
+
+if (V.getOpcode() == ISD::OR) {
+ Worklist.push_back(V.getOperand(0));
+ Worklist.push_back(V.getOperand(1));
+ continue;
+}
+
+if (V.getOpcode() == ISD::SRL) {
+ SDValue ShiftSrc = V.getOperand(0);
+ SDValue ShiftAmt = V.getOperand(1);
+
+ if (!IsSrc(ShiftSrc) || !isa(ShiftAmt))
+return SDValue();
+
+ PartsMask |= (RootMask <<
cast(ShiftAmt)->getAsZExtVal());
+ continue;
+}
+
+if (IsSrc(V)) {
+ PartsMask |= RootMask;
+ continue;
+}
+
+return SDValue();
+ }
+
+ if (!RootMask.isMask() || !Src)
jayfoad wrote:
You checked isMask before.
https://github.com/llvm/llvm-project/pull/146054
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[llvm-branch-commits] [llvm] [DAG] Fold (setcc ((x | x >> c0 | ...) & mask)) sequences (PR #146054)
@@ -28909,13 +28909,97 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc
&DL, SDValue N0, SDValue N1,
return SDValue();
}
+static SDValue matchMergedBFX(SDValue Root, SelectionDAG &DAG,
+ const TargetLowering &TLI) {
+ // Match a pattern such as:
+ // (X | (X >> C0) | (X >> C1) | ...) & Mask
+ // This extracts contiguous parts of X and ORs them together before
comparing.
+ // We can optimize this so that we directly check (X & SomeMask) instead,
+ // eliminating the shifts.
+
+ EVT VT = Root.getValueType();
+
+ if (Root.getOpcode() != ISD::AND)
+return SDValue();
+
+ SDValue N0 = Root.getOperand(0);
+ SDValue N1 = Root.getOperand(1);
+
+ if (N0.getOpcode() != ISD::OR || !isa(N1))
+return SDValue();
+
+ APInt RootMask = cast(N1)->getAsAPIntVal();
+ if (!RootMask.isMask())
+return SDValue();
+
+ SDValue Src;
+ const auto IsSrc = [&](SDValue V) {
+if (!Src) {
+ Src = V;
+ return true;
+}
+
+return Src == V;
+ };
+
+ SmallVector Worklist = {N0};
+ APInt PartsMask(VT.getSizeInBits(), 0);
+ while (!Worklist.empty()) {
+SDValue V = Worklist.pop_back_val();
+if (!V.hasOneUse() && Src != V)
jayfoad wrote:
It feels to me like this should also check `Src != nullptr`. I think perhaps
you're getting away without it, because od the order in which nodes are added
to the worklist.
https://github.com/llvm/llvm-project/pull/146054
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[llvm-branch-commits] [llvm] [DAG] Fold (setcc ((x | x >> c0 | ...) & mask)) sequences (PR #146054)
@@ -28909,13 +28909,97 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc
&DL, SDValue N0, SDValue N1,
return SDValue();
}
+static SDValue matchMergedBFX(SDValue Root, SelectionDAG &DAG,
+ const TargetLowering &TLI) {
+ // Match a pattern such as:
+ // (X | (X >> C0) | (X >> C1) | ...) & Mask
+ // This extracts contiguous parts of X and ORs them together before
comparing.
+ // We can optimize this so that we directly check (X & SomeMask) instead,
+ // eliminating the shifts.
+
+ EVT VT = Root.getValueType();
+
+ if (Root.getOpcode() != ISD::AND)
+return SDValue();
+
+ SDValue N0 = Root.getOperand(0);
+ SDValue N1 = Root.getOperand(1);
+
+ if (N0.getOpcode() != ISD::OR || !isa(N1))
+return SDValue();
+
+ APInt RootMask = cast(N1)->getAsAPIntVal();
+ if (!RootMask.isMask())
jayfoad wrote:
You don't need this check. The optimization still works for any RootMask values.
https://github.com/llvm/llvm-project/pull/146054
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[llvm-branch-commits] [llvm] [DAG] Fold (setcc ((x | x >> c0 | ...) & mask)) sequences (PR #146054)
@@ -28909,13 +28909,97 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc
&DL, SDValue N0, SDValue N1,
return SDValue();
}
+static SDValue matchMergedBFX(SDValue Root, SelectionDAG &DAG,
+ const TargetLowering &TLI) {
+ // Match a pattern such as:
+ // (X | (X >> C0) | (X >> C1) | ...) & Mask
+ // This extracts contiguous parts of X and ORs them together before
comparing.
+ // We can optimize this so that we directly check (X & SomeMask) instead,
+ // eliminating the shifts.
+
+ EVT VT = Root.getValueType();
jayfoad wrote:
Do you need to explicitly reject vector types here. (Or can this be made to
work on vector types?)
https://github.com/llvm/llvm-project/pull/146054
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[llvm-branch-commits] [llvm] [AMDGPU] Add tests for workgroup/workitem intrinsic optimizations (PR #146053)
https://github.com/jayfoad approved this pull request. LGTM with nits https://github.com/llvm/llvm-project/pull/146053 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Add tests for workgroup/workitem intrinsic optimizations (PR #146053)
https://github.com/jayfoad edited https://github.com/llvm/llvm-project/pull/146053 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Add tests for workgroup/workitem intrinsic optimizations (PR #146053)
@@ -0,0 +1,553 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 jayfoad wrote: Nit: I think "workitem-intrinsic-opts" sounds better https://github.com/llvm/llvm-project/pull/146053 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Add tests for workgroup/workitem intrinsic optimizations (PR #146053)
@@ -0,0 +1,553 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -O3 -mtriple=amdgcn -mcpu=fiji %s -o - | FileCheck %s --check-prefixes=GFX8,DAGISEL-GFX9 jayfoad wrote: ```suggestion ; RUN: llc -O3 -mtriple=amdgcn -mcpu=fiji %s -o - | FileCheck %s --check-prefixes=GFX8,DAGISEL-GFX8 ``` https://github.com/llvm/llvm-project/pull/146053 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] RuntimeLibcalls: Remove table of soft float compare cond codes (PR #146082)
https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/146082 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [flang][fir] Small clean-up in `fir_DoConcurrentLoopOp`'s defintion (PR #146028)
https://github.com/ergawy edited https://github.com/llvm/llvm-project/pull/146028 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [NFC][flang] Move `ReductionProcessor` to `Lower/Support`. (PR #146025)
https://github.com/ergawy edited https://github.com/llvm/llvm-project/pull/146025 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [flang][OpenMP] Basic mapping of `do concurrent ... reduce` to OpenMP (PR #146033)
https://github.com/ergawy edited https://github.com/llvm/llvm-project/pull/146033 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] ARM: Unconditionally set eabi libcall calling convs in RuntimeLibcalls (PR #146083)
llvmbot wrote:
@llvm/pr-subscribers-llvm-ir
Author: Matt Arsenault (arsenm)
Changes
This fully consolidates all the calling convention configuration into
RuntimeLibcallInfo. I'm assuming that __aeabi functions have a universal
calling convention, and on other ABIs just don't use them. This will
enable splitting of RuntimeLibcallInfo into the ABI and lowering component.
---
Full diff: https://github.com/llvm/llvm-project/pull/146083.diff
2 Files Affected:
- (modified) llvm/lib/IR/RuntimeLibcalls.cpp (+39)
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+71-88)
``diff
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index b08ee16791dfd..9f24e9d1fc4b1 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -98,6 +98,45 @@ static void setARMLibcallNames(RuntimeLibcallsInfo &Info,
const Triple &TT,
Info.setLibcallImpl(RTLIB::SDIVREM_I32, RTLIB::__divmodsi4);
Info.setLibcallImpl(RTLIB::UDIVREM_I32, RTLIB::__udivmodsi4);
}
+
+ static const RTLIB::LibcallImpl AAPCS_Libcalls[] = {
+ RTLIB::__aeabi_dadd, RTLIB::__aeabi_ddiv,
+ RTLIB::__aeabi_dmul, RTLIB::__aeabi_dsub,
+ RTLIB::__aeabi_dcmpeq__ne, RTLIB::__aeabi_dcmpeq__eq,
+ RTLIB::__aeabi_dcmplt, RTLIB::__aeabi_dcmple,
+ RTLIB::__aeabi_dcmpge, RTLIB::__aeabi_dcmpgt,
+ RTLIB::__aeabi_dcmpun, RTLIB::__aeabi_fadd,
+ RTLIB::__aeabi_fdiv, RTLIB::__aeabi_fmul,
+ RTLIB::__aeabi_fsub, RTLIB::__aeabi_fcmpeq__ne,
+ RTLIB::__aeabi_fcmpeq__eq, RTLIB::__aeabi_fcmplt,
+ RTLIB::__aeabi_fcmple, RTLIB::__aeabi_fcmpge,
+ RTLIB::__aeabi_fcmpgt, RTLIB::__aeabi_fcmpun,
+ RTLIB::__aeabi_d2iz, RTLIB::__aeabi_d2uiz,
+ RTLIB::__aeabi_d2lz, RTLIB::__aeabi_d2ulz,
+ RTLIB::__aeabi_f2iz, RTLIB::__aeabi_f2uiz,
+ RTLIB::__aeabi_f2lz, RTLIB::__aeabi_f2ulz,
+ RTLIB::__aeabi_d2f,RTLIB::__aeabi_d2h,
+ RTLIB::__aeabi_f2d,RTLIB::__aeabi_i2d,
+ RTLIB::__aeabi_ui2d, RTLIB::__aeabi_l2d,
+ RTLIB::__aeabi_ul2d, RTLIB::__aeabi_i2f,
+ RTLIB::__aeabi_ui2f, RTLIB::__aeabi_l2f,
+ RTLIB::__aeabi_ul2f, RTLIB::__aeabi_lmul,
+ RTLIB::__aeabi_llsl, RTLIB::__aeabi_llsr,
+ RTLIB::__aeabi_lasr, RTLIB::__aeabi_idiv__i8,
+ RTLIB::__aeabi_idiv__i16, RTLIB::__aeabi_idiv__i32,
+ RTLIB::__aeabi_ldivmod,RTLIB::__aeabi_uidiv__i8,
+ RTLIB::__aeabi_uidiv__i16, RTLIB::__aeabi_uidiv__i32,
+ RTLIB::__aeabi_uldivmod, RTLIB::__aeabi_f2h,
+ RTLIB::__aeabi_d2h,RTLIB::__aeabi_h2f,
+ RTLIB::__aeabi_memcpy, RTLIB::__aeabi_memmove,
+ RTLIB::__aeabi_memset, RTLIB::__aeabi_memcpy4,
+ RTLIB::__aeabi_memcpy8,RTLIB::__aeabi_memmove4,
+ RTLIB::__aeabi_memmove8, RTLIB::__aeabi_memset4,
+ RTLIB::__aeabi_memset8,RTLIB::__aeabi_memclr,
+ RTLIB::__aeabi_memclr4,RTLIB::__aeabi_memclr8};
+
+ for (RTLIB::LibcallImpl Impl : AAPCS_Libcalls)
+Info.setLibcallImplCallingConv(Impl, CallingConv::ARM_AAPCS);
}
static void setLongDoubleIsF128Libm(RuntimeLibcallsInfo &Info,
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp
b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 78ef3c23e8423..2ece698df264b 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -578,9 +578,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
};
// clang-format on
- for (const auto &LC : LibraryCalls) {
+ for (const auto &LC : LibraryCalls)
setLibcallImpl(LC.Op, LC.Impl);
- }
}
}
@@ -594,94 +593,91 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
static const struct {
const RTLIB::Libcall Op;
const RTLIB::LibcallImpl Impl;
- const CallingConv::ID CC;
} LibraryCalls[] = {
// Double-precision floating-point arithmetic helper functions
// RTABI chapter 4.1.2, Table 2
- { RTLIB::ADD_F64, RTLIB::__aeabi_dadd, CallingConv::ARM_AAPCS },
- { RTLIB::DIV_F64, RTLIB::__aeabi_ddiv, CallingConv::ARM_AAPCS },
- { RTLIB::MUL_F64, RTLIB::__aeabi_dmul, CallingConv::ARM_AAPCS },
- { RTLIB::SUB_F64, RTLIB::__aeabi_dsub, CallingConv::ARM_AAPCS },
+ { RTLIB::ADD_F64, RTLIB::__aeabi_dadd },
+ { RTLIB::DIV_F64, RTLIB::__aeabi_ddiv },
+ { RTLIB::MUL_F64, RTLIB::__aeabi_dmul },
+ { RTLIB::SUB_F64, RTLIB::__aeabi_dsub },
// Double-precision floating-point comparison helper functions
// RTABI chapter 4.1.2, Table 3
- { RTLIB::OEQ_F64, RTLIB::__aeabi_dcmpeq__ne, CallingConv::ARM_AAPCS },
- { RTLIB::UNE_F64, RTLIB::__aeabi_dcmpeq__eq, CallingConv::ARM_AAPCS },
- { RTLIB::OLT_F64, RTLIB::__aeabi_dcmplt, CallingConv::ARM_AAPCS },
- { RTLIB::OLE_F64, RTLIB::__aeabi_dcmple, CallingConv::ARM_AAPCS },
- { RTLIB::OGE_F64, RTLIB::__aeabi_
[llvm-branch-commits] [llvm] ARM: Unconditionally set eabi libcall calling convs in RuntimeLibcalls (PR #146083)
arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146083?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#146084** https://app.graphite.dev/github/pr/llvm/llvm-project/146084?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#146083** https://app.graphite.dev/github/pr/llvm/llvm-project/146083?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/146083?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#146082** https://app.graphite.dev/github/pr/llvm/llvm-project/146082?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#146081** https://app.graphite.dev/github/pr/llvm/llvm-project/146081?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#146080** https://app.graphite.dev/github/pr/llvm/llvm-project/146080?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144980** https://app.graphite.dev/github/pr/llvm/llvm-project/144980?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144979** https://app.graphite.dev/github/pr/llvm/llvm-project/144979?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144978** https://app.graphite.dev/github/pr/llvm/llvm-project/144978?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144977** https://app.graphite.dev/github/pr/llvm/llvm-project/144977?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144976** https://app.graphite.dev/github/pr/llvm/llvm-project/144976?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144975** https://app.graphite.dev/github/pr/llvm/llvm-project/144975?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144974** https://app.graphite.dev/github/pr/llvm/llvm-project/144974?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144973** https://app.graphite.dev/github/pr/llvm/llvm-project/144973?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144972** https://app.graphite.dev/github/pr/llvm/llvm-project/144972?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#143836** https://app.graphite.dev/github/pr/llvm/llvm-project/143836?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/146083 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] TableGen: Handle setting runtime libcall calling conventions (PR #144980)
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/144980 >From eaca2334fb46cc6a706876cd1738fe73b11db5ee Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 13 Jun 2025 15:54:41 +0900 Subject: [PATCH] TableGen: Handle setting runtime libcall calling conventions Allow associating a non-default CallingConv with a set of library functions, and applying a default for a SystemLibrary. I also wanted to be able to apply a default calling conv to a RuntimeLibcallImpl, but that turned out to be annoying so leave it for later. --- llvm/include/llvm/IR/RuntimeLibcalls.td | 140 +-- llvm/include/llvm/IR/RuntimeLibcallsImpl.td | 27 ++- llvm/lib/IR/RuntimeLibcalls.cpp | 141 --- .../RuntimeLibcallEmitter-calling-conv.td | 128 ++ llvm/test/TableGen/RuntimeLibcallEmitter.td | 19 +- .../TableGen/Basic/RuntimeLibcallsEmitter.cpp | 165 ++ 6 files changed, 429 insertions(+), 191 deletions(-) create mode 100644 llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.td b/llvm/include/llvm/IR/RuntimeLibcalls.td index 61031140e105e..59e9481201de4 100644 --- a/llvm/include/llvm/IR/RuntimeLibcalls.td +++ b/llvm/include/llvm/IR/RuntimeLibcalls.td @@ -1282,11 +1282,12 @@ def __gnu_h2f_ieee : RuntimeLibcallImpl; //===--===// // Several of the runtime library functions use a special calling conv -def __divmodqi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN -def __divmodhi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN +def __divmodqi4 : RuntimeLibcallImpl; +def __divmodhi4 : RuntimeLibcallImpl; +def __udivmodqi4 : RuntimeLibcallImpl; +def __udivmodhi4 : RuntimeLibcallImpl; + //def __divmodsi4 : RuntimeLibcallImpl; -def __udivmodqi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN -def __udivmodhi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN //def __udivmodsi4 : RuntimeLibcallImpl; // Standard sinf/cosf name replaced with "sin" and "cos". Define a @@ -1312,9 +1313,12 @@ def AVRSystemLibrary // Standard f64 names are replaced sin, cos, sinf, cosf), - __divmodqi4, __divmodhi4, __divmodsi4, __udivmodqi4, __udivmodhi4, - __udivmodsi4, - + // Several of the runtime library functions use a special calling + // conv + LibcallsWithCC<(add __divmodqi4, __divmodhi4, __udivmodqi4, + __udivmodhi4), + AVR_BUILTIN>, + __divmodsi4, __udivmodsi4, // Trigonometric rtlib functions avr_sin, avr_cos)>; @@ -1537,6 +1541,117 @@ def __mspabi_mpyll : RuntimeLibcallImpl; // setLibcallCallingConv(MUL_I64, CallingConv::MSP430_BUILTIN); +def isMSP430 : RuntimeLibcallPredicate<"TT.getArch() == Triple::msp430">; + +defvar MSP430DefaultOptOut = [ + __addsf3, __divsf3, __extendsfdf2, __truncdfsf2, __fixsfsi, + __fixsfdi, __fixunssfsi, __mulsf3, __eqsf2, __gesf2, __gtsf2, + __divhi3, __divsi3, __ashlsi3, __floatsidf, __floatsisf, + __ashrsi3, __modhi3, __udivsi3, __fixdfsi, __fixunssfdi, + __udivhi3, __umodsi3, __nesf2, __lesf2, __floatundisf, + __fixdfdi, __fixunsdfsi, __modsi3, __floatunsisf, + __fixunsdfdi, __ltsf2, __floatdisf, __floatdidf, + __lshrsi3, __subsf3, __umodhi3, __floatunsidf, + __floatundidf +]; + +// EABI Libcalls - EABI Section 6.2 +def MSP430SystemLibrary +: SystemRuntimeLibrary, + __mspabi_cmpf__oeq, + __mspabi_cmpf__une, + __mspabi_cmpf__oge, + __mspabi_cmpf__olt, + __mspabi_cmpf__ole, + __mspabi_cmpf__ogt, + + // Floating point arithmetic - EABI Table 8 + LibcallsWithCC<(add __mspabi_addd, + __mspabi_subd, + __mspabi_mpyd, + __mspabi_divd), MSP430_BUILTIN>, + + __mspabi_addf, + __mspabi_subf, + __mspabi_mpyf, + __mspabi_divf, + + // The following are NOT implemented in libgcc + // __mspabi_negd, + // __mspabi_negf, + + // Universal Integer Operations - EABI Table 9 + __mspabi_divi, + __mspabi_divli, + LibcallsWithCC<(add __mspabi_divlli), MSP430_BUILTIN>, + __mspabi_divu, + __mspabi_divul, + LibcallsWithCC<(add __mspabi_divull), MSP430_BUILTIN>, + __mspabi_remi, + __mspabi_remli, + LibcallsWithCC<(add __mspabi_remlli), MSP430_BUILTIN>, + __mspabi_remu, + __mspabi_remul, + LibcallsWithCC<(add __mspabi_remull), MSP430_BUILTIN>, + + // Bitwise Operations - EABI Table 10 + // TODO: __mspabi_[srli/srai/slli] ARE implemented in libgcc + __mspabi_srll, + __mspabi_sral, + __mspabi_slll + // __mspabi_[srlll/srall/s/rlli/rlll] are NOT implemented in libgcc + ) +>; + //===--===// // NVPTX Runtime Libcalls //===---
[llvm-branch-commits] [llvm] RuntimeLibcalls: Associate calling convention with libcall impls (PR #144979)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144979
>From 60fa20112d54cf42958f6e22187402a1b0dd73d3 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 17 Jun 2025 16:25:50 +0900
Subject: [PATCH] RuntimeLibcalls: Associate calling convention with libcall
impls
Instead of associating the libcall with the RTLIB::Libcall, put it
into a table indexed by the RTLIB::LibcallImpl. The LibcallImpls
should contain all ABI details for a particular implementation, not
the abstract Libcall. In the future the wrappers in terms of the
RTLIB::Libcall should be removed.
---
llvm/include/llvm/CodeGen/TargetLowering.h| 16 -
llvm/include/llvm/IR/RuntimeLibcalls.h| 32 ++---
llvm/lib/IR/RuntimeLibcalls.cpp | 70 +++
llvm/lib/Target/ARM/ARMISelLowering.cpp | 18 ++---
llvm/lib/Target/Lanai/LanaiISelLowering.cpp | 4 +-
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp | 3 +-
6 files changed, 92 insertions(+), 51 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h
b/llvm/include/llvm/CodeGen/TargetLowering.h
index 84c53e1e45452..8e05c53dc513d 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -3562,6 +3562,11 @@ class LLVM_ABI TargetLoweringBase {
Libcalls.setLibcallImpl(Call, Impl);
}
+ /// Get the libcall impl routine name for the specified libcall.
+ RTLIB::LibcallImpl getLibcallImpl(RTLIB::Libcall Call) const {
+return Libcalls.getLibcallImpl(Call);
+ }
+
/// Get the libcall routine name for the specified libcall.
const char *getLibcallName(RTLIB::Libcall Call) const {
return Libcalls.getLibcallName(Call);
@@ -3584,11 +3589,18 @@ class LLVM_ABI TargetLoweringBase {
}
/// Set the CallingConv that should be used for the specified libcall.
- void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
-Libcalls.setLibcallCallingConv(Call, CC);
+ void setLibcallImplCallingConv(RTLIB::LibcallImpl Call, CallingConv::ID CC) {
+Libcalls.setLibcallImplCallingConv(Call, CC);
+ }
+
+ /// Get the CallingConv that should be used for the specified libcall
+ /// implementation.
+ CallingConv::ID getLibcallImplCallingConv(RTLIB::LibcallImpl Call) const {
+return Libcalls.getLibcallImplCallingConv(Call);
}
/// Get the CallingConv that should be used for the specified libcall.
+ // FIXME: Remove this wrapper and directly use the used LibcallImpl
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
return Libcalls.getLibcallCallingConv(Call);
}
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.h
b/llvm/include/llvm/IR/RuntimeLibcalls.h
index 811a9893abde2..8c11ce9ed2920 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.h
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.h
@@ -37,6 +37,10 @@ template <> struct enum_iteration_traits {
static constexpr bool is_iterable = true;
};
+template <> struct enum_iteration_traits {
+ static constexpr bool is_iterable = true;
+};
+
namespace RTLIB {
// Return an iterator over all Libcall values.
@@ -44,6 +48,10 @@ static inline auto libcalls() {
return enum_seq(static_cast(0), RTLIB::UNKNOWN_LIBCALL);
}
+static inline auto libcall_impls() {
+ return enum_seq(static_cast(1), RTLIB::NumLibcallImpls);
+}
+
/// A simple container for information about the supported runtime calls.
struct RuntimeLibcallsInfo {
explicit RuntimeLibcallsInfo(
@@ -76,16 +84,21 @@ struct RuntimeLibcallsInfo {
return LibcallImpls[Call];
}
- /// Set the CallingConv that should be used for the specified libcall.
- // FIXME: This should be a function of RTLIB::LibcallImpl
- void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
-LibcallCallingConvs[Call] = CC;
+ /// Set the CallingConv that should be used for the specified libcall
+ /// implementation
+ void setLibcallImplCallingConv(RTLIB::LibcallImpl Call, CallingConv::ID CC) {
+LibcallImplCallingConvs[Call] = CC;
}
- /// Get the CallingConv that should be used for the specified libcall.
- // FIXME: This should be a function of RTLIB::LibcallImpl
+ // FIXME: Remove this wrapper in favor of directly using
+ // getLibcallImplCallingConv
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
-return LibcallCallingConvs[Call];
+return LibcallImplCallingConvs[LibcallImpls[Call]];
+ }
+
+ /// Get the CallingConv that should be used for the specified libcall.
+ CallingConv::ID getLibcallImplCallingConv(RTLIB::LibcallImpl Call) const {
+return LibcallImplCallingConvs[Call];
}
ArrayRef getLibcallImpls() const {
@@ -130,8 +143,9 @@ struct RuntimeLibcallsInfo {
static_assert(static_cast(CallingConv::C) == 0,
"default calling conv should be encoded as 0");
- /// Stores the CallingConv that should be used for each libcall.
- CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL] = {};
+ /// Stores th
[llvm-branch-commits] [llvm] RuntimeLibcalls: Associate calling convention with libcall impls (PR #144979)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144979
>From 60fa20112d54cf42958f6e22187402a1b0dd73d3 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 17 Jun 2025 16:25:50 +0900
Subject: [PATCH] RuntimeLibcalls: Associate calling convention with libcall
impls
Instead of associating the libcall with the RTLIB::Libcall, put it
into a table indexed by the RTLIB::LibcallImpl. The LibcallImpls
should contain all ABI details for a particular implementation, not
the abstract Libcall. In the future the wrappers in terms of the
RTLIB::Libcall should be removed.
---
llvm/include/llvm/CodeGen/TargetLowering.h| 16 -
llvm/include/llvm/IR/RuntimeLibcalls.h| 32 ++---
llvm/lib/IR/RuntimeLibcalls.cpp | 70 +++
llvm/lib/Target/ARM/ARMISelLowering.cpp | 18 ++---
llvm/lib/Target/Lanai/LanaiISelLowering.cpp | 4 +-
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp | 3 +-
6 files changed, 92 insertions(+), 51 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h
b/llvm/include/llvm/CodeGen/TargetLowering.h
index 84c53e1e45452..8e05c53dc513d 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -3562,6 +3562,11 @@ class LLVM_ABI TargetLoweringBase {
Libcalls.setLibcallImpl(Call, Impl);
}
+ /// Get the libcall impl routine name for the specified libcall.
+ RTLIB::LibcallImpl getLibcallImpl(RTLIB::Libcall Call) const {
+return Libcalls.getLibcallImpl(Call);
+ }
+
/// Get the libcall routine name for the specified libcall.
const char *getLibcallName(RTLIB::Libcall Call) const {
return Libcalls.getLibcallName(Call);
@@ -3584,11 +3589,18 @@ class LLVM_ABI TargetLoweringBase {
}
/// Set the CallingConv that should be used for the specified libcall.
- void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
-Libcalls.setLibcallCallingConv(Call, CC);
+ void setLibcallImplCallingConv(RTLIB::LibcallImpl Call, CallingConv::ID CC) {
+Libcalls.setLibcallImplCallingConv(Call, CC);
+ }
+
+ /// Get the CallingConv that should be used for the specified libcall
+ /// implementation.
+ CallingConv::ID getLibcallImplCallingConv(RTLIB::LibcallImpl Call) const {
+return Libcalls.getLibcallImplCallingConv(Call);
}
/// Get the CallingConv that should be used for the specified libcall.
+ // FIXME: Remove this wrapper and directly use the used LibcallImpl
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
return Libcalls.getLibcallCallingConv(Call);
}
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.h
b/llvm/include/llvm/IR/RuntimeLibcalls.h
index 811a9893abde2..8c11ce9ed2920 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.h
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.h
@@ -37,6 +37,10 @@ template <> struct enum_iteration_traits {
static constexpr bool is_iterable = true;
};
+template <> struct enum_iteration_traits {
+ static constexpr bool is_iterable = true;
+};
+
namespace RTLIB {
// Return an iterator over all Libcall values.
@@ -44,6 +48,10 @@ static inline auto libcalls() {
return enum_seq(static_cast(0), RTLIB::UNKNOWN_LIBCALL);
}
+static inline auto libcall_impls() {
+ return enum_seq(static_cast(1), RTLIB::NumLibcallImpls);
+}
+
/// A simple container for information about the supported runtime calls.
struct RuntimeLibcallsInfo {
explicit RuntimeLibcallsInfo(
@@ -76,16 +84,21 @@ struct RuntimeLibcallsInfo {
return LibcallImpls[Call];
}
- /// Set the CallingConv that should be used for the specified libcall.
- // FIXME: This should be a function of RTLIB::LibcallImpl
- void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
-LibcallCallingConvs[Call] = CC;
+ /// Set the CallingConv that should be used for the specified libcall
+ /// implementation
+ void setLibcallImplCallingConv(RTLIB::LibcallImpl Call, CallingConv::ID CC) {
+LibcallImplCallingConvs[Call] = CC;
}
- /// Get the CallingConv that should be used for the specified libcall.
- // FIXME: This should be a function of RTLIB::LibcallImpl
+ // FIXME: Remove this wrapper in favor of directly using
+ // getLibcallImplCallingConv
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
-return LibcallCallingConvs[Call];
+return LibcallImplCallingConvs[LibcallImpls[Call]];
+ }
+
+ /// Get the CallingConv that should be used for the specified libcall.
+ CallingConv::ID getLibcallImplCallingConv(RTLIB::LibcallImpl Call) const {
+return LibcallImplCallingConvs[Call];
}
ArrayRef getLibcallImpls() const {
@@ -130,8 +143,9 @@ struct RuntimeLibcallsInfo {
static_assert(static_cast(CallingConv::C) == 0,
"default calling conv should be encoded as 0");
- /// Stores the CallingConv that should be used for each libcall.
- CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL] = {};
+ /// Stores th
[llvm-branch-commits] [llvm] Lanai: Use TableGen to set libcall calling conventions (PR #146080)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/146080
None
>From 9cbb4db6b98fdb15ef00770df2068a2f73484a2f Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 16:17:26 +0900
Subject: [PATCH] Lanai: Use TableGen to set libcall calling conventions
---
llvm/include/llvm/IR/RuntimeLibcalls.td | 12
llvm/lib/Target/Lanai/LanaiISelLowering.cpp | 4
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.td
b/llvm/include/llvm/IR/RuntimeLibcalls.td
index 59e9481201de4..396dc45240412 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.td
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.td
@@ -1360,6 +1360,18 @@ def __hexagon_fast2_sqrtdf2 :
RuntimeLibcallImpl;
def __hexagon_memcpy_likely_aligned_min32bytes_mult8bytes
: RuntimeLibcallImpl;
+//===--===//
+// Lanai Runtime Libcalls
+//===--===//
+
+def isLanai : RuntimeLibcallPredicate<"TT.getArch() == Triple::lanai">;
+
+// Use fast calling convention for library functions.
+def LanaiSystemLibrary
+: SystemRuntimeLibrary {
+ let DefaultLibcallCallingConv = FASTCC;
+}
+
//===--===//
// Mips16 Runtime Libcalls
//===--===//
diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
index ec668ebaeab0d..272c7bc1a8db6 100644
--- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
+++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
@@ -150,10 +150,6 @@ LanaiTargetLowering::LanaiTargetLowering(const
TargetMachine &TM,
// statements. Re-evaluate this on new benchmarks.
setMinimumJumpTableEntries(100);
- // Use fast calling convention for library functions.
- for (RTLIB::LibcallImpl LC : RTLIB::libcall_impls())
-setLibcallImplCallingConv(LC, CallingConv::Fast);
-
MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
MaxStoresPerMemsetOptSize = 8;
MaxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
___
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[llvm-branch-commits] [llvm] RuntimeLibcalls: Remove table of soft float compare cond codes (PR #146082)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/146082
Previously we had a table of entries for every Libcall for
the comparison to use against an integer 0 if it was a soft
float compare function. This was only relevant to a handful of
opcodes, so it was wasteful. Now that we can distinguish the
abstract libcall for the compare with the concrete implementation,
we can just directly hardcode the comparison against the libcall
impl without this configuration system.
>From a26bf5a90570903f88ca47e392850f0816801364 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 19:10:30 +0900
Subject: [PATCH] RuntimeLibcalls: Remove table of soft float compare cond
codes
Previously we had a table of entries for every Libcall for
the comparison to use against an integer 0 if it was a soft
float compare function. This was only relevant to a handful of
opcodes, so it was wasteful. Now that we can distinguish the
abstract libcall for the compare with the concrete implementation,
we can just directly hardcode the comparison against the libcall
impl without this configuration system.
---
.../include/llvm/CodeGen/RuntimeLibcallUtil.h | 3 -
llvm/include/llvm/CodeGen/TargetLowering.h| 17 +-
llvm/include/llvm/IR/RuntimeLibcalls.h| 32 +---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 16 +-
llvm/lib/CodeGen/TargetLoweringBase.cpp | 107 +++
llvm/lib/IR/RuntimeLibcalls.cpp | 31 ---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 176 +-
7 files changed, 182 insertions(+), 200 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
b/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
index 7481ed5b80b3f..09a8151e9ec9c 100644
--- a/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
+++ b/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
@@ -105,9 +105,6 @@ LLVM_ABI Libcall
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize);
/// UNKNOW_LIBCALL if there is none.
LLVM_ABI Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize);
-/// Initialize the default condition code on the libcalls.
-LLVM_ABI void initCmpLibcallCCs(ISD::CondCode *CmpLibcallCCs);
-
} // namespace RTLIB
} // namespace llvm
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h
b/llvm/include/llvm/CodeGen/TargetLowering.h
index 8e05c53dc513d..31bd0887e1b14 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -3574,19 +3574,10 @@ class LLVM_ABI TargetLoweringBase {
const char *getMemcpyName() const { return Libcalls.getMemcpyName(); }
- /// Override the default CondCode to be used to test the result of the
- /// comparison libcall against zero.
- /// FIXME: This should be removed
- void setCmpLibcallCC(RTLIB::Libcall Call, CmpInst::Predicate Pred) {
-Libcalls.setSoftFloatCmpLibcallPredicate(Call, Pred);
- }
-
- /// Get the CondCode that's to be used to test the result of the comparison
- /// libcall against zero.
- CmpInst::Predicate
- getSoftFloatCmpLibcallPredicate(RTLIB::Libcall Call) const {
-return Libcalls.getSoftFloatCmpLibcallPredicate(Call);
- }
+ /// Get the comparison predicate that's to be used to test the result of the
+ /// comparison libcall against zero. This should only be used with
+ /// floating-point compare libcalls.
+ ISD::CondCode getSoftFloatCmpLibcallPredicate(RTLIB::LibcallImpl Call) const;
/// Set the CallingConv that should be used for the specified libcall.
void setLibcallImplCallingConv(RTLIB::LibcallImpl Call, CallingConv::ID CC) {
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.h
b/llvm/include/llvm/IR/RuntimeLibcalls.h
index 8c11ce9ed2920..ecf20cbfd09f2 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.h
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.h
@@ -59,7 +59,6 @@ struct RuntimeLibcallsInfo {
ExceptionHandling ExceptionModel = ExceptionHandling::None,
FloatABI::ABIType FloatABI = FloatABI::Default,
EABI EABIVersion = EABI::Default, StringRef ABIName = "") {
-initSoftFloatCmpLibcallPredicates();
initLibcalls(TT, ExceptionModel, FloatABI, EABIVersion, ABIName);
}
@@ -106,22 +105,6 @@ struct RuntimeLibcallsInfo {
return ArrayRef(LibcallImpls).drop_front();
}
- /// Get the comparison predicate that's to be used to test the result of the
- /// comparison libcall against zero. This should only be used with
- /// floating-point compare libcalls.
- // FIXME: This should be a function of RTLIB::LibcallImpl
- CmpInst::Predicate
- getSoftFloatCmpLibcallPredicate(RTLIB::Libcall Call) const {
-return SoftFloatCompareLibcallPredicates[Call];
- }
-
- // FIXME: This should be removed. This should be private constant.
- // FIXME: This should be a function of RTLIB::LibcallImpl
- void setSoftFloatCmpLibcallPredicate(RTLIB::Libcall Call,
- CmpInst::Predicate Pred) {
-SoftFloatCompareLibcallPredicates[Call] = P
[llvm-branch-commits] [llvm] TableGen: Handle setting runtime libcall calling conventions (PR #144980)
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/144980 >From eaca2334fb46cc6a706876cd1738fe73b11db5ee Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 13 Jun 2025 15:54:41 +0900 Subject: [PATCH] TableGen: Handle setting runtime libcall calling conventions Allow associating a non-default CallingConv with a set of library functions, and applying a default for a SystemLibrary. I also wanted to be able to apply a default calling conv to a RuntimeLibcallImpl, but that turned out to be annoying so leave it for later. --- llvm/include/llvm/IR/RuntimeLibcalls.td | 140 +-- llvm/include/llvm/IR/RuntimeLibcallsImpl.td | 27 ++- llvm/lib/IR/RuntimeLibcalls.cpp | 141 --- .../RuntimeLibcallEmitter-calling-conv.td | 128 ++ llvm/test/TableGen/RuntimeLibcallEmitter.td | 19 +- .../TableGen/Basic/RuntimeLibcallsEmitter.cpp | 165 ++ 6 files changed, 429 insertions(+), 191 deletions(-) create mode 100644 llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.td b/llvm/include/llvm/IR/RuntimeLibcalls.td index 61031140e105e..59e9481201de4 100644 --- a/llvm/include/llvm/IR/RuntimeLibcalls.td +++ b/llvm/include/llvm/IR/RuntimeLibcalls.td @@ -1282,11 +1282,12 @@ def __gnu_h2f_ieee : RuntimeLibcallImpl; //===--===// // Several of the runtime library functions use a special calling conv -def __divmodqi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN -def __divmodhi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN +def __divmodqi4 : RuntimeLibcallImpl; +def __divmodhi4 : RuntimeLibcallImpl; +def __udivmodqi4 : RuntimeLibcallImpl; +def __udivmodhi4 : RuntimeLibcallImpl; + //def __divmodsi4 : RuntimeLibcallImpl; -def __udivmodqi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN -def __udivmodhi4 : RuntimeLibcallImpl; // CallingConv::AVR_BUILTIN //def __udivmodsi4 : RuntimeLibcallImpl; // Standard sinf/cosf name replaced with "sin" and "cos". Define a @@ -1312,9 +1313,12 @@ def AVRSystemLibrary // Standard f64 names are replaced sin, cos, sinf, cosf), - __divmodqi4, __divmodhi4, __divmodsi4, __udivmodqi4, __udivmodhi4, - __udivmodsi4, - + // Several of the runtime library functions use a special calling + // conv + LibcallsWithCC<(add __divmodqi4, __divmodhi4, __udivmodqi4, + __udivmodhi4), + AVR_BUILTIN>, + __divmodsi4, __udivmodsi4, // Trigonometric rtlib functions avr_sin, avr_cos)>; @@ -1537,6 +1541,117 @@ def __mspabi_mpyll : RuntimeLibcallImpl; // setLibcallCallingConv(MUL_I64, CallingConv::MSP430_BUILTIN); +def isMSP430 : RuntimeLibcallPredicate<"TT.getArch() == Triple::msp430">; + +defvar MSP430DefaultOptOut = [ + __addsf3, __divsf3, __extendsfdf2, __truncdfsf2, __fixsfsi, + __fixsfdi, __fixunssfsi, __mulsf3, __eqsf2, __gesf2, __gtsf2, + __divhi3, __divsi3, __ashlsi3, __floatsidf, __floatsisf, + __ashrsi3, __modhi3, __udivsi3, __fixdfsi, __fixunssfdi, + __udivhi3, __umodsi3, __nesf2, __lesf2, __floatundisf, + __fixdfdi, __fixunsdfsi, __modsi3, __floatunsisf, + __fixunsdfdi, __ltsf2, __floatdisf, __floatdidf, + __lshrsi3, __subsf3, __umodhi3, __floatunsidf, + __floatundidf +]; + +// EABI Libcalls - EABI Section 6.2 +def MSP430SystemLibrary +: SystemRuntimeLibrary, + __mspabi_cmpf__oeq, + __mspabi_cmpf__une, + __mspabi_cmpf__oge, + __mspabi_cmpf__olt, + __mspabi_cmpf__ole, + __mspabi_cmpf__ogt, + + // Floating point arithmetic - EABI Table 8 + LibcallsWithCC<(add __mspabi_addd, + __mspabi_subd, + __mspabi_mpyd, + __mspabi_divd), MSP430_BUILTIN>, + + __mspabi_addf, + __mspabi_subf, + __mspabi_mpyf, + __mspabi_divf, + + // The following are NOT implemented in libgcc + // __mspabi_negd, + // __mspabi_negf, + + // Universal Integer Operations - EABI Table 9 + __mspabi_divi, + __mspabi_divli, + LibcallsWithCC<(add __mspabi_divlli), MSP430_BUILTIN>, + __mspabi_divu, + __mspabi_divul, + LibcallsWithCC<(add __mspabi_divull), MSP430_BUILTIN>, + __mspabi_remi, + __mspabi_remli, + LibcallsWithCC<(add __mspabi_remlli), MSP430_BUILTIN>, + __mspabi_remu, + __mspabi_remul, + LibcallsWithCC<(add __mspabi_remull), MSP430_BUILTIN>, + + // Bitwise Operations - EABI Table 10 + // TODO: __mspabi_[srli/srai/slli] ARE implemented in libgcc + __mspabi_srll, + __mspabi_sral, + __mspabi_slll + // __mspabi_[srlll/srall/s/rlli/rlll] are NOT implemented in libgcc + ) +>; + //===--===// // NVPTX Runtime Libcalls //===---
[llvm-branch-commits] [llvm] MSP430: Move libcall CC setting to RuntimeLibcallsInfo (PR #146081)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/146081
As a temporary step configure the calling convention here. This
can't be moved into tablegen until RuntimeLibcallsInfo is split
into a separate lowering component.
>From ff47400094d159274353b4322d98cad6e3bf4181 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 16:35:14 +0900
Subject: [PATCH] MSP430: Move libcall CC setting to RuntimeLibcallsInfo
As a temporary step configure the calling convention here. This
can't be moved into tablegen until RuntimeLibcallsInfo is split
into a separate lowering component.
---
llvm/lib/IR/RuntimeLibcalls.cpp | 5 +
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp | 2 --
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index 6f1f7014249c7..a5605329c7d28 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -365,6 +365,11 @@ void RuntimeLibcallsInfo::initLibcalls(const Triple &TT,
RTLIB::HEXAGON_MEMCPY_LIKELY_ALIGNED_MIN32BYTES_MULT8BYTES,
RTLIB::__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes);
}
+
+ if (TT.getArch() == Triple::ArchType::msp430) {
+setLibcallImplCallingConv(RTLIB::__mspabi_mpyll,
+ CallingConv::MSP430_BUILTIN);
+ }
}
bool RuntimeLibcallsInfo::darwinHasExp10(const Triple &TT) {
diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
index d558dd253dc46..0d7c7b5c7a813 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -208,8 +208,6 @@ MSP430TargetLowering::MSP430TargetLowering(const
TargetMachine &TM,
for (const auto &LC : LibraryCalls) {
setLibcallImpl(LC.Op, LC.Impl);
}
-setLibcallImplCallingConv(RTLIB::__mspabi_mpyll,
- CallingConv::MSP430_BUILTIN);
}
setMinFunctionAlignment(Align(2));
___
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[llvm-branch-commits] [llvm] ARM: Unconditionally set eabi libcall calling convs in RuntimeLibcalls (PR #146083)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/146083
This fully consolidates all the calling convention configuration into
RuntimeLibcallInfo. I'm assuming that __aeabi functions have a universal
calling convention, and on other ABIs just don't use them. This will
enable splitting of RuntimeLibcallInfo into the ABI and lowering component.
>From 77239be520a0f7b226874eeb6922cf43c6b2b873 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 20:14:11 +0900
Subject: [PATCH] ARM: Unconditionally set eabi libcall calling convs in
RuntimeLibcalls
This fully consolidates all the calling convention configuration into
RuntimeLibcallInfo. I'm assuming that __aeabi functions have a universal
calling convention, and on other ABIs just don't use them. This will
enable splitting of RuntimeLibcallInfo into the ABI and lowering component.
---
llvm/lib/IR/RuntimeLibcalls.cpp | 39 ++
llvm/lib/Target/ARM/ARMISelLowering.cpp | 159 +++-
2 files changed, 110 insertions(+), 88 deletions(-)
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index b08ee16791dfd..9f24e9d1fc4b1 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -98,6 +98,45 @@ static void setARMLibcallNames(RuntimeLibcallsInfo &Info,
const Triple &TT,
Info.setLibcallImpl(RTLIB::SDIVREM_I32, RTLIB::__divmodsi4);
Info.setLibcallImpl(RTLIB::UDIVREM_I32, RTLIB::__udivmodsi4);
}
+
+ static const RTLIB::LibcallImpl AAPCS_Libcalls[] = {
+ RTLIB::__aeabi_dadd, RTLIB::__aeabi_ddiv,
+ RTLIB::__aeabi_dmul, RTLIB::__aeabi_dsub,
+ RTLIB::__aeabi_dcmpeq__ne, RTLIB::__aeabi_dcmpeq__eq,
+ RTLIB::__aeabi_dcmplt, RTLIB::__aeabi_dcmple,
+ RTLIB::__aeabi_dcmpge, RTLIB::__aeabi_dcmpgt,
+ RTLIB::__aeabi_dcmpun, RTLIB::__aeabi_fadd,
+ RTLIB::__aeabi_fdiv, RTLIB::__aeabi_fmul,
+ RTLIB::__aeabi_fsub, RTLIB::__aeabi_fcmpeq__ne,
+ RTLIB::__aeabi_fcmpeq__eq, RTLIB::__aeabi_fcmplt,
+ RTLIB::__aeabi_fcmple, RTLIB::__aeabi_fcmpge,
+ RTLIB::__aeabi_fcmpgt, RTLIB::__aeabi_fcmpun,
+ RTLIB::__aeabi_d2iz, RTLIB::__aeabi_d2uiz,
+ RTLIB::__aeabi_d2lz, RTLIB::__aeabi_d2ulz,
+ RTLIB::__aeabi_f2iz, RTLIB::__aeabi_f2uiz,
+ RTLIB::__aeabi_f2lz, RTLIB::__aeabi_f2ulz,
+ RTLIB::__aeabi_d2f,RTLIB::__aeabi_d2h,
+ RTLIB::__aeabi_f2d,RTLIB::__aeabi_i2d,
+ RTLIB::__aeabi_ui2d, RTLIB::__aeabi_l2d,
+ RTLIB::__aeabi_ul2d, RTLIB::__aeabi_i2f,
+ RTLIB::__aeabi_ui2f, RTLIB::__aeabi_l2f,
+ RTLIB::__aeabi_ul2f, RTLIB::__aeabi_lmul,
+ RTLIB::__aeabi_llsl, RTLIB::__aeabi_llsr,
+ RTLIB::__aeabi_lasr, RTLIB::__aeabi_idiv__i8,
+ RTLIB::__aeabi_idiv__i16, RTLIB::__aeabi_idiv__i32,
+ RTLIB::__aeabi_ldivmod,RTLIB::__aeabi_uidiv__i8,
+ RTLIB::__aeabi_uidiv__i16, RTLIB::__aeabi_uidiv__i32,
+ RTLIB::__aeabi_uldivmod, RTLIB::__aeabi_f2h,
+ RTLIB::__aeabi_d2h,RTLIB::__aeabi_h2f,
+ RTLIB::__aeabi_memcpy, RTLIB::__aeabi_memmove,
+ RTLIB::__aeabi_memset, RTLIB::__aeabi_memcpy4,
+ RTLIB::__aeabi_memcpy8,RTLIB::__aeabi_memmove4,
+ RTLIB::__aeabi_memmove8, RTLIB::__aeabi_memset4,
+ RTLIB::__aeabi_memset8,RTLIB::__aeabi_memclr,
+ RTLIB::__aeabi_memclr4,RTLIB::__aeabi_memclr8};
+
+ for (RTLIB::LibcallImpl Impl : AAPCS_Libcalls)
+Info.setLibcallImplCallingConv(Impl, CallingConv::ARM_AAPCS);
}
static void setLongDoubleIsF128Libm(RuntimeLibcallsInfo &Info,
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp
b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 78ef3c23e8423..2ece698df264b 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -578,9 +578,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
};
// clang-format on
- for (const auto &LC : LibraryCalls) {
+ for (const auto &LC : LibraryCalls)
setLibcallImpl(LC.Op, LC.Impl);
- }
}
}
@@ -594,94 +593,91 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine
&TM_,
static const struct {
const RTLIB::Libcall Op;
const RTLIB::LibcallImpl Impl;
- const CallingConv::ID CC;
} LibraryCalls[] = {
// Double-precision floating-point arithmetic helper functions
// RTABI chapter 4.1.2, Table 2
- { RTLIB::ADD_F64, RTLIB::__aeabi_dadd, CallingConv::ARM_AAPCS },
- { RTLIB::DIV_F64, RTLIB::__aeabi_ddiv, CallingConv::ARM_AAPCS },
- { RTLIB::MUL_F64, RTLIB::__aeabi_dmul, CallingConv::ARM_AAPCS },
- { RTLIB::SUB_F64, RTLIB::__aeabi_dsub, CallingConv::ARM_AAPCS },
+ { RTLIB::ADD_F64, RTLIB::__aeabi_dadd },
+ { RTLIB::DIV_F64, RTLIB::__aeabi_ddiv },
+ { RTLIB::MUL_F64, RTLIB::__aeabi_dmul },
+ { RTLIB::SUB_F64, RTLIB::__aeab
[llvm-branch-commits] [llvm] ARM: Start moving runtime libcalls into tablegen (PR #146084)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/146084
We still need to manually set the calling conventions of
some libcalls until the lowering is separated out.
>From 6e102219d860e13b8d8d684ae8330b0cd5f83f0e Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 23:23:01 +0900
Subject: [PATCH] ARM: Start moving runtime libcalls into tablegen
We still need to manually set the calling conventions of
some libcalls until the lowering is separated out.
---
llvm/include/llvm/IR/RuntimeLibcalls.h| 2 +-
llvm/include/llvm/IR/RuntimeLibcalls.td | 48
llvm/lib/IR/RuntimeLibcalls.cpp | 76 +--
.../TableGen/Basic/RuntimeLibcallsEmitter.cpp | 2 +-
4 files changed, 51 insertions(+), 77 deletions(-)
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.h
b/llvm/include/llvm/IR/RuntimeLibcalls.h
index ecf20cbfd09f2..7fb6b503daa22 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.h
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.h
@@ -168,7 +168,7 @@ struct RuntimeLibcallsInfo {
void initDefaultLibCallImpls();
/// Generated by tablegen.
- void setTargetRuntimeLibcallSets(const Triple &TT);
+ void setTargetRuntimeLibcallSets(const Triple &TT, FloatABI::ABIType
FloatABI);
/// Set default libcall names. If a target wants to opt-out of a libcall it
/// should be placed here.
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.td
b/llvm/include/llvm/IR/RuntimeLibcalls.td
index 396dc45240412..ac9f258e39ad2 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.td
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.td
@@ -15,6 +15,9 @@ include "llvm/IR/RuntimeLibcallsImpl.td"
class DuplicateLibcallImplWithPrefix
: RuntimeLibcallImpl;
+/// Libcall Predicates
+def isOSWindows : RuntimeLibcallPredicate<"TT.isOSWindows()">;
+
//
// Declare all kinds of used libcalls
//
@@ -1243,6 +1246,7 @@ def __aeabi_memclr4 : RuntimeLibcallImpl;
def __aeabi_memclr8 : RuntimeLibcallImpl;
// isTargetWindows()
+defset list WindowsFPIntCastLibcalls = {
def __stoi64 : RuntimeLibcallImpl; //
CallingConv::ARM_AAPCS_VFP
def __dtoi64 : RuntimeLibcallImpl; //
CallingConv::ARM_AAPCS_VFP
def __stou64 : RuntimeLibcallImpl; //
CallingConv::ARM_AAPCS_VFP
@@ -1251,6 +1255,7 @@ def __i64tos : RuntimeLibcallImpl; //
CallingConv::ARM_AAPCS_V
def __i64tod : RuntimeLibcallImpl; //
CallingConv::ARM_AAPCS_VFP
def __u64tos : RuntimeLibcallImpl; //
CallingConv::ARM_AAPCS_VFP
def __u64tod : RuntimeLibcallImpl; //
CallingConv::ARM_AAPCS_VFP
+}
def __rt_sdiv : RuntimeLibcallImpl; // CallingConv::ARM_AAPCS
def __rt_sdiv64 : RuntimeLibcallImpl; // CallingConv::ARM_AAPCS
@@ -1277,6 +1282,49 @@ def __aeabi_h2f : RuntimeLibcallImpl; //
CallingConv::ARM_AAPCS
def __gnu_f2h_ieee : RuntimeLibcallImpl;
def __gnu_h2f_ieee : RuntimeLibcallImpl;
+
+def WindowARMDivRemCalls : LibcallImpls<
+ (add __rt_sdiv, __rt_sdiv64, __rt_udiv, __rt_udiv64),
+ isOSWindows> {
+ let CallingConv = ARM_AAPCS;
+}
+
+def WindowARMFPIntCasts : LibcallImpls<
+ (add WindowsFPIntCastLibcalls),
+ isOSWindows> {
+ let CallingConv = ARM_AAPCS_VFP;
+}
+
+
+// Register based DivRem for AEABI (RTABI 4.2)
+def AEABIDivRemCalls : LibcallImpls<
+ (add __aeabi_idivmod, __aeabi_ldivmod,
+ __aeabi_uidivmod, __aeabi_uldivmod),
+ RuntimeLibcallPredicate<[{TT.isTargetAEABI() || TT.isAndroid() ||
TT.isTargetGNUAEABI() ||
+TT.isTargetMuslAEABI()}]>> {
+ let CallingConv = ARM_AAPCS;
+}
+
+def isARMOrThumb : RuntimeLibcallPredicate<"TT.isARM() || TT.isThumb()">;
+
+def ARMSystemLibrary
+: SystemRuntimeLibrary>)> {
+ let DefaultLibcallCallingConv = LibcallCallingConv<[{
+ (!TT.isOSDarwin() && !TT.isiOS() && !TT.isWatchOS() && !TT.isDriverKit())
?
+(FloatABI == FloatABI::Hard ? CallingConv::ARM_AAPCS_VFP
+: CallingConv::ARM_AAPCS) :
+ CallingConv::C
+ }]>;
+}
+
//===--===//
// AVR Runtime Libcalls
//===--===//
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index 9f24e9d1fc4b1..46b4acde922e2 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -25,80 +25,6 @@ static cl::opt
static void setARMLibcallNames(RuntimeLibcallsInfo &Info, const Triple &TT,
FloatABI::ABIType FloatABIType,
EABI EABIVersion) {
- if (!TT.isOSDarwin() && !TT.isiOS() && !TT.isWatchOS() && !TT.isDriverKit())
{
-CallingConv::ID DefaultCC = FloatABIType == FloatABI::Hard
-? CallingConv::ARM_AAPCS_VFP
-: CallingConv::ARM_AAPCS;
-for (R
[llvm-branch-commits] [llvm] Lanai: Use TableGen to set libcall calling conventions (PR #146080)
arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146080?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#146084** https://app.graphite.dev/github/pr/llvm/llvm-project/146084?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#146083** https://app.graphite.dev/github/pr/llvm/llvm-project/146083?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#146082** https://app.graphite.dev/github/pr/llvm/llvm-project/146082?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#146081** https://app.graphite.dev/github/pr/llvm/llvm-project/146081?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#146080** https://app.graphite.dev/github/pr/llvm/llvm-project/146080?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/146080?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#144980** https://app.graphite.dev/github/pr/llvm/llvm-project/144980?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144979** https://app.graphite.dev/github/pr/llvm/llvm-project/144979?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144978** https://app.graphite.dev/github/pr/llvm/llvm-project/144978?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144977** https://app.graphite.dev/github/pr/llvm/llvm-project/144977?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144976** https://app.graphite.dev/github/pr/llvm/llvm-project/144976?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144975** https://app.graphite.dev/github/pr/llvm/llvm-project/144975?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144974** https://app.graphite.dev/github/pr/llvm/llvm-project/144974?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144973** https://app.graphite.dev/github/pr/llvm/llvm-project/144973?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144972** https://app.graphite.dev/github/pr/llvm/llvm-project/144972?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#143836** https://app.graphite.dev/github/pr/llvm/llvm-project/143836?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/146080 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] RuntimeLibcalls: Remove table of soft float compare cond codes (PR #146082)
arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146082?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#146084** https://app.graphite.dev/github/pr/llvm/llvm-project/146084?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#146083** https://app.graphite.dev/github/pr/llvm/llvm-project/146083?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#146082** https://app.graphite.dev/github/pr/llvm/llvm-project/146082?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/146082?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#146081** https://app.graphite.dev/github/pr/llvm/llvm-project/146081?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#146080** https://app.graphite.dev/github/pr/llvm/llvm-project/146080?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144980** https://app.graphite.dev/github/pr/llvm/llvm-project/144980?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144979** https://app.graphite.dev/github/pr/llvm/llvm-project/144979?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144978** https://app.graphite.dev/github/pr/llvm/llvm-project/144978?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144977** https://app.graphite.dev/github/pr/llvm/llvm-project/144977?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144976** https://app.graphite.dev/github/pr/llvm/llvm-project/144976?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144975** https://app.graphite.dev/github/pr/llvm/llvm-project/144975?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144974** https://app.graphite.dev/github/pr/llvm/llvm-project/144974?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144973** https://app.graphite.dev/github/pr/llvm/llvm-project/144973?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144972** https://app.graphite.dev/github/pr/llvm/llvm-project/144972?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#143836** https://app.graphite.dev/github/pr/llvm/llvm-project/143836?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/146082 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] MSP430: Move libcall CC setting to RuntimeLibcallsInfo (PR #146081)
arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146081?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#146084** https://app.graphite.dev/github/pr/llvm/llvm-project/146084?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#146083** https://app.graphite.dev/github/pr/llvm/llvm-project/146083?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#146082** https://app.graphite.dev/github/pr/llvm/llvm-project/146082?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#146081** https://app.graphite.dev/github/pr/llvm/llvm-project/146081?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/146081?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#146080** https://app.graphite.dev/github/pr/llvm/llvm-project/146080?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144980** https://app.graphite.dev/github/pr/llvm/llvm-project/144980?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144979** https://app.graphite.dev/github/pr/llvm/llvm-project/144979?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144978** https://app.graphite.dev/github/pr/llvm/llvm-project/144978?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144977** https://app.graphite.dev/github/pr/llvm/llvm-project/144977?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144976** https://app.graphite.dev/github/pr/llvm/llvm-project/144976?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144975** https://app.graphite.dev/github/pr/llvm/llvm-project/144975?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144974** https://app.graphite.dev/github/pr/llvm/llvm-project/144974?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144973** https://app.graphite.dev/github/pr/llvm/llvm-project/144973?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144972** https://app.graphite.dev/github/pr/llvm/llvm-project/144972?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#143836** https://app.graphite.dev/github/pr/llvm/llvm-project/143836?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/146081 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] MSP430: Move libcall CC setting to RuntimeLibcallsInfo (PR #146081)
llvmbot wrote:
@llvm/pr-subscribers-tablegen
Author: Matt Arsenault (arsenm)
Changes
As a temporary step configure the calling convention here. This
can't be moved into tablegen until RuntimeLibcallsInfo is split
into a separate lowering component.
---
Full diff: https://github.com/llvm/llvm-project/pull/146081.diff
2 Files Affected:
- (modified) llvm/lib/IR/RuntimeLibcalls.cpp (+5)
- (modified) llvm/lib/Target/MSP430/MSP430ISelLowering.cpp (-2)
``diff
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index 6f1f7014249c7..a5605329c7d28 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -365,6 +365,11 @@ void RuntimeLibcallsInfo::initLibcalls(const Triple &TT,
RTLIB::HEXAGON_MEMCPY_LIKELY_ALIGNED_MIN32BYTES_MULT8BYTES,
RTLIB::__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes);
}
+
+ if (TT.getArch() == Triple::ArchType::msp430) {
+setLibcallImplCallingConv(RTLIB::__mspabi_mpyll,
+ CallingConv::MSP430_BUILTIN);
+ }
}
bool RuntimeLibcallsInfo::darwinHasExp10(const Triple &TT) {
diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
index d558dd253dc46..0d7c7b5c7a813 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -208,8 +208,6 @@ MSP430TargetLowering::MSP430TargetLowering(const
TargetMachine &TM,
for (const auto &LC : LibraryCalls) {
setLibcallImpl(LC.Op, LC.Impl);
}
-setLibcallImplCallingConv(RTLIB::__mspabi_mpyll,
- CallingConv::MSP430_BUILTIN);
}
setMinFunctionAlignment(Align(2));
``
https://github.com/llvm/llvm-project/pull/146081
___
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[llvm-branch-commits] [llvm] Lanai: Use TableGen to set libcall calling conventions (PR #146080)
https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/146080 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [flang][OpenMP] Basic mapping of `do concurrent ... reduce` to OpenMP (PR #146033)
https://github.com/ergawy ready_for_review https://github.com/llvm/llvm-project/pull/146033 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] ARM: Start moving runtime libcalls into tablegen (PR #146084)
arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146084?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#146084** https://app.graphite.dev/github/pr/llvm/llvm-project/146084?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/146084?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#146083** https://app.graphite.dev/github/pr/llvm/llvm-project/146083?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#146082** https://app.graphite.dev/github/pr/llvm/llvm-project/146082?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#146081** https://app.graphite.dev/github/pr/llvm/llvm-project/146081?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#146080** https://app.graphite.dev/github/pr/llvm/llvm-project/146080?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144980** https://app.graphite.dev/github/pr/llvm/llvm-project/144980?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144979** https://app.graphite.dev/github/pr/llvm/llvm-project/144979?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144978** https://app.graphite.dev/github/pr/llvm/llvm-project/144978?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144977** https://app.graphite.dev/github/pr/llvm/llvm-project/144977?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144976** https://app.graphite.dev/github/pr/llvm/llvm-project/144976?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144975** https://app.graphite.dev/github/pr/llvm/llvm-project/144975?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144974** https://app.graphite.dev/github/pr/llvm/llvm-project/144974?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144973** https://app.graphite.dev/github/pr/llvm/llvm-project/144973?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#144972** https://app.graphite.dev/github/pr/llvm/llvm-project/144972?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#143836** https://app.graphite.dev/github/pr/llvm/llvm-project/143836?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/146084 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] RuntimeLibcalls: Remove table of soft float compare cond codes (PR #146082)
llvmbot wrote:
@llvm/pr-subscribers-tablegen
Author: Matt Arsenault (arsenm)
Changes
Previously we had a table of entries for every Libcall for
the comparison to use against an integer 0 if it was a soft
float compare function. This was only relevant to a handful of
opcodes, so it was wasteful. Now that we can distinguish the
abstract libcall for the compare with the concrete implementation,
we can just directly hardcode the comparison against the libcall
impl without this configuration system.
---
Patch is 29.57 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/146082.diff
7 Files Affected:
- (modified) llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h (-3)
- (modified) llvm/include/llvm/CodeGen/TargetLowering.h (+4-13)
- (modified) llvm/include/llvm/IR/RuntimeLibcalls.h (+5-27)
- (modified) llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (+14-2)
- (modified) llvm/lib/CodeGen/TargetLoweringBase.cpp (+74-33)
- (modified) llvm/lib/IR/RuntimeLibcalls.cpp (-31)
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+85-91)
``diff
diff --git a/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
b/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
index 7481ed5b80b3f..09a8151e9ec9c 100644
--- a/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
+++ b/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
@@ -105,9 +105,6 @@ LLVM_ABI Libcall
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize);
/// UNKNOW_LIBCALL if there is none.
LLVM_ABI Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize);
-/// Initialize the default condition code on the libcalls.
-LLVM_ABI void initCmpLibcallCCs(ISD::CondCode *CmpLibcallCCs);
-
} // namespace RTLIB
} // namespace llvm
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h
b/llvm/include/llvm/CodeGen/TargetLowering.h
index 8e05c53dc513d..31bd0887e1b14 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -3574,19 +3574,10 @@ class LLVM_ABI TargetLoweringBase {
const char *getMemcpyName() const { return Libcalls.getMemcpyName(); }
- /// Override the default CondCode to be used to test the result of the
- /// comparison libcall against zero.
- /// FIXME: This should be removed
- void setCmpLibcallCC(RTLIB::Libcall Call, CmpInst::Predicate Pred) {
-Libcalls.setSoftFloatCmpLibcallPredicate(Call, Pred);
- }
-
- /// Get the CondCode that's to be used to test the result of the comparison
- /// libcall against zero.
- CmpInst::Predicate
- getSoftFloatCmpLibcallPredicate(RTLIB::Libcall Call) const {
-return Libcalls.getSoftFloatCmpLibcallPredicate(Call);
- }
+ /// Get the comparison predicate that's to be used to test the result of the
+ /// comparison libcall against zero. This should only be used with
+ /// floating-point compare libcalls.
+ ISD::CondCode getSoftFloatCmpLibcallPredicate(RTLIB::LibcallImpl Call) const;
/// Set the CallingConv that should be used for the specified libcall.
void setLibcallImplCallingConv(RTLIB::LibcallImpl Call, CallingConv::ID CC) {
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.h
b/llvm/include/llvm/IR/RuntimeLibcalls.h
index 8c11ce9ed2920..ecf20cbfd09f2 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.h
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.h
@@ -59,7 +59,6 @@ struct RuntimeLibcallsInfo {
ExceptionHandling ExceptionModel = ExceptionHandling::None,
FloatABI::ABIType FloatABI = FloatABI::Default,
EABI EABIVersion = EABI::Default, StringRef ABIName = "") {
-initSoftFloatCmpLibcallPredicates();
initLibcalls(TT, ExceptionModel, FloatABI, EABIVersion, ABIName);
}
@@ -106,22 +105,6 @@ struct RuntimeLibcallsInfo {
return ArrayRef(LibcallImpls).drop_front();
}
- /// Get the comparison predicate that's to be used to test the result of the
- /// comparison libcall against zero. This should only be used with
- /// floating-point compare libcalls.
- // FIXME: This should be a function of RTLIB::LibcallImpl
- CmpInst::Predicate
- getSoftFloatCmpLibcallPredicate(RTLIB::Libcall Call) const {
-return SoftFloatCompareLibcallPredicates[Call];
- }
-
- // FIXME: This should be removed. This should be private constant.
- // FIXME: This should be a function of RTLIB::LibcallImpl
- void setSoftFloatCmpLibcallPredicate(RTLIB::Libcall Call,
- CmpInst::Predicate Pred) {
-SoftFloatCompareLibcallPredicates[Call] = Pred;
- }
-
/// Return a function name compatible with RTLIB::MEMCPY, or nullptr if fully
/// unsupported.
const char *getMemcpyName() const {
@@ -132,6 +115,11 @@ struct RuntimeLibcallsInfo {
return getLibcallName(RTLIB::MEMMOVE);
}
+ /// Return the libcall provided by \p Impl
+ static RTLIB::Libcall getLibcallFromImpl(RTLIB::LibcallImpl Impl) {
+return ImplToLibcall[Impl];
+ }
+
private:
static const RTLIB::LibcallImpl
DefaultLibcallImpls[RTLIB::UNKNOWN
[llvm-branch-commits] [llvm] RuntimeLibcalls: Remove table of soft float compare cond codes (PR #146082)
llvmbot wrote:
@llvm/pr-subscribers-llvm-ir
Author: Matt Arsenault (arsenm)
Changes
Previously we had a table of entries for every Libcall for
the comparison to use against an integer 0 if it was a soft
float compare function. This was only relevant to a handful of
opcodes, so it was wasteful. Now that we can distinguish the
abstract libcall for the compare with the concrete implementation,
we can just directly hardcode the comparison against the libcall
impl without this configuration system.
---
Patch is 29.57 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/146082.diff
7 Files Affected:
- (modified) llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h (-3)
- (modified) llvm/include/llvm/CodeGen/TargetLowering.h (+4-13)
- (modified) llvm/include/llvm/IR/RuntimeLibcalls.h (+5-27)
- (modified) llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (+14-2)
- (modified) llvm/lib/CodeGen/TargetLoweringBase.cpp (+74-33)
- (modified) llvm/lib/IR/RuntimeLibcalls.cpp (-31)
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+85-91)
``diff
diff --git a/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
b/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
index 7481ed5b80b3f..09a8151e9ec9c 100644
--- a/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
+++ b/llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
@@ -105,9 +105,6 @@ LLVM_ABI Libcall
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize);
/// UNKNOW_LIBCALL if there is none.
LLVM_ABI Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize);
-/// Initialize the default condition code on the libcalls.
-LLVM_ABI void initCmpLibcallCCs(ISD::CondCode *CmpLibcallCCs);
-
} // namespace RTLIB
} // namespace llvm
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h
b/llvm/include/llvm/CodeGen/TargetLowering.h
index 8e05c53dc513d..31bd0887e1b14 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -3574,19 +3574,10 @@ class LLVM_ABI TargetLoweringBase {
const char *getMemcpyName() const { return Libcalls.getMemcpyName(); }
- /// Override the default CondCode to be used to test the result of the
- /// comparison libcall against zero.
- /// FIXME: This should be removed
- void setCmpLibcallCC(RTLIB::Libcall Call, CmpInst::Predicate Pred) {
-Libcalls.setSoftFloatCmpLibcallPredicate(Call, Pred);
- }
-
- /// Get the CondCode that's to be used to test the result of the comparison
- /// libcall against zero.
- CmpInst::Predicate
- getSoftFloatCmpLibcallPredicate(RTLIB::Libcall Call) const {
-return Libcalls.getSoftFloatCmpLibcallPredicate(Call);
- }
+ /// Get the comparison predicate that's to be used to test the result of the
+ /// comparison libcall against zero. This should only be used with
+ /// floating-point compare libcalls.
+ ISD::CondCode getSoftFloatCmpLibcallPredicate(RTLIB::LibcallImpl Call) const;
/// Set the CallingConv that should be used for the specified libcall.
void setLibcallImplCallingConv(RTLIB::LibcallImpl Call, CallingConv::ID CC) {
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.h
b/llvm/include/llvm/IR/RuntimeLibcalls.h
index 8c11ce9ed2920..ecf20cbfd09f2 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.h
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.h
@@ -59,7 +59,6 @@ struct RuntimeLibcallsInfo {
ExceptionHandling ExceptionModel = ExceptionHandling::None,
FloatABI::ABIType FloatABI = FloatABI::Default,
EABI EABIVersion = EABI::Default, StringRef ABIName = "") {
-initSoftFloatCmpLibcallPredicates();
initLibcalls(TT, ExceptionModel, FloatABI, EABIVersion, ABIName);
}
@@ -106,22 +105,6 @@ struct RuntimeLibcallsInfo {
return ArrayRef(LibcallImpls).drop_front();
}
- /// Get the comparison predicate that's to be used to test the result of the
- /// comparison libcall against zero. This should only be used with
- /// floating-point compare libcalls.
- // FIXME: This should be a function of RTLIB::LibcallImpl
- CmpInst::Predicate
- getSoftFloatCmpLibcallPredicate(RTLIB::Libcall Call) const {
-return SoftFloatCompareLibcallPredicates[Call];
- }
-
- // FIXME: This should be removed. This should be private constant.
- // FIXME: This should be a function of RTLIB::LibcallImpl
- void setSoftFloatCmpLibcallPredicate(RTLIB::Libcall Call,
- CmpInst::Predicate Pred) {
-SoftFloatCompareLibcallPredicates[Call] = Pred;
- }
-
/// Return a function name compatible with RTLIB::MEMCPY, or nullptr if fully
/// unsupported.
const char *getMemcpyName() const {
@@ -132,6 +115,11 @@ struct RuntimeLibcallsInfo {
return getLibcallName(RTLIB::MEMMOVE);
}
+ /// Return the libcall provided by \p Impl
+ static RTLIB::Libcall getLibcallFromImpl(RTLIB::LibcallImpl Impl) {
+return ImplToLibcall[Impl];
+ }
+
private:
static const RTLIB::LibcallImpl
DefaultLibcallImpls[RTLIB::UNKNOWN_
[llvm-branch-commits] [llvm] MSP430: Move libcall CC setting to RuntimeLibcallsInfo (PR #146081)
https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/146081 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Lanai: Use TableGen to set libcall calling conventions (PR #146080)
llvmbot wrote:
@llvm/pr-subscribers-llvm-ir
Author: Matt Arsenault (arsenm)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/146080.diff
2 Files Affected:
- (modified) llvm/include/llvm/IR/RuntimeLibcalls.td (+12)
- (modified) llvm/lib/Target/Lanai/LanaiISelLowering.cpp (-4)
``diff
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.td
b/llvm/include/llvm/IR/RuntimeLibcalls.td
index 59e9481201de4..396dc45240412 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.td
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.td
@@ -1360,6 +1360,18 @@ def __hexagon_fast2_sqrtdf2 :
RuntimeLibcallImpl;
def __hexagon_memcpy_likely_aligned_min32bytes_mult8bytes
: RuntimeLibcallImpl;
+//===--===//
+// Lanai Runtime Libcalls
+//===--===//
+
+def isLanai : RuntimeLibcallPredicate<"TT.getArch() == Triple::lanai">;
+
+// Use fast calling convention for library functions.
+def LanaiSystemLibrary
+: SystemRuntimeLibrary {
+ let DefaultLibcallCallingConv = FASTCC;
+}
+
//===--===//
// Mips16 Runtime Libcalls
//===--===//
diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
index ec668ebaeab0d..272c7bc1a8db6 100644
--- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
+++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
@@ -150,10 +150,6 @@ LanaiTargetLowering::LanaiTargetLowering(const
TargetMachine &TM,
// statements. Re-evaluate this on new benchmarks.
setMinimumJumpTableEntries(100);
- // Use fast calling convention for library functions.
- for (RTLIB::LibcallImpl LC : RTLIB::libcall_impls())
-setLibcallImplCallingConv(LC, CallingConv::Fast);
-
MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
MaxStoresPerMemsetOptSize = 8;
MaxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
``
https://github.com/llvm/llvm-project/pull/146080
___
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llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [flang][OpenMP] Basic mapping of `do concurrent ... reduce` to OpenMP (PR #146033)
https://github.com/ergawy updated
https://github.com/llvm/llvm-project/pull/146033
>From c99a5025813a43c6984ad267d38d4d4b6b508ac7 Mon Sep 17 00:00:00 2001
From: ergawy
Date: Fri, 27 Jun 2025 00:58:08 -0500
Subject: [PATCH] [flang][OpenMP] Basic mapping of `do concurrent ... reduce`
to OpenMP
Now that we have changes introduced by #145837, mapping reductions from
`do concurrent` to OpenMP is almost trivial. This PR adds such mapping.
---
.../OpenMP/DoConcurrentConversion.cpp | 83 +--
.../Transforms/DoConcurrent/reduce_add.mlir | 73
.../Transforms/DoConcurrent/reduce_local.mlir | 83 +++
3 files changed, 212 insertions(+), 27 deletions(-)
create mode 100644 flang/test/Transforms/DoConcurrent/reduce_add.mlir
create mode 100644 flang/test/Transforms/DoConcurrent/reduce_local.mlir
diff --git a/flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
b/flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
index 709cf1d0938fa..31076f6eb328f 100644
--- a/flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
+++ b/flang/lib/Optimizer/OpenMP/DoConcurrentConversion.cpp
@@ -312,6 +312,19 @@ class DoConcurrentConversion
bool isComposite) const {
mlir::omp::WsloopOperands wsloopClauseOps;
+auto cloneFIRRegionToOMP = [&rewriter](mlir::Region &firRegion,
+ mlir::Region &ompRegion) {
+ if (!firRegion.empty()) {
+rewriter.cloneRegionBefore(firRegion, ompRegion, ompRegion.begin());
+auto firYield =
+mlir::cast(ompRegion.back().getTerminator());
+rewriter.setInsertionPoint(firYield);
+rewriter.create(firYield.getLoc(),
+firYield.getOperands());
+rewriter.eraseOp(firYield);
+ }
+};
+
// For `local` (and `local_init`) opernads, emit corresponding `private`
// clauses and attach these clauses to the workshare loop.
if (!loop.getLocalVars().empty())
@@ -326,50 +339,65 @@ class DoConcurrentConversion
TODO(localizer.getLoc(),
"local_init conversion is not supported yet");
-auto oldIP = rewriter.saveInsertionPoint();
+mlir::OpBuilder::InsertionGuard guard(rewriter);
rewriter.setInsertionPointAfter(localizer);
+
auto privatizer = rewriter.create(
localizer.getLoc(), sym.getLeafReference().str() + ".omp",
localizer.getTypeAttr().getValue(),
mlir::omp::DataSharingClauseType::Private);
-if (!localizer.getInitRegion().empty()) {
- rewriter.cloneRegionBefore(localizer.getInitRegion(),
- privatizer.getInitRegion(),
- privatizer.getInitRegion().begin());
- auto firYield = mlir::cast(
- privatizer.getInitRegion().back().getTerminator());
- rewriter.setInsertionPoint(firYield);
- rewriter.create(firYield.getLoc(),
- firYield.getOperands());
- rewriter.eraseOp(firYield);
-}
-
-if (!localizer.getDeallocRegion().empty()) {
- rewriter.cloneRegionBefore(localizer.getDeallocRegion(),
- privatizer.getDeallocRegion(),
- privatizer.getDeallocRegion().begin());
- auto firYield = mlir::cast(
- privatizer.getDeallocRegion().back().getTerminator());
- rewriter.setInsertionPoint(firYield);
- rewriter.create(firYield.getLoc(),
- firYield.getOperands());
- rewriter.eraseOp(firYield);
-}
-
-rewriter.restoreInsertionPoint(oldIP);
+cloneFIRRegionToOMP(localizer.getInitRegion(),
+privatizer.getInitRegion());
+cloneFIRRegionToOMP(localizer.getDeallocRegion(),
+privatizer.getDeallocRegion());
wsloopClauseOps.privateVars.push_back(op);
wsloopClauseOps.privateSyms.push_back(
mlir::SymbolRefAttr::get(privatizer));
}
+if (!loop.getReduceVars().empty()) {
+ for (auto [op, byRef, sym, arg] : llvm::zip_equal(
+ loop.getReduceVars(), loop.getReduceByrefAttr().asArrayRef(),
+ loop.getReduceSymsAttr().getAsRange(),
+ loop.getRegionReduceArgs())) {
+auto firReducer =
+
mlir::SymbolTable::lookupNearestSymbolFrom(
+loop, sym);
+
+mlir::OpBuilder::InsertionGuard guard(rewriter);
+rewriter.setInsertionPointAfter(firReducer);
+
+auto ompReducer = rewriter.create(
+firReducer.getLoc(), sym.getLeafReference().str() + ".omp",
+firReducer.getTypeAttr().getValue());
+
+cloneFIRRegionToOMP(firReducer.getAllocRegion(),
+ompReducer.getAllocRegion());
+cloneFI
[llvm-branch-commits] [llvm] ARM: Start moving runtime libcalls into tablegen (PR #146084)
github-actions[bot] wrote: :warning: C/C++ code formatter, clang-format found issues in your code. :warning: You can test this locally with the following command: ``bash git-clang-format --diff HEAD~1 HEAD --extensions h,cpp -- llvm/include/llvm/IR/RuntimeLibcalls.h llvm/lib/IR/RuntimeLibcalls.cpp llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp `` View the diff from clang-format here. ``diff diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.h b/llvm/include/llvm/IR/RuntimeLibcalls.h index 7fb6b503d..562203509 100644 --- a/llvm/include/llvm/IR/RuntimeLibcalls.h +++ b/llvm/include/llvm/IR/RuntimeLibcalls.h @@ -168,7 +168,8 @@ private: void initDefaultLibCallImpls(); /// Generated by tablegen. - void setTargetRuntimeLibcallSets(const Triple &TT, FloatABI::ABIType FloatABI); + void setTargetRuntimeLibcallSets(const Triple &TT, + FloatABI::ABIType FloatABI); /// Set default libcall names. If a target wants to opt-out of a libcall it /// should be placed here. `` https://github.com/llvm/llvm-project/pull/146084 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [NFC][flang] Move `ReductionProcessor` to `Lower/Support`. (PR #146025)
https://github.com/ergawy edited https://github.com/llvm/llvm-project/pull/146025 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Lanai: Use TableGen to set libcall calling conventions (PR #146080)
https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/146080 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] RuntimeLibcalls: Associate calling convention with libcall impls (PR #144979)
https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/144979 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] RuntimeLibcalls: Associate calling convention with libcall impls (PR #144979)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144979
>From 5a8dc27dbdd4be0d14efeeca516376306de87ce0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 17 Jun 2025 16:25:50 +0900
Subject: [PATCH] RuntimeLibcalls: Associate calling convention with libcall
impls
Instead of associating the libcall with the RTLIB::Libcall, put it
into a table indexed by the RTLIB::LibcallImpl. The LibcallImpls
should contain all ABI details for a particular implementation, not
the abstract Libcall. In the future the wrappers in terms of the
RTLIB::Libcall should be removed.
---
llvm/include/llvm/CodeGen/TargetLowering.h| 16 -
llvm/include/llvm/IR/RuntimeLibcalls.h| 32 ++---
llvm/lib/IR/RuntimeLibcalls.cpp | 70 +++
llvm/lib/Target/ARM/ARMISelLowering.cpp | 18 ++---
llvm/lib/Target/Lanai/LanaiISelLowering.cpp | 4 +-
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp | 3 +-
6 files changed, 92 insertions(+), 51 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h
b/llvm/include/llvm/CodeGen/TargetLowering.h
index 84c53e1e45452..8e05c53dc513d 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -3562,6 +3562,11 @@ class LLVM_ABI TargetLoweringBase {
Libcalls.setLibcallImpl(Call, Impl);
}
+ /// Get the libcall impl routine name for the specified libcall.
+ RTLIB::LibcallImpl getLibcallImpl(RTLIB::Libcall Call) const {
+return Libcalls.getLibcallImpl(Call);
+ }
+
/// Get the libcall routine name for the specified libcall.
const char *getLibcallName(RTLIB::Libcall Call) const {
return Libcalls.getLibcallName(Call);
@@ -3584,11 +3589,18 @@ class LLVM_ABI TargetLoweringBase {
}
/// Set the CallingConv that should be used for the specified libcall.
- void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
-Libcalls.setLibcallCallingConv(Call, CC);
+ void setLibcallImplCallingConv(RTLIB::LibcallImpl Call, CallingConv::ID CC) {
+Libcalls.setLibcallImplCallingConv(Call, CC);
+ }
+
+ /// Get the CallingConv that should be used for the specified libcall
+ /// implementation.
+ CallingConv::ID getLibcallImplCallingConv(RTLIB::LibcallImpl Call) const {
+return Libcalls.getLibcallImplCallingConv(Call);
}
/// Get the CallingConv that should be used for the specified libcall.
+ // FIXME: Remove this wrapper and directly use the used LibcallImpl
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
return Libcalls.getLibcallCallingConv(Call);
}
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.h
b/llvm/include/llvm/IR/RuntimeLibcalls.h
index 811a9893abde2..8c11ce9ed2920 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.h
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.h
@@ -37,6 +37,10 @@ template <> struct enum_iteration_traits {
static constexpr bool is_iterable = true;
};
+template <> struct enum_iteration_traits {
+ static constexpr bool is_iterable = true;
+};
+
namespace RTLIB {
// Return an iterator over all Libcall values.
@@ -44,6 +48,10 @@ static inline auto libcalls() {
return enum_seq(static_cast(0), RTLIB::UNKNOWN_LIBCALL);
}
+static inline auto libcall_impls() {
+ return enum_seq(static_cast(1), RTLIB::NumLibcallImpls);
+}
+
/// A simple container for information about the supported runtime calls.
struct RuntimeLibcallsInfo {
explicit RuntimeLibcallsInfo(
@@ -76,16 +84,21 @@ struct RuntimeLibcallsInfo {
return LibcallImpls[Call];
}
- /// Set the CallingConv that should be used for the specified libcall.
- // FIXME: This should be a function of RTLIB::LibcallImpl
- void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
-LibcallCallingConvs[Call] = CC;
+ /// Set the CallingConv that should be used for the specified libcall
+ /// implementation
+ void setLibcallImplCallingConv(RTLIB::LibcallImpl Call, CallingConv::ID CC) {
+LibcallImplCallingConvs[Call] = CC;
}
- /// Get the CallingConv that should be used for the specified libcall.
- // FIXME: This should be a function of RTLIB::LibcallImpl
+ // FIXME: Remove this wrapper in favor of directly using
+ // getLibcallImplCallingConv
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
-return LibcallCallingConvs[Call];
+return LibcallImplCallingConvs[LibcallImpls[Call]];
+ }
+
+ /// Get the CallingConv that should be used for the specified libcall.
+ CallingConv::ID getLibcallImplCallingConv(RTLIB::LibcallImpl Call) const {
+return LibcallImplCallingConvs[Call];
}
ArrayRef getLibcallImpls() const {
@@ -130,8 +143,9 @@ struct RuntimeLibcallsInfo {
static_assert(static_cast(CallingConv::C) == 0,
"default calling conv should be encoded as 0");
- /// Stores the CallingConv that should be used for each libcall.
- CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL] = {};
+ /// Stores th
[llvm-branch-commits] [clang] [clang] Add flag fallow-runtime-check-skip-hot-cutoff (PR #145999)
@@ -2668,6 +2668,16 @@ def fsanitize_skip_hot_cutoff_EQ } // end -f[no-]sanitize* flags +def fallow_runtime_check_skip_hot_cutoff_EQ fmayer wrote: Thanks? https://github.com/llvm/llvm-project/pull/145999 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [clang] Add flag fallow-runtime-check-skip-hot-cutoff (PR #145999)
@@ -2668,6 +2668,16 @@ def fsanitize_skip_hot_cutoff_EQ } // end -f[no-]sanitize* flags +def fallow_runtime_check_skip_hot_cutoff_EQ +: Joined<["-"], "fallow-runtime-check-skip-hot-cutoff=">, fmayer wrote: This is not really about sanitizers though. Also if we want to teach this flag about kind=blah, that would become very messy. https://github.com/llvm/llvm-project/pull/145999 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [NFC][HLSL][RootSignature] Split up `HLSLRootSignatureUtils` (PR #146124)
llvmbot wrote: @llvm/pr-subscribers-clang-codegen Author: Finn Plummer (inbelic) Changes This pr breaks-up `HLSLRootSignatureUtils` into separate orthogonal and meaningful libraries. This prevents it end up as a dumping grounds of many different parts. - Creates a library `RootSignatureMetadata` to contain helper functions for interacting the root signatures in their metadata representation - Create a library `RootSignatureValidations` to contain helper functions that will validation various values of root signatures - Move the serialization of root signature elements to `HLSLRootSignature` Resolves https://github.com/llvm/llvm-project/issues/145946 --- Patch is 45.71 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/146124.diff 13 Files Affected: - (modified) clang/lib/AST/TextNodeDumper.cpp (+1-1) - (modified) clang/lib/CodeGen/CGHLSLRuntime.cpp (+1-1) - (modified) clang/lib/Sema/SemaHLSL.cpp (+1-1) - (modified) llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h (+16) - (added) llvm/include/llvm/Frontend/HLSL/RootSignatureMetadata.h (+56) - (renamed) llvm/include/llvm/Frontend/HLSL/RootSignatureValidations.h (+4-56) - (modified) llvm/lib/Frontend/HLSL/CMakeLists.txt (+3-1) - (added) llvm/lib/Frontend/HLSL/HLSLRootSignature.cpp (+244) - (removed) llvm/lib/Frontend/HLSL/HLSLRootSignatureUtils.cpp (-457) - (added) llvm/lib/Frontend/HLSL/RootSignatureMetadata.cpp (+194) - (added) llvm/lib/Frontend/HLSL/RootSignatureValidations.cpp (+84) - (modified) llvm/unittests/Frontend/HLSLRootSignatureDumpTest.cpp (+1-1) - (modified) llvm/unittests/Frontend/HLSLRootSignatureRangesTest.cpp (+1-1) ``diff diff --git a/clang/lib/AST/TextNodeDumper.cpp b/clang/lib/AST/TextNodeDumper.cpp index bb860a8f76742..9d7c2757d6ee4 100644 --- a/clang/lib/AST/TextNodeDumper.cpp +++ b/clang/lib/AST/TextNodeDumper.cpp @@ -24,7 +24,7 @@ #include "clang/Basic/Specifiers.h" #include "clang/Basic/TypeTraits.h" #include "llvm/ADT/StringExtras.h" -#include "llvm/Frontend/HLSL/HLSLRootSignatureUtils.h" +#include "llvm/Frontend/HLSL/HLSLRootSignature.h" #include #include diff --git a/clang/lib/CodeGen/CGHLSLRuntime.cpp b/clang/lib/CodeGen/CGHLSLRuntime.cpp index f2e992fb7fa69..73843247ce7f2 100644 --- a/clang/lib/CodeGen/CGHLSLRuntime.cpp +++ b/clang/lib/CodeGen/CGHLSLRuntime.cpp @@ -23,7 +23,7 @@ #include "clang/AST/Type.h" #include "clang/Basic/TargetOptions.h" #include "llvm/ADT/SmallVector.h" -#include "llvm/Frontend/HLSL/HLSLRootSignatureUtils.h" +#include "llvm/Frontend/HLSL/RootSignatureMetadata.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/GlobalVariable.h" diff --git a/clang/lib/Sema/SemaHLSL.cpp b/clang/lib/Sema/SemaHLSL.cpp index 3bab0da5edea8..ca66c71370d60 100644 --- a/clang/lib/Sema/SemaHLSL.cpp +++ b/clang/lib/Sema/SemaHLSL.cpp @@ -39,7 +39,7 @@ #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/Twine.h" -#include "llvm/Frontend/HLSL/HLSLRootSignatureUtils.h" +#include "llvm/Frontend/HLSL/RootSignatureValidations.h" #include "llvm/Support/Casting.h" #include "llvm/Support/DXILABI.h" #include "llvm/Support/ErrorHandling.h" diff --git a/llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h b/llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h index f552040ab31cc..f747c8ccaeb18 100644 --- a/llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h +++ b/llvm/include/llvm/Frontend/HLSL/HLSLRootSignature.h @@ -17,6 +17,7 @@ #include "llvm/BinaryFormat/DXContainer.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/DXILABI.h" +#include "llvm/Support/raw_ostream.h" #include #include @@ -135,6 +136,21 @@ using RootElement = std::variant; +/// The following contains the serialization interface for root elements +LLVM_ABI raw_ostream &operator<<(raw_ostream &OS, const dxbc::RootFlags &Flags); +LLVM_ABI raw_ostream &operator<<(raw_ostream &OS, + const RootConstants &Constants); +LLVM_ABI raw_ostream &operator<<(raw_ostream &OS, + const DescriptorTableClause &Clause); +LLVM_ABI raw_ostream &operator<<(raw_ostream &OS, const DescriptorTable &Table); +LLVM_ABI raw_ostream &operator<<(raw_ostream &OS, + const RootDescriptor &Descriptor); +LLVM_ABI raw_ostream &operator<<(raw_ostream &OS, + const StaticSampler &StaticSampler); +LLVM_ABI raw_ostream &operator<<(raw_ostream &OS, const RootElement &Element); + +LLVM_ABI void dumpRootElements(raw_ostream &OS, ArrayRef Elements); + } // namespace rootsig } // namespace hlsl } // namespace llvm diff --git a/llvm/include/llvm/Frontend/HLSL/RootSignatureMetadata.h b/llvm/include/llvm/Frontend/HLSL/RootSignatureMetadata.h new file mode 100644 index 0..c473a7f1e02e5 --- /dev/null +++ b/llvm/include/llvm/Frontend/HLSL/RootSignatureMetadata.h @@ -0,0 +1,56 @@ +//===-
[llvm-branch-commits] [clang] [llvm] [NFC][HLSL][RootSignature] Split up `HLSLRootSignatureUtils` (PR #146124)
https://github.com/inbelic edited https://github.com/llvm/llvm-project/pull/146124 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AArch64: Relax x16/x17 constraint on AUT in certain cases. (PR #132857)
@@ -1951,9 +1952,23 @@ let Predicates = [HasPAuth] in {
let Uses = [X16];
}
+ def AUTxMxN : Pseudo<(outs GPR64:$AuthVal, GPR64common:$Scratch),
+ (ins GPR64:$Val, i32imm:$Key,
+i64imm:$Disc, GPR64:$AddrDisc),
+ []>, Sched<[WriteI, ReadI]> {
+let Constraints = "$AuthVal = $Val";
+let isCodeGenOnly = 1;
+let hasSideEffects = 0;
atrosinenko wrote:
The fix for MachineLICM was sent as #145379.
https://github.com/llvm/llvm-project/pull/132857
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[llvm-branch-commits] [llvm] [SDAG][AMDGPU] Allow opting in to OOB-generating PTRADD transforms (PR #146074)
https://github.com/arichardson approved this pull request. Thanks, I like this hook and it should also work well for CHERI where similar constraints to CPA exist: you can go out of bounds by a specific amount (the exact range depends on the pointer bounds), but if you go too far the pointer becomes invalid. So for CHERI we can just return false from this hook to avoid these problematic transforms. Would like @jrtc27 to take a look as well in case I missed something. https://github.com/llvm/llvm-project/pull/146074 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [flang][fir] Small clean-up in `fir_DoConcurrentLoopOp`'s defintion (PR #146028)
https://github.com/tblah approved this pull request. https://github.com/llvm/llvm-project/pull/146028 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [flang][OpenMP] Basic mapping of `do concurrent ... reduce` to OpenMP (PR #146033)
https://github.com/tblah approved this pull request. LGTM but please could you add a test that covers every region. https://github.com/llvm/llvm-project/pull/146033 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
