[llvm-branch-commits] [clang] [llvm] [PowerPC] Update V18.1.0 release notes (PR #81631)

2024-02-13 Thread Maryam Moghadas via llvm-branch-commits 

https://github.com/maryammo created 
https://github.com/llvm/llvm-project/pull/81631

Adding PowerPC updates for clang and llvm into the V18.1.0 release notes.

>From 627612dff3314b8250542ca951027b8ec8f7ac71 Mon Sep 17 00:00:00 2001
From: Maryam Moghadas 
Date: Mon, 12 Feb 2024 13:35:00 -0600
Subject: [PATCH] [PowerPC] Update V18.1.0 release notes

---
 clang/docs/ReleaseNotes.rst | 26 ++
 llvm/docs/ReleaseNotes.rst  | 37 +
 2 files changed, 63 insertions(+)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 95d44951ae7ee6..22eceea5d265ef 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -304,6 +304,10 @@ Non-comprehensive list of changes in this release
 
 * The version of Unicode used by Clang (primarily to parse identifiers) has 
been updated to 15.1.
 
+* Clang now defines macro ``__LLVM_INSTR_PROFILE_GENERATE`` when compiling with
+  PGO instrumentation profile generation, and ``__LLVM_INSTR_PROFILE_USE`` when
+  compiling with PGO profile use.
+
 New Compiler Flags
 --
 
@@ -344,6 +348,8 @@ New Compiler Flags
   attribute the replaceable global new and delete operators behave normally
   (like other functions) with respect to visibility attributes, pragmas and
   options (e.g ``--fvisibility=``).
+* Full register names can be used when printing assembly via ``-mregnames``.
+  This option now matches the one used by GCC.
 
 Deprecated Compiler Flags
 -
@@ -363,6 +369,7 @@ Modified Compiler Flags
 * ``-fvisibility-global-new-delete-hidden`` is now a deprecated spelling of
   ``-fvisibility-global-new-delete=force-hidden`` 
(``-fvisibility-global-new-delete=``
   is new in this release).
+* ``-fprofile-update`` is enabled for ``-fprofile-generate``.
 
 Removed Compiler Flags
 -
@@ -860,6 +867,9 @@ Bug Fixes in This Version
   Fixes (`#78290 `_)
 - Fixed assertion failure with deleted overloaded unary operators.
   Fixes (`#78314 `_)
+- The XCOFF object file format does not support aliases to symbols having 
common
+  linkage. Clang now diagnoses the use of an alias for a common symbol when
+  compiling for AIX.
 
 - Clang now doesn't produce false-positive warning `-Wconstant-logical-operand`
   for logical operators in C23.
@@ -1261,6 +1271,16 @@ CUDA Support
 - Clang now supports CUDA SDK up to 12.3
 - Added support for sm_90a
 
+PowerPC Support
+^^^
+
+- Added ``nmmintrin.h`` to intrinsics headers.
+- Added ``__builtin_ppc_fence`` as barrier of code motion, and
+  ``__builtin_ppc_mffsl`` for corresponding instruction.
+- Supported ``__attribute__((target("tune=cpu")))``.
+- Emit ``float-abi`` module flag on 64-bit ELFv2 PowerPC targets if
+  ``long double`` type is used in current module.
+
 AIX Support
 ^^^
 
@@ -1269,6 +1289,10 @@ AIX Support
   base is encoded as an immediate operand.
   This access sequence is not used for TLS variables larger than 32KB, and is
   currently only supported on 64-bit mode.
+- Inline assembler supports VSR register in pure digits.
+- Enabled ThinLTO support. Requires AIX 7.2 TL5 SP7 or newer, or AIX 7.3 TL2
+  or newer. Similar to the LTO support on AIX, ThinLTO is implemented with
+  the libLTO.so plugin.
 
 WebAssembly Support
 ^^^
@@ -1332,6 +1356,8 @@ libclang
 - Exposed arguments of ``clang::annotate``.
 - ``clang::getCursorKindForDecl`` now recognizes linkage specifications such as
   ``extern "C"`` and reports them as ``CXCursor_LinkageSpec``.
+- Changed the libclang library on AIX to export only the necessary symbols to
+  prevent issues of resolving to the wrong duplicate symbol.
 
 Static Analyzer
 ---
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 82f4a7a15c9c13..16acbb965c5c94 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -163,6 +163,30 @@ Changes to the MIPS Backend
 
 Changes to the PowerPC Backend
 --
+* LLJIT's JIT linker now defaults to JITLink on 64-bit ELFv2 targets.
+* Initial-exec TLS model is supported on AIX.
+* Implemented new resource based scheduling model of POWER7 and POWER8.
+* ``frexp`` libcall now references correct symbol name for ``fp128``.
+* Optimized materialization of 64-bit immediates, code generation of
+  ``vec_promote`` and atomics.
+
+* Global constant strings are pooled in the TOC under one entry to reduce the
+  number of entries in the TOC.
+* Added a number of missing Power10 extended mnemonics.
+* Added the SCV instruction.
+* Fixed register class for the paddi instruction.
+* Optimize VPERM and fix code order for swapping vector operands on LE.
+* Added various bug fixes and code gen improvements.
+
+AIX Support/improvements:
+
+* Support for a non-TOC-based access sequence for the local-exec TLS model 
(called

[llvm-branch-commits] [clang] [llvm] [PowerPC] Update V18.1.0 release notes (PR #81631)

2024-02-13 Thread Maryam Moghadas via llvm-branch-commits 

https://github.com/maryammo updated 
https://github.com/llvm/llvm-project/pull/81631

>From 627612dff3314b8250542ca951027b8ec8f7ac71 Mon Sep 17 00:00:00 2001
From: Maryam Moghadas 
Date: Mon, 12 Feb 2024 13:35:00 -0600
Subject: [PATCH 1/2] [PowerPC] Update V18.1.0 release notes

---
 clang/docs/ReleaseNotes.rst | 26 ++
 llvm/docs/ReleaseNotes.rst  | 37 +
 2 files changed, 63 insertions(+)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 95d44951ae7ee6..22eceea5d265ef 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -304,6 +304,10 @@ Non-comprehensive list of changes in this release
 
 * The version of Unicode used by Clang (primarily to parse identifiers) has 
been updated to 15.1.
 
+* Clang now defines macro ``__LLVM_INSTR_PROFILE_GENERATE`` when compiling with
+  PGO instrumentation profile generation, and ``__LLVM_INSTR_PROFILE_USE`` when
+  compiling with PGO profile use.
+
 New Compiler Flags
 --
 
@@ -344,6 +348,8 @@ New Compiler Flags
   attribute the replaceable global new and delete operators behave normally
   (like other functions) with respect to visibility attributes, pragmas and
   options (e.g ``--fvisibility=``).
+* Full register names can be used when printing assembly via ``-mregnames``.
+  This option now matches the one used by GCC.
 
 Deprecated Compiler Flags
 -
@@ -363,6 +369,7 @@ Modified Compiler Flags
 * ``-fvisibility-global-new-delete-hidden`` is now a deprecated spelling of
   ``-fvisibility-global-new-delete=force-hidden`` 
(``-fvisibility-global-new-delete=``
   is new in this release).
+* ``-fprofile-update`` is enabled for ``-fprofile-generate``.
 
 Removed Compiler Flags
 -
@@ -860,6 +867,9 @@ Bug Fixes in This Version
   Fixes (`#78290 `_)
 - Fixed assertion failure with deleted overloaded unary operators.
   Fixes (`#78314 `_)
+- The XCOFF object file format does not support aliases to symbols having 
common
+  linkage. Clang now diagnoses the use of an alias for a common symbol when
+  compiling for AIX.
 
 - Clang now doesn't produce false-positive warning `-Wconstant-logical-operand`
   for logical operators in C23.
@@ -1261,6 +1271,16 @@ CUDA Support
 - Clang now supports CUDA SDK up to 12.3
 - Added support for sm_90a
 
+PowerPC Support
+^^^
+
+- Added ``nmmintrin.h`` to intrinsics headers.
+- Added ``__builtin_ppc_fence`` as barrier of code motion, and
+  ``__builtin_ppc_mffsl`` for corresponding instruction.
+- Supported ``__attribute__((target("tune=cpu")))``.
+- Emit ``float-abi`` module flag on 64-bit ELFv2 PowerPC targets if
+  ``long double`` type is used in current module.
+
 AIX Support
 ^^^
 
@@ -1269,6 +1289,10 @@ AIX Support
   base is encoded as an immediate operand.
   This access sequence is not used for TLS variables larger than 32KB, and is
   currently only supported on 64-bit mode.
+- Inline assembler supports VSR register in pure digits.
+- Enabled ThinLTO support. Requires AIX 7.2 TL5 SP7 or newer, or AIX 7.3 TL2
+  or newer. Similar to the LTO support on AIX, ThinLTO is implemented with
+  the libLTO.so plugin.
 
 WebAssembly Support
 ^^^
@@ -1332,6 +1356,8 @@ libclang
 - Exposed arguments of ``clang::annotate``.
 - ``clang::getCursorKindForDecl`` now recognizes linkage specifications such as
   ``extern "C"`` and reports them as ``CXCursor_LinkageSpec``.
+- Changed the libclang library on AIX to export only the necessary symbols to
+  prevent issues of resolving to the wrong duplicate symbol.
 
 Static Analyzer
 ---
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 82f4a7a15c9c13..16acbb965c5c94 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -163,6 +163,30 @@ Changes to the MIPS Backend
 
 Changes to the PowerPC Backend
 --
+* LLJIT's JIT linker now defaults to JITLink on 64-bit ELFv2 targets.
+* Initial-exec TLS model is supported on AIX.
+* Implemented new resource based scheduling model of POWER7 and POWER8.
+* ``frexp`` libcall now references correct symbol name for ``fp128``.
+* Optimized materialization of 64-bit immediates, code generation of
+  ``vec_promote`` and atomics.
+
+* Global constant strings are pooled in the TOC under one entry to reduce the
+  number of entries in the TOC.
+* Added a number of missing Power10 extended mnemonics.
+* Added the SCV instruction.
+* Fixed register class for the paddi instruction.
+* Optimize VPERM and fix code order for swapping vector operands on LE.
+* Added various bug fixes and code gen improvements.
+
+AIX Support/improvements:
+
+* Support for a non-TOC-based access sequence for the local-exec TLS model 
(called small local-exec).
+* XCOFF toc-data peephole optimization and bug fix

[llvm-branch-commits] [clang] [llvm] [PowerPC] Update V18.1.0 release notes (PR #81631)

2024-02-13 Thread Maryam Moghadas via llvm-branch-commits 


@@ -327,6 +352,12 @@ Changes to the LLVM tools
 
 * llvm-objcopy now supports ``--gap-fill`` and ``--pad-to`` options, for
   ELF input and binary output files only.
+* Supported parsing XCOFF auxiliary symbols in obj2yaml.

maryammo wrote:

done

https://github.com/llvm/llvm-project/pull/81631
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[llvm-branch-commits] [clang] [llvm] [PowerPC] Update V18.1.0 release notes (PR #81631)

2024-02-13 Thread Maryam Moghadas via llvm-branch-commits 


@@ -163,6 +163,30 @@ Changes to the MIPS Backend
 
 Changes to the PowerPC Backend
 --
+* LLJIT's JIT linker now defaults to JITLink on 64-bit ELFv2 targets.

maryammo wrote:

done

https://github.com/llvm/llvm-project/pull/81631
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[llvm-branch-commits] [clang] [llvm] [PowerPC] Update V18.1.0 release notes (PR #81631)

2024-02-13 Thread Maryam Moghadas via llvm-branch-commits 

maryammo wrote:

> Is this ready to merge?

Yes it is ready, thank you. 

https://github.com/llvm/llvm-project/pull/81631
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[llvm-branch-commits] [llvm] PR for llvm/llvm-project#80024 (PR #80025)

2024-01-30 Thread Maryam Moghadas via llvm-branch-commits 

maryammo wrote:




> @maryammo What do you think about merging this PR to the release branch?

Yes, thanks.

https://github.com/llvm/llvm-project/pull/80025
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[llvm-branch-commits] [llvm] PR for llvm/llvm-project#80024 (PR #80025)

2024-01-30 Thread Maryam Moghadas via llvm-branch-commits 

https://github.com/maryammo approved this pull request.


https://github.com/llvm/llvm-project/pull/80025
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[llvm-branch-commits] [llvm] [PowerPC] Add dense math half-precision floating-point outer-product accumulate to DMR instructions (PR #133272)

2025-03-27 Thread Maryam Moghadas via llvm-branch-commits 

https://github.com/maryammo created 
https://github.com/llvm/llvm-project/pull/133272

This patch adds the following Dense Math Facility 16-bit half-precision 
floating-point calculation instructions: dmxvf16gerx2, dmxvf16gerx2pp, 
dmxvf16gerx2pn, dmxvf16gerx2np, dmxvf16gerx2nn, pmdmxvf16gerx2, 
pmdmxvf16gerx2pp, pmdmxvf16gerx2pn, pmdmxvf16gerx2np, pmdmxvf16gerx2nn, along 
with their corresponding intrinsics and tests.

>From 109f52126c42231776d7cd2402827cedb036a240 Mon Sep 17 00:00:00 2001
From: Maryam Moghadas 
Date: Thu, 27 Mar 2025 16:30:41 +
Subject: [PATCH] [PowerPC] Add dense math half-precision floating-point
 outer-product accumulate to DMR instructions

This patch adds the following Dense Math Facility 16-bit half-precision
floating-point calculation instructions: dmxvf16gerx2, dmxvf16gerx2pp,
dmxvf16gerx2pn, dmxvf16gerx2np, dmxvf16gerx2nn, pmdmxvf16gerx2,
pmdmxvf16gerx2pp, pmdmxvf16gerx2pn, pmdmxvf16gerx2np, pmdmxvf16gerx2nn,
along with their corresponding intrinsics and tests.
---
 llvm/include/llvm/IR/IntrinsicsPowerPC.td |   7 +
 llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td  | 116 -
 .../test/CodeGen/PowerPC/dmf-outer-product.ll | 483 ++
 .../PowerPC/ppc-encoding-ISAFuture.txt|  30 ++
 .../PowerPC/ppc64le-encoding-ISAFuture.txt|  30 ++
 llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s |  50 ++
 6 files changed, 714 insertions(+), 2 deletions(-)

diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index b57102ef68f09..bcc3fc6f0fc13 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1755,6 +1755,13 @@ let TargetPrefix = "ppc" in {
   defm int_ppc_mma_pmdmxvbf16gerx2 :
PowerPC_MMA_DMR_Intrinsic<[llvm_v256i1_ty, llvm_v16i8_ty, llvm_i32_ty,
  llvm_i32_ty, llvm_i32_ty]>;
+
+  // MMA+ Half-precision Outer Product Intrinsic Definitions.
+  defm int_ppc_mma_dmxvf16gerx2 :
+   PowerPC_MMA_DMR_Intrinsic<[llvm_v256i1_ty, llvm_v16i8_ty]>;
+  defm int_ppc_mma_pmdmxvf16gerx2 :
+   PowerPC_MMA_DMR_Intrinsic<[llvm_v256i1_ty, llvm_v16i8_ty, llvm_i32_ty,
+ llvm_i32_ty, llvm_i32_ty]>;
 }
 
 // XL Compat intrinsics.
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td 
b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
index 8ea0924f09b43..331649bddafb7 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
@@ -207,7 +207,7 @@ multiclass DMR_BF16_UM_XOEO opcode, bits<8> xo, dag 
IOL, string asmbase,
   }
 }
 
-multiclass DMR_UM_M284_XOEO opcode, bits<8> xo, dag IOL, string 
asmbase,
+multiclass DMR_BF16_UM_M284_XOEO opcode, bits<8> xo, dag IOL, string 
asmbase,
 string asmstr> {
   defm NAME : DMR_BF16_UM_XOEO;
   let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
@@ -228,9 +228,30 @@ multiclass DMR_UM_M284_XOEO opcode, bits<8> xo, 
dag IOL, string asmbase,
   }
 }
 
+multiclass DMR_F16_UM_M284_XOEO opcode, bits<8> xo, dag IOL, string 
asmbase,
+string asmstr> {
+  defm NAME : DMR_UM_XOEO;
+  let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
+  def PM#NAME :
+MMIRR_XX3Form_X8Y4P2_XAp5B6<
+  opcode, !or(xo, 0x01), (outs dmr:$AT),
+  !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)),
+  !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
+  IIC_VecFP, []>,
+RegConstraint<"@earlyclobber $AT">;
+  def PM#NAME#PP :
+MMIRR_XX3Form_X8Y4P2_XAp5B6<
+  opcode, xo, (outs dmr:$AT),
+  !con((ins dmr:$ATi), !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, 
u2imm:$PMSK))),
+  !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
+  IIC_VecFP, []>,
+RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+  }
+}
+
 multiclass DMR_NEG_UM_M284_XOXORf939a0 opcode, bits<8> xo, dag IOL,
   string asmbase, string asmstr> {
-  defm NAME : DMR_UM_M284_XOEO;
+  defm NAME : DMR_BF16_UM_M284_XOEO;
   let Predicates = [MMA, IsISAFuture] in {
   def PN : XX3Form_AT3_XAp5B6<
  opcode, !xor(xo, 0xF9), (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
@@ -270,6 +291,48 @@ multiclass DMR_NEG_UM_M284_XOXORf939a0 opcode, 
bits<8> xo, dag IOL,
   }
 }
 
+multiclass DMR_NEG_UM_M284_XOXORd11188 opcode, bits<8> xo, dag IOL,
+  string asmbase, string asmstr> {
+  defm NAME : DMR_F16_UM_M284_XOEO;
+  let Predicates = [MMA, IsISAFuture] in {
+  def PN : XX3Form_AT3_XAp5B6<
+ opcode, !xor(xo, 0xD1), (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
+ !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
+   RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+  def NP : XX3Form_AT3_XAp5B6<
+ opcode, !xor(xo, 0x11), (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
+ !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,
+   RegConstraint<"$ATi = $AT">,