[llvm-branch-commits] [llvm] Users/ppenzin/ra saverestore offsets (PR #170607)
https://github.com/ppenzin created
https://github.com/llvm/llvm-project/pull/170607
Support scalable offsets in CFI.
This has been split out from
https://github.com/mgudim/llvm-project/tree/save_csr_in_ra3, and is PR 2 out of
5.
Co-authored-by: Mikhail Gudim
>From f621b6515740a279d51fc4ced44967b103987d13 Mon Sep 17 00:00:00 2001
From: Mikhail Gudim
Date: Mon, 25 Aug 2025 12:50:34 -0700
Subject: [PATCH 1/3] Support scalable offset in CFI.
Currently, targets with scalable vectors (AArch64, RISCV) handle
scalable offsets in cfi using cfi_escape expression. The problem is that
CFIInstrInserter doesn't understand these expressions.
We define new "pseudo" cfi instructions to support scalable offsets in
CFI:
(1) llvm_def_cfa_reg_scalable_offset - creates the new rule for calculating
cfa: `deref(Reg + ScalableOffset * x + FixedOffset)` where `x` is the
"scale" runtime constant.
(2) llvm_reg_at_scalable_offset_from_cfa - creates the new rule to calculate
previoius value of register `deref(cfa + ScalableOffset * x +
FixedOffset)` where `x` is the "scale" runtime constant.
(3) llvm_reg_at_scalable_offset_from_reg - creates the new rule to calculate
previous value
of register `deref(Reg2 + ScalableOffset * x +
FixedOffset)`. This rule is to be used when
offset from cfa is not known, but intead fixed offset from `Reg2` is
known.
All of these cfi_instructions will be "lowered" to escape expressions
during final assembly emission. But during `CFIInstrInserter` these are
not lowered yet, so their semantics can be understood without decoding
cfi expressions. Since (1) and (2) depend on how target calculates
scalable offsets, their lowering is target-dependent.
---
llvm/include/llvm/MC/MCDwarf.h| 94 +++-
llvm/include/llvm/MC/MCStreamer.h | 19
.../CodeGen/AsmPrinter/AsmPrinterDwarf.cpp| 18 +++
llvm/lib/CodeGen/CFIInstrInserter.cpp | 8 +-
llvm/lib/CodeGen/MIRParser/MILexer.cpp| 6 +
llvm/lib/CodeGen/MIRParser/MILexer.h | 3 +
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 41 +++
llvm/lib/CodeGen/MachineOperand.cpp | 26 +
llvm/lib/MC/MCDwarf.cpp | 4 +
.../MCTargetDesc/RISCVTargetStreamer.cpp | 103 +-
.../RISCV/MCTargetDesc/RISCVTargetStreamer.h | 17 +++
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 80 --
.../cfi-llvm-def-cfa-reg-scalable-offset.mir | 11 ++
...i-llvm-reg-at-scalable-offset-from-cfa.mir | 11 ++
...i-llvm-reg-at-scalable-offset-from-reg.mir | 11 ++
.../cfi-llvm-def-cfa-reg-scalable-offset.mir | 33 ++
...i-llvm-reg-at-scalable-offset-from-cfa.mir | 34 ++
...i-llvm-reg-at-scalable-offset-from-reg.mir | 36 ++
.../CodeGen/RISCV/rvv/get-vlen-debugloc.mir | 2 +-
.../rvv/wrong-stack-offset-for-rvv-object.mir | 8 +-
llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir | 2 +-
21 files changed, 498 insertions(+), 69 deletions(-)
create mode 100644
llvm/test/CodeGen/MIR/RISCV/cfi-llvm-def-cfa-reg-scalable-offset.mir
create mode 100644
llvm/test/CodeGen/MIR/RISCV/cfi-llvm-reg-at-scalable-offset-from-cfa.mir
create mode 100644
llvm/test/CodeGen/MIR/RISCV/cfi-llvm-reg-at-scalable-offset-from-reg.mir
create mode 100644
llvm/test/CodeGen/RISCV/cfi-llvm-def-cfa-reg-scalable-offset.mir
create mode 100644
llvm/test/CodeGen/RISCV/cfi-llvm-reg-at-scalable-offset-from-cfa.mir
create mode 100644
llvm/test/CodeGen/RISCV/cfi-llvm-reg-at-scalable-offset-from-reg.mir
diff --git a/llvm/include/llvm/MC/MCDwarf.h b/llvm/include/llvm/MC/MCDwarf.h
index 9944a9a92ab1f..8a46ac64cdc87 100644
--- a/llvm/include/llvm/MC/MCDwarf.h
+++ b/llvm/include/llvm/MC/MCDwarf.h
@@ -15,6 +15,7 @@
#define LLVM_MC_MCDWARF_H
#include "llvm/ADT/MapVector.h"
+#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringRef.h"
@@ -514,6 +515,9 @@ class MCCFIInstruction {
OpRestoreState,
OpOffset,
OpLLVMDefAspaceCfa,
+OpLLVMDefCfaRegScalableOffset,
+OpLLVMRegAtScalableOffsetFromCfa,
+OpLLVMRegAtScalableOffsetFromReg,
OpDefCfaRegister,
OpDefCfaOffset,
OpDefCfa,
@@ -547,6 +551,17 @@ class MCCFIInstruction {
unsigned Register;
unsigned Register2;
} RR;
+struct {
+ unsigned Register;
+ int64_t ScalableOffset;
+ int64_t FixedOffset;
+} ROO;
+struct {
+ unsigned Register;
+ unsigned Register2;
+ int64_t ScalableOffset;
+ int64_t FixedOffset;
+} RROO;
MCSymbol *CfiLabel;
} U;
OpType Operation;
@@ -579,6 +594,22 @@ class MCCFIInstruction {
U.CfiLabel = CfiLabel;
}
+ MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R, int64_t ScalableOffset,
+ int64_t FixedOffset, SMLoc Loc, StringRef Comment = "")
+ : Label(L), Operation(Op), Loc(Loc), Comment(Comment) {
+assert(Operation == OpLLVMDefCfaRegScalableOffset ||
+
[llvm-branch-commits] [llvm] Users/ppenzin/ra saverestore split calleesaves (PR #170609)
https://github.com/ppenzin created
https://github.com/llvm/llvm-project/pull/170609
Replace `determineCalleeSaves` with `determinePrologCalleeSaves`, provide
additional functions for other potential points of save.
This has been split out from
https://github.com/mgudim/llvm-project/tree/save_csr_in_ra3, and is PR 3 out of
5.
Co-authored-by: Mikhail Gudim
>From 72cc4449f96fa5a3d97d4737d623674058e9bf26 Mon Sep 17 00:00:00 2001
From: Mikhail Gudim
Date: Wed, 1 Oct 2025 12:32:55 -0700
Subject: [PATCH 1/2] [TargetFrameLowering] Refactor `determineCalleeSaves`.
Split up `determineCaleeSaves` into:
`const MCPhysReg *getMustPreserveRegisters(MachineFunction &MF) const`:
Return the list of registers which must be preserved by the function: the
value on exit must be the same as the value on entry. A register from this list
does not need to be saved / reloaded if the function did not use it.
`virtual void determineUncondPrologCalleeSaves(MachineFunction &MF, const
MCPhysReg *CSRegs, BitVector &UncondPrologCSRs) const`:
Determines which of the registers reported by getMustPreserveRegisters()
must be saved in prolog and reloaded in epilog regardless of wheather or not
they were modified by the function.
`virtual void determineEarlyCalleeSaves(MachineFunction &MF, BitVector
&EarlyCSRs)`:
Returns the difference between getMustPreserveRegisters and
determineUncondPrologCalleeSaves. These registers will be preserved by the code
optimizer and do not need to be saved in prolog.
`virtual void determinePrologCalleeSaves(MachineFunction &MF,
BitVector &PrologCSRs,
RegScavenger *RS) const`:
This method returns those registers in the difference of
getMustPreserveRegisters and determineEarlyCalleeSaves that were modified by
the function and need to be saved in prolog.
---
.../llvm/CodeGen/TargetFrameLowering.h| 31 -
.../llvm/CodeGen/TargetSubtargetInfo.h| 4 +
llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp | 106 +-
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 30 +
llvm/lib/Target/RISCV/RISCVFrameLowering.h| 2 +
llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 8 ++
llvm/lib/Target/RISCV/RISCVSubtarget.h| 2 +
.../CodeGen/RISCV/determine-callee-saves.mir | 79 +
8 files changed, 233 insertions(+), 29 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/determine-callee-saves.mir
diff --git a/llvm/include/llvm/CodeGen/TargetFrameLowering.h
b/llvm/include/llvm/CodeGen/TargetFrameLowering.h
index 75696faf114cc..085138743764e 100644
--- a/llvm/include/llvm/CodeGen/TargetFrameLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetFrameLowering.h
@@ -381,7 +381,7 @@ class LLVM_ABI TargetFrameLowering {
BitVector &SavedRegs) const;
/// This method determines which of the registers reported by
- /// TargetRegisterInfo::getCalleeSavedRegs() should actually get saved.
+ /// getMustPreserveRegisters() should actually get saved.
/// The default implementation checks populates the \p SavedRegs bitset with
/// all registers which are modified in the function, targets may override
/// this function to save additional registers.
@@ -390,9 +390,38 @@ class LLVM_ABI TargetFrameLowering {
/// This method should not be called by any passes outside of PEI, because
/// it may change state passed in by \p MF and \p RS. The preferred
/// interface outside PEI is getCalleeSaves.
+ LLVM_DEPRECATED("Use determinePrologCalleeSaves instead",
+ "determinePrologCalleeSaves")
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
RegScavenger *RS = nullptr) const;
+ /// Return the list of registers which must be preserved by the function: the
+ /// value on exit must be the same as the value on entry. A register from
this
+ /// list does not need to be saved / reloaded if the function did not use it.
+ const MCPhysReg *getMustPreserveRegisters(MachineFunction &MF) const;
+
+ /// This method determines which of the registers reported by
+ /// getMustPreserveRegisters() must be saved in prolog and reloaded in epilog
+ /// regardless of wheather or not they were modified by the function.
+ virtual void
+ determineUncondPrologCalleeSaves(MachineFunction &MF, const MCPhysReg
*CSRegs,
+ BitVector &UncondPrologCSRs) const;
+
+ /// If the target has to do all saves / restores of "must preserve" registers
+ /// in prolog / epilog, this method returns empty set. Otherwise, this method
+ /// returns the difference between getMustPreserveRegisters and
+ /// determineUncondPrologCalleeSaves. These registers will be preserved by
the
+ /// code optimizer and do not need to be saved in prolog.
+ virtual void determineEarlyCalleeSaves(MachineFunction &MF,
+
[llvm-branch-commits] [llvm] [WIP] Users/ppenzin/ra saverestore early cfi (PR #170610)
https://github.com/ppenzin created
https://github.com/llvm/llvm-project/pull/170610
Add ability to emit CFIs if the registers were saved / restored before prolog /
epilog insertion.
This has been split out from
https://github.com/mgudim/llvm-project/tree/save_csr_in_ra3, and is PR 4 out of
5.
Co-authored-by: Mikhail Gudim
>From 48b49aa918c18afc71389bdde4ceaec8b3a775ca Mon Sep 17 00:00:00 2001
From: Mikhail Gudim
Date: Fri, 19 Sep 2025 11:36:21 -0700
Subject: [PATCH] Emit early CFIs
Add ability to emit CFIs if the registers were saved / restored
before prolog / epilog insertion.
---
.../llvm/CodeGen/TargetFrameLowering.h| 27 ++--
llvm/lib/CodeGen/PrologEpilogInserter.cpp | 18 ++-
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 149 ++
llvm/lib/Target/RISCV/RISCVFrameLowering.h| 2 +
llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 15 +-
llvm/test/CodeGen/RISCV/O0-pipeline.ll| 1 +
llvm/test/CodeGen/RISCV/O3-pipeline.ll| 1 +
llvm/test/CodeGen/RISCV/emit-early-cfis.mir | 108 +
8 files changed, 300 insertions(+), 21 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/emit-early-cfis.mir
diff --git a/llvm/include/llvm/CodeGen/TargetFrameLowering.h
b/llvm/include/llvm/CodeGen/TargetFrameLowering.h
index c04cd33b3377a..fe3ebcd13b2bc 100644
--- a/llvm/include/llvm/CodeGen/TargetFrameLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetFrameLowering.h
@@ -25,16 +25,17 @@ namespace llvm {
class CalleeSavedInfo;
class MachineFunction;
class RegScavenger;
-
-namespace TargetStackID {
-enum Value {
- Default = 0,
- SGPRSpill = 1,
- ScalableVector = 2,
- WasmLocal = 3,
- ScalablePredicateVector = 4,
- NoAlloc = 255
-};
+ class ReachingDefInfo;
+
+ namespace TargetStackID {
+ enum Value {
+Default = 0,
+SGPRSpill = 1,
+ScalableVector = 2,
+WasmLocal = 3,
+ScalablePredicateVector = 4,
+NoAlloc = 255
+ };
}
/// Information about stack frame layout on the target. It holds the direction
@@ -212,6 +213,12 @@ class LLVM_ABI TargetFrameLowering {
/// for noreturn nounwind functions.
virtual bool enableCalleeSaveSkip(const MachineFunction &MF) const;
+ /// If savesCSRsEarly is true, we don't really know where the CSRs are
+ /// saved. This function calculates where each CSR is at every point in the
+ /// function and inserts necessary CFIs. It has to run before frame indicies
+ /// are resolved.
+ virtual void emitCFIsEarly(MachineFunction &MF, ReachingDefInfo &RDA) const
{}
+
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function.
virtual void emitPrologue(MachineFunction &MF,
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index 2639edcfed0a2..b97c5cd4e98d5 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -36,6 +36,7 @@
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PEI.h"
+#include "llvm/CodeGen/ReachingDefAnalysis.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
@@ -79,6 +80,7 @@ namespace {
class PEIImpl {
RegScavenger *RS = nullptr;
+ ReachingDefInfo &RDI;
// MinCSFrameIndex, MaxCSFrameIndex - Keeps the range of callee saved
// stack frame indexes.
@@ -125,7 +127,8 @@ class PEIImpl {
void insertZeroCallUsedRegs(MachineFunction &MF);
public:
- PEIImpl(MachineOptimizationRemarkEmitter *ORE) : ORE(ORE) {}
+ PEIImpl(ReachingDefInfo &RDI, MachineOptimizationRemarkEmitter *ORE)
+ : RDI(RDI), ORE(ORE) {}
bool run(MachineFunction &MF);
};
@@ -155,6 +158,7 @@ INITIALIZE_PASS_BEGIN(PEILegacy, DEBUG_TYPE,
"Prologue/Epilogue Insertion",
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineOptimizationRemarkEmitterPass)
+INITIALIZE_PASS_DEPENDENCY(ReachingDefInfoWrapperPass)
INITIALIZE_PASS_END(PEILegacy, DEBUG_TYPE,
"Prologue/Epilogue Insertion & Frame Finalization", false,
false)
@@ -171,6 +175,7 @@ void PEILegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved();
AU.addPreserved();
AU.addRequired();
+ AU.addRequired();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -361,7 +366,8 @@ bool PEIImpl::run(MachineFunction &MF) {
bool PEILegacy::runOnMachineFunction(MachineFunction &MF) {
MachineOptimizationRemarkEmitter *ORE =
&getAnalysis().getORE();
- return PEIImpl(ORE).run(MF);
+ auto &RDI = getAnalysis().getRDI();
+ return PEIImpl(RDI, ORE).run(MF);
}
PreservedAnalyses
@@ -369,7 +375,8 @@ PrologEpilogInserterPass::run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM) {
MachineOptimizationRemarkEmi
[llvm-branch-commits] [llvm] [WIP] Users/ppenzin/ra saverestore codegen (PR #170611)
https://github.com/ppenzin created
https://github.com/llvm/llvm-project/pull/170611
Use register allocator to save callee-saved registers.
This has been split out from
https://github.com/mgudim/llvm-project/tree/save_csr_in_ra3, and is PR 5 out of
5.
Co-authored-by: Mikhail Gudim
>From 2f93583a74dade13944af887178f83f857083496 Mon Sep 17 00:00:00 2001
From: Mikhail Gudim
Date: Wed, 5 Nov 2025 06:08:10 -0800
Subject: [PATCH 1/2] [CodeGen] Let RDA recompute live-ins.
This is needed for the cases when RDA has to run on a function that
does not have live-ins info.
---
llvm/lib/CodeGen/ReachingDefAnalysis.cpp | 12
llvm/test/CodeGen/RISCV/pr53662.mir | 4
.../RISCV/rvv/fixed-vectors-emergency-slot.mir | 2 +-
3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
index b12a5bc64ca0b..7014fd4bf890b 100644
--- a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
+++ b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
@@ -9,6 +9,8 @@
#include "llvm/CodeGen/ReachingDefAnalysis.h"
#include "llvm/ADT/SetOperations.h"
#include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/PostOrderIterator.h"
+#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/LiveRegUnits.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
@@ -288,6 +290,16 @@ void ReachingDefInfo::run(MachineFunction &mf) {
TRI = STI.getRegisterInfo();
TII = STI.getInstrInfo();
LLVM_DEBUG(dbgs() << "** REACHING DEFINITION ANALYSIS **\n");
+
+ MachineFunctionProperties &Props = MF->getProperties();
+ if (!Props.hasTracksLiveness()) {
+Props.setTracksLiveness();
+
+SmallVector AllMBBsInPostOrder;
+for (MachineBasicBlock *MBB : post_order(MF))
+ AllMBBsInPostOrder.push_back(MBB);
+fullyRecomputeLiveIns(AllMBBsInPostOrder);
+ }
init();
traverse();
}
diff --git a/llvm/test/CodeGen/RISCV/pr53662.mir
b/llvm/test/CodeGen/RISCV/pr53662.mir
index dccad40368111..834bcbc1cf82c 100644
--- a/llvm/test/CodeGen/RISCV/pr53662.mir
+++ b/llvm/test/CodeGen/RISCV/pr53662.mir
@@ -18,15 +18,19 @@ body: |
; CHECK-LABEL: name: b
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x8000)
+ ; CHECK-NEXT: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: PseudoBR %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x8000)
+ ; CHECK-NEXT: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: DBG_VALUE $noreg
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: PseudoRET implicit killed $x10
bb.0 :
PseudoBR %bb.1
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
index c728fcb8d8b0d..44f60a43a2790 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
@@ -47,7 +47,7 @@ body: |
SD $x10, %stack.0, 0
SD $x10, %stack.2, 0
-dead renamable $x15 = PseudoVSETIVLI 1, 72, implicit-def $vl, implicit-def
$vtype
+renamable $x15 = PseudoVSETIVLI 1, 72, implicit-def $vl, implicit-def
$vtype
VS1R_V killed renamable $v25, %stack.1 :: (store () into
%stack.1, align 8)
; This is here just to make all the eligible registers live at this point.
; This way when we replace the frame index %stack.1 with its actual address
>From 5fd960191964a3b46311ccc8550b991b41aabcf5 Mon Sep 17 00:00:00 2001
From: Mikhail Gudim
Date: Fri, 2 May 2025 09:16:49 -0700
Subject: [PATCH 2/2] Make the RA to save CSRs.
In `finalizeLowering` we copy all callee-saved registers from a physical
register to a virtual one. In all return blocks we copy do the reverse.
This has two effects:
(1) It tells the optimizer that the value of callee-saved registers
has to be preserved
(2) Allows the optimizer to work on CSRs. In particular, we get
shrink-wrapping "for free" - the register allocator will spill /
restore CSRs if needed.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 92
llvm/lib/Target/RISCV/RISCVISelLowering.h | 2 +
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp| 8 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 2 +
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 3 +
llvm/test/CodeGen/RISCV/save-csr-early.ll | 113
6 files changed, 220 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/save-csr-early.ll
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ab2652eac3823..7e7af8d48da0b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -25827,3 +25827,95 @@ bool
RISCVTargetLowering::isReassocProfitable(SelectionDAG &DAG, SDValue N0,
[llvm-branch-commits] [llvm] [WIP][CodeGen] Split `determineCalleeSaves` (PR #170609)
https://github.com/ppenzin edited https://github.com/llvm/llvm-project/pull/170609 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [WIP][CodeGen][DebugInfo][RISCV] Support scalable offsets in CFI (PR #170607)
https://github.com/ppenzin edited https://github.com/llvm/llvm-project/pull/170607 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [WIP][CodeGen] Enable early CFI (PR #170610)
https://github.com/ppenzin edited https://github.com/llvm/llvm-project/pull/170610 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [WIP][CodeGen] Enable early CFI (PR #170610)
https://github.com/ppenzin edited https://github.com/llvm/llvm-project/pull/170610 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [WIP][CodeGen] Allow register allocator to drive save/restore (PR #170611)
https://github.com/ppenzin edited https://github.com/llvm/llvm-project/pull/170611 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [WIP][CodeGen] Allow register allocator to drive save/restore (PR #170611)
https://github.com/ppenzin edited https://github.com/llvm/llvm-project/pull/170611 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [WIP][CodeGen][DebugInfo][RISCV] Support scalable offsets in CFI (PR #170607)
https://github.com/ppenzin edited https://github.com/llvm/llvm-project/pull/170607 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [WIP][CodeGen][DebugInfo][RISCV] Support scalable offsets in CFI (PR #170607)
ppenzin wrote: This change has clean CI (the failures are coming from the one it is stacked on), I think I can make it stand on its own, but it might require a bit more careful DWARF verification. https://github.com/llvm/llvm-project/pull/170607 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [WIP][CodeGen][DebugInfo][RISCV] Support scalable offsets in CFI (PR #170607)
https://github.com/ppenzin edited https://github.com/llvm/llvm-project/pull/170607 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [WIP][CodeGen] Split `determineCalleeSaves` (PR #170609)
https://github.com/ppenzin edited https://github.com/llvm/llvm-project/pull/170609 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
