[llvm-branch-commits] [llvm-branch] r296340 - [ReleaseNotes] Add MIPS release notes.
Author: sdardis Date: Mon Feb 27 07:25:42 2017 New Revision: 296340 URL: http://llvm.org/viewvc/llvm-project?rev=296340&view=rev Log: [ReleaseNotes] Add MIPS release notes. Modified: llvm/branches/release_40/docs/ReleaseNotes.rst Modified: llvm/branches/release_40/docs/ReleaseNotes.rst URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/docs/ReleaseNotes.rst?rev=296340&r1=296339&r2=296340&view=diff == --- llvm/branches/release_40/docs/ReleaseNotes.rst (original) +++ llvm/branches/release_40/docs/ReleaseNotes.rst Mon Feb 27 07:25:42 2017 @@ -238,6 +238,34 @@ Most of the work behind the scenes has b assembly, and also fixing some assertions we would hit on some well-formed inputs. +Changes to the MIPS Target +- + +**During this release the MIPS target has:** + +* IAS is now enabled by default for Debian mips64el. +* Added support for the two operand form for many instructions. +* Added the following macros: unaligned load/store, seq, double word load/store for O32. +* Improved the parsing of complex memory offset expressions. +* Enabled the integrated assembler by default for Debian mips64el. +* Added a generic scheduler based on the interAptiv CPU. +* Added support for thread local relocations. +* Added recip, rsqrt, evp, dvp, synci instructions in IAS. +* Optimized the generation of constants from some cases. + +**The following issues have been fixed:** + +* Thread local debug information is correctly recorded. +* MSA intrinsics are now range checked. +* Fixed an issue with MSA and the no-odd-spreg abi. +* Fixed some corner cases in handling forbidden slots for MIPSR6. +* Fixed an issue with jumps not being converted to relative branches for assembly. +* Fixed the handling of local symbols and jal instruction. +* N32/N64 no longer have their relocation tables sorted as per their ABIs. +* Fixed a crash when half-precision floating point conversion MSA intrinsics are used. +* Fixed several crashes involving FastISel. +* Corrected the corrected definitions for aui/daui/dahi/dati for MIPSR6. + Changes to the OCaml bindings - ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm-branch] r301169 - Merging r296105, r296016 and 296111:
Author: sdardis
Date: Mon Apr 24 04:48:54 2017
New Revision: 301169
URL: http://llvm.org/viewvc/llvm-project?rev=301169&view=rev
Log:
Merging r296105, r296016 and 296111:
r296105 | sdardis | 2017-02-24 10:50:27 + (Fri, 24 Feb 2017) | 13 lines
[mips][mc] Fix a crash when disassembling odd sized sections
Make the MIPS disassembler consistent with the other targets in returning
a Size of zero when the input buffer cannot contain an instruction due
to it's size. Previously it reported the minimum instruction size when
it failed due to the buffer not being big enough for an instruction
causing llvm-objdump to crash when disassembling all sections.
Reviewers: slthakur
Differential Revision: https://reviews.llvm.org/D29984
r296106 | sdardis | 2017-02-24 10:51:27 + (Fri, 24 Feb 2017) | 5 lines
[mips][mc] Fix a crash when disassembling odd sized sections
Corresponding test.
r296111 | rovka | 2017-02-24 12:47:11 + (Fri, 24 Feb 2017) | 1 line
Fixup r296105 - only run tests on Mips
Added:
llvm/branches/release_40/test/tools/llvm-objdump/Mips/
llvm/branches/release_40/test/tools/llvm-objdump/Mips/disassemble-all.test
llvm/branches/release_40/test/tools/llvm-objdump/Mips/lit.local.cfg
Modified:
llvm/branches/release_40/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
Modified:
llvm/branches/release_40/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=301169&r1=301168&r2=301169&view=diff
==
--- llvm/branches/release_40/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
(original)
+++ llvm/branches/release_40/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
Mon Apr 24 04:48:54 2017
@@ -1106,6 +1106,7 @@ DecodeStatus MipsDisassembler::getInstru
raw_ostream &CStream) const {
uint32_t Insn;
DecodeStatus Result;
+ Size = 0;
if (IsMicroMips) {
Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
@@ -1168,98 +1169,88 @@ DecodeStatus MipsDisassembler::getInstru
}
}
-// This is an invalid instruction. Let the disassembler move forward by the
-// minimum instruction size.
+// This is an invalid instruction. Claim that the Size is 2 bytes. Since
+// microMIPS instructions have a minimum alignment of 2, the next 2 bytes
+// could form a valid instruction. The two bytes we rejected as an
+// instruction could have actually beeen an inline constant pool that is
+// unconditionally branched over.
Size = 2;
return MCDisassembler::Fail;
}
+ // Attempt to read the instruction so that we can attempt to decode it. If
+ // the buffer is not 4 bytes long, let the higher level logic figure out
+ // what to do with a size of zero and MCDisassembler::Fail.
Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
- if (Result == MCDisassembler::Fail) {
-Size = 4;
+ if (Result == MCDisassembler::Fail)
return MCDisassembler::Fail;
- }
+
+ // The only instruction size for standard encoded MIPS.
+ Size = 4;
if (hasCOP3()) {
DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
Result =
decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this,
STI);
-if (Result != MCDisassembler::Fail) {
- Size = 4;
+if (Result != MCDisassembler::Fail)
return Result;
-}
}
if (hasMips32r6() && isGP64()) {
DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
Address, this, STI);
-if (Result != MCDisassembler::Fail) {
- Size = 4;
+if (Result != MCDisassembler::Fail)
return Result;
-}
}
if (hasMips32r6() && isPTR64()) {
DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn,
Address, this, STI);
-if (Result != MCDisassembler::Fail) {
- Size = 4;
+if (Result != MCDisassembler::Fail)
return Result;
-}
}
if (hasMips32r6()) {
DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
Address, this, STI);
-if (Re
[llvm-branch-commits] [cfe-branch] r311441 - [Sema] Update release notes with details of implicit scalar to vector conversions
Author: sdardis
Date: Tue Aug 22 03:01:35 2017
New Revision: 311441
URL: http://llvm.org/viewvc/llvm-project?rev=311441&view=rev
Log:
[Sema] Update release notes with details of implicit scalar to vector
conversions
Add notes on this to the C language section, along with the C++ section.
Reviewers: bruno, hans
Differential Revision: https://reviews.llvm.org/D36954
Modified:
cfe/branches/release_50/docs/ReleaseNotes.rst
Modified: cfe/branches/release_50/docs/ReleaseNotes.rst
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_50/docs/ReleaseNotes.rst?rev=311441&r1=311440&r2=311441&view=diff
==
--- cfe/branches/release_50/docs/ReleaseNotes.rst (original)
+++ cfe/branches/release_50/docs/ReleaseNotes.rst Tue Aug 22 03:01:35 2017
@@ -116,7 +116,41 @@ Clang's support for building native Wind
C Language Changes in Clang
---
-- ...
+- Added near complete support for implicit scalar to vector conversion, a GNU
+ C/C++ language extension. With this extension, the following code is
+ considered valid:
+
+.. code-block:: c
+
+typedef unsigned v4i32 __attribute__((vector_size(16)));
+
+v4i32 foo(v4i32 a) {
+ // Here 5 is implicitly casted to an unsigned value and replicated into a
+ // vector with as many elements as 'a'.
+ return a + 5;
+}
+
+The implicit conversion of a scalar value to a vector value--in the context of
+a vector expression--occurs when:
+
+- The type of the vector is that of a ``__attribute__((vector_size(size)))``
+ vector, not an OpenCL ``__attribute__((ext_vector_type(size)))`` vector type.
+
+- The scalar value can be casted to that of the vector element's type without
+ the loss of precision based on the type of the scalar and the type of the
+ vector's elements.
+
+- For compile time constant values, the above rule is weakened to consider the
+ value of the scalar constant rather than the constant's type.
+
+- Floating point constants with precise integral representations are not
+ implicitly converted to integer values, this is for compatability with GCC.
+
+
+Currently the basic integer and floating point types with the following
+operators are supported: ``+``, ``/``, ``-``, ``*``, ``%``, ``>``, ``<``,
+``>=``, ``<=``, ``==``, ``!=``, ``&``, ``|``, ``^`` and the corresponding
+assignment operators where applicable.
...
@@ -128,6 +162,10 @@ C11 Feature Support
C++ Language Changes in Clang
-
+- As mentioned in `C Language Changes in Clang`_, Clang's support for
+ implicit scalar to vector conversions also applies to C++. Additionally
+ the following operators are also supported: ``&&`` and ``||``.
+
...
C++1z Feature Support
___
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llvm-branch-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm-branch] r311771 - [mips][Release Notes] Release notes for 5.0
Author: sdardis Date: Fri Aug 25 02:57:29 2017 New Revision: 311771 URL: http://llvm.org/viewvc/llvm-project?rev=311771&view=rev Log: [mips][Release Notes] Release notes for 5.0 Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D37077 Modified: llvm/branches/release_50/docs/ReleaseNotes.rst Modified: llvm/branches/release_50/docs/ReleaseNotes.rst URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/docs/ReleaseNotes.rst?rev=311771&r1=311770&r2=311771&view=diff == --- llvm/branches/release_50/docs/ReleaseNotes.rst (original) +++ llvm/branches/release_50/docs/ReleaseNotes.rst Fri Aug 25 02:57:29 2017 @@ -87,7 +87,41 @@ During this release the ARM target has: Changes to the MIPS Target -- - During this release ... +* The microMIPS64R6 backend is deprecated and will be removed in the next + release. + +* The MIPS backend now directly supports vector types for arguments and return + values (previously this required ABI specific LLVM IR). + +* Added documentation for how the MIPS backend handles address lowering. + +* Added a GCC compatible option -m(no-)madd4 to control the generation of four + operand multiply addition/subtraction instructions. + +* Added basic support for the XRay instrumentation system. + +* Added support for more assembly aliases and macros. + +* Added support for the ``micromips`` and ``nomicromips`` function attributes + which control micromips code generation on a per function basis. + +* Added the ``long-calls`` feature for non-pic environments. This feature is + used where the callee is out of range of the caller using a standard call + sequence. It must be enabled specifically. + +* Added support for performing microMIPS code generation via function + attributes. + +* Added experimental support for the static relocation model for the N64 ABI. + +* Added partial support for the MT ASE. + +* Added basic support for code size reduction for microMIPS. + +* Fixed numerous bugs including: multi-precision arithmetic support, various + vectorization bugs, debug information for thread local variables, debug + sections lacking the correct flags, crashing when disassembling sections + whose size is not a multiple of two or four. Changes to the PowerPC Target ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm-branch] r318386 - Merging r318207:
Author: sdardis
Date: Thu Nov 16 02:13:49 2017
New Revision: 318386
URL: http://llvm.org/viewvc/llvm-project?rev=318386&view=rev
Log:
Merging r318207:
r318207 | sdardis | 2017-11-14 22:26:42 + (Tue, 14 Nov 2017) | 18 lines
Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."
This adjusts the tests to hopfully pacify the
llvm-clang-x86_64-expensive-checks-win buildbot.
Unlike many other instructions, these instructions have aliases which
take coprocessor registers, gpr register, accumulator (and dsp accumulator)
registers, floating point registers, floating point control registers and
coprocessor 2 data and control operands.
For the moment, these aliases are treated as pseudo instructions which are
expanded into the underlying instruction. As a result, disassembling these
instructions shows the underlying instruction and not the alias.
Reviewers: slthakur, atanasyan
Differential Revision: https://reviews.llvm.org/D35253
Added:
llvm/branches/release_50/test/MC/Mips/mt/invalid-wrong-error.s
llvm/branches/release_50/test/MC/Mips/mt/mftr-mttr-aliases-invalid-wrong-error.s
llvm/branches/release_50/test/MC/Mips/mt/mftr-mttr-aliases-invalid.s
llvm/branches/release_50/test/MC/Mips/mt/mftr-mttr-aliases.s
llvm/branches/release_50/test/MC/Mips/mt/mftr-mttr-reserved-valid.s
Modified:
llvm/branches/release_50/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/branches/release_50/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
llvm/branches/release_50/lib/Target/Mips/MipsMTInstrFormats.td
llvm/branches/release_50/lib/Target/Mips/MipsMTInstrInfo.td
llvm/branches/release_50/lib/Target/Mips/MipsSchedule.td
llvm/branches/release_50/lib/Target/Mips/MipsScheduleGeneric.td
llvm/branches/release_50/lib/Target/Mips/MipsTargetStreamer.h
llvm/branches/release_50/test/MC/Disassembler/Mips/mt/valid-r2-el.txt
llvm/branches/release_50/test/MC/Disassembler/Mips/mt/valid-r2.txt
llvm/branches/release_50/test/MC/Mips/mt/invalid.s
llvm/branches/release_50/test/MC/Mips/mt/valid.s
Modified: llvm/branches/release_50/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=318386&r1=318385&r2=318386&view=diff
==
--- llvm/branches/release_50/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
(original)
+++ llvm/branches/release_50/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Thu
Nov 16 02:13:49 2017
@@ -304,6 +304,9 @@ class MipsAsmParser : public MCTargetAsm
bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
+ bool expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ const MCSubtargetInfo *STI);
+
bool reportParseError(Twine ErrorMsg);
bool reportParseError(SMLoc Loc, Twine ErrorMsg);
@@ -2511,6 +2514,16 @@ MipsAsmParser::tryExpandInstruction(MCIn
return expandSeq(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::SEQIMacro:
return expandSeqI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
+ case Mips::MFTC0: case Mips::MTTC0:
+ case Mips::MFTGPR: case Mips::MTTGPR:
+ case Mips::MFTLO: case Mips::MTTLO:
+ case Mips::MFTHI: case Mips::MTTHI:
+ case Mips::MFTACX: case Mips::MTTACX:
+ case Mips::MFTDSP: case Mips::MTTDSP:
+ case Mips::MFTC1: case Mips::MTTC1:
+ case Mips::MFTHC1: case Mips::MTTHC1:
+ case Mips::CFTC1: case Mips::CTTC1:
+return expandMXTRAlias(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
}
}
@@ -4882,6 +4895,212 @@ bool MipsAsmParser::expandSeqI(MCInst &I
return false;
}
+// Map the DSP accumulator and control register to the corresponding gpr
+// operand. Unlike the other alias, the m(f|t)t(lo|hi|acx) instructions
+// do not map the DSP registers contigously to gpr registers.
+static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) {
+ switch (Inst.getOpcode()) {
+case Mips::MFTLO:
+case Mips::MTTLO:
+ switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
+case Mips::AC0:
+ return Mips::ZERO;
+case Mips::AC1:
+ return Mips::A0;
+case Mips::AC2:
+ return Mips::T0;
+case Mips::AC3:
+ return Mips::T4;
+default:
+ llvm_unreachable("Unknown register for 'mttr' alias!");
+}
+case Mips::MFTHI:
+case Mips::MTTHI:
+ switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
+case Mips::AC0:
+ return Mips::AT;
+case Mips::AC1:
+ return Mips::A1;
+case Mips::AC2:
+ return Mips::T1;
+case Mips::AC3:
+ return Mips::T5;
+default:
+ llvm_unreachable("Unknown register for 'mtt
[llvm-branch-commits] [llvm-branch] r325876 - [mips] 6.0 Release notes
Author: sdardis Date: Fri Feb 23 02:19:00 2018 New Revision: 325876 URL: http://llvm.org/viewvc/llvm-project?rev=325876&view=rev Log: [mips] 6.0 Release notes Reviewers: atanasyan, arichardson, petarj, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D43573 Modified: llvm/branches/release_60/docs/ReleaseNotes.rst Modified: llvm/branches/release_60/docs/ReleaseNotes.rst URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/docs/ReleaseNotes.rst?rev=325876&r1=325875&r2=325876&view=diff == --- llvm/branches/release_60/docs/ReleaseNotes.rst (original) +++ llvm/branches/release_60/docs/ReleaseNotes.rst Fri Feb 23 02:19:00 2018 @@ -113,8 +113,44 @@ Changes to the Hexagon Target Changes to the MIPS Target -- - During this release ... +Fixed numerous bugs: +* fpowi on MIPS64 giving incorrect results when used with a negative integer. +* Usage of the asm 'c' constraint with the wrong datatype causing an + assert/crash. +* Fixed a conversion bug when using the DSP ASE. +* Fixed an inconsistency where objects were not marked as using the microMIPS as + when the micromips function attribute or the ".set micromips" directive was + used. +* Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot + filler, fixing a class of rare edge case bugs where the delay slot filler + would violate ISA restrictions. +* Fixed a crash when using a type of unknown size with gp relative addressing. +* Corrected the j macro for microMIPS. +* Corrected the encoding of movep for microMIPS32r6. +* Fixed an issue with the usage of insert instructions having an invalid set of + operands. +* Fixed an issue where TLS symbols where not marked as such. +* Enabled the usage of register scavanging with MSA, due to its' shorter offsets + for loads and stores. +* Corrected the ELF headers when using the DSP ASE. + +New features: + +* The long branch pass now generates some R6 specific instructions when + targeting MIPSR6. +* The delay slot filler now performs more branch conversions if delay slots + cannot be filled. +* The MIPS MT ASE is now fully supported. +* Added support for the ``lapc`` pseudo instruction. +* Improved the selection of multiple instructions (``dext``, ``nmadd``, + ``nmsub``). +* Further improved microMIPS codesize reduction. + +Deprecation notices: + +* microMIPS64R6 support was been deprecated since 5.0, and has now been + completely removed. Changes to the PowerPC Target - ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm-branch] r327751 - Backporting r325653:
Author: sdardis Date: Fri Mar 16 15:14:38 2018 New Revision: 327751 URL: http://llvm.org/viewvc/llvm-project?rev=327751&view=rev Log: Backporting r325653: r325653 | sdardis | 2018-02-21 00:06:53 + (Wed, 21 Feb 2018) | 31 lines [mips] Spectre variant two mitigation for MIPSR2 This patch provides mitigation for CVE-2017-5715, Spectre variant two, which affects the P5600 and P6600. It implements the LLVM part of -mindirect-jump=hazard. It is _not_ enabled by default for the P5600. The migitation strategy suggested by MIPS for these processors is to use hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard barrier variants of the 'jalr' and 'jr' instructions respectively. These instructions impede the execution of instruction stream until architecturally defined hazards (changes to the instruction stream, privileged registers which may affect execution) are cleared. These instructions in MIPS' designs are not speculated past. These instructions are used with the attribute +use-indirect-jump-hazard when branching indirectly and for indirect function calls. These instructions are defined by the MIPS32R2 ISA, so this mitigation method is not compatible with processors which implement an earlier revision of the MIPS ISA. Performance benchmarking of this option with -fpic and lld using -z hazardplt shows a difference of overall 10%~ time increase for the LLVM testsuite. Certain benchmarks such as methcall show a substantially larger increase in time due to their nature. Reviewers: atanasyan, zoran.jovanovic Differential Revision: https://reviews.llvm.org/D43486 Added: llvm/branches/release_50/test/CodeGen/Mips/indirect-jump-hazard/ llvm/branches/release_50/test/CodeGen/Mips/indirect-jump-hazard/calls.ll llvm/branches/release_50/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir llvm/branches/release_50/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir llvm/branches/release_50/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll llvm/branches/release_50/test/CodeGen/Mips/indirect-jump-hazard/long-branch.ll llvm/branches/release_50/test/CodeGen/Mips/indirect-jump-hazard/long-calls.ll llvm/branches/release_50/test/CodeGen/Mips/indirect-jump-hazard/unsupported-micromips.ll llvm/branches/release_50/test/CodeGen/Mips/indirect-jump-hazard/unsupported-mips32.ll Modified: llvm/branches/release_50/lib/Target/Mips/AsmParser/MipsAsmParser.cpp llvm/branches/release_50/lib/Target/Mips/MicroMips32r6InstrInfo.td llvm/branches/release_50/lib/Target/Mips/MicroMips64r6InstrInfo.td llvm/branches/release_50/lib/Target/Mips/MicroMipsInstrInfo.td llvm/branches/release_50/lib/Target/Mips/Mips.td llvm/branches/release_50/lib/Target/Mips/Mips32r6InstrInfo.td llvm/branches/release_50/lib/Target/Mips/Mips64InstrInfo.td llvm/branches/release_50/lib/Target/Mips/Mips64r6InstrInfo.td llvm/branches/release_50/lib/Target/Mips/MipsDSPInstrFormats.td llvm/branches/release_50/lib/Target/Mips/MipsInstrFormats.td llvm/branches/release_50/lib/Target/Mips/MipsInstrInfo.cpp llvm/branches/release_50/lib/Target/Mips/MipsInstrInfo.h llvm/branches/release_50/lib/Target/Mips/MipsInstrInfo.td llvm/branches/release_50/lib/Target/Mips/MipsLongBranch.cpp llvm/branches/release_50/lib/Target/Mips/MipsSubtarget.cpp llvm/branches/release_50/lib/Target/Mips/MipsSubtarget.h llvm/branches/release_50/test/CodeGen/Mips/tailcall/tailcall.ll Modified: llvm/branches/release_50/lib/Target/Mips/AsmParser/MipsAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=327751&r1=327750&r2=327751&view=diff == --- llvm/branches/release_50/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original) +++ llvm/branches/release_50/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Fri Mar 16 15:14:38 2018 @@ -5133,6 +5133,7 @@ unsigned MipsAsmParser::checkTargetMatch // It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction // and registers Rd and Base for microMIPS lwp instruction case Mips::JALR_HB: + case Mips::JALR_HB64: case Mips::JALRC_HB_MMR6: case Mips::JALRC_MMR6: if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) Modified: llvm/branches/release_50/lib/Target/Mips/MicroMips32r6InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=327751&r1=327750&r2=327751&view=diff == --- llvm/branches/release_50/lib/Target/Mips/MicroMips32r6InstrInfo.td (original) +++ llvm/branches/release_50/lib/Target/Mips/MicroMips32r6InstrInfo.td Fri Mar 16 15:14:38 2
[llvm-branch-commits] [cfe-branch] r327755 - Backporting 325651::
Author: sdardis
Date: Fri Mar 16 15:21:00 2018
New Revision: 327755
URL: http://llvm.org/viewvc/llvm-project?rev=327755&view=rev
Log:
Backporting 325651::
r325651 | sdardis | 2018-02-21 00:05:05 + (Wed, 21 Feb 2018) | 34 lines
[mips] Spectre variant two mitigation for MIPSR2
This patch provides mitigation for CVE-2017-5715, Spectre variant two,
which affects the P5600 and P6600. It provides the option
-mindirect-jump=hazard, which instructs the LLVM backend to replace
indirect branches with their hazard barrier variants.
This option is accepted when targeting MIPS revision two or later.
The migitation strategy suggested by MIPS for these processors is to
use two hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard
barrier variants of the 'jalr' and 'jr' instructions respectively.
These instructions impede the execution of instruction stream until
architecturally defined hazards (changes to the instruction stream,
privileged registers which may affect execution) are cleared. These
instructions in MIPS' designs are not speculated past.
These instructions are used with the option -mindirect-jump=hazard
when branching indirectly and for indirect function calls.
These instructions are defined by the MIPS32R2 ISA, so this mitigation
method is not compatible with processors which implement an earlier
revision of the MIPS ISA.
Implementation note: I've opted to provide this as an
-mindirect-jump={hazard,...} style option in case alternative
mitigation methods are required for other implementations of the MIPS
ISA in future, e.g. retpoline style solutions.
Reviewers: atanasyan
Differential Revision: https://reviews.llvm.org/D43487
Modified:
cfe/branches/release_50/include/clang/Basic/DiagnosticDriverKinds.td
cfe/branches/release_50/include/clang/Driver/Options.td
cfe/branches/release_50/lib/Basic/Targets.cpp
cfe/branches/release_50/lib/Driver/ToolChains/Arch/Mips.cpp
cfe/branches/release_50/lib/Driver/ToolChains/Arch/Mips.h
cfe/branches/release_50/test/Driver/mips-features.c
Modified: cfe/branches/release_50/include/clang/Basic/DiagnosticDriverKinds.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_50/include/clang/Basic/DiagnosticDriverKinds.td?rev=327755&r1=327754&r2=327755&view=diff
==
--- cfe/branches/release_50/include/clang/Basic/DiagnosticDriverKinds.td
(original)
+++ cfe/branches/release_50/include/clang/Basic/DiagnosticDriverKinds.td Fri
Mar 16 15:21:00 2018
@@ -280,6 +280,10 @@ def warn_target_unsupported_nanlegacy :
def warn_target_unsupported_compact_branches : Warning<
"ignoring '-mcompact-branches=' option because the '%0' architecture does
not"
" support it">, InGroup;
+def err_drv_unsupported_indirect_jump_opt : Error<
+ "'-mindirect-jump=%0' is unsupported with the '%1' architecture">;
+def err_drv_unknown_indirect_jump_opt : Error<
+ "unknown '-mindirect-jump=' option '%0'">;
def warn_drv_unable_to_find_directory_expected : Warning<
"unable to find %0 directory, expected to be in '%1'">,
Modified: cfe/branches/release_50/include/clang/Driver/Options.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_50/include/clang/Driver/Options.td?rev=327755&r1=327754&r2=327755&view=diff
==
--- cfe/branches/release_50/include/clang/Driver/Options.td (original)
+++ cfe/branches/release_50/include/clang/Driver/Options.td Fri Mar 16 15:21:00
2018
@@ -2016,6 +2016,9 @@ def mcheck_zero_division : Flag<["-"], "
def mno_check_zero_division : Flag<["-"], "mno-check-zero-division">,
Group;
def mcompact_branches_EQ : Joined<["-"], "mcompact-branches=">, Group;
+def mindirect_jump_EQ : Joined<["-"], "mindirect-jump=">,
+ Group,
+ HelpText<"Change indirect jump instructions to inhibit speculation">;
def mdsp : Flag<["-"], "mdsp">, Group;
def mno_dsp : Flag<["-"], "mno-dsp">, Group;
def mdspr2 : Flag<["-"], "mdspr2">, Group;
Modified: cfe/branches/release_50/lib/Basic/Targets.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_50/lib/Basic/Targets.cpp?rev=327755&r1=327754&r2=327755&view=diff
==
--- cfe/branches/release_50/lib/Basic/Targets.cpp (original)
+++ cfe/branches/release_50/lib/Basic/Targets.cpp Fri Mar 16 15:21:00 2018
@@ -8065,6 +8065,7 @@ class MipsTargetInfo : public TargetInfo
} DspRev;
bool HasMSA;
bool DisableMadd4;
+ bool UseIndirectJumpHazard;
protected:
bool HasFP64;
@@ -8075,7 +8076,8 @@ public:
: TargetInfo(Triple), IsMips16(false), IsMicromips(false),
IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false),
CanUseBSDABICalls(false), FloatA
[llvm-branch-commits] [lld] r327757 - Backporting r325647 and r325713:
Author: sdardis
Date: Fri Mar 16 15:28:08 2018
New Revision: 327757
URL: http://llvm.org/viewvc/llvm-project?rev=327757&view=rev
Log:
Backporting r325647 and r325713:
r325713 | sdardis | 2018-02-21 20:01:43 + (Wed, 21 Feb 2018) | 5 lines
[mips][lld] Address post commit review nit.
Address @ruiu's post commit review comment about a value which is intended
to be a unsigned 32 bit integer as using uint32_t rather than unsigned.
r325647 | sdardis | 2018-02-20 23:49:17 + (Tue, 20 Feb 2018) | 27 lines
[mips][lld] Spectre variant two mitigation for MIPSR2
This patch provides migitation for CVE-2017-5715, Spectre variant two,
which affects the P5600 and P6600. It implements the LLD part of
-z hazardplt. Like the Clang part of this patch, I have opted for that
specific option name in case alternative migitation methods are required
in the future.
The mitigation strategy suggested by MIPS for these processors is to use
hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard
barrier variants of the 'jalr' and 'jr' instructions respectively.
These instructions impede the execution of instruction stream until
architecturally defined hazards (changes to the instruction stream,
privileged registers which may affect execution) are cleared. These
instructions in MIPS' designs are not speculated past.
These instructions are defined by the MIPS32R2 ISA, so this mitigation
method is not compatible with processors which implement an earlier
revision of the MIPS ISA.
For LLD, this changes PLT stubs to use 'jalr.hb' and 'jr.hb'.
Reviewers: atanasyan, ruiu
Differential Revision: https://reviews.llvm.org/D43488
Modified:
lld/branches/release_50/ELF/Arch/Mips.cpp
lld/branches/release_50/ELF/Config.h
lld/branches/release_50/ELF/Driver.cpp
lld/branches/release_50/test/ELF/mips-plt-r6.s
Modified: lld/branches/release_50/ELF/Arch/Mips.cpp
URL:
http://llvm.org/viewvc/llvm-project/lld/branches/release_50/ELF/Arch/Mips.cpp?rev=327757&r1=327756&r2=327757&view=diff
==
--- lld/branches/release_50/ELF/Arch/Mips.cpp (original)
+++ lld/branches/release_50/ELF/Arch/Mips.cpp Fri Mar 16 15:28:08 2018
@@ -203,7 +203,8 @@ template void MIPS::w
write32(Buf + 16, 0x03e07825); // move $15, $31
write32(Buf + 20, 0x0018c082); // srl $24, $24, 2
- write32(Buf + 24, 0x0320f809); // jalr $25
+ uint32_t JalrInst = Config->ZHazardplt ? 0x0320fc09 : 0x0320f809;
+ write32(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
write32(Buf + 28, 0x2718fffe); // subu $24, $24, 2
uint64_t GotPlt = InX::GotPlt->getVA();
@@ -217,10 +218,14 @@ void MIPS::writePlt(uint8_t *Buf,
uint64_t PltEntryAddr, int32_t Index,
unsigned RelOff) const {
const endianness E = ELFT::TargetEndianness;
+ uint32_t JrInst = isMipsR6()
+? (Config->ZHazardplt ? 0x03200409 : 0x0329)
+: (Config->ZHazardplt ? 0x03200408 : 0x0328);
+
write32(Buf, 0x3c0f); // lui $15, %hi(.got.plt entry)
write32(Buf + 4, 0x8df9); // l[wd] $25, %lo(.got.plt entry)($15)
// jr$25
- write32(Buf + 8, isMipsR6() ? 0x0329 : 0x0328);
+ write32(Buf + 8, JrInst); // jr $25 / jr.hb $25
write32(Buf + 12, 0x25f8); // addiu $24, $15, %lo(.got.plt entry)
writeMipsHi16(Buf, GotPltEntryAddr);
writeMipsLo16(Buf + 4, GotPltEntryAddr);
Modified: lld/branches/release_50/ELF/Config.h
URL:
http://llvm.org/viewvc/llvm-project/lld/branches/release_50/ELF/Config.h?rev=327757&r1=327756&r2=327757&view=diff
==
--- lld/branches/release_50/ELF/Config.h (original)
+++ lld/branches/release_50/ELF/Config.h Fri Mar 16 15:28:08 2018
@@ -148,6 +148,7 @@ struct Configuration {
bool WarnMissingEntry;
bool ZCombreloc;
bool ZExecstack;
+ bool ZHazardplt;
bool ZNocopyreloc;
bool ZNodelete;
bool ZNodlopen;
Modified: lld/branches/release_50/ELF/Driver.cpp
URL:
http://llvm.org/viewvc/llvm-project/lld/branches/release_50/ELF/Driver.cpp?rev=327757&r1=327756&r2=327757&view=diff
==
--- lld/branches/release_50/ELF/Driver.cpp (original)
+++ lld/branches/release_50/ELF/Driver.cpp Fri Mar 16 15:28:08 2018
@@ -682,6 +682,7 @@ void LinkerDriver::readConfigs(opt::Inpu
Config->WarnCommon = Args.hasArg(OPT_warn_common);
Config->ZCombreloc = !hasZOption(Args, "nocombreloc");
Config->ZExecstack = hasZOption(Args, "execstack");
+ Config->ZHazardplt = hasZOption(Args, "h
[llvm-branch-commits] [llvm-branch] r329798 - Merging r325653 with test fixups:
Author: sdardis
Date: Wed Apr 11 05:55:10 2018
New Revision: 329798
URL: http://llvm.org/viewvc/llvm-project?rev=329798&view=rev
Log:
Merging r325653 with test fixups:
r325653 | sdardis | 2018-02-21 00:06:53 + (Wed, 21 Feb 2018) | 31 lines
[mips] Spectre variant two mitigation for MIPSR2
This patch provides mitigation for CVE-2017-5715, Spectre variant two,
which affects the P5600 and P6600. It implements the LLVM part of
-mindirect-jump=hazard. It is _not_ enabled by default for the P5600.
The migitation strategy suggested by MIPS for these processors is to use
hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard
barrier variants of the 'jalr' and 'jr' instructions respectively.
These instructions impede the execution of instruction stream until
architecturally defined hazards (changes to the instruction stream,
privileged registers which may affect execution) are cleared. These
instructions in MIPS' designs are not speculated past.
These instructions are used with the attribute +use-indirect-jump-hazard
when branching indirectly and for indirect function calls.
These instructions are defined by the MIPS32R2 ISA, so this mitigation
method is not compatible with processors which implement an earlier
revision of the MIPS ISA.
Performance benchmarking of this option with -fpic and lld using
-z hazardplt shows a difference of overall 10%~ time increase
for the LLVM testsuite. Certain benchmarks such as methcall show a
substantially larger increase in time due to their nature.
Reviewers: atanasyan, zoran.jovanovic
Differential Revision: https://reviews.llvm.org/D43486
Added:
llvm/branches/release_60/test/CodeGen/Mips/indirect-jump-hazard/
llvm/branches/release_60/test/CodeGen/Mips/indirect-jump-hazard/calls.ll
llvm/branches/release_60/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir
llvm/branches/release_60/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir
llvm/branches/release_60/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll
llvm/branches/release_60/test/CodeGen/Mips/indirect-jump-hazard/long-branch.ll
llvm/branches/release_60/test/CodeGen/Mips/indirect-jump-hazard/long-calls.ll
llvm/branches/release_60/test/CodeGen/Mips/indirect-jump-hazard/unsupported-micromips.ll
llvm/branches/release_60/test/CodeGen/Mips/indirect-jump-hazard/unsupported-mips32.ll
Modified:
llvm/branches/release_60/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/branches/release_60/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/branches/release_60/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/branches/release_60/lib/Target/Mips/Mips.td
llvm/branches/release_60/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/branches/release_60/lib/Target/Mips/Mips64InstrInfo.td
llvm/branches/release_60/lib/Target/Mips/Mips64r6InstrInfo.td
llvm/branches/release_60/lib/Target/Mips/MipsDSPInstrFormats.td
llvm/branches/release_60/lib/Target/Mips/MipsInstrFormats.td
llvm/branches/release_60/lib/Target/Mips/MipsInstrInfo.cpp
llvm/branches/release_60/lib/Target/Mips/MipsInstrInfo.td
llvm/branches/release_60/lib/Target/Mips/MipsLongBranch.cpp
llvm/branches/release_60/lib/Target/Mips/MipsSubtarget.cpp
llvm/branches/release_60/lib/Target/Mips/MipsSubtarget.h
Modified: llvm/branches/release_60/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=329798&r1=329797&r2=329798&view=diff
==
--- llvm/branches/release_60/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
(original)
+++ llvm/branches/release_60/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Wed
Apr 11 05:55:10 2018
@@ -5136,6 +5136,7 @@ unsigned MipsAsmParser::checkTargetMatch
// It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb
instruction
// and registers Rd and Base for microMIPS lwp instruction
case Mips::JALR_HB:
+ case Mips::JALR_HB64:
case Mips::JALRC_HB_MMR6:
case Mips::JALRC_MMR6:
if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())
Modified: llvm/branches/release_60/lib/Target/Mips/MicroMips32r6InstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=329798&r1=329797&r2=329798&view=diff
==
--- llvm/branches/release_60/lib/Target/Mips/MicroMips32r6InstrInfo.td
(original)
+++ llvm/branches/release_60/lib/Target/Mips/MicroMips32r6InstrInfo.td Wed Apr
11 05:55:10 2018
@@ -1886,6 +1886,12 @@ let AddedComplexity = 41 in {
def TAILCALL_MMR6 : TailCall, ISA_MICROMIPS32R6;
+def TAILCALLREG_MMR6 : TailCallReg, ISA_MICROMIPS32R6;
+
+def PseudoIndir
[llvm-branch-commits] [cfe-branch] r329799 - Merging r325651:
Author: sdardis
Date: Wed Apr 11 05:58:50 2018
New Revision: 329799
URL: http://llvm.org/viewvc/llvm-project?rev=329799&view=rev
Log:
Merging r325651:
r325651 | sdardis | 2018-02-21 00:05:05 + (Wed, 21 Feb 2018) | 34 lines
[mips] Spectre variant two mitigation for MIPSR2
This patch provides mitigation for CVE-2017-5715, Spectre variant two,
which affects the P5600 and P6600. It provides the option
-mindirect-jump=hazard, which instructs the LLVM backend to replace
indirect branches with their hazard barrier variants.
This option is accepted when targeting MIPS revision two or later.
The migitation strategy suggested by MIPS for these processors is to
use two hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard
barrier variants of the 'jalr' and 'jr' instructions respectively.
These instructions impede the execution of instruction stream until
architecturally defined hazards (changes to the instruction stream,
privileged registers which may affect execution) are cleared. These
instructions in MIPS' designs are not speculated past.
These instructions are used with the option -mindirect-jump=hazard
when branching indirectly and for indirect function calls.
These instructions are defined by the MIPS32R2 ISA, so this mitigation
method is not compatible with processors which implement an earlier
revision of the MIPS ISA.
Implementation note: I've opted to provide this as an
-mindirect-jump={hazard,...} style option in case alternative
mitigation methods are required for other implementations of the MIPS
ISA in future, e.g. retpoline style solutions.
Reviewers: atanasyan
Differential Revision: https://reviews.llvm.org/D43487
Added:
cfe/branches/release_60/test/Driver/mips-indirect-branch.c
Modified:
cfe/branches/release_60/include/clang/Basic/DiagnosticDriverKinds.td
cfe/branches/release_60/include/clang/Driver/Options.td
cfe/branches/release_60/lib/Basic/Targets/Mips.h
cfe/branches/release_60/lib/Driver/ToolChains/Arch/Mips.cpp
cfe/branches/release_60/lib/Driver/ToolChains/Arch/Mips.h
cfe/branches/release_60/test/Driver/mips-features.c
Modified: cfe/branches/release_60/include/clang/Basic/DiagnosticDriverKinds.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_60/include/clang/Basic/DiagnosticDriverKinds.td?rev=329799&r1=329798&r2=329799&view=diff
==
--- cfe/branches/release_60/include/clang/Basic/DiagnosticDriverKinds.td
(original)
+++ cfe/branches/release_60/include/clang/Basic/DiagnosticDriverKinds.td Wed
Apr 11 05:58:50 2018
@@ -326,6 +326,10 @@ def warn_drv_unsupported_abicalls : Warn
"ignoring '-mabicalls' option as it cannot be used with "
"non position-independent code and the N64 ABI">,
InGroup;
+def err_drv_unsupported_indirect_jump_opt : Error<
+ "'-mindirect-jump=%0' is unsupported with the '%1' architecture">;
+def err_drv_unknown_indirect_jump_opt : Error<
+ "unknown '-mindirect-jump=' option '%0'">;
def warn_drv_unable_to_find_directory_expected : Warning<
"unable to find %0 directory, expected to be in '%1'">,
Modified: cfe/branches/release_60/include/clang/Driver/Options.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_60/include/clang/Driver/Options.td?rev=329799&r1=329798&r2=329799&view=diff
==
--- cfe/branches/release_60/include/clang/Driver/Options.td (original)
+++ cfe/branches/release_60/include/clang/Driver/Options.td Wed Apr 11 05:58:50
2018
@@ -1992,6 +1992,9 @@ def mbranch_likely : Flag<["-"], "mbranc
IgnoredGCCCompat;
def mno_branch_likely : Flag<["-"], "mno-branch-likely">, Group,
IgnoredGCCCompat;
+def mindirect_jump_EQ : Joined<["-"], "mindirect-jump=">,
+ Group,
+ HelpText<"Change indirect jump instructions to inhibit speculation">;
def mdsp : Flag<["-"], "mdsp">, Group;
def mno_dsp : Flag<["-"], "mno-dsp">, Group;
def mdspr2 : Flag<["-"], "mdspr2">, Group;
Modified: cfe/branches/release_60/lib/Basic/Targets/Mips.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_60/lib/Basic/Targets/Mips.h?rev=329799&r1=329798&r2=329799&view=diff
==
--- cfe/branches/release_60/lib/Basic/Targets/Mips.h (original)
+++ cfe/branches/release_60/lib/Basic/Targets/Mips.h Wed Apr 11 05:58:50 2018
@@ -54,6 +54,7 @@ class LLVM_LIBRARY_VISIBILITY MipsTarget
enum DspRevEnum { NoDSP, DSP1, DSP2 } DspRev;
bool HasMSA;
bool DisableMadd4;
+ bool UseIndirectJumpHazard;
protected:
bool HasFP64;
@@ -64,7 +65,8 @@ public:
: TargetInfo(Triple), IsMips16(false), IsMicromips(false),
IsNan2008(false), IsAbs2008(false), IsSingleFloat(false),
IsNoABICalls(false), CanUseBSDABICalls(
[llvm-branch-commits] [lld] r329800 - Merging r325647, r325713:
Author: sdardis
Date: Wed Apr 11 06:03:33 2018
New Revision: 329800
URL: http://llvm.org/viewvc/llvm-project?rev=329800&view=rev
Log:
Merging r325647, r325713:
r325713 | sdardis | 2018-02-21 20:01:43 + (Wed, 21 Feb 2018) | 5 lines
[mips][lld] Address post commit review nit.
Address @ruiu's post commit review comment about a value which is intended
to be a unsigned 32 bit integer as using uint32_t rather than unsigned.
r325647 | sdardis | 2018-02-20 23:49:17 + (Tue, 20 Feb 2018) | 27 lines
[mips][lld] Spectre variant two mitigation for MIPSR2
This patch provides migitation for CVE-2017-5715, Spectre variant two,
which affects the P5600 and P6600. It implements the LLD part of
-z hazardplt. Like the Clang part of this patch, I have opted for that
specific option name in case alternative migitation methods are required
in the future.
The mitigation strategy suggested by MIPS for these processors is to use
hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard
barrier variants of the 'jalr' and 'jr' instructions respectively.
These instructions impede the execution of instruction stream until
architecturally defined hazards (changes to the instruction stream,
privileged registers which may affect execution) are cleared. These
instructions in MIPS' designs are not speculated past.
These instructions are defined by the MIPS32R2 ISA, so this mitigation
method is not compatible with processors which implement an earlier
revision of the MIPS ISA.
For LLD, this changes PLT stubs to use 'jalr.hb' and 'jr.hb'.
Reviewers: atanasyan, ruiu
Differential Revision: https://reviews.llvm.org/D43488
Modified:
lld/branches/release_60/ELF/Arch/Mips.cpp
lld/branches/release_60/ELF/Config.h
lld/branches/release_60/ELF/Driver.cpp
lld/branches/release_60/test/ELF/mips-26-n32-n64.s
lld/branches/release_60/test/ELF/mips-plt-r6.s
Modified: lld/branches/release_60/ELF/Arch/Mips.cpp
URL:
http://llvm.org/viewvc/llvm-project/lld/branches/release_60/ELF/Arch/Mips.cpp?rev=329800&r1=329799&r2=329800&view=diff
==
--- lld/branches/release_60/ELF/Arch/Mips.cpp (original)
+++ lld/branches/release_60/ELF/Arch/Mips.cpp Wed Apr 11 06:03:33 2018
@@ -296,7 +296,8 @@ template void MIPS::w
write32(Buf + 20, 0x0018c082); // srl $24, $24, 2
}
- write32(Buf + 24, 0x0320f809); // jalr $25
+ uint32_t JalrInst = Config->ZHazardplt ? 0x0320fc09 : 0x0320f809;
+ write32(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
write32(Buf + 28, 0x2718fffe); // subu $24, $24, 2
uint64_t GotPlt = InX::GotPlt->getVA();
@@ -330,9 +331,12 @@ void MIPS::writePlt(uint8_t *Buf,
return;
}
+ uint32_t JrInst = isMipsR6() ? (Config->ZHazardplt ? 0x03200409 : 0x0329)
+ : (Config->ZHazardplt ? 0x03200408 :
0x0328);
+
write32(Buf, 0x3c0f); // lui $15, %hi(.got.plt entry)
write32(Buf + 4, 0x8df9); // l[wd] $25, %lo(.got.plt entry)($15)
- write32(Buf + 8, isMipsR6() ? 0x0329 : 0x0328); // jr $25
+ write32(Buf + 8, JrInst); // jr $25 / jr.hb $25
write32(Buf + 12, 0x25f8); // addiu $24, $15, %lo(.got.plt entry)
writeRelocation(Buf, GotPltEntryAddr + 0x8000, 16, 16);
writeRelocation(Buf + 4, GotPltEntryAddr, 16, 0);
Modified: lld/branches/release_60/ELF/Config.h
URL:
http://llvm.org/viewvc/llvm-project/lld/branches/release_60/ELF/Config.h?rev=329800&r1=329799&r2=329800&view=diff
==
--- lld/branches/release_60/ELF/Config.h (original)
+++ lld/branches/release_60/ELF/Config.h Wed Apr 11 06:03:33 2018
@@ -151,6 +151,7 @@ struct Configuration {
bool WarnMissingEntry;
bool ZCombreloc;
bool ZExecstack;
+ bool ZHazardplt;
bool ZNocopyreloc;
bool ZNodelete;
bool ZNodlopen;
Modified: lld/branches/release_60/ELF/Driver.cpp
URL:
http://llvm.org/viewvc/llvm-project/lld/branches/release_60/ELF/Driver.cpp?rev=329800&r1=329799&r2=329800&view=diff
==
--- lld/branches/release_60/ELF/Driver.cpp (original)
+++ lld/branches/release_60/ELF/Driver.cpp Wed Apr 11 06:03:33 2018
@@ -668,6 +668,7 @@ void LinkerDriver::readConfigs(opt::Inpu
Config->WarnCommon = Args.hasArg(OPT_warn_common);
Config->ZCombreloc = !hasZOption(Args, "nocombreloc");
Config->ZExecstack = hasZOption(Args, "execstack");
+ Config->ZHazardplt = hasZOption(Args, "hazardplt");
Config->ZNocopyreloc = hasZOption(Args, "nocopyreloc");
Config->ZNodelete = hasZOption(Args, "nodelete");
Config->ZNodlopen = hasZOption(Args, "nod
