[llvm-branch-commits] [libcxx] release/19.x: [libcxx] don't `#include ` if wide chars aren't enabled (#99911) (PR #106788)

2024-08-30 Thread Ties Stuij via llvm-branch-commits 

https://github.com/stuij approved this pull request.

Yup, makes sense to cherry-pick.

https://github.com/llvm/llvm-project/pull/106788
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[llvm-branch-commits] [clang] 56dcb10 - Add Cortex-X1C to Clang LLVM 14 release notes

2022-02-08 Thread Ties Stuij via llvm-branch-commits 

Author: Ties Stuij
Date: 2022-02-08T17:49:28Z
New Revision: 56dcb10a9942c206d53a59abd66c2207a01b39fa

URL: 
https://github.com/llvm/llvm-project/commit/56dcb10a9942c206d53a59abd66c2207a01b39fa
DIFF: 
https://github.com/llvm/llvm-project/commit/56dcb10a9942c206d53a59abd66c2207a01b39fa.diff

LOG: Add Cortex-X1C to Clang LLVM 14 release notes

Reviewed By: amilendra

Differential Revision: https://reviews.llvm.org/D119008

Added: 


Modified: 
clang/docs/ReleaseNotes.rst

Removed: 




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index a58e3fcd4f42c..caa2349f9d860 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -101,6 +101,10 @@ Modified Compiler Flags
   - RISC-V SiFive S51 (``sifive-s51``).
   - RISC-V SiFive S54 (``sifive-s54``).
   - RISC-V SiFive S76 (``sifive-s76``).
+  - Arm Cortex-X1C (``cortex-x1c``)
+  - Arm Cortex-X2 (``cortex-x2``)
+  - Arm Cortex-A510 (``cortex-a510``)
+  - Arm Cortex-A710 (``cortex-a710``)
 
 - Support has been added for the following architectures (``-march`` 
identifiers in parentheses):
 
@@ -283,11 +287,6 @@ DWARF Support in Clang
 Arm and AArch64 Support in Clang
 
 
-- Support has been added for the following processors (command-line 
identifiers in parentheses):
-  - Arm Cortex-A510 (``cortex-a510``)
-  - Arm Cortex-X2 (``cortex-x2``)
-  - Arm Cortex-A710 (``cortex-A710``)
-
 - The -mtune flag is no longer ignored for AArch64. It is now possible to
   tune code generation for a particular CPU with -mtune without setting any
   architectural features. For example, compiling with



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