[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.162 - 1.163
---
Log message:
If the false case is the current basic block, then this is a self loop.
We do not want to emit Loop: ... brcond Out; br Loop, as it adds an extra
instruction in the loop. Instead, invert the condition and emit
Loop: ... br!cond Loop; br Out.
Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.
---
Diffs of the changes: (+9 -0)
SelectionDAGISel.cpp |9 +
1 files changed, 9 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.162
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.163
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.162Wed Feb 15
16:12:35 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Feb 16 02:27:55 2006
@@ -562,6 +562,15 @@
} else {
std::vectorSDOperand Ops;
Ops.push_back(getRoot());
+ // If the false case is the current basic block, then this is a self
+ // loop. We do not want to emit Loop: ... brcond Out; br Loop, as it
+ // adds an extra instruction in the loop. Instead, invert the
+ // condition and emit Loop: ... br!cond Loop; br Out.
+ if (CurMBB == Succ1MBB) {
+std::swap(Succ0MBB, Succ1MBB);
+SDOperand True = DAG.getConstant(1, Cond.getValueType());
+Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
+ }
Ops.push_back(Cond);
Ops.push_back(DAG.getBasicBlock(Succ0MBB));
Ops.push_back(DAG.getBasicBlock(Succ1MBB));
___
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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64AsmPrinter.cpp
Changes in directory llvm/lib/Target/IA64:
IA64AsmPrinter.cpp updated: 1.22 - 1.23
---
Log message:
distinguish between objects and register names, now we can have stuff
with names like f84, in6 etc etc.
this should fix one or two tests
---
Diffs of the changes: (+12 -6)
IA64AsmPrinter.cpp | 18 --
1 files changed, 12 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/IA64/IA64AsmPrinter.cpp
diff -u llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.22
llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.23
--- llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.22Sun Jan 22 17:37:17 2006
+++ llvm/lib/Target/IA64/IA64AsmPrinter.cpp Thu Feb 16 07:12:57 2006
@@ -235,10 +235,16 @@
if (Needfptr)
O @fptr(;
O Mang-getValueName(MO.getGlobal());
-if (Needfptr)
- O ); // close fptr(
-if (!isBRCALLinsn)
- O ); // close ltoff(
+
+if (Needfptr !isBRCALLinsn)
+ O #)); // close both fptr( and ltoff(
+else {
+ if (Needfptr)
+O #); // close only fptr(
+ if (!isBRCALLinsn)
+O #); // close only ltoff(
+}
+
int Offset = MO.getOffset();
if (Offset 0)
O + Offset;
@@ -293,11 +299,11 @@
I-hasWeakLinkage() /* FIXME: Verify correct */)) {
SwitchSection(.data, I);
if (I-hasInternalLinkage()) {
- O \t.lcomm name , TD.getTypeSize(C-getType())
+ O \t.lcomm name #, TD.getTypeSize(C-getType())
, (1 Align);
O \t\t// ;
} else {
- O \t.common name , TD.getTypeSize(C-getType())
+ O \t.common name #, TD.getTypeSize(C-getType())
, (1 Align);
O \t\t// ;
}
___
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[llvm-commits] CVS: llvm-poolalloc/runtime/FL2Allocator/PoolAllocator.cpp
Changes in directory llvm-poolalloc/runtime/FL2Allocator:
PoolAllocator.cpp updated: 1.50 - 1.51
---
Log message:
some programs call memalign, so there should be one
---
Diffs of the changes: (+7 -0)
PoolAllocator.cpp |7 +++
1 files changed, 7 insertions(+)
Index: llvm-poolalloc/runtime/FL2Allocator/PoolAllocator.cpp
diff -u llvm-poolalloc/runtime/FL2Allocator/PoolAllocator.cpp:1.50
llvm-poolalloc/runtime/FL2Allocator/PoolAllocator.cpp:1.51
--- llvm-poolalloc/runtime/FL2Allocator/PoolAllocator.cpp:1.50 Fri May 27
15:46:20 2005
+++ llvm-poolalloc/runtime/FL2Allocator/PoolAllocator.cpp Thu Feb 16
09:50:09 2006
@@ -854,6 +854,13 @@
return poolalloc_internal(Pool, NumBytes);
}
+void *poolmemalign(PoolTyNormalPoolTraits *Pool,
+ unsigned Alignment, unsigned NumBytes) {
+ //punt and use pool alloc.
+ //I don't know if this is safe or breaks any assumptions in the runtime
+ intptr_t base = (intptr_t)poolalloc_internal(Pool, NumBytes + Alignment - 1);
+ return (void*)((base + (Alignment - 1)) ~((intptr_t)Alignment -1));
+}
void poolfree(PoolTyNormalPoolTraits *Pool, void *Node) {
DO_IF_FORCE_MALLOCFREE(free(Node); return);
___
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
Changes in directory llvm/lib/Transforms/Scalar:
LoopUnswitch.cpp updated: 1.25 - 1.26
---
Log message:
Change SplitBlock to increment a BasicBlock::iterator, not an Instruction*.
Apparently they do different things :)
This fixes a testcase that nate reduced from spass.
Also included are a couple minor code changes that don't affect the generated
code at all.
---
Diffs of the changes: (+27 -23)
LoopUnswitch.cpp | 50 +++---
1 files changed, 27 insertions(+), 23 deletions(-)
Index: llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
diff -u llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.25
llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.26
--- llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.25Wed Feb 15 22:07:37 2006
+++ llvm/lib/Transforms/Scalar/LoopUnswitch.cpp Thu Feb 16 13:36:22 2006
@@ -397,9 +397,10 @@
/// the loop info is updated.
///
BasicBlock *LoopUnswitch::SplitBlock(BasicBlock *Old, Instruction *SplitPt) {
- while (isaPHINode(SplitPt))
-++SplitPt;
- BasicBlock *New = Old-splitBasicBlock(SplitPt, Old-getName()+.split);
+ BasicBlock::iterator SplitIt = SplitPt;
+ while (isaPHINode(SplitIt))
+++SplitIt;
+ BasicBlock *New = Old-splitBasicBlock(SplitIt, Old-getName()+.split);
// The new block lives in whichever loop the old one did.
if (Loop *L = LI-getLoopFor(Old))
@@ -703,27 +704,30 @@
// Haha, this loop could be unswitched. Get it? The unswitch pass could
// unswitch itself. Amazing.
for (unsigned i = 0, e = Users.size(); i != e; ++i)
-if (Instruction *U = castInstruction(Users[i]))
- if (L-contains(U-getParent()))
-if (IsEqual) {
- U-replaceUsesOfWith(LIC, Val);
-} else if (NotVal) {
- U-replaceUsesOfWith(LIC, NotVal);
-} else {
- // If we know that LIC is not Val, use this info to simplify code.
- if (SwitchInst *SI = dyn_castSwitchInst(U)) {
-for (unsigned i = 1, e = SI-getNumCases(); i != e; ++i) {
- if (SI-getCaseValue(i) == Val) {
-// Found a dead case value. Don't remove PHI nodes in the
-// successor if they become single-entry, those PHI nodes may
-// be in the Users list.
-SI-getSuccessor(i)-removePredecessor(SI-getParent(), true);
-SI-removeCase(i);
-break;
- }
+if (Instruction *U = castInstruction(Users[i])) {
+ if (!L-contains(U-getParent()))
+continue;
+
+ if (IsEqual) {
+U-replaceUsesOfWith(LIC, Val);
+ } else if (NotVal) {
+U-replaceUsesOfWith(LIC, NotVal);
+ } else {
+// If we know that LIC is not Val, use this info to simplify code.
+if (SwitchInst *SI = dyn_castSwitchInst(U)) {
+ for (unsigned i = 1, e = SI-getNumCases(); i != e; ++i) {
+if (SI-getCaseValue(i) == Val) {
+ // Found a dead case value. Don't remove PHI nodes in the
+ // successor if they become single-entry, those PHI nodes may
+ // be in the Users list.
+ SI-getSuccessor(i)-removePredecessor(SI-getParent(), true);
+ SI-removeCase(i);
+ break;
}
}
-
- // TODO: We could simplify stuff like X == C.
}
+
+// TODO: We could simplify stuff like X == C.
+ }
+}
}
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.233 - 1.234
---
Log message:
MOVAPSrr and MOVAPDrr instruction format should be MRMSrcReg.
---
Diffs of the changes: (+2 -2)
X86InstrInfo.td |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.233
llvm/lib/Target/X86/X86InstrInfo.td:1.234
--- llvm/lib/Target/X86/X86InstrInfo.td:1.233 Tue Feb 14 18:31:03 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Thu Feb 16 13:34:41 2006
@@ -3013,10 +3013,10 @@
// XMM Packed Floating point support (requires SSE / SSE2)
//===--===//
-def MOVAPSrr : I0x28, MRMSrcMem, (ops V4F4:$dst, V4F4:$src),
+def MOVAPSrr : I0x28, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
movaps {$src, $dst|$dst, $src}, [],
Requires[HasSSE1], TB;
-def MOVAPDrr : I0x28, MRMSrcMem, (ops V2F8:$dst, V2F8:$src),
+def MOVAPDrr : I0x28, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
movapd {$src, $dst|$dst, $src}, [],
Requires[HasSSE2], TB, OpSize;
___
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[llvm-commits] CVS: llvm/tools/llc/Makefile
Changes in directory llvm/tools/llc: Makefile updated: 1.78 - 1.79 --- Log message: remove support for the skeleton target --- Diffs of the changes: (+0 -5) Makefile |5 - 1 files changed, 5 deletions(-) Index: llvm/tools/llc/Makefile diff -u llvm/tools/llc/Makefile:1.78 llvm/tools/llc/Makefile:1.79 --- llvm/tools/llc/Makefile:1.78Sun Feb 5 02:30:45 2006 +++ llvm/tools/llc/Makefile Thu Feb 16 15:10:57 2006 @@ -23,11 +23,6 @@ USEDLIBS += LLVMCBackend endif -# Check for Skeleton target -ifneq ($(strip $(filter Skeleton,$(TARGETS_TO_BUILD))),) -USEDLIB += LLVMSkeleton -endif - # Check for Sparc target ifneq ($(strip $(filter SparcV9,$(TARGETS_TO_BUILD))),) USEDLIBS += \ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.102 - 1.103
---
Log message:
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
---
Diffs of the changes: (+17 -35)
DAGCombiner.cpp | 52 +---
1 files changed, 17 insertions(+), 35 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.102
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.103
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.102 Thu Feb 16 02:02:36 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Feb 16 15:11:51 2006
@@ -98,6 +98,18 @@
DAG.DeleteNode(N);
return SDOperand(N, 0);
}
+
+bool DemandedBitsAreZero(SDOperand Op, uint64_t DemandedMask,
+ SDOperand Old, SDOperand New) const {
+ TargetLowering::TargetLoweringOpt TLO(DAG);
+ uint64_t KnownZero, KnownOne;
+ if (TLI.SimplifyDemandedBits(Op, DemandedMask, KnownZero, KnownOne,
TLO)){
+Old = TLO.Old;
+New = TLO.New;
+return true;
+ }
+ return false;
+}
SDOperand CombineTo(SDNode *N, SDOperand Res) {
std::vectorSDOperand To;
@@ -897,12 +909,8 @@
if (N1C N1C-isAllOnesValue())
return N0;
// if (and x, c) is known to be zero, return 0
- if (N1C TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL
(64-OpSizeInBits)))
+ if (N1C TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
return DAG.getConstant(0, VT);
- // fold (and x, c) - x iff (x ~c) == 0
- if (N1C
- TLI.MaskedValueIsZero(N0, ~N1C-getValue() (~0ULL(64-OpSizeInBits
-return N0;
// reassociate and
SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
if (RAND.Val != 0)
@@ -984,38 +992,12 @@
}
// fold (and (sign_extend_inreg x, i16 to i32), 1) - (and x, 1)
// fold (and (sra)) - (and (srl)) when possible.
- if (TLI.DemandedBitsAreZero(SDOperand(N, 0), ~0ULL (64-OpSizeInBits),
Old,
- New, DAG)) {
+ if (DemandedBitsAreZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT), Old,
+ New)) {
WorkList.push_back(N);
CombineTo(Old.Val, New);
return SDOperand();
}
- // FIXME: DemandedBitsAreZero cannot currently handle AND with non-constant
- // RHS and propagate known cleared bits to LHS. For this reason, we must
keep
- // this fold, for now, for the following testcase:
- //
- //int %test2(uint %mode.0.i.0) {
- // %tmp.79 = cast uint %mode.0.i.0 to int
- // %tmp.80 = shr int %tmp.79, ubyte 15
- // %tmp.81 = shr uint %mode.0.i.0, ubyte 16
- // %tmp.82 = cast uint %tmp.81 to int
- // %tmp.83 = and int %tmp.80, %tmp.82
- // ret int %tmp.83
- //}
- // fold (and (sra)) - (and (srl)) when possible.
- if (N0.getOpcode() == ISD::SRA N0.Val-hasOneUse()) {
-if (ConstantSDNode *N01C = dyn_castConstantSDNode(N0.getOperand(1))) {
- // If the RHS of the AND has zeros where the sign bits of the SRA will
- // land, turn the SRA into an SRL.
- if (TLI.MaskedValueIsZero(N1, (~0ULL (OpSizeInBits-N01C-getValue()))
-(~0ULL(64-OpSizeInBits {
-WorkList.push_back(N);
-CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
- N0.getOperand(1)));
-return SDOperand();
- }
-}
- }
// fold (zext_inreg (extload x)) - (zextload x)
if (N0.getOpcode() == ISD::EXTLOAD) {
MVT::ValueType EVT = castVTSDNode(N0.getOperand(3))-getVT();
@@ -1298,8 +1280,8 @@
// if (shl x, c) is known to be zero, return 0
if (N1C TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL
(64-OpSizeInBits)))
return DAG.getConstant(0, VT);
- if (N1C TLI.DemandedBitsAreZero(SDOperand(N,0), ~0ULL
(64-OpSizeInBits),
- Old, New, DAG)) {
+ if (N1C DemandedBitsAreZero(SDOperand(N,0), ~0ULL (64-OpSizeInBits),
+ Old, New)) {
WorkList.push_back(N);
CombineTo(Old.Val, New);
return SDOperand();
___
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[llvm-commits] CVS: llvm/configure
Changes in directory llvm:
configure updated: 1.211 - 1.212
---
Log message:
remove skeleton target
---
Diffs of the changes: (+1 -2)
configure |3 +--
1 files changed, 1 insertion(+), 2 deletions(-)
Index: llvm/configure
diff -u llvm/configure:1.211 llvm/configure:1.212
--- llvm/configure:1.211Wed Feb 15 01:56:38 2006
+++ llvm/configure Thu Feb 16 15:12:54 2006
@@ -3078,7 +3078,7 @@
enableval=all
fi;
case $enableval in
- all) TARGETS_TO_BUILD=X86 Sparc SparcV9 PowerPC Alpha IA64 Skeleton ;;
+ all) TARGETS_TO_BUILD=X86 Sparc SparcV9 PowerPC Alpha IA64 ;;
host-only)
case $llvm_cv_target_arch in
x86) TARGETS_TO_BUILD=X86 ;;
@@ -3100,7 +3100,6 @@
powerpc) TARGETS_TO_BUILD=PowerPC $TARGETS_TO_BUILD ;;
alpha) TARGETS_TO_BUILD=Alpha $TARGETS_TO_BUILD ;;
ia64)TARGETS_TO_BUILD=IA64 $TARGETS_TO_BUILD ;;
-skeleton)TARGETS_TO_BUILD=Skeleton $TARGETS_TO_BUILD;;
*) { { echo $as_me:$LINENO: error: Unrecognized target $a_target 5
echo $as_me: error: Unrecognized target $a_target 2;}
{ (exit 1); exit 1; }; } ;;
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[llvm-commits] CVS: llvm/autoconf/configure.ac
Changes in directory llvm/autoconf:
configure.ac updated: 1.209 - 1.210
---
Log message:
don't build the skeleton target
---
Diffs of the changes: (+1 -2)
configure.ac |3 +--
1 files changed, 1 insertion(+), 2 deletions(-)
Index: llvm/autoconf/configure.ac
diff -u llvm/autoconf/configure.ac:1.209 llvm/autoconf/configure.ac:1.210
--- llvm/autoconf/configure.ac:1.209Wed Feb 15 01:57:42 2006
+++ llvm/autoconf/configure.ac Thu Feb 16 15:11:49 2006
@@ -258,7 +258,7 @@
[Build specific host targets: all,host-only,{target-name} (default=all)]),,
enableval=all)
case $enableval in
- all) TARGETS_TO_BUILD=X86 Sparc SparcV9 PowerPC Alpha IA64 Skeleton ;;
+ all) TARGETS_TO_BUILD=X86 Sparc SparcV9 PowerPC Alpha IA64 ;;
host-only)
case $llvm_cv_target_arch in
x86) TARGETS_TO_BUILD=X86 ;;
@@ -278,7 +278,6 @@
powerpc) TARGETS_TO_BUILD=PowerPC $TARGETS_TO_BUILD ;;
alpha) TARGETS_TO_BUILD=Alpha $TARGETS_TO_BUILD ;;
ia64)TARGETS_TO_BUILD=IA64 $TARGETS_TO_BUILD ;;
-skeleton)TARGETS_TO_BUILD=Skeleton $TARGETS_TO_BUILD;;
*) AC_MSG_ERROR([Unrecognized target $a_target]) ;;
esac
done
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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/Sparc:
SparcISelDAGToDAG.cpp updated: 1.85 - 1.86
---
Log message:
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
---
Diffs of the changes: (+26 -13)
SparcISelDAGToDAG.cpp | 39 ++-
1 files changed, 26 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.85
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.86
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.85Wed Feb 15 00:41:34 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Thu Feb 16 15:11:51 2006
@@ -98,11 +98,14 @@
SparcTargetLowering(TargetMachine TM);
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG DAG);
-/// isMaskedValueZeroForTargetNode - Return true if 'Op Mask' is known to
-/// be zero. Op is expected to be a target specific node. Used by DAG
-/// combiner.
-virtual bool isMaskedValueZeroForTargetNode(const SDOperand Op,
-uint64_t Mask) const;
+/// computeMaskedBitsForTargetNode - Determine which of the bits specified
+/// in Mask are known to be either zero or one and return them in the
+/// KnownZero/KnownOne bitsets.
+virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
+uint64_t Mask,
+uint64_t KnownZero,
+uint64_t KnownOne,
+unsigned Depth = 0) const;
virtual std::vectorSDOperand
LowerArguments(Function F, SelectionDAG DAG);
@@ -246,20 +249,30 @@
/// isMaskedValueZeroForTargetNode - Return true if 'Op Mask' is known to
/// be zero. Op is expected to be a target specific node. Used by DAG
/// combiner.
-bool SparcTargetLowering::
-isMaskedValueZeroForTargetNode(const SDOperand Op, uint64_t Mask) const {
+void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
+ uint64_t Mask,
+ uint64_t KnownZero,
+ uint64_t KnownOne,
+ unsigned Depth) const
{
+ uint64_t KnownZero2, KnownOne2;
+ KnownZero = KnownOne = 0; // Don't know anything.
+
switch (Op.getOpcode()) {
- default: return false;
+ default: break;
case SPISD::SELECT_ICC:
case SPISD::SELECT_FCC:
-assert(MVT::isInteger(Op.getValueType()) Not an integer select!);
-// These operations are masked zero if both the left and the right are
zero.
-return MaskedValueIsZero(Op.getOperand(0), Mask)
- MaskedValueIsZero(Op.getOperand(1), Mask);
+ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
+ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
+assert((KnownZero KnownOne) == 0 Bits known to be one AND zero?);
+assert((KnownZero2 KnownOne2) == 0 Bits known to be one AND zero?);
+
+// Only known if known in both the LHS and RHS.
+KnownOne = KnownOne2;
+KnownZero = KnownZero2;
+break;
}
}
-
/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
/// either one or two GPRs, including FP values. TODO: we should pass FP
values
/// in FP registers for fastcc functions.
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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.30 - 1.31
---
Log message:
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
---
Diffs of the changes: (+506 -122)
TargetLowering.cpp | 628 ++---
1 files changed, 506 insertions(+), 122 deletions(-)
Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.30
llvm/lib/Target/TargetLowering.cpp:1.31
--- llvm/lib/Target/TargetLowering.cpp:1.30 Tue Feb 14 02:38:30 2006
+++ llvm/lib/Target/TargetLowering.cpp Thu Feb 16 15:11:51 2006
@@ -135,175 +135,559 @@
// Optimization Methods
//===--===//
-/// DemandedBitsAreZero - Return true if 'Op Mask' demands no bits from a bit
-/// set operation such as a sign extend or or/xor with constant whose only
-/// use is Op. If it returns true, the old node that sets bits which are
-/// not demanded is returned in Old, and its replacement node is returned in
-/// New, such that callers of DemandedBitsAreZero may call CombineTo on them if
-/// desired.
-bool TargetLowering::DemandedBitsAreZero(const SDOperand Op, uint64_t Mask,
- SDOperand Old, SDOperand New,
- SelectionDAG DAG) const {
- // If the operation has more than one use, we're not interested in it.
- // Tracking down and checking all uses would be problematic and slow.
- if (!Op.Val-hasOneUse())
+/// ShrinkDemandedConstant - Check to see if the specified operand of the
+/// specified instruction is a constant integer. If so, check to see if there
+/// are any bits set in the constant that are not demanded. If so, shrink the
+/// constant and return true.
+bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
+uint64_t Demanded)
{
+ // FIXME: ISD::SELECT
+ switch(Op.getOpcode()) {
+ default: break;
+ case ISD::AND:
+ case ISD::OR:
+ case ISD::XOR:
+if (ConstantSDNode *C = dyn_castConstantSDNode(Op.getOperand(1)))
+ if ((~Demanded C-getValue()) != 0) {
+MVT::ValueType VT = Op.getValueType();
+SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
+DAG.getConstant(Demanded C-getValue(),
+VT));
+return CombineTo(Op, New);
+ }
+break;
+ }
+ return false;
+}
+
+/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
+/// DemandedMask bits of the result of Op are ever used downstream. If we can
+/// use this information to simplify Op, create a new simplified DAG node and
+/// return true, returning the original and new nodes in Old and New.
Otherwise,
+/// analyze the expression and return a mask of KnownOne and KnownZero bits for
+/// the expression (used to simplify the caller). The KnownZero/One bits may
+/// only be accurate for those bits in the DemandedMask.
+bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
+ uint64_t KnownZero,
+ uint64_t KnownOne,
+ TargetLoweringOpt TLO,
+ unsigned Depth) const {
+ KnownZero = KnownOne = 0; // Don't know anything.
+ // Other users may use these bits.
+ if (!Op.Val-hasOneUse()) {
+if (Depth != 0) {
+ // If not at the root, Just compute the KnownZero/KnownOne bits to
+ // simplify things downstream.
+ ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
+ return false;
+}
+// If this is the root being simplified, allow it to have multiple uses,
+// just set the DemandedMask to all bits.
+DemandedMask = MVT::getIntVTBitMask(Op.getValueType());
+ } else if (DemandedMask == 0) {
+// Not demanding any bits from Op.
+if (Op.getOpcode() != ISD::UNDEF)
+ return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType()));
return false;
-
+ } else if (Depth == 6) {// Limit search depth.
+return false;
+ }
+
+ uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
switch (Op.getOpcode()) {
+ case ISD::Constant:
+// We know all of the bits for a constant!
+KnownOne = castConstantSDNode(Op)-getValue() DemandedMask;
+KnownZero = ~KnownOne DemandedMask;
+return false;
case ISD::AND:
-// (X C1) C2 == 0 iff C1 C2 == 0.
-if (ConstantSDNode *AndRHS = dyn_castConstantSDNode(Op.getOperand(1))) {
- uint64_t NewVal = Mask AndRHS-getValue();
- return DemandedBitsAreZero(Op.getOperand(0), NewVal, Old, New, DAG);
+// If either the LHS
[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.49 - 1.50
---
Log message:
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
---
Diffs of the changes: (+56 -18)
TargetLowering.h | 74 +--
1 files changed, 56 insertions(+), 18 deletions(-)
Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.49
llvm/include/llvm/Target/TargetLowering.h:1.50
--- llvm/include/llvm/Target/TargetLowering.h:1.49 Tue Feb 14 02:38:30 2006
+++ llvm/include/llvm/Target/TargetLowering.h Thu Feb 16 15:11:51 2006
@@ -23,6 +23,7 @@
#define LLVM_TARGET_TARGETLOWERING_H
#include llvm/Type.h
+#include llvm/CodeGen/SelectionDAGNodes.h
#include llvm/CodeGen/ValueTypes.h
#include llvm/Support/DataTypes.h
#include vector
@@ -284,22 +285,55 @@
// TargetLowering Optimization Methods
//
+ /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
+ /// SDOperands for returning information from TargetLowering to its clients
+ /// that want to combine
+ struct TargetLoweringOpt {
+SelectionDAG DAG;
+SDOperand Old;
+SDOperand New;
+
+TargetLoweringOpt::TargetLoweringOpt(SelectionDAG InDAG) : DAG(InDAG) {}
+
+bool CombineTo(SDOperand O, SDOperand N) {
+ Old = O;
+ New = N;
+ return true;
+}
+
+/// ShrinkDemandedConstant - Check to see if the specified operand of the
+/// specified instruction is a constant integer. If so, check to see if
there
+/// are any bits set in the constant that are not demanded. If so, shrink
the
+/// constant and return true.
+bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded);
+ };
+
/// MaskedValueIsZero - Return true if 'Op Mask' is known to be zero. We
/// use this predicate to simplify operations downstream. Op and Mask are
- /// known to be the same type. Targets can implement the
- /// isMaskedValueZeroForTargetNode method, to allow target nodes to be
- /// understood.
- bool MaskedValueIsZero(const SDOperand Op, uint64_t Mask) const;
-
- /// DemandedBitsAreZero - Return true if 'Op Mask' demands no bits from a
- /// bit set operation such as a sign extend or or/xor with constant whose
only
- /// use is Op. If it returns true, the old node that sets bits which are
- /// not demanded is returned in Old, and its replacement node is returned in
- /// New, such that callers of SetBitsAreZero may call CombineTo on them if
- /// desired.
- bool DemandedBitsAreZero(const SDOperand Op, uint64_t Mask, SDOperand Old,
- SDOperand New, SelectionDAG DAG) const;
-
+ /// known to be the same type.
+ bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0)
+const;
+
+ /// ComputeMaskedBits - Determine which of the bits specified in Mask are
+ /// known to be either zero or one and return them in the KnownZero/KnownOne
+ /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
+ /// processing. Targets can implement the computeMaskedBitsForTargetNode
+ /// method, to allow target nodes to be understood.
+ void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t KnownZero,
+ uint64_t KnownOne, unsigned Depth = 0) const;
+
+ /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
+ /// DemandedMask bits of the result of Op are ever used downstream. If we
can
+ /// use this information to simplify Op, create a new simplified DAG node and
+ /// return true, returning the original and new nodes in Old and New.
+ /// Otherwise, analyze the expression and return a mask of KnownOne and
+ /// KnownZero bits for the expression (used to simplify the caller).
+ /// The KnownZero/One bits may only be accurate for those bits in the
+ /// DemandedMask.
+ bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
+uint64_t KnownZero, uint64_t KnownOne,
+TargetLoweringOpt TLO, unsigned Depth = 0) const;
+
//======//
// TargetLowering Configuration Methods - These methods should be invoked by
// the derived class constructor to configure this object for the target.
@@ -433,10 +467,14 @@
/// DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const;
- /// isMaskedValueZeroForTargetNode - Return true if 'Op Mask' is known to
- /// be zero. Op is expected to be a target specific node.
- virtual bool isMaskedValueZeroForTargetNode(const SDOperand Op,
- uint64_t Mask) const;
+ /// computeMaskedBitsForTargetNode -
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.83 - 1.84
X86ISelLowering.h updated: 1.25 - 1.26
---
Log message:
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
---
Diffs of the changes: (+18 -11)
X86ISelLowering.cpp | 14 +-
X86ISelLowering.h | 15 +--
2 files changed, 18 insertions(+), 11 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.83
llvm/lib/Target/X86/X86ISelLowering.cpp:1.84
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.83Wed Feb 15 18:21:07 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Feb 16 15:11:51 2006
@@ -2035,19 +2035,23 @@
}
}
-bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand Op,
- uint64_t Mask) const {
+void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
+ uint64_t Mask,
+ uint64_t KnownZero,
+ uint64_t KnownOne,
+ unsigned Depth) const {
unsigned Opc = Op.getOpcode();
+ KnownZero = KnownOne = 0; // Don't know anything.
switch (Opc) {
default:
assert(Opc = ISD::BUILTIN_OP_END Expected a target specific node);
break;
- case X86ISD::SETCC: return (Mask 1) == 0;
+ case X86ISD::SETCC:
+KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
+break;
}
-
- return false;
}
std::vectorunsigned X86TargetLowering::
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.25
llvm/lib/Target/X86/X86ISelLowering.h:1.26
--- llvm/lib/Target/X86/X86ISelLowering.h:1.25 Fri Feb 3 20:20:30 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h Thu Feb 16 15:11:51 2006
@@ -218,12 +218,15 @@
/// DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const;
-/// isMaskedValueZeroForTargetNode - Return true if 'Op Mask' is known to
-/// be zero. Op is expected to be a target specific node. Used by DAG
-/// combiner.
-virtual bool isMaskedValueZeroForTargetNode(const SDOperand Op,
-uint64_t Mask) const;
-
+/// computeMaskedBitsForTargetNode - Determine which of the bits specified
+/// in Mask are known to be either zero or one and return them in the
+/// KnownZero/KnownOne bitsets.
+virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
+uint64_t Mask,
+uint64_t KnownZero,
+uint64_t KnownOne,
+unsigned Depth = 0) const;
+
SDOperand getReturnAddressFrameIndex(SelectionDAG DAG);
std::vectorunsigned
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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.cpp updated: 1.122 - 1.123
---
Log message:
Use movaps / movapd to spill / restore V4F4 / V2F8 registers.
---
Diffs of the changes: (+12 -4)
X86RegisterInfo.cpp | 16
1 files changed, 12 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.122
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.123
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.122 Wed Feb 15 19:50:02 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Feb 16 15:20:26 2006
@@ -57,10 +57,14 @@
Opc = X86::MOV16mr;
} else if (RC == X86::RFPRegClass || RC == X86::RSTRegClass) {
Opc = X86::FpST64m;
- } else if (RC == X86::FR32RegClass || RC == X86::V4F4RegClass) {
+ } else if (RC == X86::FR32RegClass) {
Opc = X86::MOVSSmr;
- } else if (RC == X86::FR64RegClass || RC == X86::V2F8RegClass) {
+ } else if (RC == X86::FR64RegClass) {
Opc = X86::MOVSDmr;
+ } else if (RC == X86::V4F4RegClass) {
+Opc = X86::MOVAPSmr;
+ } else if (RC == X86::V2F8RegClass) {
+Opc = X86::MOVAPDmr;
} else {
assert(0 Unknown regclass);
abort();
@@ -81,10 +85,14 @@
Opc = X86::MOV16rm;
} else if (RC == X86::RFPRegClass || RC == X86::RSTRegClass) {
Opc = X86::FpLD64m;
- } else if (RC == X86::FR32RegClass || RC == X86::V4F4RegClass) {
+ } else if (RC == X86::FR32RegClass) {
Opc = X86::MOVSSrm;
- } else if (RC == X86::FR64RegClass || RC == X86::V2F8RegClass) {
+ } else if (RC == X86::FR64RegClass) {
Opc = X86::MOVSDrm;
+ } else if (RC == X86::V4F4RegClass) {
+Opc = X86::MOVAPSrm;
+ } else if (RC == X86::V2F8RegClass) {
+Opc = X86::MOVAPDrm;
} else {
assert(0 Unknown regclass);
abort();
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp X86InstrInfo.td X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.cpp updated: 1.44 - 1.45
X86InstrInfo.td updated: 1.234 - 1.235
X86RegisterInfo.cpp updated: 1.123 - 1.124
---
Log message:
1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This
proves to be worth 20% on Ptrdist/ks. Might be related to dependency
breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
spill / restore FsMOVAPSrr and FsMOVAPDrr.
---
Diffs of the changes: (+29 -13)
X86InstrInfo.cpp|1 +
X86InstrInfo.td | 31 ---
X86RegisterInfo.cpp | 10 --
3 files changed, 29 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.44
llvm/lib/Target/X86/X86InstrInfo.cpp:1.45
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.44 Thu Feb 2 14:38:12 2006
+++ llvm/lib/Target/X86/X86InstrInfo.cppThu Feb 16 16:45:16 2006
@@ -29,6 +29,7 @@
MachineOpCode oc = MI.getOpcode();
if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
oc == X86::FpMOV || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
+ oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
oc == X86::MOVAPSrr || oc == X86::MOVAPDrr) {
assert(MI.getNumOperands() == 2
MI.getOperand(0).isRegister()
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.234
llvm/lib/Target/X86/X86InstrInfo.td:1.235
--- llvm/lib/Target/X86/X86InstrInfo.td:1.234 Thu Feb 16 13:34:41 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Thu Feb 16 16:45:17 2006
@@ -2487,13 +2487,13 @@
[(X86cmp FR64:$src1, (loadf64 addr:$src2))],
Requires[HasSSE2], TB, OpSize;
-// Pseudo-instructions that map fld0 to xorps/xorpd for sse.
+// Pseudo-instructions that map fld0 to pxor for sse.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
-def FLD0SS : I0x57, MRMInitReg, (ops FR32:$dst),
- xorps $dst, $dst, [(set FR32:$dst, fp32imm0)],
+def FLD0SS : I0xEF, MRMInitReg, (ops FR32:$dst),
+ pxor $dst, $dst, [(set FR32:$dst, fp32imm0)],
Requires[HasSSE1], TB;
-def FLD0SD : I0x57, MRMInitReg, (ops FR64:$dst),
- xorpd $dst, $dst, [(set FR64:$dst, fp64imm0)],
+def FLD0SD : I0xEF, MRMInitReg, (ops FR64:$dst),
+ pxor $dst, $dst, [(set FR64:$dst, fp64imm0)],
Requires[HasSSE2], TB, OpSize;
let isTwoAddress = 1 in {
@@ -3033,13 +3033,22 @@
movapd {$src, $dst|$dst, $src},[],
Requires[HasSSE2], TB, OpSize;
-// Pseudo-instructions to load FR32 / FR64 from f128mem using movaps / movapd.
+// Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
// Upper bits are disregarded.
-def MOVSAPSrm : I0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
- movaps {$src, $dst|$dst, $src},
- [(set FR32:$dst, (X86loadpf32 addr:$src))],
-Requires[HasSSE1], TB;
-def MOVSAPDrm : I0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
+def FsMOVAPSrr : I0x28, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
+ movaps {$src, $dst|$dst, $src}, [],
+ Requires[HasSSE1], TB;
+def FsMOVAPDrr : I0x28, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
+ movapd {$src, $dst|$dst, $src}, [],
+ Requires[HasSSE2], TB, OpSize;
+
+// Alias instructions to load FR32 / FR64 from f128mem using movaps / movapd.
+// Upper bits are disregarded.
+def FsMOVAPSrm : I0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
+ movaps {$src, $dst|$dst, $src},
+ [(set FR32:$dst, (X86loadpf32 addr:$src))],
+ Requires[HasSSE1], TB;
+def FsMOVAPDrm : I0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
movapd {$src, $dst|$dst, $src},
[(set FR64:$dst, (X86loadpf64 addr:$src))],
Requires[HasSSE2], TB, OpSize;
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.123
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.124
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.123 Thu Feb 16 15:20:26 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Feb 16 16:45:17 2006
@@ -114,9 +114,9 @@
} else if (RC == X86::RFPRegClass || RC == X86::RSTRegClass) {
Opc = X86::FpMOV;
} else if (RC == X86::FR32RegClass || RC == X86::V4F4RegClass) {
-Opc = X86::MOVAPSrr;
+Opc = X86::FsMOVAPSrr;
} else if (RC == X86::FR64RegClass || RC == X86::V2F8RegClass) {
-Opc = X86::MOVAPDrr;
+Opc = X86::FsMOVAPDrr;
} else {
assert(0 Unknown regclass);
abort();
@@ -313,6 +313,9 @@
case X86::CMP8ri:return MakeMIInst(X86::CMP8mi , FrameIndex, MI);
case X86::CMP16ri:
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.163 - 1.164
---
Log message:
Dumb bug. Code sees a memcpy from X+c so it increments src offset. But it
turns out not to point to a constant string but it forgot change the offset
back.
---
Diffs of the changes: (+10 -4)
SelectionDAGISel.cpp | 14 ++
1 files changed, 10 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.163
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.164
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.163Thu Feb 16
02:27:55 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Feb 16 17:11:42 2006
@@ -1658,9 +1658,10 @@
if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
Size-getValue(), Align, TLI)) {
unsigned NumMemOps = MemOps.size();
-unsigned SrcOff = 0, DstOff = 0;
+unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
GlobalAddressSDNode *G = NULL;
std::string Str;
+bool CopyFromStr = false;
if (Op2.getOpcode() == ISD::GlobalAddress)
G = castGlobalAddressSDNode(Op2);
@@ -1668,12 +1669,17 @@
Op2.getOperand(0).getOpcode() == ISD::GlobalAddress
Op2.getOperand(1).getOpcode() == ISD::Constant) {
G = castGlobalAddressSDNode(Op2.getOperand(0));
- SrcOff += castConstantSDNode(Op2.getOperand(1))-getValue();
+ SrcDelta = castConstantSDNode(Op2.getOperand(1))-getValue();
}
if (G) {
GlobalVariable *GV = dyn_castGlobalVariable(G-getGlobal());
- if (GV)
+ if (GV) {
Str = getStringValue(GV);
+if (!Str.empty()) {
+ CopyFromStr = true;
+ SrcOff += SrcDelta;
+}
+ }
}
for (unsigned i = 0; i NumMemOps; i++) {
@@ -1681,7 +1687,7 @@
unsigned VTSize = getSizeInBits(VT) / 8;
SDOperand Value, Chain, Store;
- if (!Str.empty()) {
+ if (CopyFromStr) {
Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
Chain = getRoot();
Store =
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[llvm-commits] CVS: llvm/lib/Target/Skeleton/Makefile README.txt Skeleton.h Skeleton.td SkeletonInstrInfo.cpp SkeletonInstrInfo.h SkeletonInstrInfo.td SkeletonJITInfo.cpp SkeletonJITInfo.h SkeletonReg
Changes in directory llvm/lib/Target/Skeleton: Makefile (r1.4) removed README.txt (r1.2) removed Skeleton.h (r1.2) removed Skeleton.td (r1.4) removed SkeletonInstrInfo.cpp (r1.2) removed SkeletonInstrInfo.h (r1.2) removed SkeletonInstrInfo.td (r1.4) removed SkeletonJITInfo.cpp (r1.3) removed SkeletonJITInfo.h (r1.3) removed SkeletonRegisterInfo.cpp (r1.7) removed SkeletonRegisterInfo.h (r1.8) removed SkeletonRegisterInfo.td (r1.6) removed SkeletonTargetMachine.cpp (r1.6) removed SkeletonTargetMachine.h (r1.5) removed --- Log message: Remove the skeleton target, it doesn't produce useful code and there are other small targets that do that can be learned from. They also have the added advantage of being tested :) --- Diffs of the changes: (+0 -0) 0 files changed ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td
Changes in directory llvm/lib/Target/X86: X86InstrInfo.td updated: 1.235 - 1.236 --- Log message: pxor (for FLD0SS) encoding was missing the OpSize prefix. --- Diffs of the changes: (+1 -1) X86InstrInfo.td |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.235 llvm/lib/Target/X86/X86InstrInfo.td:1.236 --- llvm/lib/Target/X86/X86InstrInfo.td:1.235 Thu Feb 16 16:45:17 2006 +++ llvm/lib/Target/X86/X86InstrInfo.td Thu Feb 16 17:59:30 2006 @@ -2491,7 +2491,7 @@ // FIXME: remove when we can teach regalloc that xor reg, reg is ok. def FLD0SS : I0xEF, MRMInitReg, (ops FR32:$dst), pxor $dst, $dst, [(set FR32:$dst, fp32imm0)], - Requires[HasSSE1], TB; + Requires[HasSSE1], TB, OpSize; def FLD0SD : I0xEF, MRMInitReg, (ops FR64:$dst), pxor $dst, $dst, [(set FR64:$dst, fp64imm0)], Requires[HasSSE2], TB, OpSize; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/README.txt
Changes in directory llvm/lib/Target/X86: README.txt updated: 1.54 - 1.55 --- Log message: Remove the entry about using movapd for SSE reg-reg moves. --- Diffs of the changes: (+0 -6) README.txt |6 -- 1 files changed, 6 deletions(-) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.54 llvm/lib/Target/X86/README.txt:1.55 --- llvm/lib/Target/X86/README.txt:1.54 Tue Feb 14 19:56:48 2006 +++ llvm/lib/Target/X86/README.txt Thu Feb 16 18:00:58 2006 @@ -356,12 +356,6 @@ //===-===// -Evaluate whether using movapd for SSE reg-reg moves is faster than using -movsd/movss for them. It may eliminate false partial register dependences by -writing the whole result register. - -//===-===// - SSE should implement 'select_cc' using 'emulated conditional moves' that use pcmp/pand/pandn/por to do a selection instead of a conditional branch: ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86.h X86ISelLowering.cpp X86TargetMachine.cpp X86ISelPattern.cpp
Changes in directory llvm/lib/Target/X86:
X86.h updated: 1.43 - 1.44
X86ISelLowering.cpp updated: 1.84 - 1.85
X86TargetMachine.cpp updated: 1.102 - 1.103
X86ISelPattern.cpp (r1.204) removed
---
Log message:
Kill the x86 pattern isel. boom.
---
Diffs of the changes: (+211 -325)
X86.h|8
X86ISelLowering.cpp | 511 ---
X86TargetMachine.cpp | 17 -
3 files changed, 211 insertions(+), 325 deletions(-)
Index: llvm/lib/Target/X86/X86.h
diff -u llvm/lib/Target/X86/X86.h:1.43 llvm/lib/Target/X86/X86.h:1.44
--- llvm/lib/Target/X86/X86.h:1.43 Fri Feb 3 12:54:24 2006
+++ llvm/lib/Target/X86/X86.h Thu Feb 16 18:03:04 2006
@@ -25,14 +25,6 @@
class IntrinsicLowering;
class MachineCodeEmitter;
-extern bool X86PatIsel;
-
-/// createX86ISelPattern - This pass converts an LLVM function into a
-/// machine code representation using pattern matching and a machine
-/// description file.
-///
-FunctionPass *createX86ISelPattern(TargetMachine TM);
-
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.
///
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.84
llvm/lib/Target/X86/X86ISelLowering.cpp:1.85
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.84Thu Feb 16 15:11:51 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Feb 16 18:03:04 2006
@@ -70,13 +70,9 @@
// this operation.
setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
+ // SSE has no i16 to fp conversion, only i32
if (X86ScalarSSE)
-// SSE has no i16 to fp conversion, only i32
setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
- else if (!X86PatIsel) {
-setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
-setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
- }
// We can handle SINT_TO_FP and FP_TO_SINT from/to i64 even though i64
// isn't legal.
@@ -112,9 +108,7 @@
setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
- if (!X86PatIsel) {
-setOperationAction(ISD::BRCOND , MVT::Other, Custom);
- }
+ setOperationAction(ISD::BRCOND , MVT::Other, Custom);
setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
setOperationAction(ISD::BR_CC, MVT::Other, Expand);
@@ -136,16 +130,6 @@
setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
-
- if (X86PatIsel) {
-setOperationAction(ISD::BSWAP , MVT::i32 , Expand);
-setOperationAction(ISD::ROTL , MVT::i8 , Expand);
-setOperationAction(ISD::ROTR , MVT::i8 , Expand);
-setOperationAction(ISD::ROTL , MVT::i16 , Expand);
-setOperationAction(ISD::ROTR , MVT::i16 , Expand);
-setOperationAction(ISD::ROTL , MVT::i32 , Expand);
-setOperationAction(ISD::ROTR , MVT::i32 , Expand);
- }
setOperationAction(ISD::BSWAP, MVT::i16 , Expand);
setOperationAction(ISD::READIO , MVT::i1 , Expand);
@@ -160,31 +144,30 @@
// These should be promoted to a larger select which is supported.
setOperationAction(ISD::SELECT , MVT::i1 , Promote);
setOperationAction(ISD::SELECT , MVT::i8 , Promote);
- if (!X86PatIsel) {
-// X86 wants to expand cmov itself.
-setOperationAction(ISD::SELECT , MVT::i16 , Custom);
-setOperationAction(ISD::SELECT , MVT::i32 , Custom);
-setOperationAction(ISD::SELECT , MVT::f32 , Custom);
-setOperationAction(ISD::SELECT , MVT::f64 , Custom);
-setOperationAction(ISD::SETCC , MVT::i8 , Custom);
-setOperationAction(ISD::SETCC , MVT::i16 , Custom);
-setOperationAction(ISD::SETCC , MVT::i32 , Custom);
-setOperationAction(ISD::SETCC , MVT::f32 , Custom);
-setOperationAction(ISD::SETCC , MVT::f64 , Custom);
-// X86 ret instruction may pop stack.
-setOperationAction(ISD::RET, MVT::Other, Custom);
-// Darwin ABI issue.
-setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
-// 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
-setOperationAction(ISD::ADD_PARTS , MVT::i32 , Custom);
-setOperationAction(ISD::SUB_PARTS , MVT::i32 , Custom);
-setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
-setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
-setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
-// X86 wants to expand memset / memcpy
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.45 - 1.46
---
Log message:
Add a missing and useful pat frag
---
Diffs of the changes: (+9 -2)
TargetSelectionDAG.td | 11 +--
1 files changed, 9 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.45
llvm/lib/Target/TargetSelectionDAG.td:1.46
--- llvm/lib/Target/TargetSelectionDAG.td:1.45 Sun Jan 29 00:26:07 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Thu Feb 16 18:51:06 2006
@@ -164,7 +164,6 @@
SDTCisPtrTy1, SDTCisVT2, OtherVT, SDTCisVT3, OtherVT
];
-
//===--===//
// Selection DAG Node Properties.
//
@@ -239,6 +238,14 @@
[SDNPCommutative, SDNPAssociative];
def xor: SDNodeISD::XOR , SDTIntBinOp,
[SDNPCommutative, SDNPAssociative];
+def addc : SDNodeISD::ADDC , SDTIntBinOp,
+[SDNPCommutative, SDNPOutFlag];
+def adde : SDNodeISD::ADDE , SDTIntBinOp,
+[SDNPCommutative, SDNPOutFlag, SDNPInFlag];
+def subc : SDNodeISD::SUBC , SDTIntBinOp,
+[SDNPOutFlag];
+def sube : SDNodeISD::SUBE , SDTIntBinOp,
+[SDNPOutFlag, SDNPInFlag];
def sext_inreg : SDNodeISD::SIGN_EXTEND_INREG, SDTExtInreg;
def bswap : SDNodeISD::BSWAP , SDTIntUnaryOp;
@@ -347,7 +354,7 @@
// Leaf fragments.
def immAllOnes : PatLeaf(imm), [{ return N-isAllOnesValue(); }];
-
+def immZero: PatLeaf(imm), [{ return N-isNullValue(); }];
def vtInt : PatLeaf(vt), [{ return MVT::isInteger(N-getVT()); }];
def vtFP : PatLeaf(vt), [{ return MVT::isFloatingPoint(N-getVT());
}];
___
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.46 - 1.47 --- Log message: Whoops, didn't mean to check this in yet. --- Diffs of the changes: (+0 -8) TargetSelectionDAG.td |8 1 files changed, 8 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.46 llvm/lib/Target/TargetSelectionDAG.td:1.47 --- llvm/lib/Target/TargetSelectionDAG.td:1.46 Thu Feb 16 18:51:06 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Thu Feb 16 18:56:19 2006 @@ -238,14 +238,6 @@ [SDNPCommutative, SDNPAssociative]; def xor: SDNodeISD::XOR , SDTIntBinOp, [SDNPCommutative, SDNPAssociative]; -def addc : SDNodeISD::ADDC , SDTIntBinOp, -[SDNPCommutative, SDNPOutFlag]; -def adde : SDNodeISD::ADDE , SDTIntBinOp, -[SDNPCommutative, SDNPOutFlag, SDNPInFlag]; -def subc : SDNodeISD::SUBC , SDTIntBinOp, -[SDNPOutFlag]; -def sube : SDNodeISD::SUBE , SDTIntBinOp, -[SDNPOutFlag, SDNPInFlag]; def sext_inreg : SDNodeISD::SIGN_EXTEND_INREG, SDTExtInreg; def bswap : SDNodeISD::BSWAP , SDTIntUnaryOp; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp
Changes in directory llvm/lib/Target: TargetLowering.cpp updated: 1.31 - 1.32 --- Log message: Fix bug noticed by VC++. --- Diffs of the changes: (+2 -2) TargetLowering.cpp |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/TargetLowering.cpp diff -u llvm/lib/Target/TargetLowering.cpp:1.31 llvm/lib/Target/TargetLowering.cpp:1.32 --- llvm/lib/Target/TargetLowering.cpp:1.31 Thu Feb 16 15:11:51 2006 +++ llvm/lib/Target/TargetLowering.cpp Thu Feb 16 20:12:18 2006 @@ -243,9 +243,9 @@ // If all of the demanded bits are known zero on one side, return the other. // These bits cannot contribute to the result of the 'or'. -if ((DemandedMask ~KnownOne2 KnownZero) == DemandedMask ~KnownOne2) +if ((DemandedMask ~KnownOne2 KnownZero) == (DemandedMask ~KnownOne2)) return TLO.CombineTo(Op, Op.getOperand(0)); -if ((DemandedMask ~KnownOne KnownZero2) == DemandedMask ~KnownOne) +if ((DemandedMask ~KnownOne KnownZero2) == (DemandedMask ~KnownOne)) return TLO.CombineTo(Op, Op.getOperand(1)); // If all of the potentially set bits on one side are known to be set on // the other side, just use the 'other' side. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/win32/x86/x86.vcproj
Changes in directory llvm/win32/x86: x86.vcproj updated: 1.20 - 1.21 --- Log message: Inform Visual Studio of deleted file. --- Diffs of the changes: (+0 -3) x86.vcproj |3 --- 1 files changed, 3 deletions(-) Index: llvm/win32/x86/x86.vcproj diff -u llvm/win32/x86/x86.vcproj:1.20 llvm/win32/x86/x86.vcproj:1.21 --- llvm/win32/x86/x86.vcproj:1.20 Fri Feb 3 21:27:04 2006 +++ llvm/win32/x86/x86.vcproj Thu Feb 16 20:11:34 2006 @@ -176,9 +176,6 @@ RelativePath=..\..\lib\Target\X86\X86ISelLowering.cpp /File File - RelativePath=..\..\lib\Target\X86\X86ISelPattern.cpp - /File - File RelativePath=..\..\lib\Target\X86\X86JITInfo.cpp /File File ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/README.txt
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.56 - 1.57
---
Log message:
add note about div by power of 2
---
Diffs of the changes: (+32 -0)
README.txt | 32
1 files changed, 32 insertions(+)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.56 llvm/lib/Target/X86/README.txt:1.57
--- llvm/lib/Target/X86/README.txt:1.56 Thu Feb 16 18:04:28 2006
+++ llvm/lib/Target/X86/README.txt Thu Feb 16 22:20:13 2006
@@ -443,3 +443,35 @@
It's not clear whether we should use pxor or xorps / xorpd to clear XMM
registers. The choice may depend on subtarget information. We should do some
more experiments on different x86 machines.
+
+//===-===//
+
+Evaluate what the best way to codegen sdiv X, (2^C) is. For X/8, we currently
+get this:
+
+int %test1(int %X) {
+%Y = div int %X, 8
+ret int %Y
+}
+
+_test1:
+movl 4(%esp), %eax
+movl %eax, %ecx
+sarl $31, %ecx
+shrl $29, %ecx
+addl %ecx, %eax
+sarl $3, %eax
+ret
+
+GCC knows several different ways to codegen it, one of which is this:
+
+_test1:
+movl4(%esp), %eax
+cmpl$-1, %eax
+leal7(%eax), %ecx
+cmovle %ecx, %eax
+sarl$3, %eax
+ret
+
+which is probably slower, but it's interesting at least :)
+
___
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[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.47 - 1.48
---
Log message:
kill ADD_PARTS SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
---
Diffs of the changes: (+8 -1)
TargetSelectionDAG.td |9 -
1 files changed, 8 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.47
llvm/lib/Target/TargetSelectionDAG.td:1.48
--- llvm/lib/Target/TargetSelectionDAG.td:1.47 Thu Feb 16 18:56:19 2006
+++ llvm/lib/Target/TargetSelectionDAG.td Thu Feb 16 23:43:56 2006
@@ -238,6 +238,14 @@
[SDNPCommutative, SDNPAssociative];
def xor: SDNodeISD::XOR , SDTIntBinOp,
[SDNPCommutative, SDNPAssociative];
+def addc : SDNodeISD::ADDC , SDTIntBinOp,
+[SDNPCommutative, SDNPOutFlag];
+def adde : SDNodeISD::ADDE , SDTIntBinOp,
+[SDNPCommutative, SDNPOutFlag, SDNPInFlag];
+def subc : SDNodeISD::SUBC , SDTIntBinOp,
+[SDNPOutFlag];
+def sube : SDNodeISD::SUBE , SDTIntBinOp,
+[SDNPOutFlag, SDNPInFlag];
def sext_inreg : SDNodeISD::SIGN_EXTEND_INREG, SDTExtInreg;
def bswap : SDNodeISD::BSWAP , SDTIntUnaryOp;
@@ -346,7 +354,6 @@
// Leaf fragments.
def immAllOnes : PatLeaf(imm), [{ return N-isAllOnesValue(); }];
-def immZero: PatLeaf(imm), [{ return N-isNullValue(); }];
def vtInt : PatLeaf(vt), [{ return MVT::isInteger(N-getVT()); }];
def vtFP : PatLeaf(vt), [{ return MVT::isFloatingPoint(N-getVT());
}];
___
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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp SparcInstrInfo.td
Changes in directory llvm/lib/Target/Sparc:
SparcISelDAGToDAG.cpp updated: 1.86 - 1.87
SparcInstrInfo.td updated: 1.121 - 1.122
---
Log message:
kill ADD_PARTS SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
---
Diffs of the changes: (+18 -41)
SparcISelDAGToDAG.cpp | 35 ---
SparcInstrInfo.td | 24 ++--
2 files changed, 18 insertions(+), 41 deletions(-)
Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.86
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.87
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.86Thu Feb 16 15:11:51 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Thu Feb 16 23:43:56 2006
@@ -1075,41 +1075,6 @@
switch (N-getOpcode()) {
default: break;
- case ISD::ADD_PARTS: {
-SDOperand LHSL, LHSH, RHSL, RHSH;
-Select(LHSL, N-getOperand(0));
-Select(LHSH, N-getOperand(1));
-Select(RHSL, N-getOperand(2));
-Select(RHSH, N-getOperand(3));
-// FIXME, handle immediate RHS.
-SDOperand Low =
- SDOperand(CurDAG-getTargetNode(SP::ADDCCrr, MVT::i32, MVT::Flag,
- LHSL, RHSL), 0);
-SDOperand Hi =
- SDOperand(CurDAG-getTargetNode(SP::ADDXrr, MVT::i32, LHSH, RHSH,
- Low.getValue(1)), 0);
-CodeGenMap[SDOperand(N, 0)] = Low;
-CodeGenMap[SDOperand(N, 1)] = Hi;
-Result = Op.ResNo ? Hi : Low;
-return;
- }
- case ISD::SUB_PARTS: {
-SDOperand LHSL, LHSH, RHSL, RHSH;
-Select(LHSL, N-getOperand(0));
-Select(LHSH, N-getOperand(1));
-Select(RHSL, N-getOperand(2));
-Select(RHSH, N-getOperand(3));
-SDOperand Low =
- SDOperand(CurDAG-getTargetNode(SP::SUBCCrr, MVT::i32, MVT::Flag,
- LHSL, RHSL), 0);
-SDOperand Hi =
- SDOperand(CurDAG-getTargetNode(SP::SUBXrr, MVT::i32, LHSH, RHSH,
- Low.getValue(1)), 0);
-CodeGenMap[SDOperand(N, 0)] = Low;
-CodeGenMap[SDOperand(N, 1)] = Hi;
-Result = Op.ResNo ? Hi : Low;
-return;
- }
case ISD::SDIV:
case ISD::UDIV: {
// FIXME: should use a custom expander to expose the SRA to the dag.
Index: llvm/lib/Target/Sparc/SparcInstrInfo.td
diff -u llvm/lib/Target/Sparc/SparcInstrInfo.td:1.121
llvm/lib/Target/Sparc/SparcInstrInfo.td:1.122
--- llvm/lib/Target/Sparc/SparcInstrInfo.td:1.121 Fri Feb 10 01:35:42 2006
+++ llvm/lib/Target/Sparc/SparcInstrInfo.td Thu Feb 16 23:43:56 2006
@@ -453,16 +453,20 @@
def ADDCCrr : F3_12, 0b01,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- addcc $b, $c, $dst, [];
+ addcc $b, $c, $dst,
+ [(set IntRegs:$dst, (addc IntRegs:$b, IntRegs:$c))];
def ADDCCri : F3_22, 0b01,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- addcc $b, $c, $dst, [];
+ addcc $b, $c, $dst,
+ [(set IntRegs:$dst, (addc IntRegs:$b, simm13:$c))];
def ADDXrr : F3_12, 0b001000,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- addx $b, $c, $dst, [];
+ addx $b, $c, $dst,
+ [(set IntRegs:$dst, (adde IntRegs:$b, IntRegs:$c))];
def ADDXri : F3_22, 0b001000,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- addx $b, $c, $dst, [];
+ addx $b, $c, $dst,
+ [(set IntRegs:$dst, (adde IntRegs:$b, simm13:$c))];
// Section B.15 - Subtract Instructions, p. 110
def SUBrr : F3_12, 0b000100,
@@ -475,10 +479,12 @@
[(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))];
def SUBXrr : F3_12, 0b001100,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- subx $b, $c, $dst, [];
+ subx $b, $c, $dst,
+ [(set IntRegs:$dst, (sube IntRegs:$b, IntRegs:$c))];
def SUBXri : F3_22, 0b001100,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- subx $b, $c, $dst, [];
+ subx $b, $c, $dst,
+ [(set IntRegs:$dst, (sube IntRegs:$b, simm13:$c))];
def SUBCCrr : F3_12, 0b010100,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
subcc $b, $c, $dst,
@@ -866,6 +872,12 @@
def : Pat(i32 imm:$val),
(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val));
+// subc
+def : Pat(subc IntRegs:$b, IntRegs:$c),
+ (SUBCCrr IntRegs:$b, IntRegs:$c);
+def : Pat(subc IntRegs:$b, simm13:$val),
+ (SUBCCri IntRegs:$b, imm:$val);
+
// Global addresses, constant pool entries
def : Pat(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in);
def : Pat(SPlo tglobaladdr:$in), (ORri G0,
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.85 - 1.86
X86ISelLowering.h updated: 1.26 - 1.27
X86InstrInfo.td updated: 1.236 - 1.237
---
Log message:
kill ADD_PARTS SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
---
Diffs of the changes: (+28 -77)
X86ISelLowering.cpp | 30
X86ISelLowering.h | 10
X86InstrInfo.td | 65 ++--
3 files changed, 28 insertions(+), 77 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.85
llvm/lib/Target/X86/X86ISelLowering.cpp:1.86
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.85Thu Feb 16 18:03:04 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Feb 16 23:43:56 2006
@@ -160,8 +160,6 @@
// Darwin ABI issue.
setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
// 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
- setOperationAction(ISD::ADD_PARTS , MVT::i32 , Custom);
- setOperationAction(ISD::SUB_PARTS , MVT::i32 , Custom);
setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
@@ -1270,30 +1268,6 @@
SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG DAG) {
switch (Op.getOpcode()) {
default: assert(0 Should not custom lower this!);
- case ISD::ADD_PARTS:
- case ISD::SUB_PARTS: {
-assert(Op.getNumOperands() == 4 Op.getValueType() == MVT::i32
- Not an i64 add/sub!);
-bool isAdd = Op.getOpcode() == ISD::ADD_PARTS;
-std::vectorMVT::ValueType Tys;
-Tys.push_back(MVT::i32);
-Tys.push_back(MVT::Flag);
-std::vectorSDOperand Ops;
-Ops.push_back(Op.getOperand(0));
-Ops.push_back(Op.getOperand(2));
-SDOperand Lo = DAG.getNode(isAdd ? X86ISD::ADD_FLAG : X86ISD::SUB_FLAG,
- Tys, Ops);
-SDOperand Hi = DAG.getNode(isAdd ? X86ISD::ADC : X86ISD::SBB, MVT::i32,
- Op.getOperand(1), Op.getOperand(3),
- Lo.getValue(1));
-Tys.clear();
-Tys.push_back(MVT::i32);
-Tys.push_back(MVT::i32);
-Ops.clear();
-Ops.push_back(Lo);
-Ops.push_back(Hi);
-return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
- }
case ISD::SHL_PARTS:
case ISD::SRA_PARTS:
case ISD::SRL_PARTS: {
@@ -1910,10 +1884,6 @@
const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) {
default: return NULL;
- case X86ISD::ADD_FLAG: return X86ISD::ADD_FLAG;
- case X86ISD::SUB_FLAG: return X86ISD::SUB_FLAG;
- case X86ISD::ADC:return X86ISD::ADC;
- case X86ISD::SBB:return X86ISD::SBB;
case X86ISD::SHLD: return X86ISD::SHLD;
case X86ISD::SHRD: return X86ISD::SHRD;
case X86ISD::FAND: return X86ISD::FAND;
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.26
llvm/lib/Target/X86/X86ISelLowering.h:1.27
--- llvm/lib/Target/X86/X86ISelLowering.h:1.26 Thu Feb 16 15:11:51 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h Thu Feb 16 23:43:56 2006
@@ -26,16 +26,6 @@
// Start the numbering where the builtin ops leave off.
FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
- /// ADD_FLAG, SUB_FLAG - Same as ISD::ADD and ISD::SUB except it also
- /// produces a flag result.
- ADD_FLAG,
- SUB_FLAG,
-
- /// ADC, SBB - Add with carry and subtraction with borrow. These
- /// correspond to X86::ADCxx and X86::SBBxx instructions.
- ADC,
- SBB,
-
/// SHLD, SHRD - Double shift instructions. These correspond to
/// X86::SHLDxx and X86::SHRDxx instructions.
SHLD,
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.236
llvm/lib/Target/X86/X86InstrInfo.td:1.237
--- llvm/lib/Target/X86/X86InstrInfo.td:1.236 Thu Feb 16 17:59:30 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Thu Feb 16 23:43:56 2006
@@ -56,15 +56,6 @@
def SDTX86RdTsc : SDTypeProfile0, 0, [];
-def X86addflag : SDNodeX86ISD::ADD_FLAG, SDTIntBinOp ,
-[SDNPCommutative, SDNPAssociative, SDNPOutFlag];
-def X86subflag : SDNodeX86ISD::SUB_FLAG, SDTIntBinOp,
-[SDNPOutFlag];
-def X86adc : SDNodeX86ISD::ADC , SDTIntBinOp ,
-[SDNPCommutative, SDNPAssociative, SDNPInFlag];
-def X86sbb : SDNodeX86ISD::SBB , SDTIntBinOp,
-[SDNPInFlag];
-
def X86shld: SDNodeX86ISD::SHLD, SDTIntShiftDOp;
def X86shrd: SDNodeX86ISD::SHRD, SDTIntShiftDOp;
@@ -1873,28 +1864,28 @@
let isCommutable =
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.158 - 1.159
PPCInstrInfo.td updated: 1.176 - 1.177
---
Log message:
kill ADD_PARTS SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
---
Diffs of the changes: (+14 -83)
PPCISelDAGToDAG.cpp | 75
PPCInstrInfo.td | 22 +--
2 files changed, 14 insertions(+), 83 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.158
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.159
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.158 Thu Feb 16 02:27:56 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Feb 16 23:43:56 2006
@@ -535,75 +535,6 @@
return 0;
}
-
-SDOperand PPCDAGToDAGISel::SelectADD_PARTS(SDOperand Op) {
- SDNode *N = Op.Val;
- SDOperand LHSL, LHSH;
- Select(LHSL, N-getOperand(0));
- Select(LHSH, N-getOperand(1));
-
- unsigned Imm;
- bool ME = false, ZE = false;
- if (isIntImmediate(N-getOperand(3), Imm)) {
-ME = (signed)Imm == -1;
-ZE = Imm == 0;
- }
-
- std::vectorSDOperand Result;
- SDOperand Tmp;
- SDNode *CarryFromLo;
- if (isIntImmediate(N-getOperand(2), Imm)
- ((signed)Imm = -32768 || (signed)Imm 32768)) {
-// Codegen the low 32 bits of the add. Interestingly, there is no
-// shifted form of add immediate carrying.
-CarryFromLo = CurDAG-getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
-LHSL, getI32Imm(Imm));
- } else {
-Select(Tmp, N-getOperand(2));
-CarryFromLo = CurDAG-getTargetNode(PPC::ADDC, MVT::i32, MVT::Flag,
-LHSL, Tmp);
- }
-
- // Codegen the high 32 bits, adding zero, minus one, or the full value
- // along with the carry flag produced by addc/addic.
- SDOperand ResultHi;
- if (ZE)
-ResultHi = SDOperand(CurDAG-getTargetNode(PPC::ADDZE, MVT::i32, LHSH,
- SDOperand(CarryFromLo, 1)), 0);
- else if (ME)
-ResultHi = SDOperand(CurDAG-getTargetNode(PPC::ADDME, MVT::i32, LHSH,
- SDOperand(CarryFromLo, 1)), 0);
- else {
-Select(Tmp, N-getOperand(3));
-ResultHi = SDOperand(CurDAG-getTargetNode(PPC::ADDE, MVT::i32, LHSH,
-Tmp, SDOperand(CarryFromLo, 1)),
0);
- }
- Result.push_back(SDOperand(CarryFromLo, 0));
- Result.push_back(ResultHi);
-
- CodeGenMap[Op.getValue(0)] = Result[0];
- CodeGenMap[Op.getValue(1)] = Result[1];
- return Result[Op.ResNo];
-}
-SDOperand PPCDAGToDAGISel::SelectSUB_PARTS(SDOperand Op) {
- SDNode *N = Op.Val;
- SDOperand LHSL, LHSH, RHSL, RHSH;
- Select(LHSL, N-getOperand(0));
- Select(LHSH, N-getOperand(1));
- Select(RHSL, N-getOperand(2));
- Select(RHSH, N-getOperand(3));
-
- std::vectorSDOperand Result;
- Result.push_back(SDOperand(CurDAG-getTargetNode(PPC::SUBFC, MVT::i32,
- MVT::Flag, RHSL, LHSL), 0));
- Result.push_back(SDOperand(CurDAG-getTargetNode(PPC::SUBFE, MVT::i32,
- RHSH, LHSH,
- Result[0].getValue(1)), 0));
- CodeGenMap[Op.getValue(0)] = Result[0];
- CodeGenMap[Op.getValue(1)] = Result[1];
- return Result[Op.ResNo];
-}
-
SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
SDNode *N = Op.Val;
unsigned Imm;
@@ -846,12 +777,6 @@
switch (N-getOpcode()) {
default: break;
- case ISD::ADD_PARTS:
-Result = SelectADD_PARTS(Op);
-return;
- case ISD::SUB_PARTS:
-Result = SelectSUB_PARTS(Op);
-return;
case ISD::SETCC:
Result = SelectSETCC(Op);
return;
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.176
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.177
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.176 Sun Feb 12 03:09:52 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Thu Feb 16 23:43:56 2006
@@ -302,7 +302,7 @@
[(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))];
def ADDIC : DForm_212, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
addic $rD, $rA, $imm, IntGeneral,
- [];
+ [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))];
def ADDICo : DForm_213, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
addic. $rD, $rA, $imm, IntGeneral,
[];
@@ -684,10 +684,10 @@
[(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))];
def ADDC : XOForm_131, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
addc $rT, $rA, $rB, IntGeneral,
- [];
+ [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))];
def ADDE :
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.103 - 1.104
LegalizeDAG.cpp updated: 1.305 - 1.306
SelectionDAG.cpp updated: 1.256 - 1.257
---
Log message:
kill ADD_PARTS SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
---
Diffs of the changes: (+47 -62)
DAGCombiner.cpp | 46
LegalizeDAG.cpp | 57 +--
SelectionDAG.cpp |6 +++--
3 files changed, 47 insertions(+), 62 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.103
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.104
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.103 Thu Feb 16 15:11:51 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Feb 16 23:43:56 2006
@@ -157,14 +157,11 @@
SDOperand visitSELECT(SDNode *N);
SDOperand visitSELECT_CC(SDNode *N);
SDOperand visitSETCC(SDNode *N);
-SDOperand visitADD_PARTS(SDNode *N);
-SDOperand visitSUB_PARTS(SDNode *N);
SDOperand visitSIGN_EXTEND(SDNode *N);
SDOperand visitZERO_EXTEND(SDNode *N);
SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
SDOperand visitTRUNCATE(SDNode *N);
SDOperand visitBIT_CONVERT(SDNode *N);
-
SDOperand visitFADD(SDNode *N);
SDOperand visitFSUB(SDNode *N);
SDOperand visitFMUL(SDNode *N);
@@ -183,7 +180,6 @@
SDOperand visitBRCONDTWOWAY(SDNode *N);
SDOperand visitBR_CC(SDNode *N);
SDOperand visitBRTWOWAY_CC(SDNode *N);
-
SDOperand visitLOAD(SDNode *N);
SDOperand visitSTORE(SDNode *N);
@@ -550,8 +546,6 @@
case ISD::SELECT: return visitSELECT(N);
case ISD::SELECT_CC: return visitSELECT_CC(N);
case ISD::SETCC: return visitSETCC(N);
- case ISD::ADD_PARTS: return visitADD_PARTS(N);
- case ISD::SUB_PARTS: return visitSUB_PARTS(N);
case ISD::SIGN_EXTEND:return visitSIGN_EXTEND(N);
case ISD::ZERO_EXTEND:return visitZERO_EXTEND(N);
case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
@@ -1509,46 +1503,6 @@
castCondCodeSDNode(N-getOperand(2))-get());
}
-SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) {
- SDOperand LHSLo = N-getOperand(0);
- SDOperand RHSLo = N-getOperand(2);
- MVT::ValueType VT = LHSLo.getValueType();
-
- // fold (a_Hi, 0) + (b_Hi, b_Lo) - (b_Hi + a_Hi, b_Lo)
- if (TLI.MaskedValueIsZero(LHSLo, (1ULL MVT::getSizeInBits(VT))-1)) {
-SDOperand Hi = DAG.getNode(ISD::ADD, VT, N-getOperand(1),
- N-getOperand(3));
-WorkList.push_back(Hi.Val);
-CombineTo(N, RHSLo, Hi);
-return SDOperand();
- }
- // fold (a_Hi, a_Lo) + (b_Hi, 0) - (a_Hi + b_Hi, a_Lo)
- if (TLI.MaskedValueIsZero(RHSLo, (1ULL MVT::getSizeInBits(VT))-1)) {
-SDOperand Hi = DAG.getNode(ISD::ADD, VT, N-getOperand(1),
- N-getOperand(3));
-WorkList.push_back(Hi.Val);
-CombineTo(N, LHSLo, Hi);
-return SDOperand();
- }
- return SDOperand();
-}
-
-SDOperand DAGCombiner::visitSUB_PARTS(SDNode *N) {
- SDOperand LHSLo = N-getOperand(0);
- SDOperand RHSLo = N-getOperand(2);
- MVT::ValueType VT = LHSLo.getValueType();
-
- // fold (a_Hi, a_Lo) - (b_Hi, 0) - (a_Hi - b_Hi, a_Lo)
- if (TLI.MaskedValueIsZero(RHSLo, (1ULL MVT::getSizeInBits(VT))-1)) {
-SDOperand Hi = DAG.getNode(ISD::SUB, VT, N-getOperand(1),
- N-getOperand(3));
-WorkList.push_back(Hi.Val);
-CombineTo(N, LHSLo, Hi);
-return SDOperand();
- }
- return SDOperand();
-}
-
SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
SDOperand N0 = N-getOperand(0);
ConstantSDNode *N0C = dyn_castConstantSDNode(N0);
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.305
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.306
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.305 Thu Feb 16 22:32:33 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Feb 16 23:43:56 2006
@@ -575,7 +575,7 @@
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
break;
}
-break;
+break;
case ISD::Constant:
// We know we don't need to expand constants here, constants only have one
@@ -1749,8 +1749,6 @@
}
break;
- case ISD::ADD_PARTS:
- case ISD::SUB_PARTS:
case ISD::SHL_PARTS:
case ISD::SRA_PARTS:
case ISD::SRL_PARTS: {
@@ -1830,7 +1828,32 @@
break;
}
break;
+
+ case ISD::ADDC:
+ case ISD::SUBC:
+Tmp1 = LegalizeOp(Node-getOperand(0));
+Tmp2 = LegalizeOp(Node-getOperand(1));
+Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
+// Since this produces two values, make sure to remember that we legalized
+// both of
[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/addc.ll subc.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
addc.ll added (r1.1)
subc.ll added (r1.1)
---
Log message:
A couple new regression tests to make sure we always pattern match the new
opcodes on ppc.
---
Diffs of the changes: (+51 -0)
addc.ll | 26 ++
subc.ll | 25 +
2 files changed, 51 insertions(+)
Index: llvm/test/Regression/CodeGen/PowerPC/addc.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/addc.ll:1.1
*** /dev/null Fri Feb 17 00:17:06 2006
--- llvm/test/Regression/CodeGen/PowerPC/addc.llFri Feb 17 00:16:56 2006
***
*** 0
--- 1,26
+ ; All of these ands and shifts should be folded into rlwimi's
+ ; RUN: llvm-as %s | llc -march=ppc32 | grep addc | wc -l | grep 1
+ ; RUN: llvm-as %s | llc -march=ppc32 | grep adde | wc -l | grep 1
+ ; RUN: llvm-as %s | llc -march=ppc32 | grep addze | wc -l | grep 1
+ ; RUN: llvm-as %s | llc -march=ppc32 | grep addme | wc -l | grep 1
+ ; RUN: llvm-as %s | llc -march=ppc32 | grep addic | wc -l | grep 2
+
+ implementation ; Functions:
+
+ long %add_ll(long %a, long %b) {
+ entry:
+ %tmp.2 = add long %b, %a; long [#uses=1]
+ ret long %tmp.2
+ }
+
+ long %add_l_5(long %a) {
+ entry:
+ %tmp.1 = add long %a, 5 ; long [#uses=1]
+ ret long %tmp.1
+ }
+
+ long %add_l_m5(long %a) {
+ entry:
+ %tmp.1 = add long %a, -5; long [#uses=1]
+ ret long %tmp.1
+ }
Index: llvm/test/Regression/CodeGen/PowerPC/subc.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/subc.ll:1.1
*** /dev/null Fri Feb 17 00:17:08 2006
--- llvm/test/Regression/CodeGen/PowerPC/subc.llFri Feb 17 00:16:56 2006
***
*** 0
--- 1,25
+ ; All of these ands and shifts should be folded into rlwimi's
+ ; RUN: llvm-as %s | llc -march=ppc32 | grep subfc | wc -l | grep 1
+ ; RUN: llvm-as %s | llc -march=ppc32 | grep subfe | wc -l | grep 1
+ ; RUN: llvm-as %s | llc -march=ppc32 | grep subfze | wc -l | grep 1
+ ; RUN: llvm-as %s | llc -march=ppc32 | grep subfme | wc -l | grep 1
+ ; RUN: llvm-as %s | llc -march=ppc32 | grep subfic | wc -l | grep 2
+ implementation ; Functions:
+
+ long %sub_ll(long %a, long %b) {
+ entry:
+ %tmp.2 = sub long %a, %b; long [#uses=1]
+ ret long %tmp.2
+ }
+
+ long %sub_l_5(long %a) {
+ entry:
+ %tmp.1 = sub long 5, %a ; long [#uses=1]
+ ret long %tmp.1
+ }
+
+ long %sub_l_m5(long %a) {
+ entry:
+ %tmp.1 = sub long -5, %a; long [#uses=1]
+ ret long %tmp.1
+ }
___
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llvm-commits@cs.uiuc.edu
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/addc.ll subc.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC: addc.ll updated: 1.1 - 1.2 subc.ll updated: 1.1 - 1.2 --- Log message: Fix a comment sabre noticed :) --- Diffs of the changes: (+2 -2) addc.ll |2 +- subc.ll |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/test/Regression/CodeGen/PowerPC/addc.ll diff -u llvm/test/Regression/CodeGen/PowerPC/addc.ll:1.1 llvm/test/Regression/CodeGen/PowerPC/addc.ll:1.2 --- llvm/test/Regression/CodeGen/PowerPC/addc.ll:1.1Fri Feb 17 00:16:56 2006 +++ llvm/test/Regression/CodeGen/PowerPC/addc.llFri Feb 17 00:24:31 2006 @@ -1,4 +1,4 @@ -; All of these ands and shifts should be folded into rlwimi's +; All of these should be codegen'd without loading immediates ; RUN: llvm-as %s | llc -march=ppc32 | grep addc | wc -l | grep 1 ; RUN: llvm-as %s | llc -march=ppc32 | grep adde | wc -l | grep 1 ; RUN: llvm-as %s | llc -march=ppc32 | grep addze | wc -l | grep 1 Index: llvm/test/Regression/CodeGen/PowerPC/subc.ll diff -u llvm/test/Regression/CodeGen/PowerPC/subc.ll:1.1 llvm/test/Regression/CodeGen/PowerPC/subc.ll:1.2 --- llvm/test/Regression/CodeGen/PowerPC/subc.ll:1.1Fri Feb 17 00:16:56 2006 +++ llvm/test/Regression/CodeGen/PowerPC/subc.llFri Feb 17 00:24:31 2006 @@ -1,4 +1,4 @@ -; All of these ands and shifts should be folded into rlwimi's +; All of these should be codegen'd without loading immediates ; RUN: llvm-as %s | llc -march=ppc32 | grep subfc | wc -l | grep 1 ; RUN: llvm-as %s | llc -march=ppc32 | grep subfe | wc -l | grep 1 ; RUN: llvm-as %s | llc -march=ppc32 | grep subfze | wc -l | grep 1 ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
Changes in directory llvm/lib/Transforms/Scalar:
LoopUnswitch.cpp updated: 1.27 - 1.28
---
Log message:
Fix loops where the header has an exit, fixing a loop-unswitch crash on crafty
---
Diffs of the changes: (+15 -13)
LoopUnswitch.cpp | 28 +++-
1 files changed, 15 insertions(+), 13 deletions(-)
Index: llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
diff -u llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.27
llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.28
--- llvm/lib/Transforms/Scalar/LoopUnswitch.cpp:1.27Thu Feb 16 18:31:07 2006
+++ llvm/lib/Transforms/Scalar/LoopUnswitch.cpp Fri Feb 17 00:39:56 2006
@@ -136,20 +136,22 @@
static bool isTrivialLoopExitBlockHelper(Loop *L, BasicBlock *BB,
BasicBlock *ExitBB,
std::setBasicBlock* Visited) {
- BasicBlock *Header = L-getHeader();
+ if (!Visited.insert(BB).second) {
+// Already visited and Ok, end of recursion.
+return true;
+ } else if (!L-contains(BB)) {
+// Otherwise, this is a loop exit, this is fine so long as this is the
+// first exit.
+if (ExitBB != 0) return false;
+ExitBB = BB;
+return true;
+ }
+
+ // Otherwise, this is an unvisited intra-loop node. Check all successors.
for (succ_iterator SI = succ_begin(BB), E = succ_end(BB); SI != E; ++SI) {
-if (!Visited.insert(*SI).second) {
- // Already visited and Ok, end of recursion.
-} else if (L-contains(*SI)) {
- // Check to see if the successor is a trivial loop exit.
- if (!isTrivialLoopExitBlockHelper(L, *SI, ExitBB, Visited))
-return false;
-} else {
- // Otherwise, this is a loop exit, this is fine so long as this is the
- // first exit.
- if (ExitBB != 0) return false;
- ExitBB = *SI;
-}
+// Check to see if the successor is a trivial loop exit.
+if (!isTrivialLoopExitBlockHelper(L, *SI, ExitBB, Visited))
+ return false;
}
// Okay, everything after this looks good, check to make sure that this block
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.86 - 1.87
---
Log message:
Unbreak x86 be
---
Diffs of the changes: (+22 -17)
X86ISelLowering.cpp | 39 ++-
1 files changed, 22 insertions(+), 17 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.86
llvm/lib/Target/X86/X86ISelLowering.cpp:1.87
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.86Thu Feb 16 23:43:56 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Feb 17 01:01:52 2006
@@ -73,6 +73,10 @@
// SSE has no i16 to fp conversion, only i32
if (X86ScalarSSE)
setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
+ else {
+setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
+setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
+ }
// We can handle SINT_TO_FP and FP_TO_SINT from/to i64 even though i64
// isn't legal.
@@ -108,7 +112,7 @@
setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
- setOperationAction(ISD::BRCOND , MVT::Other, Custom);
+ setOperationAction(ISD::BRCOND , MVT::Other, Custom);
setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
setOperationAction(ISD::BR_CC, MVT::Other, Expand);
@@ -146,26 +150,27 @@
setOperationAction(ISD::SELECT , MVT::i8 , Promote);
// X86 wants to expand cmov itself.
- setOperationAction(ISD::SELECT , MVT::i16 , Custom);
- setOperationAction(ISD::SELECT , MVT::i32 , Custom);
- setOperationAction(ISD::SELECT , MVT::f32 , Custom);
- setOperationAction(ISD::SELECT , MVT::f64 , Custom);
- setOperationAction(ISD::SETCC , MVT::i8 , Custom);
- setOperationAction(ISD::SETCC , MVT::i16 , Custom);
- setOperationAction(ISD::SETCC , MVT::i32 , Custom);
- setOperationAction(ISD::SETCC , MVT::f32 , Custom);
- setOperationAction(ISD::SETCC , MVT::f64 , Custom);
+ setOperationAction(ISD::SELECT , MVT::i16 , Custom);
+ setOperationAction(ISD::SELECT , MVT::i32 , Custom);
+ setOperationAction(ISD::SELECT , MVT::f32 , Custom);
+ setOperationAction(ISD::SELECT , MVT::f64 , Custom);
+ setOperationAction(ISD::SETCC , MVT::i8 , Custom);
+ setOperationAction(ISD::SETCC , MVT::i16 , Custom);
+ setOperationAction(ISD::SETCC , MVT::i32 , Custom);
+ setOperationAction(ISD::SETCC , MVT::f32 , Custom);
+ setOperationAction(ISD::SETCC , MVT::f64 , Custom);
// X86 ret instruction may pop stack.
- setOperationAction(ISD::RET, MVT::Other, Custom);
+ setOperationAction(ISD::RET , MVT::Other, Custom);
// Darwin ABI issue.
- setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
+ setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
// 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
- setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
- setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
- setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
+ setOperationAction(ISD::SUB_PARTS , MVT::i32 , Custom);
+ setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
+ setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
+ setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
// X86 wants to expand memset / memcpy itself.
- setOperationAction(ISD::MEMSET , MVT::Other, Custom);
- setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
+ setOperationAction(ISD::MEMSET , MVT::Other, Custom);
+ setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.87 - 1.88 --- Log message: unbreak the build --- Diffs of the changes: (+0 -1) X86ISelLowering.cpp |1 - 1 files changed, 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.87 llvm/lib/Target/X86/X86ISelLowering.cpp:1.88 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.87Fri Feb 17 01:01:52 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Feb 17 01:09:27 2006 @@ -164,7 +164,6 @@ // Darwin ABI issue. setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) - setOperationAction(ISD::SUB_PARTS , MVT::i32 , Custom); setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.104 - 1.105
---
Log message:
Don't expand sdiv by power of two before legalize, since it will likely
generate illegal nodes.
---
Diffs of the changes: (+2 -2)
DAGCombiner.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.104
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.105
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.104 Thu Feb 16 23:43:56 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Feb 17 01:26:20 2006
@@ -731,8 +731,8 @@
if (TLI.MaskedValueIsZero(N1, SignBit)
TLI.MaskedValueIsZero(N0, SignBit))
return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
- // fold (sdiv X, pow2) - simple ops.
- if (N1C N1C-getValue() !TLI.isIntDivCheap()
+ // fold (sdiv X, pow2) - simple ops after legalize
+ if (N1C N1C-getValue() !TLI.isIntDivCheap() AfterLegalize
(isPowerOf2_64(N1C-getSignExtended()) ||
isPowerOf2_64(-N1C-getSignExtended( {
// If dividing by powers of two is cheap, then don't perform the following
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