[llvm-commits] CVS: llvm/lib/Analysis/ScalarEvolution.cpp

[Chris Lattner]

Changes in directory llvm/lib/Analysis:

ScalarEvolution.cpp updated: 1.46 - 1.47
---
Log message:

Signed shr by a constant is not the same as sdiv by 2^k


---
Diffs of the changes:  (+0 -9)

 ScalarEvolution.cpp |9 -
 1 files changed, 9 deletions(-)


Index: llvm/lib/Analysis/ScalarEvolution.cpp
diff -u llvm/lib/Analysis/ScalarEvolution.cpp:1.46 
llvm/lib/Analysis/ScalarEvolution.cpp:1.47
--- llvm/lib/Analysis/ScalarEvolution.cpp:1.46  Fri Mar 31 22:48:52 2006
+++ llvm/lib/Analysis/ScalarEvolution.cpp   Tue Apr  4 01:11:42 2006
@@ -1374,15 +1374,6 @@
   }
   break;
 
-case Instruction::Shr:
-  if (ConstantUInt *SA = dyn_castConstantUInt(I-getOperand(1)))
-if (V-getType()-isSigned()) {
-  Constant *X = ConstantInt::get(V-getType(), 1);
-  X = ConstantExpr::getShl(X, SA);
-  return SCEVSDivExpr::get(getSCEV(I-getOperand(0)), getSCEV(X));
-}
-  break;
-
 case Instruction::Cast:
   return createNodeForCast(castCastInst(I));
 



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[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/multiplies.c helpers.h

[Chris Lattner]

Changes in directory llvm-test/SingleSource/UnitTests/Vector:

multiplies.c added (r1.1)
helpers.h updated: 1.4 - 1.5
---
Log message:

new testcase for multiplies


---
Diffs of the changes:  (+50 -0)

 helpers.h|   16 
 multiplies.c |   34 ++
 2 files changed, 50 insertions(+)


Index: llvm-test/SingleSource/UnitTests/Vector/multiplies.c
diff -c /dev/null llvm-test/SingleSource/UnitTests/Vector/multiplies.c:1.1
*** /dev/null   Tue Apr  4 01:50:34 2006
--- llvm-test/SingleSource/UnitTests/Vector/multiplies.cTue Apr  4 
01:50:24 2006
***
*** 0 
--- 1,34 
+ #include helpers.h
+ 
+ #define ARRAYSIZE 10
+ double TheArray[ARRAYSIZE];
+ 
+ #define ProcessArray(VECTY) { \
+   VECTY V = (VECTY)((v4i32){0,0,0,0}); \
+   VECTY *AP = (VECTY*)TheArray;   \
+   IV vu;  \
+   for (j = 0; j  1000; ++j) \
+   for (i = 0; i != sizeof(TheArray)/sizeof(VECTY); ++i) \
+ V *= AP[i];\
+   vu.V = (v4i32)V;\
+   printIV(vu);\
+ }
+ 
+ 
+ int main(int argc, char **Argv) {
+   unsigned i, j;
+   for (i = 0; i  ARRAYSIZE; ++i)
+ TheArray[i] = i*12.345;
+ 
+   ProcessArray(v16i8);
+   ProcessArray(v8i16);
+   ProcessArray(v4i32);
+   ProcessArray(v2i64);
+   
+   // These break native gcc.  :(
+ #if 0
+   ProcessArray(v4f32);
+   ProcessArray(v2f64);
+ #endif
+ }
+ 


Index: llvm-test/SingleSource/UnitTests/Vector/helpers.h
diff -u llvm-test/SingleSource/UnitTests/Vector/helpers.h:1.4 
llvm-test/SingleSource/UnitTests/Vector/helpers.h:1.5
--- llvm-test/SingleSource/UnitTests/Vector/helpers.h:1.4   Thu Mar 30 
20:11:46 2006
+++ llvm-test/SingleSource/UnitTests/Vector/helpers.h   Tue Apr  4 01:50:24 2006
@@ -7,6 +7,18 @@
 typedef float  v8sf __attribute__ ((__vector_size__ (32)));
 typedef double v8sd __attribute__ ((__vector_size__ (64)));
 
+typedef intv2i64 __attribute__ ((__vector_size__ (16)));
+typedef intv4i32 __attribute__ ((__vector_size__ (16)));
+typedef short  v8i16 __attribute__ ((__vector_size__ (16)));
+typedef char   v16i8 __attribute__ ((__vector_size__ (16)));
+typedef float  v4f32 __attribute__ ((__vector_size__ (16)));
+typedef double v2f64 __attribute__ ((__vector_size__ (16)));
+
+typedef union {
+  v4i32 V;
+  int A[4];
+} IV;
+
 typedef union {
   v4sf V;
   float A[4];
@@ -22,6 +34,10 @@
   double A[8];
 } D8V;
 
+static void printIV(IV *F) {
+   printf(%u %u %u %u\n, F-A[0], F-A[1], F-A[2], F-A[3]);
+}
+
 static void printFV(FV *F) {
printf(%f %f %f %f\n, F-A[0], F-A[1], F-A[2], F-A[3]);
 }



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[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll

[Chris Lattner]

Changes in directory llvm/test/Regression/CodeGen/PowerPC:

vec_spat.ll updated: 1.2 - 1.3
---
Log message:

new testcase


---
Diffs of the changes:  (+17 -2)

 vec_spat.ll |   19 +--
 1 files changed, 17 insertions(+), 2 deletions(-)


Index: llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll
diff -u llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll:1.2 
llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll:1.3
--- llvm/test/Regression/CodeGen/PowerPC/vec_spat.ll:1.2Sat Mar 25 
00:11:56 2006
+++ llvm/test/Regression/CodeGen/PowerPC/vec_spat.llTue Apr  4 12:20:45 2006
@@ -1,7 +1,8 @@
 ; Test that vectors are scalarized/lowered correctly.
 ; RUN: llvm-as  %s | llc -march=ppc32 -mcpu=g5 | grep vspltw | wc -l | grep 2 

-; RUN: llvm-as  %s | llc -march=ppc32 -mcpu=g3 | grep stfs | wc -l | grep 4
-; RUN: llvm-as  %s | llc -march=ppc32 -mcpu=g5 | grep vsplti | wc -l | grep 2
+; RUN: llvm-as  %s | llc -march=ppc32 -mcpu=g3 | grep stfs | wc -l | grep 4 
+; RUN: llvm-as  %s | llc -march=ppc32 -mcpu=g5 | grep vsplti | wc -l | grep 2 

+; RUN: llvm-as  %s | llc -march=ppc32 -mcpu=g5 | grep vsplth | wc -l | grep 1
 
 %f4 = type 4 x float
 %i4 = type 4 x int
@@ -44,3 +45,17 @@
 ret void
 }
 
+void %splat_h(short %tmp, 16 x ubyte* %dst) {
+%tmp = insertelement 8 x short undef, short %tmp, uint 0
+%tmp72 = insertelement 8 x short %tmp, short %tmp, uint 1
+%tmp73 = insertelement 8 x short %tmp72, short %tmp, uint 2
+%tmp74 = insertelement 8 x short %tmp73, short %tmp, uint 3
+%tmp75 = insertelement 8 x short %tmp74, short %tmp, uint 4
+%tmp76 = insertelement 8 x short %tmp75, short %tmp, uint 5
+%tmp77 = insertelement 8 x short %tmp76, short %tmp, uint 6
+%tmp78 = insertelement 8 x short %tmp77, short %tmp, uint 7
+%tmp78 = cast 8 x short %tmp78 to 16 x ubyte
+store 16 x ubyte %tmp78, 16 x ubyte* %dst
+   ret void
+}
+



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[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h

[Chris Lattner]

Changes in directory llvm/include/llvm/Target:

TargetLowering.h updated: 1.66 - 1.67
---
Log message:

Move isShuffleLegal from TLI to Legalize.


---
Diffs of the changes:  (+8 -17)

 TargetLowering.h |   25 -
 1 files changed, 8 insertions(+), 17 deletions(-)


Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.66 
llvm/include/llvm/Target/TargetLowering.h:1.67
--- llvm/include/llvm/Target/TargetLowering.h:1.66  Mon Apr  3 19:25:10 2006
+++ llvm/include/llvm/Target/TargetLowering.h   Tue Apr  4 12:21:22 2006
@@ -191,6 +191,14 @@
   legal_fpimm_iterator legal_fpimm_end() const {
 return LegalFPImmediates.end();
   }
+  
+  /// isShuffleMaskLegal - Targets can use this to indicate that they only
+  /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
+  /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
+  /// are assumed to be legal.
+  virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
+return true;
+  }
 
   /// getOperationAction - Return how this operation should be treated: either
   /// it is legal, needs to be promoted to a larger size, needs to be
@@ -207,15 +215,6 @@
getOperationAction(Op, VT) == Custom;
   }
   
-  
-  /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
-  /// specified mask and type.  Targets can specify exactly which masks they
-  /// support and the code generator is tasked with not creating illegal masks.
-  bool isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const {
-return isOperationLegal(ISD::VECTOR_SHUFFLE, VT)  
-   isShuffleMaskLegal(Mask, VT);
-  }
-
   /// getTypeToPromoteTo - If the action for this operation is to promote, this
   /// method returns the ValueType to promote to.
   MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
@@ -515,14 +514,6 @@
 TargetDAGCombineArray[NT  3] |= 1  (NT7);
   }
   
-  /// isShuffleMaskLegal - Targets can use this to indicate that they only
-  /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
-  /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
-  /// are assumed to be legal.
-  virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
-return true;
-  }
-  
 public:
 
   
//======//



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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.351 - 1.352
---
Log message:

* Add supprot for SCALAR_TO_VECTOR operations where the input needs to be
  promoted/expanded (e.g. SCALAR_TO_VECTOR from i8/i16 on PPC).
* Add support for targets to request that VECTOR_SHUFFLE nodes be promoted
  to a canonical type, for example, we only want v16i8 shuffles on PPC.
* Move isShuffleLegal out of TLI into Legalize.
* Teach isShuffleLegal to allow shuffles that need to be promoted.



---
Diffs of the changes:  (+102 -21)

 LegalizeDAG.cpp |  123 ++--
 1 files changed, 102 insertions(+), 21 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.351 
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.352
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.351 Sat Apr  1 23:06:04 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp   Tue Apr  4 12:23:26 2006
@@ -165,6 +165,17 @@
   /// we know that this type is legal for the target.
   SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
   
+  /// isShuffleLegal - Return true if a vector shuffle is legal with the
+  /// specified mask and type.  Targets can specify exactly which masks they
+  /// support and the code generator is tasked with not creating illegal masks.
+  ///
+  /// Note that this will also return true for shuffles that are promoted to a
+  /// different type.
+  ///
+  /// If this is a legal shuffle, this method returns the (possibly promoted)
+  /// build_vector Mask.  If it's not a legal shuffle, it returns null.
+  SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
+  
   bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest);
 
   void LegalizeSetCCOperands(SDOperand LHS, SDOperand RHS, SDOperand CC);
@@ -178,6 +189,7 @@
 
   SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
   SDOperand ExpandBUILD_VECTOR(SDNode *Node);
+  SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
   SDOperand ExpandLegalINT_TO_FP(bool isSigned,
  SDOperand LegalOp,
  MVT::ValueType DestVT);
@@ -202,6 +214,51 @@
 };
 }
 
+/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
+/// specified mask and type.  Targets can specify exactly which masks they
+/// support and the code generator is tasked with not creating illegal masks.
+///
+/// Note that this will also return true for shuffles that are promoted to a
+/// different type.
+SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 
+ SDOperand Mask) const {
+  switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
+  default: return 0;
+  case TargetLowering::Legal:
+  case TargetLowering::Custom:
+break;
+  case TargetLowering::Promote: {
+// If this is promoted to a different type, convert the shuffle mask and
+// ask if it is legal in the promoted type!
+MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
+
+// If we changed # elements, change the shuffle mask.
+unsigned NumEltsGrowth =
+  MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
+assert(NumEltsGrowth  Cannot promote to vector type with fewer elts!);
+if (NumEltsGrowth  1) {
+  // Renumber the elements.
+  std::vectorSDOperand Ops;
+  for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
+SDOperand InOp = Mask.getOperand(i);
+for (unsigned j = 0; j != NumEltsGrowth; ++j) {
+  if (InOp.getOpcode() == ISD::UNDEF)
+Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
+  else {
+unsigned InEltNo = castConstantSDNode(InOp)-getValue();
+Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
+  }
+}
+  }
+  Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, Ops);
+}
+VT = NVT;
+break;
+  }
+  }
+  return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
+}
+
 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
 /// specified vector opcode.
 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
@@ -839,6 +896,11 @@
 }
 break;
   case ISD::SCALAR_TO_VECTOR:
+if (!TLI.isTypeLegal(Node-getOperand(0).getValueType())) {
+  Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
+  break;
+}
+
 Tmp1 = LegalizeOp(Node-getOperand(0));  // InVal
 Result = DAG.UpdateNodeOperands(Result, Tmp1);
 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
@@ -853,35 +915,43 @@
 break;
   }
   // FALLTHROUGH
-case TargetLowering::Expand: {
-  // If the target doesn't support this, store the value to a temporary
-  // stack slot, then EXTLOAD the vector back out.
-  // TODO: If a target doesn't support this, create a stack slot for the
-  // 

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrAltivec.td

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.128 - 1.129
PPCISelLowering.h updated: 1.38 - 1.39
PPCInstrAltivec.td updated: 1.32 - 1.33
---
Log message:

Ask legalize to promote all vector shuffles to be v16i8 instead of having to
handle all 4 PPC vector types.   This simplifies the matching code and allows
us to eliminate a bunch of patterns.  This also adds cases we were missing,
such as CodeGen/PowerPC/vec_splat.ll:splat_h.



---
Diffs of the changes:  (+68 -45)

 PPCISelLowering.cpp |   56 
 PPCISelLowering.h   |4 +--
 PPCInstrAltivec.td  |   53 +
 3 files changed, 68 insertions(+), 45 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.128 
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.129
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.128   Mon Apr  3 18:58:04 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Apr  4 12:25:31 2006
@@ -181,8 +181,9 @@
   setOperationAction(ISD::OR  , (MVT::ValueType)VT, Legal);
   setOperationAction(ISD::XOR , (MVT::ValueType)VT, Legal);
   
-  // We can custom expand all VECTOR_SHUFFLEs to VPERM.
-  setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
+  // We promote all shuffles to v16i8.
+  setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
+  AddPromotedToType(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
   
   setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
   setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
@@ -196,6 +197,10 @@
   setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
 }
 
+// We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
+// with merges, splats, etc.
+setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
+
 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
@@ -266,33 +271,47 @@
 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
 /// specifies a splat of a single element that is suitable for input to
 /// VSPLTB/VSPLTH/VSPLTW.
-bool PPC::isSplatShuffleMask(SDNode *N) {
-  assert(N-getOpcode() == ISD::BUILD_VECTOR);
-  
-  // We can only splat 8-bit, 16-bit, and 32-bit quantities.
-  if (N-getNumOperands() != 4  N-getNumOperands() != 8 
-  N-getNumOperands() != 16)
-return false;
+bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
+  assert(N-getOpcode() == ISD::BUILD_VECTOR 
+ N-getNumOperands() == 16 
+ (EltSize == 1 || EltSize == 2 || EltSize == 4));
   
   // This is a splat operation if each element of the permute is the same, and
   // if the value doesn't reference the second vector.
+  unsigned ElementBase = 0;
   SDOperand Elt = N-getOperand(0);
+  if (ConstantSDNode *EltV = dyn_castConstantSDNode(Elt))
+ElementBase = EltV-getValue();
+  else
+return false;   // FIXME: Handle UNDEF elements too!
+
+  if (castConstantSDNode(Elt)-getValue() = 16)
+return false;
+  
+  // Check that they are consequtive.
+  for (unsigned i = 1; i != EltSize; ++i) {
+if (!isaConstantSDNode(N-getOperand(i)) ||
+castConstantSDNode(N-getOperand(i))-getValue() != i+ElementBase)
+  return false;
+  }
+  
   assert(isaConstantSDNode(Elt)  Invalid VECTOR_SHUFFLE mask!);
-  for (unsigned i = 1, e = N-getNumOperands(); i != e; ++i) {
+  for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
 assert(isaConstantSDNode(N-getOperand(i)) 
Invalid VECTOR_SHUFFLE mask!);
-if (N-getOperand(i) != Elt) return false;
+for (unsigned j = 0; j != EltSize; ++j)
+  if (N-getOperand(i+j) != N-getOperand(j))
+return false;
   }
 
-  // Make sure it is a splat of the first vector operand.
-  return castConstantSDNode(Elt)-getValue()  N-getNumOperands();
+  return true;
 }
 
 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
-unsigned PPC::getVSPLTImmediate(SDNode *N) {
-  assert(isSplatShuffleMask(N));
-  return castConstantSDNode(N-getOperand(0))-getValue();
+unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
+  assert(isSplatShuffleMask(N, EltSize));
+  return castConstantSDNode(N-getOperand(0))-getValue() / EltSize;
 }
 
 /// isVecSplatImm - Return true if this is a build_vector of constants which
@@ -734,7 +753,10 @@
 // Cases that are handled by instructions that take permute immediates
 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
 // selected by the instruction selector.
-if (PPC::isSplatShuffleMask(PermMask.Val)  V2.getOpcode() == ISD::UNDEF)
+if (V2.getOpcode() == ISD::UNDEF  
+

[llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/2006-04-04-zextload.ll

[Chris Lattner]

Changes in directory llvm/test/Regression/CodeGen/Alpha:

2006-04-04-zextload.ll added (r1.1)
---
Log message:

New testcase


---
Diffs of the changes:  (+36 -0)

 2006-04-04-zextload.ll |   36 
 1 files changed, 36 insertions(+)


Index: llvm/test/Regression/CodeGen/Alpha/2006-04-04-zextload.ll
diff -c /dev/null llvm/test/Regression/CodeGen/Alpha/2006-04-04-zextload.ll:1.1
*** /dev/null   Tue Apr  4 12:38:41 2006
--- llvm/test/Regression/CodeGen/Alpha/2006-04-04-zextload.ll   Tue Apr  4 
12:38:31 2006
***
*** 0 
--- 1,36 
+ ; RUN: llvm-as  %s | llc -march=alpha
+ 
+ target endian = little
+ target pointersize = 64
+ target triple = alphaev67-unknown-linux-gnu
+   %llvm.dbg.compile_unit.type = type { uint, {  }*, uint, uint, sbyte*, 
sbyte*, sbyte* }
+   %struct._Callback_list = type { %struct._Callback_list*, void (uint, 
%struct.ios_base*, int)*, int, int }
+   %struct._Impl = type { int, %struct.facet**, ulong, %struct.facet**, 
sbyte** }
+   %struct._Words = type { sbyte*, long }
+   struct.__codecvt_abstract_basechar,char,__mbstate_t = type { 
%struct.facet }
+   struct.basic_streambufchar,std::char_traitschar  = type { int 
(...)**, sbyte*, sbyte*, sbyte*, sbyte*, sbyte*, sbyte*, %struct.locale }
+   %struct.facet = type { int (...)**, int }
+   %struct.ios_base = type { int (...)**, long, long, uint, uint, uint, 
%struct._Callback_list*, %struct._Words, [8 x %struct._Words], int, 
%struct._Words*, %struct.locale }
+   %struct.locale = type { %struct._Impl* }
+   struct.ostreambuf_iteratorchar,std::char_traitschar  = type { 
struct.basic_streambufchar,std::char_traitschar *, bool }
+ %llvm.dbg.compile_unit1047 = external global %llvm.dbg.compile_unit.type  
; %llvm.dbg.compile_unit.type* [#uses=1]
+ 
+ implementation   ; Functions:
+ 
+ void 
%_ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE15_M_insert_floatIdEES3_S3_RSt8ios_baseccT_()
 {
+ entry:
+   %tmp234 = seteq sbyte 0, 0  ; bool [#uses=1]
+   br bool %tmp234, label %cond_next243, label %cond_true235
+ 
+ cond_true235: ; preds = %entry
+   ret void
+ 
+ cond_next243: ; preds = %entry
+   %tmp428 = load long* null   ; long [#uses=1]
+   %tmp428 = cast long %tmp428 to uint ; uint [#uses=1]
+   %tmp429 = alloca sbyte, uint %tmp428; sbyte* [#uses=0]
+   call void %llvm.dbg.stoppoint( uint 1146, uint 0, {  }* cast 
(%llvm.dbg.compile_unit.type* %llvm.dbg.compile_unit1047 to {  }*) )
+   unreachable
+ }
+ 
+ declare void %llvm.dbg.stoppoint(uint, uint, {  }*)



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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.143 - 1.144
---
Log message:

Do not create ZEXTLOAD's unless we are before legalize or the operation is
legal.


---
Diffs of the changes:  (+2 -1)

 DAGCombiner.cpp |3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.143 
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.144
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.143 Mon Apr  3 12:29:28 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp   Tue Apr  4 12:39:18 2006
@@ -1193,7 +1193,8 @@
 
 LoadedVT = N0.getOpcode() == ISD::LOAD ? VT :
castVTSDNode(N0.getOperand(3))-getVT();
-if (EVT != MVT::Other  LoadedVT  EVT) {
+if (EVT != MVT::Other  LoadedVT  EVT 
+(!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
   MVT::ValueType PtrType = N0.getOperand(1).getValueType();
   // For big endian targets, we need to add an offset to the pointer to 
load
   // the correct bytes.  For little endian systems, we merely need to read



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[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFrameInfo.h

[Chris Lattner]

Changes in directory llvm/include/llvm/CodeGen:

MachineFrameInfo.h updated: 1.15 - 1.16
---
Log message:

Make sure to consider alignment of variable sized objects.
This, along with the previous dag combiner fix, fixes 
CodeGen/Alpha/2006-04-04-zextload.ll


---
Diffs of the changes:  (+1 -0)

 MachineFrameInfo.h |1 +
 1 files changed, 1 insertion(+)


Index: llvm/include/llvm/CodeGen/MachineFrameInfo.h
diff -u llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.15 
llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.16
--- llvm/include/llvm/CodeGen/MachineFrameInfo.h:1.15   Mon Apr  3 16:38:39 2006
+++ llvm/include/llvm/CodeGen/MachineFrameInfo.hTue Apr  4 12:39:56 2006
@@ -225,6 +225,7 @@
   ///
   int CreateVariableSizedObject() {
 HasVarSizedObjects = true;
+if (MaxAlignment  1) MaxAlignment = 1;
 Objects.push_back(StackObject(0, 1, -1));
 return Objects.size()-NumFixedObjects-1;
   }



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[llvm-commits] CVS: llvm-www/pubs/2006-04-04-CGO-GraphColoring.html 2006-04-04-CGO-GraphColoring.pdf index.html

[Chris Lattner]

Changes in directory llvm-www/pubs:

2006-04-04-CGO-GraphColoring.html added (r1.1)
2006-04-04-CGO-GraphColoring.pdf added (r1.1)
index.html updated: 1.35 - 1.36
---
Log message:

Add a new paper that uses LLVM.


---
Diffs of the changes:  (+49 -0)

 2006-04-04-CGO-GraphColoring.html |   47 ++
 2006-04-04-CGO-GraphColoring.pdf  |0 
 index.html|2 +
 3 files changed, 49 insertions(+)


Index: llvm-www/pubs/2006-04-04-CGO-GraphColoring.html
diff -c /dev/null llvm-www/pubs/2006-04-04-CGO-GraphColoring.html:1.1
*** /dev/null   Tue Apr  4 13:25:19 2006
--- llvm-www/pubs/2006-04-04-CGO-GraphColoring.html Tue Apr  4 13:25:09 2006
***
*** 0 
--- 1,47 
+ !DOCTYPE HTML PUBLIC -//W3C//DTD HTML 4.01 Transitional//EN
+ html
+ head
+   meta http-equiv=Content-Type content=text/html; charset=UTF-8 /
+   link rel=stylesheet href=../llvm.css type=text/css media=screen /
+   titleTailoring Graph-coloring Register Allocation For Runtime 
Compilation/title
+ /head
+ body
+ 
+ div class=pub_title
+   Tailoring Graph-coloring Register Allocation For Runtime Compilation
+ /div
+ div class=pub_author
+   Keith D. Cooper and Anshuman Dasgupta
+ /div
+ 
+ h2Abstract:/h2
+ blockquote
+ Just-in-time compilers are invoked during application 
+ execution and therefore need to ensure fast compilation 
+ times. Consequently, runtime compiler designers are averse 
+ to implementing compile-time intensive optimization algorithms. Instead, they 
tend to select faster but less effective 
+ transformations. In this paper, we explore this trade-off for 
+ an important optimization ⓠglobal register allocation. We 
+ present a graph-coloring register allocator that has been 
+ redesigned for runtime compilation. Compared to Chaitin-Briggs [7], a 
standard graph-coloring technique, the reformulated algorithm requires 
considerably less allocation 
+ time and produces allocations that are only marginally 
+ worse than those of Chaitin-Briggs. Our experimental results indicate that 
the allocator performs better than the 
+ linear-scan and Chaitin-Briggs allocators on most benchmarks in a runtime 
compilation environment. By increasing 
+ allocation efficiency and preserving optimization quality, 
+ the presented algorithm increases the suitability and profitability of a 
graph-coloring register allocation strategy for 
+ a runtime compiler. 
+ /blockquote
+ 
+ h2Published:/h2
+ blockquote
+   Tailoring Graph-coloring Register Allocation For Runtime Compilation, 
Keith D. Cooper and Anshuman Dasgupta.br
+   Proceedings of the 2006 International Symposium on a 
href=http://www.cgo.org/;Code Generation and Optimization/a (CGO'06), New 
York, New York, 2006.
+ /blockquote
+ 
+ h2Download:/h2
+ ul
+   lia href=2006-04-04-CGO-GraphColoring.pdfTailoring Graph-coloring 
Register Allocation For Runtime Compilation/a (PDF)/li
+ /ul
+ 
+ /body
+ /html


Index: llvm-www/pubs/2006-04-04-CGO-GraphColoring.pdf


Index: llvm-www/pubs/index.html
diff -u llvm-www/pubs/index.html:1.35 llvm-www/pubs/index.html:1.36
--- llvm-www/pubs/index.html:1.35   Fri Dec 16 12:33:09 2005
+++ llvm-www/pubs/index.htmlTue Apr  4 13:25:09 2006
@@ -34,6 +34,8 @@
 
 ol
 
+lia href=2006-04-04-CGO-GraphColoring.htmlTailoring Graph-coloring 
Register Allocation For Runtime Compilation/abrKeith D. Cooper and 
Anshuman Dasguptabri Proc. of the 2006 International Symposium on Code 
Generation and Optimization (CGO'06)/i, New York, New York, 2006.br/li
+
 lia href=2005-TR-DSAEvaluation.htmlHow Successful is Data Structure 
Analysis in Isolating and Analyzing
   Linked Data Structures?/abr Patrick Meredith, Balpreet Pankaj, Swarup 
Sahoo, Chris Lattner and Vikram Advebr iTechnical Report 
#UIUCDCS-R-2005-2658, Computer Science Dept., Univ. of
 Illinois/i, Dec. 2005.br /li



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[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c

[Evan Cheng]

Changes in directory llvm-test/SingleSource/UnitTests/Vector/SSE:

sse.expandfft.c updated: 1.1 - 1.2
---
Log message:

Eliminate timing printout. Dump more info for more meaningful comparison.


---
Diffs of the changes:  (+10 -6)

 sse.expandfft.c |   16 ++--
 1 files changed, 10 insertions(+), 6 deletions(-)


Index: llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c
diff -u llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c:1.1 
llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c:1.2
--- llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c:1.1 Mon Apr 
 3 19:47:54 2006
+++ llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c Tue Apr  4 
13:37:42 2006
@@ -65,18 +65,22 @@
   printf( for n=%d, fwd/bck error=%e\n,N,error);
   first = 0;
} else {
-  t1   = ((float)clock())/((float) CLOCKS_PER_SEC);
+   unsigned j = 0;
   for(it=0;it1000;it++){
  sign = +1.0;
  cfft2(n,x,y,w,sign);
  sign = -1.0;
  cfft2(n,y,x,w,sign);
   }
-  t1   = ((float)clock())/((float) CLOCKS_PER_SEC) - t1;
-  t1   = t1/2000.0;
-  ln2 = 10.0; // reset this for different N 
-  mflops = 5.0*((float) N)*ln2/((1.e+6)*t1);
-  printf( for n=%d, t1=%e, mflops=%e\n,n,t1,mflops);
+  printf( for n=%d\n,n);
+  for (i = 0; iN; ++i) {
+printf(%g  , w[i]);
+j++;
+if (j == 4) {
+  printf(\n);
+  j = 0;
+}
+  }
}
}
 }



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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td

[Evan Cheng]

Changes in directory llvm/lib/Target/X86:

X86InstrSSE.td updated: 1.58 - 1.59
---
Log message:

PSHUF* encoding bugs.


---
Diffs of the changes:  (+6 -6)

 X86InstrSSE.td |   12 ++--
 1 files changed, 6 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.58 
llvm/lib/Target/X86/X86InstrSSE.td:1.59
--- llvm/lib/Target/X86/X86InstrSSE.td:1.58 Mon Apr  3 22:04:07 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td  Tue Apr  4 13:40:36 2006
@@ -1239,14 +1239,14 @@
 }
 
 // Shuffle and unpack instructions
-def PSHUFWrr : PSIi80x70, MRMDestReg,
+def PSHUFWrr : PSIi80x70, MRMSrcReg,
  (ops VR64:$dst, VR64:$src1, i8imm:$src2),
  pshufw {$src2, $src1, $dst|$dst, $src1, $src2}, [];
 def PSHUFWrm : PSIi80x70, MRMSrcMem,
  (ops VR64:$dst, i64mem:$src1, i8imm:$src2),
  pshufw {$src2, $src1, $dst|$dst, $src1, $src2}, [];
 
-def PSHUFDrr : PDIi80x70, MRMDestReg,
+def PSHUFDrr : PDIi80x70, MRMSrcReg,
  (ops VR128:$dst, VR128:$src1, i8imm:$src2),
  pshufd {$src2, $src1, $dst|$dst, $src1, $src2},
  [(set VR128:$dst, (v4i32 (vector_shuffle
@@ -1260,14 +1260,14 @@
PSHUFD_shuffle_mask:$src2)))];
 
 // SSE2 with ImmT == Imm8 and XS prefix.
-def PSHUFHWrr : Ii80x70, MRMDestReg,
+def PSHUFHWrr : Ii80x70, MRMSrcReg,
 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
 pshufhw {$src2, $src1, $dst|$dst, $src1, $src2},
 [(set VR128:$dst, (v8i16 (vector_shuffle
   VR128:$src1, (undef),
   PSHUFHW_shuffle_mask:$src2)))],
 XS, Requires[HasSSE2];
-def PSHUFHWrm : Ii80x70, MRMDestMem,
+def PSHUFHWrm : Ii80x70, MRMSrcMem,
 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
 pshufhw {$src2, $src1, $dst|$dst, $src1, $src2},
 [(set VR128:$dst, (v8i16 (vector_shuffle
@@ -1276,14 +1276,14 @@
 XS, Requires[HasSSE2];
 
 // SSE2 with ImmT == Imm8 and XD prefix.
-def PSHUFLWrr : Ii80x70, MRMDestReg,
+def PSHUFLWrr : Ii80x70, MRMSrcReg,
 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
 pshuflw {$src2, $src1, $dst|$dst, $src1, $src2},
 [(set VR128:$dst, (v8i16 (vector_shuffle
   VR128:$src1, (undef),
   PSHUFLW_shuffle_mask:$src2)))],
 XD, Requires[HasSSE2];
-def PSHUFLWrm : Ii80x70, MRMDestMem,
+def PSHUFLWrm : Ii80x70, MRMSrcMem,
 (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
 pshuflw {$src2, $src1, $dst|$dst, $src1, $src2},
 [(set VR128:$dst, (v8i16 (vector_shuffle



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[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c

[Evan Cheng]

Changes in directory llvm-test/SingleSource/UnitTests/Vector/SSE:

sse.expandfft.c updated: 1.2 - 1.3
---
Log message:

Bump up the size of the test.


---
Diffs of the changes:  (+3 -3)

 sse.expandfft.c |6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c
diff -u llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c:1.2 
llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c:1.3
--- llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c:1.2 Tue Apr 
 4 13:37:42 2006
+++ llvm-test/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c Tue Apr  4 
13:51:30 2006
@@ -3,7 +3,7 @@
 #include time.h
 #include float.h
 #include xmmintrin.h
-#define N 256
+#define N 1024
 #define N2 N/2
 main()
 {
@@ -65,8 +65,8 @@
   printf( for n=%d, fwd/bck error=%e\n,N,error);
   first = 0;
} else {
-   unsigned j = 0;
-  for(it=0;it1000;it++){
+  unsigned j = 0;
+  for(it=0;it2;it++){
  sign = +1.0;
  cfft2(n,x,y,w,sign);
  sign = -1.0;



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[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c

[Evan Cheng]

Changes in directory llvm-test/SingleSource/UnitTests/Vector/SSE:

sse.stepfft.c updated: 1.1 - 1.2
---
Log message:

- Remove calls to clock() and timing printfs.
- Print out more data for comparisons.
- Bump up the test size.


---
Diffs of the changes:  (+11 -7)

 sse.stepfft.c |   18 +++---
 1 files changed, 11 insertions(+), 7 deletions(-)


Index: llvm-test/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c
diff -u llvm-test/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c:1.1 
llvm-test/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c:1.2
--- llvm-test/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c:1.1   Mon Apr 
 3 19:47:54 2006
+++ llvm-test/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c   Tue Apr  4 
13:52:26 2006
@@ -63,18 +63,22 @@
   printf( for n=%d, fwd/bck error=%e\n,N,error);
   first = 0;
} else {
-  t1   = ((float)clock())/((float) CLOCKS_PER_SEC);
-  for(it=0;it1;it++){
+  unsigned j = 0;
+  for(it=0;it2;it++){
  sign = +1.0;
  cfft2(n,x,y,w,sign);
  sign = -1.0;
  cfft2(n,y,x,w,sign);
   }
-  t1   = ((float)clock())/((float) CLOCKS_PER_SEC) - t1;
-  t1   = t1/2.0;
-  ln2 = 10.0; /* reset this for different N  */
-  mflops = 5.0*((float) N)*ln2/((1.e+6)*t1);
-  printf( for n=%d, t1=%e, mflops=%e\n,n,t1,mflops);
+  printf( for n=%d\n,n);
+  for (i = 0; iN; ++i) {
+printf(%g  , w[i]);
+j++;
+if (j == 4) {
+  printf(\n);
+  j = 0;
+}
+  }
}
}
 }



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[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c alti.stepfft.c

[Evan Cheng]

Changes in directory llvm-test/SingleSource/UnitTests/Vector/Altivec:

alti.expandfft.c updated: 1.2 - 1.3
alti.stepfft.c updated: 1.2 - 1.3
---
Log message:

Remove calls to clock() and timing info printf's.


---
Diffs of the changes:  (+0 -11)

 alti.expandfft.c |5 -
 alti.stepfft.c   |6 --
 2 files changed, 11 deletions(-)


Index: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c
diff -u llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c:1.2 
llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c:1.3
--- llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.c:1.2
Tue Apr  4 01:08:25 2006
+++ llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.expandfft.cTue Apr 
 4 13:56:15 2006
@@ -81,17 +81,12 @@
 printf( for n=%d, fwd/bck error=%e\n,n,error);
 first = 0;
  } else {
-t1   = ((double)clock())/((double) CLOCKS_PER_SEC);
 for(it=0;itnits;it++){
sign = +1.0;
cfft2(n,x,y,w,sign);
sign = -1.0;
cfft2(n,y,x,w,sign);
 }
-t1   = ((double)clock())/((double) CLOCKS_PER_SEC) - t1;
-t1   = 0.5*t1/((double) nits);
-mflops = 5.0*((double) n)*((double) ln2)/((1.e+6)*t1);
-printf( for n=%d, t1=%e, mflops=%e\n,n,t1,mflops);
  }
   }
   if((ln2%4)==0) nits /= 10;


Index: llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.stepfft.c
diff -u llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.stepfft.c:1.2 
llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.stepfft.c:1.3
--- llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.stepfft.c:1.2  Tue Apr 
 4 01:08:25 2006
+++ llvm-test/SingleSource/UnitTests/Vector/Altivec/alti.stepfft.c  Tue Apr 
 4 13:56:15 2006
@@ -62,18 +62,12 @@
   printf( for n=%d, fwd/bck error=%e\n,N,error);
   first = 0;
} else {
-  t1   = ((float)clock())/((float) CLOCKS_PER_SEC);
   for(it=0;itnits;it++){
  sign = +1.0;
  cfft2(n,x,y,w,sign);
  sign = -1.0;
  cfft2(n,y,x,w,sign);
   }
-  t1   = ((float)clock())/((float) CLOCKS_PER_SEC) - t1;
-  t1   = t1/(2.0*((float) nits));
-  ln2 = 10.0; /* reset this for different N  */
-  mflops = 5.0*((float) N)*ln2/((1.e+6)*t1);
-  printf( for n=%d, t1=%e, mflops=%e\n,n,t1,mflops);
}
}
 }



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[llvm-commits] CVS: llvm/include/llvm/Type.h

[Chris Lattner]

Changes in directory llvm/include/llvm:

Type.h updated: 1.83 - 1.84
---
Log message:

How could this ever have worked?


---
Diffs of the changes:  (+1 -1)

 Type.h |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/include/llvm/Type.h
diff -u llvm/include/llvm/Type.h:1.83 llvm/include/llvm/Type.h:1.84
--- llvm/include/llvm/Type.h:1.83   Tue Feb  7 00:17:10 2006
+++ llvm/include/llvm/Type.hTue Apr  4 14:05:42 2006
@@ -34,7 +34,7 @@
 #ifndef LLVM_TYPE_H
 #define LLVM_TYPE_H
 
-#include AbstractTypeUser.h
+#include llvm/AbstractTypeUser.h
 #include llvm/Support/Casting.h
 #include llvm/Support/DataTypes.h
 #include llvm/ADT/GraphTraits.h



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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td X86RegisterInfo.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target/X86:

X86InstrSSE.td updated: 1.59 - 1.60
X86RegisterInfo.cpp updated: 1.133 - 1.134
---
Log message:

Minor fixes + naming changes.


---
Diffs of the changes:  (+157 -156)

 X86InstrSSE.td  |  309 ++--
 X86RegisterInfo.cpp |4 
 2 files changed, 157 insertions(+), 156 deletions(-)


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.59 
llvm/lib/Target/X86/X86InstrSSE.td:1.60
--- llvm/lib/Target/X86/X86InstrSSE.td:1.59 Tue Apr  4 13:40:36 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td  Tue Apr  4 14:12:30 2006
@@ -335,45 +335,46 @@
 [(set FR64:$dst, (fsub FR64:$src1, (loadf64 addr:$src2)))];
 }
 
-def SQRTSSrr : SSI0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
- sqrtss {$src, $dst|$dst, $src},
- [(set FR32:$dst, (fsqrt FR32:$src))];
-def SQRTSSrm : SSI0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
+def SQRTSSr : SSI0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
+sqrtss {$src, $dst|$dst, $src},
+[(set FR32:$dst, (fsqrt FR32:$src))];
+def SQRTSSm : SSI0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
  sqrtss {$src, $dst|$dst, $src},
  [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))];
-def SQRTSDrr : SDI0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
+def SQRTSDr : SDI0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
  sqrtsd {$src, $dst|$dst, $src},
  [(set FR64:$dst, (fsqrt FR64:$src))];
-def SQRTSDrm : SDI0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
+def SQRTSDm : SDI0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
  sqrtsd {$src, $dst|$dst, $src},
  [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))];
 
-def RSQRTSSrr : SSI0x52, MRMSrcReg, (ops FR32:$dst, FR32:$src),
+def RSQRTSSr : SSI0x52, MRMSrcReg, (ops FR32:$dst, FR32:$src),
rsqrtss {$src, $dst|$dst, $src}, [];
-def RSQRTSSrm : SSI0x52, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
+def RSQRTSSm : SSI0x52, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
rsqrtss {$src, $dst|$dst, $src}, [];
-def RCPSSrr : SSI0x53, MRMSrcReg, (ops FR32:$dst, FR32:$src),
-  rcpss {$src, $dst|$dst, $src}, [];
-def RCPSSrm : SSI0x53, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
-  rcpss {$src, $dst|$dst, $src}, [];
-
-def MAXSSrr : SSI0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src),
-  maxss {$src, $dst|$dst, $src}, [];
-def MAXSSrm : SSI0x5F, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
-  maxss {$src, $dst|$dst, $src}, [];
-def MAXSDrr : SDI0x5F, MRMSrcReg, (ops FR64:$dst, FR64:$src),
-  maxsd {$src, $dst|$dst, $src}, [];
-def MAXSDrm : SDI0x5F, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
-  maxsd {$src, $dst|$dst, $src}, [];
-def MINSSrr : SSI0x5D, MRMSrcReg, (ops FR32:$dst, FR32:$src),
-  minss {$src, $dst|$dst, $src}, [];
-def MINSSrm : SSI0x5D, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
-  minss {$src, $dst|$dst, $src}, [];
-def MINSDrr : SDI0x5D, MRMSrcReg, (ops FR64:$dst, FR64:$src),
-  minsd {$src, $dst|$dst, $src}, [];
-def MINSDrm : SDI0x5D, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
-  minsd {$src, $dst|$dst, $src}, [];
+def RCPSSr : SSI0x53, MRMSrcReg, (ops FR32:$dst, FR32:$src),
+ rcpss {$src, $dst|$dst, $src}, [];
+def RCPSSm : SSI0x53, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
+ rcpss {$src, $dst|$dst, $src}, [];
 
+let isTwoAddress = 1 in {
+def MAXSSrr : SSI0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
+  maxss {$src2, $dst|$dst, $src2}, [];
+def MAXSSrm : SSI0x5F, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
+  maxss {$src2, $dst|$dst, $src2}, [];
+def MAXSDrr : SDI0x5F, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
+  maxsd {$src2, $dst|$dst, $src2}, [];
+def MAXSDrm : SDI0x5F, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
+  maxsd {$src2, $dst|$dst, $src2}, [];
+def MINSSrr : SSI0x5D, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
+  minss {$src2, $dst|$dst, $src2}, [];
+def MINSSrm : SSI0x5D, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
+  minss {$src2, $dst|$dst, $src2}, [];
+def MINSDrr : SDI0x5D, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
+  minsd {$src2, $dst|$dst, $src2}, [];
+def MINSDrm : SDI0x5D, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
+  minsd {$src2, $dst|$dst, $src2}, [];
+}
 
 // Aliases to match intrinsics which expect XMM operand(s).
 let isTwoAddress = 1 in {
@@ -416,23 +417,23 @@
int_x86_sse2_sub_sd;
 }
 
-def Int_SQRTSSrr : SS_Intr0x51, sqrtss {$src, $dst|$dst, $src},
-int_x86_sse_sqrt_ss;
-def 

[llvm-commits] CVS: llvm/include/llvm/Intrinsics.td IntrinsicsX86.td

[Evan Cheng]

Changes in directory llvm/include/llvm:

Intrinsics.td updated: 1.31 - 1.32
IntrinsicsX86.td updated: 1.8 - 1.9
---
Log message:

Added intrinsics to match __builtin_ia32_pslldqi128 and
__builtin_ia32_psrldqi128.


---
Diffs of the changes:  (+11 -0)

 Intrinsics.td|1 +
 IntrinsicsX86.td |   10 ++
 2 files changed, 11 insertions(+)


Index: llvm/include/llvm/Intrinsics.td
diff -u llvm/include/llvm/Intrinsics.td:1.31 
llvm/include/llvm/Intrinsics.td:1.32
--- llvm/include/llvm/Intrinsics.td:1.31Mon Mar 27 18:15:44 2006
+++ llvm/include/llvm/Intrinsics.td Tue Apr  4 16:48:31 2006
@@ -82,6 +82,7 @@
 def llvm_v16i8_ty  : LLVMPackedTypev16i8,16, llvm_sbyte_ty;  // 16 x 
sbyte
 def llvm_v8i16_ty  : LLVMPackedTypev8i16, 8, llvm_short_ty;  // 8 x short
 
+def llvm_v2i64_ty  : LLVMPackedTypev2i64, 2, llvm_long_ty;   // 2 x long
 def llvm_v2i32_ty  : LLVMPackedTypev2i32, 2, llvm_int_ty;// 2 x int
 def llvm_v4i32_ty  : LLVMPackedTypev4i32, 4, llvm_int_ty;// 4 x int
 def llvm_v4f32_ty  : LLVMPackedTypev4f32, 4, llvm_float_ty;  // 4 x float


Index: llvm/include/llvm/IntrinsicsX86.td
diff -u llvm/include/llvm/IntrinsicsX86.td:1.8 
llvm/include/llvm/IntrinsicsX86.td:1.9
--- llvm/include/llvm/IntrinsicsX86.td:1.8  Fri Mar 31 15:28:46 2006
+++ llvm/include/llvm/IntrinsicsX86.td  Tue Apr  4 16:48:31 2006
@@ -183,6 +183,16 @@
  llvm_v2f64_ty], [InstrNoMem];
 }
 
+// Integer shift ops.
+let TargetPrefix = x86 in {  // All intrinsics start with llvm.x86..
+  def int_x86_sse2_psll_dq : GCCBuiltin__builtin_ia32_pslldqi128,
+  Intrinsic[llvm_v2i64_ty, llvm_v2i64_ty,
+ llvm_int_ty], [InstrNoMem];
+  def int_x86_sse2_psrl_dq : GCCBuiltin__builtin_ia32_psrldqi128,
+  Intrinsic[llvm_v2i64_ty, llvm_v2i64_ty,
+ llvm_int_ty], [InstrNoMem];
+}
+
 // Misc.
 let TargetPrefix = x86 in {  // All intrinsics start with llvm.x86..
   def int_x86_sse2_packsswb_128 : GCCBuiltin__builtin_ia32_packsswb128,



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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td

[Evan Cheng]

Changes in directory llvm/lib/Target/X86:

X86InstrSSE.td updated: 1.60 - 1.61
---
Log message:

Added pslldq and psrldq.


---
Diffs of the changes:  (+18 -0)

 X86InstrSSE.td |   18 ++
 1 files changed, 18 insertions(+)


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.60 
llvm/lib/Target/X86/X86InstrSSE.td:1.61
--- llvm/lib/Target/X86/X86InstrSSE.td:1.60 Tue Apr  4 14:12:30 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td  Tue Apr  4 16:49:39 2006
@@ -57,6 +57,11 @@
   return N-isExactlyValue(+0.0);
 }];
 
+def PSxLDQ_imm  : SDNodeXFormimm, [{
+  // Transformation function: imm  3
+  return getI32Imm(N-getValue()  3);
+}];
+
 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
 // SHUFP* etc. imm.
 def SHUFFLE_get_shuf_imm : SDNodeXFormbuild_vector, [{
@@ -1159,6 +1164,13 @@
 (load addr:$src2];
 }
 
+let isTwoAddress = 1 in {
+def PSLLDQri : PDIi80x73, MRM7r, (ops VR128:$dst, VR128:$src1, 
i32i8imm:$src2),
+ pslldq {$src2, $dst|$dst, $src2}, [];
+def PSRLDQri : PDIi80x73, MRM7r, (ops VR128:$dst, VR128:$src1, 
i32i8imm:$src2),
+ psrldq {$src2, $dst|$dst, $src2}, [];
+}
+
 // Logical
 let isTwoAddress = 1 in {
 let isCommutable = 1 in {
@@ -1721,6 +1733,12 @@
   (v4f32 (PSHUFLWmi addr:$src1, PSHUFLW_fp_shuffle_mask:$sm)),
   Requires[HasSSE2];
 
+// 128-bit logical shifts
+def : Pat(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
+  (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)));
+def : Pat(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
+  (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)));
+
 // Logical ops
 def : Pat(and (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)),
   (ANDPSrm VR128:$src1, addr:$src2);



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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.129 - 1.130
---
Log message:

Fix some broken logic that would cause us to codegen 
{2147483647,2147483647,2147483647,2147483647} as 'vspltisb v0, -1'.


---
Diffs of the changes:  (+2 -2)

 PPCISelLowering.cpp |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.129 
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.130
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.129   Tue Apr  4 12:25:31 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Apr  4 17:28:35 2006
@@ -353,8 +353,8 @@
 ValSizeInBytes = 1;
 
 // If the top half equals the bottom half, we're still ok.
-if (((Value  (ValSizeInBytes*8))  ((8  ValSizeInBytes)-1)) !=
- (Value ((8  ValSizeInBytes)-1)))
+if (((Value  (ValSizeInBytes*8))  (1  (8*ValSizeInBytes)-1)) !=
+ (Value (1  (8*ValSizeInBytes)-1)))
   return false;
   }
 



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[llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td

[Chris Lattner]

Changes in directory llvm/include/llvm:

IntrinsicsPowerPC.td updated: 1.14 - 1.15
---
Log message:

add average intrinsics.


---
Diffs of the changes:  (+8 -0)

 IntrinsicsPowerPC.td |8 
 1 files changed, 8 insertions(+)


Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.14 
llvm/include/llvm/IntrinsicsPowerPC.td:1.15
--- llvm/include/llvm/IntrinsicsPowerPC.td:1.14 Mon Apr  3 20:40:06 2006
+++ llvm/include/llvm/IntrinsicsPowerPC.td  Tue Apr  4 18:13:21 2006
@@ -186,6 +186,14 @@
 [InstrNoMem];
 }
 
+// Vector average.
+def int_ppc_altivec_vavgsb : PowerPC_Vec_BBB_Intrinsicvavgsb;
+def int_ppc_altivec_vavgsh : PowerPC_Vec_HHH_Intrinsicvavgsh;
+def int_ppc_altivec_vavgsw : PowerPC_Vec_WWW_Intrinsicvavgsw;
+def int_ppc_altivec_vavgub : PowerPC_Vec_BBB_Intrinsicvavgub;
+def int_ppc_altivec_vavguh : PowerPC_Vec_HHH_Intrinsicvavguh;
+def int_ppc_altivec_vavguw : PowerPC_Vec_WWW_Intrinsicvavguw;
+
 // Vector maximum.
 def int_ppc_altivec_vmaxfp : PowerPC_Vec_FFF_Intrinsicvmaxfp;
 def int_ppc_altivec_vmaxsb : PowerPC_Vec_BBB_Intrinsicvmaxsb;



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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCInstrAltivec.td updated: 1.33 - 1.34
---
Log message:

add average intrinsics


---
Diffs of the changes:  (+7 -0)

 PPCInstrAltivec.td |7 +++
 1 files changed, 7 insertions(+)


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.33 
llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.34
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.33 Tue Apr  4 12:25:31 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td  Tue Apr  4 18:14:00 2006
@@ -209,6 +209,13 @@
 def VEXPTEFP : VX2_Int394, vexptefp, int_ppc_altivec_vexptefp;
 def VLOGEFP  : VX2_Int458, vlogefp,  int_ppc_altivec_vlogefp;
 
+def VAVGSB : VX1_Int1282, vavgsb, int_ppc_altivec_vavgsb;
+def VAVGSH : VX1_Int1346, vavgsh, int_ppc_altivec_vavgsh;
+def VAVGSW : VX1_Int1410, vavgsw, int_ppc_altivec_vavgsw;
+def VAVGUB : VX1_Int1026, vavgub, int_ppc_altivec_vavgub;
+def VAVGUH : VX1_Int1090, vavguh, int_ppc_altivec_vavguh;
+def VAVGUW : VX1_Int1154, vavguw, int_ppc_altivec_vavguw;
+
 def VMAXFP : VX1_Int1034, vmaxfp, int_ppc_altivec_vmaxfp;
 def VMAXSB : VX1_Int 258, vmaxsb, int_ppc_altivec_vmaxsb;
 def VMAXSH : VX1_Int 322, vmaxsh, int_ppc_altivec_vmaxsh;



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[llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td

[Chris Lattner]

Changes in directory llvm/include/llvm:

IntrinsicsPowerPC.td updated: 1.15 - 1.16
---
Log message:

Add FP - Int Conversions


---
Diffs of the changes:  (+7 -1)

 IntrinsicsPowerPC.td |8 +++-
 1 files changed, 7 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.15 
llvm/include/llvm/IntrinsicsPowerPC.td:1.16
--- llvm/include/llvm/IntrinsicsPowerPC.td:1.15 Tue Apr  4 18:13:21 2006
+++ llvm/include/llvm/IntrinsicsPowerPC.td  Tue Apr  4 18:24:25 2006
@@ -350,13 +350,19 @@
 Intrinsic[llvm_v4i32_ty, llvm_v8i16_ty], [InstrNoMem];
 
 
-  // FP to integer conversion.
+  // FP - integer conversion.
   def int_ppc_altivec_vcfsx : GCCBuiltin__builtin_altivec_vcfsx,
   Intrinsic[llvm_v4f32_ty, llvm_v4i32_ty, llvm_int_ty],
 [InstrNoMem];
   def int_ppc_altivec_vcfux : GCCBuiltin__builtin_altivec_vcfux,
   Intrinsic[llvm_v4f32_ty, llvm_v4i32_ty, llvm_int_ty],
 [InstrNoMem];
+  def int_ppc_altivec_vctsxs : GCCBuiltin__builtin_altivec_vctsxs,
+  Intrinsic[llvm_v4i32_ty, llvm_v4f32_ty, llvm_int_ty],
+[InstrNoMem];
+  def int_ppc_altivec_vctuxs : GCCBuiltin__builtin_altivec_vctuxs,
+  Intrinsic[llvm_v4i32_ty, llvm_v4f32_ty, llvm_int_ty],
+[InstrNoMem];
 
   def int_ppc_altivec_vrfim : GCCBuiltin__builtin_altivec_vrfim,
   Intrinsic[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem];



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[llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td

[Chris Lattner]

Changes in directory llvm/include/llvm:

IntrinsicsPowerPC.td updated: 1.16 - 1.17
---
Log message:

Add missing byte merges.


---
Diffs of the changes:  (+6 -0)

 IntrinsicsPowerPC.td |6 ++
 1 files changed, 6 insertions(+)


Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.16 
llvm/include/llvm/IntrinsicsPowerPC.td:1.17
--- llvm/include/llvm/IntrinsicsPowerPC.td:1.16 Tue Apr  4 18:24:25 2006
+++ llvm/include/llvm/IntrinsicsPowerPC.td  Tue Apr  4 18:43:44 2006
@@ -374,12 +374,18 @@
   Intrinsic[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem];
 
   // Merges
+  def int_ppc_altivec_vmrghb : GCCBuiltin__builtin_altivec_vmrghb,
+  Intrinsic[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
+[InstrNoMem];
   def int_ppc_altivec_vmrghh : GCCBuiltin__builtin_altivec_vmrghh,
   Intrinsic[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
 [InstrNoMem];
   def int_ppc_altivec_vmrghw : GCCBuiltin__builtin_altivec_vmrghw,
   Intrinsic[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
 [InstrNoMem];
+  def int_ppc_altivec_vmrglb : GCCBuiltin__builtin_altivec_vmrglb,
+  Intrinsic[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
+[InstrNoMem];
   def int_ppc_altivec_vmrglh : GCCBuiltin__builtin_altivec_vmrglh,
   Intrinsic[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
 [InstrNoMem];



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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCInstrAltivec.td updated: 1.35 - 1.36
---
Log message:

Add missing byte merges.


---
Diffs of the changes:  (+2 -0)

 PPCInstrAltivec.td |2 ++
 1 files changed, 2 insertions(+)


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.35 
llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.36
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.35 Tue Apr  4 18:25:02 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td  Tue Apr  4 18:43:56 2006
@@ -233,8 +233,10 @@
 def VMINUH : VX1_Int 578, vminuh, int_ppc_altivec_vminuh;
 def VMINUW : VX1_Int 642, vminuw, int_ppc_altivec_vminuw;
 
+def VMRGHB : VX1_Int12 , vmrghb, int_ppc_altivec_vmrghb;
 def VMRGHH : VX1_Int76 , vmrghh, int_ppc_altivec_vmrghh;
 def VMRGHW : VX1_Int140, vmrghw, int_ppc_altivec_vmrghw;
+def VMRGLB : VX1_Int268, vmrglb, int_ppc_altivec_vmrglb;
 def VMRGLH : VX1_Int332, vmrglh, int_ppc_altivec_vmrglh;
 def VMRGLW : VX1_Int396, vmrglw, int_ppc_altivec_vmrglw;
 



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[llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

README_ALTIVEC.txt updated: 1.12 - 1.13
---
Log message:

add a note


---
Diffs of the changes:  (+4 -2)

 README_ALTIVEC.txt |6 --
 1 files changed, 4 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.12 
llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.13
--- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.12 Tue Apr  4 17:43:55 2006
+++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt  Tue Apr  4 18:45:11 2006
@@ -51,9 +51,7 @@
 
 ds*
 mf*
-vavg*
 vmladduhm
-vmr*
 vsel (some aliases only accessible using builtins)
 
 
//===--===//
@@ -154,3 +152,7 @@
 }
 
 
//===--===//
+
+Lower merges in the front-end to shuffles, reconstruct in the backend.
+
+//===--===//



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[llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td

[Chris Lattner]

Changes in directory llvm/include/llvm:

IntrinsicsPowerPC.td updated: 1.17 - 1.18
---
Log message:

Add m[tf]vscr intrinsics.


---
Diffs of the changes:  (+7 -0)

 IntrinsicsPowerPC.td |7 +++
 1 files changed, 7 insertions(+)


Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.17 
llvm/include/llvm/IntrinsicsPowerPC.td:1.18
--- llvm/include/llvm/IntrinsicsPowerPC.td:1.17 Tue Apr  4 18:43:44 2006
+++ llvm/include/llvm/IntrinsicsPowerPC.td  Tue Apr  4 19:03:03 2006
@@ -66,6 +66,13 @@
 // PowerPC Altivec Intrinsic Definitions.
 
 let TargetPrefix = ppc in {  // All intrinsics start with llvm.ppc..
+  // VSCR access.
+  def int_ppc_altivec_mfvscr : GCCBuiltin__builtin_altivec_mfvscr,
+  Intrinsic[llvm_v8i16_ty], [IntrReadMem];
+  def int_ppc_altivec_mtvscr : GCCBuiltin__builtin_altivec_mtvscr,
+  Intrinsic[llvm_void_ty, llvm_v4i32_ty], [IntrWriteMem];
+
+
   // Loads.  These don't map directly to GCC builtins because they represent 
the
   // source address with a single pointer.
   def int_ppc_altivec_lvx :



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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td PPCInstrFormats.td

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCInstrAltivec.td updated: 1.36 - 1.37
PPCInstrFormats.td updated: 1.71 - 1.72
---
Log message:

Add m[tf]vscr instructions.


---
Diffs of the changes:  (+34 -0)

 PPCInstrAltivec.td |7 +++
 PPCInstrFormats.td |   27 +++
 2 files changed, 34 insertions(+)


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.36 
llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.37
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.36 Tue Apr  4 18:43:56 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td  Tue Apr  4 19:03:57 2006
@@ -93,6 +93,13 @@
 def IMPLICIT_DEF_VRRC : Pseudo(ops VRRC:$rD), ; $rD = IMPLICIT_DEF_VRRC,
[(set VRRC:$rD, (v4f32 (undef)))];
 
+def MFVSCR : VXForm_41540, (ops VRRC:$vD),
+  mfvcr $vD, LdStGeneral,
+  [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]; 
+def MTVSCR : VXForm_51604, (ops VRRC:$vB),
+  mtvcr $vB, LdStGeneral,
+  [(int_ppc_altivec_mtvscr VRRC:$vB)]; 
+
 let isLoad = 1, PPC970_Unit = 2 in {  // Loads.
 def LVEBX: XForm_131,   7, (ops VRRC:$vD, memrr:$src),
lvebx $vD, $src, LdStGeneral,


Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.71 
llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.72
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.71 Sun Mar 26 21:34:17 2006
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td  Tue Apr  4 19:03:57 2006
@@ -697,6 +697,33 @@
   let Inst{21-31} = xo;
 }
 
+/// VXForm_4 - VX instructions with VD,0,0 register fields, like mfvscr.
+class VXForm_4bits11 xo, dag OL, string asmstr,
+   InstrItinClass itin, listdag pattern
+: I4, OL, asmstr, itin {
+  bits5 VD;
+  
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = VD;
+  let Inst{11-15} = 0;
+  let Inst{16-20} = 0;
+  let Inst{21-31} = xo;
+}
+
+/// VXForm_5 - VX instructions with 0,0,VB register fields, like mtvscr.
+class VXForm_5bits11 xo, dag OL, string asmstr,
+   InstrItinClass itin, listdag pattern
+: I4, OL, asmstr, itin {
+  bits5 VB;
+  
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = 0;
+  let Inst{11-15} = 0;
+  let Inst{16-20} = VB;
+  let Inst{21-31} = xo;
+}
 
 // E-4 VXR-Form
 class VXRForm_1bits10 xo, dag OL, string asmstr,



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[llvm-commits] CVS: llvm/include/llvm/IntrinsicsPowerPC.td

[Chris Lattner]

Changes in directory llvm/include/llvm:

IntrinsicsPowerPC.td updated: 1.18 - 1.19
---
Log message:

correct the type of two intrinsics, add int_ppc_altivec_vmladduhm


---
Diffs of the changes:  (+7 -2)

 IntrinsicsPowerPC.td |9 +++--
 1 files changed, 7 insertions(+), 2 deletions(-)


Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.18 
llvm/include/llvm/IntrinsicsPowerPC.td:1.19
--- llvm/include/llvm/IntrinsicsPowerPC.td:1.18 Tue Apr  4 19:03:03 2006
+++ llvm/include/llvm/IntrinsicsPowerPC.td  Tue Apr  4 19:49:14 2006
@@ -317,6 +317,11 @@
 Intrinsic[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v4i32_ty],
   [InstrNoMem];
 
+  // Other multiplies.
+  def int_ppc_altivec_vmladduhm : GCCBuiltin__builtin_altivec_vmladduhm,
+Intrinsic[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, 
+   llvm_v8i16_ty], [InstrNoMem];
+
   // Packs.
   def int_ppc_altivec_vpkpx : GCCBuiltin__builtin_altivec_vpkpx,
 Intrinsic[llvm_v8i16_ty, llvm_v4i32_ty, llvm_v4i32_ty],
@@ -328,10 +333,10 @@
 Intrinsic[llvm_v16i8_ty, llvm_v8i16_ty, llvm_v8i16_ty],
   [InstrNoMem];
   def int_ppc_altivec_vpkswss : GCCBuiltin__builtin_altivec_vpkswss,
-Intrinsic[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty],
+Intrinsic[llvm_v16i8_ty, llvm_v4i32_ty, llvm_v4i32_ty],
   [InstrNoMem];
   def int_ppc_altivec_vpkswus : GCCBuiltin__builtin_altivec_vpkswus,
-Intrinsic[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty],
+Intrinsic[llvm_v16i8_ty, llvm_v4i32_ty, llvm_v4i32_ty],
   [InstrNoMem];
   // vpkuhum is lowered to a shuffle.
   def int_ppc_altivec_vpkuhus : GCCBuiltin__builtin_altivec_vpkuhus,



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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td README_ALTIVEC.txt

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCInstrAltivec.td updated: 1.37 - 1.38
README_ALTIVEC.txt updated: 1.13 - 1.14
---
Log message:

add vmladduhm


---
Diffs of the changes:  (+2 -2)

 PPCInstrAltivec.td |2 ++
 README_ALTIVEC.txt |2 --
 2 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.37 
llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.38
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.37 Tue Apr  4 19:03:57 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td  Tue Apr  4 19:49:48 2006
@@ -157,8 +157,10 @@
[(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
VRRC:$vB)))],
Requires[FPContractions];
+
 def VMHADDSHS  : VA1a_Int32, vmhaddshs,  int_ppc_altivec_vmhaddshs;
 def VMHRADDSHS : VA1a_Int33, vmhraddshs, int_ppc_altivec_vmhraddshs;
+def VMLADDUHM  : VA1a_Int34, vmladduhm,  int_ppc_altivec_vmladduhm;
 def VPERM  : VA1a_Int43, vperm,  int_ppc_altivec_vperm;
 def VSEL   : VA1a_Int42, vsel,   int_ppc_altivec_vsel;
 


Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.13 
llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.14
--- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.13 Tue Apr  4 18:45:11 2006
+++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt  Tue Apr  4 19:49:48 2006
@@ -50,8 +50,6 @@
 Missing intrinsics:
 
 ds*
-mf*
-vmladduhm
 vsel (some aliases only accessible using builtins)
 
 
//===--===//



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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCInstrAltivec.td updated: 1.38 - 1.39
---
Log message:

add vsl


---
Diffs of the changes:  (+2 -0)

 PPCInstrAltivec.td |2 ++
 1 files changed, 2 insertions(+)


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.38 
llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.39
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.38 Tue Apr  4 19:49:48 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td  Tue Apr  4 20:16:22 2006
@@ -312,6 +312,8 @@
 def VRLB   : VX1_Int   4, vrlb, int_ppc_altivec_vrlb;
 def VRLH   : VX1_Int  68, vrlh, int_ppc_altivec_vrlh;
 def VRLW   : VX1_Int 132, vrlw, int_ppc_altivec_vrlw;
+
+def VSL: VX1_Int 452, vsl , int_ppc_altivec_vsl ;
 def VSLO   : VX1_Int1036, vslo, int_ppc_altivec_vslo;
 def VSLB   : VX1_Int 260, vslb, int_ppc_altivec_vslb;
 def VSLH   : VX1_Int 324, vslh, int_ppc_altivec_vslh;



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[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/vec_shuffle.ll

[Evan Cheng]

Changes in directory llvm/test/Regression/CodeGen/X86:

vec_shuffle.ll updated: 1.4 - 1.5
---
Log message:

Add a new shuffle test case that requires pshuflw / pshufhw pair.


---
Diffs of the changes:  (+27 -2)

 vec_shuffle.ll |   29 +++--
 1 files changed, 27 insertions(+), 2 deletions(-)


Index: llvm/test/Regression/CodeGen/X86/vec_shuffle.ll
diff -u llvm/test/Regression/CodeGen/X86/vec_shuffle.ll:1.4 
llvm/test/Regression/CodeGen/X86/vec_shuffle.ll:1.5
--- llvm/test/Regression/CodeGen/X86/vec_shuffle.ll:1.4 Wed Mar 29 16:51:28 2006
+++ llvm/test/Regression/CodeGen/X86/vec_shuffle.ll Tue Apr  4 20:44:57 2006
@@ -1,6 +1,7 @@
 ; RUN: llvm-as  %s | llc -march=x86 -mattr=+sse2 | grep shufp | wc -l | grep 1
-; RUN: llvm-as  %s | llc -march=x86 -mattr=+sse2 | grep movhpd
-; RUN: llvm-as  %s | llc -march=x86 -mattr=+sse2 | grep pshufhw
+; RUN: llvm-as  %s | llc -march=x86 -mattr=+sse2 | grep movhpd | wc -l | grep 
1
+; RUN: llvm-as  %s | llc -march=x86 -mattr=+sse2 | grep pshufhw | wc -l | 
grep 2
+; RUN: llvm-as  %s | llc -march=x86 -mattr=+sse2 | grep pshuflw | wc -l | 
grep 1
 
 void %test_v4sf(4 x float* %P, float %X, float %Y) {
%tmp = insertelement 4 x float zeroinitializer, float %X, uint 0
@@ -41,3 +42,27 @@
store 2 x long %tmp15, 2 x long* %res
ret void
 }
+
+void %test_v8i16_2(2 x long* %res, 2 x long* %A) {
+   %tmp = load 2 x long* %A
+   %tmp = cast 2 x long %tmp to 8 x short
+   %tmp0 = extractelement 8 x short %tmp, uint 0
+   %tmp1 = extractelement 8 x short %tmp, uint 1
+   %tmp2 = extractelement 8 x short %tmp, uint 2
+   %tmp3 = extractelement 8 x short %tmp, uint 3
+   %tmp4 = extractelement 8 x short %tmp, uint 4
+   %tmp5 = extractelement 8 x short %tmp, uint 5
+   %tmp6 = extractelement 8 x short %tmp, uint 6
+   %tmp7 = extractelement 8 x short %tmp, uint 7
+   %tmp8 = insertelement 8 x short undef, short %tmp2, uint 0
+   %tmp9 = insertelement 8 x short %tmp8, short %tmp1, uint 1
+   %tmp10 = insertelement 8 x short %tmp9, short %tmp0, uint 2
+   %tmp11 = insertelement 8 x short %tmp10, short %tmp3, uint 3
+   %tmp12 = insertelement 8 x short %tmp11, short %tmp6, uint 4
+   %tmp13 = insertelement 8 x short %tmp12, short %tmp5, uint 5
+   %tmp14 = insertelement 8 x short %tmp13, short %tmp4, uint 6
+   %tmp15 = insertelement 8 x short %tmp14, short %tmp7, uint 7
+   %tmp15 = cast 8 x short %tmp15 to 2 x long
+   store 2 x long %tmp15, 2 x long* %res
+   ret void
+}



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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.153 - 1.154
---
Log message:

Handle v8i16 shuffle that must be broken into a pair of pshufhw / pshuflw.


---
Diffs of the changes:  (+55 -2)

 X86ISelLowering.cpp |   57 ++--
 1 files changed, 55 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.153 
llvm/lib/Target/X86/X86ISelLowering.cpp:1.154
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.153   Mon Apr  3 17:30:54 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Apr  4 20:47:37 2006
@@ -1417,7 +1417,7 @@
 }
 
 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
-/// specifies a shuffle of elements that is suitable for input to PSHUFD.
+/// specifies a shuffle of elements that is suitable for input to PSHUFHW.
 bool X86::isPSHUFHWMask(SDNode *N) {
   assert(N-getOpcode() == ISD::BUILD_VECTOR);
 
@@ -1447,7 +1447,7 @@
 }
 
 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
-/// specifies a shuffle of elements that is suitable for input to PSHUFD.
+/// specifies a shuffle of elements that is suitable for input to PSHUFLW.
 bool X86::isPSHUFLWMask(SDNode *N) {
   assert(N-getOpcode() == ISD::BUILD_VECTOR);
 
@@ -1781,6 +1781,38 @@
   return SDOperand();
 }
 
+/// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
+/// specifies a 8 element shuffle that can be broken into a pair of
+/// PSHUFHW and PSHUFLW.
+static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
+  assert(N-getOpcode() == ISD::BUILD_VECTOR);
+
+  if (N-getNumOperands() != 8)
+return false;
+
+  // Lower quadword shuffled.
+  for (unsigned i = 0; i != 4; ++i) {
+SDOperand Arg = N-getOperand(i);
+if (Arg.getOpcode() == ISD::UNDEF) continue;
+assert(isaConstantSDNode(Arg)  Invalid VECTOR_SHUFFLE mask!);
+unsigned Val = castConstantSDNode(Arg)-getValue();
+if (Val  4)
+  return false;
+  }
+
+  // Upper quadword shuffled.
+  for (unsigned i = 4; i != 8; ++i) {
+SDOperand Arg = N-getOperand(i);
+if (Arg.getOpcode() == ISD::UNDEF) continue;
+assert(isaConstantSDNode(Arg)  Invalid VECTOR_SHUFFLE mask!);
+unsigned Val = castConstantSDNode(Arg)-getValue();
+if (Val  4 || Val  7)
+  return false;
+  }
+
+  return true;
+}
+
 /// LowerOperation - Provide custom lowering hooks for some operations.
 ///
 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG DAG) {
@@ -2590,6 +2622,26 @@
 
   if (X86::isSHUFPMask(PermMask.Val))
 return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG);
+
+  // Handle v8i16 shuffle high / low shuffle node pair.
+  if (VT == MVT::v8i16  isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
+MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
+MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
+std::vectorSDOperand MaskVec;
+for (unsigned i = 0; i != 4; ++i)
+  MaskVec.push_back(PermMask.getOperand(i));
+for (unsigned i = 4; i != 8; ++i)
+  MaskVec.push_back(DAG.getConstant(i, BaseVT));
+SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
+V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
+MaskVec.clear();
+for (unsigned i = 0; i != 4; ++i)
+  MaskVec.push_back(DAG.getConstant(i, BaseVT));
+for (unsigned i = 4; i != 8; ++i)
+  MaskVec.push_back(PermMask.getOperand(i));
+Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
+return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
+  }
 } else {
   // Floating point cases in the other order.
   if (X86::isSHUFPMask(PermMask.Val))
@@ -2872,6 +2924,7 @@
   X86::isPSHUFDMask(Mask.Val) ||
   X86::isPSHUFHWMask(Mask.Val) ||
   X86::isPSHUFLWMask(Mask.Val) ||
+  isPSHUFHW_PSHUFLWMask(Mask.Val) ||
   X86::isSHUFPMask(Mask.Val) ||
   X86::isUNPCKLMask(Mask.Val) ||
   X86::isUNPCKHMask(Mask.Val));



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[llvm-commits] CVS: llvm/lib/Analysis/DataStructure/Local.cpp

[Andrew Lenharth]

Changes in directory llvm/lib/Analysis/DataStructure:

Local.cpp updated: 1.143 - 1.144
---
Log message:

revert this, this is safe, if conservative.  leave a note to that effect

---
Diffs of the changes:  (+7 -9)

 Local.cpp |   16 +++-
 1 files changed, 7 insertions(+), 9 deletions(-)


Index: llvm/lib/Analysis/DataStructure/Local.cpp
diff -u llvm/lib/Analysis/DataStructure/Local.cpp:1.143 
llvm/lib/Analysis/DataStructure/Local.cpp:1.144
--- llvm/lib/Analysis/DataStructure/Local.cpp:1.143 Wed Mar 15 13:03:16 2006
+++ llvm/lib/Analysis/DataStructure/Local.cpp   Tue Apr  4 21:42:36 2006
@@ -546,17 +546,15 @@
   case Intrinsic::vaend:
 return;  // noop
   case Intrinsic::memcpy_i32: 
-  case Intrinsic::memcpy_i64: {
-//write first location
-if (DSNode *N = getValueDest(**CS.arg_begin()).getNode())
-  N-setModifiedMarker();
-//and read second pointer
-if (DSNode *N = getValueDest(**(CS.arg_begin() + 1)).getNode())
-  N-setReadMarker();
-return;
-  }
+  case Intrinsic::memcpy_i64:
   case Intrinsic::memmove_i32:
   case Intrinsic::memmove_i64: {
+//This is over aggressive.  What these functions do is not make the 
+// targets pointers alias, but rather merge the out edges of the graphs
+// for the pointers according to the type merging of the graphs.
+//Simply merging the two graphs is a crude approximation to this.
+//I might be wrong though.
+
 // Merge the first  second arguments, and mark the memory read and
 // modified.
 DSNodeHandle RetNH = getValueDest(**CS.arg_begin());



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[llvm-commits] CVS: llvm/test/Regression/Analysis/DSGraph/2004-02-13-memcpy.ll

[Andrew Lenharth]

Changes in directory llvm/test/Regression/Analysis/DSGraph:

2004-02-13-memcpy.ll updated: 1.3 - 1.4
---
Log message:

make this test less exacting

---
Diffs of the changes:  (+1 -1)

 2004-02-13-memcpy.ll |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/test/Regression/Analysis/DSGraph/2004-02-13-memcpy.ll
diff -u llvm/test/Regression/Analysis/DSGraph/2004-02-13-memcpy.ll:1.3 
llvm/test/Regression/Analysis/DSGraph/2004-02-13-memcpy.ll:1.4
--- llvm/test/Regression/Analysis/DSGraph/2004-02-13-memcpy.ll:1.3  Wed Mar 
15 13:02:54 2006
+++ llvm/test/Regression/Analysis/DSGraph/2004-02-13-memcpy.ll  Tue Apr  4 
22:31:45 2006
@@ -1,5 +1,5 @@
 ; RUN: analyze %s -datastructure-gc -dsgc-check-flags=Xn:SMR
-; RUN: analyze %s -datastructure-gc -dsgc-check-flags=X:SM
+; RUN: analyze %s -datastructure-gc -dsgc-check-flags=X:SMR
 
 declare void %llvm.memcpy.i32(sbyte*, sbyte*, uint, uint)
 declare void %llvm.memmove.i32(sbyte*, sbyte*, uint, uint)



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[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/vec_shuffle.ll

[Evan Cheng]

Changes in directory llvm/test/Regression/CodeGen/X86:

vec_shuffle.ll updated: 1.5 - 1.6
---
Log message:

Separate out to 2 test cases

---
Diffs of the changes:  (+1 -26)

 vec_shuffle.ll |   27 +--
 1 files changed, 1 insertion(+), 26 deletions(-)


Index: llvm/test/Regression/CodeGen/X86/vec_shuffle.ll
diff -u llvm/test/Regression/CodeGen/X86/vec_shuffle.ll:1.5 
llvm/test/Regression/CodeGen/X86/vec_shuffle.ll:1.6
--- llvm/test/Regression/CodeGen/X86/vec_shuffle.ll:1.5 Tue Apr  4 20:44:57 2006
+++ llvm/test/Regression/CodeGen/X86/vec_shuffle.ll Tue Apr  4 23:40:55 2006
@@ -1,7 +1,6 @@
 ; RUN: llvm-as  %s | llc -march=x86 -mattr=+sse2 | grep shufp | wc -l | grep 1
 ; RUN: llvm-as  %s | llc -march=x86 -mattr=+sse2 | grep movhpd | wc -l | grep 
1
-; RUN: llvm-as  %s | llc -march=x86 -mattr=+sse2 | grep pshufhw | wc -l | 
grep 2
-; RUN: llvm-as  %s | llc -march=x86 -mattr=+sse2 | grep pshuflw | wc -l | 
grep 1
+; RUN: llvm-as  %s | llc -march=x86 -mattr=+sse2 | grep pshufhw | wc -l | 
grep 1
 
 void %test_v4sf(4 x float* %P, float %X, float %Y) {
%tmp = insertelement 4 x float zeroinitializer, float %X, uint 0
@@ -42,27 +41,3 @@
store 2 x long %tmp15, 2 x long* %res
ret void
 }
-
-void %test_v8i16_2(2 x long* %res, 2 x long* %A) {
-   %tmp = load 2 x long* %A
-   %tmp = cast 2 x long %tmp to 8 x short
-   %tmp0 = extractelement 8 x short %tmp, uint 0
-   %tmp1 = extractelement 8 x short %tmp, uint 1
-   %tmp2 = extractelement 8 x short %tmp, uint 2
-   %tmp3 = extractelement 8 x short %tmp, uint 3
-   %tmp4 = extractelement 8 x short %tmp, uint 4
-   %tmp5 = extractelement 8 x short %tmp, uint 5
-   %tmp6 = extractelement 8 x short %tmp, uint 6
-   %tmp7 = extractelement 8 x short %tmp, uint 7
-   %tmp8 = insertelement 8 x short undef, short %tmp2, uint 0
-   %tmp9 = insertelement 8 x short %tmp8, short %tmp1, uint 1
-   %tmp10 = insertelement 8 x short %tmp9, short %tmp0, uint 2
-   %tmp11 = insertelement 8 x short %tmp10, short %tmp3, uint 3
-   %tmp12 = insertelement 8 x short %tmp11, short %tmp6, uint 4
-   %tmp13 = insertelement 8 x short %tmp12, short %tmp5, uint 5
-   %tmp14 = insertelement 8 x short %tmp13, short %tmp4, uint 6
-   %tmp15 = insertelement 8 x short %tmp14, short %tmp7, uint 7
-   %tmp15 = cast 8 x short %tmp15 to 2 x long
-   store 2 x long %tmp15, 2 x long* %res
-   ret void
-}



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[llvm-commits] CVS: llvm/win32/x86/x86.vcproj

[Jeff Cohen]

Changes in directory llvm/win32/x86:

x86.vcproj updated: 1.23 - 1.24
---
Log message:

Fix more tablegen depedency issues in Visual Studio.

---
Diffs of the changes:  (+2 -2)

 x86.vcproj |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/win32/x86/x86.vcproj
diff -u llvm/win32/x86/x86.vcproj:1.23 llvm/win32/x86/x86.vcproj:1.24
--- llvm/win32/x86/x86.vcproj:1.23  Sat Apr  1 23:20:53 2006
+++ llvm/win32/x86/x86.vcproj   Wed Apr  5 00:19:18 2006
@@ -126,7 +126,7 @@
 ..\$(IntDir)\TableGen.exe -gen-dag-isel -I ..\..\lib\Target\X86 -I 
..\..\include $(InputPath) -o X86GenDAGISel.inc
 ..\$(IntDir)\TableGen.exe -gen-subtarget -I ..\..\lib\Target\X86 -I 
..\..\include $(InputPath) -o X86GenSubtarget.inc
 
-   
AdditionalDependencies=$(InputDir)X86InstrInfo.td;$(InputDir)X86RegisterInfo.td;$(InputDir)..\Target.td;$(ProjectDir)..\$(IntDir)\TableGen.exe
+   
AdditionalDependencies=$(InputDir)X86InstrInfo.td;$(InputDir)X86RegisterInfo.td;$(InputDir)X86InstrFPStack.td;$(InputDir)X86InstrMMX.td;$(InputDir)X86InstrSSE.td;$(InputDir)..\Target.td;$(InputDir)..\TargetSchedule.td;$(InputDir)..\TargetScheduleDAG.td;$(ProjectDir)..\$(IntDir)\TableGen.exe

Outputs=X86GenRegisterNames.inc;X86GenRegisterInfo.h.inc;X86GenRegisterInfo.inc;X86GenInstrNames.inc;X86GenInstrInfo.inc;X86GenAsmWriter.inc;X86GenAsmWriter1.inc;X86GenDAGISel.inc;X86GenSubtarget.inc/
/FileConfiguration
FileConfiguration
@@ -144,7 +144,7 @@
 ..\$(IntDir)\TableGen.exe -gen-dag-isel -I ..\..\lib\Target\X86 -I 
..\..\include $(InputPath) -o X86GenDAGISel.inc
 ..\$(IntDir)\TableGen.exe -gen-subtarget -I ..\..\lib\Target\X86 -I 
..\..\include $(InputPath) -o X86GenSubtarget.inc
 
-   
AdditionalDependencies=$(InputDir)X86InstrInfo.td;$(InputDir)X86RegisterInfo.td;$(InputDir)..\Target.td;$(ProjectDir)..\$(IntDir)\TableGen.exe
+   
AdditionalDependencies=$(InputDir)X86InstrInfo.td;$(InputDir)X86RegisterInfo.td;$(InputDir)X86InstrFPStack.td;$(InputDir)X86InstrMMX.td;$(InputDir)X86InstrSSE.td;$(InputDir)..\Target.td;$(InputDir)..\TargetSchedule.td;$(InputDir)..\TargetScheduleDAG.td;$(ProjectDir)..\$(IntDir)\TableGen.exe

Outputs=X86GenRegisterNames.inc;X86GenRegisterInfo.h.inc;X86GenRegisterInfo.inc;X86GenInstrNames.inc;X86GenInstrInfo.inc;X86GenAsmWriter.inc;X86GenAsmWriter1.inc;X86GenDAGISel.inc;X86GenSubtarget.inc/
/FileConfiguration
/File



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