[llvm-commits] CVS: llvm/lib/CodeGen/VirtRegMap.cpp

2006-05-01 Thread Evan Cheng 


Changes in directory llvm/lib/CodeGen:

VirtRegMap.cpp updated: 1.61 - 1.62
---
Log message:

Remove temp. option -spiller-check-liveout, it didn't cause any failure nor 
performance regressions.

---
Diffs of the changes:  (+1 -5)

 VirtRegMap.cpp |6 +-
 1 files changed, 1 insertion(+), 5 deletions(-)


Index: llvm/lib/CodeGen/VirtRegMap.cpp
diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.61 
llvm/lib/CodeGen/VirtRegMap.cpp:1.62
--- llvm/lib/CodeGen/VirtRegMap.cpp:1.61Sun Apr 30 03:41:47 2006
+++ llvm/lib/CodeGen/VirtRegMap.cpp Mon May  1 03:54:57 2006
@@ -50,10 +50,6 @@
 clEnumVal(local,local spiller),
 clEnumValEnd),
  cl::init(local));
-
-  // TEMPORARY option to test a fix.
-  cl::optbool
-  SpillerCheckLiveOut(spiller-check-liveout, cl::Hidden);
 }
 
 
//===--===//
@@ -735,7 +731,7 @@
   // If we get here, the store is dead, nuke it now.
   assert(!(MR  VirtRegMap::isRef)  Can't be modref!);
   // Don't nuke it if the value is needed in another block.
-  if (!SpillerCheckLiveOut || !(MR  VirtRegMap::isLiveOut)) {
+  if (!(MR  VirtRegMap::isLiveOut)) {
 DEBUG(std::cerr   Killed store:\t  *MDSI-second);
 MBB.erase(MDSI-second);
 MaybeDeadStores.erase(MDSI);



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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp

2006-05-01 Thread Evan Cheng 


Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAGList.cpp updated: 1.48 - 1.49
---
Log message:

Remove temp. option -spiller-check-liveout, it didn't cause any failure nor 
performance regressions.

---
Diffs of the changes:  (+33 -17)

 ScheduleDAGList.cpp |   50 +-
 1 files changed, 33 insertions(+), 17 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.48 
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.49
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.48  Sun Mar 12 
03:01:41 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp   Mon May  1 03:54:57 2006
@@ -51,6 +51,7 @@
 short NumSuccsLeft; // # of succs not scheduled.
 short NumChainPredsLeft;// # of chain preds not scheduled.
 short NumChainSuccsLeft;// # of chain succs not scheduled.
+bool isStore  : 1;  // Is a store.
 bool isTwoAddress : 1;  // Is a two-address instruction.
 bool isDefNUseOperand : 1;  // Is a defuse operand.
 bool isPending: 1;  // True once pending.
@@ -63,7 +64,7 @@
 
 SUnit(SDNode *node, unsigned nodenum)
   : Node(node), NumPredsLeft(0), NumSuccsLeft(0),
-  NumChainPredsLeft(0), NumChainSuccsLeft(0),
+  NumChainPredsLeft(0), NumChainSuccsLeft(0), isStore(false),
   isTwoAddress(false), isDefNUseOperand(false),
   isPending(false), isAvailable(false), isScheduled(false), 
   Latency(0), CycleBound(0), Cycle(0), NodeNum(nodenum) {}
@@ -315,9 +316,13 @@
 SUnit *SU = SUnits[su];
 SDNode *MainNode = SU-Node;
 
-if (MainNode-isTargetOpcode() 
-TII-isTwoAddrInstr(MainNode-getTargetOpcode()))
-  SU-isTwoAddress = true;
+if (MainNode-isTargetOpcode()) {
+  unsigned Opc = MainNode-getTargetOpcode();
+  if (TII-isTwoAddrInstr(Opc))
+SU-isTwoAddress = true;
+  if (TII-isStore(Opc))
+SU-isStore = true;
+}
 
 // Find all predecessors and successors of the group.
 // Temporarily add N to make code simpler.
@@ -358,9 +363,9 @@
 SU-FlaggedNodes.pop_back();
   }
   
-  return;
   DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
 SUnits[su].dumpAll(DAG));
+  return;
 }
 
 /// EmitSchedule - Emit the machine code in scheduled order.
@@ -735,7 +740,7 @@
 const std::vectorSUnit *SUnits;
 
 // SethiUllmanNumbers - The SethiUllman number for each node.
-std::vectorint SethiUllmanNumbers;
+std::vectorunsigned SethiUllmanNumbers;
 
 std::priority_queueSUnit*, std::vectorSUnit*, ls_rr_sort Queue;
   public:
@@ -774,7 +779,7 @@
 }
   private:
 void CalculatePriorities();
-int CalcNodePriority(const SUnit *SU);
+unsigned CalcNodePriority(const SUnit *SU);
   };
 }
 
@@ -784,7 +789,7 @@
   
   int LBonus = (int)left -isDefNUseOperand;
   int RBonus = (int)right-isDefNUseOperand;
-  
+
   // Special tie breaker: if two nodes share a operand, the one that
   // use it as a defuse operand is preferred.
   if (left-isTwoAddress  !right-isTwoAddress) {
@@ -798,6 +803,20 @@
   RBonus++;
   }
   
+  // Push stores up as much as possible. This really help code like this:
+  //   load
+  //   compute
+  //   store
+  //   load
+  //   compute
+  //   store
+  // This would make sure the scheduled code completed all computations and
+  // the stores before the next series of computation starts.
+  if (!left-isStore  right-isStore)
+LBonus += 2;
+  if (left-isStore  !right-isStore)
+RBonus += 2;
+
   // Priority1 is just the number of live range genned.
   int LPriority1 = left -NumPredsLeft - LBonus;
   int RPriority1 = right-NumPredsLeft - RBonus;
@@ -819,9 +838,9 @@
 
 /// CalcNodePriority - Priority is the Sethi Ullman number. 
 /// Smaller number is the higher priority.
-int RegReductionPriorityQueue::CalcNodePriority(const SUnit *SU) {
-  int SethiUllmanNumber = SethiUllmanNumbers[SU-NodeNum];
-  if (SethiUllmanNumber != INT_MIN)
+unsigned RegReductionPriorityQueue::CalcNodePriority(const SUnit *SU) {
+  unsigned SethiUllmanNumber = SethiUllmanNumbers[SU-NodeNum];
+  if (SethiUllmanNumber != 0)
 return SethiUllmanNumber;
   
   if (SU-Preds.size() == 0) {
@@ -832,7 +851,7 @@
  I = SU-Preds.begin(), E = SU-Preds.end(); I != E; ++I) {
   if (I-second) continue;  // ignore chain preds.
   SUnit *PredSU = I-first;
-  int PredSethiUllman = CalcNodePriority(PredSU);
+  unsigned PredSethiUllman = CalcNodePriority(PredSU);
   if (PredSethiUllman  SethiUllmanNumber) {
 SethiUllmanNumber = PredSethiUllman;
 Extra = 0;
@@ -840,10 +859,7 @@
 Extra++;
 }
 
-if (SU-Node-getOpcode() != ISD::TokenFactor)
-  SethiUllmanNumber += Extra;
-else
-  SethiUllmanNumber = (Extra == 1) ? 0 : Extra-1;
+SethiUllmanNumber += Extra;

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp

2006-05-01 Thread Evan Cheng 


Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAGList.cpp updated: 1.49 - 1.50
---
Log message:

Didn't mean ScheduleDAGList.cpp to make the last checkin.

---
Diffs of the changes:  (+17 -33)

 ScheduleDAGList.cpp |   50 +-
 1 files changed, 17 insertions(+), 33 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.49 
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.50
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.49  Mon May  1 
03:54:57 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp   Mon May  1 03:56:34 2006
@@ -51,7 +51,6 @@
 short NumSuccsLeft; // # of succs not scheduled.
 short NumChainPredsLeft;// # of chain preds not scheduled.
 short NumChainSuccsLeft;// # of chain succs not scheduled.
-bool isStore  : 1;  // Is a store.
 bool isTwoAddress : 1;  // Is a two-address instruction.
 bool isDefNUseOperand : 1;  // Is a defuse operand.
 bool isPending: 1;  // True once pending.
@@ -64,7 +63,7 @@
 
 SUnit(SDNode *node, unsigned nodenum)
   : Node(node), NumPredsLeft(0), NumSuccsLeft(0),
-  NumChainPredsLeft(0), NumChainSuccsLeft(0), isStore(false),
+  NumChainPredsLeft(0), NumChainSuccsLeft(0),
   isTwoAddress(false), isDefNUseOperand(false),
   isPending(false), isAvailable(false), isScheduled(false), 
   Latency(0), CycleBound(0), Cycle(0), NodeNum(nodenum) {}
@@ -316,13 +315,9 @@
 SUnit *SU = SUnits[su];
 SDNode *MainNode = SU-Node;
 
-if (MainNode-isTargetOpcode()) {
-  unsigned Opc = MainNode-getTargetOpcode();
-  if (TII-isTwoAddrInstr(Opc))
-SU-isTwoAddress = true;
-  if (TII-isStore(Opc))
-SU-isStore = true;
-}
+if (MainNode-isTargetOpcode() 
+TII-isTwoAddrInstr(MainNode-getTargetOpcode()))
+  SU-isTwoAddress = true;
 
 // Find all predecessors and successors of the group.
 // Temporarily add N to make code simpler.
@@ -363,9 +358,9 @@
 SU-FlaggedNodes.pop_back();
   }
   
+  return;
   DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
 SUnits[su].dumpAll(DAG));
-  return;
 }
 
 /// EmitSchedule - Emit the machine code in scheduled order.
@@ -740,7 +735,7 @@
 const std::vectorSUnit *SUnits;
 
 // SethiUllmanNumbers - The SethiUllman number for each node.
-std::vectorunsigned SethiUllmanNumbers;
+std::vectorint SethiUllmanNumbers;
 
 std::priority_queueSUnit*, std::vectorSUnit*, ls_rr_sort Queue;
   public:
@@ -779,7 +774,7 @@
 }
   private:
 void CalculatePriorities();
-unsigned CalcNodePriority(const SUnit *SU);
+int CalcNodePriority(const SUnit *SU);
   };
 }
 
@@ -789,7 +784,7 @@
   
   int LBonus = (int)left -isDefNUseOperand;
   int RBonus = (int)right-isDefNUseOperand;
-
+  
   // Special tie breaker: if two nodes share a operand, the one that
   // use it as a defuse operand is preferred.
   if (left-isTwoAddress  !right-isTwoAddress) {
@@ -803,20 +798,6 @@
   RBonus++;
   }
   
-  // Push stores up as much as possible. This really help code like this:
-  //   load
-  //   compute
-  //   store
-  //   load
-  //   compute
-  //   store
-  // This would make sure the scheduled code completed all computations and
-  // the stores before the next series of computation starts.
-  if (!left-isStore  right-isStore)
-LBonus += 2;
-  if (left-isStore  !right-isStore)
-RBonus += 2;
-
   // Priority1 is just the number of live range genned.
   int LPriority1 = left -NumPredsLeft - LBonus;
   int RPriority1 = right-NumPredsLeft - RBonus;
@@ -838,9 +819,9 @@
 
 /// CalcNodePriority - Priority is the Sethi Ullman number. 
 /// Smaller number is the higher priority.
-unsigned RegReductionPriorityQueue::CalcNodePriority(const SUnit *SU) {
-  unsigned SethiUllmanNumber = SethiUllmanNumbers[SU-NodeNum];
-  if (SethiUllmanNumber != 0)
+int RegReductionPriorityQueue::CalcNodePriority(const SUnit *SU) {
+  int SethiUllmanNumber = SethiUllmanNumbers[SU-NodeNum];
+  if (SethiUllmanNumber != INT_MIN)
 return SethiUllmanNumber;
   
   if (SU-Preds.size() == 0) {
@@ -851,7 +832,7 @@
  I = SU-Preds.begin(), E = SU-Preds.end(); I != E; ++I) {
   if (I-second) continue;  // ignore chain preds.
   SUnit *PredSU = I-first;
-  unsigned PredSethiUllman = CalcNodePriority(PredSU);
+  int PredSethiUllman = CalcNodePriority(PredSU);
   if (PredSethiUllman  SethiUllmanNumber) {
 SethiUllmanNumber = PredSethiUllman;
 Extra = 0;
@@ -859,7 +840,10 @@
 Extra++;
 }
 
-SethiUllmanNumber += Extra;
+if (SU-Node-getOpcode() != ISD::TokenFactor)
+  SethiUllmanNumber += Extra;
+else
+  SethiUllmanNumber = (Extra == 1) ? 0 : Extra-1;
   }
   
   return SethiUllmanNumber;
@@

[llvm-commits] CVS: llvm-test/Makefile.programs

2006-05-01 Thread Evan Cheng 


Changes in directory llvm-test:

Makefile.programs updated: 1.206 - 1.207
---
Log message:

Revert x86 llcbeta to -enable-x86-fastcc

---
Diffs of the changes:  (+1 -1)

 Makefile.programs |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm-test/Makefile.programs
diff -u llvm-test/Makefile.programs:1.206 llvm-test/Makefile.programs:1.207
--- llvm-test/Makefile.programs:1.206   Sun Apr 30 03:42:35 2006
+++ llvm-test/Makefile.programs Mon May  1 03:57:18 2006
@@ -197,7 +197,7 @@
 LLCBETAOPTION := -sched=simple 
 endif
 ifeq ($(ARCH),x86)
-LLCBETAOPTION := -spiller-check-liveout
+LLCBETAOPTION := -enable-x86-fastcc
 endif
 ifeq ($(ARCH),Sparc)
 LLCBETAOPTION := -enable-sparc-v9-insts



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[llvm-commits] CVS: llvm/utils/TableGen/InstrInfoEmitter.cpp

2006-05-01 Thread Evan Cheng 


Changes in directory llvm/utils/TableGen:

InstrInfoEmitter.cpp updated: 1.36 - 1.37
---
Log message:

Mark instructions whose pattern is (store ...) isStore.

---
Diffs of the changes:  (+17 -1)

 InstrInfoEmitter.cpp |   18 +-
 1 files changed, 17 insertions(+), 1 deletion(-)


Index: llvm/utils/TableGen/InstrInfoEmitter.cpp
diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.36 
llvm/utils/TableGen/InstrInfoEmitter.cpp:1.37
--- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.36   Thu Apr 20 13:32:22 2006
+++ llvm/utils/TableGen/InstrInfoEmitter.cppMon May  1 04:04:20 2006
@@ -184,6 +184,22 @@
   OS  \,\t  NumOperands  ,   ItinClass
   , 0;
 
+  // Try to determine (from the pattern), if the instruction is a store.
+  bool isStore = false;
+  if (dynamic_castListInit*(Inst.TheDef-getValueInit(Pattern))) {
+ListInit *LI = Inst.TheDef-getValueAsListInit(Pattern);
+if (LI  LI-getSize()  0) {
+  DagInit *Dag = (DagInit *)LI-getElement(0);
+  DefInit *OpDef = dynamic_castDefInit*(Dag-getOperator());
+  if (OpDef) {
+Record *Operator = OpDef-getDef();
+if (Operator-isSubClassOf(SDNode) 
+Operator-getValueAsString(Opcode) == ISD::STORE)
+isStore = true;
+  }
+}
+  }
+
   // Emit all of the target indepedent flags...
   if (Inst.isReturn) OS  |M_RET_FLAG;
   if (Inst.isBranch) OS  |M_BRANCH_FLAG;
@@ -191,7 +207,7 @@
   if (Inst.hasDelaySlot) OS  |M_DELAY_SLOT_FLAG;
   if (Inst.isCall)   OS  |M_CALL_FLAG;
   if (Inst.isLoad)   OS  |M_LOAD_FLAG;
-  if (Inst.isStore)  OS  |M_STORE_FLAG;
+  if (Inst.isStore || isStore) OS  |M_STORE_FLAG;
   if (Inst.isTwoAddress) OS  |M_2_ADDR_FLAG;
   if (Inst.isConvertibleToThreeAddress) OS  |M_CONVERTIBLE_TO_3_ADDR;
   if (Inst.isCommutable) OS  |M_COMMUTABLE;



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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp

2006-05-01 Thread Evan Cheng 


Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAGList.cpp updated: 1.50 - 1.51
---
Log message:

Bottom up register-pressure reduction scheduler now pushes store operations
up the schedule. This helps code that looks like this:

loads ...
computations (first set) ...
stores (first set) ...
loads
computations (seccond set) ...
stores (seccond set) ...

Without this change, the stores and computations are more likely to
interleave:

loads ...
loads ...
computations (first set) ...
computations (second set) ...
computations (first set) ...
stores (first set) ...
computations (second set) ...
stores (stores set) ...

This can increase the number of spills if we are unlucky.


---
Diffs of the changes:  (+41 -17)

 ScheduleDAGList.cpp |   58 
 1 files changed, 41 insertions(+), 17 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.50 
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.51
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.50  Mon May  1 
03:56:34 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp   Mon May  1 04:14:40 2006
@@ -33,6 +33,13 @@
 using namespace llvm;
 
 namespace {
+  // TEMPORARY option to test a fix.
+  cl::optbool
+  SchedIgnorStore(sched-ignore-store, cl::Hidden);
+
+}
+
+namespace {
   Statistic NumNoops (scheduler, Number of noops inserted);
   Statistic NumStalls(scheduler, Number of pipeline stalls);
 
@@ -51,6 +58,7 @@
 short NumSuccsLeft; // # of succs not scheduled.
 short NumChainPredsLeft;// # of chain preds not scheduled.
 short NumChainSuccsLeft;// # of chain succs not scheduled.
+bool isStore  : 1;  // Is a store.
 bool isTwoAddress : 1;  // Is a two-address instruction.
 bool isDefNUseOperand : 1;  // Is a defuse operand.
 bool isPending: 1;  // True once pending.
@@ -63,7 +71,7 @@
 
 SUnit(SDNode *node, unsigned nodenum)
   : Node(node), NumPredsLeft(0), NumSuccsLeft(0),
-  NumChainPredsLeft(0), NumChainSuccsLeft(0),
+  NumChainPredsLeft(0), NumChainSuccsLeft(0), isStore(false),
   isTwoAddress(false), isDefNUseOperand(false),
   isPending(false), isAvailable(false), isScheduled(false), 
   Latency(0), CycleBound(0), Cycle(0), NodeNum(nodenum) {}
@@ -315,9 +323,14 @@
 SUnit *SU = SUnits[su];
 SDNode *MainNode = SU-Node;
 
-if (MainNode-isTargetOpcode() 
-TII-isTwoAddrInstr(MainNode-getTargetOpcode()))
-  SU-isTwoAddress = true;
+if (MainNode-isTargetOpcode()) {
+  unsigned Opc = MainNode-getTargetOpcode();
+  if (TII-isTwoAddrInstr(Opc))
+SU-isTwoAddress = true;
+  if (TII-isStore(Opc))
+if (!SchedIgnorStore)
+  SU-isStore = true;
+}
 
 // Find all predecessors and successors of the group.
 // Temporarily add N to make code simpler.
@@ -358,9 +371,9 @@
 SU-FlaggedNodes.pop_back();
   }
   
-  return;
   DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
 SUnits[su].dumpAll(DAG));
+  return;
 }
 
 /// EmitSchedule - Emit the machine code in scheduled order.
@@ -735,7 +748,7 @@
 const std::vectorSUnit *SUnits;
 
 // SethiUllmanNumbers - The SethiUllman number for each node.
-std::vectorint SethiUllmanNumbers;
+std::vectorunsigned SethiUllmanNumbers;
 
 std::priority_queueSUnit*, std::vectorSUnit*, ls_rr_sort Queue;
   public:
@@ -774,7 +787,7 @@
 }
   private:
 void CalculatePriorities();
-int CalcNodePriority(const SUnit *SU);
+unsigned CalcNodePriority(const SUnit *SU);
   };
 }
 
@@ -784,7 +797,7 @@
   
   int LBonus = (int)left -isDefNUseOperand;
   int RBonus = (int)right-isDefNUseOperand;
-  
+
   // Special tie breaker: if two nodes share a operand, the one that
   // use it as a defuse operand is preferred.
   if (left-isTwoAddress  !right-isTwoAddress) {
@@ -798,6 +811,20 @@
   RBonus++;
   }
   
+  // Push stores up as much as possible. This really help code like this:
+  //   load
+  //   compute
+  //   store
+  //   load
+  //   compute
+  //   store
+  // This would make sure the scheduled code completed all computations and
+  // the stores before the next series of computation starts.
+  if (!left-isStore  right-isStore)
+LBonus += 2;
+  if (left-isStore  !right-isStore)
+RBonus += 2;
+
   // Priority1 is just the number of live range genned.
   int LPriority1 = left -NumPredsLeft - LBonus;
   int RPriority1 = right-NumPredsLeft - RBonus;
@@ -819,9 +846,9 @@
 
 /// CalcNodePriority - Priority is the Sethi Ullman number. 
 /// Smaller number is the higher priority.
-int RegReductionPriorityQueue::CalcNodePriority(const SUnit *SU) {
-  int SethiUllmanNumber = SethiUllmanNumbers[SU-NodeNum];
-  if (SethiUllmanNumber != INT_MIN)
+unsigned

[llvm-commits] CVS: llvm-test/Makefile.programs

2006-05-01 Thread Evan Cheng 


Changes in directory llvm-test:

Makefile.programs updated: 1.207 - 1.208
---
Log message:

Set llcbeta to -sched-ignore-store to test a scheduler tweak. (This option 
turns off the tweak.)

---
Diffs of the changes:  (+1 -1)

 Makefile.programs |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm-test/Makefile.programs
diff -u llvm-test/Makefile.programs:1.207 llvm-test/Makefile.programs:1.208
--- llvm-test/Makefile.programs:1.207   Mon May  1 03:57:18 2006
+++ llvm-test/Makefile.programs Mon May  1 04:16:32 2006
@@ -197,7 +197,7 @@
 LLCBETAOPTION := -sched=simple 
 endif
 ifeq ($(ARCH),x86)
-LLCBETAOPTION := -enable-x86-fastcc
+LLCBETAOPTION := -sched-ignore-store
 endif
 ifeq ($(ARCH),Sparc)
 LLCBETAOPTION := -enable-sparc-v9-insts



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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp

2006-05-01 Thread Evan Cheng 


Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAGList.cpp updated: 1.51 - 1.52
---
Log message:

Dis-favor stores more

---
Diffs of the changes:  (+2 -2)

 ScheduleDAGList.cpp |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.51 
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.52
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.51  Mon May  1 
04:14:40 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp   Mon May  1 04:20:44 2006
@@ -821,9 +821,9 @@
   // This would make sure the scheduled code completed all computations and
   // the stores before the next series of computation starts.
   if (!left-isStore  right-isStore)
-LBonus += 2;
+LBonus += 4;
   if (left-isStore  !right-isStore)
-RBonus += 2;
+RBonus += 4;
 
   // Priority1 is just the number of live range genned.
   int LPriority1 = left -NumPredsLeft - LBonus;



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[llvm-commits] CVS: llvm/utils/TableGen/InstrInfoEmitter.cpp

2006-05-01 Thread Evan Cheng 


Changes in directory llvm/utils/TableGen:

InstrInfoEmitter.cpp updated: 1.37 - 1.38
---
Log message:

Formating

---
Diffs of the changes:  (+1 -1)

 InstrInfoEmitter.cpp |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/utils/TableGen/InstrInfoEmitter.cpp
diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.37 
llvm/utils/TableGen/InstrInfoEmitter.cpp:1.38
--- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.37   Mon May  1 04:04:20 2006
+++ llvm/utils/TableGen/InstrInfoEmitter.cppMon May  1 04:30:17 2006
@@ -195,7 +195,7 @@
 Record *Operator = OpDef-getDef();
 if (Operator-isSubClassOf(SDNode) 
 Operator-getValueAsString(Opcode) == ISD::STORE)
-isStore = true;
+  isStore = true;
   }
 }
   }



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[llvm-commits] CVS: llvm/lib/Target/Target.td

2006-05-01 Thread Chris Lattner 


Changes in directory llvm/lib/Target:

Target.td updated: 1.77 - 1.78
---
Log message:

Put PHI/INLINEASM into the correct namespace.


---
Diffs of the changes:  (+2 -0)

 Target.td |2 ++
 1 files changed, 2 insertions(+)


Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td:1.77 llvm/lib/Target/Target.td:1.78
--- llvm/lib/Target/Target.td:1.77  Wed Apr 19 15:38:28 2006
+++ llvm/lib/Target/Target.td   Mon May  1 12:00:49 2006
@@ -224,10 +224,12 @@
 def PHI : Instruction {
   let OperandList = (ops variable_ops);
   let AsmString = PHINODE;
+  let Namespace = TargetInstrInfo;
 }
 def INLINEASM : Instruction {
   let OperandList = (ops variable_ops);
   let AsmString = ;
+  let Namespace = TargetInstrInfo;
 }
 
 
//===--===//



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[llvm-commits] CVS: llvm/lib/CodeGen/VirtRegMap.cpp

2006-05-01 Thread Chris Lattner 


Changes in directory llvm/lib/CodeGen:

VirtRegMap.cpp updated: 1.63 - 1.64
---
Log message:

When promoting a load to a reg-reg copy, where the load was a previous 
instruction folded with spill code, make sure the remove the load from
the virt reg folded map.


---
Diffs of the changes:  (+1 -0)

 VirtRegMap.cpp |1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/CodeGen/VirtRegMap.cpp
diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.63 
llvm/lib/CodeGen/VirtRegMap.cpp:1.64
--- llvm/lib/CodeGen/VirtRegMap.cpp:1.63Mon May  1 16:16:03 2006
+++ llvm/lib/CodeGen/VirtRegMap.cpp Mon May  1 16:17:10 2006
@@ -712,6 +712,7 @@
   NextMII = MI;
   --NextMII;  // backtrack to the copy.
 }
+VRM.RemoveFromFoldedVirtMap(MI);
 MBB.erase(MI);
 goto ProcessNextInst;
   }



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[llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h

2006-05-01 Thread Jeff Cohen 


Changes in directory llvm/include/llvm/CodeGen:

AsmPrinter.h updated: 1.32 - 1.33
---
Log message:

Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more 
work).

---
Diffs of the changes:  (+6 -1)

 AsmPrinter.h |7 ++-
 1 files changed, 6 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/CodeGen/AsmPrinter.h
diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.32 
llvm/include/llvm/CodeGen/AsmPrinter.h:1.33
--- llvm/include/llvm/CodeGen/AsmPrinter.h:1.32 Sat Apr 22 13:53:45 2006
+++ llvm/include/llvm/CodeGen/AsmPrinter.h  Mon May  1 20:16:28 2006
@@ -21,6 +21,7 @@
 
 namespace llvm {
   class Constant;
+  class ConstantArray;
   class Mangler;
   class GlobalVariable;
 
@@ -253,7 +254,11 @@
 
 /// EmitZeros - Emit a block of zeros.
 ///
-void EmitZeros(uint64_t NumZeros) const;
+virtual void EmitZeros(uint64_t NumZeros) const;
+
+/// EmitString - Emit a zero-byte-terminated string constant.
+///
+virtual void EmitString(const ConstantArray *CVA) const;
 
 /// EmitConstantValueOnly - Print out the specified constant, without a
 /// storage class.  Only constants of first-class type are allowed here.



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[llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp

2006-05-01 Thread Jeff Cohen 


Changes in directory llvm/lib/CodeGen:

AsmPrinter.cpp updated: 1.60 - 1.61
---
Log message:

Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more 
work).

---
Diffs of the changes:  (+16 -10)

 AsmPrinter.cpp |   26 --
 1 files changed, 16 insertions(+), 10 deletions(-)


Index: llvm/lib/CodeGen/AsmPrinter.cpp
diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.60 
llvm/lib/CodeGen/AsmPrinter.cpp:1.61
--- llvm/lib/CodeGen/AsmPrinter.cpp:1.60Sun Apr 30 23:11:03 2006
+++ llvm/lib/CodeGen/AsmPrinter.cpp Mon May  1 20:16:28 2006
@@ -372,6 +372,21 @@
   O  \;
 }
 
+/// EmitString - Emit a zero-byte-terminated string constant.
+///
+void AsmPrinter::EmitString(const ConstantArray *CVA) const {
+  unsigned NumElts = CVA-getNumOperands();
+  if (AscizDirective  NumElts  
+  castConstantInt(CVA-getOperand(NumElts-1))-getRawValue() == 0) {
+O  AscizDirective;
+printAsCString(O, CVA, NumElts-1);
+  } else {
+O  AsciiDirective;
+printAsCString(O, CVA, NumElts);
+  }
+  O  \n;
+}
+
 /// EmitGlobalConstant - Print a general LLVM constant to the .s file.
 ///
 void AsmPrinter::EmitGlobalConstant(const Constant *CV) {
@@ -382,16 +397,7 @@
 return;
   } else if (const ConstantArray *CVA = dyn_castConstantArray(CV)) {
 if (CVA-isString()) {
-  unsigned NumElts = CVA-getNumOperands();
-  if (AscizDirective  NumElts  
-  castConstantInt(CVA-getOperand(NumElts-1))-getRawValue() == 0) {
-O  AscizDirective;
-printAsCString(O, CVA, NumElts-1);
-  } else {
-O  AsciiDirective;
-printAsCString(O, CVA, NumElts);
-  }
-  O  \n;
+  EmitString(CVA);
 } else { // Not a string.  Print the values in successive locations
   for (unsigned i = 0, e = CVA-getNumOperands(); i != e; ++i)
 EmitGlobalConstant(CVA-getOperand(i));



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[llvm-commits] CVS: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp X86IntelAsmPrinter.h

2006-05-01 Thread Jeff Cohen 


Changes in directory llvm/lib/Target/X86:

X86IntelAsmPrinter.cpp updated: 1.31 - 1.32
X86IntelAsmPrinter.h updated: 1.15 - 1.16
---
Log message:

Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more 
work).

---
Diffs of the changes:  (+97 -17)

 X86IntelAsmPrinter.cpp |  106 ++---
 X86IntelAsmPrinter.h   |8 ++-
 2 files changed, 97 insertions(+), 17 deletions(-)


Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.31 
llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.32
--- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.31 Mon May  1 00:53:50 2006
+++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp  Mon May  1 20:16:28 2006
@@ -15,12 +15,31 @@
 
 #include X86IntelAsmPrinter.h
 #include X86.h
+#include llvm/Constants.h
 #include llvm/Module.h
 #include llvm/Assembly/Writer.h
 #include llvm/Support/Mangler.h
 #include llvm/Target/TargetOptions.h
 using namespace llvm;
 
+X86IntelAsmPrinter::X86IntelAsmPrinter(std::ostream O, X86TargetMachine TM)
+: X86SharedAsmPrinter(O, TM) {
+  CommentString = ;;
+  GlobalPrefix = _;
+  PrivateGlobalPrefix = $;
+  AlignDirective = \talign\t;
+  ZeroDirective = 0;
+  AsciiDirective = \tdb\t;
+  AscizDirective = 0;
+  Data8bitsDirective = \t.db\t;
+  Data16bitsDirective = \t.dw\t;
+  Data32bitsDirective = \t.dd\t;
+  Data64bitsDirective = \t.dq\t;
+  HasDotTypeDotSizeDirective = false;
+
+  O  \t.686\n\t.model flat\n\toption dotname\n;
+}
+
 /// runOnMachineFunction - This uses the printMachineInstruction()
 /// method to print assembly for each instruction.
 ///
@@ -38,12 +57,11 @@
   EmitConstantPool(MF.getConstantPool());
 
   // Print out labels for the function.
-  SwitchSection(\t.text\n, MF.getFunction());
+  SwitchSection(.code\n, MF.getFunction());
   EmitAlignment(4);
-  O  \t.globl\t  CurrentFnName  \n;
-  if (HasDotTypeDotSizeDirective)
-O  \t.type\t  CurrentFnName  , @function\n;
-  O  CurrentFnName  :\n;
+  if (MF.getFunction()-getLinkage() == GlobalValue::ExternalLinkage)
+O  \tpublic   CurrentFnName  \n;
+  O  CurrentFnName  \tproc near\n;
   
   if (forDarwin) {
 // Emit pre-function debug information.
@@ -71,6 +89,8 @@
 DW.EndFunction();
   }
 
+  O  CurrentFnName  \tendp\n;
+
   // We didn't modify anything.
   return false;
 }
@@ -403,17 +423,75 @@
 
 bool X86IntelAsmPrinter::doInitialization(Module M) {
   X86SharedAsmPrinter::doInitialization(M);
-  // Tell gas we are outputting Intel syntax (not ATT syntax) assembly.
-  //
-  // Bug: gas in `intel_syntax noprefix' mode interprets the symbol `Sp' in an
-  // instruction as a reference to the register named sp, and if you try to
-  // reference a symbol `Sp' (e.g. `mov ECX, OFFSET Sp') then it gets 
lowercased
-  // before being looked up in the symbol table. This creates spurious
-  // `undefined symbol' errors when linking. Workaround: Do not use `noprefix'
-  // mode, and decorate all register names with percent signs.
-  O  \t.intel_syntax\n;
+  Mang-markCharUnacceptable('.');
   return false;
 }
 
+void X86IntelAsmPrinter::EmitZeros(uint64_t NumZeros) const {
+  if (NumZeros) {
+O  \tdb   NumZeros   dup(0)\n;
+  }
+}
+
+void X86IntelAsmPrinter::EmitString(const ConstantArray *CVA) const {
+  unsigned NumElts = CVA-getNumOperands();
+  if (NumElts) {
+// ML does not have escape sequences except '' for '.  It also has a 
maximum
+// string length of 255.
+unsigned len = 0;
+bool inString = false;
+for (unsigned i = 0; i  NumElts; i++) {
+  int n = castConstantInt(CVA-getOperand(i))-getRawValue()  255;
+  if (len == 0)
+O  \tdb ;
+
+  if (n = 32  n = 127) {
+if (!inString) {
+  if (len  0) {
+O  ,';
+len += 2;
+  } else {
+O  ';
+len++;
+  }
+  inString = true;
+}
+if (n == '\'') {
+  O  ';
+  len++;
+}
+O  char(n);
+  } else {
+if (inString) {
+  O  ';
+  len++;
+  inString = false;
+}
+if (len  0) {
+  O  ,;
+  len++;
+}
+O  n;
+len += 1 + (n  9) + (n  99);
+  }
+
+  if (len  60) {
+if (inString) {
+  O  ';
+  inString = false;
+}
+O  \n;
+len = 0;
+  }
+}
+
+if (len  0) {
+  if (inString)
+O  ';
+  O  \n;
+}
+  }
+}
+
 // Include the auto-generated portion of the assembly writer.
 #include X86GenAsmWriter1.inc


Index: llvm/lib/Target/X86/X86IntelAsmPrinter.h
diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.15 
llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.16
--- llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.15   Mon May  1 00:53:50 2006
+++ llvm/lib/Target/X86/X86IntelAsmPrinter.hMon May  1 20:16:28 2006
@@ -21,8 +21,7 @@
 namespace llvm {
 
 struct X86IntelAsmPrinter : public X86SharedAsmPrinter {
-

[llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h

2006-05-01 Thread Jeff Cohen 


Changes in directory llvm/include/llvm/CodeGen:

AsmPrinter.h updated: 1.33 - 1.34
---
Log message:

Finish support for Microsoft ML/MASM.  May still be a few rough edges.

---
Diffs of the changes:  (+3 -1)

 AsmPrinter.h |4 +++-
 1 files changed, 3 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/CodeGen/AsmPrinter.h
diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.33 
llvm/include/llvm/CodeGen/AsmPrinter.h:1.34
--- llvm/include/llvm/CodeGen/AsmPrinter.h:1.33 Mon May  1 20:16:28 2006
+++ llvm/include/llvm/CodeGen/AsmPrinter.h  Mon May  1 22:11:50 2006
@@ -26,10 +26,12 @@
   class GlobalVariable;
 
   class AsmPrinter : public MachineFunctionPass {
+  protected:
 /// CurrentSection - The current section we are emitting to.  This is
 /// controlled and used by the SwitchSection method.
 std::string CurrentSection;
 
+  private:
 /// FunctionNumber - This provides a unique ID for each function emitted in
 /// this translation unit.  It is autoincremented by SetupMachineFunction,
 /// and can be accessed with getFunctionNumber() and 
@@ -185,7 +187,7 @@
 /// If the new section is an empty string, this method forgets what the
 /// current section is, but does not emit a .section directive.
 ///
-void SwitchSection(const char *NewSection, const GlobalValue *GV);
+virtual void SwitchSection(const char *NewSection, const GlobalValue *GV);
 
 /// getPreferredAlignmentLog - Return the preferred alignment of the
 /// specified global, returned in log form.  This includes an explicitly



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[llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp

2006-05-01 Thread Jeff Cohen 


Changes in directory llvm/lib/CodeGen:

AsmPrinter.cpp updated: 1.61 - 1.62
---
Log message:

De-virtualize EmitZeroes.

---
Diffs of the changes:  (+7 -3)

 AsmPrinter.cpp |   10 +++---
 1 files changed, 7 insertions(+), 3 deletions(-)


Index: llvm/lib/CodeGen/AsmPrinter.cpp
diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.61 
llvm/lib/CodeGen/AsmPrinter.cpp:1.62
--- llvm/lib/CodeGen/AsmPrinter.cpp:1.61Mon May  1 20:16:28 2006
+++ llvm/lib/CodeGen/AsmPrinter.cpp Mon May  1 22:46:13 2006
@@ -37,6 +37,7 @@
   InlineAsmStart(#APP\n\t),
   InlineAsmEnd(\t#NO_APP\n),
   ZeroDirective(\t.zero\t),
+  ZeroDirectiveSuffix(0),
   AsciiDirective(\t.ascii\t),
   AscizDirective(\t.asciz\t),
   Data8bitsDirective(\t.byte\t),
@@ -240,9 +241,12 @@
 ///
 void AsmPrinter::EmitZeros(uint64_t NumZeros) const {
   if (NumZeros) {
-if (ZeroDirective)
-  O  ZeroDirective  NumZeros  \n;
-else {
+if (ZeroDirective) {
+  O  ZeroDirective  NumZeros;
+  if (ZeroDirectiveSuffix)
+O  ZeroDirectiveSuffix;
+  O  \n;
+} else {
   for (; NumZeros; --NumZeros)
 O  Data8bitsDirective  0\n;
 }



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[llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp

2006-05-01 Thread Jeff Cohen 


Changes in directory llvm/lib/CodeGen:

AsmPrinter.cpp updated: 1.62 - 1.63
---
Log message:

De-virtualize SwitchSection.

---
Diffs of the changes:  (+42 -10)

 AsmPrinter.cpp |   52 ++--
 1 files changed, 42 insertions(+), 10 deletions(-)


Index: llvm/lib/CodeGen/AsmPrinter.cpp
diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.62 
llvm/lib/CodeGen/AsmPrinter.cpp:1.63
--- llvm/lib/CodeGen/AsmPrinter.cpp:1.62Mon May  1 22:46:13 2006
+++ llvm/lib/CodeGen/AsmPrinter.cpp Mon May  1 22:58:45 2006
@@ -47,6 +47,7 @@
   AlignDirective(\t.align\t),
   AlignmentIsInBytes(true),
   SwitchToSectionDirective(\t.section\t),
+  MLSections(false),
   ConstantPoolSection(\t.section .rodata\n),
   JumpTableSection(\t.section .rodata\n),
   StaticCtorsSection(\t.section .ctors,\aw\,@progbits),
@@ -63,16 +64,47 @@
 ///
 void AsmPrinter::SwitchSection(const char *NewSection, const GlobalValue *GV) {
   std::string NS;
-  
-  if (GV  GV-hasSection())
-NS = SwitchToSectionDirective + GV-getSection();
-  else
-NS = std::string(\t)+NewSection;
-  
-  if (CurrentSection != NS) {
-CurrentSection = NS;
-if (!CurrentSection.empty())
-  O  CurrentSection  '\n';
+
+  // Microsoft ML/MASM has a fundamentally different approach to handling
+  // sections.
+
+  if (MLSections) {
+if (*NewSection == 0) {
+  // Simply end the current section, if any.
+  if (CurrentSection != ) {
+O  CurrentSection  \tends\n;
+CurrentSection = ;
+  }
+  return;
+}
+
+bool isData = strcmp(NewSection , .data) == 0;
+
+if (GV  GV-hasSection())
+  NS = GV-getSection();
+else if (isData)
+  NS = _data;
+else
+  NS = _text;
+
+if (CurrentSection != NS) {
+  if (CurrentSection != )
+O  CurrentSection  \tends\n;
+  CurrentSection = NS;
+  O  CurrentSection  (isData ? \tsegment 'DATA'\n
+ : \tsegment 'CODE'\n);
+}
+  } else {
+if (GV  GV-hasSection())
+  NS = SwitchToSectionDirective + GV-getSection();
+else
+  NS = std::string(\t)+NewSection;
+
+if (CurrentSection != NS) {
+  CurrentSection = NS;
+  if (!CurrentSection.empty())
+O  CurrentSection  '\n';
+}
   }
 }
 



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[llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h

2006-05-01 Thread Jeff Cohen 


Changes in directory llvm/include/llvm/CodeGen:

AsmPrinter.h updated: 1.35 - 1.36
---
Log message:

De-virtualize SwitchSection.

---
Diffs of the changes:  (+2 -3)

 AsmPrinter.h |5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)


Index: llvm/include/llvm/CodeGen/AsmPrinter.h
diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.35 
llvm/include/llvm/CodeGen/AsmPrinter.h:1.36
--- llvm/include/llvm/CodeGen/AsmPrinter.h:1.35 Mon May  1 22:46:13 2006
+++ llvm/include/llvm/CodeGen/AsmPrinter.h  Mon May  1 22:58:45 2006
@@ -26,12 +26,10 @@
   class GlobalVariable;
 
   class AsmPrinter : public MachineFunctionPass {
-  protected:
 /// CurrentSection - The current section we are emitting to.  This is
 /// controlled and used by the SwitchSection method.
 std::string CurrentSection;
 
-  private:
 /// FunctionNumber - This provides a unique ID for each function emitted in
 /// this translation unit.  It is autoincremented by SetupMachineFunction,
 /// and can be accessed with getFunctionNumber() and 
@@ -139,6 +137,7 @@
 /// emit a global to an arbitrary section.  The section name is emited 
after
 /// this.
 const char *SwitchToSectionDirective;  // Defaults to \t.section\t
+bool MLSections;  // True if Microsoft ML assembler is targetted
 
 /// ConstantPoolSection - This is the section that we SwitchToSection right
 /// before emitting the constant pool for a function.
@@ -188,7 +187,7 @@
 /// If the new section is an empty string, this method forgets what the
 /// current section is, but does not emit a .section directive.
 ///
-virtual void SwitchSection(const char *NewSection, const GlobalValue *GV);
+void SwitchSection(const char *NewSection, const GlobalValue *GV);
 
 /// getPreferredAlignmentLog - Return the preferred alignment of the
 /// specified global, returned in log form.  This includes an explicitly



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[llvm-commits] CVS: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp X86IntelAsmPrinter.h

2006-05-01 Thread Jeff Cohen 


Changes in directory llvm/lib/Target/X86:

X86IntelAsmPrinter.cpp updated: 1.34 - 1.35
X86IntelAsmPrinter.h updated: 1.18 - 1.19
---
Log message:

De-virtualize SwitchSection.

---
Diffs of the changes:  (+2 -27)

 X86IntelAsmPrinter.cpp |   28 ++--
 X86IntelAsmPrinter.h   |1 -
 2 files changed, 2 insertions(+), 27 deletions(-)


Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.34 
llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.35
--- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.34 Mon May  1 22:46:13 2006
+++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp  Mon May  1 22:58:45 2006
@@ -28,6 +28,7 @@
   GlobalPrefix = _;
   PrivateGlobalPrefix = $;
   AlignDirective = \talign\t;
+  MLSections = true;
   ZeroDirective = \tdb\t;
   ZeroDirectiveSuffix =  dup(0);
   AsciiDirective = \tdb\t;
@@ -443,36 +444,11 @@
 
 bool X86IntelAsmPrinter::doFinalization(Module M) {
   X86SharedAsmPrinter::doFinalization(M);
-  if (CurrentSection != )
-O  CurrentSection  \tends\n;
+  SwitchSection(, 0);
   O  \tend\n;
   return false;
 }
 
-void X86IntelAsmPrinter::SwitchSection(const char *NewSection,
-   const GlobalValue *GV) {
-  if (*NewSection == 0)
-return;
-  
-  std::string NS;
-  bool isData = strcmp(NewSection , .data) == 0;
-
-  if (GV  GV-hasSection())
-NS = GV-getSection();
-  else if (isData)
-NS = _data;
-  else
-NS = _text;
-
-  if (CurrentSection != NS) {
-if (CurrentSection != )
-  O  CurrentSection  \tends\n;
-CurrentSection = NS;
-O  CurrentSection  (isData ? \tsegment 'DATA'\n
-   : \tsegment 'CODE'\n);
-  }
-}
-
 void X86IntelAsmPrinter::EmitString(const ConstantArray *CVA) const {
   unsigned NumElts = CVA-getNumOperands();
   if (NumElts) {


Index: llvm/lib/Target/X86/X86IntelAsmPrinter.h
diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.18 
llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.19
--- llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.18   Mon May  1 22:46:13 2006
+++ llvm/lib/Target/X86/X86IntelAsmPrinter.hMon May  1 22:58:45 2006
@@ -92,7 +92,6 @@
   bool doInitialization(Module M);
   bool doFinalization(Module M);
 
-  virtual void SwitchSection(const char *NewSection, const GlobalValue *GV);
   virtual void EmitString(const ConstantArray *CVA) const;
 };
 



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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/LowerAllocations.cpp LowerSelect.cpp LowerSwitch.cpp Mem2Reg.cpp

2006-05-01 Thread Chris Lattner 


Changes in directory llvm/lib/Transforms/Scalar:

LowerAllocations.cpp updated: 1.55 - 1.56
LowerSelect.cpp updated: 1.3 - 1.4
LowerSwitch.cpp updated: 1.18 - 1.19
Mem2Reg.cpp updated: 1.14 - 1.15
---
Log message:

Add pass ID's for various passes, so they can be AddRequiredID.  Patch by
Domagoj Babic!


---
Diffs of the changes:  (+8 -0)

 LowerAllocations.cpp |2 ++
 LowerSelect.cpp  |2 ++
 LowerSwitch.cpp  |2 ++
 Mem2Reg.cpp  |2 ++
 4 files changed, 8 insertions(+)


Index: llvm/lib/Transforms/Scalar/LowerAllocations.cpp
diff -u llvm/lib/Transforms/Scalar/LowerAllocations.cpp:1.55 
llvm/lib/Transforms/Scalar/LowerAllocations.cpp:1.56
--- llvm/lib/Transforms/Scalar/LowerAllocations.cpp:1.55Sat Oct 22 
23:37:20 2005
+++ llvm/lib/Transforms/Scalar/LowerAllocations.cpp Mon May  1 23:24:36 2006
@@ -60,6 +60,8 @@
   X(lowerallocs, Lower allocations from instructions to calls);
 }
 
+// Publically exposed interface to pass...
+const PassInfo *llvm::LowerAllocationsID = X.getPassInfo();
 // createLowerAllocationsPass - Interface to this file...
 FunctionPass *llvm::createLowerAllocationsPass(bool LowerMallocArgToInteger) {
   return new LowerAllocations(LowerMallocArgToInteger);


Index: llvm/lib/Transforms/Scalar/LowerSelect.cpp
diff -u llvm/lib/Transforms/Scalar/LowerSelect.cpp:1.3 
llvm/lib/Transforms/Scalar/LowerSelect.cpp:1.4
--- llvm/lib/Transforms/Scalar/LowerSelect.cpp:1.3  Thu Apr 21 18:45:12 2005
+++ llvm/lib/Transforms/Scalar/LowerSelect.cpp  Mon May  1 23:24:36 2006
@@ -47,6 +47,8 @@
   X(lowerselect, Lower select instructions to branches);
 }
 
+// Publically exposed interface to pass...
+const PassInfo *llvm::LowerSelectID = X.getPassInfo();
 
//===--===//
 // This pass converts SelectInst instructions into conditional branch and PHI
 // instructions.  If the OnlyFP flag is set to true, then only floating point


Index: llvm/lib/Transforms/Scalar/LowerSwitch.cpp
diff -u llvm/lib/Transforms/Scalar/LowerSwitch.cpp:1.18 
llvm/lib/Transforms/Scalar/LowerSwitch.cpp:1.19
--- llvm/lib/Transforms/Scalar/LowerSwitch.cpp:1.18 Sun Jan 22 17:32:06 2006
+++ llvm/lib/Transforms/Scalar/LowerSwitch.cpp  Mon May  1 23:24:36 2006
@@ -60,6 +60,8 @@
   X(lowerswitch, Lower SwitchInst's to branches);
 }
 
+// Publically exposed interface to pass...
+const PassInfo *llvm::LowerSwitchID = X.getPassInfo();
 // createLowerSwitchPass - Interface to this file...
 FunctionPass *llvm::createLowerSwitchPass() {
   return new LowerSwitch();


Index: llvm/lib/Transforms/Scalar/Mem2Reg.cpp
diff -u llvm/lib/Transforms/Scalar/Mem2Reg.cpp:1.14 
llvm/lib/Transforms/Scalar/Mem2Reg.cpp:1.15
--- llvm/lib/Transforms/Scalar/Mem2Reg.cpp:1.14 Thu Apr 21 18:45:12 2005
+++ llvm/lib/Transforms/Scalar/Mem2Reg.cpp  Mon May  1 23:24:36 2006
@@ -74,6 +74,8 @@
   return Changed;
 }
 
+// Publically exposed interface to pass...
+const PassInfo *llvm::PromoteMemoryToRegisterID = X.getPassInfo();
 // createPromoteMemoryToRegister - Provide an entry point to create this pass.
 //
 FunctionPass *llvm::createPromoteMemoryToRegisterPass() {



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[llvm-commits] CVS: llvm/include/llvm/Transforms/Scalar.h

2006-05-01 Thread Chris Lattner 


Changes in directory llvm/include/llvm/Transforms:

Scalar.h updated: 1.63 - 1.64
---
Log message:

Add pass ID's for various passes, so they can be AddRequiredID.  Patch by
Domagoj Babic!


---
Diffs of the changes:  (+20 -14)

 Scalar.h |   34 --
 1 files changed, 20 insertions(+), 14 deletions(-)


Index: llvm/include/llvm/Transforms/Scalar.h
diff -u llvm/include/llvm/Transforms/Scalar.h:1.63 
llvm/include/llvm/Transforms/Scalar.h:1.64
--- llvm/include/llvm/Transforms/Scalar.h:1.63  Thu Apr 20 10:45:54 2006
+++ llvm/include/llvm/Transforms/Scalar.h   Mon May  1 23:24:20 2006
@@ -163,6 +163,7 @@
 //   ret int %Y
 //
 FunctionPass *createPromoteMemoryToRegisterPass();
+extern const PassInfo *PromoteMemoryToRegisterID;
 
 
//===--===//
 //
@@ -240,31 +241,36 @@
 extern const PassInfo *LoopSimplifyID;
 
 
//===--===//
+// This pass converts SelectInst instructions into conditional branch and PHI
+// instructions.  If the OnlyFP flag is set to true, then only floating point
+// select instructions are lowered.
 //
-// This pass eliminates call instructions to the current function which occur
-// immediately before return instructions.
-//
-FunctionPass *createTailCallEliminationPass();
-
+FunctionPass *createLowerSelectPass(bool OnlyFP = false);
+extern const PassInfo *LowerSelectID;
 
 
//===--===//
-// This pass convert malloc and free instructions to %malloc  %free function
-// calls.
+//
+// LowerAllocations Pass - Turn malloc and free instructions into %malloc and
+// %free calls.
+//
+//   AU.addRequiredID(LowerAllocationsID);
 //
 FunctionPass *createLowerAllocationsPass(bool LowerMallocArgToInteger = false);
+extern const PassInfo *LowerAllocationsID;
 
 
//===--===//
-// This pass converts SwitchInst instructions into a sequence of chained binary
-// branch instructions.
 //
-FunctionPass *createLowerSwitchPass();
+// This pass eliminates call instructions to the current function which occur
+// immediately before return instructions.
+//
+FunctionPass *createTailCallEliminationPass();
 
 
//===--===//
-// This pass converts SelectInst instructions into conditional branch and PHI
-// instructions.  If the OnlyFP flag is set to true, then only floating point
-// select instructions are lowered.
+// This pass converts SwitchInst instructions into a sequence of chained binary
+// branch instructions.
 //
-FunctionPass *createLowerSelectPass(bool OnlyFP = false);
+FunctionPass *createLowerSwitchPass();
+extern const PassInfo *LowerSwitchID;
 
 
//===--===//
 // This pass converts PackedType operations into low-level scalar operations.



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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCJITInfo.cpp

2006-05-01 Thread Nate Begeman 


Changes in directory llvm/lib/Target/PowerPC:

PPCJITInfo.cpp updated: 1.19 - 1.20
---
Log message:

Update the PPC compilation callback code to not need weird abi-violating
prologs and epilogs, keep all the asm in one place, and remove use of 
compiler builtin functions.


---
Diffs of the changes:  (+46 -49)

 PPCJITInfo.cpp |   95 +++--
 1 files changed, 46 insertions(+), 49 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCJITInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCJITInfo.cpp:1.19 
llvm/lib/Target/PowerPC/PPCJITInfo.cpp:1.20
--- llvm/lib/Target/PowerPC/PPCJITInfo.cpp:1.19 Mon Apr 24 23:45:59 2006
+++ llvm/lib/Target/PowerPC/PPCJITInfo.cpp  Mon May  1 23:50:05 2006
@@ -60,23 +60,51 @@
 .align 2\n
 .globl _PPC32CompilationCallback\n
 _PPC32CompilationCallback:\n
-// Make space for 29 ints r[3-31] and 14 doubles f[0-13]
-stwu r1, -272(r1)\n
-mflr r11\n
-stw r11, 280(r1)\n// Set up a proper stack frame
-stmw r3, 156(r1)\n// Save all of the integer registers
+// Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the 
+// FIXME: need to save v[0-19] for altivec?
+// Set up a proper stack frame
+stwu r1, -208(r1)\n
+mflr r0\n
+stw r0,  216(r1)\n
+// Save all int arg registers
+stw r10, 204(r1)\nstw r9,  200(r1)\n
+stw r8,  196(r1)\nstw r7,  192(r1)\n
+stw r6,  188(r1)\nstw r5,  184(r1)\n
+stw r4,  180(r1)\nstw r3,  176(r1)\n
 // Save all call-clobbered FP regs.
-stfd f1, 44(r1)\n  stfd f2, 52(r1)\n  stfd f3, 60(r1)\n
-stfd f4, 68(r1)\n stfd f5, 76(r1)\n stfd f6, 84(r1)\n
-stfd f7, 92(r1)\n stfd f8, 100(r1)\n stfd f9, 108(r1)\n
-stfd f10, 116(r1)\n stfd f11, 124(r1)\n stfd f12, 132(r1)\n
-stfd f13, 140(r1)\n
-
-// Now that everything is saved, go to the C compilation callback function,
-// passing the address of the intregs and fpregs.
-addi r3, r1, 156\n  // IntRegs[0]
-addi r4, r1, 44\n   // FPRegs[0]
+stfd f13, 168(r1)\n   stfd f12, 160(r1)\n
+stfd f11, 152(r1)\n   stfd f10, 144(r1)\n
+stfd f9,  136(r1)\n   stfd f8,  128(r1)\n
+stfd f7,  120(r1)\n   stfd f6,  112(r1)\n
+stfd f5,  104(r1)\n   stfd f4,   96(r1)\n
+stfd f3,   88(r1)\n   stfd f2,   80(r1)\n
+stfd f1,   72(r1)\n
+// Arguments to Compilation Callback:
+// r3 - our lr (address of the call instruction in stub plus 4)
+// r4 - stub's lr (address of instruction that called the stub plus 4)
+mr   r3, r0\n
+lwz  r2, 208(r1)\n // stub's frame
+lwz  r4, 8(r2)\n // stub's lr
 bl _PPC32CompilationCallbackC\n
+mtctr r3\n
+// Restore all int arg registers
+lwz r10, 204(r1)\nlwz r9,  200(r1)\n
+lwz r8,  196(r1)\nlwz r7,  192(r1)\n
+lwz r6,  188(r1)\nlwz r5,  184(r1)\n
+lwz r4,  180(r1)\nlwz r3,  176(r1)\n
+// Restore all FP arg registers
+lfd f13, 168(r1)\nlfd f12, 160(r1)\n
+lfd f11, 152(r1)\nlfd f10, 144(r1)\n
+lfd f9,  136(r1)\nlfd f8,  128(r1)\n
+lfd f7,  120(r1)\nlfd f6,  112(r1)\n
+lfd f5,  104(r1)\nlfd f4,   96(r1)\n
+lfd f3,   88(r1)\nlfd f2,   80(r1)\n
+lfd f1,   72(r1)\n
+// Pop 3 frames off the stack and branch to target
+lwz  r1, 208(r1)\n
+lwz  r2, 8(r1)\n
+mtlr r2\n
+bctr\n
 );
 #else
 void PPC32CompilationCallback() {
@@ -85,12 +113,8 @@
 }
 #endif
 
-extern C void PPC32CompilationCallbackC(unsigned *IntRegs, double *FPRegs) {
-  unsigned *StubCallAddrPlus4 = (unsigned*)__builtin_return_address(0+1);
-  unsigned *OrigCallAddrPlus4 = (unsigned*)__builtin_return_address(1+1);
-  unsigned *CurStackPtr   = (unsigned*)__builtin_frame_address(0);
-  unsigned *OrigStackPtr  = (unsigned*)__builtin_frame_address(2+1);
-
+extern C unsigned *PPC32CompilationCallbackC(unsigned *StubCallAddrPlus4,
+   unsigned *OrigCallAddrPlus4) {
   // Adjust the pointer to the address of the call instruction in the stub
   // emitted by emitFunctionStub, rather than the instruction after it.
   unsigned *StubCallAddr = StubCallAddrPlus4 - 1;
@@ -124,37 +148,10 @@
   // who took the address of the stub.
   EmitBranchToAt(StubCallAddr, Target, false);
 
-  // Change the stored stack pointer so that we pop three stack frames:
-  // 1. PPC32CompilationCallbackC's frame
-  // 2. _PPC32CompilationCallback's frame
-  // 3. the stub's frame
-  *CurStackPtr = (intptr_t)OrigStackPtr;
-
   // Put the address of the target function to call and the address to return 
to
   // after calling the target function in a place that is easy to get on the
   // stack after we restore all regs.
-  CurStackPtr[2] = (intptr_t)Target;
-  CurStackPtr[1] = (intptr_t)OrigCallAddrPlus4;
-
-  // Note, this is not a standard epilog!
-#if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)
-  register unsigned *IRR asm (r2) = IntRegs;
-  register double   *FRR asm (r3)

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

2006-05-01 Thread Nate Begeman 


Changes in directory llvm/lib/Target/PowerPC:

PPCAsmPrinter.cpp updated: 1.164 - 1.165
---
Log message:

Extend printBasicBlockLabel a bit so that it can be used to print all 
basic block labels, consolidating the code to do so in one place for each
target.


---
Diffs of the changes:  (+13 -9)

 PPCAsmPrinter.cpp |   22 +-
 1 files changed, 13 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.164 
llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.165
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.164 Sat Apr 22 13:53:45 2006
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp   Tue May  2 00:37:32 2006
@@ -233,7 +233,9 @@
   printOperand(MI, OpNo+1);
 }
 
-virtual void printBasicBlockLabel(const MachineBasicBlock *MBB) const; 
+virtual void printBasicBlockLabel(const MachineBasicBlock *MBB,
+  bool printColon = false,
+  bool printComment = true) const;
 
 virtual bool runOnMachineFunction(MachineFunction F) = 0;
 virtual bool doFinalization(Module M) = 0;
@@ -505,10 +507,15 @@
   return;
 }
 
-void PPCAsmPrinter::printBasicBlockLabel(const MachineBasicBlock *MBB) const {
+void PPCAsmPrinter::printBasicBlockLabel(const MachineBasicBlock *MBB,
+ bool printColon,
+ bool printComment) const {
   O  PrivateGlobalPrefix  BB  getFunctionNumber()  _
- MBB-getNumber()  '\t'  CommentString
- MBB-getBasicBlock()-getName();
+ MBB-getNumber();
+  if (printColon)
+O  ':';
+  if (printComment)
+O  '\t'  CommentString  MBB-getBasicBlock()-getName();
 }
 
 /// runOnMachineFunction - This uses the printMachineInstruction()
@@ -557,11 +564,8 @@
I != E; ++I) {
 // Print a label for the basic block.
 if (I != MF.begin()) {
-  O  PrivateGlobalPrefix  BB  getFunctionNumber()  '_'
- I-getNumber()  :\t;
-  if (!I-getBasicBlock()-getName().empty())
-O  CommentString I-getBasicBlock()-getName();
-  O  \n;
+  printBasicBlockLabel(I, true);
+  O  '\n';
 }
 for (MachineBasicBlock::const_iterator II = I-begin(), E = I-end();
  II != E; ++II) {



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[llvm-commits] CVS: llvm/lib/Target/IA64/IA64AsmPrinter.cpp

2006-05-01 Thread Nate Begeman 


Changes in directory llvm/lib/Target/IA64:

IA64AsmPrinter.cpp updated: 1.26 - 1.27
---
Log message:

Extend printBasicBlockLabel a bit so that it can be used to print all 
basic block labels, consolidating the code to do so in one place for each
target.


---
Diffs of the changes:  (+4 -4)

 IA64AsmPrinter.cpp |8 
 1 files changed, 4 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/IA64/IA64AsmPrinter.cpp
diff -u llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.26 
llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.27
--- llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.26Sat Apr 22 13:53:45 2006
+++ llvm/lib/Target/IA64/IA64AsmPrinter.cpp Tue May  2 00:37:32 2006
@@ -153,10 +153,10 @@
   for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I) {
 // Print a label for the basic block if there are any predecessors.
-if (I-pred_begin() != I-pred_end())
-  O  PrivateGlobalPrefix  LBB  CurrentFnName  _
- I-getNumber()  :\t
- CommentString I-getBasicBlock()-getName()  \n;
+if (I-pred_begin() != I-pred_end()) {
+  printBasicBlockLabel(I, true);
+  O  '\n';
+}
 for (MachineBasicBlock::const_iterator II = I-begin(), E = I-end();
  II != E; ++II) {
   // Print the assembly for the instruction.



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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcAsmPrinter.cpp

2006-05-01 Thread Nate Begeman 


Changes in directory llvm/lib/Target/Sparc:

SparcAsmPrinter.cpp updated: 1.58 - 1.59
---
Log message:

Extend printBasicBlockLabel a bit so that it can be used to print all 
basic block labels, consolidating the code to do so in one place for each
target.


---
Diffs of the changes:  (+4 -4)

 SparcAsmPrinter.cpp |8 
 1 files changed, 4 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
diff -u llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.58 
llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.59
--- llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.58  Sat Apr 22 13:53:45 2006
+++ llvm/lib/Target/Sparc/SparcAsmPrinter.cpp   Tue May  2 00:37:32 2006
@@ -116,10 +116,10 @@
   for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I) {
 // Print a label for the basic block.
-if (I != MF.begin())
-  O  .LBB  Mang-getValueName(MF.getFunction ())
- _  I-getNumber ()  :\t! 
- I-getBasicBlock ()-getName ()  \n;
+if (I != MF.begin()) {
+  printBasicBlockLabel(I, true);
+  O  '\n';
+}
 for (MachineBasicBlock::const_iterator II = I-begin(), E = I-end();
  II != E; ++II) {
   // Print the assembly for the instruction.



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[llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp X86AsmPrinter.cpp X86AsmPrinter.h X86IntelAsmPrinter.cpp

2006-05-01 Thread Nate Begeman 


Changes in directory llvm/lib/Target/X86:

X86ATTAsmPrinter.cpp updated: 1.37 - 1.38
X86AsmPrinter.cpp updated: 1.173 - 1.174
X86AsmPrinter.h updated: 1.15 - 1.16
X86IntelAsmPrinter.cpp updated: 1.35 - 1.36
---
Log message:

Extend printBasicBlockLabel a bit so that it can be used to print all 
basic block labels, consolidating the code to do so in one place for each
target.


---
Diffs of the changes:  (+20 -14)

 X86ATTAsmPrinter.cpp   |8 
 X86AsmPrinter.cpp  |   14 +-
 X86AsmPrinter.h|4 +++-
 X86IntelAsmPrinter.cpp |8 
 4 files changed, 20 insertions(+), 14 deletions(-)


Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.37 
llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.38
--- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.37   Fri Apr 28 18:19:39 2006
+++ llvm/lib/Target/X86/X86ATTAsmPrinter.cppTue May  2 00:37:32 2006
@@ -80,10 +80,10 @@
   for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I) {
 // Print a label for the basic block.
-if (I-pred_begin() != I-pred_end())
-  O  PrivateGlobalPrefix  BB  CurrentFnName  _  
I-getNumber()
- :\t  CommentString I-getBasicBlock()-getName()
- \n;
+if (I-pred_begin() != I-pred_end()) {
+  printBasicBlockLabel(I, true);
+  O  '\n';
+}
 for (MachineBasicBlock::const_iterator II = I-begin(), E = I-end();
  II != E; ++II) {
   // Print the assembly for the instruction.


Index: llvm/lib/Target/X86/X86AsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.173 
llvm/lib/Target/X86/X86AsmPrinter.cpp:1.174
--- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.173 Sat Apr 22 13:53:45 2006
+++ llvm/lib/Target/X86/X86AsmPrinter.cpp   Tue May  2 00:37:32 2006
@@ -206,12 +206,16 @@
   return false; // success
 }
 
-void X86SharedAsmPrinter::printBasicBlockLabel(const MachineBasicBlock *MBB) 
- const {
+void X86SharedAsmPrinter::printBasicBlockLabel(const MachineBasicBlock *MBB,
+   bool printColon,
+   bool printComment) const {
   O  PrivateGlobalPrefix  BB 
-   Mang-getValueName(MBB-getParent()-getFunction())
-   _  MBB-getNumber()  '\t'  CommentString
-   MBB-getBasicBlock()-getName();
+ Mang-getValueName(MBB-getParent()-getFunction())  _ 
+ MBB-getNumber();
+  if (printColon)
+O  ':';
+  if (printComment)
+O  '\t'  CommentString  MBB-getBasicBlock()-getName();
 }
 
 /// createX86CodePrinterPass - Returns a pass that prints the X86 assembly code


Index: llvm/lib/Target/X86/X86AsmPrinter.h
diff -u llvm/lib/Target/X86/X86AsmPrinter.h:1.15 
llvm/lib/Target/X86/X86AsmPrinter.h:1.16
--- llvm/lib/Target/X86/X86AsmPrinter.h:1.15Sat Apr 22 13:53:45 2006
+++ llvm/lib/Target/X86/X86AsmPrinter.h Tue May  2 00:37:32 2006
@@ -89,7 +89,9 @@
MI-getOperand(Op+3).isConstantPoolIndex());
   }
 
-  virtual void printBasicBlockLabel(const MachineBasicBlock *MBB) const; 
+  virtual void printBasicBlockLabel(const MachineBasicBlock *MBB,
+bool printColon = false,
+bool printComment = true) const;
 };
 
 } // end namespace llvm


Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.35 
llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.36
--- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.35 Mon May  1 22:58:45 2006
+++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp  Tue May  2 00:37:32 2006
@@ -72,10 +72,10 @@
   for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I) {
 // Print a label for the basic block if there are any predecessors.
-if (I-pred_begin() != I-pred_end())
-  O  PrivateGlobalPrefix  BB  CurrentFnName  _  
I-getNumber()
- :\t
- CommentString I-getBasicBlock()-getName()  \n;
+if (I-pred_begin() != I-pred_end()) {
+  printBasicBlockLabel(I, true);
+  O  '\n';
+}
 for (MachineBasicBlock::const_iterator II = I-begin(), E = I-end();
  II != E; ++II) {
   // Print the assembly for the instruction.



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