[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.153 - 1.154
---
Log message:
Pull and through and/or/xor. This compiles some bitfield code to:
mov EAX, DWORD PTR [ESP + 4]
mov ECX, DWORD PTR [EAX]
mov EDX, ECX
add EDX, EDX
or EDX, ECX
and EDX, -2147483648
and ECX, 2147483647
or EDX, ECX
mov DWORD PTR [EAX], EDX
ret
instead of:
sub ESP, 4
mov DWORD PTR [ESP], ESI
mov EAX, DWORD PTR [ESP + 8]
mov ECX, DWORD PTR [EAX]
mov EDX, ECX
add EDX, EDX
mov ESI, ECX
and ESI, -2147483648
and EDX, -2147483648
or EDX, ESI
and ECX, 2147483647
or EDX, ECX
mov DWORD PTR [EAX], EDX
mov ESI, DWORD PTR [ESP]
add ESP, 4
ret
---
Diffs of the changes: (+6 -4)
DAGCombiner.cpp | 10 ++
1 files changed, 6 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.153
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.154
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.153 Fri May 5 00:58:59 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri May 5 01:10:43 2006
@@ -1069,11 +1069,13 @@
return DAG.getNode(ISD::TRUNCATE, VT, ORNode);
}
- // fold (and (shl/srl/sra x), (shl/srl/sra y)) - (shl/srl/sra (and x, y))
- // fold (or (shl/srl/sra x), (shl/srl/sra y)) - (shl/srl/sra (or x, y))
- // fold (xor (shl/srl/sra x), (shl/srl/sra y)) - (shl/srl/sra (xor x, y))
+
+ // For each of OP in SHL/SRL/SRA/AND...
+ // fold (and (OP x, z), (OP y, z)) - (OP (and x, y), z)
+ // fold (or (OP x, z), (OP y, z)) - (OP (or x, y), z)
+ // fold (xor (OP x, z), (OP y, z)) - (OP (xor x, y), z)
if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
- N0.getOpcode() == ISD::SRA)
+ N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND)
N0.getOperand(1) == N1.getOperand(1)) {
SDOperand ORNode = DAG.getNode(N-getOpcode(),
N0.getOperand(0).getValueType(),
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.154 - 1.155
---
Log message:
Implement:
// fold (and (sext x), (sext y)) - (sext (and x, y))
// fold (or (sext x), (sext y)) - (sext (or x, y))
// fold (xor (sext x), (sext y)) - (sext (xor x, y))
// fold (and (aext x), (aext y)) - (aext (and x, y))
// fold (or (aext x), (aext y)) - (aext (or x, y))
// fold (xor (aext x), (aext y)) - (aext (xor x, y))
---
Diffs of the changes: (+7 -5)
DAGCombiner.cpp | 12 +++-
1 files changed, 7 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.154
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.155
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.154 Fri May 5 01:10:43 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri May 5 01:31:05 2006
@@ -1045,16 +1045,18 @@
MVT::ValueType VT = N0.getValueType();
assert(N0.getOpcode() == N1.getOpcode() Bad input!);
- // fold (and (zext x), (zext y)) - (zext (and x, y))
- // fold (or (zext x), (zext y)) - (zext (or x, y))
- // fold (xor (zext x), (zext y)) - (zext (xor x, y))
- if (N0.getOpcode() == ISD::ZERO_EXTEND
+ // For each of OP in AND/OR/XOR:
+ // fold (OP (zext x), (zext y)) - (zext (OP x, y))
+ // fold (OP (sext x), (sext y)) - (sext (OP x, y))
+ // fold (OP (aext x), (aext y)) - (aext (OP x, y))
+ if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() ==
ISD::ANY_EXTEND||
+ N0.getOpcode() == ISD::SIGN_EXTEND)
N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
SDOperand ORNode = DAG.getNode(N-getOpcode(),
N0.getOperand(0).getValueType(),
N0.getOperand(0), N1.getOperand(0));
AddToWorkList(ORNode.Val);
-return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
+return DAG.getNode(N0.getOpcode(), VT, ORNode);
}
// fold (and (trunc x), (trunc y)) - (trunc (and x, y))
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td
Changes in directory llvm/lib/Target/X86: X86InstrInfo.td updated: 1.264 - 1.265 --- Log message: Need extload patterns after Chris' DAG combiner changes --- Diffs of the changes: (+11 -1) X86InstrInfo.td | 12 +++- 1 files changed, 11 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.264 llvm/lib/Target/X86/X86InstrInfo.td:1.265 --- llvm/lib/Target/X86/X86InstrInfo.td:1.264 Fri May 5 00:40:20 2006 +++ llvm/lib/Target/X86/X86InstrInfo.td Fri May 5 03:23:07 2006 @@ -306,6 +306,11 @@ def zextloadi32i16 : PatFrag(ops node:$ptr), (i32 (zextload node:$ptr, i16)); def extloadi8i1: PatFrag(ops node:$ptr), (i8 (extload node:$ptr, i1)); +def extloadi16i1 : PatFrag(ops node:$ptr), (i16 (extload node:$ptr, i1)); +def extloadi32i1 : PatFrag(ops node:$ptr), (i32 (extload node:$ptr, i1)); +def extloadi16i8 : PatFrag(ops node:$ptr), (i16 (extload node:$ptr, i8)); +def extloadi32i8 : PatFrag(ops node:$ptr), (i32 (extload node:$ptr, i8)); +def extloadi32i16 : PatFrag(ops node:$ptr), (i32 (extload node:$ptr, i16)); //===--===// // Instruction templates... @@ -2393,7 +2398,12 @@ def : Pat(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src); // extload bool - extload byte -def : Pat(extloadi8i1 addr:$src), (MOV8rm addr:$src); +def : Pat(extloadi8i1 addr:$src), (MOV8rm addr:$src); +def : Pat(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src); +def : Pat(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src); +def : Pat(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src); +def : Pat(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src); +def : Pat(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src); // anyext - zext def : Pat(i16 (anyext R8 :$src)), (MOVZX16rr8 R8 :$src); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.475 - 1.476
---
Log message:
Fix an infinite loop compiling oggenc last night.
---
Diffs of the changes: (+9 -6)
InstructionCombining.cpp | 15 +--
1 files changed, 9 insertions(+), 6 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.475
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.476
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.475 Fri May 5
01:39:07 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Fri May 5 15:51:30 2006
@@ -2642,9 +2642,10 @@
// fold (and (cast A), (cast B)) - (cast (and A, B))
if (CastInst *Op0C = dyn_castCastInst(Op0)) {
+const Type *SrcTy = Op0C-getOperand(0)-getType();
if (CastInst *Op1C = dyn_castCastInst(Op1))
- if (Op0C-getOperand(0)-getType() == Op1C-getOperand(0)-getType()
- Op0C-getOperand(0)-getType()-isIntegral()) {
+ if (SrcTy == Op1C-getOperand(0)-getType() SrcTy-isIntegral()
+ !SrcTy-isLosslesslyConvertibleTo(Op0C-getType())) {
Instruction *NewOp = BinaryOperator::createAnd(Op0C-getOperand(0),
Op1C-getOperand(0),
I.getName());
@@ -2881,9 +2882,10 @@
// fold (or (cast A), (cast B)) - (cast (or A, B))
if (CastInst *Op0C = dyn_castCastInst(Op0)) {
+const Type *SrcTy = Op0C-getOperand(0)-getType();
if (CastInst *Op1C = dyn_castCastInst(Op1))
- if (Op0C-getOperand(0)-getType() == Op1C-getOperand(0)-getType()
- Op0C-getOperand(0)-getType()-isIntegral()) {
+ if (SrcTy == Op1C-getOperand(0)-getType() SrcTy-isIntegral()
+ !SrcTy-isLosslesslyConvertibleTo(Op0C-getType())) {
Instruction *NewOp = BinaryOperator::createOr(Op0C-getOperand(0),
Op1C-getOperand(0),
I.getName());
@@ -3059,9 +3061,10 @@
// fold (xor (cast A), (cast B)) - (cast (xor A, B))
if (CastInst *Op0C = dyn_castCastInst(Op0)) {
+const Type *SrcTy = Op0C-getOperand(0)-getType();
if (CastInst *Op1C = dyn_castCastInst(Op1))
- if (Op0C-getOperand(0)-getType() == Op1C-getOperand(0)-getType()
- Op0C-getOperand(0)-getType()-isIntegral()) {
+ if (SrcTy == Op1C-getOperand(0)-getType() SrcTy-isIntegral()
+ !SrcTy-isLosslesslyConvertibleTo(Op0C-getType())) {
Instruction *NewOp = BinaryOperator::createXor(Op0C-getOperand(0),
Op1C-getOperand(0),
I.getName());
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.234 - 1.235
---
Log message:
More aggressively sink GEP offsets into loops. For example, before we
generated:
movl 8(%esp), %eax
movl %eax, %edx
addl $4316, %edx
cmpb $1, %cl
ja LBB1_2 #cond_false
LBB1_1: #cond_true
movl L_QuantizationTables720$non_lazy_ptr, %ecx
movl %ecx, (%edx)
movl L_QNOtoQuantTableShift720$non_lazy_ptr, %edx
movl %edx, 4460(%eax)
ret
...
Now we generate:
movl 8(%esp), %eax
cmpb $1, %cl
ja LBB1_2 #cond_false
LBB1_1: #cond_true
movl L_QuantizationTables720$non_lazy_ptr, %ecx
movl %ecx, 4316(%eax)
movl L_QNOtoQuantTableShift720$non_lazy_ptr, %ecx
movl %ecx, 4460(%eax)
ret
... which uses one fewer register.
---
Diffs of the changes: (+115 -56)
SelectionDAGISel.cpp | 171 ++-
1 files changed, 115 insertions(+), 56 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.234
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.235
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.234Thu May 4
20:04:50 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri May 5 16:17:49 2006
@@ -2733,45 +2733,18 @@
}
-/// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
-/// casting to the type of GEPI.
-static Value *InsertGEPComputeCode(Value *V, BasicBlock *BB, Instruction
*GEPI,
- Value *Ptr, Value *PtrOffset) {
- if (V) return V; // Already computed.
-
- BasicBlock::iterator InsertPt;
- if (BB == GEPI-getParent()) {
-// If insert into the GEP's block, insert right after the GEP.
-InsertPt = GEPI;
-++InsertPt;
- } else {
-// Otherwise, insert at the top of BB, after any PHI nodes
-InsertPt = BB-begin();
-while (isaPHINode(InsertPt)) ++InsertPt;
- }
-
- // If Ptr is itself a cast, but in some other BB, emit a copy of the cast
into
- // BB so that there is only one value live across basic blocks (the cast
- // operand).
- if (CastInst *CI = dyn_castCastInst(Ptr))
-if (CI-getParent() != BB
isaPointerType(CI-getOperand(0)-getType()))
- Ptr = new CastInst(CI-getOperand(0), CI-getType(), , InsertPt);
-
- // Add the offset, cast it to the right type.
- Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, , InsertPt);
- Ptr = new CastInst(Ptr, GEPI-getType(), , InsertPt);
- return V = Ptr;
-}
-
/// OptimizeNoopCopyExpression - We have determined that the specified cast
/// instruction is a noop copy (e.g. it's casting from one pointer type to
/// another, int-uint, or int-sbyte on PPC.
-static void OptimizeNoopCopyExpression(CastInst *CI) {
+///
+/// Return true if any changes are made.
+static bool OptimizeNoopCopyExpression(CastInst *CI) {
BasicBlock *DefBB = CI-getParent();
/// InsertedCasts - Only insert a cast in each block once.
std::mapBasicBlock*, CastInst* InsertedCasts;
+ bool MadeChange = false;
for (Value::use_iterator UI = CI-use_begin(), E = CI-use_end();
UI != E; ) {
Use TheUse = UI.getUse();
@@ -2800,20 +2773,103 @@
InsertedCast =
new CastInst(CI-getOperand(0), CI-getType(), , InsertPt);
+ MadeChange = true;
}
// Replace a use of the cast with a use of the new casat.
TheUse = InsertedCast;
}
+
+ // If we removed all uses, nuke the cast.
+ if (CI-use_empty())
+CI-eraseFromParent();
+
+ return MadeChange;
}
+/// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
+/// casting to the type of GEPI.
+static Value *InsertGEPComputeCode(Value *V, BasicBlock *BB, Instruction
*GEPI,
+ Value *Ptr, Value *PtrOffset) {
+ if (V) return V; // Already computed.
+
+ BasicBlock::iterator InsertPt;
+ if (BB == GEPI-getParent()) {
+// If insert into the GEP's block, insert right after the GEP.
+InsertPt = GEPI;
+++InsertPt;
+ } else {
+// Otherwise, insert at the top of BB, after any PHI nodes
+InsertPt = BB-begin();
+while (isaPHINode(InsertPt)) ++InsertPt;
+ }
+
+ // If Ptr is itself a cast, but in some other BB, emit a copy of the cast
into
+ // BB so that there is only one value live across basic blocks (the cast
+ // operand).
+ if (CastInst *CI = dyn_castCastInst(Ptr))
+if (CI-getParent() != BB
isaPointerType(CI-getOperand(0)-getType()))
+ Ptr = new CastInst(CI-getOperand(0), CI-getType(), , InsertPt);
+
+ // Add the offset, cast it to the right type.
+ Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, , InsertPt);
+ Ptr = new CastInst(Ptr, GEPI-getType(), , InsertPt);
+ return V = Ptr;
+}
+
+/// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to
+/// compute its
[llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp
Changes in directory llvm/lib/CodeGen:
AsmPrinter.cpp updated: 1.66 - 1.67
---
Log message:
Indent multiline asm strings more nicely
---
Diffs of the changes: (+9 -5)
AsmPrinter.cpp | 14 +-
1 files changed, 9 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/AsmPrinter.cpp
diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.66
llvm/lib/CodeGen/AsmPrinter.cpp:1.67
--- llvm/lib/CodeGen/AsmPrinter.cpp:1.66Tue May 2 20:29:56 2006
+++ llvm/lib/CodeGen/AsmPrinter.cpp Fri May 5 16:47:05 2006
@@ -34,8 +34,8 @@
GlobalVarAddrSuffix(),
FunctionAddrPrefix(),
FunctionAddrSuffix(),
- InlineAsmStart(#APP\n\t),
- InlineAsmEnd(\t#NO_APP\n),
+ InlineAsmStart(#APP),
+ InlineAsmEnd(#NO_APP),
ZeroDirective(\t.zero\t),
ZeroDirectiveSuffix(0),
AsciiDirective(\t.ascii\t),
@@ -558,7 +558,7 @@
/// printInlineAsm - This method formats and prints the specified machine
/// instruction that is an inline asm.
void AsmPrinter::printInlineAsm(const MachineInstr *MI) const {
- O InlineAsmStart;
+ O InlineAsmStart \n\t;
unsigned NumOperands = MI-getNumOperands();
// Count the number of register definitions.
@@ -583,13 +583,17 @@
// Not a special case, emit the string section literally.
const char *LiteralEnd = LastEmitted+1;
while (*LiteralEnd *LiteralEnd != '{' *LiteralEnd != '|'
- *LiteralEnd != '}' *LiteralEnd != '$')
+ *LiteralEnd != '}' *LiteralEnd != '$' *LiteralEnd != '\n')
++LiteralEnd;
if (CurVariant == -1 || CurVariant == AsmPrinterVariant)
O.write(LastEmitted, LiteralEnd-LastEmitted);
LastEmitted = LiteralEnd;
break;
}
+case '\n':
+ ++LastEmitted; // Consume newline character.
+ O \n\t; // Indent code with newline.
+ break;
case '$': {
++LastEmitted; // Consume '$' character.
if (*LastEmitted == '$') { // $$ - $
@@ -707,7 +711,7 @@
break;
}
}
- O \n InlineAsmEnd;
+ O \n\t InlineAsmEnd \n;
}
/// PrintAsmOperand - Print the specified operand of MI, an INLINEASM
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[llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp
Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.177 - 1.178 --- Log message: Print *some* grouping around inline asm blocks so we know where they are. --- Diffs of the changes: (+2 -1) X86AsmPrinter.cpp |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.177 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.178 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.177 Thu May 4 11:19:27 2006 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Fri May 5 16:48:50 2006 @@ -66,7 +66,8 @@ forDarwin = true; StaticCtorsSection = .mod_init_func; StaticDtorsSection = .mod_term_func; -InlineAsmStart = InlineAsmEnd = ; // Don't use #APP/#NO_APP +InlineAsmStart = # InlineAsm Start; +InlineAsmEnd = # InlineAsm End; break; case X86Subtarget::isCygwin: GlobalPrefix = _; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCAsmPrinter.cpp updated: 1.171 - 1.172
---
Log message:
Print a grouping around inline asm blocks so that we can tell when we are
using them.
---
Diffs of the changes: (+2 -1)
PPCAsmPrinter.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.171
llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.172
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.171 Thu May 4 13:05:43 2006
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Fri May 5 16:50:04 2006
@@ -282,7 +282,8 @@
LCOMMDirective = \t.lcomm\t;
StaticCtorsSection = .mod_init_func;
StaticDtorsSection = .mod_term_func;
- InlineAsmStart = InlineAsmEnd = ; // Don't use #APP/#NO_APP
+ InlineAsmStart = # InlineAsm Start;
+ InlineAsmEnd = # InlineAsm End;
}
virtual const char *getPassName() const {
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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.54 - 1.55
---
Log message:
Implement ComputeMaskedBits/SimplifyDemandedBits for ISD::TRUNCATE
---
Diffs of the changes: (+18 -0)
TargetLowering.cpp | 18 ++
1 files changed, 18 insertions(+)
Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.54
llvm/lib/Target/TargetLowering.cpp:1.55
--- llvm/lib/Target/TargetLowering.cpp:1.54 Tue May 2 20:29:56 2006
+++ llvm/lib/Target/TargetLowering.cpp Fri May 5 17:32:12 2006
@@ -607,6 +607,16 @@
assert((KnownZero KnownOne) == 0 Bits known to be one AND zero?);
break;
}
+ case ISD::TRUNCATE: {
+if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask,
+ KnownZero, KnownOne, TLO, Depth+1))
+ return true;
+assert((KnownZero KnownOne) == 0 Bits known to be one AND zero?);
+uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
+KnownZero = OutMask;
+KnownOne = OutMask;
+break;
+ }
case ISD::AssertZext: {
MVT::ValueType VT = castVTSDNode(Op.getOperand(1))-getVT();
uint64_t InMask = MVT::getIntVTBitMask(VT);
@@ -864,6 +874,14 @@
KnownZero, KnownOne, Depth+1);
return;
}
+ case ISD::TRUNCATE: {
+ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
+assert((KnownZero KnownOne) == 0 Bits known to be one AND zero?);
+uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
+KnownZero = OutMask;
+KnownOne = OutMask;
+break;
+ }
case ISD::AssertZext: {
MVT::ValueType VT = castVTSDNode(Op.getOperand(1))-getVT();
uint64_t InMask = MVT::getIntVTBitMask(VT);
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.157 - 1.158
---
Log message:
Shrink shifts when possible.
---
Diffs of the changes: (+12 -0)
DAGCombiner.cpp | 12
1 files changed, 12 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.157
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.158
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.157 Fri May 5 16:34:35 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri May 5 17:53:17 2006
@@ -1615,6 +1615,18 @@
DAG.getConstant(c1 + c2, N1.getValueType()));
}
+ // fold (srl (anyextend x), c) - (anyextend (srl x, c))
+ if (N1C N0.getOpcode() == ISD::ANY_EXTEND) {
+// Shifting in all undef bits?
+MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
+if (N1C-getValue() = MVT::getSizeInBits(SmallVT))
+ return DAG.getNode(ISD::UNDEF, VT);
+
+SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0),
N1);
+AddToWorkList(SmallShift.Val);
+return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
+ }
+
// fold (srl (ctlz x), 5) - x iff x has one bit set (the low bit).
if (N1C N0.getOpcode() == ISD::CTLZ
N1C-getValue() == Log2_32(MVT::getSizeInBits(VT))) {
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.158 - 1.159
---
Log message:
Fold trunc(any_ext). This gives stuff like:
27,28c27
movzwl %di, %edi
movl %edi, %ebx
---
movw %di, %bx
---
Diffs of the changes: (+2 -1)
DAGCombiner.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.158
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.159
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.158 Fri May 5 17:53:17 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri May 5 17:56:26 2006
@@ -2005,7 +2005,8 @@
if (N0.getOpcode() == ISD::TRUNCATE)
return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
// fold (truncate (ext x)) - (ext x) or (truncate x) or x
- if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() ==
ISD::SIGN_EXTEND){
+ if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() ==
ISD::SIGN_EXTEND||
+ N0.getOpcode() == ISD::ANY_EXTEND) {
if (N0.getValueType() VT)
// if the source is smaller than the dest, we still need an extend
return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
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[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.55 - 1.56
---
Log message:
Fold (trunc (srl x, c)) - (srl (trunc x), c)
---
Diffs of the changes: (+32 -0)
TargetLowering.cpp | 32
1 files changed, 32 insertions(+)
Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.55
llvm/lib/Target/TargetLowering.cpp:1.56
--- llvm/lib/Target/TargetLowering.cpp:1.55 Fri May 5 17:32:12 2006
+++ llvm/lib/Target/TargetLowering.cpp Fri May 5 19:11:52 2006
@@ -608,9 +608,41 @@
break;
}
case ISD::TRUNCATE: {
+// Simplify the input, using demanded bit information, and compute the
known
+// zero/one bits live out.
if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask,
KnownZero, KnownOne, TLO, Depth+1))
return true;
+
+// If the input is only used by this truncate, see if we can shrink it
based
+// on the known demanded bits.
+if (Op.getOperand(0).Val-hasOneUse()) {
+ SDOperand In = Op.getOperand(0);
+ switch (In.getOpcode()) {
+ default: break;
+ case ISD::SRL:
+// Shrink SRL by a constant if none of the high bits shifted in are
+// demanded.
+if (ConstantSDNode *ShAmt =
dyn_castConstantSDNode(In.getOperand(1))){
+ uint64_t HighBits = MVT::getIntVTBitMask(In.getValueType());
+ HighBits = ~MVT::getIntVTBitMask(Op.getValueType());
+ HighBits = ShAmt-getValue();
+
+ if (ShAmt-getValue() MVT::getSizeInBits(Op.getValueType())
+ (DemandedMask HighBits) == 0) {
+// None of the shifted in bits are needed. Add a truncate of the
+// shift input, then shift it.
+SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
+ Op.getValueType(),
+ In.getOperand(0));
+return TLO.CombineTo(Op,
TLO.DAG.getNode(ISD::SRL,Op.getValueType(),
+ NewTrunc,
In.getOperand(1)));
+ }
+}
+break;
+ }
+}
+
assert((KnownZero KnownOne) == 0 Bits known to be one AND zero?);
uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
KnownZero = OutMask;
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.199 - 1.200 --- Log message: Teach the X86 backend about non-i32 inline asm register classes. --- Diffs of the changes: (+25 -5) X86ISelLowering.cpp | 30 +- 1 files changed, 25 insertions(+), 5 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.199 llvm/lib/Target/X86/X86ISelLowering.cpp:1.200 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.199 Fri May 5 16:35:18 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri May 5 19:29:37 2006 @@ -3998,14 +3998,34 @@ default: break; // Unknown constriant letter case 'r': // GENERAL_REGS case 'R': // LEGACY_REGS - return make_vectorunsigned(X86::EAX, X86::EBX, X86::ECX, X86::EDX, - X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0); + if (VT == MVT::i32) +return make_vectorunsigned(X86::EAX, X86::EDX, X86::ECX, X86::EBX, + X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0); + else if (VT == MVT::i16) +return make_vectorunsigned(X86::AX, X86::DX, X86::CX, X86::BX, + X86::SI, X86::DI, X86::BP, X86::SP, 0); + else if (VT == MVT::i8) +return make_vectorunsigned(X86::AL, X86::DL, X86::CL, X86::DL, 0); + break; case 'l': // INDEX_REGS - return make_vectorunsigned(X86::EAX, X86::EBX, X86::ECX, X86::EDX, - X86::ESI, X86::EDI, X86::EBP, 0); + if (VT == MVT::i32) +return make_vectorunsigned(X86::EAX, X86::EDX, X86::ECX, X86::EBX, + X86::ESI, X86::EDI, X86::EBP, 0); + else if (VT == MVT::i16) +return make_vectorunsigned(X86::AX, X86::DX, X86::CX, X86::BX, + X86::SI, X86::DI, X86::BP, 0); + else if (VT == MVT::i8) +return make_vectorunsigned(X86::AL, X86::DL, X86::CL, X86::DL, 0); + break; case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode) case 'Q': // Q_REGS - return make_vectorunsigned(X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0); + if (VT == MVT::i32) +return make_vectorunsigned(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); + else if (VT == MVT::i16) +return make_vectorunsigned(X86::AX, X86::DX, X86::CX, X86::BX, 0); + else if (VT == MVT::i8) +return make_vectorunsigned(X86::AL, X86::DL, X86::CL, X86::DL, 0); +break; case 'x': // SSE_REGS if SSE1 allowed if (Subtarget-hasSSE1()) return make_vectorunsigned(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
