[llvm-commits] CVS: nightlytest-serverside/index.php
Changes in directory nightlytest-serverside: index.php updated: 1.6 - 1.7 --- Log message: testing email script --- Diffs of the changes: (+0 -1) index.php |1 - 1 files changed, 1 deletion(-) Index: nightlytest-serverside/index.php diff -u nightlytest-serverside/index.php:1.6 nightlytest-serverside/index.php:1.7 --- nightlytest-serverside/index.php:1.6Thu Jul 6 13:35:06 2006 +++ nightlytest-serverside/index.phpMon Jul 10 13:13:04 2006 @@ -94,6 +94,5 @@ /td /tr /table - /body /html \ No newline at end of file ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/NewNightlyTest.pl
Changes in directory llvm/utils: NewNightlyTest.pl updated: 1.8 - 1.9 --- Log message: Fixed some output issues where newlines were not being printed after error messages --- Diffs of the changes: (+4 -3) NewNightlyTest.pl |7 --- 1 files changed, 4 insertions(+), 3 deletions(-) Index: llvm/utils/NewNightlyTest.pl diff -u llvm/utils/NewNightlyTest.pl:1.8 llvm/utils/NewNightlyTest.pl:1.9 --- llvm/utils/NewNightlyTest.pl:1.8Mon Jul 10 11:36:19 2006 +++ llvm/utils/NewNightlyTest.plMon Jul 10 13:35:41 2006 @@ -281,7 +281,7 @@ $/ = '\n'; return $Ret; } else { - print Could not open file '$_[0]' for reading!; + print Could not open file '$_[0]' for reading!\n; return ; } } @@ -289,7 +289,7 @@ #~ #~ sub WriteFile { # (filename, contents) -open (FILE, $_[0]) or die Could not open file '$_[0]' for writing!; +open (FILE, $_[0]) or die Could not open file '$_[0]' for writing!\n; print FILE $_[1]; close FILE; } @@ -429,7 +429,8 @@ my $sentdata=; foreach $x (keys (%$variables)){ -$sentdata.= $x = $hash_of_data{$x}\n; +$value = $variables-{$x}; +$sentdata.= $x = $value\n; } WriteFile $Prefix-sentdata.txt, $sentdata; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.494 - 1.495 --- Log message: Make instcombine not remove Phi nodes when LCSSA is live. --- Diffs of the changes: (+50 -46) InstructionCombining.cpp | 96 --- 1 files changed, 50 insertions(+), 46 deletions(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.494 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.495 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.494 Wed Jun 28 17:08:15 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Mon Jul 10 14:03:49 2006 @@ -96,6 +96,7 @@ virtual void getAnalysisUsage(AnalysisUsage AU) const { AU.addRequiredTargetData(); + AU.addPreservedID(LCSSAID); AU.setPreservesCFG(); } @@ -6251,56 +6252,59 @@ // PHINode simplification // Instruction *InstCombiner::visitPHINode(PHINode PN) { - if (Value *V = PN.hasConstantValue()) -return ReplaceInstUsesWith(PN, V); + // If LCSSA is around, don't nuke PHIs. + if (!mustPreserveAnalysisID(LCSSAID)) { +if (Value *V = PN.hasConstantValue()) + return ReplaceInstUsesWith(PN, V); + +// If the only user of this instruction is a cast instruction, and all of +//the incoming values are constants, change this PHI to merge together the +// casted constants. +if (PN.hasOneUse()) + if (CastInst *CI = dyn_castCastInst(PN.use_back())) +if (CI-getType() != PN.getType()) { // noop casts will be folded + bool AllConstant = true; + for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) +if (!isaConstant(PN.getIncomingValue(i))) { + AllConstant = false; + break; +} + if (AllConstant) { +// Make a new PHI with all casted values. +PHINode *New = new PHINode(CI-getType(), PN.getName(), PN); +for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) { + Constant *OldArg = castConstant(PN.getIncomingValue(i)); + New-addIncoming(ConstantExpr::getCast(OldArg, New-getType()), + PN.getIncomingBlock(i)); +} - // If the only user of this instruction is a cast instruction, and all of the - // incoming values are constants, change this PHI to merge together the casted - // constants. - if (PN.hasOneUse()) -if (CastInst *CI = dyn_castCastInst(PN.use_back())) - if (CI-getType() != PN.getType()) { // noop casts will be folded -bool AllConstant = true; -for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) - if (!isaConstant(PN.getIncomingValue(i))) { -AllConstant = false; -break; +// Update the cast instruction. +CI-setOperand(0, New); +WorkList.push_back(CI);// revisit the cast instruction to fold. +WorkList.push_back(New); // Make sure to revisit the new Phi +return PN;// PN is now dead! } -if (AllConstant) { - // Make a new PHI with all casted values. - PHINode *New = new PHINode(CI-getType(), PN.getName(), PN); - for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) { -Constant *OldArg = castConstant(PN.getIncomingValue(i)); -New-addIncoming(ConstantExpr::getCast(OldArg, New-getType()), - PN.getIncomingBlock(i)); - } - - // Update the cast instruction. - CI-setOperand(0, New); - WorkList.push_back(CI);// revisit the cast instruction to fold. - WorkList.push_back(New); // Make sure to revisit the new Phi - return PN;// PN is now dead! } - } - - // If all PHI operands are the same operation, pull them through the PHI, - // reducing code size. - if (isaInstruction(PN.getIncomingValue(0)) - PN.getIncomingValue(0)-hasOneUse()) -if (Instruction *Result = FoldPHIArgOpIntoPHI(PN)) - return Result; - - // If this is a trivial cycle in the PHI node graph, remove it. Basically, if - // this PHI only has a single use (a PHI), and if that PHI only has one use (a - // PHI)... break the cycle. - if (PN.hasOneUse()) -if (PHINode *PU = dyn_castPHINode(PN.use_back())) { - std::setPHINode* PotentiallyDeadPHIs; - PotentiallyDeadPHIs.insert(PN); - if (DeadPHICycle(PU, PotentiallyDeadPHIs)) -return ReplaceInstUsesWith(PN, UndefValue::get(PN.getType())); -} +// If all PHI operands are the same operation, pull them through the PHI, +// reducing code size. +if (isaInstruction(PN.getIncomingValue(0)) +PN.getIncomingValue(0)-hasOneUse()) + if (Instruction *Result = FoldPHIArgOpIntoPHI(PN)) +return Result; + +// If this is a trivial
[llvm-commits] CVS: nightlytest-serverside/machine.php
Changes in directory nightlytest-serverside: machine.php updated: 1.2 - 1.3 --- Log message: fixed a problem where trying to generate a graph of configure cpu time from the machine page produced a cvs checkout cpu graph. --- Diffs of the changes: (+1 -1) machine.php |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: nightlytest-serverside/machine.php diff -u nightlytest-serverside/machine.php:1.2 nightlytest-serverside/machine.php:1.3 --- nightlytest-serverside/machine.php:1.2 Fri Jul 7 19:32:18 2006 +++ nightlytest-serverside/machine.php Mon Jul 10 14:27:51 2006 @@ -138,7 +138,7 @@ echo /td; echo td align=center; echo Configure time cpu; - print brinput type=checkbox name=\measure[]\ value=\getcvstime_cpu\\n; + print brinput type=checkbox name=\measure[]\ value=\configuretime_cpu\\n; echo /td; echo td align=center; echo Configure time wall; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: nightlytest-serverside/machines/
Changes in directory nightlytest-serverside/machines: --- Log message: Directory /var/cvs/llvm/nightlytest-serverside/machines added to the repository --- Diffs of the changes: (+0 -0) 0 files changed ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.233 - 1.234 --- Log message: Mark internal function static --- Diffs of the changes: (+1 -1) X86ISelLowering.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.233 llvm/lib/Target/X86/X86ISelLowering.cpp:1.234 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.233 Fri Jul 7 03:33:52 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Jul 10 14:53:12 2006 @@ -4056,7 +4056,7 @@ return false; } -bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI) { +static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI) { GlobalValue *GV; int64_t Offset; if (isGAPlusOffset(Base, GV, Offset)) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/bswap.ll
Changes in directory llvm/test/Regression/Transforms/InstCombine: bswap.ll updated: 1.1 - 1.2 --- Log message: Add tests for 16-bit byteswaps. --- Diffs of the changes: (+15 -1) bswap.ll | 16 +++- 1 files changed, 15 insertions(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/InstCombine/bswap.ll diff -u llvm/test/Regression/Transforms/InstCombine/bswap.ll:1.1 llvm/test/Regression/Transforms/InstCombine/bswap.ll:1.2 --- llvm/test/Regression/Transforms/InstCombine/bswap.ll:1.1Thu Jun 15 14:06:42 2006 +++ llvm/test/Regression/Transforms/InstCombine/bswap.llMon Jul 10 15:25:01 2006 @@ -1,4 +1,4 @@ -; RUN: llvm-as %s | opt -instcombine | llvm-dis | grep 'call.*llvm.bswap' | wc -l | grep 2 +; RUN: llvm-as %s | opt -instcombine | llvm-dis | grep 'call.*llvm.bswap' | wc -l | grep 4 uint %test1(uint %i) { %tmp1 = shr uint %i, ubyte 24 ; uint [#uses=1] @@ -26,3 +26,17 @@ ret uint %tmp14 } +ushort %test3(ushort %s) { +%tmp2 = shr ushort %s, ubyte 8 +%tmp4 = shl ushort %s, ubyte 8 +%tmp5 = or ushort %tmp2, %tmp4 + ret ushort %tmp5 +} + +ushort %test4(ushort %s) { +%tmp2 = shr ushort %s, ubyte 8 +%tmp4 = shl ushort %s, ubyte 8 +%tmp5 = or ushort %tmp4, %tmp2 + ret ushort %tmp5 +} + ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.495 - 1.496 --- Log message: Recognize 16-bit bswaps by relaxing overconstrained pattern. This implements Transforms/InstCombine/bswap.ll:test[34]. --- Diffs of the changes: (+5 -2) InstructionCombining.cpp |7 +-- 1 files changed, 5 insertions(+), 2 deletions(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.495 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.496 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.495 Mon Jul 10 14:03:49 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Mon Jul 10 15:25:24 2006 @@ -2976,9 +2976,12 @@ if (A == Op0 || B == Op0)// A | (A ?) -- A return ReplaceInstUsesWith(I, Op0); - // (A | B) | C and A | (B | C) - bswap if possible. + // (A | B) | C and A | (B | C) - bswap if possible. + // (A B) | (C D) and (A B) | (B C) - bswap if possible. if (match(Op0, m_Or(m_Value(), m_Value())) || - match(Op1, m_Or(m_Value(), m_Value( { + match(Op1, m_Or(m_Value(), m_Value())) || + (match(Op0, m_Shift(m_Value(), m_Value())) + match(Op1, m_Shift(m_Value(), m_Value() { if (Instruction *BSwap = MatchBSwap(I)) return BSwap; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/bswap-load-store.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC: bswap-load-store.ll added (r1.1) --- Log message: New testcase for folding bswaps into i16/i32 loads and stores. --- Diffs of the changes: (+42 -0) bswap-load-store.ll | 42 ++ 1 files changed, 42 insertions(+) Index: llvm/test/Regression/CodeGen/PowerPC/bswap-load-store.ll diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/bswap-load-store.ll:1.1 *** /dev/null Mon Jul 10 15:54:03 2006 --- llvm/test/Regression/CodeGen/PowerPC/bswap-load-store.llMon Jul 10 15:53:53 2006 *** *** 0 --- 1,42 + ; RUN: llvm-as %s | llc -march=ppc32 | grep 'stwbrx\|lwbrx\|sthbrx\|lhbrx' | wc -l | grep 4 + ; RUN: llvm-as %s | llc -march=ppc32 | not grep rlwinm + ; RUN: llvm-as %s | llc -march=ppc32 | not grep rlwimi + ; RUN: llvm-as %s | llc -march=ppc64 | grep 'stwbrx\|lwbrx\|sthbrx\|lhbrx' | wc -l | grep 4 + ; RUN: llvm-as %s | llc -march=ppc64 | not grep rlwinm + ; RUN: llvm-as %s | llc -march=ppc64 | not grep rlwimi + + void %STWBRX(uint %i, sbyte* %ptr, int %off) { + %tmp1 = getelementptr sbyte* %ptr, int %off + %tmp1 = cast sbyte* %tmp1 to uint* + %tmp13 = tail call uint %llvm.bswap.i32(uint %i) + store uint %tmp13, uint* %tmp1 + ret void + } + + uint %LWBRX(sbyte* %ptr, int %off) { + %tmp1 = getelementptr sbyte* %ptr, int %off + %tmp1 = cast sbyte* %tmp1 to uint* + %tmp = load uint* %tmp1 + %tmp14 = tail call uint %llvm.bswap.i32( uint %tmp ) + ret uint %tmp14 + } + + void %STHBRX(ushort %s, sbyte* %ptr, int %off) { + %tmp1 = getelementptr sbyte* %ptr, int %off + %tmp1 = cast sbyte* %tmp1 to ushort* + %tmp5 = call ushort %llvm.bswap.i16( ushort %s ) + store ushort %tmp5, ushort* %tmp1 + ret void + } + + ushort %LHBRX(sbyte* %ptr, int %off) { + %tmp1 = getelementptr sbyte* %ptr, int %off + %tmp1 = cast sbyte* %tmp1 to ushort* + %tmp = load ushort* %tmp1 + %tmp6 = call ushort %llvm.bswap.i16(ushort %tmp) + ret ushort %tmp6 + } + + declare uint %llvm.bswap.i32(uint) + + declare ushort %llvm.bswap.i16(ushort) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt PPCInstrInfo.td PPCISelLowering.cpp PPCISelLowering.h PPCHazardRecognizers.cpp
Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.92 - 1.93 PPCInstrInfo.td updated: 1.237 - 1.238 PPCISelLowering.cpp updated: 1.197 - 1.198 PPCISelLowering.h updated: 1.50 - 1.51 PPCHazardRecognizers.cpp updated: 1.12 - 1.13 --- Log message: Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswaps into i16/i32 load/stores. --- Diffs of the changes: (+103 -6) PPCHazardRecognizers.cpp |4 +++ PPCISelLowering.cpp | 59 +++ PPCISelLowering.h| 14 ++- PPCInstrInfo.td | 27 + README.txt |5 --- 5 files changed, 103 insertions(+), 6 deletions(-) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.92 llvm/lib/Target/PowerPC/README.txt:1.93 --- llvm/lib/Target/PowerPC/README.txt:1.92 Wed May 17 14:02:25 2006 +++ llvm/lib/Target/PowerPC/README.txt Mon Jul 10 15:56:58 2006 @@ -3,7 +3,6 @@ TODO: * gpr0 allocation * implement do-loop - bdnz transform -* implement powerpc-64 for darwin ===-=== @@ -238,10 +237,6 @@ ===-=== -Generate lwbrx and other byteswapping load/store instructions when reasonable. - -===-=== - Compile this: int foo(int a) { Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.237 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.238 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.237 Tue Jun 27 13:36:44 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Mon Jul 10 15:56:58 2006 @@ -37,6 +37,13 @@ SDTCisVT1, i32, SDTCisVT2, OtherVT ]; +def SDT_PPClbrx : SDTypeProfile1, 3, [ + SDTCisVT0, i32, SDTCisPtrTy1, SDTCisVT2, OtherVT, SDTCisVT3, OtherVT +]; +def SDT_PPCstbrx : SDTypeProfile0, 4, [ + SDTCisVT0, i32, SDTCisPtrTy1, SDTCisVT2, OtherVT, SDTCisVT3, OtherVT +]; + //===--===// // PowerPC specific DAG Nodes. // @@ -88,6 +95,9 @@ def PPCcondbranch : SDNodePPCISD::COND_BRANCH, SDT_PPCcondbr, [SDNPHasChain, SDNPOptInFlag]; +def PPClbrx : SDNodePPCISD::LBRX, SDT_PPClbrx, [SDNPHasChain]; +def PPCstbrx : SDNodePPCISD::STBRX, SDT_PPCstbrx, [SDNPHasChain]; + //===--===// // PowerPC specific transformation functions and pattern fragments. // @@ -464,6 +474,15 @@ def LWZX : XForm_131, 23, (ops GPRC:$rD, memrr:$src), lwzx $rD, $src, LdStGeneral, [(set GPRC:$rD, (load xaddr:$src))]; + + +def LHBRX : XForm_131, 790, (ops GPRC:$rD, memrr:$src), + lhbrx $rD, $src, LdStGeneral, + [(set GPRC:$rD, (PPClbrx xaddr:$src,srcvalue:$dummy, i16))]; +def LWBRX : XForm_131, 534, (ops GPRC:$rD, memrr:$src), + lwbrx $rD, $src, LdStGeneral, + [(set GPRC:$rD, (PPClbrx xaddr:$src,srcvalue:$dummy, i32))]; + } let PPC970_Unit = 1 in { // FXU Operations. @@ -517,6 +536,14 @@ def STWUX : XForm_831, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB), stwux $rS, $rA, $rB, LdStGeneral, []; +def STHBRX: XForm_831, 918, (ops GPRC:$rS, memrr:$dst), + sthbrx $rS, $dst, LdStGeneral, + [(PPCstbrx GPRC:$rS, xaddr:$dst, srcvalue:$dummy, i16)], + PPC970_DGroup_Cracked; +def STWBRX: XForm_831, 662, (ops GPRC:$rS, memrr:$dst), + stwbrx $rS, $dst, LdStGeneral, + [(PPCstbrx GPRC:$rS, xaddr:$dst, srcvalue:$dummy, i32)], + PPC970_DGroup_Cracked; } let PPC970_Unit = 1 in { // FXU Operations. def SRAWI : XForm_1031, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH), Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.197 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.198 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.197 Tue Jun 27 15:14:52 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Jul 10 15:56:58 2006 @@ -266,6 +266,7 @@ setTargetDAGCombine(ISD::SINT_TO_FP); setTargetDAGCombine(ISD::STORE); setTargetDAGCombine(ISD::BR_CC); + setTargetDAGCombine(ISD::BSWAP); computeRegisterProperties(); } @@ -296,6 +297,8 @@ case PPCISD::MFCR: return PPCISD::MFCR; case PPCISD::VCMP: return PPCISD::VCMP; case PPCISD::VCMPo: return PPCISD::VCMPo; + case PPCISD::LBRX: return PPCISD::LBRX; + case PPCISD::STBRX: return PPCISD::STBRX; case PPCISD::COND_BRANCH: return PPCISD::COND_BRANCH; } } @@ -2344,6 +2347,56 @@ DCI.AddToWorklist(Val.Val); return Val;
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.234 - 1.235 --- Log message: Fixed stack objects do not specify alignments, but their offsets are known. Use that information when doing the transformation to merge multiple loads into a 128-bit load. --- Diffs of the changes: (+12 -5) X86ISelLowering.cpp | 17 - 1 files changed, 12 insertions(+), 5 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.234 llvm/lib/Target/X86/X86ISelLowering.cpp:1.235 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.234 Mon Jul 10 14:53:12 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Jul 10 16:37:44 2006 @@ -4056,7 +4056,8 @@ return false; } -static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI) { +static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI, + const X86Subtarget *Subtarget) { GlobalValue *GV; int64_t Offset; if (isGAPlusOffset(Base, GV, Offset)) @@ -4064,7 +4065,12 @@ else { assert(Base-getOpcode() == ISD::FrameIndex Unexpected base node!); int BFI = dyn_castFrameIndexSDNode(Base)-getIndex(); -return MFI-getObjectAlignment(BFI) = 16; +if (BFI 0) + // Fixed objects do not specify alignment, however the offsets are known. + return ((Subtarget-getStackAlignment() % 16) == 0 + (MFI-getObjectOffset(BFI) % 16) == 0); +else + return MFI-getObjectAlignment(BFI) = 16; } return false; } @@ -4074,7 +4080,8 @@ /// build_vector load1, load2, load3, load4, 0, 1, 2, 3 into a 128-bit load /// if the load addresses are consecutive, non-overlapping, and in the right /// order. -static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG DAG) { +static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG DAG, + const X86Subtarget *Subtarget) { MachineFunction MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); MVT::ValueType VT = N-getValueType(0); @@ -4099,7 +4106,7 @@ } } - bool isAlign16 = isBaseAlignment16(Base-getOperand(1).Val, MFI); + bool isAlign16 = isBaseAlignment16(Base-getOperand(1).Val, MFI, Subtarget); if (isAlign16) return DAG.getLoad(VT, Base-getOperand(0), Base-getOperand(1), Base-getOperand(2)); @@ -4118,7 +4125,7 @@ switch (N-getOpcode()) { default: break; case ISD::VECTOR_SHUFFLE: -return PerformShuffleCombine(N, DAG); +return PerformShuffleCombine(N, DAG, Subtarget); } return SDOperand(); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/README-SSE.txt
Changes in directory llvm/lib/Target/X86: README-SSE.txt updated: 1.3 - 1.4 --- Log message: New entry. --- Diffs of the changes: (+3 -0) README-SSE.txt |3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/Target/X86/README-SSE.txt diff -u llvm/lib/Target/X86/README-SSE.txt:1.3 llvm/lib/Target/X86/README-SSE.txt:1.4 --- llvm/lib/Target/X86/README-SSE.txt:1.3 Wed Jun 14 16:26:18 2006 +++ llvm/lib/Target/X86/README-SSE.txt Mon Jul 10 16:42:16 2006 @@ -693,3 +693,6 @@ } //===-===// + +Apply the same transformation that merged four float into a single 128-bit load +to loads from constant pool. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/vec_shuffle-6.ll
Changes in directory llvm/test/Regression/CodeGen/X86: vec_shuffle-6.ll updated: 1.1 - 1.2 --- Log message: Update. --- Diffs of the changes: (+13 -3) vec_shuffle-6.ll | 16 +--- 1 files changed, 13 insertions(+), 3 deletions(-) Index: llvm/test/Regression/CodeGen/X86/vec_shuffle-6.ll diff -u llvm/test/Regression/CodeGen/X86/vec_shuffle-6.ll:1.1 llvm/test/Regression/CodeGen/X86/vec_shuffle-6.ll:1.2 --- llvm/test/Regression/CodeGen/X86/vec_shuffle-6.ll:1.1 Fri Jul 7 12:54:24 2006 +++ llvm/test/Regression/CodeGen/X86/vec_shuffle-6.ll Mon Jul 10 16:49:09 2006 @@ -1,4 +1,6 @@ -; RUN: llvm-as %s | llc -march=x86 -mattr=+sse2 | grep movups | wc -l | grep 3 +; RUN: llvm-as %s | llc -march=x86 -mattr=+sse2 | grep movapd | wc -l | grep 1 +; RUN: llvm-as %s | llc -march=x86 -mattr=+sse2 | grep movaps | wc -l | grep 1 +; RUN: llvm-as %s | llc -march=x86 -mattr=+sse2 | grep movups | wc -l | grep 2 %x = global [4 x int] [ int 1, int 2, int 3, int 4 ] @@ -15,7 +17,7 @@ ret 2 x long %tmp16 } -4 x float %test2(float %a, float %b, float %c, float %d) { +4 x float %test2(int %dummy, float %a, float %b, float %c, float %d) { %tmp = insertelement 4 x float undef, float %a, uint 0 %tmp11 = insertelement 4 x float %tmp, float %b, uint 1 %tmp12 = insertelement 4 x float %tmp11, float %c, uint 2 @@ -23,7 +25,15 @@ ret 4 x float %tmp13 } -2 x double %test3(double %a, double %b) { +4 x float %test3(float %a, float %b, float %c, float %d) { + %tmp = insertelement 4 x float undef, float %a, uint 0 + %tmp11 = insertelement 4 x float %tmp, float %b, uint 1 + %tmp12 = insertelement 4 x float %tmp11, float %c, uint 2 + %tmp13 = insertelement 4 x float %tmp12, float %d, uint 3 + ret 4 x float %tmp13 +} + +2 x double %test4(double %a, double %b) { %tmp = insertelement 2 x double undef, double %a, uint 0 %tmp7 = insertelement 2 x double %tmp, double %b, uint 1 ret 2 x double %tmp7 ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.496 - 1.497 --- Log message: Don't indent the entire function. --- Diffs of the changes: (+48 -49) InstructionCombining.cpp | 97 +++ 1 files changed, 48 insertions(+), 49 deletions(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.496 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.497 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.496 Mon Jul 10 15:25:24 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Mon Jul 10 17:03:18 2006 @@ -6255,59 +6255,58 @@ // PHINode simplification // Instruction *InstCombiner::visitPHINode(PHINode PN) { - // If LCSSA is around, don't nuke PHIs. - if (!mustPreserveAnalysisID(LCSSAID)) { -if (Value *V = PN.hasConstantValue()) - return ReplaceInstUsesWith(PN, V); - -// If the only user of this instruction is a cast instruction, and all of -//the incoming values are constants, change this PHI to merge together the -// casted constants. -if (PN.hasOneUse()) - if (CastInst *CI = dyn_castCastInst(PN.use_back())) -if (CI-getType() != PN.getType()) { // noop casts will be folded - bool AllConstant = true; - for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) -if (!isaConstant(PN.getIncomingValue(i))) { - AllConstant = false; - break; -} - if (AllConstant) { -// Make a new PHI with all casted values. -PHINode *New = new PHINode(CI-getType(), PN.getName(), PN); -for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) { - Constant *OldArg = castConstant(PN.getIncomingValue(i)); - New-addIncoming(ConstantExpr::getCast(OldArg, New-getType()), - PN.getIncomingBlock(i)); -} + if (mustPreservePassID(LCSSAID)) return 0; + + if (Value *V = PN.hasConstantValue()) +return ReplaceInstUsesWith(PN, V); -// Update the cast instruction. -CI-setOperand(0, New); -WorkList.push_back(CI);// revisit the cast instruction to fold. -WorkList.push_back(New); // Make sure to revisit the new Phi -return PN;// PN is now dead! + // If the only user of this instruction is a cast instruction, and all of the + // incoming values are constants, change this PHI to merge together the casted + // constants. + if (PN.hasOneUse()) +if (CastInst *CI = dyn_castCastInst(PN.use_back())) + if (CI-getType() != PN.getType()) { // noop casts will be folded +bool AllConstant = true; +for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) + if (!isaConstant(PN.getIncomingValue(i))) { +AllConstant = false; +break; + } +if (AllConstant) { + // Make a new PHI with all casted values. + PHINode *New = new PHINode(CI-getType(), PN.getName(), PN); + for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) { +Constant *OldArg = castConstant(PN.getIncomingValue(i)); +New-addIncoming(ConstantExpr::getCast(OldArg, New-getType()), + PN.getIncomingBlock(i)); } -} -// If all PHI operands are the same operation, pull them through the PHI, -// reducing code size. -if (isaInstruction(PN.getIncomingValue(0)) -PN.getIncomingValue(0)-hasOneUse()) - if (Instruction *Result = FoldPHIArgOpIntoPHI(PN)) -return Result; - -// If this is a trivial cycle in the PHI node graph, remove it. Basically, -// if this PHI only has a single use (a PHI), and if that PHI only has one -// use (a PHI)... break the cycle. -if (PN.hasOneUse()) - if (PHINode *PU = dyn_castPHINode(PN.use_back())) { -std::setPHINode* PotentiallyDeadPHIs; -PotentiallyDeadPHIs.insert(PN); -if (DeadPHICycle(PU, PotentiallyDeadPHIs)) - return ReplaceInstUsesWith(PN, UndefValue::get(PN.getType())); + // Update the cast instruction. + CI-setOperand(0, New); + WorkList.push_back(CI);// revisit the cast instruction to fold. + WorkList.push_back(New); // Make sure to revisit the new Phi + return PN;// PN is now dead! +} } - } - + + // If all PHI operands are the same operation, pull them through the PHI, + // reducing code size. + if (isaInstruction(PN.getIncomingValue(0)) + PN.getIncomingValue(0)-hasOneUse()) +if (Instruction *Result = FoldPHIArgOpIntoPHI(PN)) + return Result; + + // If this is a trivial cycle in the PHI node graph, remove it. Basically, if + // this PHI only has a single use (a PHI), and if that PHI only has one use
[llvm-commits] CVS: nightlytest-serverside/NightlyTestAccept.cgi
Changes in directory nightlytest-serverside: NightlyTestAccept.cgi updated: 1.10 - 1.11 --- Log message: Hopefully fixed the code that creates a file of the buildlog for each nightly test --- Diffs of the changes: (+9 -7) NightlyTestAccept.cgi | 16 +--- 1 files changed, 9 insertions(+), 7 deletions(-) Index: nightlytest-serverside/NightlyTestAccept.cgi diff -u nightlytest-serverside/NightlyTestAccept.cgi:1.10 nightlytest-serverside/NightlyTestAccept.cgi:1.11 --- nightlytest-serverside/NightlyTestAccept.cgi:1.10 Fri Jul 7 13:36:01 2006 +++ nightlytest-serverside/NightlyTestAccept.cgiMon Jul 10 17:25:32 2006 @@ -451,15 +451,17 @@ # writing logs to directory # ## +$curr=`pwd`; +chomp($curr); + if(! -d machines){ -mkdir machines, 0777 or print(couldnt create directory $base); -} -ChangeDir(machines, Moving into machines directory); +mkdir $curr/machines, 0777 or print(couldnt create directory $base); + } +ChangeDir($curr/machines, Moving into machines directory); if(! -d $machine_id){ -mkdir $machine_id, 0777 or print(couldnt create directory $machine_id because $!); -} -ChangeDir($machine_id, Moving into machine $machine_id 's directory); - +mkdir $curr/machines/$machine_id, 0777 or print(couldnt create directory $machine_id because $!); + } +ChangeDir($curr/machines/$machine_id, Moving into machine $machine_id 's directory); $db_date =~ s/ /\_/g; my $build_file = $db_date-Build-Log.txt; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.cpp updated: 1.22 - 1.23 PPCRegisterInfo.cpp updated: 1.71 - 1.72 PPCRegisterInfo.h updated: 1.15 - 1.16 --- Log message: In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones. --- Diffs of the changes: (+99 -62) PPCInstrInfo.cpp|3 - PPCRegisterInfo.cpp | 153 +++- PPCRegisterInfo.h |5 + 3 files changed, 99 insertions(+), 62 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.22 llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.23 --- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.22 Tue Jun 20 18:18:58 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.cppMon Jul 10 19:48:23 2006 @@ -19,7 +19,8 @@ using namespace llvm; PPCInstrInfo::PPCInstrInfo(PPCTargetMachine tm) - : TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])), TM(tm) {} + : TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])), TM(tm), +RI(*TM.getSubtargetImpl()) {} /// getPointerRegClass - Return the register class to use to hold pointers. /// This is used for addressing modes. Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.71 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.72 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.71Tue Jun 27 13:55:49 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Jul 10 19:48:23 2006 @@ -15,6 +15,7 @@ #include PPC.h #include PPCInstrBuilder.h #include PPCRegisterInfo.h +#include PPCSubtarget.h #include llvm/Constants.h #include llvm/Type.h #include llvm/CodeGen/ValueTypes.h @@ -78,8 +79,9 @@ } } -PPCRegisterInfo::PPCRegisterInfo() - : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) { +PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget ST) + : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), +Subtarget(ST) { ImmToIdxMap[PPC::LD] = PPC::LDX;ImmToIdxMap[PPC::STD] = PPC::STDX; ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; @@ -207,70 +209,103 @@ } const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const { - static const unsigned CalleeSaveRegs[] = { -PPC::R1, PPC::R13, -PPC::R14, PPC::R15, -PPC::R16, PPC::R17, -PPC::R18, PPC::R19, -PPC::R20, PPC::R21, -PPC::R22, PPC::R23, -PPC::R24, PPC::R25, -PPC::R26, PPC::R27, -PPC::R28, PPC::R29, -PPC::R30, PPC::R31, -PPC::F14, PPC::F15, -PPC::F16, PPC::F17, -PPC::F18, PPC::F19, -PPC::F20, PPC::F21, -PPC::F22, PPC::F23, -PPC::F24, PPC::F25, -PPC::F26, PPC::F27, -PPC::F28, PPC::F29, + // 32-bit Darwin calling convention. + static const unsigned Darwin32_CalleeSaveRegs[] = { +PPC::R1 , PPC::R13, PPC::R14, PPC::R15, +PPC::R16, PPC::R17, PPC::R18, PPC::R19, +PPC::R20, PPC::R21, PPC::R22, PPC::R23, +PPC::R24, PPC::R25, PPC::R26, PPC::R27, +PPC::R28, PPC::R29, PPC::R30, PPC::R31, + +PPC::F14, PPC::F15, PPC::F16, PPC::F17, +PPC::F18, PPC::F19, PPC::F20, PPC::F21, +PPC::F22, PPC::F23, PPC::F24, PPC::F25, +PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, -PPC::CR2, PPC::CR3, -PPC::CR4, PPC::V20, -PPC::V21, PPC::V22, -PPC::V23, PPC::V24, -PPC::V25, PPC::V26, -PPC::V27, PPC::V28, -PPC::V29, PPC::V30, -PPC::V31, PPC::LR, 0 + +PPC::CR2, PPC::CR3, PPC::CR4, +PPC::V20, PPC::V21, PPC::V22, PPC::V23, +PPC::V24, PPC::V25, PPC::V26, PPC::V27, +PPC::V28, PPC::V29, PPC::V30, PPC::V31, + +PPC::LR, 0 }; - return CalleeSaveRegs; + // 64-bit Darwin calling convention. + static const unsigned Darwin64_CalleeSaveRegs[] = { +PPC::X1 , PPC::X13, PPC::X14, PPC::X15, +PPC::X16, PPC::X17, PPC::X18, PPC::X19, +PPC::X20, PPC::X21, PPC::X22, PPC::X23, +PPC::X24, PPC::X25, PPC::X26, PPC::X27, +PPC::X28, PPC::X29, PPC::X30, PPC::X31, + +PPC::F14, PPC::F15, PPC::F16, PPC::F17, +PPC::F18, PPC::F19, PPC::F20, PPC::F21, +PPC::F22, PPC::F23, PPC::F24, PPC::F25, +PPC::F26, PPC::F27, PPC::F28, PPC::F29, +PPC::F30, PPC::F31, + +PPC::CR2, PPC::CR3, PPC::CR4, +PPC::V20, PPC::V21, PPC::V22, PPC::V23, +PPC::V24, PPC::V25, PPC::V26, PPC::V27, +PPC::V28, PPC::V29, PPC::V30, PPC::V31, + +PPC::LR, 0 + }; + + return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegs : + Darwin32_CalleeSaveRegs; } const TargetRegisterClass* const* PPCRegisterInfo::getCalleeSaveRegClasses() const { - static const TargetRegisterClass * const CalleeSaveRegClasses[] = { -PPC::GPRCRegClass, PPC::GPRCRegClass, -PPC::GPRCRegClass, PPC::GPRCRegClass, -PPC::GPRCRegClass, PPC::GPRCRegClass, -PPC::GPRCRegClass, PPC::GPRCRegClass, -PPC::GPRCRegClass, PPC::GPRCRegClass, -
[llvm-commits] CVS: llvm/utils/TableGen/CodeEmitterGen.cpp
Changes in directory llvm/utils/TableGen: CodeEmitterGen.cpp updated: 1.44 - 1.45 --- Log message: Reduce bloat in target libraries by removing per machine instruction assertion from code emitter generation. --- Diffs of the changes: (+1 -3) CodeEmitterGen.cpp |4 +--- 1 files changed, 1 insertion(+), 3 deletions(-) Index: llvm/utils/TableGen/CodeEmitterGen.cpp diff -u llvm/utils/TableGen/CodeEmitterGen.cpp:1.44 llvm/utils/TableGen/CodeEmitterGen.cpp:1.45 --- llvm/utils/TableGen/CodeEmitterGen.cpp:1.44 Fri Mar 17 18:40:36 2006 +++ llvm/utils/TableGen/CodeEmitterGen.cpp Mon Jul 10 20:25:59 2006 @@ -82,7 +82,6 @@ o unsigned Target.getName() CodeEmitter:: getBinaryCodeForInstr(MachineInstr MI) {\n unsigned Value = 0;\n - DEBUG(std::cerr MI);\n switch (MI.getOpcode()) {\n; // Emit a case statement for each opcode @@ -91,8 +90,7 @@ Record *R = *I; if (R-getName() == PHI || R-getName() == INLINEASM) continue; -o case Namespace R-getName() : {\n - DEBUG(std::cerr \Emitting R-getName() \\n\);\n; +o case Namespace R-getName() : {\n; BitsInit *BI = R-getValueAsBitsInit(Inst); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/2006-07-03-ASMFormalLowering.ll
Changes in directory llvm/test/Regression/CodeGen/Alpha: 2006-07-03-ASMFormalLowering.ll updated: 1.2 - 1.3 --- Log message: This is fixed --- Diffs of the changes: (+0 -1) 2006-07-03-ASMFormalLowering.ll |1 - 1 files changed, 1 deletion(-) Index: llvm/test/Regression/CodeGen/Alpha/2006-07-03-ASMFormalLowering.ll diff -u llvm/test/Regression/CodeGen/Alpha/2006-07-03-ASMFormalLowering.ll:1.2 llvm/test/Regression/CodeGen/Alpha/2006-07-03-ASMFormalLowering.ll:1.3 --- llvm/test/Regression/CodeGen/Alpha/2006-07-03-ASMFormalLowering.ll:1.2 Thu Jul 6 23:43:24 2006 +++ llvm/test/Regression/CodeGen/Alpha/2006-07-03-ASMFormalLowering.ll Mon Jul 10 20:39:30 2006 @@ -1,5 +1,4 @@ ; RUN: llvm-as %s | llc -march=alpha -; XFAIL: * target endian = little target pointersize = 64 ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.380 - 1.381 --- Log message: Fix CodeGen/Alpha/2006-07-03-ASMFormalLowering.ll and PR818: http://llvm.org/PR818 . --- Diffs of the changes: (+29 -12) LegalizeDAG.cpp | 41 + 1 files changed, 29 insertions(+), 12 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.380 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.381 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.380 Wed Jun 28 16:58:30 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Jul 10 20:40:09 2006 @@ -1163,25 +1163,42 @@ AddLegalizedOperand(SDOperand(Node, 1), Tmp2); return Op.ResNo ? Tmp2 : Tmp1; } - case ISD::INLINEASM: -Tmp1 = LegalizeOp(Node-getOperand(0)); // Legalize Chain. -Tmp2 = Node-getOperand(Node-getNumOperands()-1); -if (Tmp2.getValueType() == MVT::Flag) // Legalize Flag if it exists. - Tmp2 = Tmp3 = SDOperand(0, 0); -else - Tmp3 = LegalizeOp(Tmp2); + case ISD::INLINEASM: { +std::vectorSDOperand Ops(Node-op_begin(), Node-op_end()); +bool Changed = false; +// Legalize all of the operands of the inline asm, in case they are nodes +// that need to be expanded or something. Note we skip the asm string and +// all of the TargetConstant flags. +SDOperand Op = LegalizeOp(Ops[0]); +Changed = Op != Ops[0]; +Ops[0] = Op; + +bool HasInFlag = Ops.back().getValueType() == MVT::Flag; +for (unsigned i = 2, e = Ops.size()-HasInFlag; i e; ) { + unsigned NumVals = castConstantSDNode(Ops[i])-getValue() 3; + for (++i; NumVals; ++i, --NumVals) { +SDOperand Op = LegalizeOp(Ops[i]); +if (Op != Ops[i]) { + Changed = true; + Ops[i] = Op; +} + } +} + +if (HasInFlag) { + Op = LegalizeOp(Ops.back()); + Changed |= Op != Ops.back(); + Ops.back() = Op; +} -if (Tmp1 != Node-getOperand(0) || Tmp2 != Tmp3) { - std::vectorSDOperand Ops(Node-op_begin(), Node-op_end()); - Ops[0] = Tmp1; - if (Tmp3.Val) Ops.back() = Tmp3; +if (Changed) Result = DAG.UpdateNodeOperands(Result, Ops); -} // INLINE asm returns a chain and flag, make sure to add both to the map. AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); return Result.getValue(Op.ResNo); + } case ISD::BR: Tmp1 = LegalizeOp(Node-getOperand(0)); // Legalize the chain. // Ensure that libcalls are emitted before a branch. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll
Changes in directory llvm/test/Regression/CodeGen/X86: 2006-07-10-InlineAsmAConstraint.ll added (r1.1) --- Log message: New testcase for PR825: http://llvm.org/PR825 . --- Diffs of the changes: (+7 -0) 2006-07-10-InlineAsmAConstraint.ll |7 +++ 1 files changed, 7 insertions(+) Index: llvm/test/Regression/CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll diff -c /dev/null llvm/test/Regression/CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll:1.1 *** /dev/null Mon Jul 10 21:52:47 2006 --- llvm/test/Regression/CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll Mon Jul 10 21:52:37 2006 *** *** 0 --- 1,7 + ; RUN: llvm-as %s | llc -march=x86 + ; PR825 + + long %test() { + %tmp.i5 = call long asm sideeffect rdtsc, =A,~{dirflag},~{fpsr},~{flags}( ) ; long [#uses=0] + ret long %tmp.i5 + } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.235 - 1.236 X86ISelLowering.h updated: 1.68 - 1.69 --- Log message: Implement the inline asm 'A' constraint. This implements PR825: http://llvm.org/PR825 and CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll --- Diffs of the changes: (+17 -1) X86ISelLowering.cpp | 16 +++- X86ISelLowering.h |2 ++ 2 files changed, 17 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.235 llvm/lib/Target/X86/X86ISelLowering.cpp:1.236 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.235 Mon Jul 10 16:37:44 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Jul 10 21:54:03 2006 @@ -4135,6 +4135,16 @@ // X86 Inline Assembly Support //===--===// +/// getConstraintType - Given a constraint letter, return the type of +/// constraint it is for this target. +X86TargetLowering::ConstraintType +X86TargetLowering::getConstraintType(char ConstraintLetter) const { + switch (ConstraintLetter) { + case 'A': return C_RegisterClass; + default: return TargetLowering::getConstraintType(ConstraintLetter); + } +} + std::vectorunsigned X86TargetLowering:: getRegClassForInlineAsmConstraint(const std::string Constraint, MVT::ValueType VT) const { @@ -4142,7 +4152,11 @@ // FIXME: not handling fp-stack yet! // FIXME: not handling MMX registers yet ('y' constraint). switch (Constraint[0]) { // GCC X86 Constraint Letters -default: break; // Unknown constriant letter +default: break; // Unknown constraint letter +case 'A': // EAX/EDX + if (VT == MVT::i32 || VT == MVT::i64) +return make_vectorunsigned(X86::EAX, X86::EDX, 0); + break; case 'r': // GENERAL_REGS case 'R': // LEGACY_REGS if (VT == MVT::i32) Index: llvm/lib/Target/X86/X86ISelLowering.h diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.68 llvm/lib/Target/X86/X86ISelLowering.h:1.69 --- llvm/lib/Target/X86/X86ISelLowering.h:1.68 Fri Jul 7 03:33:52 2006 +++ llvm/lib/Target/X86/X86ISelLowering.h Mon Jul 10 21:54:03 2006 @@ -310,6 +310,8 @@ SDOperand getReturnAddressFrameIndex(SelectionDAG DAG); +ConstraintType getConstraintType(char ConstraintLetter) const; + std::vectorunsigned getRegClassForInlineAsmConstraint(const std::string Constraint, MVT::ValueType VT) const; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits