Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.47 - 1.48
ARMInstrInfo.td updated: 1.28 - 1.29
ARMRegisterInfo.td updated: 1.3 - 1.4
---
Log message:
add floating point registers
implement SINT_TO_FP
---
Diffs of the changes: (+137 -23)
ARMISelDAGToDAG.cpp | 32 --
ARMInstrInfo.td | 16 +++
ARMRegisterInfo.td | 112 +++-
3 files changed, 137 insertions(+), 23 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.47
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.48
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.47Thu Sep 21 08:06:26 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Fri Sep 29 16:20:15 2006
@@ -45,9 +45,10 @@
ARMTargetLowering::ARMTargetLowering(TargetMachine TM)
: TargetLowering(TM) {
addRegisterClass(MVT::i32, ARM::IntRegsRegisterClass);
+ addRegisterClass(MVT::f32, ARM::FPRegsRegisterClass);
+ addRegisterClass(MVT::f64, ARM::DFPRegsRegisterClass);
- //LLVM requires that a register class supports MVT::f64!
- addRegisterClass(MVT::f64, ARM::IntRegsRegisterClass);
+ setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
setOperationAction(ISD::RET, MVT::Other, Custom);
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
@@ -79,7 +80,9 @@
SELECT,
- BR
+ BR,
+
+ FSITOS
};
}
}
@@ -111,6 +114,7 @@
case ARMISD::SELECT:return ARMISD::SELECT;
case ARMISD::CMP: return ARMISD::CMP;
case ARMISD::BR:return ARMISD::BR;
+ case ARMISD::FSITOS:return ARMISD::FSITOS;
}
}
@@ -241,11 +245,18 @@
SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
}
- case 3:
-Copy = DAG.getCopyToReg(Chain, ARM::R0, Op.getOperand(1), SDOperand());
+ case 3: {
+SDOperand Val = Op.getOperand(1);
+assert(Val.getValueType() == MVT::i32 ||
+ Val.getValueType() == MVT::f32);
+
+if (Val.getValueType() == MVT::f32)
+ Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
+Copy = DAG.getCopyToReg(Chain, ARM::R0, Val, SDOperand());
if (DAG.getMachineFunction().liveout_empty())
DAG.getMachineFunction().addLiveOut(ARM::R0);
break;
+ }
case 5:
Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
@@ -409,6 +420,15 @@
return DAG.getNode(ARMISD::BR, MVT::Other, Chain, Dest, ARMCC, Cmp);
}
+static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG DAG) {
+ SDOperand IntVal = Op.getOperand(0);
+ assert(IntVal.getValueType() == MVT::i32);
+ assert(Op.getValueType() == MVT::f32);
+
+ SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, IntVal);
+ return DAG.getNode(ARMISD::FSITOS, MVT::f32, Tmp);
+}
+
SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG DAG) {
switch (Op.getOpcode()) {
default:
@@ -418,6 +438,8 @@
return LowerConstantPool(Op, DAG);
case ISD::GlobalAddress:
return LowerGlobalAddress(Op, DAG);
+ case ISD::SINT_TO_FP:
+return LowerSINT_TO_FP(Op, DAG);
case ISD::FORMAL_ARGUMENTS:
return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex);
case ISD::CALL:
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.28
llvm/lib/Target/ARM/ARMInstrInfo.td:1.29
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.28Wed Sep 13 07:09:43 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td Fri Sep 29 16:20:15 2006
@@ -74,6 +74,8 @@
def SDTVoidBinOp : SDTypeProfile0, 2, [SDTCisSameAs0, 1];
def armcmp : SDNodeARMISD::CMP, SDTVoidBinOp, [SDNPOutFlag];
+def armfsitos: SDNodeARMISD::FSITOS, SDTUnaryOp;
+
def ADJCALLSTACKUP : InstARM(ops i32imm:$amt),
!ADJCALLSTACKUP $amt,
[(callseq_end imm:$amt)];
@@ -150,3 +152,17 @@
def cmp : InstARM(ops IntRegs:$a, op_addr_mode1:$b),
cmp $a, $b,
[(armcmp IntRegs:$a, addr_mode1:$b)];
+
+
+// Floating Point Conversion
+// We use bitconvert for moving the data between the register classes.
+// The format conversion is done with ARM specific nodes
+
+def FMSR: InstARM(ops FPRegs:$dst, IntRegs:$src),
+ fmsr $dst, $src, [(set FPRegs:$dst, (bitconvert
IntRegs:$src))];
+
+def FMRS: InstARM(ops IntRegs:$dst, FPRegs:$src),
+ fmrs $dst, $src, [(set IntRegs:$dst, (bitconvert
FPRegs:$src))];
+
+def FSITOS : InstARM(ops FPRegs:$dst, FPRegs:$src),
+ fsitos $dst, $src, [(set FPRegs:$dst, (armfsitos
FPRegs:$src))];
Index: llvm/lib/Target/ARM/ARMRegisterInfo.td
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.td:1.3
llvm/lib/Target/ARM/ARMRegisterInfo.td:1.4
--- llvm/lib/Target/ARM/ARMRegisterInfo.td:1.3 Thu Aug 17
