[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.132 - 1.133
---
Log message:
These don't have immediate operands.
---
Diffs of the changes: (+64 -64)
X86InstrSSE.td | 128 -
1 files changed, 64 insertions(+), 64 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.132
llvm/lib/Target/X86/X86InstrSSE.td:1.133
--- llvm/lib/Target/X86/X86InstrSSE.td:1.132Sun Sep 10 21:19:56 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Oct 3 01:55:11 2006
@@ -1603,38 +1603,38 @@
}
let isTwoAddress = 1 in {
-def PSLLWrr : PDIi80xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
-psllw {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
- VR128:$src2))];
-def PSLLWrm : PDIi80xF1, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
-psllw {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
- (bc_v4i32 (loadv2i64 addr:$src2];
+def PSLLWrr : PDI0xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ psllw {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
+ VR128:$src2))];
+def PSLLWrm : PDI0xF1, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ psllw {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2];
def PSLLWri : PDIi80x71, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
psllw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
(scalar_to_vector (i32 imm:$src2];
-def PSLLDrr : PDIi80xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
-pslld {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
- VR128:$src2))];
-def PSLLDrm : PDIi80xF2, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
-pslld {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
- (bc_v4i32 (loadv2i64 addr:$src2];
+def PSLLDrr : PDI0xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ pslld {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
+ VR128:$src2))];
+def PSLLDrm : PDI0xF2, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ pslld {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2];
def PSLLDri : PDIi80x72, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
pslld {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
(scalar_to_vector (i32 imm:$src2];
-def PSLLQrr : PDIi80xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
-psllq {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
- VR128:$src2))];
-def PSLLQrm : PDIi80xF3, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
-psllq {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
- (bc_v4i32 (loadv2i64 addr:$src2];
+def PSLLQrr : PDI0xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ psllq {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
+ VR128:$src2))];
+def PSLLQrm : PDI0xF3, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ psllq {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2];
def PSLLQri : PDIi80x73, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
psllq {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
@@ -1642,38 +1642,38 @@
def PSLLDQri : PDIi80x73, MRM7r, (ops VR128:$dst, VR128:$src1,
i32i8imm:$src2),
pslldq {$src2, $dst|$dst, $src2}, [];
-def PSRLWrr : PDIi80xD1, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
-psrlw {$src2, $dst|$dst, $src2},
-
[llvm-commits] CVS: llvm/test/Regression/Analysis/Dominators/2006-10-02-BreakCritEdges.ll
Changes in directory llvm/test/Regression/Analysis/Dominators:
2006-10-02-BreakCritEdges.ll added (r1.1)
---
Log message:
New testcase for PR932: http://llvm.org/PR932
---
Diffs of the changes: (+20 -0)
2006-10-02-BreakCritEdges.ll | 20
1 files changed, 20 insertions(+)
Index: llvm/test/Regression/Analysis/Dominators/2006-10-02-BreakCritEdges.ll
diff -c /dev/null
llvm/test/Regression/Analysis/Dominators/2006-10-02-BreakCritEdges.ll:1.1
*** /dev/null Tue Oct 3 02:00:23 2006
--- llvm/test/Regression/Analysis/Dominators/2006-10-02-BreakCritEdges.ll
Tue Oct 3 02:00:13 2006
***
*** 0
--- 1,20
+ ; RUN: llvm-as %s | opt -domtree -break-crit-edges -analyze -domtree | grep
'3.*%brtrue$'
+ ; PR932
+ implementation ; Functions:
+
+ declare void %use1(int)
+
+ void %f(int %i, bool %c) {
+ entry:
+ %A = seteq int %i, 0; bool [#uses=1]
+ br bool %A, label %brtrue, label %brfalse
+
+ brtrue: ; preds = %brtrue, %entry
+ %B = phi bool [ true, %brtrue ], [ false, %entry ] ;
bool [#uses=1]
+ call void %use1( int %i )
+ br bool %B, label %brtrue, label %brfalse
+
+ brfalse: ; preds = %brtrue, %entry
+ call void %use1( int %i )
+ ret void
+ }
___
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[llvm-commits] CVS: llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
Changes in directory llvm/lib/Transforms/Utils:
BreakCriticalEdges.cpp updated: 1.32 - 1.33
---
Log message:
Fix PR932: http://llvm.org/PR932 and
Analysis/Dominators/2006-10-02-BreakCritEdges.ll:
The critical edge block dominates the dest block if the destblock dominates
all edges other than the one incoming from the critical edge.
---
Diffs of the changes: (+113 -16)
BreakCriticalEdges.cpp | 129 ++---
1 files changed, 113 insertions(+), 16 deletions(-)
Index: llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
diff -u llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp:1.32
llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp:1.33
--- llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp:1.32 Sun Aug 27
17:42:52 2006
+++ llvm/lib/Transforms/Utils/BreakCriticalEdges.cppTue Oct 3 02:02:02 2006
@@ -25,6 +25,7 @@
#include llvm/Type.h
#include llvm/Support/CFG.h
#include llvm/Support/Compiler.h
+#include llvm/ADT/SmallVector.h
#include llvm/ADT/Statistic.h
using namespace llvm;
@@ -135,10 +136,21 @@
// If we don't have a pass object, we can't update anything...
if (P == 0) return true;
- // Now update analysis information. These are the analyses that we are
- // currently capable of updating...
- //
-
+ // Now update analysis information. Since the only predecessor of NewBB is
+ // the TIBB, TIBB clearly dominates NewBB. TIBB usually doesn't dominate
+ // anything, as there are other successors of DestBB. However, if all other
+ // predecessors of DestBB are already dominated by DestBB (e.g. DestBB is a
+ // loop header) then NewBB dominates DestBB.
+ SmallVectorBasicBlock*, 8 OtherPreds;
+
+ for (pred_iterator I = pred_begin(DestBB), E = pred_end(DestBB); I != E; ++I)
+if (*I != NewBB)
+ OtherPreds.push_back(*I);
+
+ // NewBBDominatesDestBB is valid if OtherPreds is empty, otherwise it isn't
+ // yet computed.
+ bool NewBBDominatesDestBB = true;
+
// Should we update DominatorSet information?
if (DominatorSet *DS = P-getAnalysisToUpdateDominatorSet()) {
// The blocks that dominate the new one are the blocks that dominate TIBB
@@ -146,18 +158,65 @@
DominatorSet::DomSetType DomSet = DS-getDominators(TIBB);
DomSet.insert(NewBB); // A block always dominates itself.
DS-addBasicBlock(NewBB, DomSet);
+
+// If NewBBDominatesDestBB hasn't been computed yet, do so with DS.
+if (!OtherPreds.empty()) {
+ while (!OtherPreds.empty() NewBBDominatesDestBB) {
+NewBBDominatesDestBB = DS-dominates(DestBB, OtherPreds.back());
+OtherPreds.pop_back();
+ }
+ OtherPreds.clear();
+}
+
+// If NewBBDominatesDestBB, then NewBB dominates DestBB, otherwise it
+// doesn't dominate anything. If NewBB does dominates DestBB, then it
+// dominates everything that DestBB dominates.
+if (NewBBDominatesDestBB) {
+ for (DominatorSet::iterator I = DS-begin(), E = DS-end(); I != E; ++I)
+if (I-second.count(DestBB))
+ I-second.insert(NewBB);
+}
}
// Should we update ImmediateDominator information?
if (ImmediateDominators *ID = P-getAnalysisToUpdateImmediateDominators())
{
-// TIBB is the new immediate dominator for NewBB. NewBB doesn't dominate
-// anything.
+// TIBB is the new immediate dominator for NewBB.
ID-addNewBlock(NewBB, TIBB);
+
+// If NewBBDominatesDestBB hasn't been computed yet, do so with ID.
+if (!OtherPreds.empty()) {
+ while (!OtherPreds.empty() NewBBDominatesDestBB) {
+NewBBDominatesDestBB = ID-dominates(DestBB, OtherPreds.back());
+OtherPreds.pop_back();
+ }
+ OtherPreds.clear();
+}
+
+// If NewBBDominatesDestBB, then NewBB dominates DestBB, otherwise it
+// doesn't dominate anything.
+if (NewBBDominatesDestBB)
+ ID-setImmediateDominator(DestBB, NewBB);
}
// Update the forest?
- if (ETForest *EF = P-getAnalysisToUpdateETForest())
+ if (ETForest *EF = P-getAnalysisToUpdateETForest()) {
+// NewBB is dominated by TIBB.
EF-addNewBlock(NewBB, TIBB);
+
+// If NewBBDominatesDestBB hasn't been computed yet, do so with EF.
+if (!OtherPreds.empty()) {
+ while (!OtherPreds.empty() NewBBDominatesDestBB) {
+NewBBDominatesDestBB = EF-dominates(DestBB, OtherPreds.back());
+OtherPreds.pop_back();
+ }
+ OtherPreds.clear();
+}
+
+// If NewBBDominatesDestBB, then NewBB dominates DestBB, otherwise it
+// doesn't dominate anything.
+if (NewBBDominatesDestBB)
+ EF-setImmediateDominator(DestBB, NewBB);
+ }
// Should we update DominatorTree information?
if (DominatorTree *DT = P-getAnalysisToUpdateDominatorTree()) {
@@ -166,18 +225,57 @@
// The new block is not the immediate dominator for any other nodes, but
// TINode is the immediate dominator for the new node.
//
-if (TINode)// Don't break unreachable code!
-
[llvm-commits] CVS: llvm/include/llvm/CodeGen/LiveVariables.h
Changes in directory llvm/include/llvm/CodeGen:
LiveVariables.h updated: 1.29 - 1.30
---
Log message:
Fix for PR929: http://llvm.org/PR929 . The PHI nodes were being gone through
for each instruction
in a successor block for every block...resulting in some O(N^k) algorithm
which wasn't very good for performance. Calculating this information up
front and keeping it in a map made it much faster.
---
Diffs of the changes: (+11 -1)
LiveVariables.h | 12 +++-
1 files changed, 11 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/CodeGen/LiveVariables.h
diff -u llvm/include/llvm/CodeGen/LiveVariables.h:1.29
llvm/include/llvm/CodeGen/LiveVariables.h:1.30
--- llvm/include/llvm/CodeGen/LiveVariables.h:1.29 Sat Sep 2 19:05:09 2006
+++ llvm/include/llvm/CodeGen/LiveVariables.h Tue Oct 3 02:20:20 2006
@@ -39,7 +39,7 @@
class LiveVariables : public MachineFunctionPass {
public:
/// VarInfo - This represents the regions where a virtual register is live in
- /// the program. We represent this with three difference pieces of
+ /// the program. We represent this with three different pieces of
/// information: the instruction that uniquely defines the value, the set of
/// blocks the instruction is live into and live out of, and the set of
/// non-phi instructions that are the last users of the value.
@@ -136,9 +136,19 @@
MachineInstr **PhysRegInfo;
bool *PhysRegUsed;
+ typedef std::mapconst MachineBasicBlock*,
+ std::vectorunsigned PHIVarInfoMap;
+
+ PHIVarInfoMap PHIVarInfo;
+
void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
void HandlePhysRegDef(unsigned Reg, MachineInstr *MI);
+ /// analyzePHINodes - Gather information about the PHI nodes in here. In
+ /// particular, we want to map the variable information of a virtual
+ /// register which is used in a PHI node. We map that to the BB the vreg
+ /// is coming from.
+ void analyzePHINodes(const MachineFunction Fn);
public:
virtual bool runOnMachineFunction(MachineFunction MF);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/LiveVariables.cpp
Changes in directory llvm/lib/CodeGen:
LiveVariables.cpp updated: 1.59 - 1.60
---
Log message:
Fix for PR929: http://llvm.org/PR929 . The PHI nodes were being gone through
for each instruction
in a successor block for every block...resulting in some O(N^k) algorithm
which wasn't very good for performance. Calculating this information up
front and keeping it in a map made it much faster.
---
Diffs of the changes: (+26 -21)
LiveVariables.cpp | 47 ++-
1 files changed, 26 insertions(+), 21 deletions(-)
Index: llvm/lib/CodeGen/LiveVariables.cpp
diff -u llvm/lib/CodeGen/LiveVariables.cpp:1.59
llvm/lib/CodeGen/LiveVariables.cpp:1.60
--- llvm/lib/CodeGen/LiveVariables.cpp:1.59 Tue Sep 5 15:19:27 2006
+++ llvm/lib/CodeGen/LiveVariables.cpp Tue Oct 3 02:20:20 2006
@@ -92,7 +92,6 @@
return std::binary_search(I-second.begin(), I-second.end(), Reg);
}
-
void LiveVariables::MarkVirtRegAliveInBlock(VarInfo VRInfo,
MachineBasicBlock *MBB) {
unsigned BBNum = MBB-getNumber();
@@ -212,6 +211,8 @@
HandlePhysRegDef(I-first, 0);
}
+ analyzePHINodes(MF);
+
// Calculate live variable information in depth first order on the CFG of the
// function. This guarantees that we will see the definition of a virtual
// register before its uses due to dominance properties of SSA (except for
PHI
@@ -288,26 +289,16 @@
// bottom of this basic block. We check all of our successor blocks to see
// if they have PHI nodes, and if so, we simulate an assignment at the end
// of the current block.
-for (MachineBasicBlock::succ_iterator SI = MBB-succ_begin(),
- E = MBB-succ_end(); SI != E; ++SI) {
- MachineBasicBlock *Succ = *SI;
-
- // PHI nodes are guaranteed to be at the top of the block...
- for (MachineBasicBlock::iterator MI = Succ-begin(), ME = Succ-end();
- MI != ME MI-getOpcode() == TargetInstrInfo::PHI; ++MI) {
-for (unsigned i = 1; ; i += 2) {
- assert(MI-getNumOperands() i+1
- Didn't find an entry for our predecessor??);
- if (MI-getOperand(i+1).getMachineBasicBlock() == MBB) {
-MachineOperand MO = MI-getOperand(i);
-VarInfo VRInfo = getVarInfo(MO.getReg());
-assert(VRInfo.DefInst Register use before def (or no def)!);
+if (!PHIVarInfo[MBB].empty()) {
+ std::vectorunsigned VarInfoVec = PHIVarInfo[MBB];
-// Only mark it alive only in the block we are representing.
-MarkVirtRegAliveInBlock(VRInfo, MBB);
-break; // Found the PHI entry for this block.
- }
-}
+ for (std::vectorunsigned::iterator I = VarInfoVec.begin(),
+ E = VarInfoVec.end(); I != E; ++I) {
+VarInfo VRInfo = getVarInfo(*I);
+assert(VRInfo.DefInst Register use before def (or no def)!);
+
+// Only mark it alive only in the block we are representing.
+MarkVirtRegAliveInBlock(VRInfo, MBB);
}
}
@@ -362,6 +353,7 @@
assert(Visited.count(*i) != 0 unreachable basic block found);
#endif
+ PHIVarInfo.clear();
return false;
}
@@ -450,4 +442,17 @@
RegistersDead.erase(I);
}
-
+/// analyzePHINodes - Gather information about the PHI nodes in here. In
+/// particular, we want to map the variable information of a virtual
+/// register which is used in a PHI node. We map that to the BB the vreg is
+/// coming from.
+///
+void LiveVariables::analyzePHINodes(const MachineFunction Fn) {
+ for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
+ I != E; ++I)
+for (MachineBasicBlock::const_iterator BBI = I-begin(), BBE = I-end();
+ BBI != BBE BBI-getOpcode() == TargetInstrInfo::PHI; ++BBI)
+ for (unsigned i = 1, e = BBI-getNumOperands(); i != e; i += 2)
+PHIVarInfo[BBI-getOperand(i + 1).getMachineBasicBlock()].
+ push_back(BBI-getOperand(i).getReg());
+}
___
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[llvm-commits] CVS: llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
Changes in directory llvm/lib/Transforms/IPO:
ArgumentPromotion.cpp updated: 1.26 - 1.27
---
Log message:
Revert previous patch. Still breaking things.
---
Diffs of the changes: (+1 -49)
ArgumentPromotion.cpp | 50 +-
1 files changed, 1 insertion(+), 49 deletions(-)
Index: llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
diff -u llvm/lib/Transforms/IPO/ArgumentPromotion.cpp:1.26
llvm/lib/Transforms/IPO/ArgumentPromotion.cpp:1.27
--- llvm/lib/Transforms/IPO/ArgumentPromotion.cpp:1.26 Thu Sep 28 18:02:22 2006
+++ llvm/lib/Transforms/IPO/ArgumentPromotion.cpp Tue Oct 3 02:26:07 2006
@@ -179,53 +179,6 @@
return true;
}
-/// AccessOccursOnPath - Returns true if and only if a load or GEP instruction
-/// on Pointer occurs in Path, or in every control-flow path that succeeds it.
-bool AccessOccursOnPath(Value* V, BasicBlock* Start) {
- std::vectorBasicBlock* Worklist;
- Worklist.push_back(Start);
-
- std::setBasicBlock* Visited;
-
- while (!Worklist.empty()) {
-BasicBlock* BB = Worklist.back();
-Worklist.pop_back();
-Visited.insert(BB);
-
-bool ContainsAccess = false;
-for (BasicBlock::iterator I = BB-begin(), E = BB-end(); I != E; ++I) {
- if (isaLoadInst(I)) {
-for (Instruction::op_iterator OI = I-op_begin(), OE = I-op_end(); OI
!= OE; ++OI)
- if (*OI == V) {
-ContainsAccess = true;
-break;
- }
- } else if (isaGetElementPtrInst(I)) {
-for (Instruction::op_iterator OI = I-op_begin(), OE = I-op_end(); OI
!= OE; ++OI)
- if (*OI == V) {
-ContainsAccess = AccessOccursOnPath(I, I-getParent());
-break;
- }
- }
-
- if (ContainsAccess)
- break;
-}
-
-if (ContainsAccess) continue;
-
-TerminatorInst* TI = BB-getTerminator();
-if (isaBranchInst(TI) || isaSwitchInst(TI)) {
- for (unsigned i = 0; i TI-getNumSuccessors(); ++i)
-if (!Visited.count(TI-getSuccessor(i)))
- Worklist.push_back(TI-getSuccessor(i));
-} else {
- return false;
-}
- }
-
- return true;
-}
/// isSafeToPromoteArgument - As you might guess from the name of this method,
/// it checks to see if it is both safe and useful to promote the argument.
@@ -299,8 +252,7 @@
// of the pointer in the entry block of the function) or if we can prove that
// all pointers passed in are always to legal locations (for example, no null
// pointers are passed in, no pointers to free'd memory, etc).
- if (!AccessOccursOnPath(Arg, Arg-getParent()-begin())
- !AllCalleesPassInValidPointerForArgument(Arg))
+ if (!HasLoadInEntryBlock !AllCalleesPassInValidPointerForArgument(Arg))
return false; // Cannot prove that this is safe!!
// Okay, now we know that the argument is only used by load instructions and
___
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp
Changes in directory llvm/lib/Transforms/Scalar:
PredicateSimplifier.cpp updated: 1.16 - 1.17
---
Log message:
Move break-crit-edges before the predicate simplifier. Allows us to
optimize in more cases.
---
Diffs of the changes: (+3 -7)
PredicateSimplifier.cpp | 10 +++---
1 files changed, 3 insertions(+), 7 deletions(-)
Index: llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp
diff -u llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.16
llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.17
--- llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.16 Thu Sep 28
18:35:21 2006
+++ llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp Tue Oct 3 09:52:23 2006
@@ -500,8 +500,10 @@
}
void PredicateSimplifier::getAnalysisUsage(AnalysisUsage AU) const {
+ AU.addRequiredID(BreakCriticalEdgesID);
AU.addRequiredDominatorTree();
AU.setPreservesCFG();
+ AU.addPreservedID(BreakCriticalEdgesID);
}
// resolve catches cases addProperty won't because it wasn't used as a
@@ -622,13 +624,7 @@
PropertySet NextPS) {
assert(edge TI-getNumSuccessors() Invalid index for edge.);
- BasicBlock *BB = TI-getParent(),
- *BBNext = TI-getSuccessor(edge);
-
- if (BBNext-getSinglePredecessor() == BB)
-visitBasicBlock(BBNext, NextPS);
- else
-visitBasicBlock(BBNext, CurrentPS);
+ visitBasicBlock(TI-getSuccessor(edge), NextPS);
}
void PredicateSimplifier::proceedToSuccessors(PropertySet KP,
___
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[llvm-commits] CVS: llvm/test/Regression/Transforms/PredicateSimplifier/2006-09-20-SetCC.ll
Changes in directory llvm/test/Regression/Transforms/PredicateSimplifier: 2006-09-20-SetCC.ll updated: 1.1 - 1.2 --- Log message: Move break-crit-edges before the predicate simplifier. Allows us to optimize in more cases. --- Diffs of the changes: (+1 -1) 2006-09-20-SetCC.ll |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/PredicateSimplifier/2006-09-20-SetCC.ll diff -u llvm/test/Regression/Transforms/PredicateSimplifier/2006-09-20-SetCC.ll:1.1 llvm/test/Regression/Transforms/PredicateSimplifier/2006-09-20-SetCC.ll:1.2 --- llvm/test/Regression/Transforms/PredicateSimplifier/2006-09-20-SetCC.ll:1.1 Wed Sep 20 18:02:24 2006 +++ llvm/test/Regression/Transforms/PredicateSimplifier/2006-09-20-SetCC.ll Tue Oct 3 09:52:22 2006 @@ -1,4 +1,4 @@ -; RUN: llvm-as %s | opt -predsimplify | llvm-dis | grep br | grep bb8 | grep cond_true$ | grep false +; RUN: llvm-as %s | opt -predsimplify | llvm-dis | grep br | grep return.i.bb8_crit_edge | grep false %str = external global [4 x sbyte] ; [4 x sbyte]* [#uses=1] ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp
Changes in directory llvm/lib/Transforms/Scalar:
PredicateSimplifier.cpp updated: 1.17 - 1.18
---
Log message:
Simplify, now that predsimplify depends on break-crit-edges.
Fix SwitchInst where dest-block is the same as one of the cases.
---
Diffs of the changes: (+8 -26)
PredicateSimplifier.cpp | 34 --
1 files changed, 8 insertions(+), 26 deletions(-)
Index: llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp
diff -u llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.17
llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.18
--- llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.17 Tue Oct 3
09:52:23 2006
+++ llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp Tue Oct 3 10:19:11 2006
@@ -413,8 +413,6 @@
// Used by terminator instructions to proceed from the current basic
// block to the next. Verifies that current dominates next,
// then calls visitBasicBlock.
-void proceedToSuccessor(TerminatorInst *TI, unsigned edge,
-PropertySet CurrentPS, PropertySet NextPS);
void proceedToSuccessors(PropertySet CurrentPS, BasicBlock *Current);
// Visits each instruction in the basic block.
@@ -616,17 +614,6 @@
visit(BO, KnownProperties);
}
-// The basic block on the target of the specified edge must be known
-// to be immediately dominated by the parent of the TerminatorInst.
-void PredicateSimplifier::proceedToSuccessor(TerminatorInst *TI,
- unsigned edge,
- PropertySet CurrentPS,
- PropertySet NextPS) {
- assert(edge TI-getNumSuccessors() Invalid index for edge.);
-
- visitBasicBlock(TI-getSuccessor(edge), NextPS);
-}
-
void PredicateSimplifier::proceedToSuccessors(PropertySet KP,
BasicBlock *BBCurrent) {
DTNodeType *Current = DT-getNode(BBCurrent);
@@ -676,14 +663,14 @@
if ((*I)-getBlock() == TrueDest) {
PropertySet TrueProperties(KP);
TrueProperties.addEqual(ConstantBool::getTrue(), Condition);
- proceedToSuccessor(BI, 0, KP, TrueProperties);
+ visitBasicBlock(TrueDest, TrueProperties);
continue;
}
if ((*I)-getBlock() == FalseDest) {
PropertySet FalseProperties(KP);
FalseProperties.addEqual(ConstantBool::getFalse(), Condition);
- proceedToSuccessor(BI, 1, KP, FalseProperties);
+ visitBasicBlock(FalseDest, FalseProperties);
continue;
}
@@ -702,20 +689,15 @@
for (DTNodeType::iterator I = Node-begin(), E = Node-end(); I != E; ++I) {
BasicBlock *BB = (*I)-getBlock();
-PropertySet Copy(KP);
-
+PropertySet BBProperties(KP);
if (BB == SI-getDefaultDest()) {
- PropertySet NewProperties(KP);
for (unsigned i = 1, e = SI-getNumCases(); i e; ++i)
-NewProperties.addNotEqual(Condition, SI-getCaseValue(i));
-
- proceedToSuccessor(SI, 0, Copy, NewProperties);
+if (SI-getSuccessor(i) != BB)
+ BBProperties.addNotEqual(Condition, SI-getCaseValue(i));
} else if (ConstantInt *CI = SI-findCaseDest(BB)) {
- PropertySet NewProperties(KP);
- NewProperties.addEqual(Condition, CI);
- proceedToSuccessor(SI, SI-findCaseValue(CI), Copy, NewProperties);
-} else
- visitBasicBlock(BB, Copy);
+ BBProperties.addEqual(Condition, CI);
+}
+visitBasicBlock(BB, BBProperties);
}
}
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[llvm-commits] CVS: llvm/include/llvm/Instructions.h
Changes in directory llvm/include/llvm:
Instructions.h updated: 1.42 - 1.43
---
Log message:
clean up use of 'explicit'. This is PR934: http://llvm.org/PR934 .
Patch contributed by Kevin Sopp!
---
Diffs of the changes: (+42 -43)
Instructions.h | 85 -
1 files changed, 42 insertions(+), 43 deletions(-)
Index: llvm/include/llvm/Instructions.h
diff -u llvm/include/llvm/Instructions.h:1.42
llvm/include/llvm/Instructions.h:1.43
--- llvm/include/llvm/Instructions.h:1.42 Mon Sep 18 15:44:37 2006
+++ llvm/include/llvm/Instructions.hTue Oct 3 12:09:12 2006
@@ -42,7 +42,7 @@
public:
// Out of line virtual method, so the vtable, etc has a home.
virtual ~AllocationInst();
-
+
/// isArrayAllocation - Return true if there is an allocation size parameter
/// to the allocation instruction that is not 1.
///
@@ -73,7 +73,7 @@
assert((Align (Align-1)) == 0 Alignment is not a power of 2!);
Alignment = Align;
}
-
+
virtual Instruction *clone() const = 0;
// Methods for support type inquiry through isa, cast, and dyn_cast:
@@ -104,21 +104,21 @@
MallocInst(const Type *Ty, Value *ArraySize, const std::string Name,
BasicBlock *InsertAtEnd)
: AllocationInst(Ty, ArraySize, Malloc, 0, Name, InsertAtEnd) {}
-
- explicit MallocInst(const Type *Ty, const std::string Name,
- Instruction *InsertBefore = 0)
+
+ MallocInst(const Type *Ty, const std::string Name,
+ Instruction *InsertBefore = 0)
: AllocationInst(Ty, 0, Malloc, 0, Name, InsertBefore) {}
MallocInst(const Type *Ty, const std::string Name, BasicBlock *InsertAtEnd)
: AllocationInst(Ty, 0, Malloc, 0, Name, InsertAtEnd) {}
-
- MallocInst(const Type *Ty, Value *ArraySize, unsigned Align,
+
+ MallocInst(const Type *Ty, Value *ArraySize, unsigned Align,
const std::string Name, BasicBlock *InsertAtEnd)
: AllocationInst(Ty, ArraySize, Malloc, Align, Name, InsertAtEnd) {}
MallocInst(const Type *Ty, Value *ArraySize, unsigned Align,
const std::string Name = ,
Instruction *InsertBefore = 0)
: AllocationInst(Ty, ArraySize, Malloc, Align, Name, InsertBefore) {}
-
+
virtual MallocInst *clone() const;
// Methods for support type inquiry through isa, cast, and dyn_cast:
@@ -154,14 +154,14 @@
: AllocationInst(Ty, 0, Alloca, 0, Name, InsertBefore) {}
AllocaInst(const Type *Ty, const std::string Name, BasicBlock *InsertAtEnd)
: AllocationInst(Ty, 0, Alloca, 0, Name, InsertAtEnd) {}
-
+
AllocaInst(const Type *Ty, Value *ArraySize, unsigned Align,
const std::string Name = , Instruction *InsertBefore = 0)
: AllocationInst(Ty, ArraySize, Alloca, Align, Name, InsertBefore) {}
AllocaInst(const Type *Ty, Value *ArraySize, unsigned Align,
const std::string Name, BasicBlock *InsertAtEnd)
: AllocationInst(Ty, ArraySize, Alloca, Align, Name, InsertAtEnd) {}
-
+
virtual AllocaInst *clone() const;
// Methods for support type inquiry through isa, cast, and dyn_cast:
@@ -222,8 +222,8 @@
public:
LoadInst(Value *Ptr, const std::string Name, Instruction *InsertBefore);
LoadInst(Value *Ptr, const std::string Name, BasicBlock *InsertAtEnd);
- LoadInst(Value *Ptr, const std::string Name = , bool isVolatile = false,
- Instruction *InsertBefore = 0);
+ explicit LoadInst(Value *Ptr, const std::string Name = ,
+bool isVolatile = false, Instruction *InsertBefore = 0);
LoadInst(Value *Ptr, const std::string Name, bool isVolatile,
BasicBlock *InsertAtEnd);
@@ -458,13 +458,13 @@
bool isEquality() const {
return getOpcode() == SetEQ || getOpcode() == SetNE;
}
-
+
/// isRelational - Return true if this comparison is a //=/= comparison.
///
bool isRelational() const {
return !isEquality();
}
-
+
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const SetCondInst *) { return true; }
static inline bool classof(const Instruction *I) {
@@ -501,8 +501,8 @@
/// isTruncIntCast - Return true if this is a truncating integer cast
/// instruction, e.g. a cast from long to uint.
bool isTruncIntCast() const;
-
-
+
+
virtual CastInst *clone() const;
// Methods for support type inquiry through isa, cast, and dyn_cast:
@@ -550,8 +550,7 @@
BasicBlock *InsertAtEnd);
explicit CallInst(Value *F, const std::string Name = ,
Instruction *InsertBefore = 0);
- explicit CallInst(Value *F, const std::string Name,
-BasicBlock *InsertAtEnd);
+ CallInst(Value *F, const std::string Name, BasicBlock *InsertAtEnd);
~CallInst();
virtual CallInst *clone() const;
@@ -640,14 +639,14 @@
/// isLogicalShift - Return true if this is a logical shift left or a logical
/// shift right.
[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/2006-10-02-BoolRetCrash.ll
Changes in directory llvm/test/Regression/CodeGen/X86:
2006-10-02-BoolRetCrash.ll added (r1.1)
---
Log message:
testcase for PR933: http://llvm.org/PR933
---
Diffs of the changes: (+7 -0)
2006-10-02-BoolRetCrash.ll |7 +++
1 files changed, 7 insertions(+)
Index: llvm/test/Regression/CodeGen/X86/2006-10-02-BoolRetCrash.ll
diff -c /dev/null
llvm/test/Regression/CodeGen/X86/2006-10-02-BoolRetCrash.ll:1.1
*** /dev/null Tue Oct 3 12:18:04 2006
--- llvm/test/Regression/CodeGen/X86/2006-10-02-BoolRetCrash.ll Tue Oct 3
12:17:54 2006
***
*** 0
--- 1,7
+ ; RUN: llvm-as %s | llc
+ ; RUN: llvm-as %s | llc -enable-x86-fastcc
+ ; PR933
+
+ fastcc bool %test() {
+ ret bool true
+ }
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.265 - 1.266
---
Log message:
Fix PR933: http://llvm.org/PR933 and CodeGen/X86/2006-10-02-BoolRetCrash.ll
---
Diffs of the changes: (+2 -0)
X86ISelLowering.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.265
llvm/lib/Target/X86/X86ISelLowering.cpp:1.266
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.265 Wed Sep 27 13:29:38 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Oct 3 12:18:42 2006
@@ -1494,6 +1494,7 @@
switch (getValueType(MF.getFunction()-getReturnType())) {
default: assert(0 Unknown type!);
case MVT::isVoid: break;
+ case MVT::i1:
case MVT::i8:
case MVT::i16:
case MVT::i32:
@@ -2276,6 +2277,7 @@
switch (getValueType(MF.getFunction()-getReturnType())) {
default: assert(0 Unknown type!);
case MVT::isVoid: break;
+ case MVT::i1:
case MVT::i8:
case MVT::i16:
case MVT::i32:
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ARMInstrInfo.td README.txt
Changes in directory llvm/lib/Target/ARM: ARMISelDAGToDAG.cpp updated: 1.49 - 1.50 ARMInstrInfo.td updated: 1.30 - 1.31 README.txt updated: 1.2 - 1.3 --- Log message: Implement floating point constants --- Diffs of the changes: (+11 -0) ARMISelDAGToDAG.cpp |3 +++ ARMInstrInfo.td |4 README.txt |4 3 files changed, 11 insertions(+) Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.49 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.50 --- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.49Mon Oct 2 14:30:56 2006 +++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Oct 3 12:27:58 2006 @@ -61,6 +61,9 @@ setOperationAction(ISD::VASTART, MVT::Other, Custom); setOperationAction(ISD::VAEND, MVT::Other, Expand); + setOperationAction(ISD::ConstantFP, MVT::f64, Expand); + setOperationAction(ISD::ConstantFP, MVT::f32, Expand); + setSchedulingPreference(SchedulingForRegPressure); computeRegisterProperties(); } Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.30 llvm/lib/Target/ARM/ARMInstrInfo.td:1.31 --- llvm/lib/Target/ARM/ARMInstrInfo.td:1.30Mon Oct 2 14:30:56 2006 +++ llvm/lib/Target/ARM/ARMInstrInfo.td Tue Oct 3 12:27:58 2006 @@ -100,6 +100,10 @@ ldr $dst, $addr, [(set IntRegs:$dst, (load iaddr:$addr))]; +def FLDS : InstARM(ops FPRegs:$dst, IntRegs:$addr), + flds $dst, $addr, + [(set FPRegs:$dst, (load IntRegs:$addr))]; + def str : InstARM(ops IntRegs:$src, memri:$addr), str $src, $addr, [(store IntRegs:$src, iaddr:$addr)]; Index: llvm/lib/Target/ARM/README.txt diff -u llvm/lib/Target/ARM/README.txt:1.2 llvm/lib/Target/ARM/README.txt:1.3 --- llvm/lib/Target/ARM/README.txt:1.2 Fri Sep 22 06:36:17 2006 +++ llvm/lib/Target/ARM/README.txt Tue Oct 3 12:27:58 2006 @@ -28,3 +28,7 @@ add r0, r1, r0 -- + +add an offset to FLDS addressing mode + +-- ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/fp.ll
Changes in directory llvm/test/Regression/CodeGen/ARM:
fp.ll updated: 1.2 - 1.3
---
Log message:
Implement floating point constants
---
Diffs of the changes: (+8 -1)
fp.ll |9 -
1 files changed, 8 insertions(+), 1 deletion(-)
Index: llvm/test/Regression/CodeGen/ARM/fp.ll
diff -u llvm/test/Regression/CodeGen/ARM/fp.ll:1.2
llvm/test/Regression/CodeGen/ARM/fp.ll:1.3
--- llvm/test/Regression/CodeGen/ARM/fp.ll:1.2 Mon Oct 2 14:30:56 2006
+++ llvm/test/Regression/CodeGen/ARM/fp.ll Tue Oct 3 12:27:58 2006
@@ -3,7 +3,9 @@
; RUN: llvm-as %s | llc -march=arm | grep fsitos
; RUN: llvm-as %s | llc -march=arm | grep fmrs
; RUN: llvm-as %s | llc -march=arm | grep fsitod
-; RUN: llvm-as %s | llc -march=arm | grep fmrrd
+; RUN: llvm-as %s | llc -march=arm | grep fmrrd
+; RUN: llvm-as %s | llc -march=arm | grep flds
+; RUN: llvm-as %s | llc -march=arm | grep .word.*1065353216
float %f(int %a) {
entry:
@@ -16,3 +18,8 @@
%tmp = cast int %a to double; double [#uses=1]
ret double %tmp
}
+
+float %h() {
+entry:
+ret float 1.00e+00
+}
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp
Changes in directory llvm/lib/Transforms/Scalar:
PredicateSimplifier.cpp updated: 1.18 - 1.19
---
Log message:
Simplify logic further.
Ensure that we copy KnownProperties before calling visitBasicBlock, else
we may leak properties into blocks where they don't belong.
---
Diffs of the changes: (+8 -17)
PredicateSimplifier.cpp | 25 -
1 files changed, 8 insertions(+), 17 deletions(-)
Index: llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp
diff -u llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.18
llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.19
--- llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.18 Tue Oct 3
10:19:11 2006
+++ llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp Tue Oct 3 12:36:01 2006
@@ -650,31 +650,22 @@
BasicBlock *TrueDest = BI-getSuccessor(0),
*FalseDest = BI-getSuccessor(1);
- if (Condition == ConstantBool::getTrue() || TrueDest == FalseDest) {
-proceedToSuccessors(KP, BB);
-return;
- } else if (Condition == ConstantBool::getFalse()) {
+ if (isaConstantBool(Condition) || TrueDest == FalseDest) {
proceedToSuccessors(KP, BB);
return;
}
DTNodeType *Node = DT-getNode(BB);
for (DTNodeType::iterator I = Node-begin(), E = Node-end(); I != E; ++I) {
-if ((*I)-getBlock() == TrueDest) {
- PropertySet TrueProperties(KP);
- TrueProperties.addEqual(ConstantBool::getTrue(), Condition);
- visitBasicBlock(TrueDest, TrueProperties);
- continue;
-}
+BasicBlock *Dest = (*I)-getBlock();
+PropertySet DestProperties(KP);
-if ((*I)-getBlock() == FalseDest) {
- PropertySet FalseProperties(KP);
- FalseProperties.addEqual(ConstantBool::getFalse(), Condition);
- visitBasicBlock(FalseDest, FalseProperties);
- continue;
-}
+if (Dest == TrueDest)
+ DestProperties.addEqual(ConstantBool::getTrue(), Condition);
+else if (Dest == FalseDest)
+ DestProperties.addEqual(ConstantBool::getFalse(), Condition);
-visitBasicBlock((*I)-getBlock(), KP);
+visitBasicBlock(Dest, DestProperties);
}
}
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[llvm-commits] CVS: llvm/lib/CodeGen/MachineFunction.cpp
Changes in directory llvm/lib/CodeGen:
MachineFunction.cpp updated: 1.100 - 1.101
---
Log message:
Provide a function that ensures MBB numbering is dense and inorder. This
can be used by MachineFunctionPasses who need this property.
---
Diffs of the changes: (+47 -0)
MachineFunction.cpp | 47 +++
1 files changed, 47 insertions(+)
Index: llvm/lib/CodeGen/MachineFunction.cpp
diff -u llvm/lib/CodeGen/MachineFunction.cpp:1.100
llvm/lib/CodeGen/MachineFunction.cpp:1.101
--- llvm/lib/CodeGen/MachineFunction.cpp:1.100 Thu Sep 14 02:41:12 2006
+++ llvm/lib/CodeGen/MachineFunction.cppTue Oct 3 14:18:57 2006
@@ -132,6 +132,53 @@
delete[] UsedPhysRegs;
}
+
+/// RenumberBlocks - This discards all of the MachineBasicBlock numbers and
+/// recomputes them. This guarantees that the MBB numbers are sequential,
+/// dense, and match the ordering of the blocks within the function. If a
+/// specific MachineBasicBlock is specified, only that block and those after
+/// it are renumbered.
+void MachineFunction::RenumberBlocks(MachineBasicBlock *MBB) {
+ if (empty()) { MBBNumbering.clear(); return; }
+ MachineFunction::iterator MBBI, E = end();
+ if (MBB == 0)
+MBBI = begin();
+ else
+MBBI = MBB;
+
+ // Figure out the block number this should have.
+ unsigned BlockNo = 0;
+ if (MBB != front()) {
+MachineFunction::iterator I = MBB;
+--I;
+BlockNo = I-getNumber()+1;
+ }
+
+ for (; MBBI != E; ++MBBI, ++BlockNo) {
+if (MBBI-getNumber() != (int)BlockNo) {
+ // Remove use of the old number.
+ if (MBBI-getNumber() != -1) {
+assert(MBBNumbering[MBBI-getNumber()] == *MBBI
+ MBB number mismatch!);
+MBBNumbering[MBBI-getNumber()] = 0;
+ }
+
+ // If BlockNo is already taken, set that block's number to -1.
+ if (MBBNumbering[BlockNo])
+MBBNumbering[BlockNo]-setNumber(-1);
+
+ MBBNumbering[BlockNo] = MBBI;
+ MBBI-setNumber(BlockNo);
+}
+ }
+
+ // Okay, all the blocks are renumbered. If we have compactified the block
+ // numbering, shrink MBBNumbering now.
+ assert(BlockNo = MBBNumbering.size() Mismatch!);
+ MBBNumbering.resize(BlockNo);
+}
+
+
void MachineFunction::dump() const { print(std::cerr); }
void MachineFunction::print(std::ostream OS) const {
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFunction.h
Changes in directory llvm/include/llvm/CodeGen:
MachineFunction.h updated: 1.61 - 1.62
---
Log message:
Provide a function that ensures MBB numbering is dense and inorder. This
can be used by MachineFunctionPasses who need this property.
---
Diffs of the changes: (+8 -0)
MachineFunction.h |8
1 files changed, 8 insertions(+)
Index: llvm/include/llvm/CodeGen/MachineFunction.h
diff -u llvm/include/llvm/CodeGen/MachineFunction.h:1.61
llvm/include/llvm/CodeGen/MachineFunction.h:1.62
--- llvm/include/llvm/CodeGen/MachineFunction.h:1.61Thu Sep 14 01:40:48 2006
+++ llvm/include/llvm/CodeGen/MachineFunction.h Tue Oct 3 14:18:57 2006
@@ -224,8 +224,16 @@
}
/// getNumBlockIDs - Return the number of MBB ID's allocated.
+ ///
unsigned getNumBlockIDs() const { return MBBNumbering.size(); }
+ /// RenumberBlocks - This discards all of the MachineBasicBlock numbers and
+ /// recomputes them. This guarantees that the MBB numbers are sequential,
+ /// dense, and match the ordering of the blocks within the function. If a
+ /// specific MachineBasicBlock is specified, only that block and those after
+ /// it are renumbered.
+ void RenumberBlocks(MachineBasicBlock *MBBFrom = 0);
+
/// print - Print out the MachineFunction in a format suitable for debugging
/// to the specified stream.
///
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineBasicBlock.h
Changes in directory llvm/include/llvm/CodeGen:
MachineBasicBlock.h updated: 1.44 - 1.45
---
Log message:
ADd a method
---
Diffs of the changes: (+1 -0)
MachineBasicBlock.h |1 +
1 files changed, 1 insertion(+)
Index: llvm/include/llvm/CodeGen/MachineBasicBlock.h
diff -u llvm/include/llvm/CodeGen/MachineBasicBlock.h:1.44
llvm/include/llvm/CodeGen/MachineBasicBlock.h:1.45
--- llvm/include/llvm/CodeGen/MachineBasicBlock.h:1.44 Thu Apr 21 15:38:00 2005
+++ llvm/include/llvm/CodeGen/MachineBasicBlock.h Tue Oct 3 15:16:45 2006
@@ -179,6 +179,7 @@
/// will return -1.
///
int getNumber() const { return Number; }
+ void setNumber(int N) { Number = N; }
private: // Methods used to maintain doubly linked list of blocks...
friend struct ilist_traitsMachineBasicBlock;
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[llvm-commits] CVS: llvm/lib/CodeGen/MachineBasicBlock.cpp
Changes in directory llvm/lib/CodeGen:
MachineBasicBlock.cpp updated: 1.29 - 1.30
---
Log message:
Print the MBB ID # along with the bb tag in the -print-machine-instrs output.
---
Diffs of the changes: (+1 -1)
MachineBasicBlock.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/MachineBasicBlock.cpp
diff -u llvm/lib/CodeGen/MachineBasicBlock.cpp:1.29
llvm/lib/CodeGen/MachineBasicBlock.cpp:1.30
--- llvm/lib/CodeGen/MachineBasicBlock.cpp:1.29 Mon Sep 25 22:41:59 2006
+++ llvm/lib/CodeGen/MachineBasicBlock.cpp Tue Oct 3 15:17:24 2006
@@ -96,7 +96,7 @@
const BasicBlock *LBB = getBasicBlock();
if (LBB)
OS \n LBB-getName() ( (const void*)this
-, LLVM BB @ (const void*) LBB ):\n;
+, LLVM BB @ (const void*) LBB , ID# getNumber()
):\n;
// Print the preds of this block according to the CFG.
if (!pred_empty()) {
OS Predecessors according to CFG:;
___
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[llvm-commits] CVS: llvm-test/MultiSource/Applications/viterbi/
Changes in directory llvm-test/MultiSource/Applications/viterbi: --- Log message: Directory /var/cvs/llvm/llvm-test/MultiSource/Applications/viterbi added to the repository --- Diffs of the changes: (+0 -0) 0 files changed ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.400 - 1.401
---
Log message:
Fix an obvious typo.
---
Diffs of the changes: (+1 -1)
LegalizeDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.400
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.401
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.400 Sun Sep 24 14:44:59 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Oct 3 18:08:27 2006
@@ -1398,7 +1398,7 @@
Tmp2 = Result.getValue(1);
if (isCustom) {
-Tmp3 = TLI.LowerOperation(Tmp3, DAG);
+Tmp3 = TLI.LowerOperation(Result, DAG);
if (Tmp3.Val) {
Tmp1 = LegalizeOp(Tmp3);
Tmp2 = LegalizeOp(Tmp3.getValue(1));
___
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[llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp
Changes in directory llvm/lib/CodeGen:
AsmPrinter.cpp updated: 1.102 - 1.103
---
Log message:
Use $( $| $) to represent alternatives in asm blocks instead of {|}. This
is needed to support targets where {|} aren't special symbols.
---
Diffs of the changes: (+34 -28)
AsmPrinter.cpp | 62 +++--
1 files changed, 34 insertions(+), 28 deletions(-)
Index: llvm/lib/CodeGen/AsmPrinter.cpp
diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.102
llvm/lib/CodeGen/AsmPrinter.cpp:1.103
--- llvm/lib/CodeGen/AsmPrinter.cpp:1.102 Thu Sep 28 18:17:41 2006
+++ llvm/lib/CodeGen/AsmPrinter.cpp Tue Oct 3 18:27:09 2006
@@ -694,12 +694,45 @@
break;
case '$': {
++LastEmitted; // Consume '$' character.
- if (*LastEmitted == '$') { // $$ - $
+ bool Done = true;
+
+ // Handle escapes.
+ switch (*LastEmitted) {
+ default: Done = false; break;
+ case '$': // $$ - $
if (CurVariant == -1 || CurVariant == AsmPrinterVariant)
O '$';
++LastEmitted; // Consume second '$' character.
break;
+ case '(': // $( - same as GCC's { character.
+++LastEmitted; // Consume '(' character.
+if (CurVariant != -1) {
+ std::cerr Nested variants found in inline asm string: '
+ AsmStr '\n;
+ exit(1);
+}
+CurVariant = 0; // We're in the first variant now.
+break;
+ case '|':
+++LastEmitted; // consume '|' character.
+if (CurVariant == -1) {
+ std::cerr Found '|' character outside of variant in inline asm
+ string: ' AsmStr '\n;
+ exit(1);
+}
+++CurVariant; // We're in the next variant.
+break;
+ case ')': // $) - same as GCC's } char.
+++LastEmitted; // consume ')' character.
+if (CurVariant == -1) {
+ std::cerr Found '}' character outside of variant in inline asm
+ string: ' AsmStr '\n;
+ exit(1);
+}
+CurVariant = -1;
+break;
}
+ if (Done) break;
bool HasCurlyBraces = false;
if (*LastEmitted == '{') { // ${variable}
@@ -786,33 +819,6 @@
}
break;
}
-case '{':
- ++LastEmitted; // Consume '{' character.
- if (CurVariant != -1) {
-std::cerr Nested variants found in inline asm string: '
- AsmStr '\n;
-exit(1);
- }
- CurVariant = 0; // We're in the first variant now.
- break;
-case '|':
- ++LastEmitted; // consume '|' character.
- if (CurVariant == -1) {
-std::cerr Found '|' character outside of variant in inline asm
- string: ' AsmStr '\n;
-exit(1);
- }
- ++CurVariant; // We're in the next variant.
- break;
-case '}':
- ++LastEmitted; // consume '}' character.
- if (CurVariant == -1) {
-std::cerr Found '}' character outside of variant in inline asm
- string: ' AsmStr '\n;
-exit(1);
- }
- CurVariant = -1;
- break;
}
}
O \n\t TAI-getInlineAsmEnd() \n;
___
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[llvm-commits] llvm-gcc patch
Applied, to match recent AsmPrinter.cpp change.
-Chris
Index: llvm-convert.cpp
===
--- llvm-convert.cpp(revision 118526)
+++ llvm-convert.cpp(working copy)
@@ -2474,6 +2474,12 @@
case 0: return Result; // End of string.
default: Result += InStr[-1]; break; // Normal character.
case '$': Result += $$; break; // Escape '$' characters.
+#ifdef ASSEMBLER_DIALECT
+// Note that we can't escape to ${, because that is the syntax
for vars.
+case '{': Result += $(; break; // Escape '{' character.
+case '}': Result += $); break; // Escape '}' character.
+case '|': Result += $|; break; // Escape '|' character.
+#endif
case '%': // GCC escape character.
char EscapedChar = *InStr++;
if (EscapedChar == '%') {// Escaped '%' character
___
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.78 - 1.79
---
Log message:
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.
---
Diffs of the changes: (+32 -0)
TargetLowering.h | 32
1 files changed, 32 insertions(+)
Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.78
llvm/include/llvm/Target/TargetLowering.h:1.79
--- llvm/include/llvm/Target/TargetLowering.h:1.78 Mon Sep 4 01:21:35 2006
+++ llvm/include/llvm/Target/TargetLowering.h Tue Oct 3 19:50:21 2006
@@ -215,16 +215,33 @@
/// expanded to some other code sequence, or the target has a custom expander
/// for it.
LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
+assert(Op != ISD::LOADX Should use getLoadXAction instead);
return (LegalizeAction)((OpActions[Op] (2*VT)) 3);
}
/// isOperationLegal - Return true if the specified operation is legal on
this
/// target.
bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
+assert(Op != ISD::LOADX Should use isLoadXLegal instead);
return getOperationAction(Op, VT) == Legal ||
getOperationAction(Op, VT) == Custom;
}
+ /// getLoadXAction - Return how this load with extension should be treated:
+ /// either it is legal, needs to be promoted to a larger size, needs to be
+ /// expanded to some other code sequence, or the target has a custom expander
+ /// for it.
+ LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const {
+return (LegalizeAction)((LoadXActions[LType] (2*VT)) 3);
+ }
+
+ /// isLoadXLegal - Return true if the specified load with extension is legal
+ /// is legal on this target.
+ bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const {
+return getLoadXAction(LType, VT) == Legal ||
+ getLoadXAction(LType, VT) == Custom;
+ }
+
/// getTypeToPromoteTo - If the action for this operation is to promote, this
/// method returns the ValueType to promote to.
MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
@@ -521,12 +538,22 @@
/// with the specified type and indicate what to do about it.
void setOperationAction(unsigned Op, MVT::ValueType VT,
LegalizeAction Action) {
+assert(Op != ISD::LOADX Should use setLoadXAction instead);
assert(VT 32 Op sizeof(OpActions)/sizeof(OpActions[0])
Table isn't big enough!);
OpActions[Op] = ~(uint64_t(3UL) VT*2);
OpActions[Op] |= (uint64_t)Action VT*2;
}
+ /// setLoadXAction - Indicate that the specified load with extension does not
+ /// work with the with specified type and indicate what to do about it.
+ void setLoadXAction(unsigned LType, MVT::ValueType VT, LegalizeAction
Action){
+assert(VT 32 LType sizeof(LoadXActions)/sizeof(LoadXActions[0])
+ Table isn't big enough!);
+LoadXActions[LType] = ~(uint64_t(3UL) VT*2);
+LoadXActions[LType] |= (uint64_t)Action VT*2;
+ }
+
/// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
/// promotion code defaults to trying a larger integer/fp until it can find
/// one that works. If that default is insufficient, this method can be used
@@ -773,6 +800,11 @@
/// non-legal value types are not described here.
uint64_t OpActions[156];
+ /// LoadXActions - For each load of load extension type and each value type,
+ /// keep a LegalizeAction that indicates how instruction selection should
deal
+ /// with the load.
+ uint64_t LoadXActions[ISD::LAST_LOADX_TYPE];
+
ValueTypeActionImpl ValueTypeActions;
std::vectordouble LegalFPImmediates;
___
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[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h SelectionDAGNodes.h
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAG.h updated: 1.131 - 1.132
SelectionDAGNodes.h updated: 1.148 - 1.149
---
Log message:
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.
---
Diffs of the changes: (+53 -8)
SelectionDAG.h |5 ++--
SelectionDAGNodes.h | 56 ++--
2 files changed, 53 insertions(+), 8 deletions(-)
Index: llvm/include/llvm/CodeGen/SelectionDAG.h
diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.131
llvm/include/llvm/CodeGen/SelectionDAG.h:1.132
--- llvm/include/llvm/CodeGen/SelectionDAG.h:1.131 Mon Oct 2 07:26:53 2006
+++ llvm/include/llvm/CodeGen/SelectionDAG.hTue Oct 3 19:50:21 2006
@@ -303,8 +303,9 @@
SDOperand SV);
SDOperand getVecLoad(unsigned Count, MVT::ValueType VT, SDOperand Chain,
SDOperand Ptr, SDOperand SV);
- SDOperand getExtLoad(unsigned Opcode, MVT::ValueType VT, SDOperand Chain,
- SDOperand Ptr, SDOperand SV, MVT::ValueType EVT);
+ SDOperand getExtLoad(ISD::LoadExtType LType, MVT::ValueType VT,
+ SDOperand Chain, SDOperand Ptr, SDOperand SV,
+ MVT::ValueType EVT);
// getSrcValue - construct a node to track a Value* through the backend
SDOperand getSrcValue(const Value* I, int offset = 0);
Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.148
llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.149
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.148 Sun Sep 24 14:43:29 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Tue Oct 3 19:50:21 2006
@@ -380,11 +380,11 @@
// the elements, a token chain, a pointer operand, and a SRCVALUE node.
VLOAD,
-// EXTLOAD, SEXTLOAD, ZEXTLOAD - These three operators all load a value
from
-// memory and extend them to a larger value (e.g. load a byte into a word
-// register). All three of these have four operands, a token chain, a
-// pointer to load from, a SRCVALUE for alias analysis, and a VALUETYPE
node
-// indicating the type to load.
+// Load a value from memory and extend them to a larger value (e.g. load a
+// byte into a word register). All three of these have four operands, a
+// token chain, a pointer to load from, a SRCVALUE for alias analysis, a
+// VALUETYPE node indicating the type to load, and an enum indicating what
+// sub-type of LOADX it is:
//
// SEXTLOAD loads the integer operand and sign extends it to a larger
// integer result type.
@@ -393,7 +393,7 @@
// EXTLOAD is used for three things: floating point extending loads,
// integer extending loads [the top bits are undefined], and
vector
// extending loads [load into low elt].
-EXTLOAD, SEXTLOAD, ZEXTLOAD,
+LOADX,
// TRUNCSTORE - This operators truncates (for integer) or rounds (for FP) a
// value and stores it to memory in one operation. This can be used for
@@ -534,6 +534,17 @@
bool isBuildVectorAllZeros(const SDNode *N);
//======//
+ /// LoadExtType enum - This enum defines the three variants of LOADEXT
+ /// (load with extension).
+ ///
+ enum LoadExtType {
+EXTLOAD,
+SEXTLOAD,
+ZEXTLOAD,
+LAST_LOADX_TYPE
+ };
+
+
//======//
/// ISD::CondCode enum - These are ordered carefully to make the bitfields
/// below work out, when considering SETFALSE (something that never exists
/// dynamically) as 0. U - Unsigned (for integer operands) or Unordered
@@ -671,6 +682,7 @@
inline unsigned getOpcode() const;
inline unsigned getNumOperands() const;
inline const SDOperand getOperand(unsigned i) const;
+ inline uint64_t getConstantOperandVal(unsigned i) const;
inline bool isTargetOpcode() const;
inline unsigned getTargetOpcode() const;
@@ -775,10 +787,15 @@
///
unsigned getNumOperands() const { return NumOperands; }
+ /// getConstantOperandVal - Helper method returns the integer value of a
+ /// ConstantSDNode operand.
+ uint64_t getConstantOperandVal(unsigned Num) const;
+
const SDOperand getOperand(unsigned Num) const {
assert(Num NumOperands Invalid child # of SDNode!);
return OperandList[Num];
}
+
typedef const SDOperand* op_iterator;
op_iterator op_begin() const { return OperandList; }
op_iterator op_end() const { return OperandList+NumOperands; }
@@ -997,6 +1014,9 @@
inline const SDOperand SDOperand::getOperand(unsigned i) const {
return Val-getOperand(i);
}
+inline uint64_t SDOperand::getConstantOperandVal(unsigned i) const {
+ return Val-getConstantOperandVal(i);
+}
inline bool SDOperand::isTargetOpcode() const {
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.204 - 1.205
LegalizeDAG.cpp updated: 1.401 - 1.402
SelectionDAG.cpp updated: 1.341 - 1.342
TargetLowering.cpp updated: 1.72 - 1.73
---
Log message:
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.
---
Diffs of the changes: (+102 -118)
DAGCombiner.cpp| 67 ++-
LegalizeDAG.cpp| 90 ++---
SelectionDAG.cpp | 25 --
TargetLowering.cpp | 38 ++
4 files changed, 102 insertions(+), 118 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.204
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.205
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.204 Tue Sep 26 12:44:58 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Oct 3 19:52:21 2006
@@ -217,7 +217,7 @@
SDOperand visitBRCOND(SDNode *N);
SDOperand visitBR_CC(SDNode *N);
SDOperand visitLOAD(SDNode *N);
-SDOperand visitXEXTLOAD(SDNode *N);
+SDOperand visitLOADX(SDNode *N);
SDOperand visitSTORE(SDNode *N);
SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
@@ -511,9 +511,7 @@
case ISD::BRCOND: return visitBRCOND(N);
case ISD::BR_CC: return visitBR_CC(N);
case ISD::LOAD: return visitLOAD(N);
- case ISD::EXTLOAD:
- case ISD::SEXTLOAD:
- case ISD::ZEXTLOAD: return visitXEXTLOAD(N);
+ case ISD::LOADX: return visitLOADX(N);
case ISD::STORE: return visitSTORE(N);
case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
@@ -1082,12 +1080,12 @@
SimplifyDemandedBits(SDOperand(N, 0)))
return SDOperand(N, 0);
// fold (zext_inreg (extload x)) - (zextload x)
- if (N0.getOpcode() == ISD::EXTLOAD) {
+ if (ISD::isEXTLoad(N0.Val)) {
MVT::ValueType EVT = castVTSDNode(N0.getOperand(3))-getVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
if (TLI.MaskedValueIsZero(N1, ~0ULL MVT::getSizeInBits(EVT))
-(!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
+(!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
N0.getOperand(1), N0.getOperand(2),
EVT);
@@ -1097,12 +1095,12 @@
}
}
// fold (zext_inreg (sextload x)) - (zextload x) iff load has one use
- if (N0.getOpcode() == ISD::SEXTLOAD N0.hasOneUse()) {
+ if (ISD::isSEXTLoad(N0.Val) N0.hasOneUse()) {
MVT::ValueType EVT = castVTSDNode(N0.getOperand(3))-getVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
if (TLI.MaskedValueIsZero(N1, ~0ULL MVT::getSizeInBits(EVT))
-(!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
+(!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
N0.getOperand(1), N0.getOperand(2),
EVT);
@@ -1115,8 +1113,8 @@
// fold (and (load x), 255) - (zextload x, i8)
// fold (and (extload x, i16), 255) - (zextload x, i8)
if (N1C
- (N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD ||
- N0.getOpcode() == ISD::ZEXTLOAD)
+ (N0.getOpcode() == ISD::LOAD || ISD::isEXTLoad(N0.Val) ||
+ ISD::isZEXTLoad(N0.Val))
N0.hasOneUse()) {
MVT::ValueType EVT, LoadedVT;
if (N1C-getValue() == 255)
@@ -1131,7 +1129,7 @@
LoadedVT = N0.getOpcode() == ISD::LOAD ? VT :
castVTSDNode(N0.getOperand(3))-getVT();
if (EVT != MVT::Other LoadedVT EVT
-(!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
+(!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
MVT::ValueType PtrType = N0.getOperand(1).getValueType();
// For big endian targets, we need to add an offset to the pointer to
load
// the correct bytes. For little endian systems, we merely need to read
@@ -1863,7 +1861,7 @@
// fold (sext (load x)) - (sext (truncate (sextload x)))
if (N0.getOpcode() == ISD::LOAD N0.hasOneUse()
- (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD,
N0.getValueType({
+ (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType({
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD,
[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td
Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.68 - 1.69 --- Log message: Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an extra operand to LOADX to specify the exact value extension type. --- Diffs of the changes: (+10 -12) TargetSelectionDAG.td | 22 ++ 1 files changed, 10 insertions(+), 12 deletions(-) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.68 llvm/lib/Target/TargetSelectionDAG.td:1.69 --- llvm/lib/Target/TargetSelectionDAG.td:1.68 Thu Jun 15 03:19:05 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Tue Oct 3 19:53:53 2006 @@ -164,10 +164,10 @@ SDTCisPtrTy1 ]; -def SDTExtLoad : SDTypeProfile1, 3, [ // extload - SDTCisPtrTy1, SDTCisVT2, OtherVT, SDTCisVT3, OtherVT +def SDTLoadX : SDTypeProfile1, 4, [ // loadX + SDTCisPtrTy1, SDTCisVT2, OtherVT, SDTCisVT3, OtherVT, SDTCisVT4, i32 ]; -def SDTIntExtLoad : SDTypeProfile1, 3, [ // sextload, zextload +def SDTIntExtLoad : SDTypeProfile1, 3, [ // extload, sextload, zextload SDTCisInt0, SDTCisPtrTy1, SDTCisVT2, OtherVT, SDTCisVT3, OtherVT ]; def SDTTruncStore : SDTypeProfile0, 4, [ // truncstore @@ -308,11 +308,9 @@ def load : SDNodeISD::LOAD , SDTLoad, [SDNPHasChain]; def store : SDNodeISD::STORE , SDTStore, [SDNPHasChain]; -// Do not use sextld and zextld directly. Use sextload and zextload (see -// below) which pass in a dummy srcvalue node which tblgen will skip over. -def sextld : SDNodeISD::SEXTLOAD , SDTIntExtLoad, [SDNPHasChain]; -def zextld : SDNodeISD::ZEXTLOAD , SDTIntExtLoad, [SDNPHasChain]; -def extld : SDNodeISD::EXTLOAD, SDTExtLoad,[SDNPHasChain]; +// Do not use loadx directly. Use extload, sextload and zextload (see below) +// which pass in a dummy srcvalue node which tblgen will skip over. +def loadx : SDNodeISD::LOADX , SDTLoadX, [SDNPHasChain]; def truncst: SDNodeISD::TRUNCSTORE , SDTTruncStore, [SDNPHasChain]; def vector_shuffle : SDNodeISD::VECTOR_SHUFFLE, SDTVecShuffle, []; @@ -415,12 +413,12 @@ def ineg : PatFrag(ops node:$in), (sub 0, node:$in); // extending load truncstore fragments. +def extload : PatFrag(ops node:$ptr, node:$vt), +(loadx node:$ptr, srcvalue:$dummy, node:$vt, 0); def sextload : PatFrag(ops node:$ptr, node:$vt), -(sextld node:$ptr, srcvalue:$dummy, node:$vt); +(loadx node:$ptr, srcvalue:$dummy, node:$vt, 1); def zextload : PatFrag(ops node:$ptr, node:$vt), -(zextld node:$ptr, srcvalue:$dummy, node:$vt); -def extload : PatFrag(ops node:$ptr, node:$vt), -(extld node:$ptr, srcvalue:$dummy, node:$vt); +(loadx node:$ptr, srcvalue:$dummy, node:$vt, 2); def truncstore: PatFrag(ops node:$val, node:$ptr, node:$vt), (truncst node:$val, node:$ptr, srcvalue:$dummy, node:$vt); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
Changes in directory llvm/lib/Target/Alpha: AlphaISelLowering.cpp updated: 1.62 - 1.63 --- Log message: Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an extra operand to LOADX to specify the exact value extension type. --- Diffs of the changes: (+10 -10) AlphaISelLowering.cpp | 20 ++-- 1 files changed, 10 insertions(+), 10 deletions(-) Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.62 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.63 --- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.62Sun Sep 24 14:46:56 2006 +++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Tue Oct 3 19:54:25 2006 @@ -48,19 +48,19 @@ addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass); addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass); - // setOperationAction(ISD::BRIND,MVT::i64, Expand); - setOperationAction(ISD::BR_CC,MVT::Other, Expand); - setOperationAction(ISD::SELECT_CC,MVT::Other, Expand); + setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote); + setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); - setOperationAction(ISD::EXTLOAD, MVT::i1, Promote); - setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); + setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote); + setLoadXAction(ISD::ZEXTLOAD, MVT::i32, Expand); - setOperationAction(ISD::ZEXTLOAD, MVT::i1, Promote); - setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand); + setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); + setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); + setLoadXAction(ISD::SEXTLOAD, MVT::i16, Expand); - setOperationAction(ISD::SEXTLOAD, MVT::i1, Promote); - setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand); - setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand); + // setOperationAction(ISD::BRIND,MVT::i64, Expand); + setOperationAction(ISD::BR_CC,MVT::Other, Expand); + setOperationAction(ISD::SELECT_CC,MVT::Other, Expand); setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64ISelLowering.cpp
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.54 - 1.55
IA64ISelLowering.cpp updated: 1.43 - 1.44
---
Log message:
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.
---
Diffs of the changes: (+10 -11)
IA64ISelDAGToDAG.cpp |3 +--
IA64ISelLowering.cpp | 18 +-
2 files changed, 10 insertions(+), 11 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.54
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.55
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.54 Tue Sep 12 16:02:20 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Tue Oct 3 19:55:13 2006
@@ -454,8 +454,7 @@
*/
case ISD::LOAD:
- case ISD::EXTLOAD: // FIXME: load -1, not 1, for bools?
- case ISD::ZEXTLOAD: {
+ case ISD::LOADX: { // FIXME: load -1, not 1, for bools?
SDOperand Chain = N-getOperand(0);
SDOperand Address = N-getOperand(1);
AddToISelQueue(Chain);
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.43
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.44
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.43 Tue Sep 12 16:02:20 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Tue Oct 3 19:55:13 2006
@@ -35,6 +35,15 @@
// register class for predicate registers
addRegisterClass(MVT::i1, IA64::PRRegisterClass);
+ setLoadXAction(ISD::EXTLOAD , MVT::i1 , Promote);
+
+ setLoadXAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
+
+ setLoadXAction(ISD::SEXTLOAD , MVT::i1 , Expand);
+ setLoadXAction(ISD::SEXTLOAD , MVT::i8 , Expand);
+ setLoadXAction(ISD::SEXTLOAD , MVT::i16 , Expand);
+ setLoadXAction(ISD::SEXTLOAD , MVT::i32 , Expand);
+
setOperationAction(ISD::BRIND, MVT::i64, Expand);
setOperationAction(ISD::BR_CC, MVT::Other, Expand);
setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
@@ -50,15 +59,6 @@
setSetCCResultType(MVT::i1);
setShiftAmountType(MVT::i64);
- setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote);
-
- setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
-
- setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
- setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand);
- setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand);
- setOperationAction(ISD::SEXTLOAD , MVT::i32 , Expand);
-
setOperationAction(ISD::FREM , MVT::f32 , Expand);
setOperationAction(ISD::FREM , MVT::f64 , Expand);
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[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/Sparc:
SparcISelDAGToDAG.cpp updated: 1.108 - 1.109
---
Log message:
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.
---
Diffs of the changes: (+4 -4)
SparcISelDAGToDAG.cpp |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.108
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.109
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.108 Tue Sep 12 16:03:10 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Tue Oct 3 19:55:51 2006
@@ -137,6 +137,9 @@
addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
+ // Turn FP extload into load/fextend
+ setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
+
// Custom legalize GlobalAddress nodes into LO/HI parts.
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
@@ -161,9 +164,6 @@
setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
- // Turn FP extload into load/fextend
- setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
-
// Sparc has no select or setcc: expand to SELECT_CC.
setOperationAction(ISD::SELECT, MVT::i32, Expand);
setOperationAction(ISD::SELECT, MVT::f32, Expand);
@@ -332,7 +332,7 @@
if (ObjectVT == MVT::i32) {
Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
} else {
- unsigned LoadOp =
+ ISD::LoadExtType LoadOp =
I-getType()-isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
// Sparc is big endian, so add an offset based on the ObjectVT.
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.208 - 1.209
---
Log message:
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.
---
Diffs of the changes: (+5 -5)
PPCISelLowering.cpp | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.208
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.209
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.208 Tue Sep 19 22:47:40 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Oct 3 19:55:33 2006
@@ -43,6 +43,10 @@
addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
+ // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
+ setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
+ setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
+
setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
@@ -51,10 +55,6 @@
setOperationAction(ISD::MEMSET, MVT::Other, Expand);
setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
- // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
- setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
- setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
-
// PowerPC has no SREM/UREM instructions
setOperationAction(ISD::SREM, MVT::i32, Expand);
setOperationAction(ISD::UREM, MVT::i32, Expand);
@@ -311,7 +311,7 @@
static bool isFloatingPointZero(SDOperand Op) {
if (ConstantFPSDNode *CFP = dyn_castConstantFPSDNode(Op))
return CFP-isExactlyValue(-0.0) || CFP-isExactlyValue(0.0);
- else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
+ else if (ISD::isEXTLoad(Op.Val) || Op.getOpcode() == ISD::LOAD) {
// Maybe this has already been legalized into the constant pool?
if (ConstantPoolSDNode *CP =
dyn_castConstantPoolSDNode(Op.getOperand(1)))
if (ConstantFP *CFP = dyn_castConstantFP(CP-getConstVal()))
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[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.266 - 1.267 --- Log message: Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an extra operand to LOADX to specify the exact value extension type. --- Diffs of the changes: (+2 -1) X86ISelLowering.cpp |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.266 llvm/lib/Target/X86/X86ISelLowering.cpp:1.267 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.266 Tue Oct 3 12:18:42 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue Oct 3 19:56:09 2006 @@ -75,6 +75,8 @@ if (Subtarget-is64Bit()) addRegisterClass(MVT::i64, X86::GR64RegisterClass); + setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand); + // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this // operation. setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); @@ -155,7 +157,6 @@ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); - setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand); setOperationAction(ISD::FREM , MVT::f64 , Expand); setOperationAction(ISD::CTPOP, MVT::i8 , Expand); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp
Changes in directory llvm/lib/CodeGen:
DwarfWriter.cpp updated: 1.76 - 1.77
---
Log message:
Work around for some problems with templates.
---
Diffs of the changes: (+6 -0)
DwarfWriter.cpp |6 ++
1 files changed, 6 insertions(+)
Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.76
llvm/lib/CodeGen/DwarfWriter.cpp:1.77
--- llvm/lib/CodeGen/DwarfWriter.cpp:1.76 Mon Sep 18 09:47:26 2006
+++ llvm/lib/CodeGen/DwarfWriter.cppTue Oct 3 20:43:13 2006
@@ -1526,6 +1526,12 @@
}
default: break;
}
+ } else if (SubprogramDesc *SubprogramTy = dyn_castSubprogramDesc(TyDesc)) {
+Slot = Ty = new DIE(DW_TAG_pointer_type);
+Ty-AddUInt(DW_AT_byte_size, 0, TAI-getAddressSize());
+Ty-AddString(DW_AT_name, DW_FORM_string, SubprogramTy-getName());
+Context-AddChild(Ty);
+return Slot;
}
assert(Ty Type not supported yet);
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[llvm-commits] CVS: llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
Changes in directory llvm/lib/Transforms/Utils:
BreakCriticalEdges.cpp updated: 1.33 - 1.34
---
Log message:
This case isn't implemented yet. It seems unlikely to be needed, but if it
ever is, we want to get an assert instead of silent bad codegen.
---
Diffs of the changes: (+2 -4)
BreakCriticalEdges.cpp |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
Index: llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
diff -u llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp:1.33
llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp:1.34
--- llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp:1.33 Tue Oct 3
02:02:02 2006
+++ llvm/lib/Transforms/Utils/BreakCriticalEdges.cppTue Oct 3 23:58:58 2006
@@ -253,11 +253,9 @@
if (DominanceFrontier *DF = P-getAnalysisToUpdateDominanceFrontier()) {
// If NewBBDominatesDestBB hasn't been computed yet, do so with DF.
if (!OtherPreds.empty()) {
-#if 0
// FIXME: IMPLEMENT THIS!
- OtherPreds.clear();
-#endif
- NewBBDominatesDestBB = false;
+ assert(0 Requiring domfrontiers but not idom/domtree/domset.
+ not implemented yet!);
}
// Since the new block is dominated by its only predecessor TIBB,
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[llvm-commits] CVS: llvm/lib/Target/X86/README-SSE.txt
Changes in directory llvm/lib/Target/X86:
README-SSE.txt updated: 1.5 - 1.6
---
Log message:
add a note :(
---
Diffs of the changes: (+24 -0)
README-SSE.txt | 24
1 files changed, 24 insertions(+)
Index: llvm/lib/Target/X86/README-SSE.txt
diff -u llvm/lib/Target/X86/README-SSE.txt:1.5
llvm/lib/Target/X86/README-SSE.txt:1.6
--- llvm/lib/Target/X86/README-SSE.txt:1.5 Mon Sep 11 00:35:17 2006
+++ llvm/lib/Target/X86/README-SSE.txt Wed Oct 4 00:52:13 2006
@@ -4,6 +4,30 @@
//===-===//
+There are serious issues folding loads into scalar sse intrinsics. For
+example, this:
+
+float minss4( float x, float *y ) {
+ return _mm_cvtss_f32(_mm_min_ss(_mm_set_ss(x),_mm_set_ss(*y)));
+}
+
+compiles to:
+
+_minss4:
+subl $4, %esp
+movl 12(%esp), %eax
+*** movss 8(%esp), %xmm0
+*** movss (%eax), %xmm1
+*** minss %xmm1, %xmm0
+movss %xmm0, (%esp)
+flds (%esp)
+addl $4, %esp
+ret
+
+Each operand of the minss is a load. At least one should be folded!
+
+//===-===//
+
When compiled with unsafemath enabled, main should enable SSE DAZ mode and
other fast SSE modes.
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