[llvm-commits] [llvm] r47188 - in /llvm/trunk: include/llvm/ADT/StringExtras.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp utils/TableGen/CodeGenDAGPatterns.cpp utils/TableGen/DAGISelEmitter.cpp
Author: pingbak
Date: Fri Feb 15 17:05:48 2008
New Revision: 47188
URL: http://llvm.org/viewvc/llvm-project?rev=47188view=rev
Log:
Make tblgen a little smarter about constants smaller than i32. Currently,
tblgen will complain if a sign-extended constant does not fit into a
data type smaller than i32, e.g., i16. This causes a problem when certain
hex constants are used, such as 0xff for byte masks or immediate xor
values.
tblgen will try the sign-extended value first and, if the sign extended
value would overflow, it tries to see if the unsigned value will fit.
Consequently, a software developer can now safely incant:
(XORHIr16 R16C:$rA, 0x)
which is somewhat clearer and more informative than incanting:
(XORHIr16 R16C:$rA, (i16 -1))
even if the two are bitwise equivalent.
Tblgen also outputs the 64-bit unsigned constant in the generated ISel code
when getTargetConstant() is invoked.
Modified:
llvm/trunk/include/llvm/ADT/StringExtras.h
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
Modified: llvm/trunk/include/llvm/ADT/StringExtras.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/StringExtras.h?rev=47188r1=47187r2=47188view=diff
==
--- llvm/trunk/include/llvm/ADT/StringExtras.h (original)
+++ llvm/trunk/include/llvm/ADT/StringExtras.h Fri Feb 15 17:05:48 2008
@@ -85,6 +85,10 @@
return utostr(static_castuint64_t(X));
}
+static inline std::string itohexstr(int64_t X) {
+ return utohexstr(static_castuint64_t(X));
+}
+
static inline std::string ftostr(double V) {
char Buffer[200];
sprintf(Buffer, %20.6e, V);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=47188r1=47187r2=47188view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Feb 15 17:05:48 2008
@@ -3852,6 +3852,13 @@
case Expand: assert(0 Shouldn't need to expand other operators here!);
case Legal:
Tmp1 = LegalizeOp(Node-getOperand(0));
+ if (TLI.getOperationAction(Node-getOpcode(), Node-getValueType(0)) ==
+ TargetLowering::Custom) {
+Tmp2 = TLI.LowerOperation(Result, DAG);
+if (Tmp2.Val) {
+ Tmp1 = Tmp2;
+}
+ }
Result = DAG.UpdateNodeOperands(Result, Tmp1);
break;
case Promote:
Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=47188r1=47187r2=47188view=diff
==
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Fri Feb 15 17:05:48 2008
@@ -702,10 +702,17 @@
// Make sure that the value is representable for this type.
if (Size 32) {
int Val = (II-getValue() (32-Size)) (32-Size);
-if (Val != II-getValue())
- TP.error(Sign-extended integer value ' +
itostr(II-getValue())+
- ' is out of range for type ' +
- getEnumName(getTypeNum(0)) + '!);
+if (Val != II-getValue()) {
+ // If sign-extended doesn't fit, does it fit as unsigned?
+ unsigned ValueMask = unsigned(MVT::getIntVTBitMask(VT));
+ unsigned UnsignedVal = unsigned(II-getValue());
+
+ if ((ValueMask UnsignedVal) != UnsignedVal) {
+ TP.error(Integer value ' + itostr(II-getValue())+
+' is out of range for type ' +
+getEnumName(getTypeNum(0)) + '!);
+ }
+ }
}
}
}
Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=47188r1=47187r2=47188view=diff
==
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Fri Feb 15 17:05:48 2008
@@ -730,8 +730,11 @@
const std::string VarName = N-getName();
std::string Val = VariableMap[VarName];
bool ModifiedVal = false;
- assert(!Val.empty()
- Variable referenced but not defined and not caught earlier!);
+ if (Val.empty()) {
+ cerr Variable ' VarName referenced but not defined
+ and not caught earlier!\n;
+ abort();
+ }
if (Val[0] == 'T' Val[1] == 'm' Val[2] == 'p') {
// Already selected this operand, just return the tmpval.
[llvm-commits] [llvm] r46968 - /llvm/trunk/docs/ReleaseNotes.html
Author: pingbak Date: Mon Feb 11 15:05:47 2008 New Revision: 46968 URL: http://llvm.org/viewvc/llvm-project?rev=46968view=rev Log: Added blurb for CellSPU progress Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=46968r1=46967r2=46968view=diff == --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Mon Feb 11 15:05:47 2008 @@ -124,8 +124,13 @@ pLLVM 2.2 includes several major new capabilities:/p ul -liScott Michel contributed an SPU backend, which generates code for the -vector coprocessors on the Cell processor. (Status?)/li +liA research team led by Scott Michel in the Computer Systems Research +Department at The Aerospace Corporation contributed the CellSPU backend, which +generates code for the vector coprocessors on the Sony/Toshiba/IBM Cell BE +processor. llvm-gcc 4.2 supports CellSPU as a 'configure' target and progress +is being made so that libgcc.a compiles cleanly. Notable pieces still in +development include full 64-bit integer and full double precision floating +point support./li liAnton and Duncan significantly improved llvm-gcc 4.2 support for the GCC Ada (GNAT) and Fortran (gfortran) front-ends. These front-ends should still be considered ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm-gcc-4.2] r46871 - /llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp
Author: pingbak
Date: Thu Feb 7 19:11:33 2008
New Revision: 46871
URL: http://llvm.org/viewvc/llvm-project?rev=46871view=rev
Log:
Move llvm_x86_should_pass_aggregate_in_memory so that it is declared before it
is used.
Modified:
llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp
Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp?rev=46871r1=46870r2=46871view=diff
==
--- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Thu Feb 7 19:11:33 2008
@@ -690,6 +690,48 @@
}
/* Target hook for llvm-abi.h. It returns true if an aggregate of the
+ specified type should be passed in a number of registers of mixed types.
+ It also returns a vector of types that correspond to the registers used
+ for parameter passing. This is only called for x86-32. */
+bool
+llvm_x86_32_should_pass_aggregate_in_mixed_regs(tree TreeType, const Type *Ty,
+std::vectorconst Type*
Elts){
+ // If this is a small fixed size type, investigate it.
+ HOST_WIDE_INT SrcSize = int_size_in_bytes(TreeType);
+ if (SrcSize = 0 || SrcSize 16)
+return false;
+
+ // X86-32 passes aggregates on the stack. If this is an extremely simple
+ // aggregate whose elements would be passed the same if passed as scalars,
+ // pass them that way in order to promote SROA on the caller and callee side.
+ // Note that we can't support passing all structs this way. For example,
+ // {i16, i16} should be passed in on 32-bit unit, which is not how i16, i16
+ // would be passed as stand-alone arguments.
+ const StructType *STy = dyn_castStructType(Ty);
+ if (!STy || STy-isPacked()) return false;
+
+ for (unsigned i = 0, e = STy-getNumElements(); i != e; ++i) {
+const Type *EltTy = STy-getElementType(i);
+// 32 and 64-bit integers are fine, as are float, double, and long double.
+if (EltTy == Type::Int32Ty ||
+EltTy == Type::Int64Ty ||
+EltTy-isFloatingPoint() ||
+isaPointerType(EltTy)) {
+ Elts.push_back(EltTy);
+ continue;
+}
+
+// TODO: Vectors are also ok to pass if they don't require extra alignment.
+// TODO: We can also pass structs like {i8, i32}.
+
+Elts.clear();
+return false;
+ }
+
+ return true;
+}
+
+/* Target hook for llvm-abi.h. It returns true if an aggregate of the
specified type should be passed in memory. */
bool llvm_x86_should_pass_aggregate_in_memory(tree TreeType, const Type *Ty) {
enum machine_mode Mode = ix86_getNaturalModeForType(TreeType);
@@ -800,46 +842,4 @@
}
return true;
}
-
-/* Target hook for llvm-abi.h. It returns true if an aggregate of the
- specified type should be passed in a number of registers of mixed types.
- It also returns a vector of types that correspond to the registers used
- for parameter passing. This is only called for x86-32. */
-bool
-llvm_x86_32_should_pass_aggregate_in_mixed_regs(tree TreeType, const Type *Ty,
-std::vectorconst Type*
Elts){
- // If this is a small fixed size type, investigate it.
- HOST_WIDE_INT SrcSize = int_size_in_bytes(TreeType);
- if (SrcSize = 0 || SrcSize 16)
-return false;
-
- // X86-32 passes aggregates on the stack. If this is an extremely simple
- // aggregate whose elements would be passed the same if passed as scalars,
- // pass them that way in order to promote SROA on the caller and callee side.
- // Note that we can't support passing all structs this way. For example,
- // {i16, i16} should be passed in on 32-bit unit, which is not how i16, i16
- // would be passed as stand-alone arguments.
- const StructType *STy = dyn_castStructType(Ty);
- if (!STy || STy-isPacked()) return false;
-
- for (unsigned i = 0, e = STy-getNumElements(); i != e; ++i) {
-const Type *EltTy = STy-getElementType(i);
-// 32 and 64-bit integers are fine, as are float, double, and long double.
-if (EltTy == Type::Int32Ty ||
-EltTy == Type::Int64Ty ||
-EltTy-isFloatingPoint() ||
-isaPointerType(EltTy)) {
- Elts.push_back(EltTy);
- continue;
-}
-
-// TODO: Vectors are also ok to pass if they don't require extra alignment.
-// TODO: We can also pass structs like {i8, i32}.
-
-Elts.clear();
-return false;
- }
-
- return true;
-}
/* LLVM LOCAL end (ENTIRE FILE!) */
___
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llvm-commits@cs.uiuc.edu
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[llvm-commits] [llvm] r46487 - /llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
Author: pingbak
Date: Mon Jan 28 20:29:31 2008
New Revision: 46487
URL: http://llvm.org/viewvc/llvm-project?rev=46487view=rev
Log:
Fix to bug 1951: tblgen gratuitously renames variables when no temporary was
generated. This feature would only show up in fairly complex patterns, such
as this one in CellSPU:
def : Pat(add (SPUhi tconstpool:$in, 0), (SPUlo tconstpool:$in, 0)),
(IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in);
which generated the following emit code:
SDNode *Emit_0(const SDOperand N, unsigned Opc0, unsigned Opc1, MVT::ValueType
VT0, MVT::ValueType VT1) DISABLE_INLINE {
SDOperand N0 = N.getOperand(0);
SDOperand N00 = N0.getOperand(0);
SDOperand N01 = N0.getOperand(1);
SDOperand N1 = N.getOperand(1);
SDOperand N10 = N1.getOperand(0);
SDOperand N11 = N1.getOperand(1);
SDOperand Tmp3(CurDAG-getTargetNode(Opc0, VT0, N00), 0);
return CurDAG-SelectNodeTo(N.Val, Opc1, VT1, Tmp3, Tmp2); /* Tmp2 s/b N00 */
}
Tested against the test suites without incident.
Modified:
llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=46487r1=46486r2=46487view=diff
==
--- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Mon Jan 28 20:29:31 2008
@@ -694,7 +694,9 @@
std::vectorstd::string NodeOps;
// This is something selected from the pattern we matched.
if (!N-getName().empty()) {
- std::string Val = VariableMap[N-getName()];
+ const std::string VarName = N-getName();
+ std::string Val = VariableMap[VarName];
+ bool ModifiedVal = false;
assert(!Val.empty()
Variable referenced but not defined and not caught earlier!);
if (Val[0] == 'T' Val[1] == 'm' Val[2] == 'p') {
@@ -708,6 +710,7 @@
if (!N-isLeaf() N-getOperator()-getName() == imm) {
assert(N-getExtTypes().size() == 1 Multiple types not handled!);
std::string CastType;
+std::string TmpVar = Tmp + utostr(ResNo);
switch (N-getTypeNum(0)) {
default:
cerr Cannot handle getEnumName(N-getTypeNum(0))
@@ -719,56 +722,53 @@
case MVT::i32: CastType = unsigned; break;
case MVT::i64: CastType = uint64_t; break;
}
-emitCode(SDOperand Tmp + utostr(ResNo) +
+emitCode(SDOperand + TmpVar +
= CurDAG-getTargetConstant((( + CastType +
) castConstantSDNode( + Val + )-getValue()), +
getEnumName(N-getTypeNum(0)) + ););
-NodeOps.push_back(Tmp + utostr(ResNo));
// Add TmpResNo to VariableMap, so that we don't multiply select this
// value if used multiple times by this pattern result.
-Val = Tmp+utostr(ResNo);
+Val = TmpVar;
+ModifiedVal = true;
+NodeOps.push_back(Val);
} else if (!N-isLeaf() N-getOperator()-getName() ==
texternalsym){
Record *Op = OperatorMap[N-getName()];
// Transform ExternalSymbol to TargetExternalSymbol
if (Op Op-getName() == externalsym) {
- emitCode(SDOperand Tmp + utostr(ResNo) + = CurDAG-getTarget
+ std::string TmpVar = Tmp+utostr(ResNo);
+ emitCode(SDOperand + TmpVar + = CurDAG-getTarget
ExternalSymbol(castExternalSymbolSDNode( +
Val + )-getSymbol(), +
getEnumName(N-getTypeNum(0)) + ););
- NodeOps.push_back(Tmp + utostr(ResNo));
// Add TmpResNo to VariableMap, so that we don't multiply select
// this value if used multiple times by this pattern result.
- Val = Tmp+utostr(ResNo);
-} else {
- NodeOps.push_back(Val);
+ Val = TmpVar;
+ ModifiedVal = true;
}
+NodeOps.push_back(Val);
} else if (!N-isLeaf() (N-getOperator()-getName() == tglobaladdr
|| N-getOperator()-getName() == tglobaltlsaddr)) {
Record *Op = OperatorMap[N-getName()];
// Transform GlobalAddress to TargetGlobalAddress
if (Op (Op-getName() == globaladdr ||
Op-getName() == globaltlsaddr)) {
- emitCode(SDOperand Tmp + utostr(ResNo) + = CurDAG-getTarget
+ std::string TmpVar = Tmp + utostr(ResNo);
+ emitCode(SDOperand + TmpVar + = CurDAG-getTarget
GlobalAddress(castGlobalAddressSDNode( + Val +
)-getGlobal(), + getEnumName(N-getTypeNum(0)) +
););
- NodeOps.push_back(Tmp + utostr(ResNo));
// Add TmpResNo to VariableMap, so that we don't multiply select
// this value if used multiple times by this pattern result.
- Val = Tmp+utostr(ResNo);
-} else {
- NodeOps.push_back(Val);
+
[llvm-commits] [llvm] r46142 - in /llvm/trunk: lib/Target/CellSPU/SPUISelDAGToDAG.cpp lib/Target/CellSPU/SPUISelLowering.cpp lib/Target/CellSPU/SPUInstrInfo.td lib/Target/CellSPU/SPUNodes.td test/Code
Author: pingbak
Date: Thu Jan 17 14:38:41 2008
New Revision: 46142
URL: http://llvm.org/viewvc/llvm-project?rev=46142view=rev
Log:
Forward progress: crtbegin.c now compiles successfully!
Fixed CellSPU's A-form (local store) address mode, so that all globals,
externals, constant pool and jump table symbols are now wrapped within
a SPUISD::AFormAddr pseudo-instruction. This now identifies all local
store memory addresses, although it requires a bit of legerdemain during
instruction selection to properly select loads to and stores from local
store, properly generating LQA instructions.
Also added mul_ops.ll test harness for exercising integer multiplication.
Added:
llvm/trunk/test/CodeGen/CellSPU/mul_ops.ll
Modified:
llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td
llvm/trunk/lib/Target/CellSPU/SPUNodes.td
llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll
llvm/trunk/test/CodeGen/CellSPU/struct_1.ll
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=46142r1=46141r2=46142view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Thu Jan 17 14:38:41 2008
@@ -159,16 +159,38 @@
int prefslot_byte; /// Byte offset of the preferred slot
unsigned brcc_eq_ins; /// br_cc equal instruction
unsigned brcc_neq_ins; /// br_cc not equal instruction
+unsigned load_aform;/// A-form load instruction for this VT
+unsigned store_aform; /// A-form store instruction for this VT
};
const valtype_map_s valtype_map[] = {
-{ MVT::i1, 0,3, 0, 0 },
-{ MVT::i8, 0,3, 0, 0 },
-{ MVT::i16, SPU::ORHIr16, 2, SPU::BRHZ, SPU::BRHNZ },
-{ MVT::i32, SPU::ORIr32, 0, SPU::BRZ, SPU::BRNZ },
-{ MVT::i64, SPU::ORIr64, 0, 0, 0 },
-{ MVT::f32, 0,0, 0, 0 },
-{ MVT::f64, 0,0, 0, 0 }
+{ MVT::i1,0,3, 0, 0, 0,
+ 0 },
+{ MVT::i8,SPU::ORBIr8, 3, 0, 0, SPU::LQAr8,
+ SPU::STQAr8 },
+{ MVT::i16, SPU::ORHIr16, 2, SPU::BRHZ, SPU::BRHNZ, SPU::LQAr16,
+ SPU::STQAr16 },
+{ MVT::i32, SPU::ORIr32, 0, SPU::BRZ, SPU::BRNZ, SPU::LQAr32,
+ SPU::STQAr32 },
+{ MVT::i64, SPU::ORIr64, 0, 0, 0, SPU::LQAr64,
+ SPU::STQAr64 },
+{ MVT::f32, 0,0, 0, 0, SPU::LQAf32,
+ SPU::STQAf32 },
+{ MVT::f64, 0,0, 0, 0, SPU::LQAf64,
+ SPU::STQAf64 },
+// vector types... (sigh!)
+{ MVT::v16i8, 0,0, 0, 0, SPU::LQAv16i8,
+ SPU::STQAv16i8 },
+{ MVT::v8i16, 0,0, 0, 0, SPU::LQAv8i16,
+ SPU::STQAv8i16 },
+{ MVT::v4i32, 0,0, 0, 0, SPU::LQAv4i32,
+ SPU::STQAv4i32 },
+{ MVT::v2i64, 0,0, 0, 0, SPU::LQAv2i64,
+ SPU::STQAv2i64 },
+{ MVT::v4f32, 0,0, 0, 0, SPU::LQAv4f32,
+ SPU::STQAv4f32 },
+{ MVT::v2f64, 0,0, 0, 0, SPU::LQAv2f64,
+ SPU::STQAv2f64 },
};
const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
@@ -465,14 +487,6 @@
int32_t offset = (int32_t) CN-getSignExtended();
unsigned Opc0 = Op0.getOpcode();
- if ((offset 0xf) != 0) {
-// Unaligned offset: punt and let X-form address handle it.
-// NOTE: This really doesn't have to be strictly 16-byte aligned,
-// since the load/store quadword instructions will implicitly
-// zero the lower 4 bits of the resulting address.
-return false;
- }
-
if (Opc0 == ISD::FrameIndex) {
FrameIndexSDNode *FI = dyn_castFrameIndexSDNode(Op0);
DEBUG(cerr SelectDFormAddr: ISD::ADD offset = offset
@@ -506,7 +520,8 @@
const SDOperand Op0 = N.getOperand(0); // Frame index/base
const SDOperand Op1 = N.getOperand(1); // Offset within base
-if (Op0.getOpcode() != SPUISD::XFormAddr) {
+if (Op0.getOpcode() == ISD::Constant
+|| Op0.getOpcode() == ISD::TargetConstant) {
ConstantSDNode *CN = castConstantSDNode(Op1);
assert(CN != 0 SelectDFormAddr/SPUISD::DFormAddr expecting
constant);
Base = CurDAG-getTargetConstant(CN-getValue(), PtrTy);
@@ -523,6 +538,11 @@
Index = CurDAG-getTargetFrameIndex(FI-getIndex(), PtrTy);
return true;
}
+ } else if (Opc == SPUISD::LDRESULT) {
+// It's a load result dereference
+Base = CurDAG-getTargetConstant(0, PtrTy);
+Index = N.getOperand(0);
+return true;
}
[llvm-commits] [llvm] r45882 - in /llvm/trunk: lib/Target/CellSPU/SPUISelDAGToDAG.cpp lib/Target/CellSPU/SPUISelLowering.cpp test/CodeGen/CellSPU/call_indirect.ll test/CodeGen/CellSPU/struct_1.ll test
Author: pingbak
Date: Fri Jan 11 15:01:19 2008
New Revision: 45882
URL: http://llvm.org/viewvc/llvm-project?rev=45882view=rev
Log:
More CellSPU refinements:
- struct_2.ll: Completely unaligned load/store testing
- call_indirect.ll, struct_1.ll: Add test lines to exercise
X-form [$reg($reg)] addressing
At this point, loads and stores should be under control (he says
in an optimistic tone of voice.)
Added:
llvm/trunk/test/CodeGen/CellSPU/struct_2.ll
Modified:
llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll
llvm/trunk/test/CodeGen/CellSPU/struct_1.ll
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=45882r1=45881r2=45882view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Fri Jan 11 15:01:19 2008
@@ -456,8 +456,9 @@
const SDOperand Op0 = N.getOperand(0); // Frame index/base
const SDOperand Op1 = N.getOperand(1); // Offset within base
-if (Op1.getOpcode() == ISD::Constant
-|| Op1.getOpcode() == ISD::TargetConstant) {
+if ((Op1.getOpcode() == ISD::Constant
+|| Op1.getOpcode() == ISD::TargetConstant)
+Op0.getOpcode() != SPUISD::XFormAddr) {
ConstantSDNode *CN = dyn_castConstantSDNode(Op1);
assert(CN != 0 SelectDFormAddr: Expected a constant);
@@ -499,12 +500,19 @@
} else
return false;
} else if (Opc == SPUISD::DFormAddr) {
-// D-Form address: This is pretty straightforward, naturally...
-ConstantSDNode *CN = castConstantSDNode(N.getOperand(1));
-assert(CN != 0 SelectDFormAddr/SPUISD::DFormAddr expecting constant);
-Base = CurDAG-getTargetConstant(CN-getValue(), PtrTy);
-Index = N.getOperand(0);
-return true;
+// D-Form address: This is pretty straightforward,
+// naturally... but make sure that this isn't a D-form address
+// with a X-form address embedded within:
+const SDOperand Op0 = N.getOperand(0); // Frame index/base
+const SDOperand Op1 = N.getOperand(1); // Offset within base
+
+if (Op0.getOpcode() != SPUISD::XFormAddr) {
+ ConstantSDNode *CN = castConstantSDNode(Op1);
+ assert(CN != 0 SelectDFormAddr/SPUISD::DFormAddr expecting
constant);
+ Base = CurDAG-getTargetConstant(CN-getValue(), PtrTy);
+ Index = Op0;
+ return true;
+}
} else if (Opc == ISD::FrameIndex) {
// Stack frame index must be less than 512 (divided by 16):
FrameIndexSDNode *FI = dyn_castFrameIndexSDNode(N);
@@ -564,6 +572,12 @@
Base = N;
Index = N.getOperand(1);
return true;
+ } else if (Opc == SPUISD::DFormAddr) {
+// Must be a D-form address with an X-form address embedded
+// within:
+Base = N.getOperand(0);
+Index = N.getOperand(1);
+return true;
} else if (N.getNumOperands() == 2) {
SDOperand N1 = N.getOperand(0);
SDOperand N2 = N.getOperand(1);
@@ -578,14 +592,14 @@
/*UNREACHED*/
} else {
cerr SelectXFormAddr: 2-operand unhandled operand:\n;
- N.Val-dump();
+ N.Val-dump(CurDAG);
cerr \n;
abort();
/*UNREACHED*/
}
} else {
cerr SelectXFormAddr: Unhandled operand type:\n;
-N.Val-dump();
+N.Val-dump(CurDAG);
cerr \n;
abort();
/*UNREACHED*/
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=45882r1=45881r2=45882view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Fri Jan 11 15:01:19 2008
@@ -90,13 +90,11 @@
const unsigned Opc = Op.getOpcode();
return (Opc == ISD::GlobalAddress
|| Opc == ISD::GlobalTLSAddress
-/* || Opc == ISD::FrameIndex */
|| Opc == ISD::JumpTable
|| Opc == ISD::ConstantPool
|| Opc == ISD::ExternalSymbol
|| Opc == ISD::TargetGlobalAddress
|| Opc == ISD::TargetGlobalTLSAddress
-/* || Opc == ISD::TargetFrameIndex */
|| Opc == ISD::TargetJumpTable
|| Opc == ISD::TargetConstantPool
|| Opc == ISD::TargetExternalSymbol
@@ -566,7 +564,7 @@
// Rotate the chunk if necessary
if (rotamt 0)
rotamt += 16;
-if (rotamt != 0) {
+if (rotamt != 0 || !was16aligned) {
SDVTList vecvts = DAG.getVTList(MVT::v16i8, MVT::Other);
if (was16aligned) {
@@ -574,10 +572,12 @@
Ops[1] = result;
Ops[2] = DAG.getConstant(rotamt, MVT::i16);
} else {
+ MVT::ValueType PtrVT =
[llvm-commits] [llvm] r45216 - in /llvm/trunk: lib/Target/CellSPU/SPUISelLowering.cpp lib/Target/CellSPU/SPUInstrInfo.cpp test/CodeGen/CellSPU/dg.exp test/CodeGen/CellSPU/or_ops.ll test/CodeGen/CellSP
Author: pingbak
Date: Wed Dec 19 14:15:47 2007
New Revision: 45216
URL: http://llvm.org/viewvc/llvm-project?rev=45216view=rev
Log:
Two more test cases: or_ops.ll (arithmetic or operations) and vecinsert.ll
(vector insertions)
Added:
llvm/trunk/test/CodeGen/CellSPU/dg.exp
llvm/trunk/test/CodeGen/CellSPU/or_ops.ll
llvm/trunk/test/CodeGen/CellSPU/vecinsert.ll
Modified:
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=45216r1=45215r2=45216view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Wed Dec 19 14:15:47 2007
@@ -880,13 +880,12 @@
assert((FP != 0)
LowerConstantFP: Node is not ConstantFPSDNode);
- const APFloat apf = FP-getValueAPF();
-
if (VT == MVT::f32) {
+float targetConst = FP-getValueAPF().convertToFloat();
return DAG.getNode(SPUISD::SFPConstant, VT,
- DAG.getTargetConstantFP(apf.convertToFloat(), VT));
+ DAG.getTargetConstantFP(targetConst, VT));
} else if (VT == MVT::f64) {
-uint64_t dbits = DoubleToBits(apf.convertToDouble());
+uint64_t dbits = DoubleToBits(FP-getValueAPF().convertToDouble());
return DAG.getNode(ISD::BIT_CONVERT, VT,
LowerConstant(DAG.getConstant(dbits, MVT::i64), DAG));
}
Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=45216r1=45215r2=45216view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Wed Dec 19 14:15:47 2007
@@ -98,13 +98,13 @@
destReg = MI.getOperand(0).getReg();
return true;
#endif
-// case SPU::ORv16i8_i8:
+ case SPU::ORv16i8_i8:
case SPU::ORv8i16_i16:
case SPU::ORv4i32_i32:
case SPU::ORv2i64_i64:
case SPU::ORv4f32_f32:
case SPU::ORv2f64_f64:
-// case SPU::ORi8_v16i8:
+ case SPU::ORi8_v16i8:
case SPU::ORi16_v8i16:
case SPU::ORi32_v4i32:
case SPU::ORi64_v2i64:
Added: llvm/trunk/test/CodeGen/CellSPU/dg.exp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/dg.exp?rev=45216view=auto
==
--- llvm/trunk/test/CodeGen/CellSPU/dg.exp (added)
+++ llvm/trunk/test/CodeGen/CellSPU/dg.exp Wed Dec 19 14:15:47 2007
@@ -0,0 +1,5 @@
+load_lib llvm.exp
+
+if { [llvm_supports_target CellSPU] } {
+ RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]]
+}
Added: llvm/trunk/test/CodeGen/CellSPU/or_ops.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/or_ops.ll?rev=45216view=auto
==
--- llvm/trunk/test/CodeGen/CellSPU/or_ops.ll (added)
+++ llvm/trunk/test/CodeGen/CellSPU/or_ops.ll Wed Dec 19 14:15:47 2007
@@ -0,0 +1,262 @@
+; RUN: llvm-as -o - %s | llc -march=cellspu %t1.s
+; RUN: grep and%t1.s | count 2
+; RUN: grep orc%t1.s | count 85
+; RUN: grep ori%t1.s | count 30
+; RUN: grep orhi %t1.s | count 30
+; RUN: grep orbi %t1.s | count 15
+
+; OR instruction generation:
+define 4 x i32 @or_v4i32_1(4 x i32 %arg1, 4 x i32 %arg2) {
+%A = or 4 x i32 %arg1, %arg2
+ret 4 x i32 %A
+}
+
+define 4 x i32 @or_v4i32_2(4 x i32 %arg1, 4 x i32 %arg2) {
+%A = or 4 x i32 %arg2, %arg1
+ret 4 x i32 %A
+}
+
+define 8 x i16 @or_v8i16_1(8 x i16 %arg1, 8 x i16 %arg2) {
+%A = or 8 x i16 %arg1, %arg2
+ret 8 x i16 %A
+}
+
+define 8 x i16 @or_v8i16_2(8 x i16 %arg1, 8 x i16 %arg2) {
+%A = or 8 x i16 %arg2, %arg1
+ret 8 x i16 %A
+}
+
+define 16 x i8 @or_v16i8_1(16 x i8 %arg1, 16 x i8 %arg2) {
+%A = or 16 x i8 %arg2, %arg1
+ret 16 x i8 %A
+}
+
+define 16 x i8 @or_v16i8_2(16 x i8 %arg1, 16 x i8 %arg2) {
+%A = or 16 x i8 %arg1, %arg2
+ret 16 x i8 %A
+}
+
+define i32 @or_i32_1(i32 %arg1, i32 %arg2) {
+ %A = or i32 %arg2, %arg1
+ ret i32 %A
+}
+
+define i32 @or_i32_2(i32 %arg1, i32 %arg2) {
+ %A = or i32 %arg1, %arg2
+ ret i32 %A
+}
+
+define i16 @or_i16_1(i16 %arg1, i16 %arg2) {
+ %A = or i16 %arg2, %arg1
+ ret i16 %A
+}
+
+define i16 @or_i16_2(i16 %arg1, i16 %arg2) {
+ %A = or i16 %arg1, %arg2
+ ret i16 %A
+}
+
+define i8 @or_i8_1(i8 %arg1, i8 %arg2) {
+ %A = or i8 %arg2, %arg1
+ ret i8 %A
+}
+
+define i8 @or_i8_2(i8 %arg1, i8 %arg2) {
+ %A = or i8 %arg1, %arg2
+ ret i8 %A
+}
+
+; ORC instruction generation:
+define 4 x i32 @orc_v4i32_1(4
[llvm-commits] [llvm] r45217 - in /llvm/trunk/test/CodeGen/CellSPU: call.ll ctpop.ll dp_farith.ll eqv.ll fcmp.ll fdiv.ll fneg-fabs.ll int2fp.ll rotate_ops.ll select_bits.ll shift_ops.ll sp_farith.ll
Author: pingbak
Date: Wed Dec 19 14:50:49 2007
New Revision: 45217
URL: http://llvm.org/viewvc/llvm-project?rev=45217view=rev
Log:
More working CellSPU test cases:
- call.ll: Function call
- ctpop.ll: Count population
- dp_farith.ll: DP arithmetic
- eqv.ll: Equivalence primitives
- fcmp.ll: SP comparisons
- fdiv.ll: SP division
- fneg-fabs.ll: SP negation, aboslute value
- int2fp.ll: Integer - SP conversion
- rotate_ops.ll: Rotation primitives
- select_bits.ll: (a c) | (b ~c) bit selection
- shift_ops.ll: Shift primitives
- sp_farith.ll: SP arithmentic
Added:
llvm/trunk/test/CodeGen/CellSPU/call.ll
llvm/trunk/test/CodeGen/CellSPU/ctpop.ll
llvm/trunk/test/CodeGen/CellSPU/dp_farith.ll
llvm/trunk/test/CodeGen/CellSPU/eqv.ll
llvm/trunk/test/CodeGen/CellSPU/fcmp.ll
llvm/trunk/test/CodeGen/CellSPU/fdiv.ll
llvm/trunk/test/CodeGen/CellSPU/fneg-fabs.ll
llvm/trunk/test/CodeGen/CellSPU/int2fp.ll
llvm/trunk/test/CodeGen/CellSPU/rotate_ops.ll
llvm/trunk/test/CodeGen/CellSPU/select_bits.ll
llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll
llvm/trunk/test/CodeGen/CellSPU/sp_farith.ll
Added: llvm/trunk/test/CodeGen/CellSPU/call.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/call.ll?rev=45217view=auto
==
--- llvm/trunk/test/CodeGen/CellSPU/call.ll (added)
+++ llvm/trunk/test/CodeGen/CellSPU/call.ll Wed Dec 19 14:50:49 2007
@@ -0,0 +1,20 @@
+; RUN: llvm-as -o - %s | llc -march=cellspu %t1.s
+; RUN: grep brsl%t1.s | count 1
+; RUN: grep brasl %t1.s | count 1
+
+target datalayout =
E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128
+target triple = spu
+
+define i32 @main() {
+entry:
+ %a = call i32 @stub_1(i32 1, float 0x400921FA)
+ call void @extern_stub_1(i32 %a, i32 4)
+ ret i32 %a
+}
+
+declare void @extern_stub_1(i32, i32)
+
+define i32 @stub_1(i32 %x, float %y) {
+entry:
+ ret i32 0
+}
Added: llvm/trunk/test/CodeGen/CellSPU/ctpop.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/ctpop.ll?rev=45217view=auto
==
--- llvm/trunk/test/CodeGen/CellSPU/ctpop.ll (added)
+++ llvm/trunk/test/CodeGen/CellSPU/ctpop.ll Wed Dec 19 14:50:49 2007
@@ -0,0 +1,28 @@
+; RUN: llvm-as -o - %s | llc -march=cellspu %t1.s
+; RUN: grep cntb%t1.s | count 3
+; RUN: grep andi%t1.s | count 3
+; RUN: grep rotmi %t1.s | count 2
+; RUN: grep rothmi %t1.s | count 1
+
+declare i32 @llvm.ctpop.i8(i8)
+declare i32 @llvm.ctpop.i16(i16)
+declare i32 @llvm.ctpop.i32(i32)
+
+define i32 @test_i8(i8 %X) {
+ call i32 @llvm.ctpop.i8(i8 %X)
+ %Y = bitcast i32 %1 to i32
+ ret i32 %Y
+}
+
+define i32 @test_i16(i16 %X) {
+call i32 @llvm.ctpop.i16(i16 %X)
+ %Y = bitcast i32 %1 to i32
+ret i32 %Y
+}
+
+define i32 @test_i32(i32 %X) {
+call i32 @llvm.ctpop.i32(i32 %X)
+ %Y = bitcast i32 %1 to i32
+ret i32 %Y
+}
+
Added: llvm/trunk/test/CodeGen/CellSPU/dp_farith.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/dp_farith.ll?rev=45217view=auto
==
--- llvm/trunk/test/CodeGen/CellSPU/dp_farith.ll (added)
+++ llvm/trunk/test/CodeGen/CellSPU/dp_farith.ll Wed Dec 19 14:50:49 2007
@@ -0,0 +1,100 @@
+; RUN: llvm-as -o - %s | llc -march=cellspu %t1.s
+; RUN: grep dfa%t1.s | count 2
+; RUN: grep dfs%t1.s | count 2
+; RUN: grep dfm%t1.s | count 6
+; RUN: grep dfma %t1.s | count 2
+; RUN: grep dfms %t1.s | count 2
+; RUN: grep dfnms %t1.s | count 4
+;
+; This file includes double precision floating point arithmetic instructions
+
+define double @fadd(double %arg1, double %arg2) {
+ %A = add double %arg1, %arg2
+ ret double %A
+}
+
+define 2 x double @fadd_vec(2 x double %arg1, 2 x double %arg2) {
+ %A = add 2 x double %arg1, %arg2
+ ret 2 x double %A
+}
+
+define double @fsub(double %arg1, double %arg2) {
+ %A = sub double %arg1, %arg2
+ ret double %A
+}
+
+define 2 x double @fsub_vec(2 x double %arg1, 2 x double %arg2) {
+ %A = sub 2 x double %arg1, %arg2
+ ret 2 x double %A
+}
+
+define double @fmul(double %arg1, double %arg2) {
+ %A = mul double %arg1, %arg2
+ ret double %A
+}
+
+define 2 x double @fmul_vec(2 x double %arg1, 2 x double %arg2) {
+ %A = mul 2 x double %arg1, %arg2
+ ret 2 x double %A
+}
+
+define double @fma(double %arg1, double %arg2, double %arg3) {
+ %A = mul double %arg1, %arg2
+ %B = add double %A, %arg3
+ ret double %B
+}
+
+define 2 x double @fma_vec(2 x double %arg1, 2 x double %arg2, 2 x
double %arg3) {
+ %A = mul 2 x double %arg1, %arg2
+ %B = add 2 x double %A, %arg3
+ ret 2 x double %B
+}
+
[llvm-commits] [llvm] r45219 - in /llvm/trunk: lib/Target/CellSPU/SPUISelLowering.cpp test/CodeGen/CellSPU/extract_elt.ll
Author: pingbak
Date: Wed Dec 19 15:17:42 2007
New Revision: 45219
URL: http://llvm.org/viewvc/llvm-project?rev=45219view=rev
Log:
CellSPU testcase, extract_elt.ll: extract vector element.
Added:
llvm/trunk/test/CodeGen/CellSPU/extract_elt.ll
Modified:
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=45219r1=45218r2=45219view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Wed Dec 19 15:17:42 2007
@@ -2101,7 +2101,7 @@
}
// Need to generate shuffle mask and extract:
- int prefslot_begin, prefslot_end;
+ int prefslot_begin = -1, prefslot_end = -1;
int elt_byte = EltNo * MVT::getSizeInBits(VT) / 8;
switch (VT) {
@@ -2123,6 +2123,9 @@
}
}
+ assert(prefslot_begin != -1 prefslot_end != -1
+LowerEXTRACT_VECTOR_ELT: preferred slots uninitialized);
+
for (int i = 0; i 16; ++i) {
// zero fill uppper part of preferred slot, don't care about the
// other slots:
@@ -2134,7 +2137,7 @@
? 0x80
: elt_byte + (i - prefslot_begin));
- ShufMask[i] = DAG.getConstant(mask_val, MVT::i16);
+ ShufMask[i] = DAG.getConstant(mask_val, MVT::i8);
} else
ShufMask[i] = ShufMask[i % (prefslot_end + 1)];
}
Added: llvm/trunk/test/CodeGen/CellSPU/extract_elt.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/extract_elt.ll?rev=45219view=auto
==
--- llvm/trunk/test/CodeGen/CellSPU/extract_elt.ll (added)
+++ llvm/trunk/test/CodeGen/CellSPU/extract_elt.ll Wed Dec 19 15:17:42 2007
@@ -0,0 +1,175 @@
+; RUN: llvm-as -o - %s | llc -march=cellspu %t1.s
+; RUN: llvm-as -o - %s | llc -march=cellspu -mattr=large_mem %t2.s
+; RUN: grep shufb %t1.s | count 27
+; RUN: grep lqa %t1.s | count 27
+; RUN: grep lqx %t2.s | count 27
+; RUN: grep space %t1.s | count 8
+; RUN: grep byte %t1.s | count 424
+
+define i32 @i32_extract_0(4 x i32 %v) {
+entry:
+ %a = extractelement 4 x i32 %v, i32 0
+ ret i32 %a
+}
+
+define i32 @i32_extract_1(4 x i32 %v) {
+entry:
+ %a = extractelement 4 x i32 %v, i32 1
+ ret i32 %a
+}
+
+define i32 @i32_extract_2(4 x i32 %v) {
+entry:
+ %a = extractelement 4 x i32 %v, i32 2
+ ret i32 %a
+}
+
+define i32 @i32_extract_3(4 x i32 %v) {
+entry:
+ %a = extractelement 4 x i32 %v, i32 3
+ ret i32 %a
+}
+
+define i16 @i16_extract_0(8 x i16 %v) {
+entry:
+ %a = extractelement 8 x i16 %v, i32 0
+ ret i16 %a
+}
+
+define i16 @i16_extract_1(8 x i16 %v) {
+entry:
+ %a = extractelement 8 x i16 %v, i32 1
+ ret i16 %a
+}
+
+define i16 @i16_extract_2(8 x i16 %v) {
+entry:
+ %a = extractelement 8 x i16 %v, i32 2
+ ret i16 %a
+}
+
+define i16 @i16_extract_3(8 x i16 %v) {
+entry:
+ %a = extractelement 8 x i16 %v, i32 3
+ ret i16 %a
+}
+
+define i16 @i16_extract_4(8 x i16 %v) {
+entry:
+ %a = extractelement 8 x i16 %v, i32 4
+ ret i16 %a
+}
+
+define i16 @i16_extract_5(8 x i16 %v) {
+entry:
+ %a = extractelement 8 x i16 %v, i32 5
+ ret i16 %a
+}
+
+define i16 @i16_extract_6(8 x i16 %v) {
+entry:
+ %a = extractelement 8 x i16 %v, i32 6
+ ret i16 %a
+}
+
+define i16 @i16_extract_7(8 x i16 %v) {
+entry:
+ %a = extractelement 8 x i16 %v, i32 7
+ ret i16 %a
+}
+
+define i8 @i8_extract_0(16 x i8 %v) {
+entry:
+ %a = extractelement 16 x i8 %v, i32 0
+ ret i8 %a
+}
+
+define i8 @i8_extract_1(16 x i8 %v) {
+entry:
+ %a = extractelement 16 x i8 %v, i32 1
+ ret i8 %a
+}
+
+define i8 @i8_extract_2(16 x i8 %v) {
+entry:
+ %a = extractelement 16 x i8 %v, i32 2
+ ret i8 %a
+}
+
+define i8 @i8_extract_3(16 x i8 %v) {
+entry:
+ %a = extractelement 16 x i8 %v, i32 3
+ ret i8 %a
+}
+
+define i8 @i8_extract_4(16 x i8 %v) {
+entry:
+ %a = extractelement 16 x i8 %v, i32 4
+ ret i8 %a
+}
+
+define i8 @i8_extract_5(16 x i8 %v) {
+entry:
+ %a = extractelement 16 x i8 %v, i32 5
+ ret i8 %a
+}
+
+define i8 @i8_extract_6(16 x i8 %v) {
+entry:
+ %a = extractelement 16 x i8 %v, i32 6
+ ret i8 %a
+}
+
+define i8 @i8_extract_7(16 x i8 %v) {
+entry:
+ %a = extractelement 16 x i8 %v, i32 7
+ ret i8 %a
+}
+
+define i8 @i8_extract_8(16 x i8 %v) {
+entry:
+ %a = extractelement 16 x i8 %v, i32 8
+ ret i8 %a
+}
+
+define i8 @i8_extract_9(16 x i8 %v) {
+entry:
+ %a = extractelement 16 x i8 %v, i32 9
+ ret i8 %a
+}
+
+define i8 @i8_extract_10(16 x i8 %v) {
+entry:
+ %a = extractelement 16 x i8 %v, i32 10
+ ret i8 %a
+}
+
+define i8 @i8_extract_11(16 x i8 %v) {
+entry:
+ %a = extractelement 16 x i8 %v, i32 11
+ ret i8 %a
+}
+
+define i8 @i8_extract_12(16 x i8 %v) {
+entry:
+ %a = extractelement 16 x i8 %v, i32 12
+ ret i8 %a
+}
+
+define i8 @i8_extract_13(16 x i8 %v) {
+entry:
+ %a = extractelement 16 x i8 %v, i32 13
+
[llvm-commits] [llvm] r45242 - in /llvm/trunk: lib/Target/CellSPU/SPUAsmPrinter.cpp lib/Target/CellSPU/SPUISelDAGToDAG.cpp lib/Target/CellSPU/SPUISelLowering.cpp lib/Target/CellSPU/SPUInstrInfo.cpp li
Author: pingbak
Date: Wed Dec 19 18:44:13 2007
New Revision: 45242
URL: http://llvm.org/viewvc/llvm-project?rev=45242view=rev
Log:
More working CellSPU tests:
- vec_const.ll: Vector constant loads
- immed64.ll: i64, f64 constant loads
Added:
llvm/trunk/test/CodeGen/CellSPU/immed64.ll
llvm/trunk/test/CodeGen/CellSPU/vec_const.ll
Modified:
llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td
llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
Modified: llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp?rev=45242r1=45241r2=45242view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp Wed Dec 19 18:44:13 2007
@@ -635,7 +635,7 @@
DW.EndModule();
// Emit ident information
- O \t.ident\t\(llvm 1.9+) STI CBEA Cell SPU backend\\n;
+ O \t.ident\t\(llvm 2.2+) STI CBEA Cell SPU backend\\n;
return AsmPrinter::doFinalization(M);
}
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=45242r1=45241r2=45242view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Wed Dec 19 18:44:13 2007
@@ -155,7 +155,7 @@
}
//===--===//
- //! MVT::ValueType to useful stuff structure:
+ //! MVT::ValueType to useful stuff mapping structure:
struct valtype_map_s {
MVT::ValueType VT;
@@ -166,13 +166,13 @@
};
const valtype_map_s valtype_map[] = {
-{ MVT::i1, 0,3, 0, 0 },
-{ MVT::i8, 0,3, 0, 0 },
-{ MVT::i16, SPU::ORHIr16, 2, SPU::BRHZ, SPU::BRHNZ },
-{ MVT::i32, SPU::ORIr32, 0, SPU::BRZ, SPU::BRNZ },
-{ MVT::i64, SPU::ORIr64, 0, 0, 0 },
-{ MVT::f32, SPU::ORIf32, 0, 0, 0 },
-{ MVT::f64, SPU::ORIf64, 0, 0, 0 }
+{ MVT::i1, 0,3, 0, 0 },
+{ MVT::i8, 0,3, 0, 0 },
+{ MVT::i16, SPU::ORHIr16, 2, SPU::BRHZ, SPU::BRHNZ },
+{ MVT::i32, SPU::ORIr32, 0, SPU::BRZ, SPU::BRNZ },
+{ MVT::i64, SPU::ORIr64, 0, 0, 0 },
+{ MVT::f32, 0,0, 0, 0 },
+{ MVT::f64, 0,0, 0, 0 }
};
const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
@@ -605,23 +605,32 @@
unsigned VT = N-getValueType(0);
SDOperand Arg = N-getOperand(0);
SDOperand Chain = N-getOperand(1);
-SDOperand Zero = CurDAG-getTargetConstant(0, VT);
SDNode *Result;
-const valtype_map_s *vtm = getValueTypeMapEntry(VT);
-
-if (vtm-ldresult_ins == 0) {
- cerr LDRESULT for unsupported type:
-MVT::getValueTypeString(VT)
-\n;
- abort();
-} else
- Opc = vtm-ldresult_ins;
AddToISelQueue(Arg);
-AddToISelQueue(Zero);
-AddToISelQueue(Chain);
-Result = CurDAG-SelectNodeTo(N, Opc, VT, MVT::Other, Arg, Zero, Chain);
+if (!MVT::isFloatingPoint(VT)) {
+ SDOperand Zero = CurDAG-getTargetConstant(0, VT);
+ const valtype_map_s *vtm = getValueTypeMapEntry(VT);
+
+ if (vtm-ldresult_ins == 0) {
+ cerr LDRESULT for unsupported type:
+ MVT::getValueTypeString(VT)
+ \n;
+ abort();
+ } else
+ Opc = vtm-ldresult_ins;
+
+ AddToISelQueue(Zero);
+ Result = CurDAG-SelectNodeTo(N, Opc, VT, MVT::Other, Arg, Zero, Chain);
+} else {
+ Result =
+ CurDAG-SelectNodeTo(N, (VT == MVT::f32 ? SPU::ORf32 : SPU::ORf64),
+MVT::Other, Arg, Arg, Chain);
+}
+
Chain = SDOperand(Result, 1);
+AddToISelQueue(Chain);
+
return Result;
}
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=45242r1=45241r2=45242view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Wed Dec 19 18:44:13 2007
@@ -263,10 +263,10 @@
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
- setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
- setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
- setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
-
[llvm-commits] [llvm] r45196 - in /llvm/trunk: lib/Target/CellSPU/SPUISelDAGToDAG.cpp lib/Target/CellSPU/SPUISelLowering.cpp lib/Target/CellSPU/SPUInstrInfo.cpp lib/Target/CellSPU/SPUInstrInfo.td lib/
Author: pingbak
Date: Wed Dec 19 01:35:06 2007
New Revision: 45196
URL: http://llvm.org/viewvc/llvm-project?rev=45196view=rev
Log:
Add new immed16.ll test case, fix CellSPU errata to make test case work.
Added:
llvm/trunk/test/CodeGen/CellSPU/immed16.ll
Modified:
llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td
llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=45196r1=45195r2=45196view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Wed Dec 19 01:35:06 2007
@@ -597,7 +597,7 @@
int FI = castFrameIndexSDNode(N)-getIndex();
SDOperand TFI = CurDAG-getTargetFrameIndex(FI, SPUtli.getPointerTy());
-DEBUG(cerr SPUDAGToDAGISel: Replacing FrameIndex with AI32 TFI, 0\n);
+DEBUG(cerr SPUDAGToDAGISel: Replacing FrameIndex with AI32 FI, 0\n);
return CurDAG-SelectNodeTo(N, SPU::AIr32, Op.getValueType(), TFI,
CurDAG-getTargetConstant(0, MVT::i32));
} else if (Opc == SPUISD::LDRESULT) {
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=45196r1=45195r2=45196view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Wed Dec 19 01:35:06 2007
@@ -670,6 +670,11 @@
SDOperand ptrOp;
int offset;
+if (basep.getOpcode() == ISD::FrameIndex) {
+ // FrameIndex nodes are always properly aligned. Really.
+ return SDOperand();
+}
+
if (basep.getOpcode() == ISD::ADD) {
const ConstantSDNode *CN =
castConstantSDNode(basep.Val-getOperand(1));
assert(CN != NULL
@@ -694,13 +699,10 @@
stVecVT = MVT::v16i8;
vecVT = MVT::getVectorType(VT, (128 / MVT::getSizeInBits(VT)));
-// Realign the pointer as a D-Form address (ptrOp is the pointer,
-// to force a register load with the address; basep is the actual
-// dform addr offs($reg).
-ptrOp = DAG.getNode(SPUISD::DFormAddr, PtrVT, ptrOp,
- DAG.getConstant(0, PtrVT));
-basep = DAG.getNode(SPUISD::DFormAddr, PtrVT,
- ptrOp, DAG.getConstant((offset ~0xf), PtrVT));
+// Realign the pointer as a D-Form address (ptrOp is the pointer, basep is
+// the actual dform addr offs($reg).
+basep = DAG.getNode(SPUISD::DFormAddr, PtrVT, ptrOp,
+DAG.getConstant((offset ~0xf), PtrVT));
// Create the 16-byte aligned vector load
SDOperand alignLoad =
Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=45196r1=45195r2=45196view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Wed Dec 19 01:35:06 2007
@@ -62,7 +62,6 @@
case SPU::AHIvec:
case SPU::AHIr16:
case SPU::AIvec:
- case SPU::AIr32:
assert(MI.getNumOperands() == 3
MI.getOperand(0).isRegister()
MI.getOperand(1).isRegister()
@@ -74,6 +73,19 @@
return true;
}
break;
+ case SPU::AIr32:
+assert(MI.getNumOperands() == 3
+ wrong number of operands to AIr32);
+if (MI.getOperand(0).isRegister()
+(MI.getOperand(1).isRegister() ||
+ MI.getOperand(1).isFrameIndex())
+(MI.getOperand(2).isImmediate()
+ MI.getOperand(2).getImmedValue() == 0)) {
+ sourceReg = MI.getOperand(1).getReg();
+ destReg = MI.getOperand(0).getReg();
+ return true;
+}
+break;
#if 0
case SPU::ORIf64:
case SPU::ORIf32:
Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td?rev=45196r1=45195r2=45196view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td Wed Dec 19 01:35:06 2007
@@ -3476,10 +3476,8 @@
// Force load of global address to a register. These forms show up in
// SPUISD::DFormAddr pseudo instructions:
-/*
def : Pat(add tglobaladdr:$in, 0), (ILAlsa tglobaladdr:$in);
def : Pat(add tconstpool:$in, 0), (ILAlsa tglobaladdr:$in);
def : Pat(add tjumptable:$in, 0), (ILAlsa tglobaladdr:$in);
- */
// Instrinsics:
include
[llvm-commits] [llvm] r45050 - in /llvm/trunk: lib/Target/CellSPU/SPU.h lib/Target/CellSPU/SPUISelDAGToDAG.cpp lib/Target/CellSPU/SPUInstrInfo.td lib/Target/CellSPU/SPUOperands.td test/CodeGen/CellSPU
Author: pingbak
Date: Fri Dec 14 18:38:50 2007
New Revision: 45050
URL: http://llvm.org/viewvc/llvm-project?rev=45050view=rev
Log:
Start committing working test cases for CellSPU.
Added:
llvm/trunk/test/CodeGen/CellSPU/
llvm/trunk/test/CodeGen/CellSPU/and_ops.ll
Modified:
llvm/trunk/lib/Target/CellSPU/SPU.h
llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td
llvm/trunk/lib/Target/CellSPU/SPUOperands.td
Modified: llvm/trunk/lib/Target/CellSPU/SPU.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU.h?rev=45050r1=45049r2=45050view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPU.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPU.h Fri Dec 14 18:38:50 2007
@@ -25,7 +25,7 @@
FunctionPass *createSPUISelDag(SPUTargetMachine TM);
FunctionPass *createSPUAsmPrinterPass(std::ostream o, SPUTargetMachine tm);
- /* Utility functions/predicates/etc used all over the place: */
+ /*--== Utility functions/predicates/etc used all over the place: --==*/
//! Predicate test for a signed 10-bit value
/*!
\param Value The input value to be tested
@@ -54,6 +54,33 @@
inline bool isS10Constant(uint64_t Value) {
return (Value = ((1 9) - 1));
}
+
+ //! Predicate test for an unsigned 10-bit value
+ /*!
+\param Value The input value to be tested
+
+This predicate tests for an unsigned 10-bit value, returning the 10-bit
value
+as a short if true.
+ */
+ inline bool isU10Constant(short Value) {
+return (Value == (Value 0x3ff));
+ }
+
+ inline bool isU10Constant(int Value) {
+return (Value == (Value 0x3ff));
+ }
+
+ inline bool isU10Constant(uint32_t Value) {
+return (Value == (Value 0x3ff));
+ }
+
+ inline bool isU10Constant(int64_t Value) {
+return (Value == (Value 0x3ff));
+ }
+
+ inline bool isU10Constant(uint64_t Value) {
+return (Value == (Value 0x3ff));
+ }
}
// Defines symbolic names for the SPU instructions.
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=45050r1=45049r2=45050view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Fri Dec 14 18:38:50 2007
@@ -78,6 +78,21 @@
isI16IntS10Immediate(castConstantSDNode(N)));
}
+ //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
+ bool
+ isI16IntU10Immediate(ConstantSDNode *CN)
+ {
+return isU10Constant((short) CN-getValue());
+ }
+
+ //! SDNode predicate for i16 sign-extended, 10-bit immediate values
+ bool
+ isI16IntU10Immediate(SDNode *N)
+ {
+return (N-getOpcode() == ISD::Constant
+ isI16IntU10Immediate(castConstantSDNode(N)));
+ }
+
//! ConstantSDNode predicate for signed 16-bit values
/*!
\arg CN The constant SelectionDAG node holding the value
Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td?rev=45050r1=45049r2=45050view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td Fri Dec 14 18:38:50 2007
@@ -1127,7 +1127,7 @@
def ANDHIr16:
RI10Form0b10101000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
andhi\t$rT, $rA, $val, IntegerOp,
- [(set R16C:$rT, (and R16C:$rA, i16ImmSExt10:$val))];
+ [(set R16C:$rT, (and R16C:$rA, i16ImmU10:$val))];
def ANDIv4i32:
RI10Form0b00101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
Modified: llvm/trunk/lib/Target/CellSPU/SPUOperands.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUOperands.td?rev=45050r1=45049r2=45050view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUOperands.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUOperands.td Fri Dec 14 18:38:50 2007
@@ -99,12 +99,18 @@
return isI32IntS10Immediate(N);
}];
-// i16ImmSExt10 predicate - True if the i32 immediate fits in a 10-bit sign
+// i16ImmSExt10 predicate - True if the i16 immediate fits in a 10-bit sign
// extended field. Used by RI10Form instructions like 'ldq'.
def i16ImmSExt10 : PatLeaf(imm), [{
return isI16IntS10Immediate(N);
}];
+// i16ImmU10 predicate - True if the i16 immediate fits into a 10-bit unsigned
+// value. Used by RI10Form instructions.
+def i16ImmU10 : PatLeaf(imm), [{
+ return isI16IntU10Immediate(N);
+}];
+
def immSExt16 : PatLeaf(imm), [{
// immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
// field.
@@ -206,7 +212,7 @@
}], FPimm_u18;
[llvm-commits] [llvm] r44904 - /llvm/trunk/lib/Target/X86/X86JITInfo.cpp
Author: pingbak Date: Tue Dec 11 20:38:28 2007 New Revision: 44904 URL: http://llvm.org/viewvc/llvm-project?rev=44904view=rev Log: Correct typo for Linux: s/esp/%rsp/ Modified: llvm/trunk/lib/Target/X86/X86JITInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86JITInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86JITInfo.cpp?rev=44904r1=44903r2=44904view=diff == --- llvm/trunk/lib/Target/X86/X86JITInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86JITInfo.cpp Tue Dec 11 20:38:28 2007 @@ -116,7 +116,7 @@ movaps (%rsp), %xmm0\n // Restore RSP movq%rbp, %rsp\n -CFI(.cfi_def_cfa_register esp\n) +CFI(.cfi_def_cfa_register %rsp\n) // Restore all int arg registers subq$48, %rsp\n CFI(.cfi_adjust_cfa_offset 48\n) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm-gcc-4.2] r44828 - /llvm-gcc-4.2/trunk/README.LLVM
Author: pingbak
Date: Mon Dec 10 18:35:46 2007
New Revision: 44828
URL: http://llvm.org/viewvc/llvm-project?rev=44828view=rev
Log:
Add a blurb about installing a link to libstdc++.6.dylib so that C++
executables link correctly when the compiler is installed in a nonstandard
place.
Modified:
llvm-gcc-4.2/trunk/README.LLVM
Modified: llvm-gcc-4.2/trunk/README.LLVM
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/README.LLVM?rev=44828r1=44827r2=44828view=diff
==
--- llvm-gcc-4.2/trunk/README.LLVM (original)
+++ llvm-gcc-4.2/trunk/README.LLVM Mon Dec 10 18:35:46 2007
@@ -126,6 +126,11 @@
--enable-llvm=$LLVMOBJDIR --enable-languages=c,c++$EXTRALANGS
$TARGETOPTIONS
$ make $BUILDOPTIONS
$ make install
+$ ln -sf /usr/lib/libstdc++.6.dylib `pwd`/../install/lib
+
+That last step, ln -sf ... is required so that the linker (collect2) can find
+libstdc++ ('-lstdc++') and subsequently link C++ executables link correctly.
+
Note that if you prefer to bootstrap llvm-gcc (so that the final llvm-gcc
executables have been compiled with llvm-gcc itself), replace make with
___
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[llvm-commits] [llvm-gcc-4.2] r44829 - /llvm-gcc-4.2/trunk/README.LLVM
Author: pingbak
Date: Mon Dec 10 18:43:14 2007
New Revision: 44829
URL: http://llvm.org/viewvc/llvm-project?rev=44829view=rev
Log:
Fix typo.
Modified:
llvm-gcc-4.2/trunk/README.LLVM
Modified: llvm-gcc-4.2/trunk/README.LLVM
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/README.LLVM?rev=44829r1=44828r2=44829view=diff
==
--- llvm-gcc-4.2/trunk/README.LLVM (original)
+++ llvm-gcc-4.2/trunk/README.LLVM Mon Dec 10 18:43:14 2007
@@ -129,8 +129,7 @@
$ ln -sf /usr/lib/libstdc++.6.dylib `pwd`/../install/lib
That last step, ln -sf ... is required so that the linker (collect2) can find
-libstdc++ ('-lstdc++') and subsequently link C++ executables link correctly.
-
+libstdc++ ('-lstdc++') and subsequently link C++ executables correctly.
Note that if you prefer to bootstrap llvm-gcc (so that the final llvm-gcc
executables have been compiled with llvm-gcc itself), replace make with
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[llvm-commits] [llvm] r44627 - in /llvm/trunk: CREDITS.TXT autoconf/configure.ac lib/Target/CellSPU/SPUCallingConv.td
Author: pingbak
Date: Wed Dec 5 15:23:16 2007
New Revision: 44627
URL: http://llvm.org/viewvc/llvm-project?rev=44627view=rev
Log:
Minor updates:
- Fix typo in SPUCallingConv.td
- Credit myself for CellSPU work
- Add CellSPU to 'all' host target list
Modified:
llvm/trunk/CREDITS.TXT
llvm/trunk/autoconf/configure.ac
llvm/trunk/lib/Target/CellSPU/SPUCallingConv.td
Modified: llvm/trunk/CREDITS.TXT
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/CREDITS.TXT?rev=44627r1=44626r2=44627view=diff
==
--- llvm/trunk/CREDITS.TXT (original)
+++ llvm/trunk/CREDITS.TXT Wed Dec 5 15:23:16 2007
@@ -257,3 +257,7 @@
D: Darwin exception handling
D: MMX SSSE3 instructions
D: SPEC2006 support
+
+N: Scott Michel
+E: [EMAIL PROTECTED]
+D: Added STI Cell SPU backend.
Modified: llvm/trunk/autoconf/configure.ac
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=44627r1=44626r2=44627view=diff
==
--- llvm/trunk/autoconf/configure.ac (original)
+++ llvm/trunk/autoconf/configure.ac Wed Dec 5 15:23:16 2007
@@ -363,8 +363,7 @@
[Build specific host targets: all,host-only,{target-name} (default=all)]),,
enableval=all)
case $enableval in
- # Note: Add CellSPU to all when fully functional.
- all) TARGETS_TO_BUILD=X86 Sparc PowerPC Alpha IA64 ARM Mips ;;
+ all) TARGETS_TO_BUILD=X86 Sparc PowerPC Alpha IA64 ARM Mips CellSPU ;;
host-only)
case $llvm_cv_target_arch in
x86) TARGETS_TO_BUILD=X86 ;;
Modified: llvm/trunk/lib/Target/CellSPU/SPUCallingConv.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUCallingConv.td?rev=44627r1=44626r2=44627view=diff
==
--- llvm/trunk/lib/Target/CellSPU/SPUCallingConv.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUCallingConv.td Wed Dec 5 15:23:16 2007
@@ -48,7 +48,6 @@
// The first 12 Vector arguments are passed in altivec registers.
CCIfType[v16i8, v8i16, v4i32, v4f32],
CCAssignToReg[V2, V3, V4, V5, V6, V7, V8, V9, V10,V11,V12,V13]
- */
/*
// Integer/FP values get stored in stack slots that are 8 bytes in size and
// 8-byte aligned if there are no more registers to hold them.
@@ -56,6 +55,6 @@
// Vectors get 16-byte stack slots that are 16-byte aligned.
CCIfType[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
- CCAssignToStack16, 16
+ CCAssignToStack16, 16*/
];
*/
___
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[llvm-commits] [llvm] r44596 - in /llvm/trunk/lib/Target/CellSPU: CellSDKIntrinsics.td SPURegisterNames.h
Author: pingbak Date: Tue Dec 4 19:31:18 2007 New Revision: 44596 URL: http://llvm.org/viewvc/llvm-project?rev=44596view=rev Log: Two missing files. Added: llvm/trunk/lib/Target/CellSPU/CellSDKIntrinsics.td llvm/trunk/lib/Target/CellSPU/SPURegisterNames.h Added: llvm/trunk/lib/Target/CellSPU/CellSDKIntrinsics.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/CellSDKIntrinsics.td?rev=44596view=auto == --- llvm/trunk/lib/Target/CellSPU/CellSDKIntrinsics.td (added) +++ llvm/trunk/lib/Target/CellSPU/CellSDKIntrinsics.td Tue Dec 4 19:31:18 2007 @@ -0,0 +1,449 @@ +//===-- CellSDKIntrinsics.td - Cell SDK Intrinsics -*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by a team from the Computer Systems Research +// Department at The Aerospace Corporation. +// +// See README.txt for details. +//===--===// + +///--==-- Arithmetic ops intrinsics --==-- +def CellSDKah: +RR_Int_v8i160b00010011000, ah, IntegerOp, int_spu_si_ah; +def CellSDKahi: +RI10_Int_v8i160b00010011000, ahi, IntegerOp, int_spu_si_ahi; +def CellSDKa: +RR_Int_v4i320b0011000, a, IntegerOp, int_spu_si_a; +def CellSDKai: +RI10_Int_v4i320b00111000, ai, IntegerOp, int_spu_si_ai; +def CellSDKsfh: +RR_Int_v8i160b0001001, sfh, IntegerOp, int_spu_si_sfh; +def CellSDKsfhi: +RI10_Int_v8i160b1011, sfhi, IntegerOp, int_spu_si_sfhi; +def CellSDKsf: +RR_Int_v4i320b001, sf, IntegerOp, int_spu_si_sf; +def CellSDKsfi: +RI10_Int_v4i320b0011, sfi, IntegerOp, int_spu_si_sfi; +def CellSDKaddx: +RR_Int_v4i320b0010110, addx, IntegerOp, int_spu_si_addx; +def CellSDKcg: +RR_Int_v4i320b011100, cg, IntegerOp, int_spu_si_cg; +def CellSDKcgx: +RR_Int_v4i320b0110110, cgx, IntegerOp, int_spu_si_cgx; +def CellSDKsfx: +RR_Int_v4i320b1010110, sfx, IntegerOp, int_spu_si_sfx; +def CellSDKbg: +RR_Int_v4i320b011, bg, IntegerOp, int_spu_si_bg; +def CellSDKbgx: +RR_Int_v4i320b1110110, bgx, IntegerOp, int_spu_si_bgx; + +def CellSDKmpy: +RRForm0b0010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + mpy $rT, $rA, $rB, IntegerMulDiv, + [(set (v4i32 VECREG:$rT), (int_spu_si_mpy (v8i16 VECREG:$rA), +(v8i16 VECREG:$rB)))]; + +def CellSDKmpyu: +RRForm0b0011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + mpyu $rT, $rA, $rB, IntegerMulDiv, + [(set (v4i32 VECREG:$rT), (int_spu_si_mpyu (v8i16 VECREG:$rA), + (v8i16 VECREG:$rB)))] ; + +def CellSDKmpyi: +RI10Form0b00101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), + mpyi $rT, $rA, $val, IntegerMulDiv, + [(set (v4i32 VECREG:$rT), (int_spu_si_mpyi (v8i16 VECREG:$rA), + i16ImmSExt10:$val))]; + +def CellSDKmpyui: +RI10Form0b10101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), + mpyui $rT, $rA, $val, IntegerMulDiv, + [(set (v4i32 VECREG:$rT), (int_spu_si_mpyui (v8i16 VECREG:$rA), + i16ImmSExt10:$val))]; + +def CellSDKmpya: +RRRForm0b0011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), + mpya $rT, $rA, $rB, $rC, IntegerMulDiv, + [(set (v4i32 VECREG:$rT), (int_spu_si_mpya (v8i16 VECREG:$rA), + (v8i16 VECREG:$rB), + (v8i16 VECREG:$rC)))]; + +def CellSDKmpyh: +RRForm0b1010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + mpyh $rT, $rA, $rB, IntegerMulDiv, + [(set (v4i32 VECREG:$rT), (int_spu_si_mpyh (v4i32 VECREG:$rA), + (v8i16 VECREG:$rB)))]; + +def CellSDKmpys: +RRForm0b1110000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + mpys $rT, $rA, $rB, IntegerMulDiv, + [(set (v4i32 VECREG:$rT), (int_spu_si_mpys (v8i16 VECREG:$rA), + (v8i16 VECREG:$rB)))]; + +def CellSDKmpyhh: +RRForm0b0110000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + mpyhh $rT, $rA, $rB, IntegerMulDiv, + [(set (v4i32 VECREG:$rT), (int_spu_si_mpyhh (v8i16 VECREG:$rA), + (v8i16 VECREG:$rB)))]; + +def CellSDKmpyhha: +RRForm0b01100010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + mpyhha $rT, $rA, $rB, IntegerMulDiv, + [(set (v4i32 VECREG:$rT), (int_spu_si_mpyhha (v8i16 VECREG:$rA), + (v8i16 VECREG:$rB)))]; + +// Not sure how to match a (set $rT, (add $rT (mpyhh $rA, $rB)))... so leave +// as an intrinsic for the time being +def CellSDKmpyhhu: +
[llvm-commits] [llvm] r44597 - in /llvm/trunk: ./ lib/Target/CellSPU/
Author: pingbak Date: Tue Dec 4 19:40:25 2007 New Revision: 44597 URL: http://llvm.org/viewvc/llvm-project?rev=44597view=rev Log: Updated source file headers to llvm coding standard. Modified: llvm/trunk/LICENSE.TXT llvm/trunk/lib/Target/CellSPU/CellSDKIntrinsics.td llvm/trunk/lib/Target/CellSPU/Makefile llvm/trunk/lib/Target/CellSPU/SPU.h llvm/trunk/lib/Target/CellSPU/SPU.td llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp llvm/trunk/lib/Target/CellSPU/SPUCallingConv.td llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.h llvm/trunk/lib/Target/CellSPU/SPUHazardRecognizers.cpp llvm/trunk/lib/Target/CellSPU/SPUHazardRecognizers.h llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h llvm/trunk/lib/Target/CellSPU/SPUInstrBuilder.h llvm/trunk/lib/Target/CellSPU/SPUInstrFormats.td llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td llvm/trunk/lib/Target/CellSPU/SPUMachineFunction.h llvm/trunk/lib/Target/CellSPU/SPUNodes.td llvm/trunk/lib/Target/CellSPU/SPUOperands.td llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.td llvm/trunk/lib/Target/CellSPU/SPURegisterNames.h llvm/trunk/lib/Target/CellSPU/SPUSchedule.td llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h llvm/trunk/lib/Target/CellSPU/SPUTargetAsmInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUTargetAsmInfo.h llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Modified: llvm/trunk/LICENSE.TXT URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/LICENSE.TXT?rev=44597r1=44596r2=44597view=diff == --- llvm/trunk/LICENSE.TXT (original) +++ llvm/trunk/LICENSE.TXT Tue Dec 4 19:40:25 2007 @@ -67,5 +67,6 @@ llvm/projects/ModuleMaker/autoconf llvm/projects/sample/autoconf Boost C++ Libraries llvm/include : docs/BOOST_LICENSE_1_0.txt +CellSPU backend llvm/lib/Target/CellSPU/README.txt Modified: llvm/trunk/lib/Target/CellSPU/CellSDKIntrinsics.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/CellSDKIntrinsics.td?rev=44597r1=44596r2=44597view=diff == --- llvm/trunk/lib/Target/CellSPU/CellSDKIntrinsics.td (original) +++ llvm/trunk/lib/Target/CellSPU/CellSDKIntrinsics.td Tue Dec 4 19:40:25 2007 @@ -3,9 +3,8 @@ // The LLVM Compiler Infrastructure // // This file was developed by a team from the Computer Systems Research -// Department at The Aerospace Corporation. -// -// See README.txt for details. +// Department at The Aerospace Corporation and is distributed under the +// University of Illinois Open Source License. See LICENSE.TXT for details. //===--===// ///--==-- Arithmetic ops intrinsics --==-- Modified: llvm/trunk/lib/Target/CellSPU/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/Makefile?rev=44597r1=44596r2=44597view=diff == --- llvm/trunk/lib/Target/CellSPU/Makefile (original) +++ llvm/trunk/lib/Target/CellSPU/Makefile Tue Dec 4 19:40:25 2007 @@ -3,9 +3,8 @@ # The LLVM Compiler Infrastructure # # This file was developed by a team from the Computer Systems Research -# Department at The Aerospace Corporation. -# -# See README.txt for details. +# Department at The Aerospace Corporation and is distributed under the +# University of Illinois Open Source License. See LICENSE.TXT for details. ##===--===## LEVEL = ../../.. LIBRARYNAME = LLVMCellSPU Modified: llvm/trunk/lib/Target/CellSPU/SPU.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU.h?rev=44597r1=44596r2=44597view=diff == --- llvm/trunk/lib/Target/CellSPU/SPU.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPU.h Tue Dec 4 19:40:25 2007 @@ -3,9 +3,8 @@ // The LLVM Compiler Infrastructure // // This file was developed by a team from the Computer Systems Research -// Department at The Aerospace Corporation. -// -// See README.txt for details. +// Department at The Aerospace Corporation and is distributed under the +// University of Illinois Open Source License. See LICENSE.TXT for details. //
[llvm-commits] [llvm] r44598 - in /llvm/trunk: autoconf/configure.ac include/llvm/Intrinsics.td include/llvm/IntrinsicsCellSPU.td lib/Target/CellSPU/README.txt
Author: pingbak
Date: Tue Dec 4 20:01:41 2007
New Revision: 44598
URL: http://llvm.org/viewvc/llvm-project?rev=44598view=rev
Log:
More stuff for CellSPU -- this should be enough to get an error-free
compilation (no files missing). Test cases remain to be checked in.
Added:
llvm/trunk/include/llvm/IntrinsicsCellSPU.td
Modified:
llvm/trunk/autoconf/configure.ac
llvm/trunk/include/llvm/Intrinsics.td
llvm/trunk/lib/Target/CellSPU/README.txt
Modified: llvm/trunk/autoconf/configure.ac
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=44598r1=44597r2=44598view=diff
==
--- llvm/trunk/autoconf/configure.ac (original)
+++ llvm/trunk/autoconf/configure.ac Tue Dec 4 20:01:41 2007
@@ -363,6 +363,7 @@
[Build specific host targets: all,host-only,{target-name} (default=all)]),,
enableval=all)
case $enableval in
+ # Note: Add CellSPU to all when fully functional.
all) TARGETS_TO_BUILD=X86 Sparc PowerPC Alpha IA64 ARM Mips ;;
host-only)
case $llvm_cv_target_arch in
@@ -374,6 +375,7 @@
IA64)TARGETS_TO_BUILD=IA64 ;;
ARM) TARGETS_TO_BUILD=ARM ;;
Mips)TARGETS_TO_BUILD=Mips ;;
+ CellSPU|SPU) TARGETS_TO_BUILD=CellSPU ;;
*) AC_MSG_ERROR([Can not set target to build]) ;;
esac
;;
@@ -387,6 +389,7 @@
ia64)TARGETS_TO_BUILD=IA64 $TARGETS_TO_BUILD ;;
arm) TARGETS_TO_BUILD=ARM $TARGETS_TO_BUILD ;;
mips)TARGETS_TO_BUILD=Mips $TARGETS_TO_BUILD ;;
+spu) TARGETS_TO_BUILD=CellSPU $TARGETS_TO_BUILD ;;
*) AC_MSG_ERROR([Unrecognized target $a_target]) ;;
esac
done
Modified: llvm/trunk/include/llvm/Intrinsics.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=44598r1=44597r2=44598view=diff
==
--- llvm/trunk/include/llvm/Intrinsics.td (original)
+++ llvm/trunk/include/llvm/Intrinsics.td Tue Dec 4 20:01:41 2007
@@ -274,3 +274,4 @@
include llvm/IntrinsicsPowerPC.td
include llvm/IntrinsicsX86.td
include llvm/IntrinsicsARM.td
+include llvm/IntrinsicsCellSPU.td
Added: llvm/trunk/include/llvm/IntrinsicsCellSPU.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsCellSPU.td?rev=44598view=auto
==
--- llvm/trunk/include/llvm/IntrinsicsCellSPU.td (added)
+++ llvm/trunk/include/llvm/IntrinsicsCellSPU.td Tue Dec 4 20:01:41 2007
@@ -0,0 +1,230 @@
+//==- IntrinsicsCellSPU.td - Cell SDK intrinsics -*- tablegen -*-==//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by The Aerospace Corporation.
+//
+//===--===//
+// Cell SPU Instructions:
+//===--===//
+// TODO Items (not urgent today, but would be nice, low priority)
+//
+// ANDBI, ORBI: SPU constructs a 4-byte constant for these instructions by
+// concatenating the byte argument b as . Could recognize this bit
pattern
+// in 16-bit and 32-bit constants and reduce instruction count.
+//===--===//
+
+// 7-bit integer type, used as an immediate:
+def cell_i7_ty: LLVMTypei16; // Note: This was i8
+def cell_i8_ty: LLVMTypei16; // Note: This was i8
+
+class v16i8_u7immstring builtin_suffix :
+ GCCBuiltin!strconcat(__builtin_si_, builtin_suffix),
+ Intrinsic[llvm_v16i8_ty, llvm_v16i8_ty, cell_i7_ty],
+[IntrNoMem];
+
+class v16i8_u8immstring builtin_suffix :
+ GCCBuiltin!strconcat(__builtin_si_, builtin_suffix),
+ Intrinsic[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty],
+[IntrNoMem];
+
+class v16i8_s10immstring builtin_suffix :
+ GCCBuiltin!strconcat(__builtin_si_, builtin_suffix),
+ Intrinsic[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty],
+[IntrNoMem];
+
+class v16i8_u16immstring builtin_suffix :
+ GCCBuiltin!strconcat(__builtin_si_, builtin_suffix),
+ Intrinsic[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty],
+[IntrNoMem];
+
+class v16i8_rrstring builtin_suffix :
+ GCCBuiltin!strconcat(__builtin_si_, builtin_suffix),
+ Intrinsic[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
+[IntrNoMem];
+
+class v8i16_s10immstring builtin_suffix :
+ GCCBuiltin!strconcat(__builtin_si_, builtin_suffix),
+ Intrinsic[llvm_v8i16_ty, llvm_v8i16_ty, llvm_i16_ty],
+[IntrNoMem];
+
+class v8i16_u16immstring builtin_suffix :
+ GCCBuiltin!strconcat(__builtin_si_, builtin_suffix),
+ Intrinsic[llvm_v8i16_ty, llvm_v8i16_ty, llvm_i16_ty],
+[IntrNoMem];
+
+class v8i16_rrstring builtin_suffix :
+ GCCBuiltin!strconcat(__builtin_si_, builtin_suffix),
+ Intrinsic[llvm_v8i16_ty, llvm_v8i16_ty,
[llvm-commits] [llvm] r44599 - /llvm/trunk/include/llvm/IntrinsicsCellSPU.td
Author: pingbak Date: Tue Dec 4 20:08:01 2007 New Revision: 44599 URL: http://llvm.org/viewvc/llvm-project?rev=44599view=rev Log: fixed header attribution Modified: llvm/trunk/include/llvm/IntrinsicsCellSPU.td Modified: llvm/trunk/include/llvm/IntrinsicsCellSPU.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsCellSPU.td?rev=44599r1=44598r2=44599view=diff == --- llvm/trunk/include/llvm/IntrinsicsCellSPU.td (original) +++ llvm/trunk/include/llvm/IntrinsicsCellSPU.td Tue Dec 4 20:08:01 2007 @@ -2,7 +2,9 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by The Aerospace Corporation. +// This file was developed by a team from the Computer Systems Research +// Department at The Aerospace Corporation and is distributed under the +// University of Illinois Open Source License. See LICENSE.TXT for details. // //===--===// // Cell SPU Instructions: ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r44559 - in /llvm/trunk/lib/Target/CellSPU: SPU.h SPU.td
Author: pingbak
Date: Mon Dec 3 17:14:43 2007
New Revision: 44559
URL: http://llvm.org/viewvc/llvm-project?rev=44559view=rev
Log:
More CellSPU files... more to follow.
Added:
llvm/trunk/lib/Target/CellSPU/SPU.h
llvm/trunk/lib/Target/CellSPU/SPU.td
Added: llvm/trunk/lib/Target/CellSPU/SPU.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU.h?rev=44559view=auto
==
--- llvm/trunk/lib/Target/CellSPU/SPU.h (added)
+++ llvm/trunk/lib/Target/CellSPU/SPU.h Mon Dec 3 17:14:43 2007
@@ -0,0 +1,64 @@
+//===-- SPU.h - Top-level interface for Cell SPU Target --*- C++
-*-==//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by a team from the Computer Systems Research
+// Department at The Aerospace Corporation.
+//
+// See README.txt for details.
+//
+//===--===//
+//
+// This file contains the entry points for global functions defined in the LLVM
+// Cell SPU back-end.
+//
+//===--===//
+
+#ifndef LLVM_TARGET_IBMCELLSPU_H
+#define LLVM_TARGET_IBMCELLSPU_H
+
+#include iosfwd
+
+namespace llvm {
+ class SPUTargetMachine;
+ class FunctionPass;
+
+ FunctionPass *createSPUISelDag(SPUTargetMachine TM);
+ FunctionPass *createSPUAsmPrinterPass(std::ostream o, SPUTargetMachine tm);
+
+ /* Utility functions/predicates/etc used all over the place: */
+ //! Predicate test for a signed 10-bit value
+ /*!
+\param Value The input value to be tested
+
+This predicate tests for a signed 10-bit value, returning the 10-bit value
+as a short if true.
+ */
+ inline bool isS10Constant(short Value) {
+int SExtValue = ((int) Value (32 - 10)) (32 - 10);
+return ((Value 0 Value = (1 9) - 1)
+ || (Value 0 (short) SExtValue == Value));
+ }
+
+ inline bool isS10Constant(int Value) {
+return (Value = -(1 9) Value = (1 9) - 1);
+ }
+
+ inline bool isS10Constant(uint32_t Value) {
+return (Value = ((1 9) - 1));
+ }
+
+ inline bool isS10Constant(int64_t Value) {
+return (Value = -(1 9) Value = (1 9) - 1);
+ }
+
+ inline bool isS10Constant(uint64_t Value) {
+return (Value = ((1 9) - 1));
+ }
+}
+
+// Defines symbolic names for the SPU instructions.
+//
+#include SPUGenInstrNames.inc
+
+#endif /* LLVM_TARGET_IBMCELLSPU_H */
Added: llvm/trunk/lib/Target/CellSPU/SPU.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU.td?rev=44559view=auto
==
--- llvm/trunk/lib/Target/CellSPU/SPU.td (added)
+++ llvm/trunk/lib/Target/CellSPU/SPU.td Mon Dec 3 17:14:43 2007
@@ -0,0 +1,61 @@
+//===- SPU.td - Describe the STI Cell SPU Target Machine *- tablegen
-*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+//
+// This file was developed by a team from the Computer Systems Research
+// Department at The Aerospace Corporation.
+//
+// See README.txt for details.
+//===--===//
+//
+// This is the top level entry point for the STI Cell SPU target machine.
+//
+//===--===//
+
+// Get the target-independent interfaces which we are implementing.
+//
+include ../Target.td
+
+//===--===//
+// Register File Description
+//===--===//
+
+include SPURegisterInfo.td
+
+//===--===//
+// Instruction formats, instructions
+//===--===//
+
+include SPUNodes.td
+include SPUOperands.td
+include SPUSchedule.td
+include SPUInstrFormats.td
+include SPUInstrInfo.td
+
+//===--===//
+// Subtarget features:
+//===--===//
+
+def DefaultProc: SubtargetFeature, ProcDirective, SPU::DEFAULT_PROC,
;
+def LargeMemFeature:
+ SubtargetFeaturelarge_mem,UseLargeMem, true,
+ Use large (256) LSA memory addressing [default = false];
+
+def SPURev0 : Processorv0, SPUItineraries, [DefaultProc];
+
+//===--===//
+// Calling convention:
+//===--===//
+
+include SPUCallingConv.td
+
+// Target:
+
+def SPUInstrInfo : InstrInfo {
+ let isLittleEndianEncoding = 1;
+}
+
+def SPU : Target {
+ let InstructionSet = SPUInstrInfo;
+}
___
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[llvm-commits] [llvm] r44557 - /llvm/trunk/lib/Target/CellSPU/README.txt
Author: pingbak Date: Mon Dec 3 17:09:49 2007 New Revision: 44557 URL: http://llvm.org/viewvc/llvm-project?rev=44557view=rev Log: First commit to CellSPU. More to follow Modified: llvm/trunk/lib/Target/CellSPU/README.txt Modified: llvm/trunk/lib/Target/CellSPU/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/README.txt?rev=44557r1=44556r2=44557view=diff == --- llvm/trunk/lib/Target/CellSPU/README.txt (original) +++ llvm/trunk/lib/Target/CellSPU/README.txt Mon Dec 3 17:09:49 2007 @@ -1,10 +1,41 @@ //===- README.txt - Notes for improving CellSPU-specific code gen -===// +This code was contributed by a team from the Computer Systems Research +Department in The Aerospace Corporation: + +- Scott Michel (head bottle washer and much of the non-floating point + instructions) +- Mark Thomas (floating point instructions) +- Michael AuYeung (intrinsics) +- Chandler Carruth (LLVM expertise) + +THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, OR +OTHERWISE. IN NO EVENT SHALL THE AEROSPACE CORPORATION BE LIABLE FOR DAMAGES +OF ANY KIND OR NATURE WHETHER BASED IN CONTRACT, TORT, OR OTHERWISE ARISING +OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE INCLUDING, WITHOUT +LIMITATION, DAMAGES RESULTING FROM LOST OR CONTAMINATED DATA, LOST PROFITS OR +REVENUE, COMPUTER MALFUNCTION, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL, +OR PUNITIVE DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR +SUCH DAMAGES ARE FORESEEABLE. + +--- +--WARNING--: The CellSPU work is work-in-progress and alpha quality code. +--- + TODO: -* Check in the actual code. +* Finish branch instructions, branch prediction -===-=== + These instructions were started, but only insofar as to get llvm-gcc-4.2's + crtbegin.ll working (which doesn't.) -Note: The CellSPU work is work-in-progress and alpha quality code. No code -has been officially checked into the llvm repo, but this will happen Real Soon, -Real Soon Now. +* Double floating point support + + This was started. What's missing? to be filled in. + +* Intrinsics + + Lots of progress. What's missing/incomplete? to be filled in. + +===-=== ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r44558 - /llvm/trunk/lib/Target/CellSPU/Makefile
Author: pingbak Date: Mon Dec 3 17:12:49 2007 New Revision: 44558 URL: http://llvm.org/viewvc/llvm-project?rev=44558view=rev Log: Makefile fragment for CellSPU. Added: llvm/trunk/lib/Target/CellSPU/Makefile Added: llvm/trunk/lib/Target/CellSPU/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/Makefile?rev=44558view=auto == --- llvm/trunk/lib/Target/CellSPU/Makefile (added) +++ llvm/trunk/lib/Target/CellSPU/Makefile Mon Dec 3 17:12:49 2007 @@ -0,0 +1,20 @@ +##===- lib/Target/CellSPU/Makefile -*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file was developed by a team from the Computer Systems Research +# Department at The Aerospace Corporation. +# +# See README.txt for details. +##===--===## +LEVEL = ../../.. +LIBRARYNAME = LLVMCellSPU +TARGET = SPU + +BUILT_SOURCES = SPUGenInstrNames.inc SPUGenRegisterNames.inc \ + SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \ + SPUGenRegisterInfo.h.inc SPUGenRegisterInfo.inc \ + SPUGenInstrInfo.inc SPUGenDAGISel.inc \ + SPUGenSubtarget.inc SPUGenCallingConv.inc + +include $(LEVEL)/Makefile.common ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm-gcc-4.2] r43302 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
Author: pingbak
Date: Wed Oct 24 13:15:43 2007
New Revision: 43302
URL: http://llvm.org/viewvc/llvm-project?rev=43302view=rev
Log:
::entry should be ::Entry.
Modified:
llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=43302r1=43301r2=43302view=diff
==
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Wed Oct 24 13:15:43 2007
@@ -163,7 +163,7 @@
// Create the TargetMachine we will be generating code with.
// FIXME: Figure out how to select the target and pass down subtarget info.
std::string Err;
- const TargetMachineRegistry::entry *TME =
+ const TargetMachineRegistry::Entry *TME =
TargetMachineRegistry::getClosestStaticTargetForModule(*TheModule, Err);
if (!TME) {
cerr Did not get a target machine!\n;
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[llvm-commits] [llvm-gcc-4.2] r43303 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
Author: pingbak
Date: Wed Oct 24 13:42:58 2007
New Revision: 43303
URL: http://llvm.org/viewvc/llvm-project?rev=43303view=rev
Log:
Revert the change.
Modified:
llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=43303r1=43302r2=43303view=diff
==
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Wed Oct 24 13:42:58 2007
@@ -163,7 +163,7 @@
// Create the TargetMachine we will be generating code with.
// FIXME: Figure out how to select the target and pass down subtarget info.
std::string Err;
- const TargetMachineRegistry::Entry *TME =
+ const TargetMachineRegistry::entry *TME =
TargetMachineRegistry::getClosestStaticTargetForModule(*TheModule, Err);
if (!TME) {
cerr Did not get a target machine!\n;
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[llvm-commits] [llvm] r40955 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Author: pingbak
Date: Wed Aug 8 18:23:31 2007
New Revision: 40955
URL: http://llvm.org/viewvc/llvm-project?rev=40955view=rev
Log:
If a target really needs to custom lower constants, it should be allowed
to do so.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=40955r1=40954r2=40955view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Aug 8 18:23:31 2007
@@ -965,13 +965,21 @@
}
break;
- case ISD::Constant:
+ case ISD::Constant: {
+ConstantSDNode *CN = castConstantSDNode(Node);
+unsigned opAction =
+ TLI.getOperationAction(ISD::Constant, CN-getValueType(0));
+
// We know we don't need to expand constants here, constants only have one
// value and we check that it is fine above.
-// FIXME: Maybe we should handle things like targets that don't support
full
-// 32-bit immediates?
+if (opAction == TargetLowering::Custom) {
+ Tmp1 = TLI.LowerOperation(Result, DAG);
+ if (Tmp1.Val)
+Result = Tmp1;
+}
break;
+ }
case ISD::ConstantFP: {
// Spill FP immediates to the constant pool if the target cannot directly
// codegen them. Targets often have some immediate values that can be
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[llvm-commits] [llvm] r40712 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Author: pingbak
Date: Wed Aug 1 21:22:46 2007
New Revision: 40712
URL: http://llvm.org/viewvc/llvm-project?rev=40712view=rev
Log:
Style police: Expand the tabs to spaces!
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=40712r1=40711r2=40712view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Aug 1 21:22:46 2007
@@ -2879,11 +2879,11 @@
case TargetLowering::Legal:
Result = DAG.UpdateNodeOperands(Result, Tmp1);
if (TLI.getOperationAction(Node-getOpcode(), Node-getValueType(0)) ==
- TargetLowering::Custom) {
- Tmp1 = TLI.LowerOperation(Result, DAG);
- if (Tmp1.Val) {
- Result = Tmp1;
- }
+ TargetLowering::Custom) {
+Tmp1 = TLI.LowerOperation(Result, DAG);
+if (Tmp1.Val) {
+ Result = Tmp1;
+}
}
break;
case TargetLowering::Promote: {
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[llvm-commits] [llvm] r40605 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Author: pingbak
Date: Mon Jul 30 16:00:31 2007
New Revision: 40605
URL: http://llvm.org/viewvc/llvm-project?rev=40605view=rev
Log:
- Allow custom lowering for CTPOP, CTTZ, CTLZ.
- Fixed an existing unexpanded tab.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=40605r1=40604r2=40605view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Jul 30 16:00:31 2007
@@ -2738,9 +2738,16 @@
case ISD::CTLZ:
Tmp1 = LegalizeOp(Node-getOperand(0)); // Op
switch (TLI.getOperationAction(Node-getOpcode(), Node-getValueType(0))) {
-case TargetLowering::Custom: assert(0 Cannot custom handle this yet!);
+case TargetLowering::Custom:
case TargetLowering::Legal:
Result = DAG.UpdateNodeOperands(Result, Tmp1);
+ if (TLI.getOperationAction(Node-getOpcode(), Node-getValueType(0)) ==
+ TargetLowering::Custom) {
+ Tmp1 = TLI.LowerOperation(Result, DAG);
+ if (Tmp1.Val) {
+ Result = Tmp1;
+ }
+ }
break;
case TargetLowering::Promote: {
MVT::ValueType OVT = Tmp1.getValueType();
@@ -2760,7 +2767,7 @@
DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
ISD::SETEQ);
Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
- DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
+ DAG.getConstant(MVT::getSizeInBits(OVT),NVT),
Tmp1);
break;
case ISD::CTLZ:
// Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
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[llvm-commits] [llvm-gcc-4.2] r40011 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Author: pingbak
Date: Wed Jul 18 13:27:26 2007
New Revision: 40011
URL: http://llvm.org/viewvc/llvm-project?rev=40011view=rev
Log:
Conditionalize code to fix today's daily compile problem:
- TreeToLLVM::EmitBuiltinEHReturnDataRegno() is only called if preprocessor
symbol EH_RETURN_DATA_REGNO is defined,
- TreeToLLVM::EmitBuiltinInitDwarfRegSizes() is only called if preprocessor
symbol DWARF2_UNWIND_INFO is defined
Modified:
llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=40011r1=40010r2=40011view=diff
==
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Jul 18 13:27:26 2007
@@ -4634,6 +4634,7 @@
}
bool TreeToLLVM::EmitBuiltinEHReturnDataRegno(tree exp, Value *Result) {
+#ifdef EH_RETURN_DATA_REGNO
tree arglist = TREE_OPERAND(exp, 1);
if (!validate_arglist(arglist, INTEGER_TYPE, VOID_TYPE))
@@ -4655,6 +4656,7 @@
iwhich = DWARF_FRAME_REGNUM (iwhich);
Result = ConstantInt::get(ConvertType(TREE_TYPE(exp)), iwhich);
+#endif
return true;
}
@@ -4680,6 +4682,7 @@
}
bool TreeToLLVM::EmitBuiltinInitDwarfRegSizes(tree exp, Value *Result) {
+#ifdef DWARF2_UNWIND_INFO
unsigned int i;
bool wrote_return_column = false;
static bool reg_modes_initialized = false;
@@ -4733,6 +4736,8 @@
Builder.CreateStore(Size, Builder.CreateGEP(Addr, Idx, tmp), false);
#endif
+#endif /* DWARF2_UNWIND_INFO */
+
// TODO: the RS6000 target needs extra initialization [gcc changeset 122468].
return true;
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[llvm-commits] [llvm-gcc-4.2] r40017 - /llvm-gcc-4.2/trunk/gcc/Makefile.in
Author: pingbak Date: Wed Jul 18 16:08:46 2007 New Revision: 40017 URL: http://llvm.org/viewvc/llvm-project?rev=40017view=rev Log: Use the correct name cellspu for the STI Cell SPU builds. Modified: llvm-gcc-4.2/trunk/gcc/Makefile.in Modified: llvm-gcc-4.2/trunk/gcc/Makefile.in URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/Makefile.in?rev=40017r1=40016r2=40017view=diff == --- llvm-gcc-4.2/trunk/gcc/Makefile.in (original) +++ llvm-gcc-4.2/trunk/gcc/Makefile.in Wed Jul 18 16:08:46 2007 @@ -1123,7 +1123,7 @@ powerpc*-*-*) echo powerpc;; \ sparc-*-*) echo sparc;; \ sparcv9-*-*) echo sparc;; \ -spu-*-*) echo spu;; \ +spu-*-*) echo cellspu;; \ esac LLVMTARGETOBJ := $(shell $(LLVMTARGETCOMPONENT)) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm-gcc-4.2] r39987 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Author: pingbak Date: Tue Jul 17 19:52:36 2007 New Revision: 39987 URL: http://llvm.org/viewvc/llvm-project?rev=39987view=rev Log: build - build2. (Typo) Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=39987r1=39986r2=39987view=diff == --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Jul 17 19:52:36 2007 @@ -2090,7 +2090,7 @@ // by the lang_protect_cleanup_actions langhook. // FIXME: the handler is supposed to be a nothrow region. Support for // this is blocked on support for nothrow functions. -tree filter = build (EH_FILTER_EXPR, void_type_node, NULL, NULL); +tree filter = build2 (EH_FILTER_EXPR, void_type_node, NULL, NULL); append_to_statement_list (lang_protect_cleanup_actions(), EH_FILTER_FAILURE (filter)); // CleanupFilter is the filter wrapped in a STATEMENT_LIST. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm-gcc-4.2] r39988 - /llvm-gcc-4.2/trunk/gcc/Makefile.in
Author: pingbak Date: Tue Jul 17 19:53:06 2007 New Revision: 39988 URL: http://llvm.org/viewvc/llvm-project?rev=39988view=rev Log: Make llvm recognize STI Cell SPU builds. Modified: llvm-gcc-4.2/trunk/gcc/Makefile.in Modified: llvm-gcc-4.2/trunk/gcc/Makefile.in URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/Makefile.in?rev=39988r1=39987r2=39988view=diff == --- llvm-gcc-4.2/trunk/gcc/Makefile.in (original) +++ llvm-gcc-4.2/trunk/gcc/Makefile.in Tue Jul 17 19:53:06 2007 @@ -1123,6 +1123,7 @@ powerpc*-*-*) echo powerpc;; \ sparc-*-*) echo sparc;; \ sparcv9-*-*) echo sparc;; \ +spu-*-*) echo spu;; \ esac LLVMTARGETOBJ := $(shell $(LLVMTARGETCOMPONENT)) ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm-gcc-4-2] r39948 - in /llvm-gcc-4-2/trunk/gcc: fold-const.c gimplify.c
Author: pingbak
Date: Mon Jul 16 20:01:43 2007
New Revision: 39948
URL: http://llvm.org/viewvc/llvm-project?rev=39948view=rev
Log:
Fix null dereference and an obvious syntax error when llvm is not
enabled...
Modified:
llvm-gcc-4-2/trunk/gcc/fold-const.c
llvm-gcc-4-2/trunk/gcc/gimplify.c
Modified: llvm-gcc-4-2/trunk/gcc/fold-const.c
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4-2/trunk/gcc/fold-const.c?rev=39948r1=39947r2=39948view=diff
==
--- llvm-gcc-4-2/trunk/gcc/fold-const.c (original)
+++ llvm-gcc-4-2/trunk/gcc/fold-const.c Mon Jul 16 20:01:43 2007
@@ -12942,11 +12942,11 @@
{
if ((TREE_CODE (exp) == INDIRECT_REF
|| TREE_CODE (exp) == ARRAY_REF)
- TREE_CODE (TREE_TYPE (exp)) == INTEGER_TYPE
+ TREE_CODE (TREE_TYPE (exp)) == INTEGER_TYPE
/* LLVM LOCAL begin */
#if ENABLE_LLVM
/* LLVM extends ARRAY_REF to allow pointers to be the base value. */
- (TREE_CODE (TREE_TYPE (TREE_OPERAND (exp, 0))) == ARRAY_TYPE)
+ (TREE_CODE (TREE_TYPE (TREE_OPERAND (exp, 0))) == ARRAY_TYPE)
#endif
/* LLVM LOCAL end */
)
Modified: llvm-gcc-4-2/trunk/gcc/gimplify.c
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4-2/trunk/gcc/gimplify.c?rev=39948r1=39947r2=39948view=diff
==
--- llvm-gcc-4-2/trunk/gcc/gimplify.c (original)
+++ llvm-gcc-4-2/trunk/gcc/gimplify.c Mon Jul 16 20:01:43 2007
@@ -179,8 +179,10 @@
/* LLVM LOCAL begin */
#ifndef ENABLE_LLVM
/* LLVM wants to know about gimple formal temps. */
- for (t = gimplify_ctxp-temps; t ; t = TREE_CHAIN (t))
-DECL_GIMPLE_FORMAL_TEMP_P (t) = 0;
+ if (gimplify_ctxp != 0) {
+for (t = gimplify_ctxp-temps; t ; t = TREE_CHAIN (t))
+ DECL_GIMPLE_FORMAL_TEMP_P (t) = 0;
+ }
#else
t = 0;
#endif
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Re: [llvm-commits] [llvm-gcc-4-2] r39948 - in /llvm-gcc-4-2/trunk/gcc: fold-const.c gimplify.c
Chris Lattner wrote:
Log:
Fix null dereference and an obvious syntax error when llvm is not
enabled...
--- llvm-gcc-4-2/trunk/gcc/gimplify.c (original)
+++ llvm-gcc-4-2/trunk/gcc/gimplify.c Mon Jul 16 20:01:43 2007
@@ -179,8 +179,10 @@
/* LLVM LOCAL begin */
#ifndef ENABLE_LLVM
/* LLVM wants to know about gimple formal temps. */
- for (t = gimplify_ctxp-temps; t ; t = TREE_CHAIN (t))
-DECL_GIMPLE_FORMAL_TEMP_P (t) = 0;
+ if (gimplify_ctxp != 0) {
+for (t = gimplify_ctxp-temps; t ; t = TREE_CHAIN (t))
+ DECL_GIMPLE_FORMAL_TEMP_P (t) = 0;
+ }
#else
t = 0;
#endif
Hey Scott,
Doesn't this patch change the behavior of the code when LLVM is *not*
enabled? What am I missing here? Should the #ifndef ENABLE_LLVM
really be #ifdef ENABLE_LLVM ?
Not sure what the original author intended here. I'm compiling the
spu-unknown-elf target _w/o_ llvm enabled, which is how I tripped the
null deref bug.
If this was supposed to be '#ifdef LLVM'... well, I'll check the file's
log to make sure.
-scooter
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Re: [llvm-commits] [llvm-gcc-4-2] r39948 - in /llvm-gcc-4-2/trunk/gcc: fold-const.c gimplify.c
Devang Patel wrote: On Jul 16, 2007, at 6:34 PM, Scott Michel wrote: Not sure what the original author intended here. I'm compiling the spu-unknown-elf target _w/o_ llvm enabled, which is how I tripped the null deref bug. Please test LLVM enabled build before commit, because that is the main focus of llvm-gcc development. We do not want to intentionally break llvm-gcc without LLVM builds, but that is lower priority. Hard to do with the Cell SPU... :-) But seriously, I understand. -scooter ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm-gcc-4-2] r39951 - /llvm-gcc-4-2/trunk/gcc/gimplify.c
Author: pingbak
Date: Mon Jul 16 20:56:08 2007
New Revision: 39951
URL: http://llvm.org/viewvc/llvm-project?rev=39951view=rev
Log:
The actual code is slightly different in the non-llvm case, if compared to
the 4.2 branch's current code.
Modified:
llvm-gcc-4-2/trunk/gcc/gimplify.c
Modified: llvm-gcc-4-2/trunk/gcc/gimplify.c
URL:
http://llvm.org/viewvc/llvm-project/llvm-gcc-4-2/trunk/gcc/gimplify.c?rev=39951r1=39950r2=39951view=diff
==
--- llvm-gcc-4-2/trunk/gcc/gimplify.c (original)
+++ llvm-gcc-4-2/trunk/gcc/gimplify.c Mon Jul 16 20:56:08 2007
@@ -179,10 +179,8 @@
/* LLVM LOCAL begin */
#ifndef ENABLE_LLVM
/* LLVM wants to know about gimple formal temps. */
- if (gimplify_ctxp != 0) {
-for (t = gimplify_ctxp-temps; t ; t = TREE_CHAIN (t))
- DECL_GIMPLE_FORMAL_TEMP_P (t) = 0;
- }
+ for (t = c-temps; t ; t = TREE_CHAIN (t))
+DECL_GIMPLE_FORMAL_TEMP_P (t) = 0;
#else
t = 0;
#endif
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.424 - 1.425
---
Log message:
Use '-1U' where '-1UL' is obvious overkill, eliminating gcc warnings about
tests always being true in the process.
---
Diffs of the changes: (+2 -2)
SelectionDAGISel.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.424
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.425
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.424Sun Apr 22
18:15:29 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Apr 23 20:24:20 2007
@@ -1177,7 +1177,7 @@
/// visitJumpTable - Emit JumpTable node in the current MBB
void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable JT) {
// Emit the code for the jump table
- assert(JT.Reg != -1UL Should lower JT Header first!);
+ assert(JT.Reg != -1U Should lower JT Header first!);
MVT::ValueType PTy = TLI.getPointerTy();
SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
@@ -1544,7 +1544,7 @@
// Set the jump table information so that we can codegen it as a second
// MachineBasicBlock
- SelectionDAGISel::JumpTable JT(-1UL, JTI, JumpTableBB, Default);
+ SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
(CR.CaseBB == CurMBB));
if (CR.CaseBB == CurMBB)
___
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[llvm-commits] Ignore .svn directories when installing include files
Speeds up installation a bit... s/b ignoring them anyway, just like
CVS directories.
-scooter
Index: Makefile.rules
===
--- Makefile.rules (.../trunk) (revision 2452)
+++ Makefile.rules (.../branches/llvm-spu) (revision 2452)
@@ -1691,7 +1691,7 @@
$(Verb) if test -d $(PROJ_SRC_ROOT)/include ; then \
cd $(PROJ_SRC_ROOT)/include \
for hdr in `find . -type f '!' '(' -name '*~' -o -name '.cvsignore' \
- -o -name '.#*' -o -name '*.in' ')' -print | grep -v CVS ` ; do \
+ -o -name '.#*' -o -name '*.in' ')' -print | grep -v CVS | grep -v
.svn` ; do \
instdir=`dirname $(PROJ_includedir)/$$hdr` ; \
if test \! -d $$instdir ; then \
$(EchoCmd) Making install directory $$instdir ; \
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.284 - 1.285
LegalizeDAG.cpp updated: 1.485 - 1.486
---
Log message:
1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.
---
Diffs of the changes: (+76 -25)
DAGCombiner.cpp | 81
LegalizeDAG.cpp | 20 +++--
2 files changed, 76 insertions(+), 25 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.284
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.285
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.284 Fri Mar 30 16:38:07 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Apr 2 16:36:32 2007
@@ -1488,23 +1488,24 @@
}
unsigned OpSizeInBits = MVT::getSizeInBits(VT);
+ SDOperand LHSShiftArg = LHSShift.getOperand(0);
+ SDOperand LHSShiftAmt = LHSShift.getOperand(1);
+ SDOperand RHSShiftAmt = RHSShift.getOperand(1);
// fold (or (shl x, C1), (srl x, C2)) - (rotl x, C1)
// fold (or (shl x, C1), (srl x, C2)) - (rotr x, C2)
- if (LHSShift.getOperand(1).getOpcode() == ISD::Constant
- RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
-uint64_t LShVal = castConstantSDNode(LHSShift.getOperand(1))-getValue();
-uint64_t RShVal = castConstantSDNode(RHSShift.getOperand(1))-getValue();
+ if (LHSShiftAmt.getOpcode() == ISD::Constant
+ RHSShiftAmt.getOpcode() == ISD::Constant) {
+uint64_t LShVal = castConstantSDNode(LHSShiftAmt)-getValue();
+uint64_t RShVal = castConstantSDNode(RHSShiftAmt)-getValue();
if ((LShVal + RShVal) != OpSizeInBits)
return 0;
SDOperand Rot;
if (HasROTL)
- Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
-LHSShift.getOperand(1));
+ Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
else
- Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
-RHSShift.getOperand(1));
+ Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
// If there is an AND of either shifted operand, apply it to the result.
if (LHSMask.Val || RHSMask.Val) {
@@ -1532,33 +1533,69 @@
// fold (or (shl x, y), (srl x, (sub 32, y))) - (rotl x, y)
// fold (or (shl x, y), (srl x, (sub 32, y))) - (rotr x, (sub 32, y))
- if (RHSShift.getOperand(1).getOpcode() == ISD::SUB
- LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
+ if (RHSShiftAmt.getOpcode() == ISD::SUB
+ LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
if (ConstantSDNode *SUBC =
- dyn_castConstantSDNode(RHSShift.getOperand(1).getOperand(0))) {
+ dyn_castConstantSDNode(RHSShiftAmt.getOperand(0))) {
if (SUBC-getValue() == OpSizeInBits)
if (HasROTL)
- return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
- LHSShift.getOperand(1)).Val;
+ return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
else
- return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
- LHSShift.getOperand(1)).Val;
+ return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
}
}
// fold (or (shl x, (sub 32, y)), (srl x, r)) - (rotr x, y)
// fold (or (shl x, (sub 32, y)), (srl x, r)) - (rotl x, (sub 32, y))
- if (LHSShift.getOperand(1).getOpcode() == ISD::SUB
- RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
+ if (LHSShiftAmt.getOpcode() == ISD::SUB
+ RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
if (ConstantSDNode *SUBC =
- dyn_castConstantSDNode(LHSShift.getOperand(1).getOperand(0))) {
+ dyn_castConstantSDNode(LHSShiftAmt.getOperand(0))) {
if (SUBC-getValue() == OpSizeInBits)
if (HasROTL)
- return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
- LHSShift.getOperand(1)).Val;
+ return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
else
- return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
- RHSShift.getOperand(1)).Val;
+ return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
+}
+ }
+
+ // Look for sign/zext/any-extended cases:
+ if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
+ || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
+ || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)
+ (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
+ || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
+ || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
+SDOperand LExtOp0 =
Re: [llvm-commits] Patch resubmit: ROTL/ROTR cleanups
On Apr 2, 2007, at 1:11 PM, Chris Lattner wrote:
On Mar 30, 2007, at 12:02 PM, Scott Michel wrote:
Spotted what was probably a long-standing bug, since some of my
cleanups
were simple substitutions.
Sorry for the delay. In general, if you keep the changes as simple
and disjoint as possible, I'm more likely to look at them soon :).
Here you could split up the allow custom legalize of rotates part
from the introduce some temporary vars part from match ext
rotate cases part.
I did, I did, I did! Really! They're part and parcel of the same
functionality... :-)
+
+ // Look for sign/zext/any-extended cases:
+ if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
+ || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
+ || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)
+ (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
+ || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
+ || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
+SDOperand LExtOp0 = LHSShiftAmt.getOperand(0);
+SDOperand RExtOp0 = RHSShiftAmt.getOperand(0);
+if (RExtOp0.getOpcode() == ISD::SUB
+RExtOp0.getOperand(1) == LExtOp0) {
+ // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y -
+ // (rotr x, y)
+ // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y -
+ // (rotl x, (sub 32, y))
+ if (ConstantSDNode *SUBC = castConstantSDNode
(RExtOp0.getOperand(0))) {
+if (SUBC-getValue() == OpSizeInBits) {
+ if (HasROTL)
+return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
LHSShiftAmt).Val;
+ else
+return DAG.getNode(ISD::ROTR, VT, LHSShiftArg,
RHSShiftAmt).Val;
+}
Okay, but needs an extra level of spacing for the indentation here
(2 spaces, not 1).
+ }
+} else if (LExtOp0.getOpcode() == ISD::SUB
+ RExtOp0 == LExtOp0.getOperand(1)) {
+ // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -
+ // (rotl x, y)
+ // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -
+ // (rotr x, (sub 32, y))
+ if (ConstantSDNode *SUBC = castConstantSDNode
(LExtOp0.getOperand(0))) {
+if (SUBC-getValue() == OpSizeInBits) {
+ if (HasROTL)
+return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
RHSShiftAmt).Val;
+ else
+return DAG.getNode(ISD::ROTL, VT, LHSShiftArg,
LHSShiftAmt).Val;
+}
Likewise.
Fixed tab violations, which made it look like incorrect indentation...
-scooter
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[llvm-commits] Cleanups in ROTL/ROTR DAG combiner code
The attached patch contains:
- Cleanups in the DAGCombiner.cpp ROTL/ROTR combine code, primarily
helping me to fix 80col violations (benefiting the code as a whole).
- Detect sign/zext/any-extended versions of ROTL/ROTR patterns.
- Allow custom lowering for ROTL/ROTR (needed in the CellSPU's case
for 8-bit rotates, when only 16-bit and 32-bit rotates are actually
implemented in the instruction set.)
-scooter
Index: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
===
--- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp(.../trunk) (revision 2118)
+++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp(.../branches/llvm-spu)
(revision 2118)
@@ -2683,10 +2683,24 @@
case ISD::ROTR:
Tmp1 = LegalizeOp(Node-getOperand(0)); // LHS
Tmp2 = LegalizeOp(Node-getOperand(1)); // RHS
-
-assert(TLI.isOperationLegal(Node-getOpcode(), Node-getValueType(0))
- Cannot handle this yet!);
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
+switch (TLI.getOperationAction(Node-getOpcode(), Node-getValueType(0))) {
+default:
+ assert(0 ROTL/ROTR legalize operation not supported);
+ break;
+case TargetLowering::Legal:
+ break;
+case TargetLowering::Custom:
+ Tmp1 = TLI.LowerOperation(Result, DAG);
+ if (Tmp1.Val) Result = Tmp1;
+ break;
+case TargetLowering::Promote:
+ assert(0 Do not know how to promote ROTL/ROTR);
+ break;
+case TargetLowering::Expand:
+ assert(0 Do not know how to expand ROTL/ROTR);
+ break;
+}
break;
case ISD::BSWAP:
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp(.../trunk) (revision 2118)
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp(.../branches/llvm-spu)
(revision 2118)
@@ -1488,23 +1488,24 @@
}
unsigned OpSizeInBits = MVT::getSizeInBits(VT);
+ SDOperand LHSShiftArg = LHSShift.getOperand(0);
+ SDOperand LHSShiftAmt = LHSShift.getOperand(1);
+ SDOperand RHSShiftAmt = RHSShift.getOperand(1);
// fold (or (shl x, C1), (srl x, C2)) - (rotl x, C1)
// fold (or (shl x, C1), (srl x, C2)) - (rotr x, C2)
- if (LHSShift.getOperand(1).getOpcode() == ISD::Constant
- RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
-uint64_t LShVal = castConstantSDNode(LHSShift.getOperand(1))-getValue();
-uint64_t RShVal = castConstantSDNode(RHSShift.getOperand(1))-getValue();
+ if (LHSShiftAmt.getOpcode() == ISD::Constant
+ RHSShiftAmt.getOpcode() == ISD::Constant) {
+uint64_t LShVal = castConstantSDNode(LHSShiftAmt)-getValue();
+uint64_t RShVal = castConstantSDNode(RHSShiftAmt)-getValue();
if ((LShVal + RShVal) != OpSizeInBits)
return 0;
SDOperand Rot;
if (HasROTL)
- Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
-LHSShift.getOperand(1));
+ Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
else
- Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
-RHSShift.getOperand(1));
+ Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
// If there is an AND of either shifted operand, apply it to the result.
if (LHSMask.Val || RHSMask.Val) {
@@ -1532,35 +1533,71 @@
// fold (or (shl x, y), (srl x, (sub 32, y))) - (rotl x, y)
// fold (or (shl x, y), (srl x, (sub 32, y))) - (rotr x, (sub 32, y))
- if (RHSShift.getOperand(1).getOpcode() == ISD::SUB
- LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
+ if (RHSShiftAmt.getOpcode() == ISD::SUB
+ LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
if (ConstantSDNode *SUBC =
- dyn_castConstantSDNode(RHSShift.getOperand(1).getOperand(0))) {
+ dyn_castConstantSDNode(RHSShiftAmt.getOperand(0))) {
if (SUBC-getValue() == OpSizeInBits)
if (HasROTL)
- return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
- LHSShift.getOperand(1)).Val;
+ return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
else
- return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
- LHSShift.getOperand(1)).Val;
+ return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, LHSShiftAmt).Val;
}
}
// fold (or (shl x, (sub 32, y)), (srl x, r)) - (rotr x, y)
// fold (or (shl x, (sub 32, y)), (srl x, r)) - (rotl x, (sub 32, y))
- if (LHSShift.getOperand(1).getOpcode() == ISD::SUB
- RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
+ if (LHSShiftAmt.getOpcode() == ISD::SUB
+ RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
if (ConstantSDNode *SUBC =
- dyn_castConstantSDNode(LHSShift.getOperand(1).getOperand(0))) {
+ dyn_castConstantSDNode(LHSShiftAmt.getOperand(0))) {
if (SUBC-getValue()
[llvm-commits] Patch resubmit: ROTL/ROTR cleanups
Spotted what was probably a long-standing bug, since some of my cleanups
were simple substitutions.
-scooter
Index: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
===
--- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp(.../trunk) (revision 2119)
+++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp(.../branches/llvm-spu)
(revision 2119)
@@ -2683,10 +2683,24 @@
case ISD::ROTR:
Tmp1 = LegalizeOp(Node-getOperand(0)); // LHS
Tmp2 = LegalizeOp(Node-getOperand(1)); // RHS
-
-assert(TLI.isOperationLegal(Node-getOpcode(), Node-getValueType(0))
- Cannot handle this yet!);
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
+switch (TLI.getOperationAction(Node-getOpcode(), Node-getValueType(0))) {
+default:
+ assert(0 ROTL/ROTR legalize operation not supported);
+ break;
+case TargetLowering::Legal:
+ break;
+case TargetLowering::Custom:
+ Tmp1 = TLI.LowerOperation(Result, DAG);
+ if (Tmp1.Val) Result = Tmp1;
+ break;
+case TargetLowering::Promote:
+ assert(0 Do not know how to promote ROTL/ROTR);
+ break;
+case TargetLowering::Expand:
+ assert(0 Do not know how to expand ROTL/ROTR);
+ break;
+}
break;
case ISD::BSWAP:
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp(.../trunk) (revision 2119)
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp(.../branches/llvm-spu)
(revision 2119)
@@ -1488,23 +1488,24 @@
}
unsigned OpSizeInBits = MVT::getSizeInBits(VT);
+ SDOperand LHSShiftArg = LHSShift.getOperand(0);
+ SDOperand LHSShiftAmt = LHSShift.getOperand(1);
+ SDOperand RHSShiftAmt = RHSShift.getOperand(1);
// fold (or (shl x, C1), (srl x, C2)) - (rotl x, C1)
// fold (or (shl x, C1), (srl x, C2)) - (rotr x, C2)
- if (LHSShift.getOperand(1).getOpcode() == ISD::Constant
- RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
-uint64_t LShVal = castConstantSDNode(LHSShift.getOperand(1))-getValue();
-uint64_t RShVal = castConstantSDNode(RHSShift.getOperand(1))-getValue();
+ if (LHSShiftAmt.getOpcode() == ISD::Constant
+ RHSShiftAmt.getOpcode() == ISD::Constant) {
+uint64_t LShVal = castConstantSDNode(LHSShiftAmt)-getValue();
+uint64_t RShVal = castConstantSDNode(RHSShiftAmt)-getValue();
if ((LShVal + RShVal) != OpSizeInBits)
return 0;
SDOperand Rot;
if (HasROTL)
- Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
-LHSShift.getOperand(1));
+ Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
else
- Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
-RHSShift.getOperand(1));
+ Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
// If there is an AND of either shifted operand, apply it to the result.
if (LHSMask.Val || RHSMask.Val) {
@@ -1532,35 +1533,71 @@
// fold (or (shl x, y), (srl x, (sub 32, y))) - (rotl x, y)
// fold (or (shl x, y), (srl x, (sub 32, y))) - (rotr x, (sub 32, y))
- if (RHSShift.getOperand(1).getOpcode() == ISD::SUB
- LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
+ if (RHSShiftAmt.getOpcode() == ISD::SUB
+ LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
if (ConstantSDNode *SUBC =
- dyn_castConstantSDNode(RHSShift.getOperand(1).getOperand(0))) {
+ dyn_castConstantSDNode(RHSShiftAmt.getOperand(0))) {
if (SUBC-getValue() == OpSizeInBits)
if (HasROTL)
- return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
- LHSShift.getOperand(1)).Val;
+ return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
else
- return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
- LHSShift.getOperand(1)).Val;
+ return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
}
}
// fold (or (shl x, (sub 32, y)), (srl x, r)) - (rotr x, y)
// fold (or (shl x, (sub 32, y)), (srl x, r)) - (rotl x, (sub 32, y))
- if (LHSShift.getOperand(1).getOpcode() == ISD::SUB
- RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
+ if (LHSShiftAmt.getOpcode() == ISD::SUB
+ RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
if (ConstantSDNode *SUBC =
- dyn_castConstantSDNode(LHSShift.getOperand(1).getOperand(0))) {
+ dyn_castConstantSDNode(LHSShiftAmt.getOperand(0))) {
if (SUBC-getValue() == OpSizeInBits)
if (HasROTL)
- return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
- LHSShift.getOperand(1)).Val;
+ return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
else
- return DAG.getNode(ISD::ROTR, VT,
[llvm-commits] CVS: llvm/lib/Target/CellSPU/README.txt
Changes in directory llvm/lib/Target/CellSPU: README.txt added (r1.1) --- Log message: First test check-in. --- Diffs of the changes: (+10 -0) README.txt | 10 ++ 1 files changed, 10 insertions(+) Index: llvm/lib/Target/CellSPU/README.txt diff -c /dev/null llvm/lib/Target/CellSPU/README.txt:1.1 *** /dev/null Wed Mar 28 12:04:53 2007 --- llvm/lib/Target/CellSPU/README.txt Wed Mar 28 12:04:43 2007 *** *** 0 --- 1,10 + //===- README.txt - Notes for improving CellSPU-specific code gen -===// + + TODO: + * Check in the actual code. + + ===-=== + + Note: The CellSPU work is work-in-progress and alpha quality code. No code + has been officially checked into the llvm repo, but this will happen Real Soon, + Real Soon Now. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] Minor TD nick
Packed structures are always packed for ABI and preferred alignment.
Index: lib/Target/TargetData.cpp
===
--- lib/Target/TargetData.cpp (.../trunk) (revision 924)
+++ lib/Target/TargetData.cpp (.../branches/llvm-spu) (revision 924)
@@ -458,7 +458,7 @@
case Type::StructTyID: {
// Packed structure types always have an ABI alignment of one.
-if (castStructType(Ty)-isPacked() abi_or_pref)
+if (castStructType(Ty)-isPacked())
return 1;
// Get the layout annotation... which is lazily created on demand.
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[llvm-commits] Bug 1202 fix
Attached patch fixes bug 1202.
Index: lib/Target/TargetData.cpp
===
--- lib/Target/TargetData.cpp (.../trunk) (revision 877)
+++ lib/Target/TargetData.cpp (.../branches/llvm-spu) (revision 877)
@@ -245,7 +245,8 @@
std::pairalign_iterator, align_iterator ins_result =
std::equal_range(Alignments.begin(), Alignments.end(), elt);
align_iterator I = ins_result.first;
- if (I-AlignType == align_type I-TypeBitWidth == bit_width) {
+ align_iterator E = ins_result.second;
+ if (I != E I-AlignType == align_type I-TypeBitWidth == bit_width) {
// Update the abi, preferred alignments.
I-ABIAlign = abi_align;
I-PrefAlign = pref_align;
@@ -254,7 +255,6 @@
#if 0
// Keep around for debugging and testing...
- align_iterator E = ins_result.second;
cerr setAlignment( elt )\n;
cerr I = (I - Alignments.begin())
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] TargetData update
Included most of Chris' comments, fixed packed structure
bug...
-scooter
--
Scott Michel [EMAIL PROTECTED]
High Performance Hardware Section Manager 310/336-5034
Computer Systems Research Department
The Aerospace Corporation
Index: include/llvm/Target/TargetData.h
===
--- include/llvm/Target/TargetData.h (.../trunk) (revision 853)
+++ include/llvm/Target/TargetData.h (.../branches/llvm-spu) (revision 853)
@@ -48,7 +48,7 @@
/// @note The unusual order of elements in the structure attempts to reduce
/// padding and make the structure slightly more cache friendly.
struct TargetAlignElem {
- unsigned char AlignType; // Alignment type (AlignTypeEnum)
+ AlignTypeEnum AlignType : 8; // Alignment type (AlignTypeEnum)
unsigned char ABIAlign; // ABI alignment for this type/bitw
unsigned char PrefAlign; // Pref. alignment for this type/bitw
short TypeBitWidth; // Type bit width
@@ -64,18 +64,12 @@
std::ostream dump(std::ostream os) const;
};
-//! TargetAlignElem output stream inserter
-/*!
- @sa TargetAlignElem::dump()
- */
-std::ostream operator(std::ostream os, const TargetAlignElem elem);
-
class TargetData : public ImmutablePass {
private:
bool LittleEndian; /// Defaults to false
unsigned char PointerMemSize;/// Pointer size in bytes
unsigned char PointerABIAlign; /// Pointer ABI alignment
- unsigned char PointerPrefAlign; /// Pointer preferred global alignment
+ unsigned char PointerPrefAlign; /// Pointer preferred alignment
//! Where the primitive type alignment data is stored.
/*!
@@ -99,7 +93,8 @@
void setAlignment(AlignTypeEnum align_type, unsigned char abi_align,
unsigned char pref_align, short bit_width);
//! Get TargetAlignElem from alignment type and bit width
- const TargetAlignElem getAlignment(AlignTypeEnum, short) const;
+ const TargetAlignElem getAlignment(AlignTypeEnum align_type,
+ short bit_width) const;
//! Internal helper method that returns requested alignment for type.
unsigned char getAlignment(const Type *Ty, bool abi_or_pref) const;
Index: lib/Target/TargetData.cpp
===
--- lib/Target/TargetData.cpp (.../trunk) (revision 853)
+++ lib/Target/TargetData.cpp (.../branches/llvm-spu) (revision 853)
@@ -50,8 +50,8 @@
const Type *Ty = ST-getElementType(i);
unsigned TyAlign;
uint64_t TySize;
-TyAlign = (unsigned) TD.getABITypeAlignment(Ty);
-TySize = (unsigned) TD.getTypeSize(Ty);
+TyAlign = (ST-isPacked() ? 1 : TD.getABITypeAlignment(Ty));
+TySize = TD.getTypeSize(Ty);
// Add padding if necessary to make the data element aligned properly...
if (StructSize % TyAlign != 0)
@@ -94,8 +94,7 @@
TargetAlignElem
TargetAlignElem::get(AlignTypeEnum align_type, unsigned char abi_align,
- unsigned char pref_align, short bit_width)
-{
+ unsigned char pref_align, short bit_width) {
TargetAlignElem retval;
retval.AlignType = align_type;
retval.ABIAlign = abi_align;
@@ -105,15 +104,13 @@
}
bool
-TargetAlignElem::operator(const TargetAlignElem rhs) const
-{
+TargetAlignElem::operator(const TargetAlignElem rhs) const {
return ((AlignType rhs.AlignType)
|| (AlignType == rhs.AlignType TypeBitWidth rhs.TypeBitWidth));
}
bool
-TargetAlignElem::operator==(const TargetAlignElem rhs) const
-{
+TargetAlignElem::operator==(const TargetAlignElem rhs) const {
return (AlignType == rhs.AlignType
ABIAlign == rhs.ABIAlign
PrefAlign == rhs.PrefAlign
@@ -121,20 +118,13 @@
}
std::ostream
-TargetAlignElem::dump(std::ostream os) const
-{
+TargetAlignElem::dump(std::ostream os) const {
return os AlignType
TypeBitWidth
: (int) (ABIAlign * 8)
: (int) (PrefAlign * 8);
}
-std::ostream
-llvm::operator(std::ostream os, const TargetAlignElem elem)
-{
- return elem.dump(os);
-}
-
const TargetAlignElem TargetData::InvalidAlignmentElem =
TargetAlignElem::get((AlignTypeEnum) -1, 0, 0, 0);
@@ -146,9 +136,9 @@
A TargetDescription string consists of a sequence of hyphen-delimited
specifiers for target endianness, pointer size and alignments, and various
primitive type sizes and alignments. A typical string looks something like:
- br
+ brbr
E-p:32:32:32-i1:8:8-i8:8:8-i32:32:32-i64:32:64-f32:32:32-f64:32:64
- br
+ brbr
(note: this string is not fully specified and is only an example.)
\p
Alignments come in two flavors: ABI and preferred. ABI alignment (abi_align,
@@ -187,16 +177,16 @@
PointerPrefAlign = PointerABIAlign;
// Default alignments
- setAlignment(INTEGER_ALIGN, 1, 1, 1); // Bool
- setAlignment(INTEGER_ALIGN
[llvm-commits] (yet another) updated TargetData patch
- Merged llvm HEAD changes.
- Found/fixed structure size calculation bug.
Index: include/llvm/Target/TargetData.h
===
--- include/llvm/Target/TargetData.h (.../trunk) (revision 818)
+++ include/llvm/Target/TargetData.h (.../branches/llvm-spu) (revision 818)
@@ -22,6 +22,8 @@
#include llvm/Pass.h
#include llvm/Support/DataTypes.h
+#include llvm/ADT/SmallVector.h
+#include string
namespace llvm {
@@ -31,45 +33,96 @@
class StructLayout;
class GlobalVariable;
+/// Enum used to categorize the alignment types stored by TargetAlignElem
+enum AlignTypeEnum {
+ INTEGER_ALIGN = 'i', /// Integer type alignment
+ PACKED_ALIGN = 'v',/// Vector type alignment
+ FLOAT_ALIGN = 'f', /// Floating point type alignment
+ AGGREGATE_ALIGN = 'a' /// Aggregate alignment
+};
+/// Target alignment element.
+///
+/// Stores the alignment data associated with a given alignment type (pointer,
+/// integer, packed/vector, float) and type bit width.
+///
+/// @note The unusual order of elements in the structure attempts to reduce
+/// padding and make the structure slightly more cache friendly.
+struct TargetAlignElem {
+ unsigned char AlignType; // Alignment type (AlignTypeEnum)
+ unsigned char ABIAlign; // ABI alignment for this type/bitw
+ unsigned char PrefAlign; // Pref. alignment for this type/bitw
+ short TypeBitWidth; // Type bit width
+
+ /// Initializer
+ static TargetAlignElem get(AlignTypeEnum align_type, unsigned char abi_align,
+ unsigned char pref_align, short bit_width);
+ /// Less-than predicate
+ bool operator(const TargetAlignElem rhs) const;
+ /// Equality predicate
+ bool operator==(const TargetAlignElem rhs) const;
+ /// output stream operator
+ std::ostream dump(std::ostream os) const;
+};
+
+//! TargetAlignElem output stream inserter
+/*!
+ @sa TargetAlignElem::dump()
+ */
+std::ostream operator(std::ostream os, const TargetAlignElem elem);
+
class TargetData : public ImmutablePass {
- bool LittleEndian; // Defaults to false
+private:
+ bool LittleEndian; /// Defaults to false
+ unsigned char PointerMemSize;/// Pointer size in bytes
+ unsigned char PointerABIAlign; /// Pointer ABI alignment
+ unsigned char PointerPrefAlign; /// Pointer preferred global alignment
- // ABI alignments
- unsigned char BoolABIAlignment; // Defaults to 1 byte
- unsigned char ByteABIAlignment; // Defaults to 1 byte
- unsigned char ShortABIAlignment; // Defaults to 2 bytes
- unsigned char IntABIAlignment;// Defaults to 4 bytes
- unsigned char LongABIAlignment; // Defaults to 8 bytes
- unsigned char FloatABIAlignment; // Defaults to 4 bytes
- unsigned char DoubleABIAlignment; // Defaults to 8 bytes
- unsigned char PointerMemSize;// Defaults to 8 bytes
- unsigned char PointerABIAlignment;// Defaults to 8 bytes
+ //! Where the primitive type alignment data is stored.
+ /*!
+ @sa init().
+ @note Could support multiple size pointer alignments, e.g., 32-bit pointers
+ vs. 64-bit pointers by extending TargetAlignment, but for now, we don't.
+ */
+ SmallVectorTargetAlignElem, 16 Alignments;
+ //! Alignment iterator shorthand
+ typedef SmallVectorTargetAlignElem, 16::iterator align_iterator;
+ //! Constant alignment iterator shorthand
+ typedef SmallVectorTargetAlignElem, 16::const_iterator align_const_iterator;
+ //! Invalid alignment.
+ /*!
+This member is a signal that a requested alignment type and bit width were
+not found in the SmallVector.
+ */
+ static const TargetAlignElem InvalidAlignmentElem;
- // Preferred stack/global type alignments
- unsigned char BoolPrefAlignment;// Defaults to BoolABIAlignment
- unsigned char BytePrefAlignment;// Defaults to ByteABIAlignment
- unsigned char ShortPrefAlignment; // Defaults to ShortABIAlignment
- unsigned char IntPrefAlignment; // Defaults to IntABIAlignment
- unsigned char LongPrefAlignment;// Defaults to LongABIAlignment
- unsigned char FloatPrefAlignment; // Defaults to FloatABIAlignment
- unsigned char DoublePrefAlignment; // Defaults to DoubleABIAlignment
- unsigned char PointerPrefAlignment; // Defaults to PointerABIAlignment
- unsigned char AggMinPrefAlignment; // Defaults to 0 bytes
+ //! Set/initialize target alignments
+ void setAlignment(AlignTypeEnum align_type, unsigned char abi_align,
+unsigned char pref_align, short bit_width);
+ //! Get TargetAlignElem from alignment type and bit width
+ const TargetAlignElem getAlignment(AlignTypeEnum, short) const;
+ //! Internal helper method that returns requested alignment for type.
+ unsigned char getAlignment(const Type *Ty, bool abi_or_pref) const;
+ /// Valid alignment predicate.
+ ///
+ ///
[llvm-commits] updated TargetData mods...
Resolved recent commit conflicts.
-scooter
Index: include/llvm/Target/TargetData.h
===
--- include/llvm/Target/TargetData.h (.../trunk) (revision 773)
+++ include/llvm/Target/TargetData.h (.../branches/llvm-spu) (revision 773)
@@ -22,6 +22,8 @@
#include llvm/Pass.h
#include llvm/Support/DataTypes.h
+#include llvm/ADT/SmallVector.h
+#include string
namespace llvm {
@@ -31,45 +33,96 @@
class StructLayout;
class GlobalVariable;
+/// Enum used to categorize the alignment types stored by TargetAlignElem
+enum AlignTypeEnum {
+ INTEGER_ALIGN = 'i', /// Integer type alignment
+ PACKED_ALIGN = 'v',/// Vector type alignment
+ FLOAT_ALIGN = 'f', /// Floating point type alignment
+ AGGREGATE_ALIGN = 'a' /// Aggregate alignment
+};
+/// Target alignment element.
+///
+/// Stores the alignment data associated with a given alignment type (pointer,
+/// integer, packed/vector, float) and type bit width.
+///
+/// @note The unusual order of elements in the structure attempts to reduce
+/// padding and make the structure slightly more cache friendly.
+struct TargetAlignElem {
+ unsigned char AlignType; // Alignment type (AlignTypeEnum)
+ unsigned char ABIAlign; // ABI alignment for this type/bitw
+ unsigned char PrefAlign; // Pref. alignment for this type/bitw
+ short TypeBitWidth; // Type bit width
+
+ /// Initializer
+ static TargetAlignElem get(AlignTypeEnum align_type, unsigned char abi_align,
+ unsigned char pref_align, short bit_width);
+ /// Less-than predicate
+ bool operator(const TargetAlignElem rhs) const;
+ /// Equality predicate
+ bool operator==(const TargetAlignElem rhs) const;
+ /// output stream operator
+ std::ostream dump(std::ostream os) const;
+};
+
+//! TargetAlignElem output stream inserter
+/*!
+ @sa TargetAlignElem::dump()
+ */
+std::ostream operator(std::ostream os, const TargetAlignElem elem);
+
class TargetData : public ImmutablePass {
- bool LittleEndian; // Defaults to false
+private:
+ bool LittleEndian; /// Defaults to false
+ unsigned char PointerMemSize;/// Pointer size in bytes
+ unsigned char PointerABIAlign; /// Pointer ABI alignment
+ unsigned char PointerPrefAlign; /// Pointer preferred global alignment
- // ABI alignments
- unsigned char BoolABIAlignment; // Defaults to 1 byte
- unsigned char ByteABIAlignment; // Defaults to 1 byte
- unsigned char ShortABIAlignment; // Defaults to 2 bytes
- unsigned char IntABIAlignment;// Defaults to 4 bytes
- unsigned char LongABIAlignment; // Defaults to 8 bytes
- unsigned char FloatABIAlignment; // Defaults to 4 bytes
- unsigned char DoubleABIAlignment; // Defaults to 8 bytes
- unsigned char PointerMemSize;// Defaults to 8 bytes
- unsigned char PointerABIAlignment;// Defaults to 8 bytes
+ //! Where the primitive type alignment data is stored.
+ /*!
+ @sa init().
+ @note Could support multiple size pointer alignments, e.g., 32-bit pointers
+ vs. 64-bit pointers by extending TargetAlignment, but for now, we don't.
+ */
+ SmallVectorTargetAlignElem, 16 Alignments;
+ //! Alignment iterator shorthand
+ typedef SmallVectorTargetAlignElem, 16::iterator align_iterator;
+ //! Constant alignment iterator shorthand
+ typedef SmallVectorTargetAlignElem, 16::const_iterator align_const_iterator;
+ //! Invalid alignment.
+ /*!
+This member is a signal that a requested alignment type and bit width were
+not found in the SmallVector.
+ */
+ static const TargetAlignElem InvalidAlignmentElem;
- // Preferred stack/global type alignments
- unsigned char BoolPrefAlignment;// Defaults to BoolABIAlignment
- unsigned char BytePrefAlignment;// Defaults to ByteABIAlignment
- unsigned char ShortPrefAlignment; // Defaults to ShortABIAlignment
- unsigned char IntPrefAlignment; // Defaults to IntABIAlignment
- unsigned char LongPrefAlignment;// Defaults to LongABIAlignment
- unsigned char FloatPrefAlignment; // Defaults to FloatABIAlignment
- unsigned char DoublePrefAlignment; // Defaults to DoubleABIAlignment
- unsigned char PointerPrefAlignment; // Defaults to PointerABIAlignment
- unsigned char AggMinPrefAlignment; // Defaults to 0 bytes
+ //! Set/initialize target alignments
+ void setAlignment(AlignTypeEnum align_type, unsigned char abi_align,
+unsigned char pref_align, short bit_width);
+ //! Get TargetAlignElem from alignment type and bit width
+ const TargetAlignElem getAlignment(AlignTypeEnum, short) const;
+ //! Internal helper method that returns requested alignment for type.
+ unsigned char getAlignment(const Type *Ty, bool abi_or_pref) const;
+ /// Valid alignment predicate.
+ ///
+ /// Predicate that tests a
[llvm-commits] TargetData patch
Incorporated suggestions from Chris. Rebsubmitted patch.
--
Scott Michel [EMAIL PROTECTED]
High Performance Hardware Section Manager 310/336-5034
Computer Systems Research Department
The Aerospace Corporation
Index: include/llvm/Target/TargetData.h
===
--- include/llvm/Target/TargetData.h (.../trunk) (revision 570)
+++ include/llvm/Target/TargetData.h (.../branches/llvm-spu) (revision 570)
@@ -22,7 +22,7 @@
#include llvm/Pass.h
#include llvm/Support/DataTypes.h
-#include vector
+#include llvm/ADT/SmallVector.h
#include string
namespace llvm {
@@ -33,45 +33,96 @@
class StructLayout;
class GlobalVariable;
+/// Enum used to categorize the alignment types stored by TargetAlignElem
+enum AlignTypeEnum {
+ INTEGER_ALIGN = 'i', /// Integer type alignment
+ PACKED_ALIGN = 'v',/// Vector type alignment
+ FLOAT_ALIGN = 'f', /// Floating point type alignment
+ AGGREGATE_ALIGN = 'a' /// Aggregate alignment
+};
+/// Target alignment element.
+///
+/// Stores the alignment data associated with a given alignment type (pointer,
+/// integer, packed/vector, float) and type bit width.
+///
+/// @note The unusual order of elements in the structure attempts to reduce
+/// padding and make the structure slightly more cache friendly.
+struct TargetAlignElem {
+ unsigned char AlignType; // Alignment type (AlignTypeEnum)
+ unsigned char ABIAlign; // ABI alignment for this type/bitw
+ unsigned char PrefAlign; // Pref. alignment for this type/bitw
+ short TypeBitWidth; // Type bit width
+
+ /// Initializer
+ static TargetAlignElem get(AlignTypeEnum align_type, unsigned char abi_align,
+ unsigned char pref_align, short bit_width);
+ /// Less-than predicate
+ bool operator(const TargetAlignElem rhs) const;
+ /// Equality predicate
+ bool operator==(const TargetAlignElem rhs) const;
+ /// output stream operator
+ std::ostream dump(std::ostream os) const;
+};
+
+//! TargetAlignElem output stream inserter
+/*!
+ @sa TargetAlignElem::dump()
+ */
+std::ostream operator(std::ostream os, const TargetAlignElem elem);
+
class TargetData : public ImmutablePass {
- bool LittleEndian; // Defaults to false
+private:
+ bool LittleEndian; /// Defaults to false
+ unsigned char PointerMemSize;/// Pointer size in bytes
+ unsigned char PointerABIAlign; /// Pointer ABI alignment
+ unsigned char PointerPrefAlign; /// Pointer preferred global alignment
- // ABI alignments
- unsigned char BoolABIAlignment; // Defaults to 1 byte
- unsigned char ByteABIAlignment; // Defaults to 1 byte
- unsigned char ShortABIAlignment; // Defaults to 2 bytes
- unsigned char IntABIAlignment;// Defaults to 4 bytes
- unsigned char LongABIAlignment; // Defaults to 8 bytes
- unsigned char FloatABIAlignment; // Defaults to 4 bytes
- unsigned char DoubleABIAlignment; // Defaults to 8 bytes
- unsigned char PointerMemSize;// Defaults to 8 bytes
- unsigned char PointerABIAlignment;// Defaults to 8 bytes
+ //! Where the primitive type alignment data is stored.
+ /*!
+ @sa init().
+ @note Could support multiple size pointer alignments, e.g., 32-bit pointers
+ vs. 64-bit pointers by extending TargetAlignment, but for now, we don't.
+ */
+ SmallVectorTargetAlignElem, 16 Alignments;
+ //! Alignment iterator shorthand
+ typedef SmallVectorTargetAlignElem, 16::iterator align_iterator;
+ //! Constant alignment iterator shorthand
+ typedef SmallVectorTargetAlignElem, 16::const_iterator align_const_iterator;
+ //! Invalid alignment.
+ /*!
+This member is a signal that a requested alignment type and bit width were
+not found in the SmallVector.
+ */
+ static const TargetAlignElem InvalidAlignmentElem;
- // Preferred stack/global type alignments
- unsigned char BoolPrefAlignment;// Defaults to BoolABIAlignment
- unsigned char BytePrefAlignment;// Defaults to ByteABIAlignment
- unsigned char ShortPrefAlignment; // Defaults to ShortABIAlignment
- unsigned char IntPrefAlignment; // Defaults to IntABIAlignment
- unsigned char LongPrefAlignment;// Defaults to LongABIAlignment
- unsigned char FloatPrefAlignment; // Defaults to FloatABIAlignment
- unsigned char DoublePrefAlignment; // Defaults to DoubleABIAlignment
- unsigned char PointerPrefAlignment; // Defaults to PointerABIAlignment
- unsigned char AggMinPrefAlignment; // Defaults to 0 bytes
+ //! Set/initialize target alignments
+ void setAlignment(AlignTypeEnum align_type, unsigned char abi_align,
+unsigned char pref_align, short bit_width);
+ //! Get TargetAlignElem from alignment type and bit width
+ const TargetAlignElem getAlignment(AlignTypeEnum, short) const
[llvm-commits] Updated TargetData patch.
Found a minor bug in the previous patch (bit-byte conversion),
fixed 80col violations (hopefully), got rid of tabs.
-scooter
Index: include/llvm/Target/TargetData.h
===
--- include/llvm/Target/TargetData.h (.../trunk) (revision 522)
+++ include/llvm/Target/TargetData.h (.../branches/llvm-spu) (revision 522)
@@ -23,6 +23,7 @@
#include llvm/Pass.h
#include llvm/Support/DataTypes.h
#include vector
+#include llvm/ADT/SmallVector.h
#include string
namespace llvm {
@@ -33,45 +34,120 @@
class StructLayout;
class GlobalVariable;
+/// Enum used to categorize the alignment types stored by TargetAlignElem
+enum AlignTypeEnum {
+ INTEGER_ALIGN = 'i', /// Integer type alignment
+ PACKED_ALIGN = 'v',/// Vector type alignment
+ FLOAT_ALIGN = 'f', /// Floating point type alignment
+ AGGREGATE_ALIGN = 'a' /// Aggregate alignment
+};
+/// Target alignment element.
+///
+/// Stores the alignment data associated with a given alignment type (pointer,
+/// integer, packed/vector, float) and type bit width.
+///
+/// @note The unusual order of elements in the structure attempts to reduce
+/// padding and make the structure slightly more cache friendly.
+struct TargetAlignElem {
+ unsigned char AlignType; // Alignment type (AlignTypeEnum)
+ unsigned char ABIAlign; // ABI alignment for this type/bitw
+ unsigned char PrefAlign; // Preferred alignment for this type/bitw
+ short TypeBitWidth; // Type bit width
+
+ /// Default constructor
+ TargetAlignElem();
+ /// Full constructor
+ TargetAlignElem(AlignTypeEnum align_type, unsigned char abi_align,
+ unsigned char pref_align, short bit_width);
+ /// Copy constructor
+ TargetAlignElem(const TargetAlignElem src);
+ /// Destructor
+ ~TargetAlignElem() { }
+ /// Assignment operator
+ TargetAlignElem operator=(const TargetAlignElem rhs);
+ /// Less-than predicate
+ bool operator(const TargetAlignElem rhs) const;
+ /// Equality predicate
+ bool operator==(const TargetAlignElem rhs) const;
+ /// output stream operator
+ std::ostream dump(std::ostream os) const;
+};
+
+/// Output stream inserter
+/// @sa TargetAlignElem::dump()
+std::ostream operator(std::ostream os, const TargetAlignElem elem);
+
+/// Target alignment container
+///
+/// This is the container for most primitive types' alignment, i.e., integer,
+/// floating point, vectors and aggregates.
+class TargetAlign : public SmallVectorTargetAlignElem, 16 {
+private:
+ /// Invalid alignment
+ /// This member is a signal that a requested alignment type and
+ /// bit width were not found in the SmallVector.
+ static const TargetAlignElem InvalidAlignmentElem;
+public:
+ /// Default constructor
+ TargetAlign();
+ /// Destructor
+ ~TargetAlign() { }
+ /// Copy constructor
+ TargetAlign(const TargetAlign src);
+ /// Assignment operator
+ TargetAlign operator=(const TargetAlign rhs);
+ /// Add elements to the container.
+ ///
+ /// Adds elements to the container, keeping the container sorted. If the
+ /// requested alignment type (@a align_type) and bit width (@a bit_width)
+ /// exist in the container, then the matching element's ABI and preferred
+ /// alignments are overwritten with @a abi_align and @a pref_align.
+ void set(AlignTypeEnum align_type, short bit_width, unsigned char abi_align,
+ unsigned char pref_align);
+ /// Get the data associated with a given alignment type and bit width.
+ ///
+ /// @return InvalidAlignmentElem if not found, otherwise, the matching
+ /// TargetAlignElem.
+ const TargetAlignElem get(AlignTypeEnum align_type, short bit_width) const;
+ /// Valid alignment predicate.
+ ///
+ /// Predicate that tests a TargetAlignElem reference returned by get() against
+ /// InvalidAlignmentElem.
+ inline bool valid(const TargetAlignElem align) const {
+return (align != InvalidAlignmentElem);
+ }
+};
+
class TargetData : public ImmutablePass {
- bool LittleEndian; // Defaults to false
+private:
+ bool LittleEndian; /// Defaults to false
+ unsigned char PointerMemSize;/// Pointer size in bytes
+ unsigned char PointerABIAlign; /// Pointer ABI alignment
+ unsigned char PointerPrefAlign; /// Pointer preferred global alignment
- // ABI alignments
- unsigned char BoolABIAlignment; // Defaults to 1 byte
- unsigned char ByteABIAlignment; // Defaults to 1 byte
- unsigned char ShortABIAlignment; // Defaults to 2 bytes
- unsigned char IntABIAlignment;// Defaults to 4 bytes
- unsigned char LongABIAlignment; // Defaults to 8 bytes
- unsigned char FloatABIAlignment; // Defaults to 4 bytes
- unsigned char DoubleABIAlignment; // Defaults to 8 bytes
- unsigned char PointerMemSize;// Defaults to 8 bytes
- unsigned char PointerABIAlignment;//
[llvm-commits] More TargetData mods...
Revamped the TargetData spec string so that alignments for differently
sized types can be more flexibly specified. Also added support for
vector alignments (32 and 64 bits). The default spec string now looks
like:
E-p:64:64:64-a0:0:0-f32:32:32-f64:0:64
-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:0:64
-v64:64:64-v128:128:128
Although, it should be noted, that this isn't actually parsed (it's the
result of calling TargetData::getRepresentation()). Internally, a
SmallVector is created with these various and sundry types, sizes and
alignments.
Gratuitously changed getTypeAlignmentABI to getABITypeAlignment
and getTypeAlignmentPref to getPrefTypeAlignment.
Slimmed down the TargetData code so that there are fewer moving
parts -- if changes have to be made, it's should be more maintainable.
-scooter
--
Scott Michel [EMAIL PROTECTED]
High Performance Hardware Section Manager 310/336-5034
Computer Systems Research Department
The Aerospace Corporation
Index: include/llvm/Target/TargetData.h
===
--- include/llvm/Target/TargetData.h (.../trunk) (revision 423)
+++ include/llvm/Target/TargetData.h (.../branches/llvm-spu) (revision 423)
@@ -23,6 +23,7 @@
#include llvm/Pass.h
#include llvm/Support/DataTypes.h
#include vector
+#include llvm/ADT/SmallVector.h
#include string
namespace llvm {
@@ -33,45 +34,120 @@
class StructLayout;
class GlobalVariable;
+/// Enum used to categorize the alignment types stored by TargetAlignElem
+enum AlignTypeEnum {
+ INTEGER_ALIGN = 'i', /// Integer type alignment
+ PACKED_ALIGN = 'v',/// Vector type alignment
+ FLOAT_ALIGN = 'f', /// Floating point type alignment
+ AGGREGATE_ALIGN = 'a' /// Aggregate alignment
+};
+/// Target alignment element.
+///
+/// Stores the alignment data associated with a given alignment type (pointer,
+/// integer, packed/vector, float) and type bit width.
+///
+/// @note The unusual order of elements in the structure attempts to reduce
+/// padding and make the structure slightly more cache friendly.
+struct TargetAlignElem {
+ unsigned char AlignType; // Alignment type (AlignTypeEnum)
+ unsigned char ABIAlign; // ABI alignment for this type/bitw
+ unsigned char PrefAlign; // Preferred alignment for this type/bitw
+ short TypeBitWidth; // Type bit width
+
+ /// Default constructor
+ TargetAlignElem();
+ /// Full constructor
+ TargetAlignElem(AlignTypeEnum align_type, unsigned char abi_align,
+ unsigned char pref_align, short bit_width);
+ /// Copy constructor
+ TargetAlignElem(const TargetAlignElem src);
+ /// Destructor
+ ~TargetAlignElem() { }
+ /// Assignment operator
+ TargetAlignElem operator=(const TargetAlignElem rhs);
+ /// Less-than predicate
+ bool operator(const TargetAlignElem rhs) const;
+ /// Equality predicate
+ bool operator==(const TargetAlignElem rhs) const;
+ /// output stream operator
+ std::ostream dump(std::ostream os) const;
+};
+
+/// Output stream inserter
+/// @sa TargetAlignElem::dump()
+std::ostream operator(std::ostream os, const TargetAlignElem elem);
+
+/// Target alignment container
+///
+/// This is the container for most primitive types' alignment, i.e., integer,
+/// floating point, vectors and aggregates.
+class TargetAlign : public SmallVectorTargetAlignElem, 16 {
+private:
+ /// Invalid alignment
+ /// This member is a signal that a requested alignment type and
+ /// bit width were not found in the SmallVector.
+ static const TargetAlignElem InvalidAlignmentElem;
+public:
+ /// Default constructor
+ TargetAlign();
+ /// Destructor
+ ~TargetAlign() { }
+ /// Copy constructor
+ TargetAlign(const TargetAlign src);
+ /// Assignment operator
+ TargetAlign operator=(const TargetAlign rhs);
+ /// Add elements to the container.
+ ///
+ /// Adds elements to the container, keeping the container sorted. If the
+ /// requested alignment type (@a align_type) and bit width (@a bit_width)
+ /// exist in the container, then the matching element's ABI and preferred
+ /// alignments are overwritten with @a abi_align and @a pref_align.
+ void set(AlignTypeEnum align_type, short bit_width, unsigned char abi_align,
+ unsigned char pref_align);
+ /// Get the data associated with a given alignment type and bit width.
+ ///
+ /// @return InvalidAlignmentElem if not found, otherwise, the matching
+ /// TargetAlignElem.
+ const TargetAlignElem get(AlignTypeEnum align_type, short bit_width) const;
+ /// Valid alignment predicate.
+ ///
+ /// Predicate that tests a TargetAlignElem reference returned by get() against
+ /// InvalidAlignmentElem.
+ inline bool valid(const TargetAlignElem align) const {
+return (align != InvalidAlignmentElem);
+ }
+};
+
class TargetData : public ImmutablePass {
- bool LittleEndian
[llvm-commits] Stack and global alignment enhancement patch
Per Chris' suggestion to submit enhancement patches to llvm-commits,...
- Adds stack and global alignment options to TargetData specification
strings.
- Adds minimum stack and global alignment for aggregates.
-scooter
--
Scott Michel [EMAIL PROTECTED]
Member of Technical Staff, CSRD 310/336-5034
The Aerospace Corporation
--- old-llvm/include/llvm/Target/TargetData.h 2007-01-17 12:23:39.0
-0800
+++ new-llvm/include/llvm/Target/TargetData.h 2007-01-17 12:23:39.0
-0800
@@ -35,15 +35,39 @@
class TargetData : public ImmutablePass {
bool LittleEndian; // Defaults to false
- unsigned char BoolAlignment; // Defaults to 1 byte
- unsigned char ByteAlignment; // Defaults to 1 byte
- unsigned char ShortAlignment;// Defaults to 2 bytes
- unsigned char IntAlignment; // Defaults to 4 bytes
- unsigned char LongAlignment; // Defaults to 8 bytes
- unsigned char FloatAlignment;// Defaults to 4 bytes
- unsigned char DoubleAlignment; // Defaults to 8 bytes
- unsigned char PointerSize; // Defaults to 8 bytes
- unsigned char PointerAlignment; // Defaults to 8 bytes
+
+ // SAAlignment: Struct/Array alignments
+ unsigned char BoolSAAlignment; // Defaults to 1 byte
+ unsigned char ByteSAAlignment; // Defaults to 1 byte
+ unsigned char ShortSAAlignment; // Defaults to 2 bytes
+ unsigned char IntSAAlignment;// Defaults to 4 bytes
+ unsigned char LongSAAlignment; // Defaults to 8 bytes
+ unsigned char FloatSAAlignment; // Defaults to 4 bytes
+ unsigned char DoubleSAAlignment; // Defaults to 8 bytes
+ unsigned char PointerMemSize;// Defaults to 8 bytes
+ unsigned char PointerSAAlignment;// Defaults to 8 bytes
+
+ // Stack type alignments.
+ unsigned char BoolStackAlignment;// Defaults to BoolAlignment
+ unsigned char ByteStackAlignment;// Defaults to ByteAlignment
+ unsigned char ShortStackAlignment; // Defaults to ShortAlignment
+ unsigned char IntStackAlignment; // Defaults to IntAlignment
+ unsigned char LongStackAlignment;// Defaults to LongAlignment
+ unsigned char FloatStackAlignment; // Defaults to FloatAlignment
+ unsigned char DoubleStackAlignment; // Defaults to DoubleAlignment
+ unsigned char PointerStackAlignment; // Defaults to PointerAlignment
+ unsigned char AggMinStackAlignment; // Defaults to 4 bytes
+
+ // Global alignments
+ unsigned char BoolGlobalAlignment; // Defaults to BoolAlignment
+ unsigned char ByteGlobalAlignment; // Defaults to ByteAlignment
+ unsigned char ShortGlobalAlignment; // Defaults to ShortAlignment
+ unsigned char IntGlobalAlignment;// Defaults to IntAlignment
+ unsigned char LongGlobalAlignment; // Defaults to LongAlignment
+ unsigned char FloatGlobalAlignment; // Defaults to FloatAlignment
+ unsigned char DoubleGlobalAlignment; // Defaults to DoubleAlignment
+ unsigned char PointerGlobalAlignment;// Defaults to PointerAlignment
+ unsigned char AggMinGlobalAlignment; // Defaults to 4 bytes
public:
/// Default ctor - This has to exist, because this is a pass, but it should
@@ -68,15 +92,33 @@
TargetData(const TargetData TD) :
ImmutablePass(),
LittleEndian(TD.isLittleEndian()),
-BoolAlignment(TD.getBoolAlignment()),
-ByteAlignment(TD.getByteAlignment()),
-ShortAlignment(TD.getShortAlignment()),
-IntAlignment(TD.getIntAlignment()),
-LongAlignment(TD.getLongAlignment()),
-FloatAlignment(TD.getFloatAlignment()),
-DoubleAlignment(TD.getDoubleAlignment()),
-PointerSize(TD.getPointerSize()),
-PointerAlignment(TD.getPointerAlignment()) {
+BoolSAAlignment(TD.getBoolSAAlignment()),
+ByteSAAlignment(TD.getByteSAAlignment()),
+ShortSAAlignment(TD.getShortSAAlignment()),
+IntSAAlignment(TD.getIntSAAlignment()),
+LongSAAlignment(TD.getLongSAAlignment()),
+FloatSAAlignment(TD.getFloatSAAlignment()),
+DoubleSAAlignment(TD.getDoubleSAAlignment()),
+PointerMemSize(TD.getPointerSize()),
+PointerSAAlignment(TD.getPointerSAAlignment()),
+BoolStackAlignment(TD.getBoolStackAlignment()),
+ByteStackAlignment(TD.getByteStackAlignment()),
+ShortStackAlignment(TD.getShortStackAlignment()),
+IntStackAlignment(TD.getIntStackAlignment()),
+LongStackAlignment(TD.getLongStackAlignment()),
+FloatStackAlignment(TD.getFloatStackAlignment()),
+DoubleStackAlignment(TD.getDoubleStackAlignment()),
+PointerStackAlignment(TD.getPointerStackAlignment()),
+AggMinStackAlignment(TD.getAggMinStackAlignment()),
+BoolGlobalAlignment(TD.getBoolGlobalAlignment()),
+ByteGlobalAlignment(TD.getByteGlobalAlignment()),
+ShortGlobalAlignment(TD.getShortGlobalAlignment()),
+IntGlobalAlignment(TD.getIntGlobalAlignment()),
+LongGlobalAlignment(TD.getLongGlobalAlignment()),
+FloatGlobalAlignment
[llvm-commits] Round 2: ABI and preferred alignment enhancement
Previously known as struct/array vs. stack vs. global alignments...
-scooter
--
Scott Michel [EMAIL PROTECTED]
Member of Technical Staff, CSRD 310/336-5034
The Aerospace Corporation
--- old-llvm/include/llvm/Target/TargetData.h 2007-01-17 19:06:51.0
-0800
+++ new-llvm/include/llvm/Target/TargetData.h 2007-01-17 19:06:51.0
-0800
@@ -35,15 +35,28 @@
class TargetData : public ImmutablePass {
bool LittleEndian; // Defaults to false
- unsigned char BoolAlignment; // Defaults to 1 byte
- unsigned char ByteAlignment; // Defaults to 1 byte
- unsigned char ShortAlignment;// Defaults to 2 bytes
- unsigned char IntAlignment; // Defaults to 4 bytes
- unsigned char LongAlignment; // Defaults to 8 bytes
- unsigned char FloatAlignment;// Defaults to 4 bytes
- unsigned char DoubleAlignment; // Defaults to 8 bytes
- unsigned char PointerSize; // Defaults to 8 bytes
- unsigned char PointerAlignment; // Defaults to 8 bytes
+
+ // ABI alignments
+ unsigned char BoolABIAlignment; // Defaults to 1 byte
+ unsigned char ByteABIAlignment; // Defaults to 1 byte
+ unsigned char ShortABIAlignment; // Defaults to 2 bytes
+ unsigned char IntABIAlignment;// Defaults to 4 bytes
+ unsigned char LongABIAlignment; // Defaults to 8 bytes
+ unsigned char FloatABIAlignment; // Defaults to 4 bytes
+ unsigned char DoubleABIAlignment; // Defaults to 8 bytes
+ unsigned char PointerMemSize;// Defaults to 8 bytes
+ unsigned char PointerABIAlignment;// Defaults to 8 bytes
+
+ // Preferred stack/global type alignments
+ unsigned char BoolPrefAlignment;// Defaults to BoolABIAlignment
+ unsigned char BytePrefAlignment;// Defaults to ByteABIAlignment
+ unsigned char ShortPrefAlignment; // Defaults to ShortABIAlignment
+ unsigned char IntPrefAlignment; // Defaults to IntABIAlignment
+ unsigned char LongPrefAlignment;// Defaults to LongABIAlignment
+ unsigned char FloatPrefAlignment; // Defaults to FloatABIAlignment
+ unsigned char DoublePrefAlignment; // Defaults to DoubleABIAlignment
+ unsigned char PointerPrefAlignment; // Defaults to PointerABIAlignment
+ unsigned char AggMinPrefAlignment; // Defaults to 0 bytes
public:
/// Default ctor - This has to exist, because this is a pass, but it should
@@ -68,15 +81,24 @@
TargetData(const TargetData TD) :
ImmutablePass(),
LittleEndian(TD.isLittleEndian()),
-BoolAlignment(TD.getBoolAlignment()),
-ByteAlignment(TD.getByteAlignment()),
-ShortAlignment(TD.getShortAlignment()),
-IntAlignment(TD.getIntAlignment()),
-LongAlignment(TD.getLongAlignment()),
-FloatAlignment(TD.getFloatAlignment()),
-DoubleAlignment(TD.getDoubleAlignment()),
-PointerSize(TD.getPointerSize()),
-PointerAlignment(TD.getPointerAlignment()) {
+BoolABIAlignment(TD.getBoolABIAlignment()),
+ByteABIAlignment(TD.getByteABIAlignment()),
+ShortABIAlignment(TD.getShortABIAlignment()),
+IntABIAlignment(TD.getIntABIAlignment()),
+LongABIAlignment(TD.getLongABIAlignment()),
+FloatABIAlignment(TD.getFloatABIAlignment()),
+DoubleABIAlignment(TD.getDoubleABIAlignment()),
+PointerMemSize(TD.getPointerSize()),
+PointerABIAlignment(TD.getPointerABIAlignment()),
+BoolPrefAlignment(TD.getBoolPrefAlignment()),
+BytePrefAlignment(TD.getBytePrefAlignment()),
+ShortPrefAlignment(TD.getShortPrefAlignment()),
+IntPrefAlignment(TD.getIntPrefAlignment()),
+LongPrefAlignment(TD.getLongPrefAlignment()),
+FloatPrefAlignment(TD.getFloatPrefAlignment()),
+DoublePrefAlignment(TD.getDoublePrefAlignment()),
+PointerPrefAlignment(TD.getPointerPrefAlignment()),
+AggMinPrefAlignment(TD.getAggMinPrefAlignment()) {
}
~TargetData(); // Not virtual, do not subclass this class
@@ -86,10 +108,16 @@
/// Parse a target data layout string, initializing the various TargetData
/// members along the way. A TargetData specification string looks like
/// E-p:64:64-d:64-f:32-l:64-i:32-s:16-b:8-B:8 and specifies the
- /// target's endianess, the alignments of various data types and
- /// the size of pointers. The - is used as a separator and :
- /// separates a token from its argument. Alignment is indicated in bits
- /// and internally converted to the appropriate number of bytes.
+ /// target's endianess, the ABI alignments of various data types and
+ /// the size of pointers.
+ ///
+ /// - is used as a separator and : separates a token from its argument.
+ ///
+ /// Alignment is indicated in bits and internally converted to the
+ /// appropriate number of bytes.
+ ///
+ /// The preferred stack/global alignment specifications (:[prefalign]) are
+ /// optional and default to the ABI alignment.
///
/// Valid tokens:
/// br
@@ -97,20 +125,24 @@
/// eme/em
