[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.498 - 1.499
TargetLowering.cpp updated: 1.120 - 1.121
---
Log message:
Tidy up ValueType names in comments.
---
Diffs of the changes: (+5 -5)
LegalizeDAG.cpp|4 ++--
TargetLowering.cpp |6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.498
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.499
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.498 Mon Jun 18 16:28:10 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Jun 21 09:48:26 2007
@@ -5649,8 +5649,8 @@
/// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
-/// equivalent operation that returns a scalar (e.g. F32) or packed value
-/// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
+/// equivalent operation that returns a scalar (e.g. MVT::f32) or packed value
+/// (e.g. MVT::v4f32). When this is called, we know that PackedVT is the right
/// type for the result.
SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
MVT::ValueType NewVT) {
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.120
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.121
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.120 Thu Jun 21
09:42:22 2007
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cppThu Jun 21 09:48:26 2007
@@ -243,10 +243,10 @@
else
TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg;
- // If the target does not have native F64 support, expand it to I64. We will
+ // If the target does not have native f64 support, expand it to i64. We will
// be generating soft float library calls. If the target does not have native
- // support for F32, promote it to F64 if it is legal. Otherwise, expand it to
- // I32.
+ // support for f32, promote it to f64 if it is legal. Otherwise, expand it to
+ // i32.
if (isTypeLegal(MVT::f64))
TransformToType[MVT::f64] = MVT::f64;
else {
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.462 - 1.463
TargetLowering.cpp updated: 1.86 - 1.87
---
Log message:
Allow the target to override the ISD::CondCode that's to be used to test the
result of the comparison libcall against zero.
---
Diffs of the changes: (+29 -18)
LegalizeDAG.cpp| 22 --
TargetLowering.cpp | 25 +
2 files changed, 29 insertions(+), 18 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.462
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.463
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.462 Mon Jan 29 16:58:52 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jan 31 03:29:11 2007
@@ -3604,72 +3604,58 @@
if (VT == MVT::f32 || VT == MVT::f64) {
// Expand into one or more soft-fp libcall(s).
RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
- ISD::CondCode CC1, CC2 = ISD::SETCC_INVALID;
switch (castCondCodeSDNode(CC)-get()) {
case ISD::SETEQ:
case ISD::SETOEQ:
LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
-CC1 = ISD::SETEQ;
break;
case ISD::SETNE:
case ISD::SETUNE:
LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
-CC1 = ISD::SETNE;
break;
case ISD::SETGE:
case ISD::SETOGE:
LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
-CC1 = ISD::SETGE;
break;
case ISD::SETLT:
case ISD::SETOLT:
LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
-CC1 = ISD::SETLT;
break;
case ISD::SETLE:
case ISD::SETOLE:
LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
-CC1 = ISD::SETLE;
break;
case ISD::SETGT:
case ISD::SETOGT:
LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
-CC1 = ISD::SETGT;
break;
case ISD::SETUO:
+LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
+break;
case ISD::SETO:
LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
-CC1 = castCondCodeSDNode(CC)-get() == ISD::SETO
- ? ISD::SETEQ : ISD::SETNE;
break;
default:
LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
-CC1 = ISD::SETNE;
switch (castCondCodeSDNode(CC)-get()) {
case ISD::SETONE:
// SETONE = SETOLT | SETOGT
LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
- CC1 = ISD::SETLT;
// Fallthrough
case ISD::SETUGT:
LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
- CC2 = ISD::SETGT;
break;
case ISD::SETUGE:
LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
- CC2 = ISD::SETGE;
break;
case ISD::SETULT:
LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
- CC2 = ISD::SETLT;
break;
case ISD::SETULE:
LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
- CC2 = ISD::SETLE;
break;
case ISD::SETUEQ:
LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
- CC2 = ISD::SETEQ;
break;
default: assert(0 Unsupported FP setcc!);
}
@@ -3680,14 +3666,14 @@
DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
false /*sign irrelevant*/, Dummy);
Tmp2 = DAG.getConstant(0, MVT::i32);
- CC = DAG.getCondCode(CC1);
+ CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
LHS = ExpandLibCall(TLI.getLibcallName(LC2),
DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
false /*sign irrelevant*/, Dummy);
Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
- DAG.getCondCode(CC2));
+ DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
Tmp2 = SDOperand();
}
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.86
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.87
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.86 Fri Jan 12
17:30:31 2007
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cppWed Jan 31 03:29:11 2007
@@ -94,6 +94,30 @@
Names[RTLIB::OGT_F64] = __gtdf2;
Names[RTLIB::UO_F32] = __unordsf2;
Names[RTLIB::UO_F64] = __unorddf2;
+ Names[RTLIB::O_F32] = __unordsf2;
+ Names[RTLIB::O_F64] = __unorddf2;
+}
+
+/// InitCmpLibcallCCs - Set default comparison
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.454 - 1.455
TargetLowering.cpp updated: 1.83 - 1.84
---
Log message:
Store default libgcc routine names and allow them to be redefined by target.
---
Diffs of the changes: (+205 -82)
LegalizeDAG.cpp| 210 -
TargetLowering.cpp | 77 +++
2 files changed, 205 insertions(+), 82 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.454
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.455
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.454 Fri Jan 5 17:33:44 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Jan 11 20:11:51 2007
@@ -2284,11 +2284,11 @@
default: assert(0 Do not know how to expand this integer BinOp!);
case ISD::UDIV:
case ISD::SDIV:
- const char *FnName = Node-getOpcode() == ISD::UDIV
-? __udivsi3 : __divsi3;
+ RTLIB::Libcall LC = Node-getOpcode() == ISD::UDIV
+? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
SDOperand Dummy;
bool isSigned = Node-getOpcode() == ISD::SDIV;
- Result = ExpandLibCall(FnName, Node, isSigned, Dummy);
+ Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned,
Dummy);
};
break;
}
@@ -2470,16 +2470,18 @@
} else {
assert(Node-getValueType(0) == MVT::i32
Cannot expand this binary operator!);
- const char *FnName = Node-getOpcode() == ISD::UREM
-? __umodsi3 : __modsi3;
+ RTLIB::Libcall LC = Node-getOpcode() == ISD::UREM
+? RTLIB::UREM_I32 : RTLIB::SREM_I32;
SDOperand Dummy;
- Result = ExpandLibCall(FnName, Node, isSigned, Dummy);
+ Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned,
Dummy);
}
} else {
// Floating point mod - fmod libcall.
-const char *FnName = Node-getValueType(0) == MVT::f32 ?
fmodf:fmod;
+RTLIB::Libcall LC = Node-getValueType(0) == MVT::f32
+ ? RTLIB::REM_F32 : RTLIB::REM_F64;
SDOperand Dummy;
-Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
+Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
+ false/*sign irrelevant*/, Dummy);
}
break;
}
@@ -2720,15 +2722,22 @@
case ISD::FSIN:
case ISD::FCOS: {
MVT::ValueType VT = Node-getValueType(0);
-const char *FnName = 0;
+RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
switch(Node-getOpcode()) {
-case ISD::FSQRT: FnName = VT == MVT::f32 ? sqrtf : sqrt; break;
-case ISD::FSIN: FnName = VT == MVT::f32 ? sinf : sin; break;
-case ISD::FCOS: FnName = VT == MVT::f32 ? cosf : cos; break;
+case ISD::FSQRT:
+ LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
+ break;
+case ISD::FSIN:
+ LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
+ break;
+case ISD::FCOS:
+ LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64;
+ break;
default: assert(0 Unreachable!);
}
SDOperand Dummy;
-Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
+Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
+ false/*sign irrelevant*/, Dummy);
break;
}
}
@@ -2737,10 +2746,11 @@
break;
case ISD::FPOWI: {
// We always lower FPOWI into a libcall. No target support it yet.
-const char *FnName = Node-getValueType(0) == MVT::f32
-? __powisf2 : __powidf2;
+RTLIB::Libcall LC = Node-getValueType(0) == MVT::f32
+ ? RTLIB::POWI_F32 : RTLIB::POWI_F64;
SDOperand Dummy;
-Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
+Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
+ false/*sign irrelevant*/, Dummy);
break;
}
case ISD::BIT_CONVERT:
@@ -2909,24 +2919,29 @@
case Expand: {
// Convert f32 / f64 to i32 / i64.
MVT::ValueType VT = Op.getValueType();
- const char *FnName = 0;
+ RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
switch (Node-getOpcode()) {
case ISD::FP_TO_SINT:
if (Node-getOperand(0).getValueType() == MVT::f32)
- FnName = (VT == MVT::i32) ? __fixsfsi : __fixsfdi;
+ LC = (VT == MVT::i32)
+? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
else
- FnName = (VT == MVT::i32) ? __fixdfsi : __fixdfdi;
+ LC = (VT == MVT::i32)
+? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
break;
case ISD::FP_TO_UINT:
if (Node-getOperand(0).getValueType() == MVT::f32)
- FnName = (VT
