[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.215 - 1.216
PPCISelLowering.cpp updated: 1.221 - 1.222
PPCInstrInfo.td updated: 1.254 - 1.255
---
Log message:
add an initial cut at preinc loads for ppc32. This is broken for ppc64
(because the 64-bit reg target versions aren't implemented yet), doesn't
support r+r addr modes, and doesn't handle stores, but it works otherwise. :)
This is disabled unless -enable-ppc-preinc is passed to llc for now.
---
Diffs of the changes: (+88 -22)
PPCISelDAGToDAG.cpp | 38 ++
PPCISelLowering.cpp | 27 ++-
PPCInstrInfo.td | 45 -
3 files changed, 88 insertions(+), 22 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.215
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.216
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.215 Wed Nov 8 14:33:09 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Nov 9 20:08:47 2006
@@ -818,6 +818,44 @@
// Other cases are autogenerated.
break;
}
+
+ case ISD::LOAD: {
+// Handle preincrement loads.
+LoadSDNode *LD = castLoadSDNode(Op);
+MVT::ValueType LoadedVT = LD-getLoadedVT();
+
+// Normal loads are handled by code generated from the .td file.
+if (LD-getAddressingMode() != ISD::PRE_INC)
+ break;
+
+unsigned Opcode;
+bool isSExt = LD-getExtensionType() == ISD::SEXTLOAD;
+assert(!isSExt || LoadedVT == MVT::i16 Invalid sext update load);
+switch (LoadedVT) {
+default: assert(0 Invalid PPC load type!);
+case MVT::f64: Opcode = PPC::LFDU; break;
+case MVT::f32: Opcode = PPC::LFSU; break;
+case MVT::i32: Opcode = PPC::LWZU; break;
+case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
+case MVT::i8: Opcode = PPC::LBZU; break;
+}
+
+SDOperand Offset = LD-getOffset();
+if (isaConstantSDNode(Offset)) {
+ SDOperand Chain = LD-getChain();
+ SDOperand Base = LD-getBasePtr();
+ AddToISelQueue(Chain);
+ AddToISelQueue(Base);
+ AddToISelQueue(Offset);
+ SDOperand Ops[] = { Offset, Base, Chain };
+ // FIXME: PPC64
+ return CurDAG-getTargetNode(Opcode, MVT::i32, MVT::i32,
+ MVT::Other, Ops, 3);
+} else {
+ assert(0 R+R preindex loads not supported yet!);
+}
+ }
+
case ISD::AND: {
unsigned Imm, Imm2, SH, MB, ME;
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.221
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.222
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.221 Thu Nov 9 13:11:50 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Nov 9 20:08:47 2006
@@ -26,8 +26,11 @@
#include llvm/Intrinsics.h
#include llvm/Support/MathExtras.h
#include llvm/Target/TargetOptions.h
+#include llvm/Support/CommandLine.h
using namespace llvm;
+static cl::optbool EnablePPCPreinc(enable-ppc-preinc);
+
PPCTargetLowering::PPCTargetLowering(PPCTargetMachine TM)
: TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
@@ -861,29 +864,27 @@
SDOperand Offset,
ISD::MemIndexedMode AM,
SelectionDAG DAG) {
- return false;
+ // Disabled by default for now.
+ if (!EnablePPCPreinc) return false;
-#if 0
- MVT::ValueType VT;
SDOperand Ptr;
if (LoadSDNode *LD = dyn_castLoadSDNode(N)) {
Ptr = LD-getBasePtr();
-VT = LD-getLoadedVT();
-
-// TODO: handle other cases.
-if (VT != MVT::i32) return false;
} else if (StoreSDNode *ST = dyn_castStoreSDNode(N)) {
-Ptr = ST-getBasePtr();
-VT = ST-getStoredVT();
-// TODO: handle other cases.
+ST = ST;
+//Ptr = ST-getBasePtr();
+//VT = ST-getStoredVT();
+// TODO: handle stores.
return false;
} else
return false;
+ // TODO: Handle reg+reg.
+ if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
+return false;
-
- return false;
-#endif
+ AM = ISD::PRE_INC;
+ return true;
}
//===--===//
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.254
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.255
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.254 Tue Nov 7 20:13:12 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Thu Nov 9 20:08:47 2006
@@ -422,9 +422,44 @@
lwz $rD, $src, LdStGeneral,
[(set GPRC:$rD, (load iaddr:$src))];
-def LWZU : DForm_133, (ops GPRC:$rD, GPRC:$rA_result, i32imm:$disp, GPRC:$rA),
+def LFS : DForm_848, (ops F4RC:$rD, memri:$src),
+ lfs $rD, $src, LdStLFDU,
+ [(set
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.192 - 1.193
PPCISelLowering.cpp updated: 1.192 - 1.193
PPCInstrInfo.td updated: 1.234 - 1.235
---
Log message:
Implement a bunch of 64-bit cleanliness work. With this, treeadd builds (but
doesn't work right).
---
Diffs of the changes: (+198 -113)
PPCISelDAGToDAG.cpp | 303
PPCISelLowering.cpp |4
PPCInstrInfo.td |4
3 files changed, 198 insertions(+), 113 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.192
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.193
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.192 Fri Jun 9 20:15:02 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Jun 26 19:04:13 2006
@@ -63,6 +63,18 @@
return CurDAG-getTargetConstant(Imm, MVT::i32);
}
+/// getI64Imm - Return a target constant with the specified value, of type
+/// i64.
+inline SDOperand getI64Imm(uint64_t Imm) {
+ return CurDAG-getTargetConstant(Imm, MVT::i64);
+}
+
+/// getSmallIPtrImm - Return a target constant of pointer type.
+inline SDOperand getSmallIPtrImm(unsigned Imm) {
+ return CurDAG-getTargetConstant(Imm, PPCLowering.getPointerTy());
+}
+
+
/// getGlobalBaseReg - insert code into the entry mbb to materialize the
PIC
/// base register. Return the virtual register that holds this value.
SDOperand getGlobalBaseReg();
@@ -111,7 +123,7 @@
case 'o': // offsetable
if (!SelectAddrImm(Op, Op0, Op1)) {
Select(Op0, Op); // r+0.
- Op1 = getI32Imm(0);
+ Op1 = getSmallIPtrImm(0);
}
break;
case 'v': // not offsetable
@@ -290,26 +302,73 @@
MachineBasicBlock FirstMBB = BB-getParent()-front();
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
SSARegMap *RegMap = BB-getParent()-getSSARegMap();
-// FIXME: when we get to LP64, we will need to create the appropriate
-// type of register here.
-GlobalBaseReg = RegMap-createVirtualRegister(PPC::GPRCRegisterClass);
+
+if (PPCLowering.getPointerTy() == MVT::i32)
+ GlobalBaseReg = RegMap-createVirtualRegister(PPC::GPRCRegisterClass);
+else
+ GlobalBaseReg = RegMap-createVirtualRegister(PPC::G8RCRegisterClass);
+
BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
}
- return CurDAG-getRegister(GlobalBaseReg, MVT::i32);
+ return CurDAG-getRegister(GlobalBaseReg, PPCLowering.getPointerTy());
}
+/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
+/// or 64-bit immediate, and if the value can be accurately represented as a
+/// sign extension from a 16-bit value. If so, this returns true and the
+/// immediate.
+static bool isIntS16Immediate(SDNode *N, short Imm) {
+ if (N-getOpcode() != ISD::Constant)
+return false;
-// isIntImmediate - This method tests to see if a constant operand.
-// If so Imm will receive the 32 bit value.
-static bool isIntImmediate(SDNode *N, unsigned Imm) {
- if (N-getOpcode() == ISD::Constant) {
+ Imm = (short)castConstantSDNode(N)-getValue();
+ if (N-getValueType(0) == MVT::i32)
+return Imm == (int32_t)castConstantSDNode(N)-getValue();
+ else
+return Imm == (int64_t)castConstantSDNode(N)-getValue();
+}
+
+static bool isIntS16Immediate(SDOperand Op, short Imm) {
+ return isIntS16Immediate(Op.Val, Imm);
+}
+
+
+/// isInt32Immediate - This method tests to see if the node is a 32-bit
constant
+/// operand. If so Imm will receive the 32-bit value.
+static bool isInt32Immediate(SDNode *N, unsigned Imm) {
+ if (N-getOpcode() == ISD::Constant N-getValueType(0) == MVT::i32) {
Imm = castConstantSDNode(N)-getValue();
return true;
}
return false;
}
+/// isInt64Immediate - This method tests to see if the node is a 64-bit
constant
+/// operand. If so Imm will receive the 64-bit value.
+static bool isInt64Immediate(SDNode *N, uint64_t Imm) {
+ if (N-getOpcode() == ISD::Constant N-getValueType(0) == MVT::i32) {
+Imm = castConstantSDNode(N)-getValue();
+return true;
+ }
+ return false;
+}
+
+// isInt32Immediate - This method tests to see if a constant operand.
+// If so Imm will receive the 32 bit value.
+static bool isInt32Immediate(SDOperand N, unsigned Imm) {
+ return isInt32Immediate(N.Val, Imm);
+}
+
+
+// isOpcWithIntImmediate - This method tests to see if the node is a specific
+// opcode and that it has a immediate integer right operand.
+// If so Imm will receive the 32 bit value.
+static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned Imm) {
+ return N-getOpcode() == Opc isInt32Immediate(N-getOperand(1).Val, Imm);
+}
+
+
// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
// any number of 0s on either side. The 1s are allowed to
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.185 - 1.186
PPCISelLowering.cpp updated: 1.178 - 1.179
PPCInstrInfo.td updated: 1.218 - 1.219
---
Log message:
Switch PPC over to a call-selection model where the lowering code creates
the copyto/fromregs instead of making the PPCISD::CALL selection code create
them. This vastly simplifies the selection code, and moves the ABI handling
parts into one place.
---
Diffs of the changes: (+136 -155)
PPCISelDAGToDAG.cpp | 124 -
PPCISelLowering.cpp | 157 ++--
PPCInstrInfo.td | 10 ++-
3 files changed, 136 insertions(+), 155 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.185
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.186
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.185 Tue May 16 18:54:25 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Wed May 17 01:01:33 2006
@@ -874,129 +874,55 @@
SDOperand PPCDAGToDAGISel::SelectCALL(SDOperand Op) {
SDNode *N = Op.Val;
- SDOperand Chain;
+ SDOperand Chain, Flag;
Select(Chain, N-getOperand(0));
+ if (N-getNumOperands() == 3) // input flag
+Select(Flag, N-getOperand(2));
unsigned CallOpcode;
- std::vectorSDOperand CallOperands;
-
+
+ std::vectorSDOperand CallArgs;
if (GlobalAddressSDNode *GASD =
dyn_castGlobalAddressSDNode(N-getOperand(1))) {
CallOpcode = PPC::BL;
-CallOperands.push_back(N-getOperand(1));
+CallArgs.push_back(N-getOperand(1));
} else if (ExternalSymbolSDNode *ESSDN =
dyn_castExternalSymbolSDNode(N-getOperand(1))) {
CallOpcode = PPC::BL;
-CallOperands.push_back(N-getOperand(1));
+CallArgs.push_back(N-getOperand(1));
} else if (isaConstantSDNode(N-getOperand(1))
isCallCompatibleAddress(castConstantSDNode(N-getOperand(1 {
ConstantSDNode *C = castConstantSDNode(N-getOperand(1));
CallOpcode = PPC::BLA;
-CallOperands.push_back(getI32Imm((int)C-getValue() 2));
+CallArgs.push_back(getI32Imm((int)C-getValue() 2));
} else {
// Copy the callee address into the CTR register.
SDOperand Callee;
Select(Callee, N-getOperand(1));
-Chain = SDOperand(CurDAG-getTargetNode(PPC::MTCTR, MVT::Other, Callee,
-Chain), 0);
+if (Flag.Val)
+ Chain = SDOperand(CurDAG-getTargetNode(PPC::MTCTR, MVT::Other,
MVT::Flag,
+ Callee, Chain, Flag), 0);
+else
+ Chain = SDOperand(CurDAG-getTargetNode(PPC::MTCTR, MVT::Other,
MVT::Flag,
+ Callee, Chain), 0);
+Flag = Chain.getValue(1);
// Copy the callee address into R12 on darwin.
-SDOperand R12 = CurDAG-getRegister(PPC::R12, MVT::i32);
-Chain = CurDAG-getNode(ISD::CopyToReg, MVT::Other, Chain, R12, Callee);
+Chain = CurDAG-getCopyToReg(Chain, PPC::R12, Callee, Flag);
+Flag = Chain.getValue(1);
-CallOperands.push_back(R12);
CallOpcode = PPC::BCTRL;
}
- unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
- static const unsigned GPR[] = {
-PPC::R3, PPC::R4, PPC::R5, PPC::R6,
-PPC::R7, PPC::R8, PPC::R9, PPC::R10,
- };
- static const unsigned FPR[] = {
-PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
-PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
- };
- static const unsigned VR[] = {
-PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
-PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
- };
-
- SDOperand InFlag; // Null incoming flag value.
-
- for (unsigned i = 2, e = N-getNumOperands(); i != e; ++i) {
-unsigned DestReg = 0;
-MVT::ValueType RegTy = N-getOperand(i).getValueType();
-if (RegTy == MVT::i32) {
- assert(GPR_idx 8 Too many int args);
- DestReg = GPR[GPR_idx++];
-} else if (MVT::isFloatingPoint(N-getOperand(i).getValueType())) {
- assert(FPR_idx 13 Too many fp args);
- DestReg = FPR[FPR_idx++];
-} else {
- assert(MVT::isVector(N-getOperand(i).getValueType()) unknown arg!);
- assert(VR_idx 12 Too many vector args);
- DestReg = VR[VR_idx++];
-}
-
-if (N-getOperand(i).getOpcode() != ISD::UNDEF) {
- SDOperand Val;
- Select(Val, N-getOperand(i));
- Chain = CurDAG-getCopyToReg(Chain, DestReg, Val, InFlag);
- InFlag = Chain.getValue(1);
- CallOperands.push_back(CurDAG-getRegister(DestReg, RegTy));
-}
- }
-
- // Finally, once everything is in registers to pass to the call, emit the
- // call itself.
- if (InFlag.Val)
-CallOperands.push_back(InFlag); // Strong dep on register copies.
- else
-CallOperands.push_back(Chain);// Weak dep on whatever occurs before
+ // Emit the call itself.
+ CallArgs.push_back(Chain);
+ if (Flag.Val)
+CallArgs.push_back(Flag);
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.178 - 1.179
PPCISelLowering.cpp updated: 1.140 - 1.141
PPCInstrInfo.td updated: 1.214 - 1.215
---
Log message:
Add VRRC select support
---
Diffs of the changes: (+8 -2)
PPCISelDAGToDAG.cpp |5 -
PPCISelLowering.cpp |3 ++-
PPCInstrInfo.td |2 ++
3 files changed, 8 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.178
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.179
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.178 Sun Mar 26 04:06:40 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Sat Apr 8 17:45:08 2006
@@ -1219,8 +1219,11 @@
SelectCCOp = PPC::SELECT_CC_Int;
else if (N-getValueType(0) == MVT::f32)
SelectCCOp = PPC::SELECT_CC_F4;
-else
+else if (N-getValueType(0) == MVT::f64)
SelectCCOp = PPC::SELECT_CC_F8;
+else
+ SelectCCOp = PPC::SELECT_CC_VRRC;
+
SDOperand N2, N3;
Select(N2, N-getOperand(2));
Select(N3, N-getOperand(3));
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.140
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.141
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.140 Sat Apr 8 02:14:26 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Apr 8 17:45:08 2006
@@ -1484,7 +1484,8 @@
MachineBasicBlock *BB) {
assert((MI-getOpcode() == PPC::SELECT_CC_Int ||
MI-getOpcode() == PPC::SELECT_CC_F4 ||
- MI-getOpcode() == PPC::SELECT_CC_F8)
+ MI-getOpcode() == PPC::SELECT_CC_F8 ||
+ MI-getOpcode() == PPC::SELECT_CC_VRRC)
Unexpected instr type to insert);
// To insert a SELECT_CC instruction, we actually have to insert the
diamond
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.214
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.215
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.214 Thu Mar 30 23:13:27 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Sat Apr 8 17:45:08 2006
@@ -247,6 +247,8 @@
i32imm:$BROPC), ; SELECT_CC PSEUDO!, [];
def SELECT_CC_F8 : Pseudo(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
i32imm:$BROPC), ; SELECT_CC PSEUDO!, [];
+ def SELECT_CC_VRRC: Pseudo(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F,
+ i32imm:$BROPC), ; SELECT_CC PSEUDO!, [];
}
let isTerminator = 1, noResults = 1, PPC970_Unit = 7 in {
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.169 - 1.170
PPCISelLowering.cpp updated: 1.103 - 1.104
PPCInstrInfo.td updated: 1.196 - 1.197
---
Log message:
Add support for generating vspltw, instead of a vperm instruction with a
constant pool load. This generates significantly nicer code for splats.
When tblgen gets bugfixed, we can remove the custom selection code.
---
Diffs of the changes: (+41 -13)
PPCISelDAGToDAG.cpp | 16
PPCISelLowering.cpp | 28 +++-
PPCInstrInfo.td | 10 ++
3 files changed, 41 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.169
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.170
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.169 Thu Mar 16 19:40:33 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Mar 20 00:51:10 2006
@@ -927,6 +927,22 @@
switch (N-getOpcode()) {
default: break;
+ case ISD::VECTOR_SHUFFLE:
+// FIXME: This should be autogenerated from the .td file, it is here for
now
+// due to bugs in tblgen.
+if (Op.getOperand(1).getOpcode() == ISD::UNDEF
+(Op.getValueType() == MVT::v4f32 || Op.getValueType() == MVT::v4i32)
+PPC::isSplatShuffleMask(Op.getOperand(2).Val)) {
+ SDOperand N0;
+ Select(N0, N-getOperand(0));
+
+ Result = CodeGenMap[Op] =
+SDOperand(CurDAG-getTargetNode(PPC::VSPLTW, MVT::v4f32,
+ getI32Imm(PPC::getVSPLTImmediate(Op.getOperand(2).Val)),
+N0), 0);
+ return;
+}
+assert(0 ILLEGAL VECTOR_SHUFFLE!);
case ISD::SETCC:
Result = SelectSETCC(Op);
return;
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.103
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.104
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.103 Mon Mar 20 00:37:44 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Mar 20 00:51:10 2006
@@ -245,6 +245,12 @@
/// VSPLTB/VSPLTH/VSPLTW.
bool PPC::isSplatShuffleMask(SDNode *N) {
assert(N-getOpcode() == ISD::BUILD_VECTOR);
+
+ // We can only splat 8-bit, 16-bit, and 32-bit quantities.
+ if (N-getNumOperands() != 4 N-getNumOperands() != 8
+ N-getNumOperands() != 16)
+return false;
+
// This is a splat operation if each element of the permute is the same, and
// if the value doesn't reference the second vector.
SDOperand Elt = N-getOperand(0);
@@ -263,11 +269,10 @@
/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
unsigned PPC::getVSPLTImmediate(SDNode *N) {
assert(isSplatShuffleMask(N));
- return castConstantSDNode(N)-getValue();
+ return castConstantSDNode(N-getOperand(0))-getValue();
}
-
/// LowerOperation - Provide custom lowering hooks for some operations.
///
SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG DAG) {
@@ -602,17 +607,22 @@
DAG.getSrcValue(NULL));
}
case ISD::VECTOR_SHUFFLE: {
-// FIXME: Cases that are handled by instructions that take permute
-// immediates (such as vsplt*) shouldn't be lowered here! Also handle
cases
-// that are cheaper to do as multiple such instructions than as a constant
-// pool load/vperm pair.
+SDOperand V1 = Op.getOperand(0);
+SDOperand V2 = Op.getOperand(1);
+SDOperand PermMask = Op.getOperand(2);
+
+// Cases that are handled by instructions that take permute immediates
+// (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
+// selected by the instruction selector.
+if (PPC::isSplatShuffleMask(PermMask.Val) V2.getOpcode() == ISD::UNDEF)
+ break;
+
+// TODO: Handle more cases, and also handle cases that are cheaper to do as
+// multiple such instructions than as a constant pool load/vperm pair.
// Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
// vector that will get spilled to the constant pool.
-SDOperand V1 = Op.getOperand(0);
-SDOperand V2 = Op.getOperand(1);
if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
-SDOperand PermMask = Op.getOperand(2);
// The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
// that it is in input element units, not in bytes. Convert now.
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.196
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.197
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.196 Mon Mar 20 00:15:45 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Mon Mar 20 00:51:10 2006
@@ -1032,10 +1032,12 @@
vsplth $vD, $vB, $UIMM, VecPerm,
[];
-//def VSPLTW : VXForm_1652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
-// vspltw $vD, $vB, $UIMM, VecPerm,
-//
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.139 - 1.140
PPCISelLowering.cpp updated: 1.49 - 1.50
PPCInstrInfo.td updated: 1.153 - 1.154
---
Log message:
Add support for TargetConstantPool nodes to the dag isel emitter, and use
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
---
Diffs of the changes: (+40 -29)
PPCISelDAGToDAG.cpp | 29 +
PPCISelLowering.cpp | 35 +++
PPCInstrInfo.td |5 -
3 files changed, 40 insertions(+), 29 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.139
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.140
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.139 Tue Dec 6 14:56:18 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Fri Dec 9 20:36:00 2005
@@ -423,7 +423,8 @@
assert(!castConstantSDNode(Addr.getOperand(1).getOperand(1))-getValue()
Cannot handle constant offsets yet!);
Op1 = Addr.getOperand(1).getOperand(0); // The global address.
- assert(Op1.getOpcode() == ISD::TargetGlobalAddress);
+ assert(Op1.getOpcode() == ISD::TargetGlobalAddress ||
+ Op1.getOpcode() == ISD::TargetConstantPool);
Op2 = Select(Addr.getOperand(0));
return false; // [g+r]
} else {
@@ -433,20 +434,11 @@
}
}
- if (FrameIndexSDNode *FI = dyn_castFrameIndexSDNode(Addr)) {
-Op1 = getI32Imm(0);
+ if (FrameIndexSDNode *FI = dyn_castFrameIndexSDNode(Addr))
Op2 = CurDAG-getTargetFrameIndex(FI-getIndex(), MVT::i32);
-return false;
- } else if (ConstantPoolSDNode *CP = dyn_castConstantPoolSDNode(Addr)) {
-Op1 = Addr;
-if (PICEnabled)
- Op2 = CurDAG-getTargetNode(PPC::ADDIS, MVT::i32,
getGlobalBaseReg(),Op1);
-else
- Op2 = CurDAG-getTargetNode(PPC::LIS, MVT::i32, Op1);
-return false;
- }
+ else
+Op2 = Select(Addr);
Op1 = getI32Imm(0);
- Op2 = Select(Addr);
return false;
}
@@ -893,17 +885,6 @@
CurDAG-getTargetFrameIndex(FI, MVT::i32),
getI32Imm(0));
}
- case ISD::ConstantPool: {
-Constant *C = castConstantPoolSDNode(N)-get();
-SDOperand Tmp, CPI = CurDAG-getTargetConstantPool(C, MVT::i32);
-if (PICEnabled)
- Tmp = CurDAG-getTargetNode(PPC::ADDIS, MVT::i32,
getGlobalBaseReg(),CPI);
-else
- Tmp = CurDAG-getTargetNode(PPC::LIS, MVT::i32, CPI);
-if (N-hasOneUse())
- return CurDAG-SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
-return CodeGenMap[Op] = CurDAG-getTargetNode(PPC::LA, MVT::i32, Tmp, CPI);
- }
case ISD::FADD: {
MVT::ValueType Ty = N-getValueType(0);
if (!NoExcessFPPrecision) { // Match FMA ops
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.49
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.50
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.49Mon Dec 5 20:10:38 2005
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Dec 9 20:36:00 2005
@@ -94,9 +94,10 @@
// PowerPC doesn't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
- // We want to legalize GlobalAddress into the appropriate instructions to
- // materialize the address.
+ // We want to legalize GlobalAddress and ConstantPool nodes into the
+ // appropriate instructions to materialize the address.
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
+ setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
if (TM.getSubtargetPPCSubtarget().is64Bit()) {
// They also have instructions for converting between i64 and fp.
@@ -341,14 +342,40 @@
Tmp4, Tmp6, ISD::SETLE);
return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
}
+ case ISD::ConstantPool: {
+Constant *C = castConstantPoolSDNode(Op)-get();
+SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32);
+SDOperand Zero = DAG.getConstant(0, MVT::i32);
+
+if (PPCGenerateStaticCode) {
+ // Generate non-pic code that has direct accesses to the constant pool.
+ // The address of the global is just (hi(g)+lo(g)).
+ SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
+ SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
+ return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
+}
+
+// Only lower ConstantPool on Darwin.
+if (!getTargetMachine().getSubtargetPPCSubtarget().isDarwin()) break;
+SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
+if (PICEnabled) {
+ // With PIC, the first instruction is actually GR+hi(G).
+ Hi = DAG.getNode(ISD::ADD, MVT::i32,
+ DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
+}
+
+SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
+Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
+
