subject:"\[llvm\-commits\] CVS\: llvm\/lib\/Target\/X86\/X86RegisterInfo.cpp"

[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86TargetAsmInfo.cpp

2007-05-12 Thread Anton Korobeynikov



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.219 - 1.220
X86TargetAsmInfo.cpp updated: 1.41 - 1.42
---
Log message:

More DWARF-related things cleanup:
1. Fix PR1380: http://llvm.org/PR1380 
2. Apply Duncan's patch from PR1410: http://llvm.org/PR1410 
3. Insert workaround for one personality function per module as noted in 
PR1414: http://llvm.org/PR1414 
4. Emit correct debug frames for x86/linux. This partly fixes 
DebugInfo/2006-11-06-StackTrace.cpp: stack trace is 
shown correctly, but arguments for function on top of stack are displayed 
incorrectly.


---
Diffs of the changes:  (+10 -9)

 X86RegisterInfo.cpp  |   17 ++---
 X86TargetAsmInfo.cpp |2 --
 2 files changed, 10 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.219 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.220
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.219   Wed May  2 14:53:33 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Sat May 12 17:36:25 2007
@@ -1153,11 +1153,6 @@
TargetFrameInfo::StackGrowsUp ?
TAI-getAddressSize() : -TAI-getAddressSize());
 
-// Add return address to move list
-MachineLocation CSDst(StackPtr, stackGrowth);
-MachineLocation CSSrc(getRARegister());
-Moves.push_back(MachineMove(StartLabelId, CSDst, CSSrc));
-
 if (NumBytes) {
   // Show update of SP.
   if (hasFP(MF)) {
@@ -1282,10 +1277,18 @@
 
 void X86RegisterInfo::getInitialFrameState(std::vectorMachineMove Moves)
  const 
{
-  // Initial state of the frame pointer is esp.
+  // Calculate amount of bytes used for return address storing
+  int stackGrowth = (Is64Bit ? -8 : -4);
+
+  // Initial state of the frame pointer is esp+4.
   MachineLocation Dst(MachineLocation::VirtualFP);
-  MachineLocation Src(StackPtr, 0);
+  MachineLocation Src(StackPtr, stackGrowth);
   Moves.push_back(MachineMove(0, Dst, Src));
+
+  // Add return address to move list
+  MachineLocation CSDst(StackPtr, stackGrowth);
+  MachineLocation CSSrc(getRARegister());
+  Moves.push_back(MachineMove(0, CSDst, CSSrc));
 }
 
 unsigned X86RegisterInfo::getEHExceptionRegister() const {


Index: llvm/lib/Target/X86/X86TargetAsmInfo.cpp
diff -u llvm/lib/Target/X86/X86TargetAsmInfo.cpp:1.41 
llvm/lib/Target/X86/X86TargetAsmInfo.cpp:1.42
--- llvm/lib/Target/X86/X86TargetAsmInfo.cpp:1.41   Sat May  5 04:04:50 2007
+++ llvm/lib/Target/X86/X86TargetAsmInfo.cppSat May 12 17:36:25 2007
@@ -113,7 +113,6 @@
 AbsoluteDebugSectionOffsets = true;
 AbsoluteEHSectionOffsets = false;
 SupportsDebugInformation = true;
-DwarfRequiresFrameSection = false;
 DwarfAbbrevSection =  \t.section\t.debug_abbrev,\\,@progbits;
 DwarfInfoSection =\t.section\t.debug_info,\\,@progbits;
 DwarfLineSection =\t.section\t.debug_line,\\,@progbits;
@@ -149,7 +148,6 @@
 AbsoluteDebugSectionOffsets = true;
 AbsoluteEHSectionOffsets = false;
 SupportsDebugInformation = true;
-DwarfRequiresFrameSection = false;
 DwarfSectionOffsetDirective = \t.secrel32\t;
 DwarfAbbrevSection =  \t.section\t.debug_abbrev,\dr\;
 DwarfInfoSection =\t.section\t.debug_info,\dr\;



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86RegisterInfo.td

2007-05-02 Thread Anton Korobeynikov



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.217 - 1.218
X86RegisterInfo.td updated: 1.42 - 1.43
---
Log message:

Emit correct DWARF reg # for RA (return address) register


---
Diffs of the changes:  (+7 -1)

 X86RegisterInfo.cpp |5 -
 X86RegisterInfo.td  |3 +++
 2 files changed, 7 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.217 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.218
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.217   Tue May  1 04:13:03 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed May  2 03:46:03 2007
@@ -1235,7 +1235,10 @@
 }
 
 unsigned X86RegisterInfo::getRARegister() const {
-  return X86::ST0;  // use a non-register register
+  if (Is64Bit)
+return X86::RIP;  // Should have dwarf #16
+  else
+return X86::EIP;  // Should have dwarf #8
 }
 
 unsigned X86RegisterInfo::getFrameRegister(MachineFunction MF) const {


Index: llvm/lib/Target/X86/X86RegisterInfo.td
diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.42 
llvm/lib/Target/X86/X86RegisterInfo.td:1.43
--- llvm/lib/Target/X86/X86RegisterInfo.td:1.42 Fri Apr 20 16:15:21 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.td  Wed May  2 03:46:03 2007
@@ -60,6 +60,7 @@
   def BP : RegisterWithSubRegsBP, [BPL], DwarfRegNum5;
   def SI : RegisterWithSubRegsSI, [SIL], DwarfRegNum6;
   def DI : RegisterWithSubRegsDI, [DIL], DwarfRegNum7;
+  def IP : RegisterIP, DwarfRegNum8;  
   
   // X86-64 only
   def R8W  : RegisterWithSubRegsR8W, [R8B], DwarfRegNum8;
@@ -80,6 +81,7 @@
   def EBP : RegisterWithSubRegsEBP, [BP], DwarfRegNum5;
   def ESI : RegisterWithSubRegsESI, [SI], DwarfRegNum6;
   def EDI : RegisterWithSubRegsEDI, [DI], DwarfRegNum7;
+  def EIP : RegisterWithSubRegsEIP, [IP], DwarfRegNum8;  
   
   // X86-64 only
   def R8D  : RegisterWithSubRegsR8D, [R8W], DwarfRegNum8;
@@ -109,6 +111,7 @@
   def R13 : RegisterWithSubRegsR13, [R13D], DwarfRegNum13;
   def R14 : RegisterWithSubRegsR14, [R14D], DwarfRegNum14;
   def R15 : RegisterWithSubRegsR15, [R15D], DwarfRegNum15;
+  def RIP : RegisterWithSubRegsRIP, [EIP],  DwarfRegNum16;
 
   // MMX Registers. These are actually aliased to ST0 .. ST7
   def MM0 : RegisterMM0, DwarfRegNum29;



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Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86RegisterInfo.td

2007-05-02 Thread Evan Cheng

Anton, I believe different OS / target / DWARF imeplementations  
assign different DWARF numbers to register. On Mac OS X, I am fairly  
certain x86 and x86-64 assign different numbers. :-(  We need a  
better way to handle this.

Evan

On May 2, 2007, at 1:46 AM, Anton Korobeynikov wrote:



 Changes in directory llvm/lib/Target/X86:

 X86RegisterInfo.cpp updated: 1.217 - 1.218
 X86RegisterInfo.td updated: 1.42 - 1.43
 ---
 Log message:

 Emit correct DWARF reg # for RA (return address) register


 ---
 Diffs of the changes:  (+7 -1)

  X86RegisterInfo.cpp |5 -
  X86RegisterInfo.td  |3 +++
  2 files changed, 7 insertions(+), 1 deletion(-)


 Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
 diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.217 llvm/lib/ 
 Target/X86/X86RegisterInfo.cpp:1.218
 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.217 Tue May  1  
 04:13:03 2007
 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp   Wed May  2 03:46:03 2007
 @@ -1235,7 +1235,10 @@
  }

  unsigned X86RegisterInfo::getRARegister() const {
 -  return X86::ST0;  // use a non-register register
 +  if (Is64Bit)
 +return X86::RIP;  // Should have dwarf #16
 +  else
 +return X86::EIP;  // Should have dwarf #8
  }

  unsigned X86RegisterInfo::getFrameRegister(MachineFunction MF)  
 const {


 Index: llvm/lib/Target/X86/X86RegisterInfo.td
 diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.42 llvm/lib/Target/ 
 X86/X86RegisterInfo.td:1.43
 --- llvm/lib/Target/X86/X86RegisterInfo.td:1.42   Fri Apr 20 16:15:21  
 2007
 +++ llvm/lib/Target/X86/X86RegisterInfo.tdWed May  2 03:46:03 2007
 @@ -60,6 +60,7 @@
def BP : RegisterWithSubRegsBP, [BPL], DwarfRegNum5;
def SI : RegisterWithSubRegsSI, [SIL], DwarfRegNum6;
def DI : RegisterWithSubRegsDI, [DIL], DwarfRegNum7;
 +  def IP : RegisterIP, DwarfRegNum8;

// X86-64 only
def R8W  : RegisterWithSubRegsR8W, [R8B], DwarfRegNum8;
 @@ -80,6 +81,7 @@
def EBP : RegisterWithSubRegsEBP, [BP], DwarfRegNum5;
def ESI : RegisterWithSubRegsESI, [SI], DwarfRegNum6;
def EDI : RegisterWithSubRegsEDI, [DI], DwarfRegNum7;
 +  def EIP : RegisterWithSubRegsEIP, [IP], DwarfRegNum8;

// X86-64 only
def R8D  : RegisterWithSubRegsR8D, [R8W], DwarfRegNum8;
 @@ -109,6 +111,7 @@
def R13 : RegisterWithSubRegsR13, [R13D], DwarfRegNum13;
def R14 : RegisterWithSubRegsR14, [R14D], DwarfRegNum14;
def R15 : RegisterWithSubRegsR15, [R15D], DwarfRegNum15;
 +  def RIP : RegisterWithSubRegsRIP, [EIP],  DwarfRegNum16;

// MMX Registers. These are actually aliased to ST0 .. ST7
def MM0 : RegisterMM0, DwarfRegNum29;



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Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86RegisterInfo.td

2007-05-02 Thread Anton Korobeynikov

Evan,

 Anton, I believe different OS / target / DWARF imeplementations  
 assign different DWARF numbers to register. On Mac OS X, I am fairly  
 certain x86 and x86-64 assign different numbers. :-(  We need a  
 better way to handle this.
I've specially checked this case. DWARF register numbers are fixed for
all i386-based platforms (at least ones, supported by GCC). The only
special case seems to be cygwin/mingw, but I'll handle this case
separately.

Currently, I'm interested only in narrowing necessary bits (probably,
platform-dependent). Anyway, this won't hurt :)
-- 
With best regards, Anton Korobeynikov.

Faculty of Mathematics  Mechanics, Saint Petersburg State University.


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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2007-04-25 Thread Chris Lattner



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.214 - 1.215
---
Log message:

do the multiplication as signed, so that 2*-2 == -4 instead of 4294967292
when promoted to 64-bits


---
Diffs of the changes:  (+2 -1)

 X86RegisterInfo.cpp |3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.214 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.215
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.214   Tue Apr 24 23:30:24 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed Apr 25 12:23:53 2007
@@ -1016,7 +1016,8 @@
 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction MF) 
const{
   if (hasFP(MF)) {
 // Create a frame entry for the EBP register that must be saved.
-int FrameIdx = MF.getFrameInfo()-CreateFixedObject(SlotSize,SlotSize * 
-2);
+int FrameIdx = MF.getFrameInfo()-CreateFixedObject(SlotSize,
+(int)SlotSize * -2);
 assert(FrameIdx == MF.getFrameInfo()-getObjectIndexBegin() 
Slot for EBP register must be last in order to be found!);
   }



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2007-04-25 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.215 - 1.216
---
Log message:

Fix for PR1348: http://llvm.org/PR1348 . If stack inc / dec amount is  
32-bits, issue a series of add / sub instructions.

---
Diffs of the changes:  (+27 -18)

 X86RegisterInfo.cpp |   45 +++--
 1 files changed, 27 insertions(+), 18 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.215 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.216
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.215   Wed Apr 25 12:23:53 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed Apr 25 20:09:28 2007
@@ -1023,6 +1023,30 @@
   }
 }
 
+/// emitSPUpdate - Emit a series of instructions to increment / decrement the
+/// stack pointer by a constant value.
+static
+void emitSPUpdate(MachineBasicBlock MBB, MachineBasicBlock::iterator MBBI,
+  unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
+  const TargetInstrInfo TII) {
+  bool isSub = NumBytes  0;
+  uint64_t Offset = isSub ? -NumBytes : NumBytes;
+  unsigned Opc = isSub
+? ((Offset  128) ?
+   (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
+   (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
+: ((Offset  128) ?
+   (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
+   (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
+  uint64_t Chunk = (1LL  31) - 1;
+
+  while (Offset) {
+uint64_t ThisVal = (Offset  Chunk) ? Chunk : Offset;
+BuildMI(MBB, MBBI, TII.get(Opc), 
StackPtr).addReg(StackPtr).addImm(ThisVal);
+Offset -= ThisVal;
+  }
+}
+
 void X86RegisterInfo::emitPrologue(MachineFunction MF) const {
   MachineBasicBlock MBB = MF.front();   // Prolog goes in entry BB
   MachineBasicBlock::iterator MBBI = MBB.begin();
@@ -1075,11 +1099,7 @@
 MBB.insert(MBBI, MI);
   }
 } else {
-  unsigned Opc = (NumBytes  128) ?
-(Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
-(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
-  MI= BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(NumBytes);
-  MBB.insert(MBBI, MI);
+  emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
 }
   }
 
@@ -1206,19 +1226,8 @@
 }
   }
 
-  if (NumBytes  0) {
-unsigned Opc = (NumBytes  128) ?
-  (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
-  (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
-BuildMI(MBB, MBBI, TII.get(Opc), StackPtr)
-.addReg(StackPtr).addImm(NumBytes);
-  } else if ((int)NumBytes  0) {
-unsigned Opc = (-NumBytes  128) ?
-  (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
-  (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
-BuildMI(MBB, MBBI, TII.get(Opc), StackPtr)
-.addReg(StackPtr).addImm(-NumBytes);
-  }
+  if (NumBytes)
+emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
 }
   }
 }



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2007-04-24 Thread Bill Wendling



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.211 - 1.212
---
Log message:

Add the PADDQ to the list.


---
Diffs of the changes:  (+1 -0)

 X86RegisterInfo.cpp |1 +
 1 files changed, 1 insertion(+)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.211 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.212
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.211   Tue Apr 17 12:21:52 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Apr 24 16:19:14 2007
@@ -769,6 +769,7 @@
   { X86::PACKUSWBrr,  X86::PACKUSWBrm },
   { X86::PADDBrr, X86::PADDBrm },
   { X86::PADDDrr, X86::PADDDrm },
+  { X86::PADDQrr, X86::PADDQrm },
   { X86::PADDSBrr,X86::PADDSBrm },
   { X86::PADDSWrr,X86::PADDSWrm },
   { X86::PADDWrr, X86::PADDWrm },



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2007-04-24 Thread Chris Lattner



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.212 - 1.213
---
Log message:

support 4G stack frames


---
Diffs of the changes:  (+9 -9)

 X86RegisterInfo.cpp |   18 +-
 1 files changed, 9 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.212 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.213
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.212   Tue Apr 24 16:19:14 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Apr 24 23:25:10 2007
@@ -939,7 +939,7 @@
 // 'sub ESP, amt' and the adjcallstackdown instruction into 'add ESP,
 // amt'
 MachineInstr *Old = I;
-unsigned Amount = Old-getOperand(0).getImmedValue();
+uint64_t Amount = Old-getOperand(0).getImm();
 if (Amount != 0) {
   // We need to keep the stack aligned properly.  To do this, we round the
   // amount of space needed for the outgoing arguments up to the next
@@ -954,7 +954,7 @@
   } else {
 assert(Old-getOpcode() == X86::ADJCALLSTACKUP);
 // factor out the amount the callee already popped.
-unsigned CalleeAmt = Old-getOperand(1).getImmedValue();
+uint64_t CalleeAmt = Old-getOperand(1).getImm();
 Amount -= CalleeAmt;
 if (Amount) {
   unsigned Opc = (Amount  128) ?
@@ -972,7 +972,7 @@
 // If we are performing frame pointer elimination and if the callee pops
 // something off the stack pointer, add it back.  We do this until we have
 // more advanced stack pointer tracking ability.
-if (unsigned CalleeAmt = I-getOperand(1).getImmedValue()) {
+if (uint64_t CalleeAmt = I-getOperand(1).getImm()) {
   unsigned Opc = (CalleeAmt  128) ?
 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
@@ -1001,8 +1001,8 @@
   MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
 
   // Now add the frame object offset to the offset from EBP.
-  int Offset = MF.getFrameInfo()-getObjectOffset(FrameIndex) +
-   MI.getOperand(i+3).getImmedValue()+SlotSize;
+  int64_t Offset = MF.getFrameInfo()-getObjectOffset(FrameIndex) +
+   MI.getOperand(i+3).getImm()+SlotSize;
 
   if (!hasFP(MF))
 Offset += MF.getFrameInfo()-getStackSize();
@@ -1182,8 +1182,8 @@
 // pop EBP
 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
   } else {
-// Get the number of bytes allocated from the FrameInfo...
-unsigned NumBytes = MFI-getStackSize();
+// Get the number of bytes allocated from the FrameInfo.
+uint64_t NumBytes = MFI-getStackSize();
 
 if (NumBytes) {// adjust stack pointer back: ESP += numbytes
   // If there is an ADD32ri or SUB32ri of ESP immediately before this
@@ -1194,12 +1194,12 @@
 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
  Opc == X86::ADD32ri || Opc == X86::ADD32ri8) 
 PI-getOperand(0).getReg() == StackPtr) {
-  NumBytes += PI-getOperand(2).getImmedValue();
+  NumBytes += PI-getOperand(2).getImm();
   MBB.erase(PI);
 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) 
PI-getOperand(0).getReg() == StackPtr) {
-  NumBytes -= PI-getOperand(2).getImmedValue();
+  NumBytes -= PI-getOperand(2).getImm();
   MBB.erase(PI);
 }
   }



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2007-04-24 Thread Chris Lattner



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.213 - 1.214
---
Log message:

support for 4G stack frames


---
Diffs of the changes:  (+4 -3)

 X86RegisterInfo.cpp |7 ---
 1 files changed, 4 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.213 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.214
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.213   Tue Apr 24 23:25:10 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Apr 24 23:30:24 2007
@@ -1036,7 +1036,7 @@
   unsigned FrameLabelId = 0;
   
   // Get the number of bytes to allocate from the FrameInfo
-  unsigned NumBytes = MFI-getStackSize();
+  uint64_t NumBytes = MFI-getStackSize();
 
   if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
 if (NumBytes = 4096  Subtarget-isTargetCygMing()) {
@@ -1091,7 +1091,8 @@
   if (hasFP(MF)) {
 // Get the offset of the stack slot for the EBP register... which is
 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
-int EBPOffset = MFI-getObjectOffset(MFI-getObjectIndexBegin())+SlotSize;
+int64_t EBPOffset =
+  MFI-getObjectOffset(MFI-getObjectIndexBegin())+SlotSize;
 // Update the frame offset adjustment.
 MFI-setOffsetAdjustment(SlotSize-NumBytes);
 
@@ -1128,7 +1129,7 @@
 // Add callee saved registers to move list.
 const std::vectorCalleeSavedInfo CSI = MFI-getCalleeSavedInfo();
 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
-  int Offset = MFI-getObjectOffset(CSI[I].getFrameIdx());
+  int64_t Offset = MFI-getObjectOffset(CSI[I].getFrameIdx());
   unsigned Reg = CSI[I].getReg();
   MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
   MachineLocation CSSrc(Reg);



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2007-04-03 Thread Bill Wendling



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.208 - 1.209
---
Log message:

Changed to new MMX_ recipes.


---
Diffs of the changes:  (+3 -3)

 X86RegisterInfo.cpp |6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.208 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.209
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.208   Tue Mar 20 03:09:38 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Apr  3 01:18:31 2007
@@ -90,7 +90,7 @@
   } else if (RC == X86::VR128RegClass) {
 Opc = X86::MOVAPSmr;
   } else if (RC == X86::VR64RegClass) {
-Opc = X86::MOVQ64mr;
+Opc = X86::MMX_MOVQ64mr;
   } else {
 assert(0  Unknown regclass);
 abort();
@@ -125,7 +125,7 @@
   } else if (RC == X86::VR128RegClass) {
 Opc = X86::MOVAPSrm;
   } else if (RC == X86::VR64RegClass) {
-Opc = X86::MOVQ64rm;
+Opc = X86::MMX_MOVQ64rm;
   } else {
 assert(0  Unknown regclass);
 abort();
@@ -159,7 +159,7 @@
   } else if (RC == X86::VR128RegClass) {
 Opc = X86::MOVAPSrr;
   } else if (RC == X86::VR64RegClass) {
-Opc = X86::MOVQ64rr;
+Opc = X86::MMX_MOVQ64rr;
   } else {
 assert(0  Unknown regclass);
 abort();



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86RegisterInfo.h

2007-02-27 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.205 - 1.206
X86RegisterInfo.h updated: 1.49 - 1.50
---
Log message:

PEI now passes a RegScavenger ptr to eliminateFrameIndex.

---
Diffs of the changes:  (+4 -2)

 X86RegisterInfo.cpp |3 ++-
 X86RegisterInfo.h   |3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.205 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.206
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.205   Thu Feb 22 19:10:04 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Feb 27 18:20:26 2007
@@ -968,7 +968,8 @@
   MBB.erase(I);
 }
 
-void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) 
const{
+void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
+  RegScavenger *RS) const{
   unsigned i = 0;
   MachineInstr MI = *II;
   MachineFunction MF = *MI.getParent()-getParent();


Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.49 
llvm/lib/Target/X86/X86RegisterInfo.h:1.50
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.49  Wed Feb 21 16:54:50 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.h   Tue Feb 27 18:20:26 2007
@@ -90,7 +90,8 @@
  MachineBasicBlock MBB,
  MachineBasicBlock::iterator MI) const;
 
-  void eliminateFrameIndex(MachineBasicBlock::iterator MI) const;
+  void eliminateFrameIndex(MachineBasicBlock::iterator MI,
+   RegScavenger *RS = NULL) const;
 
   void processFunctionBeforeFrameFinalized(MachineFunction MF) const;
 



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2007-02-22 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.204 - 1.205
---
Log message:

By default, spills kills the register being stored.

---
Diffs of the changes:  (+2 -1)

 X86RegisterInfo.cpp |3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.204 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.205
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.204   Wed Feb 21 16:54:50 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Feb 22 19:10:04 2007
@@ -93,7 +93,8 @@
 assert(0  Unknown regclass);
 abort();
   }
-  addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx).addReg(SrcReg);
+  addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx)
+.addReg(SrcReg, false, false, true);
 }
 
 void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock MBB,



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86RegisterInfo.h

2007-02-18 Thread Reid Spencer



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.201 - 1.202
X86RegisterInfo.h updated: 1.46 - 1.47
---
Log message:

For PR1207: http://llvm.org/PR1207 :
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.


---
Diffs of the changes:  (+0 -22)

 X86RegisterInfo.cpp |   16 
 X86RegisterInfo.h   |6 --
 2 files changed, 22 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.201 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.202
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.201   Sat Feb 17 05:06:00 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Sun Feb 18 21:20:00 2007
@@ -31,7 +31,6 @@
 #include llvm/Target/TargetMachine.h
 #include llvm/Target/TargetOptions.h
 #include llvm/Support/CommandLine.h
-#include llvm/ADT/BitVector.h
 #include llvm/ADT/STLExtras.h
 using namespace llvm;
 
@@ -884,21 +883,6 @@
   return Is64Bit ? CalleeSavedRegClasses64Bit : CalleeSavedRegClasses32Bit;
 }
 
-BitVector X86RegisterInfo::getReservedRegs(const MachineFunction MF) const {
-  BitVector Reserved(getNumRegs());
-  Reserved.set(X86::RSP);
-  Reserved.set(X86::ESP);
-  Reserved.set(X86::SP);
-  Reserved.set(X86::SPL);
-  if (hasFP(MF)) {
-Reserved.set(X86::RBP);
-Reserved.set(X86::EBP);
-Reserved.set(X86::BP);
-Reserved.set(X86::BPL);
-  }
-  return Reserved;
-}
-
 
//===--===//
 // Stack Frame Processing methods
 
//===--===//


Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.46 
llvm/lib/Target/X86/X86RegisterInfo.h:1.47
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.46  Sat Feb 17 05:06:00 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.h   Sun Feb 18 21:20:00 2007
@@ -78,12 +78,6 @@
   /// length of this list match the getCalleeSavedRegs() list.
   const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
 
-  /// getReservedRegs - Returns a bitset indexed by physical register number
-  /// indicating if a register is a special register that has particular uses 
and
-  /// should be considered unavailable at all times, e.g. SP, RA. This is used 
by
-  /// register scavenger to determine what registers are free.
-  BitVector getReservedRegs(const MachineFunction MF) const;
-
   bool hasFP(const MachineFunction MF) const;
 
   void eliminateCallFramePseudoInstr(MachineFunction MF,



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86RegisterInfo.h

2007-02-17 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.200 - 1.201
X86RegisterInfo.h updated: 1.45 - 1.46
---
Log message:

Added getReservedRegs().

---
Diffs of the changes:  (+22 -0)

 X86RegisterInfo.cpp |   16 
 X86RegisterInfo.h   |6 ++
 2 files changed, 22 insertions(+)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.200 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.201
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.200   Mon Jan 29 17:20:22 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Sat Feb 17 05:06:00 2007
@@ -31,6 +31,7 @@
 #include llvm/Target/TargetMachine.h
 #include llvm/Target/TargetOptions.h
 #include llvm/Support/CommandLine.h
+#include llvm/ADT/BitVector.h
 #include llvm/ADT/STLExtras.h
 using namespace llvm;
 
@@ -883,6 +884,21 @@
   return Is64Bit ? CalleeSavedRegClasses64Bit : CalleeSavedRegClasses32Bit;
 }
 
+BitVector X86RegisterInfo::getReservedRegs(const MachineFunction MF) const {
+  BitVector Reserved(getNumRegs());
+  Reserved.set(X86::RSP);
+  Reserved.set(X86::ESP);
+  Reserved.set(X86::SP);
+  Reserved.set(X86::SPL);
+  if (hasFP(MF)) {
+Reserved.set(X86::RBP);
+Reserved.set(X86::EBP);
+Reserved.set(X86::BP);
+Reserved.set(X86::BPL);
+  }
+  return Reserved;
+}
+
 
//===--===//
 // Stack Frame Processing methods
 
//===--===//


Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.45 
llvm/lib/Target/X86/X86RegisterInfo.h:1.46
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.45  Wed Jan 24 13:15:24 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.h   Sat Feb 17 05:06:00 2007
@@ -78,6 +78,12 @@
   /// length of this list match the getCalleeSavedRegs() list.
   const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
 
+  /// getReservedRegs - Returns a bitset indexed by physical register number
+  /// indicating if a register is a special register that has particular uses 
and
+  /// should be considered unavailable at all times, e.g. SP, RA. This is used 
by
+  /// register scavenger to determine what registers are free.
+  BitVector getReservedRegs(const MachineFunction MF) const;
+
   bool hasFP(const MachineFunction MF) const;
 
   void eliminateCallFramePseudoInstr(MachineFunction MF,



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2007-01-29 Thread Jim Laskey



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.198 - 1.199
---
Log message:

Landing pad-less eh for PPC.

---
Diffs of the changes:  (+3 -4)

 X86RegisterInfo.cpp |7 +++
 1 files changed, 3 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.198 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.199
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.198   Fri Jan 26 15:22:28 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Mon Jan 29 12:51:14 2007
@@ -997,8 +997,7 @@
   MachineInstr *MI;
   MachineModuleInfo *MMI = MFI-getMachineModuleInfo();
   
-  // Prepare for debug frame info.
-  bool hasDebugInfo = MMI  MMI-hasDebugInfo();
+  // Prepare for frame info.
   unsigned FrameLabelId = 0;
   
   // Get the number of bytes to allocate from the FrameInfo
@@ -1023,7 +1022,7 @@
 }
   }
 
-  if (hasDebugInfo) {
+  if (MMI) {
 // Mark effective beginning of when frame pointer becomes valid.
 FrameLabelId = MMI-NextLabelID();
 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId);
@@ -1053,7 +1052,7 @@
 MBB.insert(MBBI, MI);
   }
 
-  if (hasDebugInfo) {
+  if (MMI) {
 std::vectorMachineMove Moves = MMI-getFrameMoves();
 
 if (NumBytes) {



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2007-01-29 Thread Jim Laskey



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.199 - 1.200
---
Log message:

Only gather frame info if debug or eh.

---
Diffs of the changes:  (+2 -2)

 X86RegisterInfo.cpp |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.199 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.200
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.199   Mon Jan 29 12:51:14 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Mon Jan 29 17:20:22 2007
@@ -1022,7 +1022,7 @@
 }
   }
 
-  if (MMI) {
+  if (MMI  MMI-needsFrameInfo()) {
 // Mark effective beginning of when frame pointer becomes valid.
 FrameLabelId = MMI-NextLabelID();
 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId);
@@ -1052,7 +1052,7 @@
 MBB.insert(MBBI, MI);
   }
 
-  if (MMI) {
+  if (MMI  MMI-needsFrameInfo()) {
 std::vectorMachineMove Moves = MMI-getFrameMoves();
 
 if (NumBytes) {



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2007-01-24 Thread Jim Laskey



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.194 - 1.195
---
Log message:

80 columns

---
Diffs of the changes:  (+8 -4)

 X86RegisterInfo.cpp |   12 
 1 files changed, 8 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.194 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.195
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.194   Tue Jan 23 03:38:11 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed Jan 24 12:50:57 2007
@@ -926,7 +926,8 @@
   unsigned Opc = (Amount  128) ?
 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
-  New = BuildMI(TII.get(Opc),  
StackPtr).addReg(StackPtr).addImm(Amount);
+  New = BuildMI(TII.get(Opc),  StackPtr)
+.addReg(StackPtr).addImm(Amount);
 }
   }
 
@@ -1044,7 +1045,8 @@
   // If it's main() on Cygwin\Mingw32 we should align stack as well
   if (Fn-hasExternalLinkage()  Fn-getName() == main 
   Subtarget-isTargetCygMing()) {
-MI= BuildMI(TII.get(X86::AND32ri), 
X86::ESP).addReg(X86::ESP).addImm(-Align);
+MI= BuildMI(TII.get(X86::AND32ri), X86::ESP)
+.addReg(X86::ESP).addImm(-Align);
 MBB.insert(MBBI, MI);
 
 // Probe the stack
@@ -1104,12 +1106,14 @@
 unsigned Opc = (NumBytes  128) ?
   (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
   (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
-BuildMI(MBB, MBBI, TII.get(Opc), 
StackPtr).addReg(StackPtr).addImm(NumBytes);
+BuildMI(MBB, MBBI, TII.get(Opc), StackPtr)
+.addReg(StackPtr).addImm(NumBytes);
   } else if ((int)NumBytes  0) {
 unsigned Opc = (-NumBytes  128) ?
   (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
   (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
-BuildMI(MBB, MBBI, TII.get(Opc), 
StackPtr).addReg(StackPtr).addImm(-NumBytes);
+BuildMI(MBB, MBBI, TII.get(Opc), StackPtr)
+.addReg(StackPtr).addImm(-NumBytes);
   }
 }
   }



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2007-01-23 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.193 - 1.194
---
Log message:

PEI is now responsible for adding MaxCallFrameSize to frame size and align the 
stack. Each target can further adjust the frame size if necessary.

---
Diffs of the changes:  (+0 -17)

 X86RegisterInfo.cpp |   17 -
 1 files changed, 17 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.193 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.194
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.193   Mon Jan 22 18:57:47 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Jan 23 03:38:11 2007
@@ -991,29 +991,12 @@
   MachineBasicBlock::iterator MBBI = MBB.begin();
   MachineFrameInfo *MFI = MF.getFrameInfo();
   unsigned Align = MF.getTarget().getFrameInfo()-getStackAlignment();
-  unsigned AlignMask = Align - 1;
   const Function* Fn = MF.getFunction();
   const X86Subtarget* Subtarget = MF.getTarget().getSubtargetX86Subtarget();
   MachineInstr *MI;
   
   // Get the number of bytes to allocate from the FrameInfo
   unsigned NumBytes = MFI-getStackSize();
-  if (MFI-hasCalls() || MFI-hasVarSizedObjects()) {
-// When we have no frame pointer, we reserve argument space for call sites
-// in the function immediately on entry to the current function.  This
-// eliminates the need for add/sub ESP brackets around call sites.
-//
-if (!hasFP(MF))
-  NumBytes += MFI-getMaxCallFrameSize();
-
-// Round the size to a multiple of the alignment (don't forget the 4/8 byte
-// offset pushed by the caller though). No need to align the stack if this
-// is a leaf function.
-NumBytes = (((NumBytes+SlotSize) + AlignMask)  ~AlignMask) - SlotSize;
-  }
-
-  // Update frame info to pretend that this is part of the stack...
-  MFI-setStackSize(NumBytes);
 
   if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
 if (NumBytes = 4096  Subtarget-isTargetCygMing()) {



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86RegisterInfo.h X86RegisterInfo.td

2007-01-22 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.192 - 1.193
X86RegisterInfo.h updated: 1.43 - 1.44
X86RegisterInfo.td updated: 1.39 - 1.40
---
Log message:

hasFP() is now a virtual method of MRegisterInfo.

---
Diffs of the changes:  (+23 -13)

 X86RegisterInfo.cpp |4 ++--
 X86RegisterInfo.h   |2 ++
 X86RegisterInfo.td  |   30 +++---
 3 files changed, 23 insertions(+), 13 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.192 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.193
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.192   Sat Jan 20 04:17:53 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Mon Jan 22 18:57:47 2007
@@ -891,7 +891,7 @@
 // pointer register.  This is true if the function has variable sized allocas 
or
 // if frame pointer elimination is disabled.
 //
-static bool hasFP(const MachineFunction MF) {
+bool X86RegisterInfo::hasFP(const MachineFunction MF) const {
   return (NoFramePointerElim || 
   MF.getFrameInfo()-hasVarSizedObjects() ||
   MF.getInfoX86FunctionInfo()-getForceFramePointer());
@@ -998,7 +998,7 @@
   
   // Get the number of bytes to allocate from the FrameInfo
   unsigned NumBytes = MFI-getStackSize();
-  if (MFI-hasCalls() || MF.getFrameInfo()-hasVarSizedObjects()) {
+  if (MFI-hasCalls() || MFI-hasVarSizedObjects()) {
 // When we have no frame pointer, we reserve argument space for call sites
 // in the function immediately on entry to the current function.  This
 // eliminates the need for add/sub ESP brackets around call sites.


Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.43 
llvm/lib/Target/X86/X86RegisterInfo.h:1.44
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.43  Tue Jan  2 15:33:40 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.h   Mon Jan 22 18:57:47 2007
@@ -78,6 +78,8 @@
   /// length of this list match the getCalleeSavedRegs() list.
   const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
 
+  bool hasFP(const MachineFunction MF) const;
+
   void eliminateCallFramePseudoInstr(MachineFunction MF,
  MachineBasicBlock MBB,
  MachineBasicBlock::iterator MI) const;


Index: llvm/lib/Target/X86/X86RegisterInfo.td
diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.39 
llvm/lib/Target/X86/X86RegisterInfo.td:1.40
--- llvm/lib/Target/X86/X86RegisterInfo.td:1.39 Fri Sep  8 01:48:29 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.td  Mon Jan 22 18:57:47 2007
@@ -197,10 +197,11 @@
 GR8Class::iterator
 GR8Class::allocation_order_begin(const MachineFunction MF) const {
   const TargetMachine TM = MF.getTarget();
+  const MRegisterInfo *RI = TM.getRegisterInfo();
   const X86Subtarget Subtarget = TM.getSubtargetX86Subtarget();
   if (!Subtarget.is64Bit())
 return X86_GR8_AO_32;
-  else if (hasFP(MF))
+  else if (RI-hasFP(MF))
 return X86_GR8_AO_64_fp;
   else
 return X86_GR8_AO_64;
@@ -209,10 +210,11 @@
 GR8Class::iterator
 GR8Class::allocation_order_end(const MachineFunction MF) const {
   const TargetMachine TM = MF.getTarget();
+  const MRegisterInfo *RI = TM.getRegisterInfo();
   const X86Subtarget Subtarget = TM.getSubtargetX86Subtarget();
   if (!Subtarget.is64Bit())
 return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned));
-  else if (hasFP(MF))
+  else if (RI-hasFP(MF))
 return X86_GR8_AO_64_fp + (sizeof(X86_GR8_AO_64_fp) / 
sizeof(unsigned));
   else
 return X86_GR8_AO_64 + (sizeof(X86_GR8_AO_64) / sizeof(unsigned));
@@ -248,14 +250,15 @@
 GR16Class::iterator
 GR16Class::allocation_order_begin(const MachineFunction MF) const {
   const TargetMachine TM = MF.getTarget();
+  const MRegisterInfo *RI = TM.getRegisterInfo();
   const X86Subtarget Subtarget = TM.getSubtargetX86Subtarget();
   if (Subtarget.is64Bit()) {
-if (hasFP(MF))
+if (RI-hasFP(MF))
   return X86_GR16_AO_64_fp;
 else
   return X86_GR16_AO_64;
   } else {
-if (hasFP(MF))
+if (RI-hasFP(MF))
   return X86_GR16_AO_32_fp;
 else
   return X86_GR16_AO_32;
@@ -265,14 +268,15 @@
 GR16Class::iterator
 GR16Class::allocation_order_end(const MachineFunction MF) const {
   const TargetMachine TM = MF.getTarget();
+  const MRegisterInfo *RI = TM.getRegisterInfo();
   const X86Subtarget Subtarget = TM.getSubtargetX86Subtarget();
   if (Subtarget.is64Bit()) {
-if (hasFP(MF))
+if (RI-hasFP(MF))
   return 
X86_GR16_AO_64_fp+(sizeof(X86_GR16_AO_64_fp)/sizeof(unsigned));
 else
   return X86_GR16_AO_64 + (sizeof(X86_GR16_AO_64) / sizeof(unsigned));
   } else {
-if (hasFP(MF))
+if (RI-hasFP(MF))
   return

[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2007-01-20 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.191 - 1.192
---
Log message:

One more try...

---
Diffs of the changes:  (+3 -2)

 X86RegisterInfo.cpp |5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.191 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.192
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.191   Sat Jan 20 04:11:56 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Sat Jan 20 04:17:53 2007
@@ -998,12 +998,13 @@
   
   // Get the number of bytes to allocate from the FrameInfo
   unsigned NumBytes = MFI-getStackSize();
-  if (MFI-hasCalls()  !hasFP(MF))
+  if (MFI-hasCalls() || MF.getFrameInfo()-hasVarSizedObjects()) {
 // When we have no frame pointer, we reserve argument space for call sites
 // in the function immediately on entry to the current function.  This
 // eliminates the need for add/sub ESP brackets around call sites.
 //
-NumBytes += MFI-getMaxCallFrameSize();
+if (!hasFP(MF))
+  NumBytes += MFI-getMaxCallFrameSize();
 
 // Round the size to a multiple of the alignment (don't forget the 4/8 byte
 // offset pushed by the caller though). No need to align the stack if this



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2007-01-20 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.190 - 1.191
---
Log message:

Last check-in was bogus. There is no need to align the stack if the function is 
a leaf function (and without alloca).

---
Diffs of the changes:  (+6 -3)

 X86RegisterInfo.cpp |9 ++---
 1 files changed, 6 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.190 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.191
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.190   Fri Jan 19 20:08:16 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Sat Jan 20 04:11:56 2007
@@ -991,6 +991,7 @@
   MachineBasicBlock::iterator MBBI = MBB.begin();
   MachineFrameInfo *MFI = MF.getFrameInfo();
   unsigned Align = MF.getTarget().getFrameInfo()-getStackAlignment();
+  unsigned AlignMask = Align - 1;
   const Function* Fn = MF.getFunction();
   const X86Subtarget* Subtarget = MF.getTarget().getSubtargetX86Subtarget();
   MachineInstr *MI;
@@ -1004,9 +1005,11 @@
 //
 NumBytes += MFI-getMaxCallFrameSize();
 
-  // Round the size to a multiple of the alignment (don't forget the 4/8 byte
-  // offset though).
-  NumBytes = ((NumBytes+SlotSize)+Align-1)/Align*Align - SlotSize;
+// Round the size to a multiple of the alignment (don't forget the 4/8 byte
+// offset pushed by the caller though). No need to align the stack if this
+// is a leaf function.
+NumBytes = (((NumBytes+SlotSize) + AlignMask)  ~AlignMask) - SlotSize;
+  }
 
   // Update frame info to pretend that this is part of the stack...
   MFI-setStackSize(NumBytes);



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86RegisterInfo.h

2007-01-02 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.186 - 1.187
X86RegisterInfo.h updated: 1.42 - 1.43
---
Log message:

Fix naming inconsistency.

---
Diffs of the changes:  (+13 -13)

 X86RegisterInfo.cpp |   16 
 X86RegisterInfo.h   |   10 +-
 2 files changed, 13 insertions(+), 13 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.186 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.187
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.186   Thu Dec 14 15:55:39 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Jan  2 15:33:40 2007
@@ -853,30 +853,30 @@
 }
 
 
-const unsigned *X86RegisterInfo::getCalleeSaveRegs() const {
-  static const unsigned CalleeSaveRegs32Bit[] = {
+const unsigned *X86RegisterInfo::getCalleeSavedRegs() const {
+  static const unsigned CalleeSavedRegs32Bit[] = {
 X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
   };
-  static const unsigned CalleeSaveRegs64Bit[] = {
+  static const unsigned CalleeSavedRegs64Bit[] = {
 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
   };
 
-  return Is64Bit ? CalleeSaveRegs64Bit : CalleeSaveRegs32Bit;
+  return Is64Bit ? CalleeSavedRegs64Bit : CalleeSavedRegs32Bit;
 }
 
 const TargetRegisterClass* const*
-X86RegisterInfo::getCalleeSaveRegClasses() const {
-  static const TargetRegisterClass * const CalleeSaveRegClasses32Bit[] = {
+X86RegisterInfo::getCalleeSavedRegClasses() const {
+  static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
 X86::GR32RegClass, X86::GR32RegClass,
 X86::GR32RegClass, X86::GR32RegClass,  0
   };
-  static const TargetRegisterClass * const CalleeSaveRegClasses64Bit[] = {
+  static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
 X86::GR64RegClass, X86::GR64RegClass,
 X86::GR64RegClass, X86::GR64RegClass,
 X86::GR64RegClass, X86::GR64RegClass, 0
   };
 
-  return Is64Bit ? CalleeSaveRegClasses64Bit : CalleeSaveRegClasses32Bit;
+  return Is64Bit ? CalleeSavedRegClasses64Bit : CalleeSavedRegClasses32Bit;
 }
 
 
//===--===//


Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.42 
llvm/lib/Target/X86/X86RegisterInfo.h:1.43
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.42  Sun Nov  5 13:31:28 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.h   Tue Jan  2 15:33:40 2007
@@ -69,14 +69,14 @@
   unsigned OpNum,
   int FrameIndex) const;
 
-  /// getCalleeSaveRegs - Return a null-terminated list of all of the
+  /// getCalleeSavedRegs - Return a null-terminated list of all of the
   /// callee-save registers on this target.
-  const unsigned *getCalleeSaveRegs() const;
+  const unsigned *getCalleeSavedRegs() const;
 
-  /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
+  /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
   /// register classes to spill each callee-saved register with.  The order and
-  /// length of this list match the getCalleeSaveRegs() list.
-  const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
+  /// length of this list match the getCalleeSavedRegs() list.
+  const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
 
   void eliminateCallFramePseudoInstr(MachineFunction MF,
  MachineBasicBlock MBB,



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-12-14 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.184 - 1.185
---
Log message:

Added MOVSS2DIrr and MOVDI2SSrr to foldMemeoryOperand().

---
Diffs of the changes:  (+2 -0)

 X86RegisterInfo.cpp |2 ++
 1 files changed, 2 insertions(+)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.184 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.185
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.184   Thu Dec  7 16:21:48 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Dec 14 13:44:45 2006
@@ -511,6 +511,7 @@
   { X86::MOVPQIto64rr,X86::MOVPQIto64mr },
   { X86::MOVPS2SSrr,  X86::MOVPS2SSmr },
   { X86::MOVSDrr, X86::MOVSDmr },
+  { X86::MOVSS2DIrr,  X86::MOVSS2DImr },
   { X86::MOVSSrr, X86::MOVSSmr },
   { X86::MOVUPDrr,X86::MOVUPDmr },
   { X86::MOVUPSrr,X86::MOVUPSmr },
@@ -612,6 +613,7 @@
   { X86::MOVAPSrr,X86::MOVAPSrm },
   { X86::MOVDDUPrr,   X86::MOVDDUPrm },
   { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
+  { X86::MOVDI2SSrr,  X86::MOVDI2SSrm },
   { X86::MOVSD2PDrr,  X86::MOVSD2PDrm },
   { X86::MOVSDrr, X86::MOVSDrm },
   { X86::MOVSHDUPrr,  X86::MOVSHDUPrm },



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-12-06 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.182 - 1.183
---
Log message:

MI keeps a ptr of TargetInstrDescriptor, use it.

---
Diffs of the changes:  (+2 -1)

 X86RegisterInfo.cpp |3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.182 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.183
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.182   Fri Dec  1 15:52:58 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed Dec  6 19:21:59 2006
@@ -27,6 +27,7 @@
 #include llvm/CodeGen/MachineFrameInfo.h
 #include llvm/CodeGen/MachineLocation.h
 #include llvm/Target/TargetFrameInfo.h
+#include llvm/Target/TargetInstrInfo.h
 #include llvm/Target/TargetMachine.h
 #include llvm/Target/TargetOptions.h
 #include llvm/Support/CommandLine.h
@@ -289,7 +290,7 @@
   bool isTwoAddrFold = false;
   unsigned NumOps = TII.getNumOperands(MI-getOpcode());
   bool isTwoAddr = NumOps  1 
-TII.getOperandConstraint(MI-getOpcode(), 1, TOI::TIED_TO) != -1;
+MI-getInstrDescriptor()-getOperandConstraint(1, TOI::TIED_TO) != -1;
 
   MachineInstr *NewMI = NULL;
   // Folding a memory location into the two-address part of a two-address



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-11-17 Thread Jim Laskey



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.179 - 1.180
---
Log message:

Hopefully a good crack at making debugging work on intel -disable-fp-elim.


---
Diffs of the changes:  (+3 -1)

 X86RegisterInfo.cpp |4 +++-
 1 files changed, 3 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.179 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.180
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.179   Thu Nov 16 17:33:25 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Fri Nov 17 15:19:15 2006
@@ -1029,7 +1029,9 @@
 // Get the offset of the stack slot for the EBP register... which is
 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
 int EBPOffset = MFI-getObjectOffset(MFI-getObjectIndexBegin())+SlotSize;
-
+// Update the frame offset adjustment.
+MFI-setOffsetAdjustment(SlotSize-NumBytes);
+
 // Save EBP into the appropriate stack slot...
 // mov [ESP-offset], EBP
 MI = addRegOffset(BuildMI(TII, Is64Bit ? X86::MOV64mr : X86::MOV32mr, 5),



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-11-10 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.174 - 1.175
---
Log message:

Add implicit def / use operands to MachineInstr.

---
Diffs of the changes:  (+1 -1)

 X86RegisterInfo.cpp |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.174 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.175
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.174   Thu Nov  9 19:28:43 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Fri Nov 10 02:43:01 2006
@@ -196,7 +196,7 @@
   assert(MO.isReg()  Expected to fold into reg operand!);
   MIB = addFrameReference(MIB, FrameIndex);
 } else if (MO.isReg())
-  MIB = MIB.addReg(MO.getReg(), MO.isDef());
+  MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
 else if (MO.isImm())
   MIB = MIB.addImm(MO.getImm());
 else if (MO.isGlobalAddress())



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-11-02 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.171 - 1.172
---
Log message:

Dead code.

---
Diffs of the changes:  (+0 -4)

 X86RegisterInfo.cpp |4 
 1 files changed, 4 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.171 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.172
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.171   Fri Sep 22 16:43:59 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Nov  2 20:08:41 2006
@@ -1063,10 +1063,6 @@
   }
 
   if (hasFP(MF)) {
-// Get the offset of the stack slot for the EBP register... which is
-// guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
-int EBPOffset = MFI-getObjectOffset(MFI-getObjectIndexEnd()-1)+SlotSize;
-
 // mov ESP, EBP
 BuildMI(MBB, MBBI, Is64Bit ? X86::MOV64rr : X86::MOV32rr, 1, StackPtr).
   addReg(FramePtr);



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-09-08 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.168 - 1.169
---
Log message:

Fixed a FuseTwoAddrInst() bug: consider GlobalAddress and JumpTableIndex
in addition to immediate operands.


---
Diffs of the changes:  (+11 -6)

 X86RegisterInfo.cpp |   17 +++--
 1 files changed, 11 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.168 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.169
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.168   Fri Sep  8 01:48:29 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Fri Sep  8 16:08:13 2006
@@ -169,12 +169,17 @@
   
   // Loop over the rest of the ri operands, converting them over.
   for (unsigned i = 0; i != NumOps; ++i) {
-if (MI-getOperand(i+2).isReg())
-  MIB = MIB.addReg(MI-getOperand(i+2).getReg());
-else {
-  assert(MI-getOperand(i+2).isImm()  Unknown operand type!);
-  MIB = MIB.addImm(MI-getOperand(i+2).getImm());
-}
+MachineOperand MO = MI-getOperand(i+2);
+if (MO.isReg())
+  MIB = MIB.addReg(MO.getReg());
+else if (MO.isImm())
+  MIB = MIB.addImm(MO.getImm());
+else if (MO.isGlobalAddress())
+  MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
+else if (MO.isJumpTableIndex())
+  MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
+else
+  assert(0  Unknown operand type!);
   }
   return MIB;
 }



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86RegisterInfo.td

2006-08-17 Thread Chris Lattner



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.162 - 1.163
X86RegisterInfo.td updated: 1.37 - 1.38
---
Log message:

Constify some methods.  Patch provided by Anton Vayvod, thanks!


---
Diffs of the changes:  (+7 -7)

 X86RegisterInfo.cpp |2 +-
 X86RegisterInfo.td  |   12 ++--
 2 files changed, 7 insertions(+), 7 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.162 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.163
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.162   Thu Jul 20 17:52:28 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Aug 17 17:00:08 2006
@@ -737,7 +737,7 @@
 // pointer register.  This is true if the function has variable sized allocas 
or
 // if frame pointer elimination is disabled.
 //
-static bool hasFP(MachineFunction MF) {
+static bool hasFP(const MachineFunction MF) {
   return (NoFramePointerElim || 
   MF.getFrameInfo()-hasVarSizedObjects() ||
   MF.getInfoX86FunctionInfo()-getForceFramePointer());


Index: llvm/lib/Target/X86/X86RegisterInfo.td
diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.37 
llvm/lib/Target/X86/X86RegisterInfo.td:1.38
--- llvm/lib/Target/X86/X86RegisterInfo.td:1.37 Mon Aug  7 16:02:39 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.td  Thu Aug 17 17:00:08 2006
@@ -107,11 +107,11 @@
 
 def GR16 : RegisterClassX86, [i16], 16, [AX, CX, DX, SI, DI, BX, BP, SP] {
   let MethodProtos = [{
-iterator allocation_order_end(MachineFunction MF) const;
+iterator allocation_order_end(const MachineFunction MF) const;
   }];
   let MethodBodies = [{
 GR16Class::iterator
-GR16Class::allocation_order_end(MachineFunction MF) const {
+GR16Class::allocation_order_end(const MachineFunction MF) const {
   if (hasFP(MF)) // Does the function dedicate EBP to being a frame 
ptr?
 return end()-2;  // If so, don't allocate SP or BP
   else
@@ -123,11 +123,11 @@
 def GR32 : RegisterClassX86, [i32], 32, 
  [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP] {
   let MethodProtos = [{
-iterator allocation_order_end(MachineFunction MF) const;
+iterator allocation_order_end(const MachineFunction MF) const;
   }];
   let MethodBodies = [{
 GR32Class::iterator
-GR32Class::allocation_order_end(MachineFunction MF) const {
+GR32Class::allocation_order_end(const MachineFunction MF) const {
   if (hasFP(MF)) // Does the function dedicate EBP to being a frame 
ptr?
 return end()-2;  // If so, don't allocate ESP or EBP
   else
@@ -160,11 +160,11 @@
 def RST : RegisterClassX86, [f64], 32,
 [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] {
 let MethodProtos = [{
-iterator allocation_order_end(MachineFunction MF) const;
+iterator allocation_order_end(const MachineFunction MF) const;
   }];
   let MethodBodies = [{
 RSTClass::iterator
-RSTClass::allocation_order_end(MachineFunction MF) const {
+RSTClass::allocation_order_end(const MachineFunction MF) const {
   return begin();
 }
   }];



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-07-20 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.161 - 1.162
---
Log message:

Missing a space.

---
Diffs of the changes:  (+1 -1)

 X86RegisterInfo.cpp |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.161 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.162
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.161   Wed Jul 19 14:32:06 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Jul 20 17:52:28 2006
@@ -223,7 +223,7 @@
 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
   for (unsigned i = 1; i != NumEntries; ++i)
 if (!(Table[i-1]  Table[i])) {
-  std::cerr  Entries out of order  Table[i-1].from
+  std::cerr  Entries out of order   Table[i-1].from
 Table[i].from  \n;
   return false;
 }



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-06-12 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.157 - 1.158
---
Log message:

Cygwin support: use _alloca to allocate stack if  4k. Patch by Anton 
Korobeynikov.

---
Diffs of the changes:  (+21 -4)

 X86RegisterInfo.cpp |   25 +
 1 files changed, 21 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.157 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.158
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.157   Tue Jun  6 18:30:24 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Jun 13 00:14:44 2006
@@ -740,7 +740,7 @@
   const Function* Fn = MF.getFunction();
   const X86Subtarget* Subtarget = MF.getTarget().getSubtargetX86Subtarget();
   MachineInstr *MI;
-
+  
   // Get the number of bytes to allocate from the FrameInfo
   unsigned NumBytes = MFI-getStackSize();
   if (MFI-hasCalls() || MF.getFrameInfo()-hasVarSizedObjects()) {
@@ -760,9 +760,20 @@
   MFI-setStackSize(NumBytes);
 
   if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
-unsigned Opc = NumBytes  128 ? X86::SUB32ri8 : X86::SUB32ri;
-MI = BuildMI(Opc, 1, X86::ESP,MachineOperand::UseAndDef).addImm(NumBytes);
-MBB.insert(MBBI, MI);
+if (NumBytes = 4096  Subtarget-TargetType == X86Subtarget::isCygwin) {
+  // Function prologue calls _alloca to probe the stack when allocating  
+  // more than 4k bytes in one go. Touching the stack at 4K increments is  
+  // necessary to ensure that the guard pages used by the OS virtual memory
+  // manager are allocated in correct sequence.
+  MI = BuildMI(X86::MOV32ri, 2, X86::EAX).addImm(NumBytes);
+  MBB.insert(MBBI, MI);
+  MI = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(_alloca);
+  MBB.insert(MBBI, MI);
+} else {
+  unsigned Opc = NumBytes  128 ? X86::SUB32ri8 : X86::SUB32ri;
+  MI = BuildMI(Opc, 1, 
X86::ESP,MachineOperand::UseAndDef).addImm(NumBytes);
+  MBB.insert(MBBI, MI);
+}
   }
 
   if (hasFP(MF)) {
@@ -789,6 +800,12 @@
   Subtarget-TargetType == X86Subtarget::isCygwin) {
 MI = BuildMI(X86::AND32ri, 2, X86::ESP).addImm(-Align);
 MBB.insert(MBBI, MI);
+
+// Probe the stack
+MI = BuildMI(X86::MOV32ri, 2, X86::EAX).addImm(Align);
+MBB.insert(MBBI, MI);
+MI = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(_alloca);
+MBB.insert(MBBI, MI);
   }
 }
 



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Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-06-12 Thread Chris Lattner



Does this fix PR331?

-Chris

On Tue, 13 Jun 2006, Evan Cheng wrote:




Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.157 - 1.158
---
Log message:

Cygwin support: use _alloca to allocate stack if  4k. Patch by Anton 
Korobeynikov.

---
Diffs of the changes:  (+21 -4)

X86RegisterInfo.cpp |   25 +
1 files changed, 21 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.157 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.158
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.157   Tue Jun  6 18:30:24 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Jun 13 00:14:44 2006
@@ -740,7 +740,7 @@
  const Function* Fn = MF.getFunction();
  const X86Subtarget* Subtarget = MF.getTarget().getSubtargetX86Subtarget();
  MachineInstr *MI;
-
+
  // Get the number of bytes to allocate from the FrameInfo
  unsigned NumBytes = MFI-getStackSize();
  if (MFI-hasCalls() || MF.getFrameInfo()-hasVarSizedObjects()) {
@@ -760,9 +760,20 @@
  MFI-setStackSize(NumBytes);

  if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
-unsigned Opc = NumBytes  128 ? X86::SUB32ri8 : X86::SUB32ri;
-MI = BuildMI(Opc, 1, X86::ESP,MachineOperand::UseAndDef).addImm(NumBytes);
-MBB.insert(MBBI, MI);
+if (NumBytes = 4096  Subtarget-TargetType == X86Subtarget::isCygwin) {
+  // Function prologue calls _alloca to probe the stack when allocating
+  // more than 4k bytes in one go. Touching the stack at 4K increments is
+  // necessary to ensure that the guard pages used by the OS virtual memory
+  // manager are allocated in correct sequence.
+  MI = BuildMI(X86::MOV32ri, 2, X86::EAX).addImm(NumBytes);
+  MBB.insert(MBBI, MI);
+  MI = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(_alloca);
+  MBB.insert(MBBI, MI);
+} else {
+  unsigned Opc = NumBytes  128 ? X86::SUB32ri8 : X86::SUB32ri;
+  MI = BuildMI(Opc, 1, 
X86::ESP,MachineOperand::UseAndDef).addImm(NumBytes);
+  MBB.insert(MBBI, MI);
+}
  }

  if (hasFP(MF)) {
@@ -789,6 +800,12 @@
  Subtarget-TargetType == X86Subtarget::isCygwin) {
MI = BuildMI(X86::AND32ri, 2, X86::ESP).addImm(-Align);
MBB.insert(MBBI, MI);
+
+// Probe the stack
+MI = BuildMI(X86::MOV32ri, 2, X86::EAX).addImm(Align);
+MBB.insert(MBBI, MI);
+MI = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(_alloca);
+MBB.insert(MBBI, MI);
  }
}




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Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-06-12 Thread Chris Lattner


On Tue, 13 Jun 2006, Chris Lattner wrote:

Does this fix PR331?


Actually no, I don't think it does.  Dynamic alloca lowering would also 
need to be updated.  That would be a logical next step :)


-Chris


-Chris

On Tue, 13 Jun 2006, Evan Cheng wrote:




Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.157 - 1.158
---
Log message:

Cygwin support: use _alloca to allocate stack if  4k. Patch by Anton 
Korobeynikov.


---
Diffs of the changes:  (+21 -4)

X86RegisterInfo.cpp |   25 +
1 files changed, 21 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.157 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.158
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.157	Tue Jun  6 18:30:24 
2006

+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Jun 13 00:14:44 2006
@@ -740,7 +740,7 @@
  const Function* Fn = MF.getFunction();
  const X86Subtarget* Subtarget = 
MF.getTarget().getSubtargetX86Subtarget();

  MachineInstr *MI;
-
+
  // Get the number of bytes to allocate from the FrameInfo
  unsigned NumBytes = MFI-getStackSize();
  if (MFI-hasCalls() || MF.getFrameInfo()-hasVarSizedObjects()) {
@@ -760,9 +760,20 @@
  MFI-setStackSize(NumBytes);

  if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
-unsigned Opc = NumBytes  128 ? X86::SUB32ri8 : X86::SUB32ri;
-MI = BuildMI(Opc, 1, 
X86::ESP,MachineOperand::UseAndDef).addImm(NumBytes);

-MBB.insert(MBBI, MI);
+if (NumBytes = 4096  Subtarget-TargetType == 
X86Subtarget::isCygwin) {
+  // Function prologue calls _alloca to probe the stack when 
allocating
+  // more than 4k bytes in one go. Touching the stack at 4K increments 
is
+  // necessary to ensure that the guard pages used by the OS virtual 
memory

+  // manager are allocated in correct sequence.
+  MI = BuildMI(X86::MOV32ri, 2, X86::EAX).addImm(NumBytes);
+  MBB.insert(MBBI, MI);
+  MI = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(_alloca);
+  MBB.insert(MBBI, MI);
+} else {
+  unsigned Opc = NumBytes  128 ? X86::SUB32ri8 : X86::SUB32ri;
+  MI = BuildMI(Opc, 1, 
X86::ESP,MachineOperand::UseAndDef).addImm(NumBytes);

+  MBB.insert(MBBI, MI);
+}
  }

  if (hasFP(MF)) {
@@ -789,6 +800,12 @@
  Subtarget-TargetType == X86Subtarget::isCygwin) {
MI = BuildMI(X86::AND32ri, 2, X86::ESP).addImm(-Align);
MBB.insert(MBBI, MI);
+
+// Probe the stack
+MI = BuildMI(X86::MOV32ri, 2, X86::EAX).addImm(Align);
+MBB.insert(MBBI, MI);
+MI = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(_alloca);
+MBB.insert(MBBI, MI);
  }
}




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-Chris




-Chris

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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-05-04 Thread Chris Lattner



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.147 - 1.148
---
Log message:

Move some methods out of MachineInstr into MachineOperand


---
Diffs of the changes:  (+2 -2)

 X86RegisterInfo.cpp |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.147 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.148
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.147   Thu May  4 12:21:20 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu May  4 12:52:23 2006
@@ -665,7 +665,7 @@
 
   // This must be part of a four operand memory reference.  Replace the
   // FrameIndex with base register with EBP.  Add add an offset to the offset.
-  MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
+  MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP);
 
   // Now add the frame object offset to the offset from EBP.
   int Offset = MF.getFrameInfo()-getObjectOffset(FrameIndex) +
@@ -676,7 +676,7 @@
   else
 Offset += 4;  // Skip the saved EBP
 
-  MI.SetMachineOperandConst(i+3, MachineOperand::MO_Immediate, Offset);
+  MI.getOperand(i+3).ChangeToImmediate(Offset);
 }
 
 void



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-04-27 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.144 - 1.145
---
Log message:

Use movaps instead of movapd for spill / restore.


---
Diffs of the changes:  (+2 -2)

 X86RegisterInfo.cpp |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.144 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.145
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.144   Mon Apr 24 00:37:35 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Apr 27 21:23:35 2006
@@ -63,7 +63,7 @@
   } else if (RC == X86::FR64RegClass) {
 Opc = X86::MOVSDmr;
   } else if (RC == X86::VR128RegClass) {
-Opc = X86::MOVAPDmr;
+Opc = X86::MOVAPSmr;
   } else {
 assert(0  Unknown regclass);
 abort();
@@ -89,7 +89,7 @@
   } else if (RC == X86::FR64RegClass) {
 Opc = X86::MOVSDrm;
   } else if (RC == X86::VR128RegClass) {
-Opc = X86::MOVAPDrm;
+Opc = X86::MOVAPSrm;
   } else {
 assert(0  Unknown regclass);
 abort();



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-04-18 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.140 - 1.141
---
Log message:

Encoding bug: CMPPSrmi, CMPPDrmi dropped operand 2 (condtion immediate).


---
Diffs of the changes:  (+2 -2)

 X86RegisterInfo.cpp |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.140 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.141
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.140   Mon Apr 17 13:06:12 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Apr 18 16:31:08 2006
@@ -510,8 +510,8 @@
 case X86::XORPDrr:   return MakeRMInst(X86::XORPDrm, FrameIndex, MI);
 case X86::ANDNPSrr:  return MakeRMInst(X86::ANDNPSrm, FrameIndex, MI);
 case X86::ANDNPDrr:  return MakeRMInst(X86::ANDNPDrm, FrameIndex, MI);
-case X86::CMPPSrr:   return MakeRMInst(X86::CMPPSrm, FrameIndex, MI);
-case X86::CMPPDrr:   return MakeRMInst(X86::CMPPDrm, FrameIndex, MI);
+case X86::CMPPSrri:  return MakeRMIInst(X86::CMPPSrmi, FrameIndex, MI);
+case X86::CMPPDrri:  return MakeRMIInst(X86::CMPPDrmi, FrameIndex, MI);
 case X86::SHUFPSrr:  return MakeRMInst(X86::SHUFPSrm, FrameIndex, MI);
 case X86::SHUFPDrr:  return MakeRMInst(X86::SHUFPDrm, FrameIndex, MI);
 case X86::UNPCKHPSrr:return MakeRMInst(X86::UNPCKHPSrm, FrameIndex, MI);



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-04-18 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.141 - 1.142
---
Log message:

SHUFP{S|D}, PSHUF* encoding bugs. Left out the mask immediate operand.


---
Diffs of the changes:  (+5 -5)

 X86RegisterInfo.cpp |   10 +-
 1 files changed, 5 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.141 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.142
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.141   Tue Apr 18 16:31:08 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Apr 18 16:56:36 2006
@@ -512,8 +512,8 @@
 case X86::ANDNPDrr:  return MakeRMInst(X86::ANDNPDrm, FrameIndex, MI);
 case X86::CMPPSrri:  return MakeRMIInst(X86::CMPPSrmi, FrameIndex, MI);
 case X86::CMPPDrri:  return MakeRMIInst(X86::CMPPDrmi, FrameIndex, MI);
-case X86::SHUFPSrr:  return MakeRMInst(X86::SHUFPSrm, FrameIndex, MI);
-case X86::SHUFPDrr:  return MakeRMInst(X86::SHUFPDrm, FrameIndex, MI);
+case X86::SHUFPSrri: return MakeRMIInst(X86::SHUFPSrmi, FrameIndex, MI);
+case X86::SHUFPDrri: return MakeRMIInst(X86::SHUFPDrmi, FrameIndex, MI);
 case X86::UNPCKHPSrr:return MakeRMInst(X86::UNPCKHPSrm, FrameIndex, MI);
 case X86::UNPCKHPDrr:return MakeRMInst(X86::UNPCKHPDrm, FrameIndex, MI);
 case X86::UNPCKLPSrr:return MakeRMInst(X86::UNPCKLPSrm, FrameIndex, MI);
@@ -561,9 +561,9 @@
 case X86::PACKSSWBrr:return MakeRMInst(X86::PACKSSWBrm, FrameIndex, MI);
 case X86::PACKSSDWrr:return MakeRMInst(X86::PACKSSDWrm, FrameIndex, MI);
 case X86::PACKUSWBrr:return MakeRMInst(X86::PACKUSWBrm, FrameIndex, MI);
-case X86::PSHUFDri:  return MakeRMInst(X86::PSHUFDmi, FrameIndex, MI);
-case X86::PSHUFHWri: return MakeRMInst(X86::PSHUFHWmi, FrameIndex, MI);
-case X86::PSHUFLWri: return MakeRMInst(X86::PSHUFLWmi, FrameIndex, MI);
+case X86::PSHUFDri:  return MakeRMIInst(X86::PSHUFDmi, FrameIndex, MI);
+case X86::PSHUFHWri: return MakeRMIInst(X86::PSHUFHWmi, FrameIndex, MI);
+case X86::PSHUFLWri: return MakeRMIInst(X86::PSHUFLWmi, FrameIndex, MI);
 case X86::PUNPCKLBWrr:return MakeRMInst(X86::PUNPCKLBWrm, FrameIndex, MI);
 case X86::PUNPCKLWDrr:return MakeRMInst(X86::PUNPCKLWDrm, FrameIndex, MI);
 case X86::PUNPCKLDQrr:return MakeRMInst(X86::PUNPCKLDQrm, FrameIndex, MI);



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86InstrSSE.td

2006-04-18 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.142 - 1.143
X86InstrSSE.td updated: 1.104 - 1.105
---
Log message:

- PEXTRW cannot take a memory location as its first source operand.
- PINSRWrmi encoding bug.


---
Diffs of the changes:  (+1 -9)

 X86InstrSSE.td  |7 ---
 X86RegisterInfo.cpp |3 +--
 2 files changed, 1 insertion(+), 9 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.142 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.143
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.142   Tue Apr 18 16:56:36 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Apr 18 16:59:43 2006
@@ -572,8 +572,7 @@
 case X86::PUNPCKHWDrr:return MakeRMInst(X86::PUNPCKHWDrm, FrameIndex, MI);
 case X86::PUNPCKHDQrr:return MakeRMInst(X86::PUNPCKHDQrm, FrameIndex, MI);
 case X86::PUNPCKHQDQrr:return MakeRMInst(X86::PUNPCKHQDQrm, FrameIndex, 
MI);
-case X86::PEXTRWri:   return MakeRMInst(X86::PEXTRWmi, FrameIndex, MI);
-case X86::PINSRWrri:  return MakeRMInst(X86::PINSRWrmi, FrameIndex, MI);
+case X86::PINSRWrri:  return MakeRMIInst(X86::PINSRWrmi, FrameIndex, MI);
 // Alias packed SSE instructions
 case X86::MOVSS2PSrr:return MakeRMInst(X86::MOVSS2PSrm, FrameIndex, MI);
 case X86::MOVSD2PDrr:return MakeRMInst(X86::MOVSD2PDrm, FrameIndex, MI);


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.104 
llvm/lib/Target/X86/X86InstrSSE.td:1.105
--- llvm/lib/Target/X86/X86InstrSSE.td:1.104Tue Apr 18 16:55:35 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td  Tue Apr 18 16:59:43 2006
@@ -2007,13 +2007,6 @@
 pextrw {$src2, $src1, $dst|$dst, $src1, $src2},
 [(set R32:$dst, (X86pextrw (v8i16 VR128:$src1),
  (i32 imm:$src2)))];
-def PEXTRWmi : PDIi80xC5, MRMSrcMem,
-(ops R32:$dst, i128mem:$src1, i32i8imm:$src2),
-pextrw {$src2, $src1, $dst|$dst, $src1, $src2},
-[(set R32:$dst, (X86pextrw
- (bc_v8i16 (loadv2i64 addr:$src1)),
- (i32 imm:$src2)))];
-
 let isTwoAddress = 1 in {
 def PINSRWrri : PDIi80xC4, MRMSrcReg,
  (ops VR128:$dst, VR128:$src1, R32:$src2, i32i8imm:$src3),



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-04-17 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.139 - 1.140
---
Log message:

Incorrect foldMemoryOperand entries

---
Diffs of the changes:  (+6 -12)

 X86RegisterInfo.cpp |   18 ++
 1 files changed, 6 insertions(+), 12 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.139 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.140
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.139   Sun Apr 16 01:58:19 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Mon Apr 17 13:06:12 2006
@@ -316,12 +316,6 @@
 case X86::SETGEr:return MakeMInst( X86::SETGEm,  FrameIndex, MI);
 case X86::SETLEr:return MakeMInst( X86::SETLEm,  FrameIndex, MI);
 case X86::SETGr: return MakeMInst( X86::SETGm,   FrameIndex, MI);
-case X86::TEST8rr:   return MakeMRInst(X86::TEST8mr ,FrameIndex, MI);
-case X86::TEST16rr:  return MakeMRInst(X86::TEST16mr,FrameIndex, MI);
-case X86::TEST32rr:  return MakeMRInst(X86::TEST32mr,FrameIndex, MI);
-case X86::CMP8rr:return MakeMRInst(X86::CMP8mr , FrameIndex, MI);
-case X86::CMP16rr:   return MakeMRInst(X86::CMP16mr, FrameIndex, MI);
-case X86::CMP32rr:   return MakeMRInst(X86::CMP32mr, FrameIndex, MI);
 // Alias instructions
 case X86::MOV8r0:return MakeM0Inst(X86::MOV8mi, FrameIndex, MI);
 case X86::MOV16r0:   return MakeM0Inst(X86::MOV16mi, FrameIndex, MI);
@@ -394,18 +388,18 @@
 case X86::XOR8rr:return MakeRMInst(X86::XOR8rm , FrameIndex, MI);
 case X86::XOR16rr:   return MakeRMInst(X86::XOR16rm, FrameIndex, MI);
 case X86::XOR32rr:   return MakeRMInst(X86::XOR32rm, FrameIndex, MI);
-case X86::TEST8rr:   return MakeRMInst(X86::TEST8rm ,FrameIndex, MI);
-case X86::TEST16rr:  return MakeRMInst(X86::TEST16rm,FrameIndex, MI);
-case X86::TEST32rr:  return MakeRMInst(X86::TEST32rm,FrameIndex, MI);
-case X86::TEST8ri:   return MakeMIInst(X86::TEST8mi ,FrameIndex, MI);
-case X86::TEST16ri:  return MakeMIInst(X86::TEST16mi,FrameIndex, MI);
-case X86::TEST32ri:  return MakeMIInst(X86::TEST32mi,FrameIndex, MI);
 case X86::IMUL16rr:  return MakeRMInst(X86::IMUL16rm,FrameIndex, MI);
 case X86::IMUL32rr:  return MakeRMInst(X86::IMUL32rm,FrameIndex, MI);
 case X86::IMUL16rri: return MakeRMIInst(X86::IMUL16rmi, FrameIndex, MI);
 case X86::IMUL32rri: return MakeRMIInst(X86::IMUL32rmi, FrameIndex, MI);
 case X86::IMUL16rri8:return MakeRMIInst(X86::IMUL16rmi8, FrameIndex, MI);
 case X86::IMUL32rri8:return MakeRMIInst(X86::IMUL32rmi8, FrameIndex, MI);
+case X86::TEST8rr:   return MakeRMInst(X86::TEST8rm ,FrameIndex, MI);
+case X86::TEST16rr:  return MakeRMInst(X86::TEST16rm,FrameIndex, MI);
+case X86::TEST32rr:  return MakeRMInst(X86::TEST32rm,FrameIndex, MI);
+case X86::TEST8ri:   return MakeMIInst(X86::TEST8mi ,FrameIndex, MI);
+case X86::TEST16ri:  return MakeMIInst(X86::TEST16mi,FrameIndex, MI);
+case X86::TEST32ri:  return MakeMIInst(X86::TEST32mi,FrameIndex, MI);
 case X86::CMP8rr:return MakeRMInst(X86::CMP8rm , FrameIndex, MI);
 case X86::CMP16rr:   return MakeRMInst(X86::CMP16rm, FrameIndex, MI);
 case X86::CMP32rr:   return MakeRMInst(X86::CMP32rm, FrameIndex, MI);



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-04-14 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.136 - 1.137
---
Log message:

We were not adjusting the frame size to ensure proper alignment when alloca /
vla are present in the function. This causes a crash when a leaf function
allocates space on the stack used to store / load with 128-bit SSE
instructions.


---
Diffs of the changes:  (+23 -30)

 X86RegisterInfo.cpp |   53 ++--
 1 files changed, 23 insertions(+), 30 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.136 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.137
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.136   Mon Apr 10 02:21:31 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Fri Apr 14 02:26:43 2006
@@ -573,17 +573,34 @@
 
   // Get the number of bytes to allocate from the FrameInfo
   unsigned NumBytes = MFI-getStackSize();
+  if (MFI-hasCalls() || MF.getFrameInfo()-hasVarSizedObjects()) {
+// When we have no frame pointer, we reserve argument space for call sites
+// in the function immediately on entry to the current function.  This
+// eliminates the need for add/sub ESP brackets around call sites.
+//
+if (!hasFP(MF))
+  NumBytes += MFI-getMaxCallFrameSize();
+
+// Round the size to a multiple of the alignment (don't forget the 4 byte
+// offset though).
+unsigned Align = MF.getTarget().getFrameInfo()-getStackAlignment();
+NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
+  }
+
+  // Update frame info to pretend that this is part of the stack...
+  MFI-setStackSize(NumBytes);
+
+  if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
+unsigned Opc = NumBytes  128 ? X86::SUB32ri8 : X86::SUB32ri;
+MI = BuildMI(Opc, 1, X86::ESP,MachineOperand::UseAndDef).addImm(NumBytes);
+MBB.insert(MBBI, MI);
+  }
+
   if (hasFP(MF)) {
 // Get the offset of the stack slot for the EBP register... which is
 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
 int EBPOffset = MFI-getObjectOffset(MFI-getObjectIndexBegin())+4;
 
-if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
-  unsigned Opc = NumBytes  128 ? X86::SUB32ri8 : X86::SUB32ri;
-  MI = BuildMI(Opc, 1, 
X86::ESP,MachineOperand::UseAndDef).addImm(NumBytes);
-  MBB.insert(MBBI, MI);
-}
-
 // Save EBP into the appropriate stack slot...
 MI = addRegOffset(BuildMI(X86::MOV32mr, 5),// mov [ESP-offset], EBP
   X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
@@ -596,30 +613,6 @@
   MI = addRegOffset(BuildMI(X86::LEA32r, 5, X86::EBP), 
X86::ESP,NumBytes-4);
 
 MBB.insert(MBBI, MI);
-
-  } else {
-if (MFI-hasCalls()) {
-  // When we have no frame pointer, we reserve argument space for call 
sites
-  // in the function immediately on entry to the current function.  This
-  // eliminates the need for add/sub ESP brackets around call sites.
-  //
-  NumBytes += MFI-getMaxCallFrameSize();
-
-  // Round the size to a multiple of the alignment (don't forget the 4 byte
-  // offset though).
-  unsigned Align = MF.getTarget().getFrameInfo()-getStackAlignment();
-  NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
-}
-
-// Update frame info to pretend that this is part of the stack...
-MFI-setStackSize(NumBytes);
-
-if (NumBytes) {
-  // adjust stack pointer: ESP -= numbytes
-  unsigned Opc = NumBytes  128 ? X86::SUB32ri8 : X86::SUB32ri;
-  MI= BuildMI(Opc, 1, X86::ESP, 
MachineOperand::UseAndDef).addImm(NumBytes);
-  MBB.insert(MBBI, MI);
-}
   }
 }
 



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-04-10 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.135 - 1.136
---
Log message:

Use movaps to do VR128 reg-to-reg copies for now. It's shorter and available 
for SSE1.

---
Diffs of the changes:  (+1 -1)

 X86RegisterInfo.cpp |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.135 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.136
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.135   Fri Apr  7 11:34:46 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Mon Apr 10 02:21:31 2006
@@ -115,7 +115,7 @@
   } else if (RC == X86::FR64RegClass) {
 Opc = X86::FsMOVAPDrr;
   } else if (RC == X86::VR128RegClass) {
-Opc = X86::MOVAPDrr;
+Opc = X86::MOVAPSrr;
   } else {
 assert(0  Unknown regclass);
 abort();



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86RegisterInfo.h

2006-03-28 Thread Jim Laskey



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.132 - 1.133
X86RegisterInfo.h updated: 1.35 - 1.36
---
Log message:

Expose base register for DwarfWriter.  Refactor code accordingly.


---
Diffs of the changes:  (+4 -11)

 X86RegisterInfo.cpp |   11 ++-
 X86RegisterInfo.h   |4 ++--
 2 files changed, 4 insertions(+), 11 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.132 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.133
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.132   Mon Mar 27 14:18:45 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Mar 28 07:48:33 2006
@@ -686,15 +686,8 @@
   }
 }
 
-void X86RegisterInfo::getLocation(MachineFunction MF, unsigned Index,
-  MachineLocation ML) const {
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  bool FP = hasFP(MF);
-  
-  // FIXME - Needs to handle register variables.
-  // FIXME - Hardcoding gcc numbering.
-  ML.set(getDwarfRegNum(FP ? X86::EBP : X86::ESP),
- MFI-getObjectOffset(Index) + MFI-getStackSize());
+unsigned X86RegisterInfo::getFrameRegister(MachineFunction MF) const {
+  return getDwarfRegNum(hasFP(MF) ? X86::EBP : X86::ESP);
 }
 
 #include X86GenRegisterInfo.inc


Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.35 
llvm/lib/Target/X86/X86RegisterInfo.h:1.36
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.35  Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.h   Tue Mar 28 07:48:33 2006
@@ -63,8 +63,8 @@
   void emitPrologue(MachineFunction MF) const;
   void emitEpilogue(MachineFunction MF, MachineBasicBlock MBB) const;
 
-  void getLocation(MachineFunction MF, unsigned Index,
-   MachineLocation ML) const;
+  // Debug information queries.
+  unsigned getFrameRegister(MachineFunction MF) const;
 };
 
 } // End llvm namespace



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-03-27 Thread Jim Laskey



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.131 - 1.132
---
Log message:

Translate llvm target registers to dwarf register numbers properly.


---
Diffs of the changes:  (+1 -1)

 X86RegisterInfo.cpp |2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.131 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.132
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.131   Thu Mar 23 12:12:57 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Mon Mar 27 14:18:45 2006
@@ -693,7 +693,7 @@
   
   // FIXME - Needs to handle register variables.
   // FIXME - Hardcoding gcc numbering.
-  ML.set(FP ? 6 : 7,
+  ML.set(getDwarfRegNum(FP ? X86::EBP : X86::ESP),
  MFI-getObjectOffset(Index) + MFI-getStackSize());
 }
 



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86RegisterInfo.h

2006-03-23 Thread Jim Laskey



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.130 - 1.131
X86RegisterInfo.h updated: 1.34 - 1.35
---
Log message:

Add support to locate local variables in frames (early version.)


---
Diffs of the changes:  (+15 -0)

 X86RegisterInfo.cpp |   12 
 X86RegisterInfo.h   |3 +++
 2 files changed, 15 insertions(+)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.130 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.131
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.130   Fri Mar 17 19:23:20 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Mar 23 12:12:57 2006
@@ -21,6 +21,7 @@
 #include llvm/CodeGen/MachineInstrBuilder.h
 #include llvm/CodeGen/MachineFunction.h
 #include llvm/CodeGen/MachineFrameInfo.h
+#include llvm/CodeGen/MachineLocation.h
 #include llvm/Target/TargetFrameInfo.h
 #include llvm/Target/TargetMachine.h
 #include llvm/Target/TargetOptions.h
@@ -685,5 +686,16 @@
   }
 }
 
+void X86RegisterInfo::getLocation(MachineFunction MF, unsigned Index,
+  MachineLocation ML) const {
+  MachineFrameInfo *MFI = MF.getFrameInfo();
+  bool FP = hasFP(MF);
+  
+  // FIXME - Needs to handle register variables.
+  // FIXME - Hardcoding gcc numbering.
+  ML.set(FP ? 6 : 7,
+ MFI-getObjectOffset(Index) + MFI-getStackSize());
+}
+
 #include X86GenRegisterInfo.inc
 


Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.34 
llvm/lib/Target/X86/X86RegisterInfo.h:1.35
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.34  Thu Feb  2 14:12:32 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.h   Thu Mar 23 12:12:57 2006
@@ -62,6 +62,9 @@
 
   void emitPrologue(MachineFunction MF) const;
   void emitEpilogue(MachineFunction MF, MachineBasicBlock MBB) const;
+
+  void getLocation(MachineFunction MF, unsigned Index,
+   MachineLocation ML) const;
 };
 
 } // End llvm namespace



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-03-16 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.127 - 1.128
---
Log message:

Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g.
ADD32ri8.


---
Diffs of the changes:  (+18 -6)

 X86RegisterInfo.cpp |   24 ++--
 1 files changed, 18 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.127 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.128
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.127   Fri Feb 24 19:37:02 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Mar 16 20:25:01 2006
@@ -221,39 +221,49 @@
 case X86::ADD8rr:return MakeMRInst(X86::ADD8mr , FrameIndex, MI);
 case X86::ADD16rr:   return MakeMRInst(X86::ADD16mr, FrameIndex, MI);
 case X86::ADD32rr:   return MakeMRInst(X86::ADD32mr, FrameIndex, MI);
-case X86::ADC32rr:   return MakeMRInst(X86::ADC32mr, FrameIndex, MI);
-case X86::ADC32ri:   return MakeMIInst(X86::ADC32mi, FrameIndex, MI);
 case X86::ADD8ri:return MakeMIInst(X86::ADD8mi , FrameIndex, MI);
 case X86::ADD16ri:   return MakeMIInst(X86::ADD16mi, FrameIndex, MI);
 case X86::ADD32ri:   return MakeMIInst(X86::ADD32mi, FrameIndex, MI);
+case X86::ADD16ri8:  return MakeMIInst(X86::ADD16mi8,FrameIndex, MI);
+case X86::ADD32ri8:  return MakeMIInst(X86::ADD32mi8,FrameIndex, MI);
+case X86::ADC32rr:   return MakeMRInst(X86::ADC32mr, FrameIndex, MI);
+case X86::ADC32ri:   return MakeMIInst(X86::ADC32mi, FrameIndex, MI);
+case X86::ADC32ri8:  return MakeMIInst(X86::ADC32mi8,FrameIndex, MI);
 case X86::SUB8rr:return MakeMRInst(X86::SUB8mr , FrameIndex, MI);
 case X86::SUB16rr:   return MakeMRInst(X86::SUB16mr, FrameIndex, MI);
 case X86::SUB32rr:   return MakeMRInst(X86::SUB32mr, FrameIndex, MI);
-case X86::SBB32rr:   return MakeMRInst(X86::SBB32mr, FrameIndex, MI);
-case X86::SBB8ri:return MakeMIInst(X86::SBB8mi,  FrameIndex, MI);
-case X86::SBB16ri:   return MakeMIInst(X86::SBB16mi, FrameIndex, MI);
-case X86::SBB32ri:   return MakeMIInst(X86::SBB32mi, FrameIndex, MI);
 case X86::SUB8ri:return MakeMIInst(X86::SUB8mi , FrameIndex, MI);
 case X86::SUB16ri:   return MakeMIInst(X86::SUB16mi, FrameIndex, MI);
 case X86::SUB32ri:   return MakeMIInst(X86::SUB32mi, FrameIndex, MI);
+case X86::SUB16ri8:  return MakeMIInst(X86::SUB16mi8,FrameIndex, MI);
+case X86::SUB32ri8:  return MakeMIInst(X86::SUB32mi8,FrameIndex, MI);
+case X86::SBB32rr:   return MakeMRInst(X86::SBB32mr, FrameIndex, MI);
+case X86::SBB32ri:   return MakeMIInst(X86::SBB32mi, FrameIndex, MI);
+case X86::SBB32ri8:  return MakeMIInst(X86::SBB32mi8,FrameIndex, MI);
 case X86::AND8rr:return MakeMRInst(X86::AND8mr , FrameIndex, MI);
 case X86::AND16rr:   return MakeMRInst(X86::AND16mr, FrameIndex, MI);
 case X86::AND32rr:   return MakeMRInst(X86::AND32mr, FrameIndex, MI);
 case X86::AND8ri:return MakeMIInst(X86::AND8mi , FrameIndex, MI);
 case X86::AND16ri:   return MakeMIInst(X86::AND16mi, FrameIndex, MI);
 case X86::AND32ri:   return MakeMIInst(X86::AND32mi, FrameIndex, MI);
+case X86::AND16ri8:  return MakeMIInst(X86::AND16mi8,FrameIndex, MI);
+case X86::AND32ri8:  return MakeMIInst(X86::AND32mi8,FrameIndex, MI);
 case X86::OR8rr: return MakeMRInst(X86::OR8mr ,  FrameIndex, MI);
 case X86::OR16rr:return MakeMRInst(X86::OR16mr,  FrameIndex, MI);
 case X86::OR32rr:return MakeMRInst(X86::OR32mr,  FrameIndex, MI);
 case X86::OR8ri: return MakeMIInst(X86::OR8mi ,  FrameIndex, MI);
 case X86::OR16ri:return MakeMIInst(X86::OR16mi,  FrameIndex, MI);
 case X86::OR32ri:return MakeMIInst(X86::OR32mi,  FrameIndex, MI);
+case X86::OR16ri8:   return MakeMIInst(X86::OR16mi8, FrameIndex, MI);
+case X86::OR32ri8:   return MakeMIInst(X86::OR32mi8, FrameIndex, MI);
 case X86::XOR8rr:return MakeMRInst(X86::XOR8mr , FrameIndex, MI);
 case X86::XOR16rr:   return MakeMRInst(X86::XOR16mr, FrameIndex, MI);
 case X86::XOR32rr:   return MakeMRInst(X86::XOR32mr, FrameIndex, MI);
 case X86::XOR8ri:return MakeMIInst(X86::XOR8mi , FrameIndex, MI);
 case X86::XOR16ri:   return MakeMIInst(X86::XOR16mi, FrameIndex, MI);
 case X86::XOR32ri:   return MakeMIInst(X86::XOR32mi, FrameIndex, MI);
+case X86::XOR16ri8:  return MakeMIInst(X86::XOR16mi8,FrameIndex, MI);
+case X86::XOR32ri8:  return MakeMIInst(X86::XOR32mi8,FrameIndex, MI);
 case X86::SHL8rCL:   return MakeMInst( X86::SHL8mCL ,FrameIndex, MI);
 case X86::SHL16rCL:  return MakeMInst( X86::SHL16mCL,FrameIndex, MI);
 case X86::SHL32rCL:  return MakeMInst( X86::SHL32mCL,FrameIndex, MI);
@@ -392,6 +402,8 @@
 case X86::IMUL32rr:  return MakeRMInst(X86::IMUL32rm,FrameIndex, MI);
 case X86::IMUL16rri: return MakeRMIInst(X86::IMUL16rmi, FrameIndex, MI);
 case X86::IMUL32rri: return

[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-03-16 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.128 - 1.129
---
Log message:

Also fold MOV8r0, MOV16r0, MOV32r0  + store to MOV8mi, MOV16mi, and MOV32mi.


---
Diffs of the changes:  (+9 -0)

 X86RegisterInfo.cpp |9 +
 1 files changed, 9 insertions(+)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.128 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.129
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.128   Thu Mar 16 20:25:01 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Mar 16 20:36:22 2006
@@ -160,6 +160,11 @@
   return 0;
 }
 
+static MachineInstr *MakeM0Inst(unsigned Opcode, unsigned FrameIndex,
+MachineInstr *MI) {
+  return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addZImm(0);
+}
+
 static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
 MachineInstr *MI) {
   const MachineOperand op = MI-getOperand(0);
@@ -328,6 +333,10 @@
 case X86::CMP8ri:return MakeMIInst(X86::CMP8mi , FrameIndex, MI);
 case X86::CMP16ri:   return MakeMIInst(X86::CMP16mi, FrameIndex, MI);
 case X86::CMP32ri:   return MakeMIInst(X86::CMP32mi, FrameIndex, MI);
+// Alias instructions
+case X86::MOV8r0:return MakeM0Inst(X86::MOV8mi, FrameIndex, MI);
+case X86::MOV16r0:   return MakeM0Inst(X86::MOV16mi, FrameIndex, MI);
+case X86::MOV32r0:   return MakeM0Inst(X86::MOV32mi, FrameIndex, MI);
 // Alias scalar SSE instructions
 case X86::FsMOVAPSrr: return MakeMRInst(X86::MOVSSmr, FrameIndex, MI);
 case X86::FsMOVAPDrr: return MakeMRInst(X86::MOVSDmr, FrameIndex, MI);



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-02-24 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.126 - 1.127
---
Log message:

Fix an obvious bug exposed when we are doing
ADD X, 4
==
MOV32ri $X+4, ...


---
Diffs of the changes:  (+2 -1)

 X86RegisterInfo.cpp |3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.126 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.127
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.126   Mon Feb 20 19:38:21 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Fri Feb 24 19:37:02 2006
@@ -154,7 +154,8 @@
   .addZImm(MI-getOperand(1).getImmedValue());
   else if (MI-getOperand(1).isGlobalAddress())
 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
-  .addGlobalAddress(MI-getOperand(1).getGlobal());
+  .addGlobalAddress(MI-getOperand(1).getGlobal(),
+false, MI-getOperand(1).getOffset());
   assert(0  Unknown operand for MakeMI!);
   return 0;
 }



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86RegisterInfo.td

2006-02-20 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.125 - 1.126
X86RegisterInfo.td updated: 1.29 - 1.30
---
Log message:

Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64.
Added generic vector types: VR64 and VR128.


---
Diffs of the changes:  (+27 -9)

 X86RegisterInfo.cpp |8 ++--
 X86RegisterInfo.td  |   28 +---
 2 files changed, 27 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.125 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.126
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.125   Mon Feb 20 16:34:53 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Mon Feb 20 19:38:21 2006
@@ -113,10 +113,14 @@
 Opc = X86::MOV16rr;
   } else if (RC == X86::RFPRegClass || RC == X86::RSTRegClass) {
 Opc = X86::FpMOV;
-  } else if (RC == X86::FR32RegClass || RC == X86::V4F32RegClass) {
+  } else if (RC == X86::FR32RegClass) {
 Opc = X86::FsMOVAPSrr;
-  } else if (RC == X86::FR64RegClass || RC == X86::V2F64RegClass) {
+  } else if (RC == X86::FR64RegClass) {
 Opc = X86::FsMOVAPDrr;
+  } else if (RC == X86::V4F32RegClass) {
+Opc = X86::MOVAPSrr;
+  } else if (RC == X86::V2F64RegClass) {
+Opc = X86::MOVAPDrr;
   } else {
 assert(0  Unknown regclass);
 abort();


Index: llvm/lib/Target/X86/X86RegisterInfo.td
diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.29 
llvm/lib/Target/X86/X86RegisterInfo.td:1.30
--- llvm/lib/Target/X86/X86RegisterInfo.td:1.29 Mon Feb 20 16:34:53 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.td  Mon Feb 20 19:38:21 2006
@@ -140,13 +140,22 @@
 }
 
 // Vector integer registers: V8I8, the 8 x i8 class, V4I16, the 4 x i16 class,
-// and V2I32, the 2 x i32 class.
-def V8I8  : RegisterClassX86, [v8i8],  64, [MM0, MM1, MM2, MM3, MM4, MM5,
-  MM6, MM7];
-def V4I16 : RegisterClassX86, [v4i16], 64, [MM0, MM1, MM2, MM3, MM4, MM5,
-  MM6, MM7];
-def V2I32 : RegisterClassX86, [v2i32], 64, [MM0, MM1, MM2, MM3, MM4, MM5,
-  MM6, MM7];
+// V2I32, the 2 x i32 class, V16I8, the 16 x i8 class, V8I16, the 8 x i16 
class,
+// V4I32, the 4 x i32 class, and V2I64, the 2 x i64 class.
+def V8I8  : RegisterClassX86, [v8i8],  64,
+  [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7];
+def V4I16 : RegisterClassX86, [v4i16], 64,
+  [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7];
+def V2I32 : RegisterClassX86, [v2i32], 64,
+  [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7];
+def V16I8 : RegisterClassX86, [v16i8], 128,
+  [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7];
+def V8I16 : RegisterClassX86, [v8i16], 128,
+  [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7];
+def V4I32 : RegisterClassX86, [v4i32], 128,
+  [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7];
+def V2I64 : RegisterClassX86, [v2i64], 128,
+  [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7];
 
 // Vector floating point registers: V4F4, the 4 x f32 class, and V2F8,
 // the 2 x f64 class.
@@ -155,3 +164,8 @@
 def V2F64 : RegisterClassX86, [v2f64], 128,
  [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7];
 
+// Generic vector registers: VR64 and VR128.
+def VR64  : RegisterClassX86, [v8i8, v4i16, v2i32], 64,
+  [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7];
+def VR128 : RegisterClassX86, [v16i8, v8i16, v4i32, v2i64, v4f32, 
v2f64],128,
+ [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7];



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-02-16 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.122 - 1.123
---
Log message:

Use movaps / movapd to spill / restore V4F4 / V2F8 registers.


---
Diffs of the changes:  (+12 -4)

 X86RegisterInfo.cpp |   16 
 1 files changed, 12 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.122 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.123
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.122   Wed Feb 15 19:50:02 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Feb 16 15:20:26 2006
@@ -57,10 +57,14 @@
 Opc = X86::MOV16mr;
   } else if (RC == X86::RFPRegClass || RC == X86::RSTRegClass) {
 Opc = X86::FpST64m;
-  } else if (RC == X86::FR32RegClass || RC == X86::V4F4RegClass) {
+  } else if (RC == X86::FR32RegClass) {
 Opc = X86::MOVSSmr;
-  } else if (RC == X86::FR64RegClass || RC == X86::V2F8RegClass) {
+  } else if (RC == X86::FR64RegClass) {
 Opc = X86::MOVSDmr;
+  } else if (RC == X86::V4F4RegClass) {
+Opc = X86::MOVAPSmr;
+  } else if (RC == X86::V2F8RegClass) {
+Opc = X86::MOVAPDmr;
   } else {
 assert(0  Unknown regclass);
 abort();
@@ -81,10 +85,14 @@
 Opc = X86::MOV16rm;
   } else if (RC == X86::RFPRegClass || RC == X86::RSTRegClass) {
 Opc = X86::FpLD64m;
-  } else if (RC == X86::FR32RegClass || RC == X86::V4F4RegClass) {
+  } else if (RC == X86::FR32RegClass) {
 Opc = X86::MOVSSrm;
-  } else if (RC == X86::FR64RegClass || RC == X86::V2F8RegClass) {
+  } else if (RC == X86::FR64RegClass) {
 Opc = X86::MOVSDrm;
+  } else if (RC == X86::V4F4RegClass) {
+Opc = X86::MOVAPSrm;
+  } else if (RC == X86::V2F8RegClass) {
+Opc = X86::MOVAPDrm;
   } else {
 assert(0  Unknown regclass);
 abort();



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-02-15 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.121 - 1.122
---
Log message:

Use movaps / movapd (instead of movss / movsd) to do FR32 / FR64 reg to reg
transfer.

According to the Intel P4 Optimization Manual:

Moves that write a portion of a register can introduce unwanted 
dependences. The movsd reg, reg instruction writes only the bottom 
64 bits of a register, not to all 128 bits. This introduces a dependence on 
the preceding instruction that produces the upper 64 bits (even if those 
bits are not longer wanted). The dependence inhibits register renaming, 
and thereby reduces parallelism. 

Not to mention movaps is shorter than movss.


---
Diffs of the changes:  (+2 -2)

 X86RegisterInfo.cpp |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.121 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.122
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.121   Fri Feb  3 12:20:04 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed Feb 15 19:50:02 2006
@@ -106,9 +106,9 @@
   } else if (RC == X86::RFPRegClass || RC == X86::RSTRegClass) {
 Opc = X86::FpMOV;
   } else if (RC == X86::FR32RegClass || RC == X86::V4F4RegClass) {
-Opc = X86::MOVSSrr;
+Opc = X86::MOVAPSrr;
   } else if (RC == X86::FR64RegClass || RC == X86::V2F8RegClass) {
-Opc = X86::MOVSDrr;
+Opc = X86::MOVAPDrr;
   } else {
 assert(0  Unknown regclass);
 abort();



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[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp

2006-02-01 Thread Evan Cheng



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.117 - 1.118
---
Log message:

Added SSE entries to foldMemoryOperand().


---
Diffs of the changes:  (+49 -1)

 X86RegisterInfo.cpp |   50 +-
 1 files changed, 49 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.117 
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.118
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.117   Mon Jan  9 12:33:28 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed Feb  1 17:02:25 2006
@@ -328,6 +328,16 @@
 case X86::CMP8ri:return MakeMIInst(X86::CMP8mi , FrameIndex, MI);
 case X86::CMP16ri:   return MakeMIInst(X86::CMP16mi, FrameIndex, MI);
 case X86::CMP32ri:   return MakeMIInst(X86::CMP32mi, FrameIndex, MI);
+// Scalar SSE instructions
+case X86::MOVSSrr:   return MakeMRInst(X86::MOVSSmr, FrameIndex, MI);
+case X86::MOVSDrr:   return MakeMRInst(X86::MOVSDmr, FrameIndex, MI);
+#if 0
+// Packed SSE instructions
+// FIXME: Can't use these until we are spilling XMM registers to
+// 128-bit locations.
+case X86::MOVAPSrr:  return MakeMRInst(X86::MOVAPSmr, FrameIndex, MI);
+case X86::MOVAPDrr:  return MakeMRInst(X86::MOVAPDmr, FrameIndex, MI);
+#endif
 }
   } else if (i == 1) {
 switch(MI-getOpcode()) {
@@ -396,8 +406,46 @@
 case X86::MOVSX32rr8:return MakeRMInst(X86::MOVSX32rm8, FrameIndex, MI);
 case X86::MOVSX32rr16:return MakeRMInst(X86::MOVSX32rm16, FrameIndex, MI);
 case X86::MOVZX16rr8:return MakeRMInst(X86::MOVZX16rm8 , FrameIndex, MI);
-case X86::MOVZX32rr8:  return MakeRMInst(X86::MOVZX32rm8, FrameIndex, MI);
+case X86::MOVZX32rr8:return MakeRMInst(X86::MOVZX32rm8, FrameIndex, MI);
 case X86::MOVZX32rr16:return MakeRMInst(X86::MOVZX32rm16, FrameIndex, MI);
+// Scalar SSE instructions
+case X86::MOVSSrr:   return MakeRMInst(X86::MOVSSrm, FrameIndex, MI);
+case X86::MOVSDrr:   return MakeRMInst(X86::MOVSDrm, FrameIndex, MI);
+case X86::CVTTSS2SIrr:return MakeRMInst(X86::CVTTSS2SIrm, FrameIndex, MI);
+case X86::CVTTSD2SIrr:return MakeRMInst(X86::CVTTSD2SIrm, FrameIndex, MI);
+case X86::CVTSS2SDrr:return MakeRMInst(X86::CVTSS2SDrm, FrameIndex, MI);
+case X86::CVTSD2SSrr:return MakeRMInst(X86::CVTSD2SSrm, FrameIndex, MI);
+case X86::CVTSI2SSrr:return MakeRMInst(X86::CVTSI2SSrm, FrameIndex, MI);
+case X86::CVTSI2SDrr:return MakeRMInst(X86::CVTSI2SDrm, FrameIndex, MI);
+case X86::SQRTSSrr:  return MakeRMInst(X86::SQRTSSrm, FrameIndex, MI);
+case X86::SQRTSDrr:  return MakeRMInst(X86::SQRTSDrm, FrameIndex, MI);
+case X86::UCOMISSrr: return MakeRMInst(X86::UCOMISSrm, FrameIndex, MI);
+case X86::UCOMISDrr: return MakeRMInst(X86::UCOMISDrm, FrameIndex, MI);
+case X86::ADDSSrr:   return MakeRMInst(X86::ADDSSrm, FrameIndex, MI);
+case X86::ADDSDrr:   return MakeRMInst(X86::ADDSDrm, FrameIndex, MI);
+case X86::MULSSrr:   return MakeRMInst(X86::MULSSrm, FrameIndex, MI);
+case X86::MULSDrr:   return MakeRMInst(X86::MULSDrm, FrameIndex, MI);
+case X86::DIVSSrr:   return MakeRMInst(X86::DIVSSrm, FrameIndex, MI);
+case X86::DIVSDrr:   return MakeRMInst(X86::DIVSDrm, FrameIndex, MI);
+case X86::SUBSSrr:   return MakeRMInst(X86::SUBSSrm, FrameIndex, MI);
+case X86::SUBSDrr:   return MakeRMInst(X86::SUBSDrm, FrameIndex, MI);
+case X86::CMPSSrr:   return MakeRMInst(X86::CMPSSrm, FrameIndex, MI);
+case X86::CMPSDrr:   return MakeRMInst(X86::CMPSDrm, FrameIndex, MI);
+#if 0
+// Packed SSE instructions
+// FIXME: Can't use these until we are spilling XMM registers to
+// 128-bit locations.
+case X86::ANDPSrr:   return MakeRMInst(X86::ANDPSrm, FrameIndex, MI);
+case X86::ANDPDrr:   return MakeRMInst(X86::ANDPDrm, FrameIndex, MI);
+case X86::ORPSrr:return MakeRMInst(X86::ORPSrm, FrameIndex, MI);
+case X86::ORPDrr:return MakeRMInst(X86::ORPDrm, FrameIndex, MI);
+case X86::XORPSrr:   return MakeRMInst(X86::XORPSrm, FrameIndex, MI);
+case X86::XORPDrr:   return MakeRMInst(X86::XORPDrm, FrameIndex, MI);
+case X86::ANDNPSrr:  return MakeRMInst(X86::ANDNPSrm, FrameIndex, MI);
+case X86::ANDNPDrr:  return MakeRMInst(X86::ANDNPDrm, FrameIndex, MI);
+case X86::MOVAPSrr:  return MakeRMInst(X86::MOVAPSrm, FrameIndex, MI);
+case X86::MOVAPDrr:  return MakeRMInst(X86::MOVAPDrm, FrameIndex, MI);
+#endif
 }
   }
   if (PrintFailedFusing)



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