Re: [lng-odp] [PATCH CATERPILLAR v3] Caterpillar mdev cxgb4
Bill Fischofer(Bill-Fischofer-Linaro) replied on github web page:
platform/linux-generic/pktio/mdev/cxgb4.c
@@ -0,0 +1,887 @@
+/*Copyright (c) 2018, Linaro Limited
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "config.h"
+
+#ifdef ODP_MDEV
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#define MODULE_NAME "cxgb4"
+
+#define CXGB4_TX_BUF_SIZE 2048U
+
+#define CXGB4_TX_INLINE_MAX (256 - sizeof(cxgb4_fw_eth_tx_pkt_wr_t) \
+- sizeof(cxgb4_cpl_tx_pkt_core_t))
+
+/* RX queue definitions */
+#define CXGB4_RX_QUEUE_NUM_MAX 32
+
+/** RX descriptor */
+typedef struct {
+ uint32_t padding[12];
+
+ odp_u32be_t hdrbuflen_pidx;
+#define RX_DESC_NEW_BUF_FLAG (1U << 31)
+ odp_u32be_t pldbuflen_qid;
+ union {
+#define RX_DESC_GEN_SHIFT 7
+#define RX_DESC_GEN_MASK 0x1
+#define RX_DESC_TYPE_SHIFT 4
+#define RX_DESC_TYPE_MASK 0x3
+#define RX_DESC_TYPE_FLBUF_X 0
+#define RX_DESC_TYPE_CPL_X 1
+#define RX_DESC_TYPE_INTR_X2
+ uint8_t type_gen;
+#define RX_DESC_TIMESTAMP_MASK 0xfffULL
+ odp_u64be_t last_flit;
+ };
+} cxgb4_rx_desc_t;
+
+#define RX_DESC_TO_GEN(rxd) \
+ (((rxd)->type_gen >> RX_DESC_GEN_SHIFT) & RX_DESC_GEN_MASK)
+#define RX_DESC_TO_TYPE(rxd) \
+ (((rxd)->type_gen >> RX_DESC_TYPE_SHIFT) & RX_DESC_TYPE_MASK)
+
+/** RX queue data */
+typedef struct ODP_ALIGNED_CACHE {
+ cxgb4_rx_desc_t *rx_descs; /**< RX queue base */
+
+ odp_u32le_t *doorbell_fl; /**< Free list refill doorbell */
+ odp_u32le_t *doorbell_desc; /**< Rx descriptor free doorbell */
+ uint32_t doorbell_fl_key; /**< 'Key' to the doorbell */
+ uint32_t doorbell_desc_key; /**< 'Key' to the doorbell */
+
+ uint16_t rx_queue_len; /**< Number of RX desc entries */
+ uint16_t rx_next; /**< Next RX desc to handle */
+
+ uint32_t gen:1; /**< RX queue generation */
+
+ odp_u64be_t *free_list; /**< Free list base */
+
+ uint8_t free_list_len; /**< Number of free list entries */
+ uint8_t commit_pending; /**< Free list entries pending commit */
+
+ uint8_t cidx; /**< Free list consumer index */
+ uint8_t pidx; /**< Free list producer index */
+
+ uint32_t offset;/**< Offset into last free fragment */
+
+ mdev_dma_area_t rx_data;/**< RX packet payload area */
+
+ odp_ticketlock_t lock; /**< RX queue lock */
+} cxgb4_rx_queue_t;
+
+/* TX queue definitions */
+#define CXGB4_TX_QUEUE_NUM_MAX 32
+
+typedef struct {
+ odp_u64be_t data[8];
+} cxgb4_tx_desc_t;
+
+typedef struct {
+#define CXGB4_FW_ETH_TX_PKT_WR 0x0800UL
+ odp_u32be_t op_immdlen;
+ odp_u32be_t equiq_to_len16;
+ odp_u64be_t r3;
+} cxgb4_fw_eth_tx_pkt_wr_t;
+
+typedef struct {
+#define CPL_TX_PKT_XT 0xEE00UL
+#define TXPKT_PF_S 8
+#define TXPKT_PF_V(x) ((x) << TXPKT_PF_S)
+#define TXPKT_INTF_S 16
+#define TXPKT_INTF_V(x)((x) << TXPKT_INTF_S)
+ odp_u32be_t ctrl0;
+ odp_u16be_t pack;
+ odp_u16be_t len;
+#define TXPKT_IPCSUM_DIS_F (1UL << 62)
+#define TXPKT_L4CSUM_DIS_F (1UL << 63)
+ odp_u64be_t ctrl1;
+} cxgb4_cpl_tx_pkt_core_t;
+
+typedef struct {
+ odp_u32be_t len[2];
+ odp_u64be_t addr[2];
+} cxgb4_sg_pair_t;
+
+typedef struct {
+#define CXGB4_ULP_TX_SC_DSGL (0x82UL << 24)
+ odp_u32be_t sg_pairs_num;
+ odp_u32be_t len0;
+ odp_u64be_t addr0;
+ cxgb4_sg_pair_t sg_pairs[0];
+} cxgb4_sg_list_t;
+
+typedef struct {
+ odp_u32be_t qid;
+ odp_u16be_t cidx;
+ odp_u16be_t pidx;
+} cxgb4_tx_queue_stats;
+
+/** TX queue data */
+typedef struct ODP_ALIGNED_CACHE {
+ cxgb4_tx_desc_t *tx_descs; /**< TX queue base */
+ cxgb4_tx_queue_stats *stats;/**< TX queue stats */
+
+ odp_u32le_t *doorbell_desc; /**< TX queue doorbell */
+ uint32_t doorbell_desc_key; /**< 'Key' to the doorbell */
+
+ uint16_t tx_queue_len; /**< Number of TX desc entries */
+ uint16_t tx_next; /**< Next TX desc to insert */
+
+ mdev_dma_area_t tx_data;/**< TX packet payload area */
+
+ odp_ticketlock_t lock; /**< TX queue lock */
+} cxgb4_tx_queue_t;
+
+/** Packet socket using mediated cxgb4 device */
+typedef struct {
+ /** RX queue hot data */
+ cxgb4_rx_queue_t rx_queues[CXGB4_RX_QUEUE_NUM_MAX];
+
+ /** TX queue hot data */
+ cxgb4_tx_queue_t tx_queues[CXGB4_TX_QUEUE_NUM_MAX];
+
+ odp_pool_t pool;/**< pool to alloc packets from */
+
+ odp_bool_t lockless_rx;
Re: [lng-odp] [PATCH CATERPILLAR v3] Caterpillar mdev cxgb4
Mykyta Iziumtsev(MykytaI) replied on github web page:
platform/linux-generic/pktio/mdev/cxgb4.c
@@ -0,0 +1,887 @@
+/*Copyright (c) 2018, Linaro Limited
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "config.h"
+
+#ifdef ODP_MDEV
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#define MODULE_NAME "cxgb4"
+
+#define CXGB4_TX_BUF_SIZE 2048U
+
+#define CXGB4_TX_INLINE_MAX (256 - sizeof(cxgb4_fw_eth_tx_pkt_wr_t) \
+- sizeof(cxgb4_cpl_tx_pkt_core_t))
+
+/* RX queue definitions */
+#define CXGB4_RX_QUEUE_NUM_MAX 32
+
+/** RX descriptor */
+typedef struct {
+ uint32_t padding[12];
+
+ odp_u32be_t hdrbuflen_pidx;
+#define RX_DESC_NEW_BUF_FLAG (1U << 31)
+ odp_u32be_t pldbuflen_qid;
+ union {
+#define RX_DESC_GEN_SHIFT 7
+#define RX_DESC_GEN_MASK 0x1
+#define RX_DESC_TYPE_SHIFT 4
+#define RX_DESC_TYPE_MASK 0x3
+#define RX_DESC_TYPE_FLBUF_X 0
+#define RX_DESC_TYPE_CPL_X 1
+#define RX_DESC_TYPE_INTR_X2
+ uint8_t type_gen;
+#define RX_DESC_TIMESTAMP_MASK 0xfffULL
+ odp_u64be_t last_flit;
+ };
+} cxgb4_rx_desc_t;
+
+#define RX_DESC_TO_GEN(rxd) \
+ (((rxd)->type_gen >> RX_DESC_GEN_SHIFT) & RX_DESC_GEN_MASK)
+#define RX_DESC_TO_TYPE(rxd) \
+ (((rxd)->type_gen >> RX_DESC_TYPE_SHIFT) & RX_DESC_TYPE_MASK)
+
+/** RX queue data */
+typedef struct ODP_ALIGNED_CACHE {
+ cxgb4_rx_desc_t *rx_descs; /**< RX queue base */
+
+ odp_u32le_t *doorbell_fl; /**< Free list refill doorbell */
+ odp_u32le_t *doorbell_desc; /**< Rx descriptor free doorbell */
+ uint32_t doorbell_fl_key; /**< 'Key' to the doorbell */
+ uint32_t doorbell_desc_key; /**< 'Key' to the doorbell */
+
+ uint16_t rx_queue_len; /**< Number of RX desc entries */
+ uint16_t rx_next; /**< Next RX desc to handle */
+
+ uint32_t gen:1; /**< RX queue generation */
+
+ odp_u64be_t *free_list; /**< Free list base */
+
+ uint8_t free_list_len; /**< Number of free list entries */
+ uint8_t commit_pending; /**< Free list entries pending commit */
+
+ uint8_t cidx; /**< Free list consumer index */
+ uint8_t pidx; /**< Free list producer index */
+
+ uint32_t offset;/**< Offset into last free fragment */
+
+ mdev_dma_area_t rx_data;/**< RX packet payload area */
+
+ odp_ticketlock_t lock; /**< RX queue lock */
+} cxgb4_rx_queue_t;
+
+/* TX queue definitions */
+#define CXGB4_TX_QUEUE_NUM_MAX 32
+
+typedef struct {
+ odp_u64be_t data[8];
+} cxgb4_tx_desc_t;
+
+typedef struct {
+#define CXGB4_FW_ETH_TX_PKT_WR 0x0800UL
+ odp_u32be_t op_immdlen;
+ odp_u32be_t equiq_to_len16;
+ odp_u64be_t r3;
+} cxgb4_fw_eth_tx_pkt_wr_t;
+
+typedef struct {
+#define CPL_TX_PKT_XT 0xEE00UL
+#define TXPKT_PF_S 8
+#define TXPKT_PF_V(x) ((x) << TXPKT_PF_S)
+#define TXPKT_INTF_S 16
+#define TXPKT_INTF_V(x)((x) << TXPKT_INTF_S)
+ odp_u32be_t ctrl0;
+ odp_u16be_t pack;
+ odp_u16be_t len;
+#define TXPKT_IPCSUM_DIS_F (1UL << 62)
+#define TXPKT_L4CSUM_DIS_F (1UL << 63)
+ odp_u64be_t ctrl1;
+} cxgb4_cpl_tx_pkt_core_t;
+
+typedef struct {
+ odp_u32be_t len[2];
+ odp_u64be_t addr[2];
+} cxgb4_sg_pair_t;
+
+typedef struct {
+#define CXGB4_ULP_TX_SC_DSGL (0x82UL << 24)
+ odp_u32be_t sg_pairs_num;
+ odp_u32be_t len0;
+ odp_u64be_t addr0;
+ cxgb4_sg_pair_t sg_pairs[0];
+} cxgb4_sg_list_t;
+
+typedef struct {
+ odp_u32be_t qid;
+ odp_u16be_t cidx;
+ odp_u16be_t pidx;
+} cxgb4_tx_queue_stats;
+
+/** TX queue data */
+typedef struct ODP_ALIGNED_CACHE {
+ cxgb4_tx_desc_t *tx_descs; /**< TX queue base */
+ cxgb4_tx_queue_stats *stats;/**< TX queue stats */
+
+ odp_u32le_t *doorbell_desc; /**< TX queue doorbell */
+ uint32_t doorbell_desc_key; /**< 'Key' to the doorbell */
+
+ uint16_t tx_queue_len; /**< Number of TX desc entries */
+ uint16_t tx_next; /**< Next TX desc to insert */
+
+ mdev_dma_area_t tx_data;/**< TX packet payload area */
+
+ odp_ticketlock_t lock; /**< TX queue lock */
+} cxgb4_tx_queue_t;
+
+/** Packet socket using mediated cxgb4 device */
+typedef struct {
+ /** RX queue hot data */
+ cxgb4_rx_queue_t rx_queues[CXGB4_RX_QUEUE_NUM_MAX];
+
+ /** TX queue hot data */
+ cxgb4_tx_queue_t tx_queues[CXGB4_TX_QUEUE_NUM_MAX];
+
+ odp_pool_t pool;/**< pool to alloc packets from */
+
+ odp_bool_t lockless_rx; /**< no
Re: [lng-odp] [PATCH CATERPILLAR v3] Caterpillar mdev cxgb4
Mykyta Iziumtsev(MykytaI) replied on github web page:
platform/linux-generic/pktio/mdev/cxgb4.c
line 701
@@ -0,0 +1,887 @@
+/*Copyright (c) 2018, Linaro Limited
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "config.h"
+
+#ifdef ODP_MDEV
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#define MODULE_NAME "cxgb4"
+
+#define CXGB4_TX_BUF_SIZE 2048U
+
+#define CXGB4_TX_INLINE_MAX (256 - sizeof(cxgb4_fw_eth_tx_pkt_wr_t) \
+- sizeof(cxgb4_cpl_tx_pkt_core_t))
+
+/* RX queue definitions */
+#define CXGB4_RX_QUEUE_NUM_MAX 32
+
+/** RX descriptor */
+typedef struct {
+ uint32_t padding[12];
+
+ odp_u32be_t hdrbuflen_pidx;
+#define RX_DESC_NEW_BUF_FLAG (1U << 31)
+ odp_u32be_t pldbuflen_qid;
+ union {
+#define RX_DESC_GEN_SHIFT 7
+#define RX_DESC_GEN_MASK 0x1
+#define RX_DESC_TYPE_SHIFT 4
+#define RX_DESC_TYPE_MASK 0x3
+#define RX_DESC_TYPE_FLBUF_X 0
+#define RX_DESC_TYPE_CPL_X 1
+#define RX_DESC_TYPE_INTR_X2
+ uint8_t type_gen;
+#define RX_DESC_TIMESTAMP_MASK 0xfffULL
+ odp_u64be_t last_flit;
+ };
+} cxgb4_rx_desc_t;
+
+#define RX_DESC_TO_GEN(rxd) \
+ (((rxd)->type_gen >> RX_DESC_GEN_SHIFT) & RX_DESC_GEN_MASK)
+#define RX_DESC_TO_TYPE(rxd) \
+ (((rxd)->type_gen >> RX_DESC_TYPE_SHIFT) & RX_DESC_TYPE_MASK)
+
+/** RX queue data */
+typedef struct ODP_ALIGNED_CACHE {
+ cxgb4_rx_desc_t *rx_descs; /**< RX queue base */
+
+ odp_u32le_t *doorbell_fl; /**< Free list refill doorbell */
+ odp_u32le_t *doorbell_desc; /**< Rx descriptor free doorbell */
+ uint32_t doorbell_fl_key; /**< 'Key' to the doorbell */
+ uint32_t doorbell_desc_key; /**< 'Key' to the doorbell */
+
+ uint16_t rx_queue_len; /**< Number of RX desc entries */
+ uint16_t rx_next; /**< Next RX desc to handle */
+
+ uint32_t gen:1; /**< RX queue generation */
+
+ odp_u64be_t *free_list; /**< Free list base */
+
+ uint8_t free_list_len; /**< Number of free list entries */
+ uint8_t commit_pending; /**< Free list entries pending commit */
+
+ uint8_t cidx; /**< Free list consumer index */
+ uint8_t pidx; /**< Free list producer index */
+
+ uint32_t offset;/**< Offset into last free fragment */
+
+ mdev_dma_area_t rx_data;/**< RX packet payload area */
+
+ odp_ticketlock_t lock; /**< RX queue lock */
+} cxgb4_rx_queue_t;
+
+/* TX queue definitions */
+#define CXGB4_TX_QUEUE_NUM_MAX 32
+
+typedef struct {
+ odp_u64be_t data[8];
+} cxgb4_tx_desc_t;
+
+typedef struct {
+#define CXGB4_FW_ETH_TX_PKT_WR 0x0800UL
+ odp_u32be_t op_immdlen;
+ odp_u32be_t equiq_to_len16;
+ odp_u64be_t r3;
+} cxgb4_fw_eth_tx_pkt_wr_t;
+
+typedef struct {
+#define CPL_TX_PKT_XT 0xEE00UL
+#define TXPKT_PF_S 8
+#define TXPKT_PF_V(x) ((x) << TXPKT_PF_S)
+#define TXPKT_INTF_S 16
+#define TXPKT_INTF_V(x)((x) << TXPKT_INTF_S)
+ odp_u32be_t ctrl0;
+ odp_u16be_t pack;
+ odp_u16be_t len;
+#define TXPKT_IPCSUM_DIS_F (1UL << 62)
+#define TXPKT_L4CSUM_DIS_F (1UL << 63)
+ odp_u64be_t ctrl1;
+} cxgb4_cpl_tx_pkt_core_t;
+
+typedef struct {
+ odp_u32be_t len[2];
+ odp_u64be_t addr[2];
+} cxgb4_sg_pair_t;
+
+typedef struct {
+#define CXGB4_ULP_TX_SC_DSGL (0x82UL << 24)
+ odp_u32be_t sg_pairs_num;
+ odp_u32be_t len0;
+ odp_u64be_t addr0;
+ cxgb4_sg_pair_t sg_pairs[0];
+} cxgb4_sg_list_t;
+
+typedef struct {
+ odp_u32be_t qid;
+ odp_u16be_t cidx;
+ odp_u16be_t pidx;
+} cxgb4_tx_queue_stats;
+
+/** TX queue data */
+typedef struct ODP_ALIGNED_CACHE {
+ cxgb4_tx_desc_t *tx_descs; /**< TX queue base */
+ cxgb4_tx_queue_stats *stats;/**< TX queue stats */
+
+ odp_u32le_t *doorbell_desc; /**< TX queue doorbell */
+ uint32_t doorbell_desc_key; /**< 'Key' to the doorbell */
+
+ uint16_t tx_queue_len; /**< Number of TX desc entries */
+ uint16_t tx_next; /**< Next TX desc to insert */
+
+ mdev_dma_area_t tx_data;/**< TX packet payload area */
+
+ odp_ticketlock_t lock; /**< TX queue lock */
+} cxgb4_tx_queue_t;
+
+/** Packet socket using mediated cxgb4 device */
+typedef struct {
+ /** RX queue hot data */
+ cxgb4_rx_queue_t rx_queues[CXGB4_RX_QUEUE_NUM_MAX];
+
+ /** TX queue hot data */
+ cxgb4_tx_queue_t tx_queues[CXGB4_TX_QUEUE_NUM_MAX];
+
+ odp_pool_t pool;/**< pool to alloc packets from */
+
+ odp_bool_t lockless_rx;
Re: [lng-odp] [PATCH CATERPILLAR v3] Caterpillar mdev cxgb4
Bill Fischofer(Bill-Fischofer-Linaro) replied on github web page:
platform/linux-generic/pktio/mdev/cxgb4.c
line 701
@@ -0,0 +1,887 @@
+/*Copyright (c) 2018, Linaro Limited
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "config.h"
+
+#ifdef ODP_MDEV
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#define MODULE_NAME "cxgb4"
+
+#define CXGB4_TX_BUF_SIZE 2048U
+
+#define CXGB4_TX_INLINE_MAX (256 - sizeof(cxgb4_fw_eth_tx_pkt_wr_t) \
+- sizeof(cxgb4_cpl_tx_pkt_core_t))
+
+/* RX queue definitions */
+#define CXGB4_RX_QUEUE_NUM_MAX 32
+
+/** RX descriptor */
+typedef struct {
+ uint32_t padding[12];
+
+ odp_u32be_t hdrbuflen_pidx;
+#define RX_DESC_NEW_BUF_FLAG (1U << 31)
+ odp_u32be_t pldbuflen_qid;
+ union {
+#define RX_DESC_GEN_SHIFT 7
+#define RX_DESC_GEN_MASK 0x1
+#define RX_DESC_TYPE_SHIFT 4
+#define RX_DESC_TYPE_MASK 0x3
+#define RX_DESC_TYPE_FLBUF_X 0
+#define RX_DESC_TYPE_CPL_X 1
+#define RX_DESC_TYPE_INTR_X2
+ uint8_t type_gen;
+#define RX_DESC_TIMESTAMP_MASK 0xfffULL
+ odp_u64be_t last_flit;
+ };
+} cxgb4_rx_desc_t;
+
+#define RX_DESC_TO_GEN(rxd) \
+ (((rxd)->type_gen >> RX_DESC_GEN_SHIFT) & RX_DESC_GEN_MASK)
+#define RX_DESC_TO_TYPE(rxd) \
+ (((rxd)->type_gen >> RX_DESC_TYPE_SHIFT) & RX_DESC_TYPE_MASK)
+
+/** RX queue data */
+typedef struct ODP_ALIGNED_CACHE {
+ cxgb4_rx_desc_t *rx_descs; /**< RX queue base */
+
+ odp_u32le_t *doorbell_fl; /**< Free list refill doorbell */
+ odp_u32le_t *doorbell_desc; /**< Rx descriptor free doorbell */
+ uint32_t doorbell_fl_key; /**< 'Key' to the doorbell */
+ uint32_t doorbell_desc_key; /**< 'Key' to the doorbell */
+
+ uint16_t rx_queue_len; /**< Number of RX desc entries */
+ uint16_t rx_next; /**< Next RX desc to handle */
+
+ uint32_t gen:1; /**< RX queue generation */
+
+ odp_u64be_t *free_list; /**< Free list base */
+
+ uint8_t free_list_len; /**< Number of free list entries */
+ uint8_t commit_pending; /**< Free list entries pending commit */
+
+ uint8_t cidx; /**< Free list consumer index */
+ uint8_t pidx; /**< Free list producer index */
+
+ uint32_t offset;/**< Offset into last free fragment */
+
+ mdev_dma_area_t rx_data;/**< RX packet payload area */
+
+ odp_ticketlock_t lock; /**< RX queue lock */
+} cxgb4_rx_queue_t;
+
+/* TX queue definitions */
+#define CXGB4_TX_QUEUE_NUM_MAX 32
+
+typedef struct {
+ odp_u64be_t data[8];
+} cxgb4_tx_desc_t;
+
+typedef struct {
+#define CXGB4_FW_ETH_TX_PKT_WR 0x0800UL
+ odp_u32be_t op_immdlen;
+ odp_u32be_t equiq_to_len16;
+ odp_u64be_t r3;
+} cxgb4_fw_eth_tx_pkt_wr_t;
+
+typedef struct {
+#define CPL_TX_PKT_XT 0xEE00UL
+#define TXPKT_PF_S 8
+#define TXPKT_PF_V(x) ((x) << TXPKT_PF_S)
+#define TXPKT_INTF_S 16
+#define TXPKT_INTF_V(x)((x) << TXPKT_INTF_S)
+ odp_u32be_t ctrl0;
+ odp_u16be_t pack;
+ odp_u16be_t len;
+#define TXPKT_IPCSUM_DIS_F (1UL << 62)
+#define TXPKT_L4CSUM_DIS_F (1UL << 63)
+ odp_u64be_t ctrl1;
+} cxgb4_cpl_tx_pkt_core_t;
+
+typedef struct {
+ odp_u32be_t len[2];
+ odp_u64be_t addr[2];
+} cxgb4_sg_pair_t;
+
+typedef struct {
+#define CXGB4_ULP_TX_SC_DSGL (0x82UL << 24)
+ odp_u32be_t sg_pairs_num;
+ odp_u32be_t len0;
+ odp_u64be_t addr0;
+ cxgb4_sg_pair_t sg_pairs[0];
+} cxgb4_sg_list_t;
+
+typedef struct {
+ odp_u32be_t qid;
+ odp_u16be_t cidx;
+ odp_u16be_t pidx;
+} cxgb4_tx_queue_stats;
+
+/** TX queue data */
+typedef struct ODP_ALIGNED_CACHE {
+ cxgb4_tx_desc_t *tx_descs; /**< TX queue base */
+ cxgb4_tx_queue_stats *stats;/**< TX queue stats */
+
+ odp_u32le_t *doorbell_desc; /**< TX queue doorbell */
+ uint32_t doorbell_desc_key; /**< 'Key' to the doorbell */
+
+ uint16_t tx_queue_len; /**< Number of TX desc entries */
+ uint16_t tx_next; /**< Next TX desc to insert */
+
+ mdev_dma_area_t tx_data;/**< TX packet payload area */
+
+ odp_ticketlock_t lock; /**< TX queue lock */
+} cxgb4_tx_queue_t;
+
+/** Packet socket using mediated cxgb4 device */
+typedef struct {
+ /** RX queue hot data */
+ cxgb4_rx_queue_t rx_queues[CXGB4_RX_QUEUE_NUM_MAX];
+
+ /** TX queue hot data */
+ cxgb4_tx_queue_t tx_queues[CXGB4_TX_QUEUE_NUM_MAX];
+
+ odp_pool_t pool;/**< pool to alloc packets from */
+
+ odp_bool_t lockless_rx;
Re: [lng-odp] [PATCH CATERPILLAR v3] Caterpillar mdev cxgb4
Bill Fischofer(Bill-Fischofer-Linaro) replied on github web page:
platform/linux-generic/pktio/mdev/cxgb4.c
@@ -0,0 +1,887 @@
+/*Copyright (c) 2018, Linaro Limited
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "config.h"
+
+#ifdef ODP_MDEV
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#define MODULE_NAME "cxgb4"
+
+#define CXGB4_TX_BUF_SIZE 2048U
+
+#define CXGB4_TX_INLINE_MAX (256 - sizeof(cxgb4_fw_eth_tx_pkt_wr_t) \
+- sizeof(cxgb4_cpl_tx_pkt_core_t))
+
+/* RX queue definitions */
+#define CXGB4_RX_QUEUE_NUM_MAX 32
+
+/** RX descriptor */
+typedef struct {
+ uint32_t padding[12];
+
+ odp_u32be_t hdrbuflen_pidx;
+#define RX_DESC_NEW_BUF_FLAG (1U << 31)
+ odp_u32be_t pldbuflen_qid;
+ union {
+#define RX_DESC_GEN_SHIFT 7
+#define RX_DESC_GEN_MASK 0x1
+#define RX_DESC_TYPE_SHIFT 4
+#define RX_DESC_TYPE_MASK 0x3
+#define RX_DESC_TYPE_FLBUF_X 0
+#define RX_DESC_TYPE_CPL_X 1
+#define RX_DESC_TYPE_INTR_X2
+ uint8_t type_gen;
+#define RX_DESC_TIMESTAMP_MASK 0xfffULL
+ odp_u64be_t last_flit;
+ };
+} cxgb4_rx_desc_t;
+
+#define RX_DESC_TO_GEN(rxd) \
+ (((rxd)->type_gen >> RX_DESC_GEN_SHIFT) & RX_DESC_GEN_MASK)
+#define RX_DESC_TO_TYPE(rxd) \
+ (((rxd)->type_gen >> RX_DESC_TYPE_SHIFT) & RX_DESC_TYPE_MASK)
+
+/** RX queue data */
+typedef struct ODP_ALIGNED_CACHE {
+ cxgb4_rx_desc_t *rx_descs; /**< RX queue base */
+
+ odp_u32le_t *doorbell_fl; /**< Free list refill doorbell */
+ odp_u32le_t *doorbell_desc; /**< Rx descriptor free doorbell */
+ uint32_t doorbell_fl_key; /**< 'Key' to the doorbell */
+ uint32_t doorbell_desc_key; /**< 'Key' to the doorbell */
+
+ uint16_t rx_queue_len; /**< Number of RX desc entries */
+ uint16_t rx_next; /**< Next RX desc to handle */
+
+ uint32_t gen:1; /**< RX queue generation */
+
+ odp_u64be_t *free_list; /**< Free list base */
+
+ uint8_t free_list_len; /**< Number of free list entries */
+ uint8_t commit_pending; /**< Free list entries pending commit */
+
+ uint8_t cidx; /**< Free list consumer index */
+ uint8_t pidx; /**< Free list producer index */
+
+ uint32_t offset;/**< Offset into last free fragment */
+
+ mdev_dma_area_t rx_data;/**< RX packet payload area */
+
+ odp_ticketlock_t lock; /**< RX queue lock */
+} cxgb4_rx_queue_t;
+
+/* TX queue definitions */
+#define CXGB4_TX_QUEUE_NUM_MAX 32
+
+typedef struct {
+ odp_u64be_t data[8];
+} cxgb4_tx_desc_t;
+
+typedef struct {
+#define CXGB4_FW_ETH_TX_PKT_WR 0x0800UL
+ odp_u32be_t op_immdlen;
+ odp_u32be_t equiq_to_len16;
+ odp_u64be_t r3;
+} cxgb4_fw_eth_tx_pkt_wr_t;
+
+typedef struct {
+#define CPL_TX_PKT_XT 0xEE00UL
+#define TXPKT_PF_S 8
+#define TXPKT_PF_V(x) ((x) << TXPKT_PF_S)
+#define TXPKT_INTF_S 16
+#define TXPKT_INTF_V(x)((x) << TXPKT_INTF_S)
+ odp_u32be_t ctrl0;
+ odp_u16be_t pack;
+ odp_u16be_t len;
+#define TXPKT_IPCSUM_DIS_F (1UL << 62)
+#define TXPKT_L4CSUM_DIS_F (1UL << 63)
+ odp_u64be_t ctrl1;
+} cxgb4_cpl_tx_pkt_core_t;
+
+typedef struct {
+ odp_u32be_t len[2];
+ odp_u64be_t addr[2];
+} cxgb4_sg_pair_t;
+
+typedef struct {
+#define CXGB4_ULP_TX_SC_DSGL (0x82UL << 24)
+ odp_u32be_t sg_pairs_num;
+ odp_u32be_t len0;
+ odp_u64be_t addr0;
+ cxgb4_sg_pair_t sg_pairs[0];
+} cxgb4_sg_list_t;
+
+typedef struct {
+ odp_u32be_t qid;
+ odp_u16be_t cidx;
+ odp_u16be_t pidx;
+} cxgb4_tx_queue_stats;
+
+/** TX queue data */
+typedef struct ODP_ALIGNED_CACHE {
+ cxgb4_tx_desc_t *tx_descs; /**< TX queue base */
+ cxgb4_tx_queue_stats *stats;/**< TX queue stats */
+
+ odp_u32le_t *doorbell_desc; /**< TX queue doorbell */
+ uint32_t doorbell_desc_key; /**< 'Key' to the doorbell */
+
+ uint16_t tx_queue_len; /**< Number of TX desc entries */
+ uint16_t tx_next; /**< Next TX desc to insert */
+
+ mdev_dma_area_t tx_data;/**< TX packet payload area */
+
+ odp_ticketlock_t lock; /**< TX queue lock */
+} cxgb4_tx_queue_t;
+
+/** Packet socket using mediated cxgb4 device */
+typedef struct {
+ /** RX queue hot data */
+ cxgb4_rx_queue_t rx_queues[CXGB4_RX_QUEUE_NUM_MAX];
+
+ /** TX queue hot data */
+ cxgb4_tx_queue_t tx_queues[CXGB4_TX_QUEUE_NUM_MAX];
+
+ odp_pool_t pool;/**< pool to alloc packets from */
+
+ odp_bool_t lockless_rx;
Re: [lng-odp] [PATCH CATERPILLAR v3] Caterpillar mdev cxgb4
Bill Fischofer(Bill-Fischofer-Linaro) replied on github web page:
platform/linux-generic/pktio/mdev/cxgb4.c
@@ -0,0 +1,887 @@
+/*Copyright (c) 2018, Linaro Limited
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "config.h"
+
+#ifdef ODP_MDEV
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#define MODULE_NAME "cxgb4"
+
+#define CXGB4_TX_BUF_SIZE 2048U
+
+#define CXGB4_TX_INLINE_MAX (256 - sizeof(cxgb4_fw_eth_tx_pkt_wr_t) \
+- sizeof(cxgb4_cpl_tx_pkt_core_t))
+
+/* RX queue definitions */
+#define CXGB4_RX_QUEUE_NUM_MAX 32
+
+/** RX descriptor */
+typedef struct {
+ uint32_t padding[12];
+
+ odp_u32be_t hdrbuflen_pidx;
+#define RX_DESC_NEW_BUF_FLAG (1U << 31)
+ odp_u32be_t pldbuflen_qid;
+ union {
+#define RX_DESC_GEN_SHIFT 7
+#define RX_DESC_GEN_MASK 0x1
+#define RX_DESC_TYPE_SHIFT 4
+#define RX_DESC_TYPE_MASK 0x3
+#define RX_DESC_TYPE_FLBUF_X 0
+#define RX_DESC_TYPE_CPL_X 1
+#define RX_DESC_TYPE_INTR_X2
+ uint8_t type_gen;
+#define RX_DESC_TIMESTAMP_MASK 0xfffULL
+ odp_u64be_t last_flit;
+ };
+} cxgb4_rx_desc_t;
+
+#define RX_DESC_TO_GEN(rxd) \
+ (((rxd)->type_gen >> RX_DESC_GEN_SHIFT) & RX_DESC_GEN_MASK)
+#define RX_DESC_TO_TYPE(rxd) \
+ (((rxd)->type_gen >> RX_DESC_TYPE_SHIFT) & RX_DESC_TYPE_MASK)
+
+/** RX queue data */
+typedef struct ODP_ALIGNED_CACHE {
+ cxgb4_rx_desc_t *rx_descs; /**< RX queue base */
+
+ odp_u32le_t *doorbell_fl; /**< Free list refill doorbell */
+ odp_u32le_t *doorbell_desc; /**< Rx descriptor free doorbell */
+ uint32_t doorbell_fl_key; /**< 'Key' to the doorbell */
+ uint32_t doorbell_desc_key; /**< 'Key' to the doorbell */
+
+ uint16_t rx_queue_len; /**< Number of RX desc entries */
+ uint16_t rx_next; /**< Next RX desc to handle */
+
+ uint32_t gen:1; /**< RX queue generation */
+
+ odp_u64be_t *free_list; /**< Free list base */
+
+ uint8_t free_list_len; /**< Number of free list entries */
+ uint8_t commit_pending; /**< Free list entries pending commit */
+
+ uint8_t cidx; /**< Free list consumer index */
+ uint8_t pidx; /**< Free list producer index */
+
+ uint32_t offset;/**< Offset into last free fragment */
+
+ mdev_dma_area_t rx_data;/**< RX packet payload area */
+
+ odp_ticketlock_t lock; /**< RX queue lock */
+} cxgb4_rx_queue_t;
+
+/* TX queue definitions */
+#define CXGB4_TX_QUEUE_NUM_MAX 32
+
+typedef struct {
+ odp_u64be_t data[8];
+} cxgb4_tx_desc_t;
+
+typedef struct {
+#define CXGB4_FW_ETH_TX_PKT_WR 0x0800UL
+ odp_u32be_t op_immdlen;
+ odp_u32be_t equiq_to_len16;
+ odp_u64be_t r3;
+} cxgb4_fw_eth_tx_pkt_wr_t;
+
+typedef struct {
+#define CPL_TX_PKT_XT 0xEE00UL
+#define TXPKT_PF_S 8
+#define TXPKT_PF_V(x) ((x) << TXPKT_PF_S)
+#define TXPKT_INTF_S 16
+#define TXPKT_INTF_V(x)((x) << TXPKT_INTF_S)
+ odp_u32be_t ctrl0;
+ odp_u16be_t pack;
+ odp_u16be_t len;
+#define TXPKT_IPCSUM_DIS_F (1UL << 62)
+#define TXPKT_L4CSUM_DIS_F (1UL << 63)
+ odp_u64be_t ctrl1;
+} cxgb4_cpl_tx_pkt_core_t;
+
+typedef struct {
+ odp_u32be_t len[2];
+ odp_u64be_t addr[2];
+} cxgb4_sg_pair_t;
+
+typedef struct {
+#define CXGB4_ULP_TX_SC_DSGL (0x82UL << 24)
+ odp_u32be_t sg_pairs_num;
+ odp_u32be_t len0;
+ odp_u64be_t addr0;
+ cxgb4_sg_pair_t sg_pairs[0];
+} cxgb4_sg_list_t;
+
+typedef struct {
+ odp_u32be_t qid;
+ odp_u16be_t cidx;
+ odp_u16be_t pidx;
+} cxgb4_tx_queue_stats;
+
+/** TX queue data */
+typedef struct ODP_ALIGNED_CACHE {
+ cxgb4_tx_desc_t *tx_descs; /**< TX queue base */
+ cxgb4_tx_queue_stats *stats;/**< TX queue stats */
+
+ odp_u32le_t *doorbell_desc; /**< TX queue doorbell */
+ uint32_t doorbell_desc_key; /**< 'Key' to the doorbell */
+
+ uint16_t tx_queue_len; /**< Number of TX desc entries */
+ uint16_t tx_next; /**< Next TX desc to insert */
+
+ mdev_dma_area_t tx_data;/**< TX packet payload area */
+
+ odp_ticketlock_t lock; /**< TX queue lock */
+} cxgb4_tx_queue_t;
+
+/** Packet socket using mediated cxgb4 device */
+typedef struct {
+ /** RX queue hot data */
+ cxgb4_rx_queue_t rx_queues[CXGB4_RX_QUEUE_NUM_MAX];
+
+ /** TX queue hot data */
+ cxgb4_tx_queue_t tx_queues[CXGB4_TX_QUEUE_NUM_MAX];
+
+ odp_pool_t pool;/**< pool to alloc packets from */
+
+ odp_bool_t lockless_rx;
