Mesa (master): glx: Add missing null check in __glX_send_client_info()
Module: Mesa
Branch: master
Commit: d530745169282469b2dd8221629ef948ff31bcf3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d530745169282469b2dd8221629ef948ff31bcf3
Author: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com
Date: Fri Feb 7 14:44:03 2014 +0200
glx: Add missing null check in __glX_send_client_info()
Signed-off-by: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com
Reviewed-by: Brian Paul bri...@vmware.com
---
src/glx/clientinfo.c |4
1 file changed, 4 insertions(+)
diff --git a/src/glx/clientinfo.c b/src/glx/clientinfo.c
index e90fd79..8f3fdeb 100644
--- a/src/glx/clientinfo.c
+++ b/src/glx/clientinfo.c
@@ -113,6 +113,10 @@ __glX_send_client_info(struct glx_display *glx_dpy)
}
gl_extension_string = __glXGetClientGLExtensionString();
+ if (gl_extension_string == NULL) {
+ return;
+ }
+
gl_extension_length = strlen(gl_extension_string) + 1;
c = XGetXCBConnection(glx_dpy-dpy);
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Mesa (master): gallium/tgsi: correct typo propagated from NV_vertex_program1_1
Module: Mesa Branch: master Commit: 5125165dde6ea6c3599810a92d6bcd4a5650adfd URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5125165dde6ea6c3599810a92d6bcd4a5650adfd Author: Erik Faye-Lund kusmab...@gmail.com Date: Fri Feb 7 13:45:11 2014 +0100 gallium/tgsi: correct typo propagated from NV_vertex_program1_1 In the specification text of NV_vertex_program1_1, the upper limit of the RCC instruction is written as 1.884467e+19 in scientific notation, but as 0x5F80 in binary. But the binary version translates to 1.84467e+19 rather than 1.884467e+19 in scientific notation. Since the lower-limit equals 2^-64 and the binary version equals 2^+64, let's assume the value in scientific notation is a typo and implement this using the value from the binary version instead. Signed-off-by: Erik Faye-Lund kusmab...@gmail.com Reviewed-by: Brian Paul bri...@vmware.com --- src/gallium/auxiliary/tgsi/tgsi_exec.c |4 ++-- src/gallium/docs/source/tgsi.rst |2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c b/src/gallium/auxiliary/tgsi/tgsi_exec.c index 96809cd..55da60a 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_exec.c +++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c @@ -915,9 +915,9 @@ micro_rcc(union tgsi_exec_channel *dst, float recip = 1.0f / src-f[i]; if (recip 0.0f) - dst-f[i] = CLAMP(recip, 5.42101e-020f, 1.884467e+019f); + dst-f[i] = CLAMP(recip, 5.42101e-020f, 1.84467e+019f); else - dst-f[i] = CLAMP(recip, -1.884467e+019f, -5.42101e-020f); + dst-f[i] = CLAMP(recip, -1.84467e+019f, -5.42101e-020f); } } diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst index 0501aca..be42572 100644 --- a/src/gallium/docs/source/tgsi.rst +++ b/src/gallium/docs/source/tgsi.rst @@ -424,7 +424,7 @@ XXX cleanup on aisle three .. math:: - dst = (1 / src.x) 0 ? clamp(1 / src.x, 5.42101e-020, 1.884467e+019) : clamp(1 / src.x, -1.884467e+019, -5.42101e-020) + dst = (1 / src.x) 0 ? clamp(1 / src.x, 5.42101e-020, 1.84467e+019) : clamp(1 / src.x, -1.84467e+019, -5.42101e-020) .. opcode:: DPH - Homogeneous Dot Product ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): gallium/tgsi: use CLAMP instead of open-coded clamps
Module: Mesa
Branch: master
Commit: 7a49a796a41fa5ba3dccc2e13de43520b8d05bb6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a49a796a41fa5ba3dccc2e13de43520b8d05bb6
Author: Erik Faye-Lund kusmab...@gmail.com
Date: Fri Feb 7 13:45:10 2014 +0100
gallium/tgsi: use CLAMP instead of open-coded clamps
Signed-off-by: Erik Faye-Lund kusmab...@gmail.com
Reviewed-by: Brian Paul bri...@vmware.com
---
src/gallium/auxiliary/tgsi/tgsi_exec.c | 26 --
1 file changed, 4 insertions(+), 22 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c
b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index 3d37eaa..96809cd 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -914,28 +914,10 @@ micro_rcc(union tgsi_exec_channel *dst,
for (i = 0; i 4; i++) {
float recip = 1.0f / src-f[i];
- if (recip 0.0f) {
- if (recip 1.884467e+019f) {
-dst-f[i] = 1.884467e+019f;
- }
- else if (recip 5.42101e-020f) {
-dst-f[i] = 5.42101e-020f;
- }
- else {
-dst-f[i] = recip;
- }
- }
- else {
- if (recip -1.884467e+019f) {
-dst-f[i] = -1.884467e+019f;
- }
- else if (recip -5.42101e-020f) {
-dst-f[i] = -5.42101e-020f;
- }
- else {
-dst-f[i] = recip;
- }
- }
+ if (recip 0.0f)
+ dst-f[i] = CLAMP(recip, 5.42101e-020f, 1.884467e+019f);
+ else
+ dst-f[i] = CLAMP(recip, -1.884467e+019f, -5.42101e-020f);
}
}
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Mesa (master): glx: Add some missing null checks in glx_pbuffer.c
Module: Mesa
Branch: master
Commit: e503609e6feb9373ec3bba4ff028a66f1517be30
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e503609e6feb9373ec3bba4ff028a66f1517be30
Author: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com
Date: Fri Feb 7 14:44:00 2014 +0200
glx: Add some missing null checks in glx_pbuffer.c
Signed-off-by: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com
Reviewed-by: Brian Paul bri...@vmware.com
---
src/glx/glx_pbuffer.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/src/glx/glx_pbuffer.c b/src/glx/glx_pbuffer.c
index 183fbaa..411d6e5 100644
--- a/src/glx/glx_pbuffer.c
+++ b/src/glx/glx_pbuffer.c
@@ -60,7 +60,7 @@ warn_GLX_1_3(Display * dpy, const char *function_name)
{
struct glx_display *priv = __glXInitialize(dpy);
- if (priv-minorVersion 3) {
+ if (priv priv-minorVersion 3) {
fprintf(stderr,
WARNING: Application calling GLX 1.3 function \%s\
when GLX 1.3 is not supported! This is an application bug!\n,
@@ -91,7 +91,7 @@ ChangeDrawableAttribute(Display * dpy, GLXDrawable drawable,
CARD8 opcode;
int i;
- if ((dpy == NULL) || (drawable == 0)) {
+ if ((priv == NULL) || (dpy == NULL) || (drawable == 0)) {
return;
}
@@ -197,6 +197,11 @@ CreateDRIDrawable(Display *dpy, struct glx_config *config,
__GLXDRIdrawable *pdraw;
struct glx_screen *psc;
+ if (priv == NULL) {
+ fprintf(stderr, failed to create drawable\n);
+ return GL_FALSE;
+ }
+
psc = priv-screens[config-screen];
if (psc-driScreen == NULL)
return GL_TRUE;
@@ -226,7 +231,7 @@ DestroyDRIDrawable(Display *dpy, GLXDrawable drawable, int
destroy_xdrawable)
__GLXDRIdrawable *pdraw = GetGLXDRIDrawable(dpy, drawable);
XID xid;
- if (pdraw != NULL) {
+ if (priv != NULL pdraw != NULL) {
xid = pdraw-xDrawable;
(*pdraw-destroyDrawable) (pdraw);
__glxHashDelete(priv-drawHash, drawable);
@@ -294,6 +299,9 @@ GetDrawableAttribute(Display * dpy, GLXDrawable drawable,
}
priv = __glXInitialize(dpy);
+ if (priv == NULL)
+ return 0;
+
use_glx_1_3 = ((priv-majorVersion 1) || (priv-minorVersion = 3));
*value = 0;
@@ -504,6 +512,9 @@ CreatePbuffer(Display * dpy, struct glx_config *config,
Pixmap pixmap;
GLboolean glx_1_3 = GL_FALSE;
+ if (priv == NULL)
+ return None;
+
i = 0;
if (attrib_list) {
while (attrib_list[i * 2])
@@ -593,7 +604,7 @@ DestroyPbuffer(Display * dpy, GLXDrawable drawable)
struct glx_display *priv = __glXInitialize(dpy);
CARD8 opcode;
- if ((dpy == NULL) || (drawable == 0)) {
+ if ((priv == NULL) || (dpy == NULL) || (drawable == 0)) {
return;
}
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Mesa (master): egl: Unhide functionality in _eglInitContext()
Module: Mesa Branch: master Commit: 1456ed85f0ed8b9c9f0abd6bd389a089fa3824b2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1456ed85f0ed8b9c9f0abd6bd389a089fa3824b2 Author: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com Date: Fri Feb 7 14:44:04 2014 +0200 egl: Unhide functionality in _eglInitContext() _eglInitResource() was used to memset entire _EGLContext by writing more than size of pointed target. This does work as long as Resource is the first element in _EGLContext, this patch fixes such dependency. Signed-off-by: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com Reviewed-by: Brian Paul bri...@vmware.com --- src/egl/main/eglcontext.c |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/egl/main/eglcontext.c b/src/egl/main/eglcontext.c index 79a92c7..99d1c3e 100644 --- a/src/egl/main/eglcontext.c +++ b/src/egl/main/eglcontext.c @@ -366,7 +366,8 @@ _eglInitContext(_EGLContext *ctx, _EGLDisplay *dpy, _EGLConfig *conf, return EGL_FALSE; } - _eglInitResource(ctx-Resource, sizeof(*ctx), dpy); + memset(ctx, 0, sizeof(_EGLContext)); + _eglInitResource(ctx-Resource, sizeof(_EGLResource), dpy); ctx-ClientAPI = api; ctx-Config = conf; ctx-WindowRenderBuffer = EGL_NONE; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glx: Add missing null check in __glXCloseDisplay
Module: Mesa Branch: master Commit: 2ae1437a8ecf81676012c7a3507a6ed58e7338b2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ae1437a8ecf81676012c7a3507a6ed58e7338b2 Author: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com Date: Fri Feb 7 14:43:58 2014 +0200 glx: Add missing null check in __glXCloseDisplay Signed-off-by: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com Reviewed-by: Brian Paul bri...@vmware.com --- src/glx/glxext.c |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/glx/glxext.c b/src/glx/glxext.c index 2711e57..4a195bd 100644 --- a/src/glx/glxext.c +++ b/src/glx/glxext.c @@ -269,7 +269,8 @@ __glXCloseDisplay(Display * dpy, XExtCodes * codes) } _XUnlockMutex(_Xglobal_lock); - glx_display_free(priv); + if (priv != NULL) + glx_display_free(priv); return 1; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): egl: Unhide functionality in _eglInitSurface()
Module: Mesa Branch: master Commit: 498d10e230663f8604d00608cae6324f779c9cdd URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=498d10e230663f8604d00608cae6324f779c9cdd Author: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com Date: Fri Feb 7 14:44:05 2014 +0200 egl: Unhide functionality in _eglInitSurface() _eglInitResource() was used to memset entire _EGLSurface by writing more than size of pointed target. This does work as long as Resource is the first element in _EGLSurface, this patch fixes such dependency. Signed-off-by: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com Reviewed-by: Brian Paul bri...@vmware.com --- src/egl/main/eglsurface.c |4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/egl/main/eglsurface.c b/src/egl/main/eglsurface.c index c5ea224..1dca3e0 100644 --- a/src/egl/main/eglsurface.c +++ b/src/egl/main/eglsurface.c @@ -314,7 +314,9 @@ _eglInitSurface(_EGLSurface *surf, _EGLDisplay *dpy, EGLint type, return EGL_FALSE; } - _eglInitResource(surf-Resource, sizeof(*surf), dpy); + + memset(surf, 0, sizeof(_EGLSurface)); + _eglInitResource(surf-Resource, sizeof(_EGLResource), dpy); surf-Type = type; surf-Config = conf; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl: Fix null access on file read error
Module: Mesa
Branch: master
Commit: 88cad8356eadde7b6bc25cc5a0c1762352e5b3f7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=88cad8356eadde7b6bc25cc5a0c1762352e5b3f7
Author: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com
Date: Fri Feb 7 14:43:59 2014 +0200
glsl: Fix null access on file read error
Signed-off-by: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com
Reviewed-by: Brian Paul bri...@vmware.com
---
src/glsl/main.cpp |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/glsl/main.cpp b/src/glsl/main.cpp
index 5ea57d5..3a0f812 100644
--- a/src/glsl/main.cpp
+++ b/src/glsl/main.cpp
@@ -232,7 +232,7 @@ load_text_file(void *ctx, const char *file_name)
if (bytes size - total_read) {
free(text);
text = NULL;
- break;
+ goto error;
}
if (bytes == 0) {
@@ -243,6 +243,7 @@ load_text_file(void *ctx, const char *file_name)
} while (total_read size);
text[total_read] = '\0';
+error:;
}
fclose(fp);
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Mesa (master): i965: Add missing null check in fs_visitor:: dead_code_eliminate_local()
Module: Mesa
Branch: master
Commit: d3e948340be3fe61d3724f1b96651c2097b4026e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d3e948340be3fe61d3724f1b96651c2097b4026e
Author: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com
Date: Fri Feb 7 14:44:02 2014 +0200
i965: Add missing null check in fs_visitor::dead_code_eliminate_local()
Signed-off-by: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com
Reviewed-by: Brian Paul bri...@vmware.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp |4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index c290c28..217892a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2190,6 +2190,10 @@ fs_visitor::dead_code_eliminate_local()
ht = _mesa_hash_table_create(mem_ctx, dead_code_hash_compare);
+ if (ht == NULL) {
+ return false;
+ }
+
foreach_list_safe(node, this-instructions) {
fs_inst *inst = (fs_inst *)node;
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Mesa (master): st/mesa: avoid sw fallback for getting/ decompressing textures
Module: Mesa
Branch: master
Commit: f47e5962885d9f7de23a8c9c9ba035017e24ffd6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f47e5962885d9f7de23a8c9c9ba035017e24ffd6
Author: Brian Paul bri...@vmware.com
Date: Fri Feb 7 09:32:05 2014 -0700
st/mesa: avoid sw fallback for getting/decompressing textures
If st_GetTexImage() is to decompress the texture, avoid the fallback
path even if prefer_blit_based_texture_transfer = false. For drivers
that returned PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER = 0, we
were always taking the fallback path for texture decompression rather
than rendering a quad. The later is a lot faster.
Cc: 10.0 10.1 mesa-sta...@lists.freedesktop.org
Reviewed-by: Marek Olšák marek.ol...@amd.com
---
src/mesa/state_tracker/st_cb_texture.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st_cb_texture.c
b/src/mesa/state_tracker/st_cb_texture.c
index 824a13e..f0bf374 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -865,7 +865,9 @@ st_GetTexImage(struct gl_context * ctx,
ubyte *map = NULL;
boolean done = FALSE;
- if (!st-prefer_blit_based_texture_transfer) {
+ if (!st-prefer_blit_based_texture_transfer
+ !_mesa_is_format_compressed(texImage-TexFormat)) {
+ /* Try to avoid the fallback if we're doing texture decompression here */
goto fallback;
}
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Mesa (master): glx: Add missing null checks in glxcmds.c
Module: Mesa
Branch: master
Commit: d28e92ff74892be2ce345e33863a172ae29825b6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d28e92ff74892be2ce345e33863a172ae29825b6
Author: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com
Date: Fri Feb 7 14:43:57 2014 +0200
glx: Add missing null checks in glxcmds.c
Signed-off-by: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com
Reviewed-by: Brian Paul bri...@vmware.com
---
src/glx/glxcmds.c | 28
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/src/glx/glxcmds.c b/src/glx/glxcmds.c
index b5377c2..38a5262 100644
--- a/src/glx/glxcmds.c
+++ b/src/glx/glxcmds.c
@@ -385,7 +385,9 @@ glXCreateContext(Display * dpy, XVisualInfo * vis,
#if defined(GLX_DIRECT_RENDERING) || defined(GLX_USE_APPLEGL)
struct glx_screen *const psc = GetGLXScreenConfigs(dpy, vis-screen);
- config = glx_config_find_visual(psc-visuals, vis-visualid);
+ if (psc)
+ config = glx_config_find_visual(psc-visuals, vis-visualid);
+
if (config == NULL) {
xError error;
@@ -694,6 +696,13 @@ glXCreateGLXPixmap(Display * dpy, XVisualInfo * vis,
Pixmap pixmap)
GLXPixmap xid;
CARD8 opcode;
+#if defined(GLX_DIRECT_RENDERING) !defined(GLX_USE_APPLEGL)
+ struct glx_display *const priv = __glXInitialize(dpy);
+
+ if (priv == NULL)
+ return None;
+#endif
+
opcode = __glXSetupForCommand(dpy);
if (!opcode) {
return None;
@@ -725,7 +734,6 @@ glXCreateGLXPixmap(Display * dpy, XVisualInfo * vis, Pixmap
pixmap)
/* FIXME: Maybe delay __DRIdrawable creation until the drawable
* is actually bound to a context... */
- struct glx_display *const priv = __glXInitialize(dpy);
__GLXDRIdrawable *pdraw;
struct glx_screen *psc;
struct glx_config *config;
@@ -799,7 +807,7 @@ glXDestroyGLXPixmap(Display * dpy, GLXPixmap glxpixmap)
struct glx_display *const priv = __glXInitialize(dpy);
__GLXDRIdrawable *pdraw = GetGLXDRIDrawable(dpy, glxpixmap);
- if (pdraw != NULL) {
+ if (priv != NULL pdraw != NULL) {
(*pdraw-destroyDrawable) (pdraw);
__glxHashDelete(priv-drawHash, glxpixmap);
}
@@ -1434,6 +1442,9 @@ glXImportContextEXT(Display *dpy, GLXContextID contextID)
uint32_t screen = 0;
Bool got_screen = False;
+ if (priv == NULL)
+ return NULL;
+
/* The GLX_EXT_import_context spec says:
*
* If contextID does not refer to a valid context, then a BadContext
@@ -1750,7 +1761,8 @@ __glXSwapIntervalSGI(int interval)
psc = GetGLXScreenConfigs( gc-currentDpy, gc-screen);
#ifdef GLX_DIRECT_RENDERING
- if (gc-isDirect psc-driScreen psc-driScreen-setSwapInterval) {
+ if (gc-isDirect psc psc-driScreen
+ psc-driScreen-setSwapInterval) {
__GLXDRIdrawable *pdraw =
GetGLXDRIDrawable(gc-currentDpy, gc-currentDrawable);
psc-driScreen-setSwapInterval(pdraw, interval);
@@ -1796,7 +1808,7 @@ __glXSwapIntervalMESA(unsigned int interval)
struct glx_screen *psc;
psc = GetGLXScreenConfigs( gc-currentDpy, gc-screen);
- if (psc-driScreen psc-driScreen-setSwapInterval) {
+ if (psc psc-driScreen psc-driScreen-setSwapInterval) {
__GLXDRIdrawable *pdraw =
GetGLXDRIDrawable(gc-currentDpy, gc-currentDrawable);
return psc-driScreen-setSwapInterval(pdraw, interval);
@@ -1818,7 +1830,7 @@ __glXGetSwapIntervalMESA(void)
struct glx_screen *psc;
psc = GetGLXScreenConfigs( gc-currentDpy, gc-screen);
- if (psc-driScreen psc-driScreen-getSwapInterval) {
+ if (psc psc-driScreen psc-driScreen-getSwapInterval) {
__GLXDRIdrawable *pdraw =
GetGLXDRIDrawable(gc-currentDpy, gc-currentDrawable);
return psc-driScreen-getSwapInterval(pdraw);
@@ -1862,7 +1874,7 @@ __glXGetVideoSyncSGI(unsigned int *count)
* FIXME: documentation for the GLX encoding.
*/
#ifdef GLX_DIRECT_RENDERING
- if (psc-driScreen psc-driScreen-getDrawableMSC) {
+ if (psc psc-driScreen psc-driScreen-getDrawableMSC) {
ret = psc-driScreen-getDrawableMSC(psc, pdraw, ust, msc, sbc);
*count = (unsigned) msc;
return (ret == True) ? 0 : GLX_BAD_CONTEXT;
@@ -1900,7 +1912,7 @@ __glXWaitVideoSyncSGI(int divisor, int remainder,
unsigned int *count)
#endif
#ifdef GLX_DIRECT_RENDERING
- if (psc-driScreen psc-driScreen-waitForMSC) {
+ if (psc psc-driScreen psc-driScreen-waitForMSC) {
ret = psc-driScreen-waitForMSC(pdraw, 0, divisor, remainder, ust,
msc,
sbc);
*count = (unsigned) msc;
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Mesa (master): i965: Use the new brw_load_register_mem helper for draw indirect.
Module: Mesa
Branch: master
Commit: e990234ff6fd0f8d393cc600bf4dc681105cc30c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e990234ff6fd0f8d393cc600bf4dc681105cc30c
Author: Kenneth Graunke kenn...@whitecape.org
Date: Wed Jan 29 20:51:28 2014 -0800
i965: Use the new brw_load_register_mem helper for draw indirect.
This makes it work on Broadwell, too.
v2: Drop bogus double write to 3DPRIM_BASE_VERTEX register
(caught by Chris Forbes).
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_draw.c | 53 ++
1 file changed, 22 insertions(+), 31 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 39da953..484c4c1 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -217,42 +217,33 @@ static void brw_emit_prim(struct brw_context *brw,
indirect_flag = GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE;
- BEGIN_BATCH(15);
-
- OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
- OUT_BATCH(GEN7_3DPRIM_VERTEX_COUNT);
- OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0,
-prim-indirect_offset + 0);
- OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
- OUT_BATCH(GEN7_3DPRIM_INSTANCE_COUNT);
- OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0,
-prim-indirect_offset + 4);
- OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
- OUT_BATCH(GEN7_3DPRIM_START_VERTEX);
- OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0,
-prim-indirect_offset + 8);
-
+ brw_load_register_mem(brw, GEN7_3DPRIM_VERTEX_COUNT, bo,
+I915_GEM_DOMAIN_VERTEX, 0,
+prim-indirect_offset + 0);
+ brw_load_register_mem(brw, GEN7_3DPRIM_INSTANCE_COUNT, bo,
+I915_GEM_DOMAIN_VERTEX, 0,
+prim-indirect_offset + 4);
+
+ brw_load_register_mem(brw, GEN7_3DPRIM_START_VERTEX, bo,
+I915_GEM_DOMAIN_VERTEX, 0,
+prim-indirect_offset + 8);
if (prim-indexed) {
- OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
- OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX);
- OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0,
- prim-indirect_offset + 12);
- OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
- OUT_BATCH(GEN7_3DPRIM_START_INSTANCE);
- OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0,
- prim-indirect_offset + 16);
- }
- else {
- OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
- OUT_BATCH(GEN7_3DPRIM_START_INSTANCE);
- OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0,
- prim-indirect_offset + 12);
+ brw_load_register_mem(brw, GEN7_3DPRIM_BASE_VERTEX, bo,
+ I915_GEM_DOMAIN_VERTEX, 0,
+ prim-indirect_offset + 12);
+ brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
+ I915_GEM_DOMAIN_VERTEX, 0,
+ prim-indirect_offset + 16);
+ } else {
+ brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
+ I915_GEM_DOMAIN_VERTEX, 0,
+ prim-indirect_offset + 12);
+ BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX);
OUT_BATCH(0);
+ ADVANCE_BATCH();
}
-
- ADVANCE_BATCH();
}
else {
indirect_flag = 0;
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Mesa (master): i965: Implement a brw_load_register_mem helper function.
Module: Mesa
Branch: master
Commit: b7c435b26124464f18672acd17416ddd840d306b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7c435b26124464f18672acd17416ddd840d306b
Author: Kenneth Graunke kenn...@whitecape.org
Date: Wed Jan 29 20:43:49 2014 -0800
i965: Implement a brw_load_register_mem helper function.
This saves some boilerplate and hides the OUT_RELOC/OUT_RELOC64
distinction.
Placing the function in intel_batchbuffer.c is rather arbitrary; there
wasn't really an obvious place for it.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_context.h |7 +++
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 25 +
2 files changed, 32 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index bee39fa..98e90e2 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1575,6 +1575,13 @@ void brw_write_depth_count(struct brw_context *brw,
drm_intel_bo *bo, int idx);
void brw_store_register_mem64(struct brw_context *brw,
drm_intel_bo *bo, uint32_t reg, int idx);
+/** intel_batchbuffer.c */
+void brw_load_register_mem(struct brw_context *brw,
+ uint32_t reg,
+ drm_intel_bo *bo,
+ uint32_t read_domains, uint32_t write_domain,
+ uint32_t offset);
+
/*==
* brw_state_dump.c
*/
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index fbbd527..4624268 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -661,3 +661,28 @@ intel_batchbuffer_emit_mi_flush(struct brw_context *brw)
brw_emit_pipe_control_flush(brw, flags);
}
}
+
+void
+brw_load_register_mem(struct brw_context *brw,
+ uint32_t reg,
+ drm_intel_bo *bo,
+ uint32_t read_domains, uint32_t write_domain,
+ uint32_t offset)
+{
+ /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
+ assert(brw-gen = 7);
+
+ if (brw-gen = 8) {
+ BEGIN_BATCH(4);
+ OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (4 - 2));
+ OUT_BATCH(reg);
+ OUT_RELOC64(bo, read_domains, write_domain, offset);
+ ADVANCE_BATCH();
+ } else {
+ BEGIN_BATCH(3);
+ OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
+ OUT_BATCH(reg);
+ OUT_RELOC(bo, read_domains, write_domain, offset);
+ ADVANCE_BATCH();
+ }
+}
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Mesa (master): i965: Fix Gen8+ disassembly of half float subregister numbers.
Module: Mesa
Branch: master
Commit: 697f401a31092ee13fb7a9c3d8e5ba823d72072a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=697f401a31092ee13fb7a9c3d8e5ba823d72072a
Author: Kenneth Graunke kenn...@whitecape.org
Date: Wed Jan 29 14:12:51 2014 -0800
i965: Fix Gen8+ disassembly of half float subregister numbers.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/gen8_disasm.c |1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/gen8_disasm.c
b/src/mesa/drivers/dri/i965/gen8_disasm.c
index 0ea5e73..387bb71 100644
--- a/src/mesa/drivers/dri/i965/gen8_disasm.c
+++ b/src/mesa/drivers/dri/i965/gen8_disasm.c
@@ -176,6 +176,7 @@ static const int reg_type_size[] = {
[BRW_HW_REG_NON_IMM_TYPE_B] = 1,
[GEN7_HW_REG_NON_IMM_TYPE_DF] = 8,
[BRW_HW_REG_TYPE_F] = 4,
+ [GEN8_HW_REG_NON_IMM_TYPE_HF] = 2,
};
static const char *const m_reg_file[4] = {
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Mesa (master): i965: Fix INTEL_DEBUG=vs for fixed-function/ARB programs.
Module: Mesa
Branch: master
Commit: 2f97119950515c841bca98a890e5110206bad945
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f97119950515c841bca98a890e5110206bad945
Author: Kenneth Graunke kenn...@whitecape.org
Date: Mon Feb 3 11:13:48 2014 -0800
i965: Fix INTEL_DEBUG=vs for fixed-function/ARB programs.
Since commit 9cee3ff562f3e4b51bfd30338fd1ba7716ac5737, INTEL_DEBUG=vs
has caused a NULL pointer dereference for fixed-function/ARB programs.
In the vec4 generators, prog is a gl_program, and shader_prog is the
gl_shader_program. This is different than the FS visitor.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp |4 ++--
src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp |4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 94d1e79..e5ed2c2 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -1255,7 +1255,7 @@ vec4_generator::generate_code(exec_list *instructions)
const void *last_annotation_ir = NULL;
if (unlikely(debug_flag)) {
- if (prog) {
+ if (shader_prog) {
printf(Native code for vertex shader %d:\n, shader_prog-Name);
} else {
printf(Native code for vertex program %d:\n, prog-Id);
@@ -1271,7 +1271,7 @@ vec4_generator::generate_code(exec_list *instructions)
last_annotation_ir = inst-ir;
if (last_annotation_ir) {
printf( );
- if (prog) {
+ if (shader_prog) {
((ir_instruction *) last_annotation_ir)-print();
} else {
const prog_instruction *vpi;
diff --git a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
index 5a34858..03ed05a 100644
--- a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
@@ -782,7 +782,7 @@ gen8_vec4_generator::generate_code(exec_list *instructions)
const void *last_annotation_ir = NULL;
if (unlikely(debug_flag)) {
- if (prog) {
+ if (shader_prog) {
printf(Native code for vertex shader %d:\n, shader_prog-Name);
} else {
printf(Native code for vertex program %d:\n, prog-Id);
@@ -798,7 +798,7 @@ gen8_vec4_generator::generate_code(exec_list *instructions)
last_annotation_ir = ir-ir;
if (last_annotation_ir) {
printf( );
- if (prog) {
+ if (shader_prog) {
((ir_instruction *) last_annotation_ir)-print();
} else {
const prog_instruction *vpi;
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Mesa (master): glsl: Don't lose precision qualifiers when encountering centroid.
Module: Mesa
Branch: master
Commit: 2062f40d81de4743758851b03dad506f9cb6f306
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2062f40d81de4743758851b03dad506f9cb6f306
Author: Kenneth Graunke kenn...@whitecape.org
Date: Wed Feb 5 21:42:00 2014 -0800
glsl: Don't lose precision qualifiers when encountering centroid.
Mesa fails to retain the precision qualifier when parsing:
#version 300 es
centroid in mediump vec2 v;
Consider how the parser's type_qualifier production is applied.
First, the precision_qualifier rule creates a new ast_type_qualifier:
precision: mediump
Then the storage_qualifier rule creates a second one:
flags: in
and calls merge_qualifier() to fold in any previous qualifications,
returning:
flags: in, precision: mediump
Finally, the auxiliary_storage_qualifier creates one for centroid:
flags: centroid
it then does $$ = $1 and $$.flags |= $2.flags, resulting in:
flags: centroid, in
Since precision isn't stored in the flags bitfield, it is lost. We need
to instead call merge_qualifier to combine all the fields.
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reported-by: Kevin Rogovin kevin.rogo...@intel.com
Reviewed-by: Matt Turner matts...@gmail.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/glsl/glsl_parser.yy |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/glsl/glsl_parser.yy b/src/glsl/glsl_parser.yy
index b26c203..dc35c1a 100644
--- a/src/glsl/glsl_parser.yy
+++ b/src/glsl/glsl_parser.yy
@@ -1494,7 +1494,7 @@ type_qualifier:
just before storage qualifiers);
}
$$ = $1;
- $$.flags.i |= $2.flags.i;
+ $$.merge_qualifier(@1, state, $2);
}
| storage_qualifier type_qualifier
{
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Mesa (master): glsl: Optimize triop_csel with all-true or all-false.
Module: Mesa Branch: master Commit: 1e12dafcac4aac50bc588cead4cc0d6291718edd URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e12dafcac4aac50bc588cead4cc0d6291718edd Author: Eric Anholt e...@anholt.net Date: Fri Nov 1 12:29:12 2013 -0700 glsl: Optimize triop_csel with all-true or all-false. Reviewed-by: Matt Turner matts...@gmail.com --- src/glsl/opt_algebraic.cpp |7 +++ 1 file changed, 7 insertions(+) diff --git a/src/glsl/opt_algebraic.cpp b/src/glsl/opt_algebraic.cpp index 7863fe8..1b4d319 100644 --- a/src/glsl/opt_algebraic.cpp +++ b/src/glsl/opt_algebraic.cpp @@ -571,6 +571,13 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir) } break; + case ir_triop_csel: + if (is_vec_one(op_const[0])) +return ir-operands[1]; + if (is_vec_zero(op_const[0])) +return ir-operands[2]; + break; + default: break; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Remove redundant check in blitter-based glBlitFramebuffer().
Module: Mesa
Branch: master
Commit: b5e5f34dd2d47622a41ff9908088c37dfbcca4cd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5e5f34dd2d47622a41ff9908088c37dfbcca4cd
Author: Eric Anholt e...@anholt.net
Date: Mon Sep 30 15:19:54 2013 -0700
i965: Remove redundant check in blitter-based glBlitFramebuffer().
The intel_miptree_blit() code checks the format for us now, plus it
handles xrgb vs argb for us.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/intel_fbo.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers/dri/i965/intel_fbo.c
index d99f9a6..6180fc6 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -739,16 +739,6 @@ intel_blit_framebuffer_with_blitter(struct gl_context *ctx,
return mask;
}
- mesa_format src_format = _mesa_get_srgb_format_linear(src_rb-Format);
- mesa_format dst_format = _mesa_get_srgb_format_linear(dst_rb-Format);
- if (src_format != dst_format) {
-perf_debug(glBlitFramebuffer(): unsupported blit from %s to %s.
- Falling back to software rendering.\n,
- _mesa_get_format_name(src_format),
- _mesa_get_format_name(dst_format));
-return mask;
- }
-
if (!intel_miptree_blit(brw,
src_irb-mt,
src_irb-mt_level, src_irb-mt_layer,
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Mesa (master): glsl: Optimize ~~x into x.
Module: Mesa
Branch: master
Commit: 2c2aa353366c610382273bea10656e6d6960ce3b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c2aa353366c610382273bea10656e6d6960ce3b
Author: Eric Anholt e...@anholt.net
Date: Sat Jan 18 10:36:28 2014 -0800
glsl: Optimize ~~x into x.
v2: Fix pasteo of an extra abs being inserted (caught by many). Rewrite
to drop the silly switch statement.
Reviewed-by: Matt Turner matts...@gmail.com (v1)
---
src/glsl/opt_algebraic.cpp |5 +
1 file changed, 5 insertions(+)
diff --git a/src/glsl/opt_algebraic.cpp b/src/glsl/opt_algebraic.cpp
index d1f6435..681973d 100644
--- a/src/glsl/opt_algebraic.cpp
+++ b/src/glsl/opt_algebraic.cpp
@@ -218,6 +218,11 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir)
this-mem_ctx = ralloc_parent(ir);
switch (ir-operation) {
+ case ir_unop_bit_not:
+ if (op_expr[0] op_expr[0]-operation == ir_unop_bit_not)
+ return op_expr[0]-operands[0];
+ break;
+
case ir_unop_abs:
if (op_expr[0] == NULL)
break;
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Mesa (master): glsl: Optimize log(exp(x)) and exp(log(x)) into x.
Module: Mesa
Branch: master
Commit: 6d7c123d6ce46e71ef22e431b76e972b9be1a157
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d7c123d6ce46e71ef22e431b76e972b9be1a157
Author: Eric Anholt e...@anholt.net
Date: Sat Jan 18 10:47:19 2014 -0800
glsl: Optimize log(exp(x)) and exp(log(x)) into x.
Reviewed-by: Matt Turner matts...@gmail.com
---
src/glsl/opt_algebraic.cpp | 36
1 file changed, 36 insertions(+)
diff --git a/src/glsl/opt_algebraic.cpp b/src/glsl/opt_algebraic.cpp
index 681973d..1e71581 100644
--- a/src/glsl/opt_algebraic.cpp
+++ b/src/glsl/opt_algebraic.cpp
@@ -245,6 +245,42 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir)
}
break;
+ case ir_unop_exp:
+ if (op_expr[0] == NULL)
+break;
+
+ if (op_expr[0]-operation == ir_unop_log) {
+ return op_expr[0]-operands[0];
+ }
+ break;
+
+ case ir_unop_log:
+ if (op_expr[0] == NULL)
+break;
+
+ if (op_expr[0]-operation == ir_unop_exp) {
+ return op_expr[0]-operands[0];
+ }
+ break;
+
+ case ir_unop_exp2:
+ if (op_expr[0] == NULL)
+break;
+
+ if (op_expr[0]-operation == ir_unop_log2) {
+ return op_expr[0]-operands[0];
+ }
+ break;
+
+ case ir_unop_log2:
+ if (op_expr[0] == NULL)
+break;
+
+ if (op_expr[0]-operation == ir_unop_exp2) {
+ return op_expr[0]-operands[0];
+ }
+ break;
+
case ir_unop_logic_not: {
enum ir_expression_operation new_op = ir_unop_logic_not;
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Mesa (master): glsl: Optimize pow(x, 1) - x.
Module: Mesa Branch: master Commit: d72956790fed5f62b8eea5938ed432544530f7bd URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d72956790fed5f62b8eea5938ed432544530f7bd Author: Eric Anholt e...@anholt.net Date: Sat Jan 18 10:57:29 2014 -0800 glsl: Optimize pow(x, 1) - x. total instructions in shared programs: 1627826 - 1627754 (-0.00%) instructions in affected programs: 6640 - 6568 (-1.08%) GAINED:0 LOST: 0 (HoN and savage2) Reviewed-by: Matt Turner matts...@gmail.com --- src/glsl/opt_algebraic.cpp |4 1 file changed, 4 insertions(+) diff --git a/src/glsl/opt_algebraic.cpp b/src/glsl/opt_algebraic.cpp index 1e71581..953b03c 100644 --- a/src/glsl/opt_algebraic.cpp +++ b/src/glsl/opt_algebraic.cpp @@ -520,6 +520,10 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir) if (is_vec_one(op_const[0])) return op_const[0]; + /* x^1 == x */ + if (is_vec_one(op_const[1])) + return ir-operands[0]; + /* pow(2,x) == exp2(x) */ if (is_vec_two(op_const[0])) return expr(ir_unop_exp2, ir-operands[1]); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Add some informative debug when the X Server botches DRI2 GetBuffers.
Module: Mesa
Branch: master
Commit: 0f6279bab29614e3764a333242680ead78068d91
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f6279bab29614e3764a333242680ead78068d91
Author: Eric Anholt e...@anholt.net
Date: Mon Dec 30 18:19:21 2013 -0800
i965: Add some informative debug when the X Server botches DRI2 GetBuffers.
We've had various bug reports over the years where miptrees are missing,
and when I screwed it up while adding DRI2 to the modesetting driver, I
figured I should put the info necessary for debug here.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_context.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 6a3a4f1..1879abe 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1290,14 +1290,24 @@ intel_process_dri2_buffer(struct brw_context *brw,
buffer-pitch,
buffer-name,
buffer_name);
- if (!region)
+ if (!region) {
+ fprintf(stderr,
+ Failed to make region for returned DRI2 buffer
+ (%dx%d, named %d).\n
+ This is likely a bug in the X Server that will lead to a
+ crash soon.\n,
+ drawable-w, drawable-h, buffer-name);
return;
+ }
rb-mt = intel_miptree_create_for_dri2_buffer(brw,
buffer-attachment,
intel_rb_format(rb),
num_samples,
region);
+
+ assert(rb-mt);
+
intel_region_release(region);
}
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Mesa (master): glsl: Optimize lrp(x, x, coefficient) -- x.
Module: Mesa
Branch: master
Commit: 44577c48573acdbc8a708e6613f367507e9eafc5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=44577c48573acdbc8a708e6613f367507e9eafc5
Author: Eric Anholt e...@anholt.net
Date: Sat Jan 18 11:00:51 2014 -0800
glsl: Optimize lrp(x, x, coefficient) -- x.
total instructions in shared programs: 1627754 - 1624534 (-0.20%)
instructions in affected programs: 45748 - 42528 (-7.04%)
GAINED:3
LOST: 0
(serious sam, humus domino demo)
Reviewed-by: Matt Turner matts...@gmail.com
---
src/glsl/opt_algebraic.cpp |2 ++
1 file changed, 2 insertions(+)
diff --git a/src/glsl/opt_algebraic.cpp b/src/glsl/opt_algebraic.cpp
index 953b03c..392051f 100644
--- a/src/glsl/opt_algebraic.cpp
+++ b/src/glsl/opt_algebraic.cpp
@@ -553,6 +553,8 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir)
return ir-operands[0];
} else if (is_vec_one(op_const[2])) {
return ir-operands[1];
+ } else if (ir-operands[0]-equals(ir-operands[1])) {
+ return ir-operands[0];
}
break;
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Mesa (master): glsl: Optimize various cases of fma (aka MAD).
Module: Mesa
Branch: master
Commit: de796b0ef09f05ca3f8a568ed07293e28ae697b0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=de796b0ef09f05ca3f8a568ed07293e28ae697b0
Author: Eric Anholt e...@anholt.net
Date: Sat Jan 18 11:06:16 2014 -0800
glsl: Optimize various cases of fma (aka MAD).
Reviewed-by: Matt Turner matts...@gmail.com
---
src/glsl/opt_algebraic.cpp | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/glsl/opt_algebraic.cpp b/src/glsl/opt_algebraic.cpp
index 392051f..7863fe8 100644
--- a/src/glsl/opt_algebraic.cpp
+++ b/src/glsl/opt_algebraic.cpp
@@ -547,6 +547,19 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir)
break;
+ case ir_triop_fma:
+ /* Operands are op0 * op1 + op2. */
+ if (is_vec_zero(op_const[0]) || is_vec_zero(op_const[1])) {
+ return ir-operands[2];
+ } else if (is_vec_zero(op_const[2])) {
+ return mul(ir-operands[0], ir-operands[1]);
+ } else if (is_vec_one(op_const[0])) {
+ return add(ir-operands[1], ir-operands[2]);
+ } else if (is_vec_one(op_const[1])) {
+ return add(ir-operands[0], ir-operands[2]);
+ }
+ break;
+
case ir_triop_lrp:
/* Operands are (x, y, a). */
if (is_vec_zero(op_const[2])) {
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Mesa (master): i965/vec4: Emit shader w/a for Gen6 gather
Module: Mesa
Branch: master
Commit: 31d1077dd2f0fec34ac221168943cecc8c9afbf0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=31d1077dd2f0fec34ac221168943cecc8c9afbf0
Author: Chris Forbes chr...@ijw.co.nz
Date: Mon Feb 3 22:15:41 2014 +1300
i965/vec4: Emit shader w/a for Gen6 gather
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_vec4.h |1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 31
2 files changed, 32 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index e17b5cd..1cf74db 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -482,6 +482,7 @@ public:
uint32_t gather_channel(ir_texture *ir, int sampler);
src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, int sampler);
+ void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
void emit_ndc_computation();
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index aa5fb6a..5da043c 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -2499,10 +2499,41 @@ vec4_visitor::visit(ir_texture *ir)
}
}
+ if (brw-gen == 6 ir-op == ir_tg4) {
+ emit_gen6_gather_wa(key-tex.gen6_gather_wa[sampler], inst-dst);
+ }
+
swizzle_result(ir, src_reg(inst-dst), sampler);
}
/**
+ * Apply workarounds for Gen6 gather with UINT/SINT
+ */
+void
+vec4_visitor::emit_gen6_gather_wa(uint8_t wa, dst_reg dst)
+{
+ if (!wa)
+ return;
+
+ int width = (wa WA_8BIT) ? 8 : 16;
+ dst_reg dst_f = dst;
+ dst_f.type = BRW_REGISTER_TYPE_F;
+
+ /* Convert from UNORM to UINT */
+ emit(MUL(dst_f, src_reg(dst_f), src_reg((float)((1 width) - 1;
+ emit(MOV(dst, src_reg(dst_f)));
+
+ if (wa WA_SIGN) {
+ /* Reinterpret the UINT value as a signed INT value by
+ * shifting the sign bit into place, then shifting back
+ * preserving sign.
+ */
+ emit(SHL(dst, src_reg(dst), src_reg(32 - width)));
+ emit(ASR(dst, src_reg(dst), src_reg(32 - width)));
+ }
+}
+
+/**
* Set up the gather channel based on the swizzle, for gather4.
*/
uint32_t
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Mesa (master): i965: Add Gen6 gather wa to sampler key
Module: Mesa
Branch: master
Commit: 2b7bbd89e87c4025cfc5513a078b1e7a10640357
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b7bbd89e87c4025cfc5513a078b1e7a10640357
Author: Chris Forbes chr...@ijw.co.nz
Date: Mon Feb 3 22:13:03 2014 +1300
i965: Add Gen6 gather wa to sampler key
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_program.h | 11 +++
src/mesa/drivers/dri/i965/brw_wm.c | 21 +
2 files changed, 32 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_program.h
b/src/mesa/drivers/dri/i965/brw_program.h
index 51182ea..d7fbe9c 100644
--- a/src/mesa/drivers/dri/i965/brw_program.h
+++ b/src/mesa/drivers/dri/i965/brw_program.h
@@ -24,6 +24,12 @@
#ifndef BRW_PROGRAM_H
#define BRW_PROGRAM_H
+enum gen6_gather_sampler_wa {
+ WA_SIGN = 1, /* whether we need to sign extend */
+ WA_8BIT = 2, /* if we have an 8bit format needing wa */
+ WA_16BIT = 4, /* if we have a 16bit format needing wa */
+};
+
/**
* Sampler information needed by VS, WM, and GS program cache keys.
*/
@@ -50,6 +56,11 @@ struct brw_sampler_prog_key_data {
* Whether this sampler uses the compressed multisample surface layout.
*/
uint16_t compressed_multisample_layout_mask;
+
+ /**
+* For Sandybridge, which shader w/a we need for gather quirks.
+*/
+ uint8_t gen6_gather_wa[MAX_SAMPLERS];
};
#ifdef __cplusplus
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c
b/src/mesa/drivers/dri/i965/brw_wm.c
index a0758d2..7eccbcb 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -317,6 +317,20 @@ brw_wm_debug_recompile(struct brw_context *brw,
}
}
+static uint8_t
+gen6_gather_workaround(GLenum internalformat)
+{
+ switch (internalformat) {
+ case GL_R8I: return WA_SIGN | WA_8BIT;
+ case GL_R8UI: return WA_8BIT;
+ case GL_R16I: return WA_SIGN | WA_16BIT;
+ case GL_R16UI: return WA_16BIT;
+ /* note that even though GL_R32I and GL_R32UI have format overrides
+ * in the surface state, there is no shader w/a required */
+ default: return 0;
+ }
+}
+
void
brw_populate_sampler_prog_key_data(struct gl_context *ctx,
const struct gl_program *prog,
@@ -372,6 +386,13 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
key-gather_channel_quirk_mask |= 1 s;
}
+ /* Gen6's gather4 is broken for UINT/SINT; we treat them as
+ * UNORM/FLOAT instead and fix it in the shader.
+ */
+ if (brw-gen == 6 prog-UsesGather) {
+key-gen6_gather_wa[s] =
gen6_gather_workaround(img-InternalFormat);
+ }
+
/* If this is a multisample sampler, and uses the CMS MSAA layout,
* then we need to emit slightly different code to first sample the
* MCS surface.
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Mesa (master): i965/fs: Emit shader w/a for Gen6 gather
Module: Mesa
Branch: master
Commit: 73b91fe05a2b4a09b29c69cfefda3f6c3d0ea68c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=73b91fe05a2b4a09b29c69cfefda3f6c3d0ea68c
Author: Chris Forbes chr...@ijw.co.nz
Date: Mon Feb 3 22:15:16 2014 +1300
i965/fs: Emit shader w/a for Gen6 gather
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_fs.h |1 +
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 34 ++
2 files changed, 35 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 9c5c13a..3d668b9 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -360,6 +360,7 @@ public:
fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
fs_reg sample_index, fs_reg mcs, int sampler);
fs_reg emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, int sampler);
+ void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
fs_reg fix_math_operand(fs_reg src);
fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index d88d24c..fd0813c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1699,10 +1699,44 @@ fs_visitor::visit(ir_texture *ir)
}
}
+ if (brw-gen == 6 ir-op == ir_tg4) {
+ emit_gen6_gather_wa(c-key.tex.gen6_gather_wa[sampler], dst);
+ }
+
swizzle_result(ir, dst, sampler);
}
/**
+ * Apply workarounds for Gen6 gather with UINT/SINT
+ */
+void
+fs_visitor::emit_gen6_gather_wa(uint8_t wa, fs_reg dst)
+{
+ if (!wa)
+ return;
+
+ int width = (wa WA_8BIT) ? 8 : 16;
+
+ for (int i = 0; i 4; i++) {
+ fs_reg dst_f = dst.retype(BRW_REGISTER_TYPE_F);
+ /* Convert from UNORM to UINT */
+ emit(MUL(dst_f, dst_f, fs_reg((float)((1 width) - 1;
+ emit(MOV(dst, dst_f));
+
+ if (wa WA_SIGN) {
+ /* Reinterpret the UINT value as a signed INT value by
+ * shifting the sign bit into place, then shifting back
+ * preserving sign.
+ */
+ emit(SHL(dst, dst, fs_reg(32 - width)));
+ emit(ASR(dst, dst, fs_reg(32 - width)));
+ }
+
+ dst.reg_offset++;
+ }
+}
+
+/**
* Set up the gather channel based on the swizzle, for gather4.
*/
uint32_t
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Mesa (master): i965: Add surface format overrides for Gen6 gather
Module: Mesa
Branch: master
Commit: c2d51aaa11c2593edb9f4b9279745d39c79ff23c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2d51aaa11c2593edb9f4b9279745d39c79ff23c
Author: Chris Forbes chr...@ijw.co.nz
Date: Mon Feb 3 22:14:45 2014 +1300
i965: Add surface format overrides for Gen6 gather
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 37 +++---
1 file changed, 32 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index dd96c9b..d16953f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -282,15 +282,42 @@ brw_update_texture_surface(struct gl_context *ctx,
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
6 * 4, 32, surf_offset);
- (void) for_gather; /* no w/a to apply for this gen */
+ uint32_t tex_format = translate_tex_format(brw, mt-format,
+ sampler-sRGBDecode);
+
+ if (for_gather) {
+ /* Sandybridge's gather4 message is broken for integer formats.
+ * To work around this, we pretend the surface is UNORM for
+ * 8 or 16-bit formats, and emit shader instructions to recover
+ * the real INT/UINT value. For 32-bit formats, we pretend
+ * the surface is FLOAT, and simply reinterpret the resulting
+ * bits.
+ */
+ switch (tex_format) {
+ case BRW_SURFACEFORMAT_R8_SINT:
+ case BRW_SURFACEFORMAT_R8_UINT:
+ tex_format = BRW_SURFACEFORMAT_R8_UNORM;
+ break;
+
+ case BRW_SURFACEFORMAT_R16_SINT:
+ case BRW_SURFACEFORMAT_R16_UINT:
+ tex_format = BRW_SURFACEFORMAT_R16_UNORM;
+ break;
+
+ case BRW_SURFACEFORMAT_R32_SINT:
+ case BRW_SURFACEFORMAT_R32_UINT:
+ tex_format = BRW_SURFACEFORMAT_R32_FLOAT;
+ break;
+
+ default:
+ break;
+ }
+ }
surf[0] = (translate_tex_target(tObj-Target) BRW_SURFACE_TYPE_SHIFT |
BRW_SURFACE_MIPMAPLAYOUT_BELOW BRW_SURFACE_MIPLAYOUT_SHIFT |
BRW_SURFACE_CUBEFACE_ENABLES |
- (translate_tex_format(brw,
-mt-format,
- sampler-sRGBDecode)
- BRW_SURFACE_FORMAT_SHIFT));
+ tex_format BRW_SURFACE_FORMAT_SHIFT);
surf[1] = intelObj-mt-region-bo-offset64 + intelObj-mt-offset; /*
reloc */
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Mesa (master): i965: Enable ARB_texture_gather for one component on Gen6.
Module: Mesa
Branch: master
Commit: 0c14c5c62a1b4648381c05f024db730e4a0f90c5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c14c5c62a1b4648381c05f024db730e4a0f90c5
Author: Chris Forbes chr...@ijw.co.nz
Date: Sun Feb 2 22:00:18 2014 +1300
i965: Enable ARB_texture_gather for one component on Gen6.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_context.c |2 ++
src/mesa/drivers/dri/i965/intel_extensions.c |2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 1879abe..021287e 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -374,6 +374,8 @@ brw_initialize_context_constants(struct brw_context *brw)
if (brw-gen = 7)
ctx-Const.MaxProgramTextureGatherComponents = 4;
+ else if (brw-gen == 6)
+ ctx-Const.MaxProgramTextureGatherComponents = 1;
ctx-Const.MinLineWidth = 1.0;
ctx-Const.MinLineWidthAA = 1.0;
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index a0fd354..eb3f2c7 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -270,6 +270,7 @@ intelInitExtensions(struct gl_context *ctx)
ctx-Extensions.ARB_texture_multisample = true;
ctx-Extensions.ARB_sample_shading = true;
ctx-Extensions.ARB_vertex_type_10f_11f_11f_rev = true;
+ ctx-Extensions.ARB_texture_gather = true;
/* Test if the kernel has the ioctl. */
if (drm_intel_reg_read(brw-bufmgr, TIMESTAMP, dummy) == 0)
@@ -284,7 +285,6 @@ intelInitExtensions(struct gl_context *ctx)
}
if (brw-gen = 7) {
- ctx-Extensions.ARB_texture_gather = true;
ctx-Extensions.ARB_conservative_depth = true;
ctx-Extensions.AMD_vertex_shader_layer = true;
if (can_do_pipelined_register_writes(brw)) {
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Mesa (master): nvc0: create the SW object
Module: Mesa
Branch: master
Commit: dd2229d4c68ed78a50104637aef904f8ab6d7dd3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd2229d4c68ed78a50104637aef904f8ab6d7dd3
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Fri Feb 7 22:51:27 2014 +0100
nvc0: create the SW object
It's required for being able to use software methods now.
---
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c |9 +
src/gallium/drivers/nouveau/nvc0/nvc0_screen.h |1 +
2 files changed, 10 insertions(+)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 752d72b..6bf0a3a 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -361,6 +361,7 @@ nvc0_screen_destroy(struct pipe_screen *pscreen)
nouveau_object_del(screen-eng2d);
nouveau_object_del(screen-m2mf);
nouveau_object_del(screen-compute);
+ nouveau_object_del(screen-nvsw);
nouveau_screen_fini(screen-base);
@@ -597,6 +598,14 @@ nvc0_screen_create(struct nouveau_device *dev)
screen-base.fence.emit = nvc0_screen_fence_emit;
screen-base.fence.update = nvc0_screen_fence_update;
+
+ ret = nouveau_object_new(chan,
+(dev-chipset 0xe0) ? 0x1f906e : 0x906e, 0x906e,
+NULL, 0, screen-nvsw);
+ if (ret)
+ FAIL_SCREEN_INIT(Error creating SW object: %d\n, ret);
+
+
switch (dev-chipset ~0xf) {
case 0x100:
case 0xf0:
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
index 27a0c5f..c58add5 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
@@ -76,6 +76,7 @@ struct nvc0_screen {
struct nouveau_object *eng2d;
struct nouveau_object *m2mf;
struct nouveau_object *compute;
+ struct nouveau_object *nvsw;
};
static INLINE struct nvc0_screen *
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Mesa (master): nvc0/ir/emit: hardcode vertex output stream to 0 for now
Module: Mesa
Branch: master
Commit: b7233acf782a39c7e5643cb303022360664b6046
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7233acf782a39c7e5643cb303022360664b6046
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Fri Feb 7 22:39:44 2014 +0100
nvc0/ir/emit: hardcode vertex output stream to 0 for now
---
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp |9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index 96a4af4..f15ca1b 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -1488,8 +1488,13 @@ CodeEmitterNVC0::emitOUT(const Instruction *i)
// vertex stream
if (i-src(1).getFile() == FILE_IMMEDIATE) {
- code[1] |= 0xc000;
- code[0] |= SDATA(i-src(1)).u32 26;
+ // Using immediate encoding here triggers an invalid opcode error
+ // or random results when error reporting is disabled.
+ // TODO: figure this out when we get multiple vertex streams
+ assert(SDATA(i-src(1)).u32 == 0);
+ srcId(NULL, 26);
+ // code[1] |= 0xc000;
+ // code[0] |= SDATA(i-src(1)).u32 26;
} else {
srcId(i-src(1), 26);
}
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Mesa (master): nvc0: handle TGSI_SEMANTIC_LAYER
Module: Mesa
Branch: master
Commit: 882e98e5e6e63787d0eac572c461605e69fc1589
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=882e98e5e6e63787d0eac572c461605e69fc1589
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Fri Feb 7 23:04:43 2014 +0100
nvc0: handle TGSI_SEMANTIC_LAYER
Cc: 10.1 mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h|1 -
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp |2 +-
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp |2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_program.c |2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c|2 +-
5 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index 752bad3..f2f4ead 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -71,7 +71,6 @@ struct nv50_ir_varying
#define NV50_SEMANTIC_CLIPDISTANCE (TGSI_SEMANTIC_COUNT + 0)
#define NV50_SEMANTIC_VIEWPORTINDEX (TGSI_SEMANTIC_COUNT + 4)
-#define NV50_SEMANTIC_LAYER (TGSI_SEMANTIC_COUNT + 5)
#define NV50_SEMANTIC_INVOCATIONID (TGSI_SEMANTIC_COUNT + 6)
#define NV50_SEMANTIC_TESSFACTOR(TGSI_SEMANTIC_COUNT + 7)
#define NV50_SEMANTIC_TESSCOORD (TGSI_SEMANTIC_COUNT + 8)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index d7c06a4..78a6c83 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -861,8 +861,8 @@ int Source::inferSysValDirection(unsigned sn) const
case TGSI_SEMANTIC_INSTANCEID:
case TGSI_SEMANTIC_VERTEXID:
return 1;
-#if 0
case TGSI_SEMANTIC_LAYER:
+#if 0
case TGSI_SEMANTIC_VIEWPORTINDEX:
return 0;
#endif
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
index 636ef9e..de07646 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
@@ -532,7 +532,7 @@ recordLocation(uint16_t *locs, uint8_t *masks,
case TGSI_SEMANTIC_INSTANCEID: locs[SV_INSTANCE_ID] = addr; break;
case TGSI_SEMANTIC_VERTEXID: locs[SV_VERTEX_ID] = addr; break;
case TGSI_SEMANTIC_PRIMID: locs[SV_PRIMITIVE_ID] = addr; break;
- case NV50_SEMANTIC_LAYER: locs[SV_LAYER] = addr; break;
+ case TGSI_SEMANTIC_LAYER: locs[SV_LAYER] = addr; break;
case NV50_SEMANTIC_VIEWPORTINDEX: locs[SV_VIEWPORT_INDEX] = addr; break;
default:
break;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index 71deb34..1e7f7d2 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -64,7 +64,7 @@ nvc0_shader_output_address(unsigned sn, unsigned si, unsigned
ubase)
switch (sn) {
case NV50_SEMANTIC_TESSFACTOR:return 0x000 + si * 0x4;
case TGSI_SEMANTIC_PRIMID:return 0x060;
- case NV50_SEMANTIC_LAYER: return 0x064;
+ case TGSI_SEMANTIC_LAYER: return 0x064;
case NV50_SEMANTIC_VIEWPORTINDEX: return 0x068;
case TGSI_SEMANTIC_PSIZE: return 0x06c;
case TGSI_SEMANTIC_POSITION: return 0x070;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
index b820ef2..a52fed0 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
@@ -190,7 +190,7 @@ nvc0_gmtyprog_validate(struct nvc0_context *nvc0)
/* we allow GPs with no code for specifying stream output state only */
if (gp gp-code_size) {
- const boolean gp_selects_layer = gp-hdr[13] (1 9);
+ const boolean gp_selects_layer = !!(gp-hdr[13] (1 9));
BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
PUSH_DATA (push, 0x41);
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Mesa (10.1): glsl: Initialize ubo_binding_mask flags to zero.
Module: Mesa Branch: 10.1 Commit: 7aa84761b6afce722c4a1ad94cdbcf4282f3b7ad URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7aa84761b6afce722c4a1ad94cdbcf4282f3b7ad Author: Matt Turner matts...@gmail.com Date: Mon Feb 3 11:51:51 2014 -0800 glsl: Initialize ubo_binding_mask flags to zero. Missed in commit e63bb298. Caused sporadic test failures, like incorrect-in-layout-qualifier-repeated-prim.geom. Cc: 10.0 mesa-sta...@lists.freedesktop.org Reviewed-by: Kenneth Graunke kenn...@whitecape.org Reviewed-by: Jordan Justen jordan.l.jus...@intel.com (cherry picked from commit e2ef93cf94ee553e5de70a7c26fd0724d967d0b2) --- src/glsl/ast_type.cpp |1 + 1 file changed, 1 insertion(+) diff --git a/src/glsl/ast_type.cpp b/src/glsl/ast_type.cpp index 637da0d..5069326 100644 --- a/src/glsl/ast_type.cpp +++ b/src/glsl/ast_type.cpp @@ -118,6 +118,7 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc, ubo_layout_mask.flags.q.shared = 1; ast_type_qualifier ubo_binding_mask; + ubo_binding_mask.flags.i = 0; ubo_binding_mask.flags.q.explicit_binding = 1; ubo_binding_mask.flags.q.explicit_offset = 1; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (10.1): draw: fix incorrect color of flat-shaded clipped lines
Module: Mesa
Branch: 10.1
Commit: 6cfcc4fccffdfcfadcafb9c97618ad79e3bbd353
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6cfcc4fccffdfcfadcafb9c97618ad79e3bbd353
Author: Brian Paul bri...@vmware.com
Date: Mon Feb 3 11:33:03 2014 -0700
draw: fix incorrect color of flat-shaded clipped lines
When we clipped a line weren't copying the provoking vertex
color to the second vertex. We also weren't checking for
first vs. last provoking vertex.
Fixes failures found with the new piglit line-flat-clip-color test.
Cc: 10.0, 10.1 mesa-sta...@lists.freedesktop.org
Reviewed-by: Jose Fonseca jfons...@vmware.com
(cherry picked from commit fc3fcd1e01093e8ab8d06d95c53f875ace57ca7f)
---
src/gallium/auxiliary/draw/draw_pipe_clip.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/draw/draw_pipe_clip.c
b/src/gallium/auxiliary/draw/draw_pipe_clip.c
index de354e9..d8b56de 100644
--- a/src/gallium/auxiliary/draw/draw_pipe_clip.c
+++ b/src/gallium/auxiliary/draw/draw_pipe_clip.c
@@ -588,7 +588,12 @@ do_clip_line( struct draw_stage *stage,
if (v0-clipmask) {
interp( clipper, stage-tmp[0], t0, v0, v1, viewport_index );
- copy_flat(stage, stage-tmp[0], v0);
+ if (stage-draw-rasterizer-flatshade_first) {
+ copy_flat(stage, stage-tmp[0], v0); /* copy v0 color to tmp[0] */
+ }
+ else {
+ copy_flat(stage, stage-tmp[0], v1); /* copy v1 color to tmp[0] */
+ }
newprim.v[0] = stage-tmp[0];
}
else {
@@ -597,6 +602,12 @@ do_clip_line( struct draw_stage *stage,
if (v1-clipmask) {
interp( clipper, stage-tmp[1], t1, v1, v0, viewport_index );
+ if (stage-draw-rasterizer-flatshade_first) {
+ copy_flat(stage, stage-tmp[1], v0); /* copy v0 color to tmp[1] */
+ }
+ else {
+ copy_flat(stage, stage-tmp[1], v1); /* copy v1 color to tmp[1] */
+ }
newprim.v[1] = stage-tmp[1];
}
else {
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Mesa (10.1): st/mesa: avoid sw fallback for getting/decompressing textures
Module: Mesa
Branch: 10.1
Commit: 0fb761b404c01e3c026d4774f667ac968a965ccf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0fb761b404c01e3c026d4774f667ac968a965ccf
Author: Brian Paul bri...@vmware.com
Date: Fri Feb 7 09:32:05 2014 -0700
st/mesa: avoid sw fallback for getting/decompressing textures
If st_GetTexImage() is to decompress the texture, avoid the fallback
path even if prefer_blit_based_texture_transfer = false. For drivers
that returned PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER = 0, we
were always taking the fallback path for texture decompression rather
than rendering a quad. The later is a lot faster.
Cc: 10.0 10.1 mesa-sta...@lists.freedesktop.org
Reviewed-by: Marek Olšák marek.ol...@amd.com
(cherry picked from commit f47e5962885d9f7de23a8c9c9ba035017e24ffd6)
---
src/mesa/state_tracker/st_cb_texture.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st_cb_texture.c
b/src/mesa/state_tracker/st_cb_texture.c
index 824a13e..f0bf374 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -865,7 +865,9 @@ st_GetTexImage(struct gl_context * ctx,
ubyte *map = NULL;
boolean done = FALSE;
- if (!st-prefer_blit_based_texture_transfer) {
+ if (!st-prefer_blit_based_texture_transfer
+ !_mesa_is_format_compressed(texImage-TexFormat)) {
+ /* Try to avoid the fallback if we're doing texture decompression here */
goto fallback;
}
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Mesa (10.1): glx: Pass NULL DRI drawables into the DRI driver for None GLX drawables
Module: Mesa
Branch: 10.1
Commit: 70e8ec38b55e71144ce3ed055e7da30c330c716b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=70e8ec38b55e71144ce3ed055e7da30c330c716b
Author: Kristian Høgsberg k...@bitplanet.net
Date: Wed Feb 5 11:43:58 2014 -0800
glx: Pass NULL DRI drawables into the DRI driver for None GLX drawables
GLX_ARB_create_context allows making a GLX context current with None
drawable and readables, but this was never implemented correctly in GLX.
We would create a __DRIdrawable for the None GLX drawable and pass that
to the DRI driver and that would somehow work. Now it's somehow broken.
The way this should have worked is that we pass a NULL DRI drawable
to the DRI driver when the GLX user calls glXMakeContextCurrent()
with None for drawable and readables.
https://bugs.freedesktop.org/show_bug.cgi?id=74143
Signed-off-by: Kristian Høgsberg k...@bitplanet.net
(cherry picked from commit f658150639c36eda351590e757247c56507f494f)
---
src/glx/dri2_glx.c | 17 -
src/glx/dri_common.c |3 +++
2 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/src/glx/dri2_glx.c b/src/glx/dri2_glx.c
index 0a0dac9..67fe9c1 100644
--- a/src/glx/dri2_glx.c
+++ b/src/glx/dri2_glx.c
@@ -141,6 +141,7 @@ dri2_bind_context(struct glx_context *context, struct
glx_context *old,
struct dri2_context *pcp = (struct dri2_context *) context;
struct dri2_screen *psc = (struct dri2_screen *) pcp-base.psc;
struct dri2_drawable *pdraw, *pread;
+ __DRIdrawable *dri_draw = NULL, *dri_read = NULL;
struct dri2_display *pdp;
pdraw = (struct dri2_drawable *) driFetchDrawable(context, draw);
@@ -148,20 +149,26 @@ dri2_bind_context(struct glx_context *context, struct
glx_context *old,
driReleaseDrawables(pcp-base);
- if (pdraw == NULL || pread == NULL)
+ if (pdraw)
+ dri_draw = pdraw-driDrawable;
+ else if (draw != None)
return GLXBadDrawable;
- if (!(*psc-core-bindContext) (pcp-driContext,
- pdraw-driDrawable, pread-driDrawable))
+ if (pread)
+ dri_read = pread-driDrawable;
+ else if (read != None)
+ return GLXBadDrawable;
+
+ if (!(*psc-core-bindContext) (pcp-driContext, dri_draw, dri_read))
return GLXBadContext;
/* If the server doesn't send invalidate events, we may miss a
* resize before the rendering starts. Invalidate the buffers now
* so the driver will recheck before rendering starts. */
pdp = (struct dri2_display *) psc-base.display;
- if (!pdp-invalidateAvailable) {
+ if (!pdp-invalidateAvailable pdraw) {
dri2InvalidateBuffers(psc-base.dpy, pdraw-base.xDrawable);
- if (pread != pdraw)
+ if (pread != pdraw pread)
dri2InvalidateBuffers(psc-base.dpy, pread-base.xDrawable);
}
diff --git a/src/glx/dri_common.c b/src/glx/dri_common.c
index 0dd8982..012c8f4 100644
--- a/src/glx/dri_common.c
+++ b/src/glx/dri_common.c
@@ -392,6 +392,9 @@ driFetchDrawable(struct glx_context *gc, GLXDrawable
glxDrawable)
if (priv == NULL)
return NULL;
+ if (glxDrawable == None)
+ return NULL;
+
psc = priv-screens[gc-screen];
if (priv-drawHash == NULL)
return NULL;
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Mesa (10.1): gallium/auxiliary/indices: replace free() with FREE()
Module: Mesa
Branch: 10.1
Commit: 39a3b0313b10e9d60f36e50c3f60f5071094bd8d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=39a3b0313b10e9d60f36e50c3f60f5071094bd8d
Author: Brian Paul bri...@vmware.com
Date: Fri Jan 31 17:27:04 2014 -0700
gallium/auxiliary/indices: replace free() with FREE()
To match the CALLOC_STRUCT() call.
Cc: 10.0, 10.1 mesa-sta...@lists.freedesktop.org
Reviewed-by: Jose Fonseca jfons...@vmware.com
(cherry picked from commit 307fd76053da39242ada2701b0d32b2177fe3493)
---
src/gallium/auxiliary/indices/u_primconvert.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/indices/u_primconvert.c
b/src/gallium/auxiliary/indices/u_primconvert.c
index 14da7a6..f2a77ce 100644
--- a/src/gallium/auxiliary/indices/u_primconvert.c
+++ b/src/gallium/auxiliary/indices/u_primconvert.c
@@ -74,7 +74,7 @@ void
util_primconvert_destroy(struct primconvert_context *pc)
{
util_primconvert_save_index_buffer(pc, NULL);
- free(pc);
+ FREE(pc);
}
void
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Mesa (10.1): nvc0: handle TGSI_SEMANTIC_LAYER
Module: Mesa
Branch: 10.1
Commit: 137a0fe5c805364e0b380e92323fbe0557950011
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=137a0fe5c805364e0b380e92323fbe0557950011
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Fri Feb 7 23:04:43 2014 +0100
nvc0: handle TGSI_SEMANTIC_LAYER
Cc: 10.1 mesa-sta...@lists.freedesktop.org
(cherry picked from commit 882e98e5e6e63787d0eac572c461605e69fc1589)
---
src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h|1 -
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp |2 +-
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp |2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_program.c |2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c|2 +-
5 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index 752bad3..f2f4ead 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -71,7 +71,6 @@ struct nv50_ir_varying
#define NV50_SEMANTIC_CLIPDISTANCE (TGSI_SEMANTIC_COUNT + 0)
#define NV50_SEMANTIC_VIEWPORTINDEX (TGSI_SEMANTIC_COUNT + 4)
-#define NV50_SEMANTIC_LAYER (TGSI_SEMANTIC_COUNT + 5)
#define NV50_SEMANTIC_INVOCATIONID (TGSI_SEMANTIC_COUNT + 6)
#define NV50_SEMANTIC_TESSFACTOR(TGSI_SEMANTIC_COUNT + 7)
#define NV50_SEMANTIC_TESSCOORD (TGSI_SEMANTIC_COUNT + 8)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 33ebb54..8d5b26c 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -861,8 +861,8 @@ int Source::inferSysValDirection(unsigned sn) const
case TGSI_SEMANTIC_INSTANCEID:
case TGSI_SEMANTIC_VERTEXID:
return 1;
-#if 0
case TGSI_SEMANTIC_LAYER:
+#if 0
case TGSI_SEMANTIC_VIEWPORTINDEX:
return 0;
#endif
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
index 636ef9e..de07646 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
@@ -532,7 +532,7 @@ recordLocation(uint16_t *locs, uint8_t *masks,
case TGSI_SEMANTIC_INSTANCEID: locs[SV_INSTANCE_ID] = addr; break;
case TGSI_SEMANTIC_VERTEXID: locs[SV_VERTEX_ID] = addr; break;
case TGSI_SEMANTIC_PRIMID: locs[SV_PRIMITIVE_ID] = addr; break;
- case NV50_SEMANTIC_LAYER: locs[SV_LAYER] = addr; break;
+ case TGSI_SEMANTIC_LAYER: locs[SV_LAYER] = addr; break;
case NV50_SEMANTIC_VIEWPORTINDEX: locs[SV_VIEWPORT_INDEX] = addr; break;
default:
break;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index 71deb34..1e7f7d2 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -64,7 +64,7 @@ nvc0_shader_output_address(unsigned sn, unsigned si, unsigned
ubase)
switch (sn) {
case NV50_SEMANTIC_TESSFACTOR:return 0x000 + si * 0x4;
case TGSI_SEMANTIC_PRIMID:return 0x060;
- case NV50_SEMANTIC_LAYER: return 0x064;
+ case TGSI_SEMANTIC_LAYER: return 0x064;
case NV50_SEMANTIC_VIEWPORTINDEX: return 0x068;
case TGSI_SEMANTIC_PSIZE: return 0x06c;
case TGSI_SEMANTIC_POSITION: return 0x070;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
index b820ef2..a52fed0 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
@@ -190,7 +190,7 @@ nvc0_gmtyprog_validate(struct nvc0_context *nvc0)
/* we allow GPs with no code for specifying stream output state only */
if (gp gp-code_size) {
- const boolean gp_selects_layer = gp-hdr[13] (1 9);
+ const boolean gp_selects_layer = !!(gp-hdr[13] (1 9));
BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
PUSH_DATA (push, 0x41);
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Mesa (10.1): radeon/uvd: fix feedback buffer handling v2
Module: Mesa
Branch: 10.1
Commit: bbcd97588138d5008b962e57d950f4633ed6e5c5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bbcd97588138d5008b962e57d950f4633ed6e5c5
Author: Christian König christian.koe...@amd.com
Date: Mon Feb 3 02:28:58 2014 -0700
radeon/uvd: fix feedback buffer handling v2
Without the correct feedback buffer size UVD runs
into an error on each frame, reducing the maximum FPS.
v2: fixing Michels comments
Signed-off-by: Christian König christian.koe...@amd.com
Reviewed-by: Michel Dänzer michel.daen...@amd.com
Cc: 10.1 10.0 9.2 mesa-sta...@lists.freedesktop.org
(cherry picked from commit c3c24c3accd1401cbe96098e44850bb1130d80b9)
---
src/gallium/drivers/radeon/radeon_uvd.c | 40 +--
1 file changed, 28 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c
b/src/gallium/drivers/radeon/radeon_uvd.c
index 95757e3..e88c45c 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -58,6 +58,9 @@
#define NUM_H264_REFS 17
#define NUM_VC1_REFS 5
+#define FB_BUFFER_OFFSET 0x1000
+#define FB_BUFFER_SIZE 2048
+
/* UVD buffer representation */
struct ruvd_buffer
{
@@ -81,6 +84,7 @@ struct ruvd_decoder {
struct ruvd_buffer msg_fb_buffers[NUM_BUFFERS];
struct ruvd_msg *msg;
+ uint32_t*fb;
struct ruvd_buffer bs_buffers[NUM_BUFFERS];
void* bs_ptr;
@@ -131,16 +135,21 @@ static void send_cmd(struct ruvd_decoder *dec, unsigned
cmd,
set_reg(dec, RUVD_GPCOM_VCPU_CMD, cmd 1);
}
-/* map the next available message buffer */
-static void map_msg_buf(struct ruvd_decoder *dec)
+/* map the next available message/feedback buffer */
+static void map_msg_fb_buf(struct ruvd_decoder *dec)
{
struct ruvd_buffer* buf;
+ uint8_t *ptr;
- /* grap the current message buffer */
+ /* grab the current message/feedback buffer */
buf = dec-msg_fb_buffers[dec-cur_buffer];
- /* copy the message into it */
- dec-msg = dec-ws-buffer_map(buf-cs_handle, dec-cs,
PIPE_TRANSFER_WRITE);
+ /* and map it for CPU access */
+ ptr = dec-ws-buffer_map(buf-cs_handle, dec-cs, PIPE_TRANSFER_WRITE);
+
+ /* calc buffer offsets */
+ dec-msg = (struct ruvd_msg *)ptr;
+ dec-fb = (uint32_t *)(ptr + FB_BUFFER_OFFSET);
}
/* unmap and send a message command to the VCPU */
@@ -148,8 +157,8 @@ static void send_msg_buf(struct ruvd_decoder *dec)
{
struct ruvd_buffer* buf;
- /* ignore the request if message buffer isn't mapped */
- if (!dec-msg)
+ /* ignore the request if message/feedback buffer isn't mapped */
+ if (!dec-msg || !dec-fb)
return;
/* grap the current message buffer */
@@ -157,6 +166,8 @@ static void send_msg_buf(struct ruvd_decoder *dec)
/* unmap the buffer */
dec-ws-buffer_unmap(buf-cs_handle);
+ dec-msg = NULL;
+ dec-fb = NULL;
/* and send it to the hardware */
send_cmd(dec, RUVD_CMD_MSG_BUFFER, buf-cs_handle, 0,
@@ -644,7 +655,7 @@ static void ruvd_destroy(struct pipe_video_codec *decoder)
assert(decoder);
- map_msg_buf(dec);
+ map_msg_fb_buf(dec);
memset(dec-msg, 0, sizeof(*dec-msg));
dec-msg-size = sizeof(*dec-msg);
dec-msg-msg_type = RUVD_MSG_DESTROY;
@@ -773,7 +784,7 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder,
memset(dec-bs_ptr, 0, bs_size - dec-bs_size);
dec-ws-buffer_unmap(bs_buf-cs_handle);
- map_msg_buf(dec);
+ map_msg_fb_buf(dec);
dec-msg-size = sizeof(*dec-msg);
dec-msg-msg_type = RUVD_MSG_DECODE;
dec-msg-stream_handle = dec-stream_handle;
@@ -813,6 +824,10 @@ static void ruvd_end_frame(struct pipe_video_codec
*decoder,
dec-msg-body.decode.db_surf_tile_config =
dec-msg-body.decode.dt_surf_tile_config;
dec-msg-body.decode.extension_support = 0x1;
+
+ /* set at least the feedback buffer size */
+ dec-fb[0] = FB_BUFFER_SIZE;
+
send_msg_buf(dec);
send_cmd(dec, RUVD_CMD_DPB_BUFFER, dec-dpb.cs_handle, 0,
@@ -822,7 +837,7 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder,
send_cmd(dec, RUVD_CMD_DECODING_TARGET_BUFFER, dt, 0,
RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
send_cmd(dec, RUVD_CMD_FEEDBACK_BUFFER, msg_fb_buf-cs_handle,
-0x1000, RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
+FB_BUFFER_OFFSET, RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
set_reg(dec, RUVD_ENGINE_CNTL, 1);
flush(dec);
@@ -898,7 +913,8 @@ struct pipe_video_codec *ruvd_create_decoder(struct
pipe_context *context,
bs_buf_size = width * height * 512 / (16 * 16);
for (i = 0; i NUM_BUFFERS; ++i) {
- unsigned msg_fb_size =
Mesa (10.1): glsl: Don't lose precision qualifiers when encountering centroid.
Module: Mesa
Branch: 10.1
Commit: ecaf9259e92b22f5f219fc050337336abae642fb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ecaf9259e92b22f5f219fc050337336abae642fb
Author: Kenneth Graunke kenn...@whitecape.org
Date: Wed Feb 5 21:42:00 2014 -0800
glsl: Don't lose precision qualifiers when encountering centroid.
Mesa fails to retain the precision qualifier when parsing:
#version 300 es
centroid in mediump vec2 v;
Consider how the parser's type_qualifier production is applied.
First, the precision_qualifier rule creates a new ast_type_qualifier:
precision: mediump
Then the storage_qualifier rule creates a second one:
flags: in
and calls merge_qualifier() to fold in any previous qualifications,
returning:
flags: in, precision: mediump
Finally, the auxiliary_storage_qualifier creates one for centroid:
flags: centroid
it then does $$ = $1 and $$.flags |= $2.flags, resulting in:
flags: centroid, in
Since precision isn't stored in the flags bitfield, it is lost. We need
to instead call merge_qualifier to combine all the fields.
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reported-by: Kevin Rogovin kevin.rogo...@intel.com
Reviewed-by: Matt Turner matts...@gmail.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
(cherry picked from commit 2062f40d81de4743758851b03dad506f9cb6f306)
---
src/glsl/glsl_parser.yy |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/glsl/glsl_parser.yy b/src/glsl/glsl_parser.yy
index 928c57e..f939fe8 100644
--- a/src/glsl/glsl_parser.yy
+++ b/src/glsl/glsl_parser.yy
@@ -1466,7 +1466,7 @@ type_qualifier:
just before storage qualifiers);
}
$$ = $1;
- $$.flags.i |= $2.flags.i;
+ $$.merge_qualifier(@1, state, $2);
}
| storage_qualifier type_qualifier
{
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Mesa (10.1): glsl: Make condition_to_hir() callable from outside ast_iteration_statement.
Module: Mesa
Branch: 10.1
Commit: b5c99be4af84b47ffec5750da8a9a455c63ddd8b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5c99be4af84b47ffec5750da8a9a455c63ddd8b
Author: Paul Berry stereotype...@gmail.com
Date: Fri Jan 31 09:50:37 2014 -0800
glsl: Make condition_to_hir() callable from outside ast_iteration_statement.
In addition to making it public, we also need to change its first
argument from an ir_loop * to an exec_list *, so that it can be used
to insert the condition anywhere in the IR (rather than just in the
body of the loop).
This will be necessary in order to make continue statements work
properly in do-while loops.
Cc: mesa-sta...@lists.freedesktop.org
Acked-by: Carl Worth cwo...@cworth.org
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Matt Turner matts...@gmail.com
(cherry picked from commit 56790856b303ad5ba86d7eb261ade91edaa3ee0b)
---
src/glsl/ast.h |3 +--
src/glsl/ast_to_hir.cpp | 10 +-
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/src/glsl/ast.h b/src/glsl/ast.h
index 0bda28d..2d6f3a2 100644
--- a/src/glsl/ast.h
+++ b/src/glsl/ast.h
@@ -888,14 +888,13 @@ public:
ast_node *body;
-private:
/**
* Generate IR from the condition of a loop
*
* This is factored out of ::hir because some loops have the condition
* test at the top (for and while), and others have it at the end
(do-while).
*/
- void condition_to_hir(class ir_loop *, struct _mesa_glsl_parse_state *);
+ void condition_to_hir(exec_list *, struct _mesa_glsl_parse_state *);
};
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 1bfb4e5..950f513 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -4369,14 +4369,14 @@ ast_case_label::hir(exec_list *instructions,
}
void
-ast_iteration_statement::condition_to_hir(ir_loop *stmt,
+ast_iteration_statement::condition_to_hir(exec_list *instructions,
struct _mesa_glsl_parse_state *state)
{
void *ctx = state;
if (condition != NULL) {
ir_rvalue *const cond =
-condition-hir( stmt-body_instructions, state);
+condition-hir(instructions, state);
if ((cond == NULL)
|| !cond-type-is_boolean() || !cond-type-is_scalar()) {
@@ -4397,7 +4397,7 @@ ast_iteration_statement::condition_to_hir(ir_loop *stmt,
new(ctx) ir_loop_jump(ir_loop_jump::jump_break);
if_stmt-then_instructions.push_tail(break_stmt);
-stmt-body_instructions.push_tail(if_stmt);
+instructions-push_tail(if_stmt);
}
}
}
@@ -4432,7 +4432,7 @@ ast_iteration_statement::hir(exec_list *instructions,
state-switch_state.is_switch_innermost = false;
if (mode != ast_do_while)
- condition_to_hir(stmt, state);
+ condition_to_hir(stmt-body_instructions, state);
if (body != NULL)
body-hir( stmt-body_instructions, state);
@@ -4441,7 +4441,7 @@ ast_iteration_statement::hir(exec_list *instructions,
rest_expression-hir( stmt-body_instructions, state);
if (mode == ast_do_while)
- condition_to_hir(stmt, state);
+ condition_to_hir(stmt-body_instructions, state);
if (mode != ast_do_while)
state-symbols-pop_scope();
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Mesa (10.1): i965: Move intel_prepare_render() above first buffer access
Module: Mesa
Branch: 10.1
Commit: c79a7ef9a3d86116f8b8775d1f1960ef179198eb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c79a7ef9a3d86116f8b8775d1f1960ef179198eb
Author: Kristian Høgsberg k...@bitplanet.net
Date: Wed Feb 5 10:59:02 2014 -0800
i965: Move intel_prepare_render() above first buffer access
The driver is supposed to ensure buffers before any drawing operation, but in
do_blit_drawpixels() and do_blit_copypixels() we inspect the buffer format
before calling intel_prepare_render(). That was covered up by the
unconditional call to intel_prepare_render() in intelMakeCurrent(), but we
now only do this on the initial intelMakeCurrent call for a context
(to get the size for the initial viewport values).
https://bugs.freedesktop.org/show_bug.cgi?id=74083
Signed-off-by: Kristian Høgsberg k...@bitplanet.net
Tested-by: Alexander Monakov amona...@gmail.com
(cherry picked from commit 44338cd826623ae0675861015a56c528261f3fd3)
---
src/mesa/drivers/dri/i965/intel_pixel_copy.c |4 ++--
src/mesa/drivers/dri/i965/intel_pixel_draw.c |4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_copy.c
b/src/mesa/drivers/dri/i965/intel_pixel_copy.c
index b2795c6..486e308 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_copy.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_copy.c
@@ -66,6 +66,8 @@ do_blit_copypixels(struct gl_context * ctx,
/* Update draw buffer bounds */
_mesa_update_state(ctx);
+ intel_prepare_render(brw);
+
switch (type) {
case GL_COLOR:
if (fb-_NumColorDrawBuffers != 1) {
@@ -148,8 +150,6 @@ do_blit_copypixels(struct gl_context * ctx,
return false;
}
- intel_prepare_render(brw);
-
intel_batchbuffer_flush(brw);
/* Clip to destination buffer. */
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_draw.c
b/src/mesa/drivers/dri/i965/intel_pixel_draw.c
index a09c139..2925b63 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_draw.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_draw.c
@@ -72,6 +72,8 @@ do_blit_drawpixels(struct gl_context * ctx,
return false;
}
+ intel_prepare_render(brw);
+
struct gl_renderbuffer *rb = ctx-DrawBuffer-_ColorDrawBuffers[0];
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
@@ -101,8 +103,6 @@ do_blit_drawpixels(struct gl_context * ctx,
src_offset += _mesa_image_offset(2, unpack, width, height,
format, type, 0, 0, 0);
- intel_prepare_render(brw);
-
src_buffer = intel_bufferobj_buffer(brw, src,
src_offset, width * height *
irb-mt-cpp);
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Mesa (10.1): i965/blorp: do not use unnecessary hw-blending support
Module: Mesa
Branch: 10.1
Commit: 165868d45ebb5ed34e229788d70fe8cf129f9ddd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=165868d45ebb5ed34e229788d70fe8cf129f9ddd
Author: Topi Pohjolainen topi.pohjolai...@intel.com
Date: Mon Jan 27 10:50:01 2014 +0200
i965/blorp: do not use unnecessary hw-blending support
This is really not needed as blorp blit programs already sample
XRGB normally and get alpha channel set to 1.0 automatically by
the sampler engine. This is simply copied directly to the payload
of the render target write message and hence there is no need for
any additional blending support from the pixel processing pipeline.
The blending formula is anyway broken for color components, it
multiplies the color component with itself (blend factor is the
component itself).
Alpha blending in turn would not fix the alpha to one independent
of the source but simply used the source alpha as is instead
(1.0 * src_alpha + 0.0 * dst_alpha).
Quoting Eric:
If we want to actually make the no-alpha-bits-present thing work,
we need to override the bits in the surface state or in the
generated code. In the normal draw path, it's done for sampling
by the swizzling code in brw_wm_surface_state.c, and the blending
overrides is just to fix up the alpha blending stage which
doesn't pay attention to that for the destination surface.
If one modifies piglit test gl-3.2-layered-rendering-blit to use
color component values other than zero or one, this change will
kick in on IVB. No regressions on IVB.
This is effectively revert of c0554141a9b831b4e614747104dcbbe0fe489b9d:
i965/blorp: Support overriding destination alpha to 1.0.
Currently, Blorp requires the source and destination formats to be
equal. However, we'd really like to be able to blit between XRGB and
ARGB formats; our BLT engine paths have supported this for a long time.
For ARGB - XRGB, nothing needs to occur: the missing alpha is already
interpreted as 1.0. For XRGB - ARGB, we need to smash the alpha
channel to 1.0 when writing the destination colors. This is fairly
straightforward with blending.
For now, this code is never used, as the source and destination formats
still must be equal. The next patch will relax that restriction.
NOTE: This is a candidate for the 9.1 branch.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Eric Anholt e...@anholt.net
Signed-off-by: Topi Pohjolainen topi.pohjolai...@intel.com
(cherry picked from commit 933be19cdf97aed977cd656e5c15c99cbdb52b7f)
---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 20
1 file changed, 20 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 90b9fbb..4222fa8 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -254,26 +254,6 @@ gen6_blorp_emit_blend_state(struct brw_context *brw,
blend-blend1.write_disable_b = params-color_write_disable[2];
blend-blend1.write_disable_a = params-color_write_disable[3];
- /* When blitting from an XRGB source to a ARGB destination, we need to
-* interpret the missing channel as 1.0. Blending can do that for us:
-* we simply use the RGB values from the fragment shader (source RGB),
-* but smash the alpha channel to 1.
-*/
- if (params-src.mt
- _mesa_get_format_bits(params-dst.mt-format, GL_ALPHA_BITS) 0
- _mesa_get_format_bits(params-src.mt-format, GL_ALPHA_BITS) == 0) {
- blend-blend0.blend_enable = 1;
- blend-blend0.ia_blend_enable = 1;
-
- blend-blend0.blend_func = BRW_BLENDFUNCTION_ADD;
- blend-blend0.ia_blend_func = BRW_BLENDFUNCTION_ADD;
-
- blend-blend0.source_blend_factor = BRW_BLENDFACTOR_SRC_COLOR;
- blend-blend0.dest_blend_factor = BRW_BLENDFACTOR_ZERO;
- blend-blend0.ia_source_blend_factor = BRW_BLENDFACTOR_ONE;
- blend-blend0.ia_dest_blend_factor = BRW_BLENDFACTOR_ZERO;
- }
-
return cc_blend_state_offset;
}
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Mesa (10.1): nv50: rework primid logic
Module: Mesa
Branch: 10.1
Commit: 156ac628a8c692bf98dfdc650c999f0d549a8550
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=156ac628a8c692bf98dfdc650c999f0d549a8550
Author: Ilia Mirkin imir...@alum.mit.edu
Date: Mon Feb 3 23:20:32 2014 -0500
nv50: rework primid logic
Functionally identical but much simpler. Should also better integrate
with future layer/viewport changes/fixes.
Cc: 10.1 mesa-sta...@lists.freedesktop.org
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
Reviewed-by: Christoph Bumiller e0425...@student.tuwien.ac.at
(cherry picked from commit c7373b7dc7202b93eecc1072efda7319b1ad0da8)
---
src/gallium/drivers/nouveau/nv50/nv50_program.c |5 +
src/gallium/drivers/nouveau/nv50/nv50_program.h |1 -
src/gallium/drivers/nouveau/nv50/nv50_shader_state.c |4 +++-
3 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.c
b/src/gallium/drivers/nouveau/nv50/nv50_program.c
index 636ef87..f14d3ef 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_program.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_program.c
@@ -170,10 +170,8 @@ nv50_fragprog_assign_slots(struct nv50_ir_prog_info *info)
if (info-in[i].sn == TGSI_SEMANTIC_COLOR)
prog-vp.bfc[info-in[i].si] = j;
- else if (info-in[i].sn == TGSI_SEMANTIC_PRIMID) {
+ else if (info-in[i].sn == TGSI_SEMANTIC_PRIMID)
prog-vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_PRIMITIVE_ID;
-prog-gp.primid = j;
- }
prog-in[j].id = i;
prog-in[j].mask = info-in[i].mask;
@@ -345,7 +343,6 @@ nv50_program_translate(struct nv50_program *prog, uint16_t
chipset)
prog-vp.clpd[0] = map_undef;
prog-vp.clpd[1] = map_undef;
prog-vp.psiz = map_undef;
- prog-gp.primid = 0x80;
prog-gp.has_layer = 0;
info-driverPriv = prog;
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.h
b/src/gallium/drivers/nouveau/nv50/nv50_program.h
index 5b092bd..75de007 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_program.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_program.h
@@ -88,7 +88,6 @@ struct nv50_program {
struct {
uint32_t vert_count;
- ubyte primid; /* primitive id output register */
uint8_t prim_type; /* point, line strip or tri strip */
bool has_layer;
ubyte layerid; /* hw value of layer output */
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c
b/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c
index 9a43502..f8b1c1b 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c
@@ -401,8 +401,10 @@ nv50_fp_linkage_validate(struct nv50_context *nv50)
if (vp-out[n].sn == fp-in[i].sn
vp-out[n].si == fp-in[i].si)
break;
- if (i == fp-gp.primid) {
+ switch (fp-in[i].sn) {
+ case TGSI_SEMANTIC_PRIMID:
primid = m;
+ break;
}
m = nv50_vec4_map(map, m, lin,
fp-in[i], (n vp-out_nr) ? vp-out[n] : dummy);
___
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Mesa (10.1): st/mesa: fix crash when a shader uses a TBO and it' s not bound
Module: Mesa
Branch: 10.1
Commit: 61219adb3d759bc20a2e9f39ab865b27bb2eff3f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=61219adb3d759bc20a2e9f39ab865b27bb2eff3f
Author: Marek Olšák marek.ol...@amd.com
Date: Thu Feb 6 02:16:50 2014 +0100
st/mesa: fix crash when a shader uses a TBO and it's not bound
This binds a NULL sampler view in that case.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74251
Cc: 10.1 10.0 mesa-sta...@lists.freedesktop.org
Reviewed-by: Brian Paul bri...@vmware.com
(cherry picked from commit c6dbcf10dff1f8343a26081f5489ef732ebb5460)
---
src/mesa/state_tracker/st_cb_texture.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/state_tracker/st_cb_texture.c
b/src/mesa/state_tracker/st_cb_texture.c
index 81a5d9b..824a13e 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -1483,6 +1483,12 @@ st_finalize_texture(struct gl_context *ctx,
if (tObj-Target == GL_TEXTURE_BUFFER) {
struct st_buffer_object *st_obj = st_buffer_object(tObj-BufferObject);
+ if (!st_obj) {
+ pipe_resource_reference(stObj-pt, NULL);
+ pipe_sampler_view_reference(stObj-sampler_view, NULL);
+ return GL_TRUE;
+ }
+
if (st_obj-buffer != stObj-pt) {
pipe_resource_reference(stObj-pt, st_obj-buffer);
pipe_sampler_view_release(st-pipe, stObj-sampler_view);
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Mesa (10.1): glsl: Fix continue statements in do-while loops.
Module: Mesa
Branch: 10.1
Commit: ee632e68bd945a0650f6382750b01fc959f7d2e1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee632e68bd945a0650f6382750b01fc959f7d2e1
Author: Paul Berry stereotype...@gmail.com
Date: Fri Jan 31 09:55:35 2014 -0800
glsl: Fix continue statements in do-while loops.
From the GLSL 4.40 spec, section 6.4 (Jumps):
The continue jump is used only in loops. It skips the remainder of
the body of the inner most loop of which it is inside. For while
and do-while loops, this jump is to the next evaluation of the
loop condition-expression from which the loop continues as
previously defined.
Previously, we incorrectly treated a continue statement as jumping
to the top of a do-while loop.
This patch fixes the problem by replicating the loop condition when
converting the continue statement to IR. (We already do a similar
thing in for loops, to ensure that continue causes the loop
expression to be executed).
Fixes piglit tests:
- glsl-fs-continue-inside-do-while.shader_test
- glsl-vs-continue-inside-do-while.shader_test
- glsl-fs-continue-in-switch-in-do-while.shader_test
- glsl-vs-continue-in-switch-in-do-while.shader_test
Cc: mesa-sta...@lists.freedesktop.org
Acked-by: Carl Worth cwo...@cworth.org
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Matt Turner matts...@gmail.com
(cherry picked from commit 7f5740899fe8ee2d7fecebf1b9622e06dbc78f43)
---
src/glsl/ast_to_hir.cpp | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 950f513..8d096ad 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -4029,17 +4029,22 @@ ast_jump_statement::hir(exec_list *instructions,
_mesa_glsl_error( loc, state,
break may only appear in a loop or a switch);
} else {
-/* For a loop, inline the for loop expression again,
- * since we don't know where near the end of
- * the loop body the normal copy of it
- * is going to be placed.
+/* For a loop, inline the for loop expression again, since we don't
+ * know where near the end of the loop body the normal copy of it is
+ * going to be placed. Same goes for the condition for a do-while
+ * loop.
*/
if (state-loop_nesting_ast != NULL
-mode == ast_continue
-state-loop_nesting_ast-rest_expression) {
- state-loop_nesting_ast-rest_expression-hir(instructions,
- state);
-}
+mode == ast_continue) {
+if (state-loop_nesting_ast-rest_expression) {
+ state-loop_nesting_ast-rest_expression-hir(instructions,
+ state);
+}
+if (state-loop_nesting_ast-mode ==
+ast_iteration_statement::ast_do_while) {
+ state-loop_nesting_ast-condition_to_hir(instructions, state);
+}
+ }
if (state-switch_state.is_switch_innermost
mode == ast_break) {
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Mesa (10.1): nv50: fix layerid to be the fp input number rather than vp output number
Module: Mesa
Branch: 10.1
Commit: 142f6cc0b4b1582e6e9183ac13f55c672228bdca
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=142f6cc0b4b1582e6e9183ac13f55c672228bdca
Author: Ilia Mirkin imir...@alum.mit.edu
Date: Mon Feb 3 23:35:14 2014 -0500
nv50: fix layerid to be the fp input number rather than vp output number
In the tests they were the same so it didn't matter, but indications are
that this is the correct behaviour. Also take this opportunity to
(trivially) support using gl_Layer in fp.
Cc: 10.1 mesa-sta...@lists.freedesktop.org
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
Reviewed-by: Christoph Bumiller e0425...@student.tuwien.ac.at
(cherry picked from commit 364bdd24197e83bc76b0d244271e57ef4334a859)
---
src/gallium/drivers/nouveau/nv50/nv50_program.c |2 +-
src/gallium/drivers/nouveau/nv50/nv50_program.h |2 +-
src/gallium/drivers/nouveau/nv50/nv50_shader_state.c | 12 +++-
3 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.c
b/src/gallium/drivers/nouveau/nv50/nv50_program.c
index f14d3ef..e506438 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_program.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_program.c
@@ -104,7 +104,7 @@ nv50_vertprog_assign_slots(struct nv50_ir_prog_info *info)
prog-vp.bfc[info-out[i].si] = i;
break;
case TGSI_SEMANTIC_LAYER:
- prog-gp.has_layer = true;
+ prog-gp.has_layer = TRUE;
prog-gp.layerid = n;
break;
default:
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.h
b/src/gallium/drivers/nouveau/nv50/nv50_program.h
index 75de007..8c1b327 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_program.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_program.h
@@ -89,7 +89,7 @@ struct nv50_program {
struct {
uint32_t vert_count;
uint8_t prim_type; /* point, line strip or tri strip */
- bool has_layer;
+ uint8_t has_layer;
ubyte layerid; /* hw value of layer output */
} gp;
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c
b/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c
index f8b1c1b..129ed2a 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c
@@ -346,7 +346,7 @@ nv50_fp_linkage_validate(struct nv50_context *nv50)
struct nv50_varying dummy;
int i, n, c, m;
uint32_t primid = 0;
- uint32_t layerid = vp-gp.layerid;
+ uint32_t layerid = 0;
uint32_t psiz = 0x000;
uint32_t interp = fp-fp.interp;
uint32_t colors = fp-fp.colors;
@@ -405,15 +405,17 @@ nv50_fp_linkage_validate(struct nv50_context *nv50)
case TGSI_SEMANTIC_PRIMID:
primid = m;
break;
+ case TGSI_SEMANTIC_LAYER:
+ layerid = m;
+ break;
}
m = nv50_vec4_map(map, m, lin,
fp-in[i], (n vp-out_nr) ? vp-out[n] : dummy);
}
- if (vp-gp.has_layer) {
- // In GL4.x, layer can be an fp input, but not in 3.x. Make sure to add
- // it to the output map.
- map[m++] = layerid;
+ if (vp-gp.has_layer !layerid) {
+ layerid = m;
+ map[m++] = vp-gp.layerid;
}
if (nv50-rast-pipe.point_size_per_vertex) {
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Mesa (10.1): nv50: only over-allocate by a page for code
Module: Mesa
Branch: 10.1
Commit: 31911f8d37fe149626c4810ef264730dab204598
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=31911f8d37fe149626c4810ef264730dab204598
Author: Ilia Mirkin imir...@alum.mit.edu
Date: Tue Feb 4 02:30:18 2014 -0500
nv50: only over-allocate by a page for code
The pre-fetching doesn't go too far. Tested with over-allocating by only
a page, and didn't see any errors in dmesg. Saves ~512KB of VRAM.
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
Cc: 10.1 mesa-sta...@lists.freedesktop.org
Reviewed-by: Christoph Bumiller e0425...@student.tuwien.ac.at
(cherry picked from commit f76c7ad5b14f5646a56ca3518f0c2e739811f223)
---
src/gallium/drivers/nouveau/nv50/nv50_screen.c |9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 5bb341d..b219a3b 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -741,12 +741,13 @@ nv50_screen_create(struct nouveau_device *dev)
goto fail;
}
- /* This over-allocates by a whole code BO. The GP, which would execute at
-* the end of the last page, would trigger faults. The going theory is that
-* it prefetches up to a certain amount. This avoids dmesg spam.
+ /* This over-allocates by a page. The GP, which would execute at the end of
+* the last page, would trigger faults. The going theory is that it
+* prefetches up to a certain amount.
*/
ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 16,
-4 NV50_CODE_BO_SIZE_LOG2, NULL, screen-code);
+(3 NV50_CODE_BO_SIZE_LOG2) + 0x1000,
+NULL, screen-code);
if (ret) {
NOUVEAU_ERR(Failed to allocate code bo: %d\n, ret);
goto fail;
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Mesa (10.1): nvc0/ir/emit: hardcode vertex output stream to 0 for now
Module: Mesa
Branch: 10.1
Commit: 17aeb3fdc9e453f7994ea31f7715e069e169a819
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=17aeb3fdc9e453f7994ea31f7715e069e169a819
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Fri Feb 7 22:39:44 2014 +0100
nvc0/ir/emit: hardcode vertex output stream to 0 for now
(cherry picked from commit b7233acf782a39c7e5643cb303022360664b6046)
---
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp |9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index 96a4af4..f15ca1b 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -1488,8 +1488,13 @@ CodeEmitterNVC0::emitOUT(const Instruction *i)
// vertex stream
if (i-src(1).getFile() == FILE_IMMEDIATE) {
- code[1] |= 0xc000;
- code[0] |= SDATA(i-src(1)).u32 26;
+ // Using immediate encoding here triggers an invalid opcode error
+ // or random results when error reporting is disabled.
+ // TODO: figure this out when we get multiple vertex streams
+ assert(SDATA(i-src(1)).u32 == 0);
+ srcId(NULL, 26);
+ // code[1] |= 0xc000;
+ // code[0] |= SDATA(i-src(1)).u32 26;
} else {
srcId(i-src(1), 26);
}
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Mesa: tag mesa-10.1-rc1: Mesa 10.1 release candidate 1
Module: Mesa Branch: refs/tags/mesa-10.1-rc1 Tag:892c3e26cc2f5dfbf3bf63b307bafa5f49658fe5 URL: http://cgit.freedesktop.org/mesa/mesa/tag/?id=892c3e26cc2f5dfbf3bf63b307bafa5f49658fe5 Tagger: Ian Romanick ian.d.roman...@intel.com Date: Fri Feb 7 18:34:54 2014 -0800 Mesa 10.1 release candidate 1 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (10.1): mesa: Bump version to 10.1-rc1
Module: Mesa Branch: 10.1 Commit: 1e6bba58d8b58b3a0e97d2cda0a4078d8bd54448 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e6bba58d8b58b3a0e97d2cda0a4078d8bd54448 Author: Ian Romanick ian.d.roman...@intel.com Date: Fri Feb 7 18:34:08 2014 -0800 mesa: Bump version to 10.1-rc1 Signed-off-by: Ian Romanick ian.d.roman...@intel.com --- VERSION |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index 7432bee..ff3cc45 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -10.1.0-devel +10.1.0-rc1 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Don' t print source registers for Broadwell flow control.
Module: Mesa
Branch: master
Commit: 5230655a2ee46ad2215d8d97de2e6a6907cc47e2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5230655a2ee46ad2215d8d97de2e6a6907cc47e2
Author: Kenneth Graunke kenn...@whitecape.org
Date: Wed Feb 5 01:32:39 2014 -0800
i965: Don't print source registers for Broadwell flow control.
The bits which normally contain the source register descriptions
actually contain the JIP/UIP jump targets, which we already printed.
Interpreting JIP/UIP as source registers results in some really creepy
looking output, like IF statements with acc14.40,1,0UD sources.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/dri/i965/gen8_disasm.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_disasm.c
b/src/mesa/drivers/dri/i965/gen8_disasm.c
index 387bb71..b2ab448 100644
--- a/src/mesa/drivers/dri/i965/gen8_disasm.c
+++ b/src/mesa/drivers/dri/i965/gen8_disasm.c
@@ -828,10 +828,7 @@ gen8_disassemble(FILE *file, struct gen8_instruction
*inst, int gen)
pad(file, 64);
err |= src2_3src(file, inst);
} else {
- if (m_opcode[opcode].ndst 0) {
- pad(file, 16);
- err |= dest(file, inst);
- } else if (opcode == BRW_OPCODE_ENDIF) {
+ if (opcode == BRW_OPCODE_ENDIF) {
format(file, %d, gen8_jip(inst));
} else if (opcode == BRW_OPCODE_IF ||
opcode == BRW_OPCODE_ELSE ||
@@ -840,15 +837,19 @@ gen8_disassemble(FILE *file, struct gen8_instruction
*inst, int gen)
opcode == BRW_OPCODE_CONTINUE ||
opcode == BRW_OPCODE_HALT) {
format(file, %d %d, gen8_jip(inst), gen8_uip(inst));
- }
-
- if (m_opcode[opcode].nsrc 0) {
- pad(file, 32);
- err |= src0(file, inst);
- }
- if (m_opcode[opcode].nsrc 1) {
- pad(file, 48);
- err |= src1(file, inst);
+ } else {
+ if (m_opcode[opcode].ndst 0) {
+pad(file, 16);
+err |= dest(file, inst);
+ }
+ if (m_opcode[opcode].nsrc 0) {
+pad(file, 32);
+err |= src0(file, inst);
+ }
+ if (m_opcode[opcode].nsrc 1) {
+pad(file, 48);
+err |= src1(file, inst);
+ }
}
}
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Mesa (master): i965: Fix fast depth clear values on Broadwell.
Module: Mesa Branch: master Commit: 8e0a0e4d30be142235c2b2439fe82935b8c67888 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e0a0e4d30be142235c2b2439fe82935b8c67888 Author: Kenneth Graunke kenn...@whitecape.org Date: Fri Feb 7 13:56:27 2014 -0800 i965: Fix fast depth clear values on Broadwell. Broadwell's 3DSTATE_CLEAR_PARAMS packet expects a floating point value regardless of format. This means we need to stop converting it to UNORM. Storing the value as float would make sense, but since we already have a uint32_t field, this patch continues shoehorning it into that. In a sense, this makes mt-depth_clear_value the DWord you emit in the packet, rather than the clear value itself. Signed-off-by: Kenneth Graunke kenn...@whitecape.org Reviewed-by: Eric Anholt e...@anholt.net --- src/mesa/drivers/dri/i965/brw_clear.c |5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c index 953e9ba..523fca2 100644 --- a/src/mesa/drivers/dri/i965/brw_clear.c +++ b/src/mesa/drivers/dri/i965/brw_clear.c @@ -160,7 +160,10 @@ brw_fast_clear_depth(struct gl_context *ctx) /* FALLTHROUGH */ default: - depth_clear_value = fb-_DepthMax * ctx-Depth.Clear; + if (brw-gen = 8) + depth_clear_value = float_as_int(ctx-Depth.Clear); + else + depth_clear_value = fb-_DepthMax * ctx-Depth.Clear; break; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Don' t disassemble UIP field for Broadwell WHILE instructions.
Module: Mesa
Branch: master
Commit: 8a7fe50067cf0f0d9af4610b6e10890235fe313d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a7fe50067cf0f0d9af4610b6e10890235fe313d
Author: Kenneth Graunke kenn...@whitecape.org
Date: Wed Feb 5 01:35:50 2014 -0800
i965: Don't disassemble UIP field for Broadwell WHILE instructions.
The WHILE instruction doesn't have UIP. It only has JIP.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/dri/i965/gen8_disasm.c |3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_disasm.c
b/src/mesa/drivers/dri/i965/gen8_disasm.c
index b2ab448..3705908 100644
--- a/src/mesa/drivers/dri/i965/gen8_disasm.c
+++ b/src/mesa/drivers/dri/i965/gen8_disasm.c
@@ -828,11 +828,10 @@ gen8_disassemble(FILE *file, struct gen8_instruction
*inst, int gen)
pad(file, 64);
err |= src2_3src(file, inst);
} else {
- if (opcode == BRW_OPCODE_ENDIF) {
+ if (opcode == BRW_OPCODE_ENDIF || opcode == BRW_OPCODE_WHILE) {
format(file, %d, gen8_jip(inst));
} else if (opcode == BRW_OPCODE_IF ||
opcode == BRW_OPCODE_ELSE ||
- opcode == BRW_OPCODE_WHILE ||
opcode == BRW_OPCODE_BREAK ||
opcode == BRW_OPCODE_CONTINUE ||
opcode == BRW_OPCODE_HALT) {
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Mesa (master): i965: Label JIP and UIP in Broadwell shader disassembly.
Module: Mesa
Branch: master
Commit: dcb0330d309cdfc7c46ccb7455525f9d888eab0b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dcb0330d309cdfc7c46ccb7455525f9d888eab0b
Author: Kenneth Graunke kenn...@whitecape.org
Date: Wed Feb 5 01:47:10 2014 -0800
i965: Label JIP and UIP in Broadwell shader disassembly.
This makes it obvious which number is which.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/dri/i965/gen8_disasm.c |8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_disasm.c
b/src/mesa/drivers/dri/i965/gen8_disasm.c
index 3705908..e63babd 100644
--- a/src/mesa/drivers/dri/i965/gen8_disasm.c
+++ b/src/mesa/drivers/dri/i965/gen8_disasm.c
@@ -829,13 +829,17 @@ gen8_disassemble(FILE *file, struct gen8_instruction
*inst, int gen)
err |= src2_3src(file, inst);
} else {
if (opcode == BRW_OPCODE_ENDIF || opcode == BRW_OPCODE_WHILE) {
- format(file, %d, gen8_jip(inst));
+ pad(file, 16);
+ format(file, JIP: %d, gen8_jip(inst));
} else if (opcode == BRW_OPCODE_IF ||
opcode == BRW_OPCODE_ELSE ||
opcode == BRW_OPCODE_BREAK ||
opcode == BRW_OPCODE_CONTINUE ||
opcode == BRW_OPCODE_HALT) {
- format(file, %d %d, gen8_jip(inst), gen8_uip(inst));
+ pad(file, 16);
+ format(file, JIP: %d, gen8_jip(inst));
+ pad(file, 32);
+ format(file, UIP: %d, gen8_uip(inst));
} else {
if (m_opcode[opcode].ndst 0) {
pad(file, 16);
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