Mesa (master): mesa/teximage: use correct extension for accept stencil texture.
Module: Mesa
Branch: master
Commit: f7aad9da20b13c98f77d6a690b327716f39c0a47
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7aad9da20b13c98f77d6a690b327716f39c0a47
Author: Dave Airlie
Date: Sun Apr 5 16:48:47 2015 +1000
mesa/teximage: use correct extension for accept stencil texture.
This was using the wrong extension, ARB_stencil_texturing
doesn't mention any changes in this area.
Fixes "dEQP-GLES3.functional.fbo.completeness.renderable.texture.
stencil.stencil_index8."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90751
Signed-off-by: Dave Airlie
Reviewed-by: Ilia Mirkin
Reviewed-by: Kenneth Graunke
---
src/mesa/main/teximage.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 7bc1da7..3d85615 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -222,7 +222,7 @@ _mesa_base_tex_format( struct gl_context *ctx, GLint
internalFormat )
}
}
- if (ctx->Extensions.ARB_stencil_texturing) {
+ if (ctx->Extensions.ARB_texture_stencil8) {
switch (internalFormat) {
case GL_STENCIL_INDEX:
case GL_STENCIL_INDEX1:
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Mesa (master): i965: Move intel_miptree_choose_tiling() to brw_tex_layout.c
Module: Mesa
Branch: master
Commit: 9edac38f2a7aaa55bc4f33eb268155ba76908925
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9edac38f2a7aaa55bc4f33eb268155ba76908925
Author: Anuj Phogat
Date: Tue Apr 14 22:06:47 2015 -0700
i965: Move intel_miptree_choose_tiling() to brw_tex_layout.c
and change the name to brw_miptree_choose_tiling().
V3: Remove redundant function parameters. (Topi)
Signed-off-by: Anuj Phogat
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 107 -
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 104
src/mesa/drivers/dri/i965/intel_mipmap_tree.h |8 --
3 files changed, 103 insertions(+), 116 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 4e79cf5..c77c0ce 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -458,6 +458,108 @@ brw_miptree_layout_texture_3d(struct brw_context *brw,
align_cube(mt);
}
+/**
+ * \brief Helper function for intel_miptree_create().
+ */
+static uint32_t
+brw_miptree_choose_tiling(struct brw_context *brw,
+ enum intel_miptree_tiling_mode requested,
+ const struct intel_mipmap_tree *mt)
+{
+ if (mt->format == MESA_FORMAT_S_UINT8) {
+ /* The stencil buffer is W tiled. However, we request from the kernel a
+ * non-tiled buffer because the GTT is incapable of W fencing.
+ */
+ return I915_TILING_NONE;
+ }
+
+ /* Some usages may want only one type of tiling, like depth miptrees (Y
+* tiled), or temporary BOs for uploading data once (linear).
+*/
+ switch (requested) {
+ case INTEL_MIPTREE_TILING_ANY:
+ break;
+ case INTEL_MIPTREE_TILING_Y:
+ return I915_TILING_Y;
+ case INTEL_MIPTREE_TILING_NONE:
+ return I915_TILING_NONE;
+ }
+
+ if (mt->num_samples > 1) {
+ /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
+ * Surface"):
+ *
+ * [DevSNB+]: For multi-sample render targets, this field must be
+ * 1. MSRTs can only be tiled.
+ *
+ * Our usual reason for preferring X tiling (fast blits using the
+ * blitting engine) doesn't apply to MSAA, since we'll generally be
+ * downsampling or upsampling when blitting between the MSAA buffer
+ * and another buffer, and the blitting engine doesn't support that.
+ * So use Y tiling, since it makes better use of the cache.
+ */
+ return I915_TILING_Y;
+ }
+
+ GLenum base_format = _mesa_get_format_base_format(mt->format);
+ if (base_format == GL_DEPTH_COMPONENT ||
+ base_format == GL_DEPTH_STENCIL_EXT)
+ return I915_TILING_Y;
+
+ /* 1D textures (and 1D array textures) don't get any benefit from tiling,
+* in fact it leads to a less efficient use of memory space and bandwidth
+* due to tile alignment.
+*/
+ if (mt->logical_height0 == 1)
+ return I915_TILING_NONE;
+
+ int minimum_pitch = mt->total_width * mt->cpp;
+
+ /* If the width is much smaller than a tile, don't bother tiling. */
+ if (minimum_pitch < 64)
+ return I915_TILING_NONE;
+
+ if (ALIGN(minimum_pitch, 512) >= 32768 ||
+ mt->total_width >= 32768 || mt->total_height >= 32768) {
+ perf_debug("%dx%d miptree too large to blit, falling back to untiled",
+ mt->total_width, mt->total_height);
+ return I915_TILING_NONE;
+ }
+
+ /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
+ if (brw->gen < 6)
+ return I915_TILING_X;
+
+ /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
+* "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
+* or Linear."
+* 128 bits per pixel translates to 16 bytes per pixel. This is necessary
+* all the way back to 965, but is permitted on Gen7+.
+*/
+ if (brw->gen < 7 && mt->cpp >= 16)
+ return I915_TILING_X;
+
+ /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
+* messages), on p64, under the heading "Surface Vertical Alignment":
+*
+* This field must be set to VALIGN_4 for all tiled Y Render Target
+* surfaces.
+*
+* So if the surface is renderable and uses a vertical alignment of 2,
+* force it to be X tiled. This is somewhat conservative (it's possible
+* that the client won't ever render to this surface), but it's difficult
+* to know that ahead of time. And besides, since we use a vertical
+* alignment of 4 as often as we can, this shouldn't happen very often.
+*/
+ if (brw->gen == 7 && mt->align_h == 2 &&
+ brw->format_supported_as_render_target[mt->format]) {
+ return I915_TILING_X;
+ }
+
+ return I915_TILING_Y | I915_TILING_X;
+}
+
+
void
brw_miptree_layout(struct brw_context *brw,
bool for_bo,
@@ -562,9 +664,6 @@ brw_mi
Mesa (master): i965/gen9: Set horizontal alignment for the miptree
Module: Mesa
Branch: master
Commit: 447410b66436acde4440aeae45f701b0e4502e97
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=447410b66436acde4440aeae45f701b0e4502e97
Author: Anuj Phogat
Date: Tue Apr 14 22:06:48 2015 -0700
i965/gen9: Set horizontal alignment for the miptree
v3: Use ffs() and a switch loop in
tr_mode_vertical_texture_alignment() (Ben)
Signed-off-by: Anuj Phogat
Reviewed-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 81
1 file changed, 81 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index e461bfc..4c66bb5 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -40,6 +40,81 @@
#define FILE_DEBUG_FLAG DEBUG_MIPTREE
static unsigned int
+tr_mode_horizontal_texture_alignment(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt)
+{
+ const unsigned *align_yf, *align_ys;
+ const unsigned bpp = _mesa_get_format_bytes(mt->format) * 8;
+ unsigned ret_align, divisor;
+
+ /* Horizontal alignment tables for TRMODE_{YF,YS}. Value in below
+* tables specifies the horizontal alignment requirement in elements
+* for the surface. An element is defined as a pixel in uncompressed
+* surface formats, and as a compression block in compressed surface
+* formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an
+* element is a sample.
+*/
+ const unsigned align_1d_yf[] = {4096, 2048, 1024, 512, 256};
+ const unsigned align_1d_ys[] = {65536, 32768, 16384, 8192, 4096};
+ const unsigned align_2d_yf[] = {64, 64, 32, 32, 16};
+ const unsigned align_2d_ys[] = {256, 256, 128, 128, 64};
+ const unsigned align_3d_yf[] = {16, 8, 8, 8, 4};
+ const unsigned align_3d_ys[] = {64, 32, 32, 32, 16};
+ int i = 0;
+
+ /* Alignment computations below assume bpp >= 8 and a power of 2. */
+ assert (bpp >= 8 && bpp <= 128 && is_power_of_two(bpp));
+
+ switch(mt->target) {
+ case GL_TEXTURE_1D:
+ case GL_TEXTURE_1D_ARRAY:
+ align_yf = align_1d_yf;
+ align_ys = align_1d_ys;
+ break;
+ case GL_TEXTURE_2D:
+ case GL_TEXTURE_RECTANGLE:
+ case GL_TEXTURE_2D_ARRAY:
+ case GL_TEXTURE_CUBE_MAP:
+ case GL_TEXTURE_CUBE_MAP_ARRAY:
+ case GL_TEXTURE_2D_MULTISAMPLE:
+ case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
+ align_yf = align_2d_yf;
+ align_ys = align_2d_ys;
+ break;
+ case GL_TEXTURE_3D:
+ align_yf = align_3d_yf;
+ align_ys = align_3d_ys;
+ break;
+ default:
+ unreachable("not reached");
+ }
+
+ /* Compute array index. */
+ i = ffs(bpp/8) - 1;
+
+ ret_align = mt->tr_mode == INTEL_MIPTREE_TRMODE_YF ?
+ align_yf[i] : align_ys[i];
+
+ assert(is_power_of_two(mt->num_samples));
+
+ switch (mt->num_samples) {
+ case 2:
+ case 4:
+ divisor = 2;
+ break;
+ case 8:
+ case 16:
+ divisor = 4;
+ break;
+ default:
+ divisor = 1;
+ break;
+ }
+ return ret_align / divisor;
+}
+
+
+static unsigned int
intel_horizontal_texture_alignment_unit(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
@@ -88,6 +163,12 @@ intel_horizontal_texture_alignment_unit(struct brw_context
*brw,
if (mt->format == MESA_FORMAT_S_UINT8)
return 8;
+ if (brw->gen >= 9 && mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE) {
+ uint32_t align = tr_mode_horizontal_texture_alignment(brw, mt);
+ /* XY_FAST_COPY_BLT doesn't support horizontal alignment < 32. */
+ return align < 32 ? 32 : align;
+ }
+
if (brw->gen >= 7 && mt->format == MESA_FORMAT_Z_UNORM16)
return 8;
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Mesa (master): i965: Choose tiling in brw_miptree_layout() function
Module: Mesa
Branch: master
Commit: 2cbe730ac53a8510d0decde20a42f1acd51a93a9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2cbe730ac53a8510d0decde20a42f1acd51a93a9
Author: Anuj Phogat
Date: Tue Apr 14 22:06:47 2015 -0700
i965: Choose tiling in brw_miptree_layout() function
This refactoring is required by later patches in this series.
Signed-off-by: Anuj Phogat
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 16 -
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 47 +
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 14 +++-
3 files changed, 52 insertions(+), 25 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 72b02a2..4e79cf5 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -459,7 +459,10 @@ brw_miptree_layout_texture_3d(struct brw_context *brw,
}
void
-brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt)
+brw_miptree_layout(struct brw_context *brw,
+ bool for_bo,
+ enum intel_miptree_tiling_mode requested,
+ struct intel_mipmap_tree *mt)
{
bool multisampled = mt->num_samples > 1;
bool gen6_hiz_or_stencil = false;
@@ -543,6 +546,11 @@ brw_miptree_layout(struct brw_context *brw, struct
intel_mipmap_tree *mt)
DBG("%s: %dx%dx%d\n", __func__,
mt->total_width, mt->total_height, mt->cpp);
+ if (!mt->total_width || !mt->total_height) {
+ intel_miptree_release(&mt);
+ return;
+ }
+
/* On Gen9+ the alignment values are expressed in multiples of the block
* size
*/
@@ -552,5 +560,11 @@ brw_miptree_layout(struct brw_context *brw, struct
intel_mipmap_tree *mt)
mt->align_w /= i;
mt->align_h /= j;
}
+
+ if (!for_bo)
+ mt->tiling = intel_miptree_choose_tiling(brw, mt->format,
+ mt->logical_width0,
+ mt->num_samples,
+ requested, mt);
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 8616c01..ef2f932 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -259,6 +259,7 @@ intel_miptree_create_layout(struct brw_context *brw,
GLuint depth0,
bool for_bo,
GLuint num_samples,
+enum intel_miptree_tiling_mode requested,
bool force_all_slices_at_each_lod,
bool disable_aux_buffers)
{
@@ -473,7 +474,7 @@ intel_miptree_create_layout(struct brw_context *brw,
if (force_all_slices_at_each_lod)
mt->array_layout = ALL_SLICES_AT_EACH_LOD;
- brw_miptree_layout(brw, mt);
+ brw_miptree_layout(brw, for_bo, requested, mt);
if (mt->disable_aux_buffers)
assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS);
@@ -484,7 +485,7 @@ intel_miptree_create_layout(struct brw_context *brw,
/**
* \brief Helper function for intel_miptree_create().
*/
-static uint32_t
+uint32_t
intel_miptree_choose_tiling(struct brw_context *brw,
mesa_format format,
uint32_t width0,
@@ -628,14 +629,14 @@ intel_lower_compressed_format(struct brw_context *brw,
mesa_format format)
struct intel_mipmap_tree *
intel_miptree_create(struct brw_context *brw,
-GLenum target,
-mesa_format format,
-GLuint first_level,
-GLuint last_level,
-GLuint width0,
-GLuint height0,
-GLuint depth0,
-bool expect_accelerated_upload,
+ GLenum target,
+ mesa_format format,
+ GLuint first_level,
+ GLuint last_level,
+ GLuint width0,
+ GLuint height0,
+ GLuint depth0,
+ bool expect_accelerated_upload,
GLuint num_samples,
enum intel_miptree_tiling_mode requested_tiling,
bool force_all_slices_at_each_lod)
@@ -653,15 +654,12 @@ intel_miptree_create(struct brw_context *brw,
first_level, last_level, width0,
height0, depth0,
false, num_samples,
+requested_tiling,
force_all_slices_at_each_lod,
false /*disable_aux_buffers*/);
- /*
-* pitch == 0 || height == 0 indicates the null texture
-*/
- if (!mt ||
Mesa (master): i965/gen9: Set tiled resource mode for the miptree
Module: Mesa
Branch: master
Commit: 126078faca7a9da0f825d3ad07ce9b1183737240
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=126078faca7a9da0f825d3ad07ce9b1183737240
Author: Anuj Phogat
Date: Tue Apr 14 22:06:47 2015 -0700
i965/gen9: Set tiled resource mode for the miptree
Signed-off-by: Anuj Phogat
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_tex_layout.c|2 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h |8
2 files changed, 10 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index ec7c6c4..e461bfc 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -568,6 +568,8 @@ brw_miptree_layout(struct brw_context *brw,
{
bool gen6_hiz_or_stencil = false;
+ mt->tr_mode = INTEL_MIPTREE_TRMODE_NONE;
+
if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
const GLenum base_format = _mesa_get_format_base_format(mt->format);
gen6_hiz_or_stencil = _mesa_is_depth_or_stencil_format(base_format);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 0db6b44..20bed53 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -330,6 +330,13 @@ struct intel_miptree_aux_buffer
struct intel_mipmap_tree *mt; /**< hiz miptree used with Gen6 */
};
+/* Tile resource modes */
+enum intel_miptree_tr_mode {
+ INTEL_MIPTREE_TRMODE_NONE,
+ INTEL_MIPTREE_TRMODE_YF,
+ INTEL_MIPTREE_TRMODE_YS
+};
+
struct intel_mipmap_tree
{
/** Buffer object containing the pixel data. */
@@ -338,6 +345,7 @@ struct intel_mipmap_tree
uint32_t pitch; /**< pitch in bytes. */
uint32_t tiling; /**< One of the I915_TILING_* flags */
+ enum intel_miptree_tr_mode tr_mode;
/* Effectively the key:
*/
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Mesa (master): i965: Make a helper function intel_miptree_set_total_width_height()
Module: Mesa
Branch: master
Commit: 556b2fbd240bff5d20c5137827757e053c00c3a8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=556b2fbd240bff5d20c5137827757e053c00c3a8
Author: Anuj Phogat
Date: Tue Apr 14 22:06:47 2015 -0700
i965: Make a helper function intel_miptree_set_total_width_height()
and some more code refactoring. No functional changes in this patch.
Signed-off-by: Anuj Phogat
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 93 +++-
1 file changed, 50 insertions(+), 43 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 9a2a331..312a887 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -710,50 +710,10 @@ brw_miptree_choose_tiling(struct brw_context *brw,
return I915_TILING_Y | I915_TILING_X;
}
-
-void
-brw_miptree_layout(struct brw_context *brw,
- bool for_bo,
- enum intel_miptree_tiling_mode requested,
- struct intel_mipmap_tree *mt)
+static void
+intel_miptree_set_total_width_height(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
{
- bool gen6_hiz_or_stencil = false;
-
- mt->tr_mode = INTEL_MIPTREE_TRMODE_NONE;
-
- if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
- const GLenum base_format = _mesa_get_format_base_format(mt->format);
- gen6_hiz_or_stencil = _mesa_is_depth_or_stencil_format(base_format);
- }
-
- if (gen6_hiz_or_stencil) {
- /* On gen6, we use ALL_SLICES_AT_EACH_LOD for stencil/hiz because the
- * hardware doesn't support multiple mip levels on stencil/hiz.
- *
- * PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer:
- * "The hierarchical depth buffer does not support the LOD field"
- *
- * PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer:
- * "The stencil depth buffer does not support the LOD field"
- */
- if (mt->format == MESA_FORMAT_S_UINT8) {
- /* Stencil uses W tiling, so we force W tiling alignment for the
- * ALL_SLICES_AT_EACH_LOD miptree layout.
- */
- mt->align_w = 64;
- mt->align_h = 64;
- } else {
- /* Depth uses Y tiling, so we force need Y tiling alignment for the
- * ALL_SLICES_AT_EACH_LOD miptree layout.
- */
- mt->align_w = 128 / mt->cpp;
- mt->align_h = 32;
- }
- } else {
- mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt);
- mt->align_h = intel_vertical_texture_alignment_unit(brw, mt);
- }
-
switch (mt->target) {
case GL_TEXTURE_CUBE_MAP:
if (brw->gen == 4) {
@@ -796,8 +756,55 @@ brw_miptree_layout(struct brw_context *brw,
}
break;
}
+
DBG("%s: %dx%dx%d\n", __func__,
mt->total_width, mt->total_height, mt->cpp);
+}
+
+void
+brw_miptree_layout(struct brw_context *brw,
+ bool for_bo,
+ enum intel_miptree_tiling_mode requested,
+ struct intel_mipmap_tree *mt)
+{
+ bool gen6_hiz_or_stencil = false;
+
+ mt->tr_mode = INTEL_MIPTREE_TRMODE_NONE;
+
+ if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
+ const GLenum base_format = _mesa_get_format_base_format(mt->format);
+ gen6_hiz_or_stencil = _mesa_is_depth_or_stencil_format(base_format);
+ }
+
+ if (gen6_hiz_or_stencil) {
+ /* On gen6, we use ALL_SLICES_AT_EACH_LOD for stencil/hiz because the
+ * hardware doesn't support multiple mip levels on stencil/hiz.
+ *
+ * PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer:
+ * "The hierarchical depth buffer does not support the LOD field"
+ *
+ * PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer:
+ * "The stencil depth buffer does not support the LOD field"
+ */
+ if (mt->format == MESA_FORMAT_S_UINT8) {
+ /* Stencil uses W tiling, so we force W tiling alignment for the
+ * ALL_SLICES_AT_EACH_LOD miptree layout.
+ */
+ mt->align_w = 64;
+ mt->align_h = 64;
+ } else {
+ /* Depth uses Y tiling, so we force need Y tiling alignment for the
+ * ALL_SLICES_AT_EACH_LOD miptree layout.
+ */
+ mt->align_w = 128 / mt->cpp;
+ mt->align_h = 32;
+ }
+ } else {
+ mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt);
+ mt->align_h = intel_vertical_texture_alignment_unit(brw, mt);
+ }
+
+ intel_miptree_set_total_width_height(brw, mt);
if (!mt->total_width || !mt->total_height) {
intel_miptree_release(&mt);
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Mesa (master): i965: Pass miptree pointer as function parameter in intel_vertical_texture_alignment_unit
Module: Mesa
Branch: master
Commit: ef6b9985ea6b60a562daed3a9ed3be0f91f21e01
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef6b9985ea6b60a562daed3a9ed3be0f91f21e01
Author: Anuj Phogat
Date: Tue Apr 14 22:06:47 2015 -0700
i965: Pass miptree pointer as function parameter in
intel_vertical_texture_alignment_unit
Signed-off-by: Anuj Phogat
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index c77c0ce..ec7c6c4 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -99,7 +99,7 @@ intel_horizontal_texture_alignment_unit(struct brw_context
*brw,
static unsigned int
intel_vertical_texture_alignment_unit(struct brw_context *brw,
- mesa_format format, bool multisampled)
+ const struct intel_mipmap_tree *mt)
{
/**
* From the "Alignment Unit Size" section of various specs, namely:
@@ -124,11 +124,11 @@ intel_vertical_texture_alignment_unit(struct brw_context
*brw,
* Where "*" means either VALIGN_2 or VALIGN_4 depending on the setting of
* the SURFACE_STATE "Surface Vertical Alignment" field.
*/
- if (_mesa_is_format_compressed(format))
+ if (_mesa_is_format_compressed(mt->format))
/* See comment above for the horizontal alignment */
return brw->gen >= 9 ? 16 : 4;
- if (format == MESA_FORMAT_S_UINT8)
+ if (mt->format == MESA_FORMAT_S_UINT8)
return brw->gen >= 7 ? 8 : 4;
/* Broadwell only supports VALIGN of 4, 8, and 16. The BSpec says 4
@@ -137,10 +137,10 @@ intel_vertical_texture_alignment_unit(struct brw_context
*brw,
if (brw->gen >= 8)
return 4;
- if (multisampled)
+ if (mt->num_samples > 1)
return 4;
- GLenum base_format = _mesa_get_format_base_format(format);
+ GLenum base_format = _mesa_get_format_base_format(mt->format);
if (brw->gen >= 6 &&
(base_format == GL_DEPTH_COMPONENT ||
@@ -161,7 +161,7 @@ intel_vertical_texture_alignment_unit(struct brw_context
*brw,
*
* VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
*/
- if (base_format == GL_YCBCR_MESA || format == MESA_FORMAT_RGB_FLOAT32)
+ if (base_format == GL_YCBCR_MESA || mt->format ==
MESA_FORMAT_RGB_FLOAT32)
return 2;
return 4;
@@ -566,7 +566,6 @@ brw_miptree_layout(struct brw_context *brw,
enum intel_miptree_tiling_mode requested,
struct intel_mipmap_tree *mt)
{
- bool multisampled = mt->num_samples > 1;
bool gen6_hiz_or_stencil = false;
if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
@@ -599,8 +598,7 @@ brw_miptree_layout(struct brw_context *brw,
}
} else {
mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt);
- mt->align_h =
- intel_vertical_texture_alignment_unit(brw, mt->format, multisampled);
+ mt->align_h = intel_vertical_texture_alignment_unit(brw, mt);
}
switch (mt->target) {
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Mesa (master): i965/gen9: Set vertical alignment for the miptree
Module: Mesa
Branch: master
Commit: 9111377978edf1c688811f877896942be9f8a332
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9111377978edf1c688811f877896942be9f8a332
Author: Anuj Phogat
Date: Tue Apr 14 22:06:48 2015 -0700
i965/gen9: Set vertical alignment for the miptree
v3: Use ffs() and a switch loop in
tr_mode_horizontal_texture_alignment() (Ben)
Signed-off-by: Anuj Phogat
Reviewed-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 70
1 file changed, 70 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 4c66bb5..9a2a331 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -179,6 +179,70 @@ intel_horizontal_texture_alignment_unit(struct brw_context
*brw,
}
static unsigned int
+tr_mode_vertical_texture_alignment(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt)
+{
+ const unsigned *align_yf, *align_ys;
+ const unsigned bpp = _mesa_get_format_bytes(mt->format) * 8;
+ unsigned ret_align, divisor;
+
+ /* Vertical alignment tables for TRMODE_YF and TRMODE_YS. */
+ const unsigned align_2d_yf[] = {64, 32, 32, 16, 16};
+ const unsigned align_2d_ys[] = {256, 128, 128, 64, 64};
+ const unsigned align_3d_yf[] = {16, 16, 16, 8, 8};
+ const unsigned align_3d_ys[] = {32, 32, 32, 16, 16};
+ int i = 0;
+
+ assert(brw->gen >= 9 &&
+ mt->target != GL_TEXTURE_1D &&
+ mt->target != GL_TEXTURE_1D_ARRAY);
+
+ /* Alignment computations below assume bpp >= 8 and a power of 2. */
+ assert (bpp >= 8 && bpp <= 128 && is_power_of_two(bpp)) ;
+
+ switch(mt->target) {
+ case GL_TEXTURE_2D:
+ case GL_TEXTURE_RECTANGLE:
+ case GL_TEXTURE_2D_ARRAY:
+ case GL_TEXTURE_CUBE_MAP:
+ case GL_TEXTURE_CUBE_MAP_ARRAY:
+ case GL_TEXTURE_2D_MULTISAMPLE:
+ case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
+ align_yf = align_2d_yf;
+ align_ys = align_2d_ys;
+ break;
+ case GL_TEXTURE_3D:
+ align_yf = align_3d_yf;
+ align_ys = align_3d_ys;
+ break;
+ default:
+ unreachable("not reached");
+ }
+
+ /* Compute array index. */
+ i = ffs(bpp / 8) - 1;
+
+ ret_align = mt->tr_mode == INTEL_MIPTREE_TRMODE_YF ?
+ align_yf[i] : align_ys[i];
+
+ assert(is_power_of_two(mt->num_samples));
+
+ switch (mt->num_samples) {
+ case 4:
+ case 8:
+ divisor = 2;
+ break;
+ case 16:
+ divisor = 4;
+ break;
+ default:
+ divisor = 1;
+ break;
+ }
+ return ret_align / divisor;
+}
+
+static unsigned int
intel_vertical_texture_alignment_unit(struct brw_context *brw,
const struct intel_mipmap_tree *mt)
{
@@ -212,6 +276,12 @@ intel_vertical_texture_alignment_unit(struct brw_context
*brw,
if (mt->format == MESA_FORMAT_S_UINT8)
return brw->gen >= 7 ? 8 : 4;
+ if (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE) {
+ uint32_t align = tr_mode_vertical_texture_alignment(brw, mt);
+ /* XY_FAST_COPY_BLT doesn't support vertical alignment < 64 */
+ return align < 64 ? 64 : align;
+ }
+
/* Broadwell only supports VALIGN of 4, 8, and 16. The BSpec says 4
* should always be used, except for stencil buffers, which should be 8.
*/
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Mesa (master): i965: Disallow saturation for MACH operations.
Module: Mesa Branch: master Commit: 4f2f5c8d81673473dce8bee3d66b524b4908a823 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f2f5c8d81673473dce8bee3d66b524b4908a823 Author: Ben Widawsky Date: Mon Dec 22 19:29:24 2014 -0800 i965: Disallow saturation for MACH operations. Reviewed-by: Matt Turner Signed-off-by: Ben Widawsky --- src/mesa/drivers/dri/i965/brw_shader.cpp |1 - 1 file changed, 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 6222d52..76285f2 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -949,7 +949,6 @@ backend_instruction::can_do_saturate() const case BRW_OPCODE_LINE: case BRW_OPCODE_LRP: case BRW_OPCODE_MAC: - case BRW_OPCODE_MACH: case BRW_OPCODE_MAD: case BRW_OPCODE_MATH: case BRW_OPCODE_MOV: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Fix HW blitter pitch limits
Module: Mesa
Branch: master
Commit: 8da79b8378ae87474d8c47ad955e4833edf98359
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8da79b8378ae87474d8c47ad955e4833edf98359
Author: Chris Wilson
Date: Fri Jun 5 13:49:08 2015 +0100
i965: Fix HW blitter pitch limits
The BLT pitch is specified in bytes for linear surfaces and in dwords
for tiled surfaces. In both cases the programmable limit is 32,767, so
adjust the check to compensate for the effect of tiling.
v2: Tweak whitespace for functions (Kenneth)
Signed-off-by: Chris Wilson
Cc: Kristian Høgsberg
Cc: Kenneth Graunke
Reviewed-by Kenneth Graunke
Cc: mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965/intel_blit.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b/src/mesa/drivers/dri/i965/intel_blit.c
index 7680a40..aae0d25 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -130,6 +130,15 @@ set_blitter_tiling(struct brw_context *brw,
ADVANCE_BATCH(); \
} while (0)
+static int
+blt_pitch(struct intel_mipmap_tree *mt)
+{
+ int pitch = mt->pitch;
+ if (mt->tiling)
+ pitch /= 4;
+ return pitch;
+}
+
/**
* Implements a rectangular block transfer (blit) of pixels between two
* miptrees.
@@ -197,14 +206,14 @@ intel_miptree_blit(struct brw_context *brw,
*
* Furthermore, intelEmitCopyBlit (which is called below) uses a signed
* 16-bit integer to represent buffer pitch, so it can only handle buffer
-* pitches < 32k.
+* pitches < 32k. However, the pitch is measured in bytes for linear buffers
+* and dwords for tiled buffers.
*
* As a result of these two limitations, we can only use the blitter to do
-* this copy when the miptree's pitch is less than 32k.
+* this copy when the miptree's pitch is less than 32k linear or 128k tiled.
*/
- if (src_mt->pitch >= 32768 ||
- dst_mt->pitch >= 32768) {
- perf_debug("Falling back due to >=32k pitch\n");
+ if (blt_pitch(src_mt) >= 32768 || blt_pitch(dst_mt) >= 32768) {
+ perf_debug("Falling back due to >= 32k/128k pitch\n");
return false;
}
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Mesa (master): i915: Blit RGBX<->RGBA drawpixels
Module: Mesa
Branch: master
Commit: c2d0606827412b710dcaed80268fc665de8c9c5d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2d0606827412b710dcaed80268fc665de8c9c5d
Author: Chris Wilson
Date: Fri Jun 5 14:33:36 2015 +0100
i915: Blit RGBX<->RGBA drawpixels
The blitter already has code to accommodate filling in the alpha channel
for BGRX destination formats, so expand this to also allow filling the
alpha channgel in RGBX formats.
More importantly for the next patch is moving the test into its own
function for the purpose of exporting the check to the callers.
v2: Fix alpha expansion as spotted by Alexander with the fix suggested by
Kenneth
Signed-off-by: Chris Wilson
Cc: Jason Ekstrand
Cc: Alexander Monakov
Cc: Kristian Høgsberg
Cc: Kenneth Graunke
Reviewed-by Kenneth Graunke
Cc: mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965/intel_blit.c | 36 +---
1 file changed, 29 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b/src/mesa/drivers/dri/i965/intel_blit.c
index aae0d25..059165e 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -139,6 +139,31 @@ blt_pitch(struct intel_mipmap_tree *mt)
return pitch;
}
+static bool
+blt_compatible_formats(mesa_format src, mesa_format dst)
+{
+ /* The BLT doesn't handle sRGB conversion */
+ assert(src == _mesa_get_srgb_format_linear(src));
+ assert(dst == _mesa_get_srgb_format_linear(dst));
+
+ /* No swizzle or format conversions possible, except... */
+ if (src == dst)
+ return true;
+
+ /* ...we can either discard the alpha channel when going from A->X,
+* or we can fill the alpha channel with 0xff when going from X->A
+*/
+ if (src == MESA_FORMAT_B8G8R8A8_UNORM || src == MESA_FORMAT_B8G8R8X8_UNORM)
+ return (dst == MESA_FORMAT_B8G8R8A8_UNORM ||
+ dst == MESA_FORMAT_B8G8R8X8_UNORM);
+
+ if (src == MESA_FORMAT_R8G8B8A8_UNORM || src == MESA_FORMAT_R8G8B8X8_UNORM)
+ return (dst == MESA_FORMAT_R8G8B8A8_UNORM ||
+ dst == MESA_FORMAT_R8G8B8X8_UNORM);
+
+ return false;
+}
+
/**
* Implements a rectangular block transfer (blit) of pixels between two
* miptrees.
@@ -181,11 +206,7 @@ intel_miptree_blit(struct brw_context *brw,
* the X channel don't matter), and XRGB to ARGB by setting the A
* channel to 1.0 at the end.
*/
- if (src_format != dst_format &&
- ((src_format != MESA_FORMAT_B8G8R8A8_UNORM &&
-src_format != MESA_FORMAT_B8G8R8X8_UNORM) ||
- (dst_format != MESA_FORMAT_B8G8R8A8_UNORM &&
-dst_format != MESA_FORMAT_B8G8R8X8_UNORM))) {
+ if (!blt_compatible_formats(src_format, dst_format)) {
perf_debug("%s: Can't use hardware blitter from %s to %s, "
"falling back.\n", __func__,
_mesa_get_format_name(src_format),
@@ -270,8 +291,9 @@ intel_miptree_blit(struct brw_context *brw,
return false;
}
- if (src_mt->format == MESA_FORMAT_B8G8R8X8_UNORM &&
- dst_mt->format == MESA_FORMAT_B8G8R8A8_UNORM) {
+ /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
+ if (_mesa_get_format_bits(src_format, GL_ALPHA_BITS) == 0 &&
+ _mesa_get_format_bits(dst_format, GL_ALPHA_BITS) > 0) {
intel_miptree_set_alpha_to_one(brw, dst_mt,
dst_x, dst_y,
width, height);
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Mesa (master): i965: Export format comparison for blitting between miptrees
Module: Mesa
Branch: master
Commit: 922c0c9fd526ce19b87bc74a3159dec7705c1de1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=922c0c9fd526ce19b87bc74a3159dec7705c1de1
Author: Chris Wilson
Date: Fri Jun 5 14:45:18 2015 +0100
i965: Export format comparison for blitting between miptrees
Since the introduction of
commit 536003c11e4cb1172c540932ce3cce06f03bf44e
Author: Boyan Ding
Date: Wed Mar 25 19:36:54 2015 +0800
i965: Add XRGB format to intel_screen_make_configs
winsys buffers no longer have an alpha channel. This causes
_mesa_format_matches_format_and_type() to reject previously working BGRA
uploads from using the BLT fast path. Instead of using the generic
routine for matching formats exactly, export the slightly more relaxed
check from intel_miptree_blit() which importantly allows the blitter
routine to apply a small number of format conversions.
References: https://bugs.freedesktop.org/show_bug.cgi?id=90839
Signed-off-by: Chris Wilson
Cc: Jason Ekstrand
Cc: Alexander Monakov
Cc: Kristian Høgsberg
Cc: Kenneth Graunke
Reviewed-by: Kenneth Graunke
Cc: mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965/intel_blit.c |6 +++---
src/mesa/drivers/dri/i965/intel_blit.h |2 ++
src/mesa/drivers/dri/i965/intel_pixel_draw.c | 11 +--
3 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b/src/mesa/drivers/dri/i965/intel_blit.c
index 059165e..5afc771 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -139,8 +139,8 @@ blt_pitch(struct intel_mipmap_tree *mt)
return pitch;
}
-static bool
-blt_compatible_formats(mesa_format src, mesa_format dst)
+bool
+intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst)
{
/* The BLT doesn't handle sRGB conversion */
assert(src == _mesa_get_srgb_format_linear(src));
@@ -206,7 +206,7 @@ intel_miptree_blit(struct brw_context *brw,
* the X channel don't matter), and XRGB to ARGB by setting the A
* channel to 1.0 at the end.
*/
- if (!blt_compatible_formats(src_format, dst_format)) {
+ if (!intel_miptree_blit_compatible_formats(src_format, dst_format)) {
perf_debug("%s: Can't use hardware blitter from %s to %s, "
"falling back.\n", __func__,
_mesa_get_format_name(src_format),
diff --git a/src/mesa/drivers/dri/i965/intel_blit.h
b/src/mesa/drivers/dri/i965/intel_blit.h
index f563939..2287c37 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.h
+++ b/src/mesa/drivers/dri/i965/intel_blit.h
@@ -46,6 +46,8 @@ intelEmitCopyBlit(struct brw_context *brw,
GLshort w, GLshort h,
GLenum logicop );
+bool intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst);
+
bool intel_miptree_blit(struct brw_context *brw,
struct intel_mipmap_tree *src_mt,
int src_level, int src_slice,
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_draw.c
b/src/mesa/drivers/dri/i965/intel_pixel_draw.c
index 4ecefc8..d68cbb6 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_draw.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_draw.c
@@ -28,6 +28,7 @@
#include "main/glheader.h"
#include "main/enums.h"
#include "main/image.h"
+#include "main/glformats.h"
#include "main/mtypes.h"
#include "main/condrender.h"
#include "main/fbobject.h"
@@ -76,8 +77,14 @@ do_blit_drawpixels(struct gl_context * ctx,
struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
- if (!_mesa_format_matches_format_and_type(irb->mt->format, format, type,
- false)) {
+ mesa_format src_format = _mesa_format_from_format_and_type(format, type);
+ mesa_format dst_format = irb->mt->format;
+
+ /* We can safely discard sRGB encode/decode for the DrawPixels interface */
+ src_format = _mesa_get_srgb_format_linear(src_format);
+ dst_format = _mesa_get_srgb_format_linear(dst_format);
+
+ if (!intel_miptree_blit_compatible_formats(src_format, dst_format)) {
DBG("%s: bad format for blit\n", __func__);
return false;
}
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Mesa (master): softpipe/query: force parenthesis around a logical not
Module: Mesa Branch: master Commit: 8614b9e489e65bb672ab16053d30ce8708856214 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8614b9e489e65bb672ab16053d30ce8708856214 Author: Martin Peres Date: Fri Jun 5 15:19:01 2015 +0300 softpipe/query: force parenthesis around a logical not This makes GCC5 happy. Reviewed-by: Brian Paul Signed-off-by: Martin Peres --- src/gallium/drivers/softpipe/sp_query.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/softpipe/sp_query.c b/src/gallium/drivers/softpipe/sp_query.c index e773870..76105b4 100644 --- a/src/gallium/drivers/softpipe/sp_query.c +++ b/src/gallium/drivers/softpipe/sp_query.c @@ -277,7 +277,7 @@ softpipe_check_render_cond(struct softpipe_context *sp) b = pipe->get_query_result(pipe, sp->render_cond_query, wait, (void*)&result); if (b) - return (!result == sp->render_cond_cond); + return (!result) == sp->render_cond_cond; else return TRUE; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): main/version: make sure all the output variables get set in get_gl_override
Module: Mesa
Branch: master
Commit: 184e4de3a126fa21945fe59f68b8a29977919fc4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=184e4de3a126fa21945fe59f68b8a29977919fc4
Author: Martin Peres
Date: Fri Jun 5 15:03:19 2015 +0300
main/version: make sure all the output variables get set in get_gl_override
This fixes 2 warnings in gcc 5.1.
Reviewed-by: Brian Paul
Reviewed-by: Marek Olšák
Signed-off-by: Martin Peres
---
src/mesa/main/version.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/version.c b/src/mesa/main/version.c
index 409e5ae..60c7604 100644
--- a/src/mesa/main/version.c
+++ b/src/mesa/main/version.c
@@ -63,7 +63,7 @@ get_gl_override(gl_api api, int *version, bool *fwd_context,
static bool compat_suffix = false;
if (api == API_OPENGLES)
- return;
+ goto exit;
if (override_version < 0) {
override_version = 0;
@@ -93,6 +93,7 @@ get_gl_override(gl_api api, int *version, bool *fwd_context,
}
}
+exit:
*version = override_version;
*fwd_context = fc_suffix;
*compat_context = compat_suffix;
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Mesa (master): radeonsi: Add CIK SDMA support
Module: Mesa
Branch: master
Commit: 56e38edc960bf08213cdb0282838ccec3e5ea10e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=56e38edc960bf08213cdb0282838ccec3e5ea10e
Author: Michel Dänzer
Date: Tue May 26 16:27:15 2015 +0900
radeonsi: Add CIK SDMA support
Based on the corresponding SI support. Same as that, this is currently
only enabled for one-dimensional buffer copies due to issues with
multi-dimensional SDMA copies.
Reviewed-by: Marek Olšák
Reviewed-by: Alex Deucher
---
src/gallium/drivers/radeonsi/Makefile.sources |1 +
src/gallium/drivers/radeonsi/cik_sdma.c | 364 +
src/gallium/drivers/radeonsi/si_dma.c | 20 --
src/gallium/drivers/radeonsi/si_pipe.h|9 +
src/gallium/drivers/radeonsi/si_state.c | 22 +-
src/gallium/drivers/radeonsi/si_state.h |1 +
src/gallium/drivers/radeonsi/sid.h| 31 +++
7 files changed, 427 insertions(+), 21 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/Makefile.sources
b/src/gallium/drivers/radeonsi/Makefile.sources
index 774dc22..2876c0a 100644
--- a/src/gallium/drivers/radeonsi/Makefile.sources
+++ b/src/gallium/drivers/radeonsi/Makefile.sources
@@ -1,4 +1,5 @@
C_SOURCES := \
+ cik_sdma.c \
si_blit.c \
si_commands.c \
si_compute.c \
diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c
b/src/gallium/drivers/radeonsi/cik_sdma.c
new file mode 100644
index 000..86111cb
--- /dev/null
+++ b/src/gallium/drivers/radeonsi/cik_sdma.c
@@ -0,0 +1,364 @@
+/*
+ * Copyright 2010 Jerome Glisse
+ * Copyright 2014,2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Jerome Glisse
+ */
+
+#include "sid.h"
+#include "si_pipe.h"
+#include "../radeon/r600_cs.h"
+
+#include "util/u_format.h"
+
+static uint32_t cik_micro_tile_mode(struct si_screen *sscreen, unsigned
tile_mode)
+{
+ if (sscreen->b.info.si_tile_mode_array_valid) {
+ uint32_t gb_tile_mode =
sscreen->b.info.si_tile_mode_array[tile_mode];
+
+ return G_009910_MICRO_TILE_MODE_NEW(gb_tile_mode);
+ }
+
+ /* The kernel cannod return the tile mode array. Guess? */
+ return V_009910_ADDR_SURF_THIN_MICRO_TILING;
+}
+
+static void cik_sdma_do_copy_buffer(struct si_context *ctx,
+ struct pipe_resource *dst,
+ struct pipe_resource *src,
+ uint64_t dst_offset,
+ uint64_t src_offset,
+ uint64_t size)
+{
+ struct radeon_winsys_cs *cs = ctx->b.rings.dma.cs;
+ unsigned i, ncopy, csize;
+ struct r600_resource *rdst = (struct r600_resource*)dst;
+ struct r600_resource *rsrc = (struct r600_resource*)src;
+
+ dst_offset += r600_resource(dst)->gpu_address;
+ src_offset += r600_resource(src)->gpu_address;
+
+ ncopy = (size + CIK_SDMA_COPY_MAX_SIZE - 1) / CIK_SDMA_COPY_MAX_SIZE;
+ r600_need_dma_space(&ctx->b, ncopy * 7);
+
+ r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rsrc,
RADEON_USAGE_READ,
+ RADEON_PRIO_MIN);
+ r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rdst,
RADEON_USAGE_WRITE,
+ RADEON_PRIO_MIN);
+
+ for (i = 0; i < ncopy; i++) {
+ csize = size < CIK_SDMA_COPY_MAX_SIZE ? size :
CIK_SDMA_COPY_MAX_SIZE;
+ cs->buf[cs->cdw++] = CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
+
CIK_SDMA_COPY_SUB_OPCODE_LINEAR,
+0);
+ cs->buf[cs->cdw++] = csize;
+ cs->buf[cs->cdw++] = 0; /* src/dst endian swap */
+ cs->buf[cs->cdw++] = src_offset;
+ cs->buf[cs->cdw++] =
Mesa (master): r600g,radeonsi: Assert that there' s enough space after flushing
Module: Mesa
Branch: master
Commit: 79f2acb8f89704c609dd87d969353a506e03b05e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=79f2acb8f89704c609dd87d969353a506e03b05e
Author: Michel Dänzer
Date: Wed Nov 19 15:31:24 2014 +0900
r600g,radeonsi: Assert that there's enough space after flushing
Reviewed-by: Marek Olšák
Reviewed-by: Alex Deucher
---
src/gallium/drivers/radeon/r600_pipe_common.c |5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 42e681d..3def444 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -107,11 +107,10 @@ void r600_draw_rectangle(struct blitter_context *blitter,
void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw)
{
- /* The number of dwords we already used in the DMA so far. */
- num_dw += ctx->rings.dma.cs->cdw;
/* Flush if there's not enough space. */
- if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
+ if ((num_dw + ctx->rings.dma.cs->cdw) > RADEON_MAX_CMDBUF_DWORDS) {
ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
+ assert((num_dw + ctx->rings.dma.cs->cdw) <=
RADEON_MAX_CMDBUF_DWORDS);
}
}
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