Mesa (master): draw/gallivm: add invocation ID support for llvmpipe.
Module: Mesa
Branch: master
Commit: 1a71fbe28ca0525b618f6fb9d7354f3a6589af2f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a71fbe28ca0525b618f6fb9d7354f3a6589af2f
Author: Dave Airlie
Date: Mon Jun 22 13:59:25 2015 +1000
draw/gallivm: add invocation ID support for llvmpipe.
This extends the draw code to add support for invocations.
Reviewed-by: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/auxiliary/draw/draw_gs.c|3 ++-
src/gallium/auxiliary/draw/draw_llvm.c |5 -
src/gallium/auxiliary/draw/draw_llvm.h |3 ++-
src/gallium/auxiliary/gallivm/lp_bld_tgsi.h |1 +
src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c |5 +
5 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/src/gallium/auxiliary/draw/draw_gs.c
b/src/gallium/auxiliary/draw/draw_gs.c
index 755e527..a1564f9 100644
--- a/src/gallium/auxiliary/draw/draw_gs.c
+++ b/src/gallium/auxiliary/draw/draw_gs.c
@@ -391,7 +391,8 @@ llvm_gs_run(struct draw_geometry_shader *shader,
(struct vertex_header*)input,
input_primitives,
shader->draw->instance_id,
- shader->llvm_prim_ids);
+ shader->llvm_prim_ids,
+ shader->invocation_id);
return ret;
}
diff --git a/src/gallium/auxiliary/draw/draw_llvm.c
b/src/gallium/auxiliary/draw/draw_llvm.c
index 9629a8a..90a31bc 100644
--- a/src/gallium/auxiliary/draw/draw_llvm.c
+++ b/src/gallium/auxiliary/draw/draw_llvm.c
@@ -2069,7 +2069,7 @@ draw_gs_llvm_generate(struct draw_llvm *llvm,
struct gallivm_state *gallivm = variant->gallivm;
LLVMContextRef context = gallivm->context;
LLVMTypeRef int32_type = LLVMInt32TypeInContext(context);
- LLVMTypeRef arg_types[6];
+ LLVMTypeRef arg_types[7];
LLVMTypeRef func_type;
LLVMValueRef variant_func;
LLVMValueRef context_ptr;
@@ -2105,6 +2105,7 @@ draw_gs_llvm_generate(struct draw_llvm *llvm,
arg_types[4] = int32_type; /* instance_id */
arg_types[5] = LLVMPointerType(
LLVMVectorType(int32_type, vector_length), 0); /* prim_id_ptr */
+ arg_types[6] = int32_type;
func_type = LLVMFunctionType(int32_type, arg_types, Elements(arg_types), 0);
@@ -2125,6 +2126,7 @@ draw_gs_llvm_generate(struct draw_llvm *llvm,
num_prims = LLVMGetParam(variant_func, 3);
system_values.instance_id = LLVMGetParam(variant_func, 4);
prim_id_ptr = LLVMGetParam(variant_func, 5);
+ system_values.invocation_id = LLVMGetParam(variant_func, 6);
lp_build_name(context_ptr, "context");
lp_build_name(input_array, "input");
@@ -2132,6 +2134,7 @@ draw_gs_llvm_generate(struct draw_llvm *llvm,
lp_build_name(num_prims, "num_prims");
lp_build_name(system_values.instance_id, "instance_id");
lp_build_name(prim_id_ptr, "prim_id_ptr");
+ lp_build_name(system_values.invocation_id, "invocation_id");
variant->context_ptr = context_ptr;
variant->io_ptr = io_ptr;
diff --git a/src/gallium/auxiliary/draw/draw_llvm.h
b/src/gallium/auxiliary/draw/draw_llvm.h
index 9565fc6..d48ed72 100644
--- a/src/gallium/auxiliary/draw/draw_llvm.h
+++ b/src/gallium/auxiliary/draw/draw_llvm.h
@@ -298,7 +298,8 @@ typedef int
struct vertex_header *output,
unsigned num_prims,
unsigned instance_id,
-int *prim_ids);
+int *prim_ids,
+unsigned invocation_id);
struct draw_llvm_variant_key
{
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h
index 3f76b79..967373c 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h
@@ -165,6 +165,7 @@ struct lp_bld_tgsi_system_values {
LLVMValueRef vertex_id_nobase;
LLVMValueRef prim_id;
LLVMValueRef basevertex;
+ LLVMValueRef invocation_id;
};
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
index 092bd18..268379e 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
@@ -1532,6 +1532,11 @@ emit_fetch_system_value(
atype = TGSI_TYPE_UNSIGNED;
break;
+ case TGSI_SEMANTIC_INVOCATIONID:
+ res = lp_build_broadcast_scalar(&bld_base->uint_bld,
bld->system_values.invocation_id);
+ atype = TGSI_TYPE_UNSIGNED;
+ break;
+
default:
assert(!"unexpected semantic in emit_fetch_system_value");
res = bld_base->base.zero;
___
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Mesa (master): tgsi: handle indirect sampler arrays. (v2)
Module: Mesa
Branch: master
Commit: 24e77cb09fda9a57d4a8288ced3e01df4c8ac280
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=24e77cb09fda9a57d4a8288ced3e01df4c8ac280
Author: Dave Airlie
Date: Wed May 27 18:37:17 2015 +1000
tgsi: handle indirect sampler arrays. (v2)
This is required for ARB_gpu_shader5 support in softpipe.
v2: add support to txd/txf/txq paths.
Reviewed-by: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/auxiliary/tgsi/tgsi_exec.c | 42 +---
1 file changed, 38 insertions(+), 4 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c
b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index fde99b9..44000ff 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -1988,6 +1988,35 @@ fetch_assign_deriv_channel(struct tgsi_exec_machine
*mach,
derivs[1][3] = d.f[3];
}
+static uint
+fetch_sampler_unit(struct tgsi_exec_machine *mach,
+ const struct tgsi_full_instruction *inst,
+ uint sampler)
+{
+ uint unit;
+
+ if (inst->Src[sampler].Register.Indirect) {
+ const struct tgsi_full_src_register *reg = &inst->Src[sampler];
+ union tgsi_exec_channel indir_index, index2;
+
+ index2.i[0] =
+ index2.i[1] =
+ index2.i[2] =
+ index2.i[3] = reg->Indirect.Index;
+
+ fetch_src_file_channel(mach,
+ 0,
+ reg->Indirect.File,
+ reg->Indirect.Swizzle,
+ &index2,
+ &ZeroVec,
+ &indir_index);
+ unit = inst->Src[sampler].Register.Index + indir_index.i[0];
+ } else {
+ unit = inst->Src[sampler].Register.Index;
+ }
+ return unit;
+}
/*
* execute a texture instruction.
@@ -2001,14 +2030,15 @@ exec_tex(struct tgsi_exec_machine *mach,
const struct tgsi_full_instruction *inst,
uint modifier, uint sampler)
{
- const uint unit = inst->Src[sampler].Register.Index;
const union tgsi_exec_channel *args[5], *proj = NULL;
union tgsi_exec_channel r[5];
enum tgsi_sampler_control control = tgsi_sampler_lod_none;
uint chan;
+ uint unit;
int8_t offsets[3];
int dim, shadow_ref, i;
+ unit = fetch_sampler_unit(mach, inst, sampler);
/* always fetch all 3 offsets, overkill but keeps code simple */
fetch_texel_offsets(mach, inst, offsets);
@@ -2107,12 +2137,13 @@ static void
exec_txd(struct tgsi_exec_machine *mach,
const struct tgsi_full_instruction *inst)
{
- const uint unit = inst->Src[3].Register.Index;
union tgsi_exec_channel r[4];
float derivs[3][2][TGSI_QUAD_SIZE];
uint chan;
+ uint unit;
int8_t offsets[3];
+ unit = fetch_sampler_unit(mach, inst, 3);
/* always fetch all 3 offsets, overkill but keeps code simple */
fetch_texel_offsets(mach, inst, offsets);
@@ -2214,14 +2245,15 @@ static void
exec_txf(struct tgsi_exec_machine *mach,
const struct tgsi_full_instruction *inst)
{
- const uint unit = inst->Src[1].Register.Index;
union tgsi_exec_channel r[4];
uint chan;
+ uint unit;
float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
int j;
int8_t offsets[3];
unsigned target;
+ unit = fetch_sampler_unit(mach, inst, 1);
/* always fetch all 3 offsets, overkill but keeps code simple */
fetch_texel_offsets(mach, inst, offsets);
@@ -2296,12 +2328,14 @@ static void
exec_txq(struct tgsi_exec_machine *mach,
const struct tgsi_full_instruction *inst)
{
- const uint unit = inst->Src[1].Register.Index;
int result[4];
union tgsi_exec_channel r[4], src;
uint chan;
+ uint unit;
int i,j;
+ unit = fetch_sampler_unit(mach, inst, 1);
+
fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
/* XXX: This interface can't return per-pixel values */
___
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Mesa (master): docs: update GL3 with softpipe/llvmpipe gpu_shader5 pieces.
Module: Mesa Branch: master Commit: 4731be701f3094666c24c143d9d6ddf53c456c39 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4731be701f3094666c24c143d9d6ddf53c456c39 Author: Dave Airlie Date: Tue Jun 23 15:55:30 2015 +1000 docs: update GL3 with softpipe/llvmpipe gpu_shader5 pieces. This just updates the bits I've added in the previous few patches. Signed-off-by: Dave Airlie --- docs/GL3.txt |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/GL3.txt b/docs/GL3.txt index a40fdee..220bcc8 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -98,13 +98,13 @@ GL 4.0, GLSL 4.00: GL_ARB_draw_indirect DONE (i965, nvc0, r600, radeonsi, llvmpipe, softpipe) GL_ARB_gpu_shader5 DONE (i965, nvc0) - 'precise' qualifierDONE - - Dynamically uniform sampler array indices DONE (r600) + - Dynamically uniform sampler array indices DONE (r600, softpipe) - Dynamically uniform UBO array indices DONE (r600) - Implicit signed -> unsigned conversionsDONE - Fused multiply-add DONE () - Packing/bitfield/conversion functions DONE (r600, radeonsi, softpipe) - Enhanced textureGather DONE (r600, radeonsi, softpipe) - - Geometry shader instancing DONE (r600) + - Geometry shader instancing DONE (r600, llvmpipe, softpipe) - Geometry shader multiple streams DONE () - Enhanced per-sample shadingDONE (r600, radeonsi) - Interpolation functionsDONE (r600) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): draw/tgsi: implement geom shader invocation support.
Module: Mesa
Branch: master
Commit: 40d225803ecfa805b4dea4ee0ebd04df00ca8827
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=40d225803ecfa805b4dea4ee0ebd04df00ca8827
Author: Dave Airlie
Date: Wed May 20 10:32:32 2015 +1000
draw/tgsi: implement geom shader invocation support.
This is just for softpipe, llvmpipe won't work without
some changes.
Reviewed-by: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/auxiliary/draw/draw_gs.c | 47
src/gallium/auxiliary/draw/draw_gs.h |2 ++
src/gallium/auxiliary/tgsi/tgsi_scan.c |2 ++
src/gallium/auxiliary/tgsi/tgsi_scan.h |1 +
4 files changed, 34 insertions(+), 18 deletions(-)
diff --git a/src/gallium/auxiliary/draw/draw_gs.c
b/src/gallium/auxiliary/draw/draw_gs.c
index 6375d41..755e527 100644
--- a/src/gallium/auxiliary/draw/draw_gs.c
+++ b/src/gallium/auxiliary/draw/draw_gs.c
@@ -190,9 +190,15 @@ static void tgsi_gs_prepare(struct draw_geometry_shader
*shader,
const unsigned
constants_size[PIPE_MAX_CONSTANT_BUFFERS])
{
struct tgsi_exec_machine *machine = shader->machine;
-
+ int j;
tgsi_exec_set_constant_buffers(machine, PIPE_MAX_CONSTANT_BUFFERS,
constants, constants_size);
+
+ if (shader->info.uses_invocationid) {
+ unsigned i = machine->SysSemanticToIndex[TGSI_SEMANTIC_INVOCATIONID];
+ for (j = 0; j < TGSI_QUAD_SIZE; j++)
+ machine->SystemValue[i].i[j] = shader->invocation_id;
+ }
}
static unsigned tgsi_gs_run(struct draw_geometry_shader *shader,
@@ -555,7 +561,7 @@ int draw_geometry_shader_run(struct draw_geometry_shader
*shader,
* overflown vertices into some area where they won't harm anyone */
unsigned total_verts_per_buffer = shader->primitive_boundary *
num_in_primitives;
-
+ unsigned invocation;
//Assume at least one primitive
max_out_prims = MAX2(max_out_prims, 1);
@@ -564,7 +570,7 @@ int draw_geometry_shader_run(struct draw_geometry_shader
*shader,
output_verts->stride = output_verts->vertex_size;
output_verts->verts =
(struct vertex_header *)MALLOC(output_verts->vertex_size *
- total_verts_per_buffer);
+ total_verts_per_buffer *
shader->num_invocations);
debug_assert(output_verts->verts);
#if 0
@@ -592,7 +598,7 @@ int draw_geometry_shader_run(struct draw_geometry_shader
*shader,
shader->input = input;
shader->input_info = input_info;
FREE(shader->primitive_lengths);
- shader->primitive_lengths = MALLOC(max_out_prims * sizeof(unsigned));
+ shader->primitive_lengths = MALLOC(max_out_prims * sizeof(unsigned) *
shader->num_invocations);
#ifdef HAVE_LLVM
@@ -622,23 +628,26 @@ int draw_geometry_shader_run(struct draw_geometry_shader
*shader,
}
#endif
- shader->prepare(shader, constants, constants_size);
+ for (invocation = 0; invocation < shader->num_invocations; invocation++) {
+ shader->invocation_id = invocation;
- if (input_prim->linear)
- gs_run(shader, input_prim, input_verts,
- output_prims, output_verts);
- else
- gs_run_elts(shader, input_prim, input_verts,
- output_prims, output_verts);
+ shader->prepare(shader, constants, constants_size);
- /* Flush the remaining primitives. Will happen if
-* num_input_primitives % 4 != 0
-*/
- if (shader->fetched_prim_count > 0) {
- gs_flush(shader);
- }
+ if (input_prim->linear)
+ gs_run(shader, input_prim, input_verts,
+output_prims, output_verts);
+ else
+ gs_run_elts(shader, input_prim, input_verts,
+ output_prims, output_verts);
- debug_assert(shader->fetched_prim_count == 0);
+ /* Flush the remaining primitives. Will happen if
+ * num_input_primitives % 4 != 0
+ */
+ if (shader->fetched_prim_count > 0) {
+ gs_flush(shader);
+ }
+ debug_assert(shader->fetched_prim_count == 0);
+ }
/* Update prim_info:
*/
@@ -771,6 +780,8 @@ draw_create_geometry_shader(struct draw_context *draw,
gs->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
gs->max_output_vertices =
gs->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
+ gs->num_invocations =
+ gs->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
if (!gs->max_output_vertices)
gs->max_output_vertices = 32;
diff --git a/src/gallium/auxiliary/draw/draw_gs.h
b/src/gallium/auxiliary/draw/draw_gs.h
index 49e93d5..663ba84 100644
--- a/src/gallium/auxiliary/draw/draw_gs.h
+++ b/src/gallium/auxiliary/draw/draw_gs.h
@@ -90,6 +90,8 @@ struct draw_geometry_shader {
unsigned vector_length;
unsigned max_out_prims;
+ unsigned num_invocations;
+ unsigned invocation_id;
#ifdef HAVE_LLVM
struct draw_gs_inputs *gs_input;
struct draw_gs_jit_context *jit_context;
diff --git a/src/galliu
Mesa (amdgpu): Revert "radeon/llvm: drop support for LLVM < 3.6"
Module: Mesa
Branch: amdgpu
Commit: 18949a1d60be6705d6c43f2de00159172270625b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=18949a1d60be6705d6c43f2de00159172270625b
Author: Marek Olšák
Date: Tue Jun 16 15:35:00 2015 +0200
Revert "radeon/llvm: drop support for LLVM < 3.6"
This reverts commit df57c3d5504ba91a1de8cbaa04dc7399a02a58c6.
---
src/gallium/drivers/r600/evergreen_compute.c | 70 +++-
.../drivers/r600/evergreen_compute_internal.h | 19
src/gallium/drivers/r600/r600_llvm.c | 118 ++--
src/gallium/drivers/r600/r600_pipe.c |4 +
src/gallium/drivers/radeon/r600_pipe_common.c | 20 +++-
src/gallium/drivers/radeon/radeon_llvm_emit.c |6 +
.../drivers/radeon/radeon_setup_tgsi_llvm.c|4 +
src/gallium/drivers/radeonsi/si_compute.c | 56 +-
src/gallium/drivers/radeonsi/si_pipe.c | 15 ++-
src/gallium/drivers/radeonsi/si_shader.c | 15 ++-
10 files changed, 308 insertions(+), 19 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index 81a841c..4c3c34c 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -208,6 +208,23 @@ void *evergreen_create_compute_state(
COMPUTE_DBG(ctx->screen, "*** evergreen_create_compute_state\n");
header = cso->prog;
code = cso->prog + sizeof(struct pipe_llvm_program_header);
+#if HAVE_LLVM < 0x0306
+(void)use_kill;
+ (void)p;
+ shader->llvm_ctx = LLVMContextCreate();
+ shader->num_kernels = radeon_llvm_get_num_kernels(shader->llvm_ctx,
+ code, header->num_bytes);
+ shader->kernels = CALLOC(sizeof(struct r600_kernel),
+ shader->num_kernels);
+ {
+ unsigned i;
+ for (i = 0; i < shader->num_kernels; i++) {
+ struct r600_kernel *kernel = &shader->kernels[i];
+ kernel->llvm_module = radeon_llvm_get_kernel_module(
+ shader->llvm_ctx, i, code, header->num_bytes);
+ }
+ }
+#else
memset(&shader->binary, 0, sizeof(shader->binary));
radeon_elf_read(code, header->num_bytes, &shader->binary, true);
r600_create_shader(&shader->bc, &shader->binary, &use_kill);
@@ -218,6 +235,7 @@ void *evergreen_create_compute_state(
memcpy(p, shader->bc.bytecode, shader->bc.ndw * 4);
ctx->b.ws->buffer_unmap(shader->code_bo->cs_buf);
#endif
+#endif
shader->ctx = (struct r600_context*)ctx;
shader->local_size = cso->req_local_mem;
@@ -335,7 +353,13 @@ static void evergreen_emit_direct_dispatch(
unsigned wave_divisor = (16 * num_pipes);
int group_size = 1;
int grid_size = 1;
- unsigned lds_size = shader->local_size / 4 + shader->bc.nlds_dw;
+ unsigned lds_size = shader->local_size / 4 +
+#if HAVE_LLVM < 0x0306
+ shader->active_kernel->bc.nlds_dw;
+#else
+ shader->bc.nlds_dw;
+#endif
+
/* Calculate group_size/grid_size */
for (i = 0; i < 3; i++) {
@@ -513,10 +537,18 @@ void evergreen_emit_cs_shader(
struct r600_resource *code_bo;
unsigned ngpr, nstack;
+#if HAVE_LLVM < 0x0306
+ struct r600_kernel *kernel = &shader->kernels[state->kernel_index];
+ code_bo = kernel->code_bo;
+ va = kernel->code_bo->gpu_address;
+ ngpr = kernel->bc.ngpr;
+ nstack = kernel->bc.nstack;
+#else
code_bo = shader->code_bo;
va = shader->code_bo->gpu_address + state->pc;
ngpr = shader->bc.ngpr;
nstack = shader->bc.nstack;
+#endif
r600_write_compute_context_reg_seq(cs, R_0288D0_SQ_PGM_START_LS, 3);
radeon_emit(cs, va >> 8); /* R_0288D0_SQ_PGM_START_LS */
@@ -541,10 +573,46 @@ static void evergreen_launch_grid(
struct r600_pipe_compute *shader = ctx->cs_shader_state.shader;
boolean use_kill;
+#if HAVE_LLVM < 0x0306
+ struct r600_kernel *kernel = &shader->kernels[pc];
+ (void)use_kill;
+if (!kernel->code_bo) {
+void *p;
+struct r600_bytecode *bc = &kernel->bc;
+LLVMModuleRef mod = kernel->llvm_module;
+boolean use_kill = false;
+bool dump = (ctx->screen->b.debug_flags & DBG_CS) != 0;
+unsigned use_sb = ctx->screen->b.debug_flags & DBG_SB_CS;
+unsigned sb_disasm = use_sb ||
+(ctx->screen->b.debug_flags & DBG_SB_DISASM);
+
+r600_bytecode_init(bc, ctx->b.chip_class, ctx->b.family,
+ ctx->screen->has_compressed_msaa_texturing);
+bc->type = TGSI_PROCESSOR_COMPUTE;
+bc->isa = ctx->isa;
+r600_llvm_compile(mod, ctx->b.family, bc, &us
Mesa (amdgpu): winsys/amdgpu: require LLVM 3.6.1 for VI because of bug fixes there
Module: Mesa
Branch: amdgpu
Commit: 1f53380ee91cca711d94c98989f60f2bd1b2b1b9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f53380ee91cca711d94c98989f60f2bd1b2b1b9
Author: Marek Olšák
Date: Tue Jun 16 16:25:07 2015 +0200
winsys/amdgpu: require LLVM 3.6.1 for VI because of bug fixes there
Trivial.
---
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c |8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index 8776dfd..78ce999 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -187,9 +187,11 @@ static boolean do_winsys_init(struct amdgpu_winsys *ws)
}
/* LLVM 3.6 is required for VI. */
- if (ws->info.chip_class >= VI && HAVE_LLVM < 0x0306) {
- fprintf(stderr, "amdgpu: LLVM 3.6 is required, got LLVM %i.%i.\n",
- HAVE_LLVM >> 8, HAVE_LLVM & 255);
+ if (ws->info.chip_class >= VI &&
+ (HAVE_LLVM < 0x0306 ||
+(HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 1))) {
+ fprintf(stderr, "amdgpu: LLVM 3.6.1 is required, got LLVM %i.%i.%i\n",
+ HAVE_LLVM >> 8, HAVE_LLVM & 255, MESA_LLVM_VERSION_PATCH);
goto fail;
}
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Mesa (amdgpu): configure.ac: rename LLVM_VERSION_PATCH to avoid conflict with llvm-config.h
Module: Mesa
Branch: amdgpu
Commit: d94b2a0dc850b18176620973565ccdf5fa8b1464
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d94b2a0dc850b18176620973565ccdf5fa8b1464
Author: Marek Olšák
Date: Sat Jun 6 13:24:11 2015 +0200
configure.ac: rename LLVM_VERSION_PATCH to avoid conflict with llvm-config.h
Reviewed-by: Tom Stellard
---
configure.ac |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index 6e52d43..51c245d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1930,7 +1930,7 @@ if test "x$enable_gallium_llvm" = xyes; then
LLVM_COMPONENTS="${LLVM_COMPONENTS} all-targets ipo linker
instrumentation"
LLVM_COMPONENTS="${LLVM_COMPONENTS} irreader option objcarcopts
profiledata"
fi
-DEFINES="${DEFINES} -DHAVE_LLVM=0x0$LLVM_VERSION_INT
-DLLVM_VERSION_PATCH=$LLVM_VERSION_PATCH"
+DEFINES="${DEFINES} -DHAVE_LLVM=0x0$LLVM_VERSION_INT
-DMESA_LLVM_VERSION_PATCH=$LLVM_VERSION_PATCH"
MESA_LLVM=1
dnl Check for Clang internal headers
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Mesa (amdgpu): winsys/amdgpu: sync buffer accesses to different rings
Module: Mesa
Branch: amdgpu
Commit: 5ba350b05923ea83a831fd94e6020c7ecf667ad6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ba350b05923ea83a831fd94e6020c7ecf667ad6
Author: Christian König
Date: Mon Jun 15 20:05:48 2015 +0200
winsys/amdgpu: sync buffer accesses to different rings
Without the GPU scheduler the kernel won't sync the access for
us any more. So do so manually in the amdgpu winsys.
Signed-off-by: Christian König
Acked-by Leo Liu
---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 8aafc45..a4edb08 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -469,6 +469,19 @@ void amdgpu_cs_emit_ioctl_oneshot(struct amdgpu_cs *cs,
struct amdgpu_cs_context
int i, r;
uint64_t fence;
+ for (i = 0; i < csc->num_buffers; i++) {
+ struct amdgpu_fence *bo_fence = (void *)csc->buffers[i].bo->fence;
+ if (!bo_fence)
+ continue;
+
+ if (bo_fence->ctx == cs->ctx &&
+ bo_fence->ip_type == cs->cst->request.ip_type &&
+ bo_fence->ring == cs->cst->request.ring)
+ continue;
+
+ amdgpu_fence_wait(&cs->ctx->ws->base, (void *)bo_fence,
PIPE_TIMEOUT_INFINITE);
+ }
+
r = amdgpu_cs_submit(cs->ctx->ctx, 0, &csc->request, 1, &fence);
if (r) {
fprintf(stderr, "amdgpu: The CS has been rejected, "
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Mesa (amdgpu): radeon/llvm: Handle LLVM backend rename from R600 to AMDGPU
Module: Mesa
Branch: amdgpu
Commit: afccb3f6c8486691bab29ab88962129424a74530
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=afccb3f6c8486691bab29ab88962129424a74530
Author: Tom Stellard
Date: Thu Jun 11 15:42:25 2015 +
radeon/llvm: Handle LLVM backend rename from R600 to AMDGPU
Reviewed-by: Marek Olšák
(cherry picked from commit 4d35eef326e49cc8da50879d30a1c5088d4775e1)
---
configure.ac | 13 -
src/gallium/drivers/radeon/radeon_llvm_emit.c |8
2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/configure.ac b/configure.ac
index 51c245d..1c96e12 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2049,16 +2049,19 @@ require_egl_drm() {
}
radeon_llvm_check() {
+if test ${LLVM_VERSION_INT} -lt 307; then
+amdgpu_llvm_target_name='r600'
+else
+amdgpu_llvm_target_name='amdgpu'
+fi
if test "x$enable_gallium_llvm" != "xyes"; then
AC_MSG_ERROR([--enable-gallium-llvm is required when building $1])
fi
llvm_check_version_for "3" "4" "2" $1
-if test true && $LLVM_CONFIG --targets-built | grep -qvw 'R600' ; then
-AC_MSG_ERROR([LLVM R600 Target not enabled. You can enable it when
building the LLVM
- sources with the --enable-experimental-targets=R600
- configure flag])
+if test true && $LLVM_CONFIG --targets-built | grep -iqvw
$amdgpu_llvm_target_name ; then
+AC_MSG_ERROR([LLVM $amdgpu_llvm_target_name not enabled in your LLVM
build.])
fi
-LLVM_COMPONENTS="${LLVM_COMPONENTS} r600 bitreader ipo"
+LLVM_COMPONENTS="${LLVM_COMPONENTS} $amdgpu_llvm_target_name bitreader ipo"
NEED_RADEON_LLVM=yes
if test "x$have_libelf" != xyes; then
AC_MSG_ERROR([$1 requires libelf when using llvm])
diff --git a/src/gallium/drivers/radeon/radeon_llvm_emit.c
b/src/gallium/drivers/radeon/radeon_llvm_emit.c
index 624077c..25580b6 100644
--- a/src/gallium/drivers/radeon/radeon_llvm_emit.c
+++ b/src/gallium/drivers/radeon/radeon_llvm_emit.c
@@ -86,10 +86,18 @@ static void init_r600_target()
{
static unsigned initialized = 0;
if (!initialized) {
+#if HAVE_LLVM < 0x0307
LLVMInitializeR600TargetInfo();
LLVMInitializeR600Target();
LLVMInitializeR600TargetMC();
LLVMInitializeR600AsmPrinter();
+#else
+ LLVMInitializeAMDGPUTargetInfo();
+ LLVMInitializeAMDGPUTarget();
+ LLVMInitializeAMDGPUTargetMC();
+ LLVMInitializeAMDGPUAsmPrinter();
+
+#endif
initialized = 1;
}
}
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Mesa (amdgpu): Revert "radeon/llvm: require LLVM 3.6.1 because it has stable VI support"
Module: Mesa
Branch: amdgpu
Commit: 475dc8a1fa1a641add9e807c3f6a7b88bb6ebf60
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=475dc8a1fa1a641add9e807c3f6a7b88bb6ebf60
Author: Marek Olšák
Date: Tue Jun 16 15:35:08 2015 +0200
Revert "radeon/llvm: require LLVM 3.6.1 because it has stable VI support"
This reverts commit 4b8787ac1c511af4c222bf0f152d55d7c98cd4aa.
---
configure.ac |2 +-
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c |7 +++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index e6e9d9e..6e52d43 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2052,7 +2052,7 @@ radeon_llvm_check() {
if test "x$enable_gallium_llvm" != "xyes"; then
AC_MSG_ERROR([--enable-gallium-llvm is required when building $1])
fi
-llvm_check_version_for "3" "6" "1" $1
+llvm_check_version_for "3" "4" "2" $1
if test true && $LLVM_CONFIG --targets-built | grep -qvw 'R600' ; then
AC_MSG_ERROR([LLVM R600 Target not enabled. You can enable it when
building the LLVM
sources with the --enable-experimental-targets=R600
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index 5651fdb..8776dfd 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -186,6 +186,13 @@ static boolean do_winsys_init(struct amdgpu_winsys *ws)
goto fail;
}
+ /* LLVM 3.6 is required for VI. */
+ if (ws->info.chip_class >= VI && HAVE_LLVM < 0x0306) {
+ fprintf(stderr, "amdgpu: LLVM 3.6 is required, got LLVM %i.%i.\n",
+ HAVE_LLVM >> 8, HAVE_LLVM & 255);
+ goto fail;
+ }
+
/* family and rev_id are for addrlib */
switch (ws->info.family) {
case CHIP_BONAIRE:
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Mesa (master): nir: Allow vec2/vec3/ vec4 instructions in the select peephole pass.
Module: Mesa
Branch: master
Commit: 1762568fd39b9be42d963d335e36daea25df7044
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1762568fd39b9be42d963d335e36daea25df7044
Author: Kenneth Graunke
Date: Wed Jun 10 00:52:07 2015 -0700
nir: Allow vec2/vec3/vec4 instructions in the select peephole pass.
These are basically just moves, so they should be safe as well.
When disabling i965's GLSL IR level scalarizer (channel expressions)
pass, I started seeing NIR code like this:
if ssa_21 {
block block_1:
/* preds: block_0 */
vec4 ssa_120 = vec4 ssa_82, ssa_83, ssa_84, ssa_30
/* succs: block_3 */
} else {
block block_2:
/* preds: block_0 */
/* succs: block_3 */
}
block block_3:
/* preds: block_1 block_2 */
vec4 ssa_33 = phi block_1: ssa_120, block_2: ssa_2
Previously, the GLSL IR scalarizer pass would break the vec4 into a
series of fmovs, which were allowed by the peephole pass. But with
the vec4 operation, they were not. We want to keep getting selects.
Normal i965 on Broadwell:
instructions in affected programs: 200 -> 176 (-12.00%)
helped:4
With brw_fs_channel_expressions() disabled:
instructions in affected programs: 1832 -> 1646 (-10.15%)
helped:30
Signed-off-by: Kenneth Graunke
Reviewed-by: Jason Ekstrand
Reviewed-by: Connor Abbott
---
src/glsl/nir/nir_opt_peephole_select.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/glsl/nir/nir_opt_peephole_select.c
b/src/glsl/nir/nir_opt_peephole_select.c
index 82c65bb..ef7c977 100644
--- a/src/glsl/nir/nir_opt_peephole_select.c
+++ b/src/glsl/nir/nir_opt_peephole_select.c
@@ -86,7 +86,9 @@ block_check_for_allowed_instrs(nir_block *block)
nir_alu_instr *mov = nir_instr_as_alu(instr);
if (mov->op != nir_op_fmov && mov->op != nir_op_imov &&
mov->op != nir_op_fneg && mov->op != nir_op_ineg &&
- mov->op != nir_op_fabs && mov->op != nir_op_iabs)
+ mov->op != nir_op_fabs && mov->op != nir_op_iabs &&
+ mov->op != nir_op_vec2 && mov->op != nir_op_vec3 &&
+ mov->op != nir_op_vec4)
return false;
/* Can't handle saturate */
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Mesa (master): i965: Add and fix comments in brw_vue_map.c.
Module: Mesa
Branch: master
Commit: 94e3864707e48d4b1d5fb5f88a01370a73ddb0cb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=94e3864707e48d4b1d5fb5f88a01370a73ddb0cb
Author: Kenneth Graunke
Date: Fri May 15 09:58:42 2015 -0700
i965: Add and fix comments in brw_vue_map.c.
Signed-off-by: Kenneth Graunke
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_vue_map.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vue_map.c
b/src/mesa/drivers/dri/i965/brw_vue_map.c
index ff92bd2..7687578 100644
--- a/src/mesa/drivers/dri/i965/brw_vue_map.c
+++ b/src/mesa/drivers/dri/i965/brw_vue_map.c
@@ -24,6 +24,15 @@
/**
* @file brw_vue_map.c
*
+ * This file computes the "VUE map" for a (non-fragment) shader stage, which
+ * describes the layout of its output varyings. The VUE map is used to match
+ * outputs from one stage with the inputs of the next.
+ *
+ * Largely, varyings can be placed however we like - producers/consumers simply
+ * have to agree on the layout. However, there is also a "VUE Header" that
+ * prescribes a fixed-layout for items that interact with fixed function
+ * hardware, such as the clipper and rasterizer.
+ *
* Authors:
* Paul Berry
* Chris Forbes
@@ -45,7 +54,7 @@ assign_vue_slot(struct brw_vue_map *vue_map, int varying)
}
/**
- * Compute the VUE map for vertex shader program.
+ * Compute the VUE map for a shader stage.
*/
void
brw_compute_vue_map(const struct brw_device_info *devinfo,
@@ -76,6 +85,9 @@ brw_compute_vue_map(const struct brw_device_info *devinfo,
/* VUE header: format depends on chip generation and whether clipping is
* enabled.
+*
+* See the Sandybridge PRM, Volume 2 Part 1, section 1.5.1 (page 30),
+* "Vertex URB Entry (VUE) Formats" which describes the VUE header layout.
*/
if (devinfo->gen < 6) {
/* There are 8 dwords in VUE header pre-Ironlake:
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Mesa (master): i965: Split VUE map handling out of brw_vs.c into brw_vue_map.c.
Module: Mesa
Branch: master
Commit: 38eb9015e3be9b93248e64b6befce16872107a7c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=38eb9015e3be9b93248e64b6befce16872107a7c
Author: Kenneth Graunke
Date: Fri May 15 09:54:23 2015 -0700
i965: Split VUE map handling out of brw_vs.c into brw_vue_map.c.
This was originally only used by the vertex shader, but it's now used by
the geometry shader as well, and will also eventually be used for
tessellation control and evaluation shaders.
I suspect it will be easier to find in a file named after the concept.
Signed-off-by: Kenneth Graunke
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/Makefile.sources |1 +
src/mesa/drivers/dri/i965/brw_vs.c | 102 -
src/mesa/drivers/dri/i965/brw_vue_map.c| 136
3 files changed, 137 insertions(+), 102 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
b/src/mesa/drivers/dri/i965/Makefile.sources
index 93f336e..981fe79 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -130,6 +130,7 @@ i965_FILES = \
brw_vs.h \
brw_vs_state.c \
brw_vs_surface_state.c \
+ brw_vue_map.c \
brw_wm.c \
brw_wm.h \
brw_wm_iz.cpp \
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c
b/src/mesa/drivers/dri/i965/brw_vs.c
index d03567e..6e9848f 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -40,108 +40,6 @@
#include "util/ralloc.h"
-static inline void assign_vue_slot(struct brw_vue_map *vue_map,
- int varying)
-{
- /* Make sure this varying hasn't been assigned a slot already */
- assert (vue_map->varying_to_slot[varying] == -1);
-
- vue_map->varying_to_slot[varying] = vue_map->num_slots;
- vue_map->slot_to_varying[vue_map->num_slots++] = varying;
-}
-
-/**
- * Compute the VUE map for vertex shader program.
- */
-void
-brw_compute_vue_map(const struct brw_device_info *devinfo,
-struct brw_vue_map *vue_map,
-GLbitfield64 slots_valid)
-{
- vue_map->slots_valid = slots_valid;
- int i;
-
- /* gl_Layer and gl_ViewportIndex don't get their own varying slots -- they
-* are stored in the first VUE slot (VARYING_SLOT_PSIZ).
-*/
- slots_valid &= ~(VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT);
-
- /* Make sure that the values we store in vue_map->varying_to_slot and
-* vue_map->slot_to_varying won't overflow the signed chars that are used
-* to store them. Note that since vue_map->slot_to_varying sometimes holds
-* values equal to BRW_VARYING_SLOT_COUNT, we need to ensure that
-* BRW_VARYING_SLOT_COUNT is <= 127, not 128.
-*/
- STATIC_ASSERT(BRW_VARYING_SLOT_COUNT <= 127);
-
- vue_map->num_slots = 0;
- for (i = 0; i < BRW_VARYING_SLOT_COUNT; ++i) {
- vue_map->varying_to_slot[i] = -1;
- vue_map->slot_to_varying[i] = BRW_VARYING_SLOT_COUNT;
- }
-
- /* VUE header: format depends on chip generation and whether clipping is
-* enabled.
-*/
- if (devinfo->gen < 6) {
- /* There are 8 dwords in VUE header pre-Ironlake:
- * dword 0-3 is indices, point width, clip flags.
- * dword 4-7 is ndc position
- * dword 8-11 is the first vertex data.
- *
- * On Ironlake the VUE header is nominally 20 dwords, but the hardware
- * will accept the same header layout as Gen4 [and should be a bit
faster]
- */
- assign_vue_slot(vue_map, VARYING_SLOT_PSIZ);
- assign_vue_slot(vue_map, BRW_VARYING_SLOT_NDC);
- assign_vue_slot(vue_map, VARYING_SLOT_POS);
- } else {
- /* There are 8 or 16 DWs (D0-D15) in VUE header on Sandybridge:
- * dword 0-3 of the header is indices, point width, clip flags.
- * dword 4-7 is the 4D space position
- * dword 8-15 of the vertex header is the user clip distance if
- * enabled.
- * dword 8-11 or 16-19 is the first vertex element data we fill.
- */
- assign_vue_slot(vue_map, VARYING_SLOT_PSIZ);
- assign_vue_slot(vue_map, VARYING_SLOT_POS);
- if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST0))
- assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST0);
- if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST1))
- assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST1);
-
- /* front and back colors need to be consecutive so that we can use
- * ATTRIBUTE_SWIZZLE_INPUTATTR_FACING to swizzle them when doing
- * two-sided color.
- */
- if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_COL0))
- assign_vue_slot(vue_map, VARYING_SLOT_COL0);
- if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_BFC0))
- assign_vue_slot(vue_map, VARYING_SLOT_BFC0);
- if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_COL1))
- assign_vue_slot(vue_map, VARYING_SLOT_COL1);
- if (slots_valid & BITFIELD64_B
Demos (master): demos: flush stdout after printing frame rate
Module: Demos
Branch: master
Commit: 3d5e8e181a3d65ffd41a17110a8e552244d9f7bd
URL:
http://cgit.freedesktop.org/mesa/demos/commit/?id=3d5e8e181a3d65ffd41a17110a8e552244d9f7bd
Author: Brian Paul
Date: Mon Jun 22 13:42:44 2015 -0600
demos: flush stdout after printing frame rate
To get immediate output on Windows.
Trivial.
---
src/demos/fbo_firecube.c |3 ++-
src/demos/fire.c |1 +
src/demos/teapot.c |1 +
src/demos/terrain.c |1 +
src/demos/trispd.c |1 +
src/demos/tunnel.c |1 +
src/demos/tunnel2.c |1 +
7 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/demos/fbo_firecube.c b/src/demos/fbo_firecube.c
index 333c04c..eefbb64 100644
--- a/src/demos/fbo_firecube.c
+++ b/src/demos/fbo_firecube.c
@@ -584,7 +584,8 @@ drawfire(void)
GLfloat seconds = (t - T0) / 1000.0;
GLfloat fps = Frames / seconds;
sprintf(frbuf, "Frame rate: %f", fps);
- printf("%s\n", frbuf);
+printf("%s\n", frbuf);
+fflush(stdout);
T0 = t;
Frames = 0;
}
diff --git a/src/demos/fire.c b/src/demos/fire.c
index c40278b..34fac44 100644
--- a/src/demos/fire.c
+++ b/src/demos/fire.c
@@ -529,6 +529,7 @@ drawfire(void)
GLfloat fps = Frames / seconds;
sprintf(frbuf, "Frame rate: %f", fps);
printf("%s\n", frbuf);
+ fflush(stdout);
T0 = t;
Frames = 0;
}
diff --git a/src/demos/teapot.c b/src/demos/teapot.c
index f75ad94..23d2225 100644
--- a/src/demos/teapot.c
+++ b/src/demos/teapot.c
@@ -491,6 +491,7 @@ static void draw(void)
GLfloat fps = Frames / seconds;
sprintf(frbuf, "Frame rate: %f", fps);
printf("%s\n", frbuf);
+ fflush(stdout);
T0 = t;
Frames = 0;
}
diff --git a/src/demos/terrain.c b/src/demos/terrain.c
index 435912a..9e3629d 100644
--- a/src/demos/terrain.c
+++ b/src/demos/terrain.c
@@ -426,6 +426,7 @@ drawscene(void)
GLfloat fps = Frames / seconds;
sprintf(frbuf, "Frame rate: %f", fps);
printf("%s\n", frbuf);
+ fflush(stdout);
T0 = t;
Frames = 0;
}
diff --git a/src/demos/trispd.c b/src/demos/trispd.c
index 0c7ad6e..d6e231e 100644
--- a/src/demos/trispd.c
+++ b/src/demos/trispd.c
@@ -95,6 +95,7 @@ static void Display( void )
pixelRate = triRate * Size;
printf("Rate: %d tri in %gs = %g tri/s %d pixels/s\n",
triCount, t1-t0, triRate, (int)pixelRate);
+ fflush(stdout);
glutSwapBuffers();
}
diff --git a/src/demos/tunnel.c b/src/demos/tunnel.c
index 6e48ad4..dea689e 100644
--- a/src/demos/tunnel.c
+++ b/src/demos/tunnel.c
@@ -470,6 +470,7 @@ draw(void)
GLfloat fps = Frames / seconds;
sprintf(frbuf, "Frame rate: %f", fps);
printf("%s\n", frbuf);
+ fflush(stdout);
T0 = t;
Frames = 0;
}
diff --git a/src/demos/tunnel2.c b/src/demos/tunnel2.c
index 800ea7b..1126a38 100644
--- a/src/demos/tunnel2.c
+++ b/src/demos/tunnel2.c
@@ -491,6 +491,7 @@ draw(void)
GLfloat fps = Frames / seconds;
sprintf(frbuf, "Frame rate: %f", fps);
printf("%s\n", frbuf);
+ fflush(stdout);
T0 = t;
Frames = 0;
}
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Mesa (master): i965/gen9: Implement Push Constant Buffer workaround
Module: Mesa
Branch: master
Commit: 90754d2df05eafe1a3ee3cd9bb1611a19099fc49
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=90754d2df05eafe1a3ee3cd9bb1611a19099fc49
Author: Ben Widawsky
Date: Wed Jun 3 21:35:51 2015 -0700
i965/gen9: Implement Push Constant Buffer workaround
This implements a workaround (exact excerpt as a comment in the code). The docs
specify [clearly, after you struggle for a while] that the offset isn't relative
to state base. This actually makes sense. This fixes hangs on SKL.
Buffer #0 is meant to be used for normal uniforms.
Buffer #1 is typically used for gather constants when using RS.
Buffer #1-#3 could be used to push a bunch of UBO data which would just be
somewhere in memory, and not relative to the dynamic state.
NOTE: I've moved away from the ternary operator for the new gen9 conditions.
Admittedly it's probably not great to do this, but I really want to fix this all
up in the subsequent patch and doing it here makes that diff a lot nicer. I want
to split out the gen8/9 code to make the function a bit more readable, but to
keep this easily cherry-pickable I am doing this fix first. If we decide not to
merge the cleanup patch then I can revisit this.
Cc: "10.5 10.6"
Signed-off-by: Ben Widawsky
Reviewed-by: Anuj Phogat
Tested-by: Valtteri Rantala
---
src/mesa/drivers/dri/i965/gen7_vs_state.c | 48 -
1 file changed, 41 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c
b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index 278b3ec..4b17d06 100644
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -43,18 +43,52 @@ gen7_upload_constant_state(struct brw_context *brw,
int dwords = brw->gen >= 8 ? 11 : 7;
BEGIN_BATCH(dwords);
OUT_BATCH(opcode << 16 | (dwords - 2));
- OUT_BATCH(active ? stage_state->push_const_size : 0);
- OUT_BATCH(0);
+
+ /* Workaround for SKL+ (we use option #2 until we have a need for more
+* constant buffers). This comes from the documentation for
3DSTATE_CONSTANT_*
+*
+* The driver must ensure The following case does not occur without a flush
+* to the 3D engine: 3DSTATE_CONSTANT_* with buffer 3 read length equal to
+* zero committed followed by a 3DSTATE_CONSTANT_* with buffer 0 read length
+* not equal to zero committed. Possible ways to avoid this condition
+* include:
+* 1. always force buffer 3 to have a non zero read length
+* 2. always force buffer 0 to a zero read length
+*/
+ if (brw->gen >= 9 && active) {
+ OUT_BATCH(0);
+ OUT_BATCH(stage_state->push_const_size);
+ } else {
+ OUT_BATCH(active ? stage_state->push_const_size : 0);
+ OUT_BATCH(0);
+ }
/* Pointer to the constant buffer. Covered by the set of state flags
* from gen6_prepare_wm_contants
*/
- OUT_BATCH(active ? (stage_state->push_const_offset | mocs) : 0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- if (brw->gen >= 8) {
+ if (brw->gen >= 9 && active) {
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ /* XXX: When using buffers other than 0, you need to specify the
+ * graphics virtual address regardless of INSPM/debug bits
+ */
+ OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_RENDER, 0,
+ stage_state->push_const_offset);
OUT_BATCH(0);
OUT_BATCH(0);
+ } else if (brw->gen>= 8) {
+ OUT_BATCH(active ? (stage_state->push_const_offset | mocs) : 0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ } else {
+ OUT_BATCH(active ? (stage_state->push_const_offset | mocs) : 0);
+ OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
}
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Mesa (master): mesa: use _mesa_lookup_enum_by_nr() in print_array()
Module: Mesa Branch: master Commit: 2b07b8d104a93c26ac92edb3ba72328cdc2dcb52 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b07b8d104a93c26ac92edb3ba72328cdc2dcb52 Author: Brian Paul Date: Mon Jun 22 08:29:49 2015 -0600 mesa: use _mesa_lookup_enum_by_nr() in print_array() Print GL_FLOAT, etc. instead of hex value. Reviewed-by: Ilia Mirkin --- src/mesa/main/varray.c |8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mesa/main/varray.c b/src/mesa/main/varray.c index 7389037..ebdd9ea 100644 --- a/src/mesa/main/varray.c +++ b/src/mesa/main/varray.c @@ -2309,10 +2309,10 @@ print_array(const char *name, GLint index, const struct gl_client_array *array) fprintf(stderr, " %s[%d]: ", name, index); else fprintf(stderr, " %s: ", name); - fprintf(stderr, "Ptr=%p, Type=0x%x, Size=%d, ElemSize=%u, Stride=%d, Buffer=%u(Size %lu)\n", - array->Ptr, array->Type, array->Size, - array->_ElementSize, array->StrideB, - array->BufferObj->Name, (unsigned long) array->BufferObj->Size); + fprintf(stderr, "Ptr=%p, Type=%s, Size=%d, ElemSize=%u, Stride=%d, Buffer=%u(Size %lu)\n", + array->Ptr, _mesa_lookup_enum_by_nr(array->Type), array->Size, + array->_ElementSize, array->StrideB, array->BufferObj->Name, + (unsigned long) array->BufferObj->Size); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): ilo: add ilo_state_vf_valid_element_format()
Module: Mesa
Branch: master
Commit: aa3e5e0dded4d732ea46083201940bd23214785c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa3e5e0dded4d732ea46083201940bd23214785c
Author: Chia-I Wu
Date: Mon Jun 22 13:15:24 2015 +0800
ilo: add ilo_state_vf_valid_element_format()
Check if a surface format can be used as a VE format.
---
src/gallium/drivers/ilo/core/ilo_format.c | 126 +--
src/gallium/drivers/ilo/core/ilo_state_vf.c | 126 +++
src/gallium/drivers/ilo/core/ilo_state_vf.h |4 +
3 files changed, 132 insertions(+), 124 deletions(-)
diff --git a/src/gallium/drivers/ilo/core/ilo_format.c
b/src/gallium/drivers/ilo/core/ilo_format.c
index 280e499..c1b001b 100644
--- a/src/gallium/drivers/ilo/core/ilo_format.c
+++ b/src/gallium/drivers/ilo/core/ilo_format.c
@@ -26,12 +26,9 @@
*/
#include "genhw/genhw.h"
+#include "ilo_state_vf.h"
#include "ilo_format.h"
-struct ilo_vf_cap {
- int vertex_element;
-};
-
struct ilo_sol_cap {
int buffer;
};
@@ -54,122 +51,6 @@ struct ilo_dp_cap {
* This table is based on:
*
* - the Sandy Bridge PRM, volume 4 part 1, page 88-97
- * - the Ivy Bridge PRM, volume 2 part 1, page 97-99
- * - the Haswell PRM, volume 7, page 467-470
- */
-static const struct ilo_vf_cap ilo_vf_caps[] = {
-#define CAP(vertex_element) { ILO_GEN(vertex_element) }
- [GEN6_FORMAT_R32G32B32A32_FLOAT] = CAP( 1),
- [GEN6_FORMAT_R32G32B32A32_SINT]= CAP( 1),
- [GEN6_FORMAT_R32G32B32A32_UINT]= CAP( 1),
- [GEN6_FORMAT_R32G32B32A32_UNORM] = CAP( 1),
- [GEN6_FORMAT_R32G32B32A32_SNORM] = CAP( 1),
- [GEN6_FORMAT_R64G64_FLOAT] = CAP( 1),
- [GEN6_FORMAT_R32G32B32A32_SSCALED] = CAP( 1),
- [GEN6_FORMAT_R32G32B32A32_USCALED] = CAP( 1),
- [GEN6_FORMAT_R32G32B32A32_SFIXED] = CAP(7.5),
- [GEN6_FORMAT_R32G32B32_FLOAT] = CAP( 1),
- [GEN6_FORMAT_R32G32B32_SINT] = CAP( 1),
- [GEN6_FORMAT_R32G32B32_UINT] = CAP( 1),
- [GEN6_FORMAT_R32G32B32_UNORM] = CAP( 1),
- [GEN6_FORMAT_R32G32B32_SNORM] = CAP( 1),
- [GEN6_FORMAT_R32G32B32_SSCALED]= CAP( 1),
- [GEN6_FORMAT_R32G32B32_USCALED]= CAP( 1),
- [GEN6_FORMAT_R32G32B32_SFIXED] = CAP(7.5),
- [GEN6_FORMAT_R16G16B16A16_UNORM] = CAP( 1),
- [GEN6_FORMAT_R16G16B16A16_SNORM] = CAP( 1),
- [GEN6_FORMAT_R16G16B16A16_SINT]= CAP( 1),
- [GEN6_FORMAT_R16G16B16A16_UINT]= CAP( 1),
- [GEN6_FORMAT_R16G16B16A16_FLOAT] = CAP( 1),
- [GEN6_FORMAT_R32G32_FLOAT] = CAP( 1),
- [GEN6_FORMAT_R32G32_SINT] = CAP( 1),
- [GEN6_FORMAT_R32G32_UINT] = CAP( 1),
- [GEN6_FORMAT_R32G32_UNORM] = CAP( 1),
- [GEN6_FORMAT_R32G32_SNORM] = CAP( 1),
- [GEN6_FORMAT_R64_FLOAT]= CAP( 1),
- [GEN6_FORMAT_R16G16B16A16_SSCALED] = CAP( 1),
- [GEN6_FORMAT_R16G16B16A16_USCALED] = CAP( 1),
- [GEN6_FORMAT_R32G32_SSCALED] = CAP( 1),
- [GEN6_FORMAT_R32G32_USCALED] = CAP( 1),
- [GEN6_FORMAT_R32G32_SFIXED]= CAP(7.5),
- [GEN6_FORMAT_B8G8R8A8_UNORM] = CAP( 1),
- [GEN6_FORMAT_R10G10B10A2_UNORM]= CAP( 1),
- [GEN6_FORMAT_R10G10B10A2_UINT] = CAP( 1),
- [GEN6_FORMAT_R10G10B10_SNORM_A2_UNORM] = CAP( 1),
- [GEN6_FORMAT_R8G8B8A8_UNORM] = CAP( 1),
- [GEN6_FORMAT_R8G8B8A8_SNORM] = CAP( 1),
- [GEN6_FORMAT_R8G8B8A8_SINT]= CAP( 1),
- [GEN6_FORMAT_R8G8B8A8_UINT]= CAP( 1),
- [GEN6_FORMAT_R16G16_UNORM] = CAP( 1),
- [GEN6_FORMAT_R16G16_SNORM] = CAP( 1),
- [GEN6_FORMAT_R16G16_SINT] = CAP( 1),
- [GEN6_FORMAT_R16G16_UINT] = CAP( 1),
- [GEN6_FORMAT_R16G16_FLOAT] = CAP( 1),
- [GEN6_FORMAT_B10G10R10A2_UNORM]= CAP(7.5),
- [GEN6_FORMAT_R11G11B10_FLOAT] = CAP( 1),
- [GEN6_FORMAT_R32_SINT] = CAP( 1),
- [GEN6_FORMAT_R32_UINT] = CAP( 1),
- [GEN6_FORMAT_R32_FLOAT]= CAP( 1),
- [GEN6_FORMAT_R32_UNORM]= CAP( 1),
- [GEN6_FORMAT_R32_SNORM]= CAP( 1),
- [GEN6_FORMAT_R10G10B10X2_USCALED] = CAP( 1),
- [GEN6_FORMAT_R8G8B8A8_SSCALED] = CAP( 1),
- [GEN6_FORMAT_R8G8B8A8_USCALED] = CAP( 1),
- [GEN6_FORMAT_R16G16_SSCALED] = CAP( 1),
- [GEN6_FORMAT_R16G16_USCALED] = CAP( 1),
- [GEN6_FORMAT_R32_SSCALED] = CAP( 1),
- [GEN6_FORMAT_R32_USCALED] = CAP( 1),
- [GEN6_FORMAT_R8G8_UNORM] = CAP( 1),
- [GEN6_FORMAT_R8G8_SNORM] = CAP( 1),
- [GEN6_FORMAT_R8G8_SINT]= CAP( 1),
- [GEN6_FORMAT_R8G8_UINT]= CAP( 1),
- [GEN6_FORMAT_R16_UNORM]= CAP( 1),
- [GEN6_FORMAT_R16_SNORM]=
Mesa (master): ilo: align vertex buffer size in buf_create()
Module: Mesa
Branch: master
Commit: 58f95b332d0cbad226f5bb2e96cd0cad8864fe79
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=58f95b332d0cbad226f5bb2e96cd0cad8864fe79
Author: Chia-I Wu
Date: Mon Jun 22 14:15:52 2015 +0800
ilo: align vertex buffer size in buf_create()
With ilo_format.[ch] moved out of core, the aligning of vertex buffers does
not belong to core anymore.
---
src/gallium/drivers/ilo/core/ilo_buffer.h | 17 -
src/gallium/drivers/ilo/ilo_resource.c| 22 --
2 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/src/gallium/drivers/ilo/core/ilo_buffer.h
b/src/gallium/drivers/ilo/core/ilo_buffer.h
index 99c7b01..ca3c61f 100644
--- a/src/gallium/drivers/ilo/core/ilo_buffer.h
+++ b/src/gallium/drivers/ilo/core/ilo_buffer.h
@@ -59,23 +59,6 @@ ilo_buffer_init(struct ilo_buffer *buf, const struct ilo_dev
*dev,
*/
if (bind & PIPE_BIND_SAMPLER_VIEW)
buf->bo_size = align(buf->bo_size, 256) + 16;
-
- if ((bind & PIPE_BIND_VERTEX_BUFFER) && ilo_dev_gen(dev) < ILO_GEN(7.5)) {
- /*
- * As noted in ilo_format_translate(), we treat some 3-component formats
- * as 4-component formats to work around hardware limitations. Imagine
- * the case where the vertex buffer holds a single
- * PIPE_FORMAT_R16G16B16_FLOAT vertex, and buf->bo_size is 6. The
- * hardware would fail to fetch it at boundary check because the vertex
- * buffer is expected to hold a PIPE_FORMAT_R16G16B16A16_FLOAT vertex
- * and that takes at least 8 bytes.
- *
- * For the workaround to work, we should add 2 to the bo size. But that
- * would waste a page when the bo size is already page aligned. Let's
- * round it to page size for now and revisit this when needed.
- */
- buf->bo_size = align(buf->bo_size, 4096);
- }
}
#endif /* ILO_BUFFER_H */
diff --git a/src/gallium/drivers/ilo/ilo_resource.c
b/src/gallium/drivers/ilo/ilo_resource.c
index b6f5d26..be9fd10 100644
--- a/src/gallium/drivers/ilo/ilo_resource.c
+++ b/src/gallium/drivers/ilo/ilo_resource.c
@@ -443,6 +443,7 @@ buf_create(struct pipe_screen *screen, const struct
pipe_resource *templ)
{
const struct ilo_screen *is = ilo_screen(screen);
struct ilo_buffer_resource *buf;
+ unsigned size;
buf = CALLOC_STRUCT(ilo_buffer_resource);
if (!buf)
@@ -452,8 +453,25 @@ buf_create(struct pipe_screen *screen, const struct
pipe_resource *templ)
buf->base.screen = screen;
pipe_reference_init(&buf->base.reference, 1);
- ilo_buffer_init(&buf->buffer, &is->dev,
- templ->width0, templ->bind, templ->flags);
+ size = templ->width0;
+
+ /*
+* As noted in ilo_format_translate(), we treat some 3-component formats as
+* 4-component formats to work around hardware limitations. Imagine the
+* case where the vertex buffer holds a single PIPE_FORMAT_R16G16B16_FLOAT
+* vertex, and buf->bo_size is 6. The hardware would fail to fetch it at
+* boundary check because the vertex buffer is expected to hold a
+* PIPE_FORMAT_R16G16B16A16_FLOAT vertex and that takes at least 8 bytes.
+*
+* For the workaround to work, we should add 2 to the bo size. But that
+* would waste a page when the bo size is already page aligned. Let's
+* round it to page size for now and revisit this when needed.
+*/
+ if ((templ->bind & PIPE_BIND_VERTEX_BUFFER) &&
+ ilo_dev_gen(&is->dev) < ILO_GEN(7.5))
+ size = align(size, 4096);
+
+ ilo_buffer_init(&buf->buffer, &is->dev, size, templ->bind, templ->flags);
if (buf->buffer.bo_size < templ->width0 ||
buf->buffer.bo_size > ilo_max_resource_size ||
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Mesa (master): ilo: emit 3DPRIMITIVE from gen6_3dprimitive_info
Module: Mesa
Branch: master
Commit: 878714142999ca6a6aa03d962e01da94d44c8574
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=878714142999ca6a6aa03d962e01da94d44c8574
Author: Chia-I Wu
Date: Mon Jun 22 14:27:19 2015 +0800
ilo: emit 3DPRIMITIVE from gen6_3dprimitive_info
It allows us to remove ilo_ib_state::draw_start_offset and
ILO_PRIM_RECTANGLES. gen6_3d_translate_pipe_prim() is also replaced by
ilo_translate_draw_mode().
---
src/gallium/drivers/ilo/core/ilo_builder_3d.h | 54 +++
src/gallium/drivers/ilo/core/ilo_builder_3d_top.h | 29 ---
src/gallium/drivers/ilo/core/ilo_core.h |3 --
src/gallium/drivers/ilo/ilo_blitter.h |2 +-
src/gallium/drivers/ilo/ilo_blitter_rectlist.c|6 +--
src/gallium/drivers/ilo/ilo_render_gen.h |9 ++--
src/gallium/drivers/ilo/ilo_render_gen6.c |4 +-
src/gallium/drivers/ilo/ilo_render_gen7.c |4 +-
src/gallium/drivers/ilo/ilo_render_gen8.c |5 +-
src/gallium/drivers/ilo/ilo_state.c | 58 -
src/gallium/drivers/ilo/ilo_state.h |4 +-
11 files changed, 91 insertions(+), 87 deletions(-)
diff --git a/src/gallium/drivers/ilo/core/ilo_builder_3d.h
b/src/gallium/drivers/ilo/core/ilo_builder_3d.h
index 8d8a795..fb8b53c 100644
--- a/src/gallium/drivers/ilo/core/ilo_builder_3d.h
+++ b/src/gallium/drivers/ilo/core/ilo_builder_3d.h
@@ -35,41 +35,45 @@
#include "ilo_builder_3d_top.h"
#include "ilo_builder_3d_bottom.h"
+struct gen6_3dprimitive_info {
+ enum gen_3dprim_type topology;
+ bool indexed;
+
+ uint32_t vertex_count;
+ uint32_t vertex_start;
+ uint32_t instance_count;
+ uint32_t instance_start;
+ int32_t vertex_base;
+};
+
static inline void
gen6_3DPRIMITIVE(struct ilo_builder *builder,
- const struct pipe_draw_info *info,
- int64_t start_offset)
+ const struct gen6_3dprimitive_info *info)
{
const uint8_t cmd_len = 6;
- const int prim = gen6_3d_translate_pipe_prim(info->mode);
- const int vb_access = (info->indexed) ?
- GEN6_3DPRIM_DW0_ACCESS_RANDOM : GEN6_3DPRIM_DW0_ACCESS_SEQUENTIAL;
uint32_t *dw;
ILO_DEV_ASSERT(builder->dev, 6, 6);
ilo_builder_batch_pointer(builder, cmd_len, &dw);
- dw[0] = GEN6_RENDER_CMD(3D, 3DPRIMITIVE) |
- vb_access |
- prim << GEN6_3DPRIM_DW0_TYPE__SHIFT |
- (cmd_len - 2);
- dw[1] = info->count;
- dw[2] = info->start + start_offset;
+ dw[0] = GEN6_RENDER_CMD(3D, 3DPRIMITIVE) | (cmd_len - 2) |
+ info->topology << GEN6_3DPRIM_DW0_TYPE__SHIFT;
+ if (info->indexed)
+ dw[0] |= GEN6_3DPRIM_DW0_ACCESS_RANDOM;
+
+ dw[1] = info->vertex_count;
+ dw[2] = info->vertex_start;
dw[3] = info->instance_count;
- dw[4] = info->start_instance;
- dw[5] = info->index_bias;
+ dw[4] = info->instance_start;
+ dw[5] = info->vertex_base;
}
static inline void
gen7_3DPRIMITIVE(struct ilo_builder *builder,
- const struct pipe_draw_info *info,
- int64_t start_offset)
+ const struct gen6_3dprimitive_info *info)
{
const uint8_t cmd_len = 7;
- const int prim = gen6_3d_translate_pipe_prim(info->mode);
- const int vb_access = (info->indexed) ?
- GEN7_3DPRIM_DW1_ACCESS_RANDOM : GEN7_3DPRIM_DW1_ACCESS_SEQUENTIAL;
uint32_t *dw;
ILO_DEV_ASSERT(builder->dev, 7, 8);
@@ -77,12 +81,16 @@ gen7_3DPRIMITIVE(struct ilo_builder *builder,
ilo_builder_batch_pointer(builder, cmd_len, &dw);
dw[0] = GEN6_RENDER_CMD(3D, 3DPRIMITIVE) | (cmd_len - 2);
- dw[1] = vb_access | prim;
- dw[2] = info->count;
- dw[3] = info->start + start_offset;
+
+ dw[1] = info->topology << GEN7_3DPRIM_DW1_TYPE__SHIFT;
+ if (info->indexed)
+ dw[1] |= GEN7_3DPRIM_DW1_ACCESS_RANDOM;
+
+ dw[2] = info->vertex_count;
+ dw[3] = info->vertex_start;
dw[4] = info->instance_count;
- dw[5] = info->start_instance;
- dw[6] = info->index_bias;
+ dw[5] = info->instance_start;
+ dw[6] = info->vertex_base;
}
#endif /* ILO_BUILDER_3D_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_builder_3d_top.h
b/src/gallium/drivers/ilo/core/ilo_builder_3d_top.h
index 42d171f..8d30095 100644
--- a/src/gallium/drivers/ilo/core/ilo_builder_3d_top.h
+++ b/src/gallium/drivers/ilo/core/ilo_builder_3d_top.h
@@ -217,35 +217,6 @@ gen6_3DSTATE_VF_STATISTICS(struct ilo_builder *builder,
ilo_builder_batch_write(builder, cmd_len, &dw0);
}
-/**
- * Translate a pipe primitive type to the matching hardware primitive type.
- */
-static inline int
-gen6_3d_translate_pipe_prim(unsigned prim)
-{
- static const int prim_mapping[ILO_PRIM_MAX] = {
- [PIPE_PRIM_POINTS] = GEN6_3DPRIM_POINTLIST,
- [PIPE_PRIM_LINES] = GEN6_3DPRIM_LINELIST,
- [PIPE_PRIM_LINE_LOOP] = GEN6_3DPRIM_LINELOOP,
- [PIPE_PRIM_LINE_STRIP]
Mesa (master): ilo: add ilo_state_surface_valid_format()
Module: Mesa
Branch: master
Commit: 3547bb078307995e92d509037bc86af7fd60c8c3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3547bb078307995e92d509037bc86af7fd60c8c3
Author: Chia-I Wu
Date: Mon Jun 22 13:37:05 2015 +0800
ilo: add ilo_state_surface_valid_format()
Check if a surface format can be used for the specified access type.
---
src/gallium/drivers/ilo/Makefile.sources |1 +
src/gallium/drivers/ilo/core/ilo_format.c | 291 +---
src/gallium/drivers/ilo/core/ilo_state_surface.h |5 +
.../drivers/ilo/core/ilo_state_surface_format.c| 351
4 files changed, 364 insertions(+), 284 deletions(-)
diff --git a/src/gallium/drivers/ilo/Makefile.sources
b/src/gallium/drivers/ilo/Makefile.sources
index 95b6b7a..ed024e3 100644
--- a/src/gallium/drivers/ilo/Makefile.sources
+++ b/src/gallium/drivers/ilo/Makefile.sources
@@ -35,6 +35,7 @@ C_SOURCES := \
core/ilo_state_sol.c \
core/ilo_state_sol.h \
core/ilo_state_surface.c \
+ core/ilo_state_surface_format.c \
core/ilo_state_surface.h \
core/ilo_state_urb.c \
core/ilo_state_urb.h \
diff --git a/src/gallium/drivers/ilo/core/ilo_format.c
b/src/gallium/drivers/ilo/core/ilo_format.c
index c1b001b..b96f71c 100644
--- a/src/gallium/drivers/ilo/core/ilo_format.c
+++ b/src/gallium/drivers/ilo/core/ilo_format.c
@@ -26,264 +26,10 @@
*/
#include "genhw/genhw.h"
+#include "ilo_state_surface.h"
#include "ilo_state_vf.h"
#include "ilo_format.h"
-struct ilo_sol_cap {
- int buffer;
-};
-
-struct ilo_sampler_cap {
- int sampling;
- int filtering;
- int shadow_map;
- int chroma_key;
-};
-
-struct ilo_dp_cap {
- int rt_write;
- int rt_write_blending;
- int typed_write;
- int media_color_processing;
-};
-
-/*
- * This table is based on:
- *
- * - the Sandy Bridge PRM, volume 4 part 1, page 88-97
- * - the Ivy Bridge PRM, volume 2 part 1, page 195
- * - the Haswell PRM, volume 7, page 535
- */
-static const struct ilo_sol_cap ilo_sol_caps[] = {
-#define CAP(buffer) { ILO_GEN(buffer) }
- [GEN6_FORMAT_R32G32B32A32_FLOAT] = CAP( 1),
- [GEN6_FORMAT_R32G32B32A32_SINT]= CAP( 1),
- [GEN6_FORMAT_R32G32B32A32_UINT]= CAP( 1),
- [GEN6_FORMAT_R32G32B32_FLOAT] = CAP( 1),
- [GEN6_FORMAT_R32G32B32_SINT] = CAP( 1),
- [GEN6_FORMAT_R32G32B32_UINT] = CAP( 1),
- [GEN6_FORMAT_R32G32_FLOAT] = CAP( 1),
- [GEN6_FORMAT_R32G32_SINT] = CAP( 1),
- [GEN6_FORMAT_R32G32_UINT] = CAP( 1),
- [GEN6_FORMAT_R32_SINT] = CAP( 1),
- [GEN6_FORMAT_R32_UINT] = CAP( 1),
- [GEN6_FORMAT_R32_FLOAT]= CAP( 1),
-#undef CAP
-};
-
-/*
- * This table is based on:
- *
- * - the Sandy Bridge PRM, volume 4 part 1, page 88-97
- * - the Ivy Bridge PRM, volume 4 part 1, page 84-87
- */
-static const struct ilo_sampler_cap ilo_sampler_caps[] = {
-#define CAP(sampling, filtering, shadow_map, chroma_key) \
- { ILO_GEN(sampling), ILO_GEN(filtering), ILO_GEN(shadow_map),
ILO_GEN(chroma_key) }
- [GEN6_FORMAT_R32G32B32A32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_R32G32B32A32_SINT]= CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R32G32B32A32_UINT]= CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R32G32B32X32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_R32G32B32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_R32G32B32_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R32G32B32_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16G16B16A16_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R16G16B16A16_SNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R16G16B16A16_SINT]= CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16G16B16A16_UINT]= CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16G16B16A16_FLOAT] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R32G32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_R32G32_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R32G32_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R32_FLOAT_X8X24_TYPELESS] = CAP( 1, 5, 1, 0),
- [GEN6_FORMAT_X32_TYPELESS_G8X24_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_L32A32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_R16G16B16X16_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R16G16B16X16_FLOAT] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_A32X32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_L32X32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_I32X32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_B8G8R8A8_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_B8G8R8A8_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R10G10B10A2_UNORM]= CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R10G10B10A2_U
Mesa (master): ilo: move ilo_format.[ch] out of core
Module: Mesa
Branch: master
Commit: 513bc5d90b8e9237bd6a04da5d0dee175ff134f6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=513bc5d90b8e9237bd6a04da5d0dee175ff134f6
Author: Chia-I Wu
Date: Mon Jun 22 14:06:13 2015 +0800
ilo: move ilo_format.[ch] out of core
They provide PIPE_FORMAT_x to GEN6_FORMAT_x translation as well as some
convenient helpers. Move them out of core.
---
src/gallium/drivers/ilo/Makefile.sources|4 ++--
src/gallium/drivers/ilo/{core => }/ilo_format.c |4 ++--
src/gallium/drivers/ilo/{core => }/ilo_format.h |4 ++--
src/gallium/drivers/ilo/ilo_screen.c|2 +-
src/gallium/drivers/ilo/ilo_state.c |2 +-
5 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/ilo/Makefile.sources
b/src/gallium/drivers/ilo/Makefile.sources
index ed024e3..e1bbb9a 100644
--- a/src/gallium/drivers/ilo/Makefile.sources
+++ b/src/gallium/drivers/ilo/Makefile.sources
@@ -15,8 +15,6 @@ C_SOURCES := \
core/ilo_debug.h \
core/ilo_dev.c \
core/ilo_dev.h \
- core/ilo_format.c \
- core/ilo_format.h \
core/ilo_image.c \
core/ilo_image.h \
core/ilo_state_cc.c \
@@ -60,6 +58,8 @@ C_SOURCES := \
ilo_cp.h \
ilo_draw.c \
ilo_draw.h \
+ ilo_format.c \
+ ilo_format.h \
ilo_gpgpu.c \
ilo_gpgpu.h \
ilo_public.h \
diff --git a/src/gallium/drivers/ilo/core/ilo_format.c
b/src/gallium/drivers/ilo/ilo_format.c
similarity index 99%
rename from src/gallium/drivers/ilo/core/ilo_format.c
rename to src/gallium/drivers/ilo/ilo_format.c
index b96f71c..ca7e6b5 100644
--- a/src/gallium/drivers/ilo/core/ilo_format.c
+++ b/src/gallium/drivers/ilo/ilo_format.c
@@ -26,8 +26,8 @@
*/
#include "genhw/genhw.h"
-#include "ilo_state_surface.h"
-#include "ilo_state_vf.h"
+#include "core/ilo_state_surface.h"
+#include "core/ilo_state_vf.h"
#include "ilo_format.h"
bool
diff --git a/src/gallium/drivers/ilo/core/ilo_format.h
b/src/gallium/drivers/ilo/ilo_format.h
similarity index 99%
rename from src/gallium/drivers/ilo/core/ilo_format.h
rename to src/gallium/drivers/ilo/ilo_format.h
index 6b73ea1..4e955c0 100644
--- a/src/gallium/drivers/ilo/core/ilo_format.h
+++ b/src/gallium/drivers/ilo/ilo_format.h
@@ -29,8 +29,8 @@
#define ILO_FORMAT_H
#include "genhw/genhw.h"
-#include "ilo_core.h"
-#include "ilo_dev.h"
+
+#include "ilo_common.h"
bool
ilo_format_support_vb(const struct ilo_dev *dev,
diff --git a/src/gallium/drivers/ilo/ilo_screen.c
b/src/gallium/drivers/ilo/ilo_screen.c
index b75a259..9410555 100644
--- a/src/gallium/drivers/ilo/ilo_screen.c
+++ b/src/gallium/drivers/ilo/ilo_screen.c
@@ -31,10 +31,10 @@
#include "vl/vl_decoder.h"
#include "vl/vl_video_buffer.h"
#include "genhw/genhw.h" /* for GEN6_REG_TIMESTAMP */
-#include "core/ilo_format.h"
#include "core/intel_winsys.h"
#include "ilo_context.h"
+#include "ilo_format.h"
#include "ilo_resource.h"
#include "ilo_transfer.h" /* for ILO_TRANSFER_MAP_BUFFER_ALIGNMENT */
#include "ilo_public.h"
diff --git a/src/gallium/drivers/ilo/ilo_state.c
b/src/gallium/drivers/ilo/ilo_state.c
index 62e3180..4252dbe 100644
--- a/src/gallium/drivers/ilo/ilo_state.c
+++ b/src/gallium/drivers/ilo/ilo_state.c
@@ -26,7 +26,6 @@
*/
#include "core/ilo_builder_3d.h" /* for gen6_3d_translate_pipe_prim() */
-#include "core/ilo_format.h"
#include "util/u_dual_blend.h"
#include "util/u_dynarray.h"
#include "util/u_framebuffer.h"
@@ -35,6 +34,7 @@
#include "util/u_upload_mgr.h"
#include "ilo_context.h"
+#include "ilo_format.h"
#include "ilo_resource.h"
#include "ilo_shader.h"
#include "ilo_state.h"
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