Mesa (master): GL: update glext to svn 31811
Module: Mesa
Branch: master
Commit: 3547d9855c2103ecc5001a082965d3dda5d69d34
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3547d9855c2103ecc5001a082965d3dda5d69d34
Author: Dave Airlie airl...@gmail.com
Date: Sun Aug 16 07:37:37 2015 +1000
GL: update glext to svn 31811
This brings in the new ARB extensions.
Acked-by: Chris Forbes chr...@ijw.co.nz
Signed-off-by: Dave Airlie airl...@redhat.com
---
include/GL/glext.h | 294 ++--
1 file changed, 285 insertions(+), 9 deletions(-)
diff --git a/include/GL/glext.h b/include/GL/glext.h
index e5f1d89..907a582 100644
--- a/include/GL/glext.h
+++ b/include/GL/glext.h
@@ -6,7 +6,7 @@ extern C {
#endif
/*
-** Copyright (c) 2013-2014 The Khronos Group Inc.
+** Copyright (c) 2013-2015 The Khronos Group Inc.
**
** Permission is hereby granted, free of charge, to any person obtaining a
** copy of this software and/or associated documentation files (the
@@ -33,7 +33,7 @@ extern C {
** used to make the header, and the header can be found at
** http://www.opengl.org/registry/
**
-** Khronos $Revision: 29735 $ on $Date: 2015-02-02 19:00:01 -0800 (Mon, 02 Feb
2015) $
+** Khronos $Revision: 31811 $ on $Date: 2015-08-10 17:01:11 +1000 (Mon, 10 Aug
2015) $
*/
#if defined(_WIN32) !defined(APIENTRY) !defined(__CYGWIN__)
!defined(__SCITECH_SNAP__)
@@ -53,7 +53,7 @@ extern C {
#define GLAPI extern
#endif
-#define GL_GLEXT_VERSION 20150202
+#define GL_GLEXT_VERSION 20150809
/* Generated C header for:
* API: gl
@@ -1041,6 +1041,22 @@ typedef unsigned short GLhalf;
#define GL_COLOR_ATTACHMENT13 0x8CED
#define GL_COLOR_ATTACHMENT14 0x8CEE
#define GL_COLOR_ATTACHMENT15 0x8CEF
+#define GL_COLOR_ATTACHMENT16 0x8CF0
+#define GL_COLOR_ATTACHMENT17 0x8CF1
+#define GL_COLOR_ATTACHMENT18 0x8CF2
+#define GL_COLOR_ATTACHMENT19 0x8CF3
+#define GL_COLOR_ATTACHMENT20 0x8CF4
+#define GL_COLOR_ATTACHMENT21 0x8CF5
+#define GL_COLOR_ATTACHMENT22 0x8CF6
+#define GL_COLOR_ATTACHMENT23 0x8CF7
+#define GL_COLOR_ATTACHMENT24 0x8CF8
+#define GL_COLOR_ATTACHMENT25 0x8CF9
+#define GL_COLOR_ATTACHMENT26 0x8CFA
+#define GL_COLOR_ATTACHMENT27 0x8CFB
+#define GL_COLOR_ATTACHMENT28 0x8CFC
+#define GL_COLOR_ATTACHMENT29 0x8CFD
+#define GL_COLOR_ATTACHMENT30 0x8CFE
+#define GL_COLOR_ATTACHMENT31 0x8CFF
#define GL_DEPTH_ATTACHMENT 0x8D00
#define GL_STENCIL_ATTACHMENT 0x8D20
#define GL_FRAMEBUFFER0x8D40
@@ -2859,6 +2875,17 @@ GLAPI void APIENTRY glTextureBarrier (void);
#define GL_ARB_ES3_1_compatibility 1
#endif /* GL_ARB_ES3_1_compatibility */
+#ifndef GL_ARB_ES3_2_compatibility
+#define GL_ARB_ES3_2_compatibility 1
+#define GL_PRIMITIVE_BOUNDING_BOX_ARB 0x92BE
+#define GL_MULTISAMPLE_LINE_WIDTH_RANGE_ARB 0x9381
+#define GL_MULTISAMPLE_LINE_WIDTH_GRANULARITY_ARB 0x9382
+typedef void (APIENTRYP PFNGLPRIMITIVEBOUNDINGBOXARBPROC) (GLfloat minX,
GLfloat minY, GLfloat minZ, GLfloat minW, GLfloat maxX, GLfloat maxY, GLfloat
maxZ, GLfloat maxW);
+#ifdef GL_GLEXT_PROTOTYPES
+GLAPI void APIENTRY glPrimitiveBoundingBoxARB (GLfloat minX, GLfloat minY,
GLfloat minZ, GLfloat minW, GLfloat maxX, GLfloat maxY, GLfloat maxZ, GLfloat
maxW);
+#endif
+#endif /* GL_ARB_ES3_2_compatibility */
+
#ifndef GL_ARB_ES3_compatibility
#define GL_ARB_ES3_compatibility 1
#endif /* GL_ARB_ES3_compatibility */
@@ -3272,6 +3299,10 @@ GLAPI GLboolean APIENTRY glIsProgramARB (GLuint program);
#define GL_FRAGMENT_SHADER_DERIVATIVE_HINT_ARB 0x8B8B
#endif /* GL_ARB_fragment_shader */
+#ifndef GL_ARB_fragment_shader_interlock
+#define GL_ARB_fragment_shader_interlock 1
+#endif /* GL_ARB_fragment_shader_interlock */
+
#ifndef GL_ARB_framebuffer_no_attachments
#define GL_ARB_framebuffer_no_attachments 1
#endif /* GL_ARB_framebuffer_no_attachments */
@@ -3332,6 +3363,91 @@ GLAPI void APIENTRY glFramebufferTextureFaceARB (GLenum
target, GLenum attachmen
#define GL_ARB_gpu_shader_fp64 1
#endif /* GL_ARB_gpu_shader_fp64 */
+#ifndef GL_ARB_gpu_shader_int64
+#define GL_ARB_gpu_shader_int64 1
+#define GL_INT64_ARB 0x140E
+#define GL_INT64_VEC2_ARB 0x8FE9
+#define GL_INT64_VEC3_ARB 0x8FEA
+#define GL_INT64_VEC4_ARB 0x8FEB
+#define GL_UNSIGNED_INT64_VEC2_ARB0x8FF5
+#define GL_UNSIGNED_INT64_VEC3_ARB0x8FF6
+#define GL_UNSIGNED_INT64_VEC4_ARB0x8FF7
+typedef void (APIENTRYP PFNGLUNIFORM1I64ARBPROC) (GLint location, GLint64 x);
+typedef void (APIENTRYP PFNGLUNIFORM2I64ARBPROC) (GLint location, GLint64 x,
GLint64 y);
+typedef void (APIENTRYP PFNGLUNIFORM3I64ARBPROC) (GLint location, GLint64 x,
GLint64 y, GLint64 z);
+typedef void (APIENTRYP PFNGLUNIFORM4I64ARBPROC) (GLint location,
Mesa (master): glsl: interleave constant propagation and folding
Module: Mesa
Branch: master
Commit: dd6a6dbaf707c120f6db38036985fcc258ebe294
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd6a6dbaf707c120f6db38036985fcc258ebe294
Author: Timothy Arceri t_arc...@yahoo.com.au
Date: Sun Aug 16 14:26:23 2015 +1000
glsl: interleave constant propagation and folding
The constant folding pass can take a long time to complete
so rather than running through the entire pass each time
a new constant is propagated (and vice versa) interleave them.
This change helps ES31-CTS.arrays_of_arrays.InteractionFunctionCalls1
go from around 2 min - 23 sec.
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/glsl/opt_constant_propagation.cpp | 45 +++--
1 file changed, 43 insertions(+), 2 deletions(-)
diff --git a/src/glsl/opt_constant_propagation.cpp
b/src/glsl/opt_constant_propagation.cpp
index 10be8e8..5221417 100644
--- a/src/glsl/opt_constant_propagation.cpp
+++ b/src/glsl/opt_constant_propagation.cpp
@@ -110,6 +110,8 @@ public:
virtual ir_visitor_status visit_enter(class ir_if *);
void add_constant(ir_assignment *ir);
+ void constant_folding(ir_rvalue **rvalue);
+ void constant_propagation(ir_rvalue **rvalue);
void kill(ir_variable *ir, unsigned write_mask);
void handle_if_block(exec_list *instructions);
void handle_rvalue(ir_rvalue **rvalue);
@@ -132,8 +134,38 @@ public:
void
-ir_constant_propagation_visitor::handle_rvalue(ir_rvalue **rvalue)
-{
+ir_constant_propagation_visitor::constant_folding(ir_rvalue **rvalue) {
+
+ if (*rvalue == NULL || (*rvalue)-ir_type == ir_type_constant)
+ return;
+
+ /* Note that we visit rvalues one leaving. So if an expression has a
+* non-constant operand, no need to go looking down it to find if it's
+* constant. This cuts the time of this pass down drastically.
+*/
+ ir_expression *expr = (*rvalue)-as_expression();
+ if (expr) {
+ for (unsigned int i = 0; i expr-get_num_operands(); i++) {
+if (!expr-operands[i]-as_constant())
+ return;
+ }
+ }
+
+ /* Ditto for swizzles. */
+ ir_swizzle *swiz = (*rvalue)-as_swizzle();
+ if (swiz !swiz-val-as_constant())
+ return;
+
+ ir_constant *constant = (*rvalue)-constant_expression_value();
+ if (constant) {
+ *rvalue = constant;
+ this-progress = true;
+ }
+}
+
+void
+ir_constant_propagation_visitor::constant_propagation(ir_rvalue **rvalue) {
+
if (this-in_assignee || !*rvalue)
return;
@@ -216,6 +248,13 @@ ir_constant_propagation_visitor::handle_rvalue(ir_rvalue
**rvalue)
this-progress = true;
}
+void
+ir_constant_propagation_visitor::handle_rvalue(ir_rvalue **rvalue)
+{
+ constant_propagation(rvalue);
+ constant_folding(rvalue);
+}
+
ir_visitor_status
ir_constant_propagation_visitor::visit_enter(ir_function_signature *ir)
{
@@ -243,6 +282,8 @@
ir_constant_propagation_visitor::visit_enter(ir_function_signature *ir)
ir_visitor_status
ir_constant_propagation_visitor::visit_leave(ir_assignment *ir)
{
+ constant_folding(ir-rhs);
+
if (this-in_assignee)
return visit_continue;
___
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Mesa (master): glsl: fix binding validation for interface blocks
Module: Mesa
Branch: master
Commit: ad89748541159968787dce02bb9c19d9367fddc6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad89748541159968787dce02bb9c19d9367fddc6
Author: Timothy Arceri t_arc...@yahoo.com.au
Date: Wed May 27 20:12:42 2015 +1000
glsl: fix binding validation for interface blocks
V2: rebase on SSBO changes
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/glsl/ast_to_hir.cpp | 30 ++
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index e8b61ae..c7ce409 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -2098,10 +2098,10 @@ validate_matrix_layout_for_type(struct
_mesa_glsl_parse_state *state,
static bool
validate_binding_qualifier(struct _mesa_glsl_parse_state *state,
YYLTYPE *loc,
- ir_variable *var,
+ const glsl_type *type,
const ast_type_qualifier *qual)
{
- if (var-data.mode != ir_var_uniform var-data.mode !=
ir_var_shader_storage) {
+ if (!qual-flags.q.uniform !qual-flags.q.buffer) {
_mesa_glsl_error(loc, state,
the \binding\ qualifier only applies to uniforms and
shader storage buffer objects);
@@ -2114,10 +2114,11 @@ validate_binding_qualifier(struct
_mesa_glsl_parse_state *state,
}
const struct gl_context *const ctx = state-ctx;
- unsigned elements = var-type-is_array() ? var-type-length : 1;
+ unsigned elements = type-is_array() ? type-length : 1;
unsigned max_index = qual-binding + elements - 1;
+ const glsl_type *base_type = type-without_array();
- if (var-type-is_interface()) {
+ if (base_type-is_interface()) {
/* UBOs. From page 60 of the GLSL 4.20 specification:
* If the binding point for any uniform block instance is less than
zero,
* or greater than or equal to the implementation-dependent maximum
@@ -2128,7 +2129,7 @@ validate_binding_qualifier(struct _mesa_glsl_parse_state
*state,
*
* The implementation-dependent maximum is
GL_MAX_UNIFORM_BUFFER_BINDINGS.
*/
- if (var-data.mode == ir_var_uniform
+ if (qual-flags.q.uniform
max_index = ctx-Const.MaxUniformBufferBindings) {
_mesa_glsl_error(loc, state, layout(binding = %d) for %d UBOs
exceeds
the maximum number of UBO binding points (%d),
@@ -2136,6 +2137,7 @@ validate_binding_qualifier(struct _mesa_glsl_parse_state
*state,
ctx-Const.MaxUniformBufferBindings);
return false;
}
+
/* SSBOs. From page 67 of the GLSL 4.30 specification:
* If the binding point for any uniform or shader storage block instance
* is less than zero, or greater than or equal to the
@@ -2145,7 +2147,7 @@ validate_binding_qualifier(struct _mesa_glsl_parse_state
*state,
* N, all elements of the array from binding through binding + N – 1
must
* be within this range.
*/
- if (var-data.mode == ir_var_shader_storage
+ if (qual-flags.q.buffer
max_index = ctx-Const.MaxShaderStorageBufferBindings) {
_mesa_glsl_error(loc, state, layout(binding = %d) for %d SSBOs
exceeds
the maximum number of SSBO binding points (%d),
@@ -2153,8 +2155,7 @@ validate_binding_qualifier(struct _mesa_glsl_parse_state
*state,
ctx-Const.MaxShaderStorageBufferBindings);
return false;
}
- } else if (var-type-is_sampler() ||
- (var-type-is_array()
var-type-fields.array-is_sampler())) {
+ } else if (base_type-is_sampler()) {
/* Samplers. From page 63 of the GLSL 4.20 specification:
* If the binding is less than zero, or greater than or equal to the
* implementation-dependent maximum supported number of units, a
@@ -2171,7 +2172,7 @@ validate_binding_qualifier(struct _mesa_glsl_parse_state
*state,
return false;
}
- } else if (var-type-contains_atomic()) {
+ } else if (base_type-contains_atomic()) {
assert(ctx-Const.MaxAtomicBufferBindings =
MAX_COMBINED_ATOMIC_BUFFERS);
if (unsigned(qual-binding) = ctx-Const.MaxAtomicBufferBindings) {
_mesa_glsl_error(loc, state, layout(binding = %d) exceeds the
@@ -2181,8 +2182,7 @@ validate_binding_qualifier(struct _mesa_glsl_parse_state
*state,
return false;
}
- } else if (state-is_version(420, 310)
- var-type-without_array()-is_image()) {
+ } else if (state-is_version(420, 310) base_type-is_image()) {
assert(ctx-Const.MaxImageUnits = MAX_IMAGE_UNITS);
if (max_index = ctx-Const.MaxImageUnits) {
_mesa_glsl_error(loc, state, Image binding %d exceeds the
@@ -2783,7 +2783,7 @@ apply_type_qualifier_to_variable(const struct
ast_type_qualifier *qual,
}
Mesa (master): 22 new commits
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f6c622f58432b0c3cb80bc2ed41e314abf876e03 Author: Francisco Jerez curroje...@riseup.net Date: Thu Aug 20 13:46:53 2015 +0300 docs: Mark GLES 3.1 image load/store as done on i965. URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5070c801c4885521df17a65c297f24ae628d414 Author: Francisco Jerez curroje...@riseup.net Date: Wed Aug 19 14:42:50 2015 +0300 mesa: Add ES31 API tag for the extension table. I'll mark the OES_shader_image_atomic extension entry with this tag to make sure that we don't expose it on earlier GLES API versions accidentally, because according to the extension: OpenGL ES 3.1 and GLSL ES 3.10 are required. Reviewed-by: Tapani Pälli tapani.pa...@intel.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6379f5cb2ab7c5ae3f3769204f95088e35c53217 Author: Francisco Jerez curroje...@riseup.net Date: Mon Aug 17 01:47:50 2015 +0300 glsl: Parse the allowed image format qualifiers in GLSL ES 3.1. This includes the minimum required desktop/ES GLSL version in the format qualifier table in anticipation of new GLSL versions extending the set of supported image formats. According to section 4.4.7 of the GLSL ES 3.1 spec: The format layout qualifier identifiers for image variable declarations are: [...] rgba32f rgba16f r32f rgba8 rgba8_snorm [...] rgba32i rgba16i rgba8i r32i [...] rgba32ui rgba16ui rgba8ui r32ui Reviewed-by: Tapani Pälli tapani.pa...@intel.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e3fb2e1f0e160573c3d164818f556c7f6725835e Author: Francisco Jerez curroje...@riseup.net Date: Mon Aug 17 19:12:00 2015 +0300 glsl: Recognise image memory qualifiers in GLSL ES 3.1. Reviewed-by: Tapani Pälli tapani.pa...@intel.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=307c382c1b514629c342587d2f320f5491de9b65 Author: Francisco Jerez curroje...@riseup.net Date: Mon Aug 17 17:42:30 2015 +0300 glsl: Define image-related built-in constants required by GLSL ES 3.1. Reviewed-by: Tapani Pälli tapani.pa...@intel.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a976b7255b2c84e6cccefb447029add02ddf86ae Author: Francisco Jerez curroje...@riseup.net Date: Mon Aug 17 01:39:38 2015 +0300 glsl: Remove duplicate definition of gl_MaxTess*ImageUniforms built-in constants. These seem to have been re-added at some point during the ARB_tessellation_shader implementation work. AFAICT the second (correct) definition of each constant would have had no effect because the symbols were already defined. Reviewed-by: Tapani Pälli tapani.pa...@intel.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d0bb6be097080e2568b7b6cc18f2bf800fed1b1 Author: Francisco Jerez curroje...@riseup.net Date: Mon Aug 17 01:38:00 2015 +0300 glsl: Accept atomic_uint type in GLSL ES 3.1. Reviewed-by: Tapani Pälli tapani.pa...@intel.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d589df94013bd04b23ef88cdac6debe04e3075a1 Author: Francisco Jerez curroje...@riseup.net Date: Mon Aug 17 01:37:12 2015 +0300 glsl: Accept supported image types in GLSL ES 3.1. These are a subset of the image types supported by desktop GL, excluding 1D, 1D array, rectangle, buffer, cube array, 2D MS and 2D MS array texture targets. Reviewed-by: Tapani Pälli tapani.pa...@intel.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6da187f80560b44b59551757c1322e921d8ca025 Author: Francisco Jerez curroje...@riseup.net Date: Mon Aug 17 01:34:41 2015 +0300 glsl: Expose image load and store built-ins in GLSL ES 3.1. Reviewed-by: Tapani Pälli tapani.pa...@intel.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=76a09c87c14f65d8ad8bd805ef03101f4455a24f Author: Francisco Jerez curroje...@riseup.net Date: Mon Aug 17 01:34:13 2015 +0300 glsl: Use a separate availability class for image atomic built-ins. These are not part of unextended GLSL ES 3.1. Reviewed-by: Timothy Arceri t_arc...@yahoo.com.au Reviewed-by: Tapani Pälli tapani.pa...@intel.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=26b1141a78cfec0e2eface4b399009ee5eb421df Author: Francisco Jerez curroje...@riseup.net Date: Mon Aug 17 01:28:57 2015 +0300 glsl: Allow precision qualifiers on general opaque types. From the GLSL ES 3.1 spec, section 4.7.3: Any floating point, integer, opaque type declaration can have the type preceded by one of these precision qualifiers: [...] highp [...], mediump [...], lowp [...]. Reviewed-by: Timothy Arceri t_arc...@yahoo.com.au Reviewed-by: Tapani Pälli tapani.pa...@intel.com URL:
Mesa (master): nir: convert the glsl intrinsic image_size to nir_intrinsic_image_size
Module: Mesa
Branch: master
Commit: 80b1707e26734ac9c957cfc876ab5893f1749c74
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=80b1707e26734ac9c957cfc876ab5893f1749c74
Author: Martin Peres martin.pe...@linux.intel.com
Date: Tue Aug 11 17:42:12 2015 +0300
nir: convert the glsl intrinsic image_size to nir_intrinsic_image_size
v2, review from Francisco Jerez:
- make the destination variable as large as what the nir instrinsic
defines (4) instead of the size of the return variable of glsl. This
is still safe for the already existing code because all the intrinsics
affected returned the same amount of components as expected by glsl IR.
In the case of image_size, it is not possible to do so because the
returned number of component depends on the image type and this case
is not well handled by nir.
v3:
- Style fix
Signed-off-by: Martin Peres martin.pe...@linux.intel.com
Reviewed-by: Francisco Jerez curroje...@riseup.net
---
src/glsl/nir/glsl_to_nir.cpp | 21 +++--
src/glsl/nir/nir_intrinsics.h |2 ++
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp
index 77327b6..913f2f4 100644
--- a/src/glsl/nir/glsl_to_nir.cpp
+++ b/src/glsl/nir/glsl_to_nir.cpp
@@ -641,6 +641,8 @@ nir_visitor::visit(ir_call *ir)
op = nir_intrinsic_image_atomic_comp_swap;
} else if (strcmp(ir-callee_name(), __intrinsic_memory_barrier) == 0)
{
op = nir_intrinsic_memory_barrier;
+ } else if (strcmp(ir-callee_name(), __intrinsic_image_size) == 0) {
+ op = nir_intrinsic_image_size;
} else {
unreachable(not reached);
}
@@ -666,7 +668,8 @@ nir_visitor::visit(ir_call *ir)
case nir_intrinsic_image_atomic_or:
case nir_intrinsic_image_atomic_xor:
case nir_intrinsic_image_atomic_exchange:
- case nir_intrinsic_image_atomic_comp_swap: {
+ case nir_intrinsic_image_atomic_comp_swap:
+ case nir_intrinsic_image_size: {
nir_ssa_undef_instr *instr_undef =
nir_ssa_undef_instr_create(shader, 1);
nir_instr_insert_after_cf_list(this-cf_node_list,
@@ -681,6 +684,17 @@ nir_visitor::visit(ir_call *ir)
instr-variables[0] = evaluate_deref(instr-instr, image);
param = param-get_next();
+ /* Set the intrinsic destination. */
+ if (ir-return_deref) {
+const nir_intrinsic_info *info =
+nir_intrinsic_infos[instr-intrinsic];
+nir_ssa_dest_init(instr-instr, instr-dest,
+ info-dest_components, NULL);
+ }
+
+ if (op == nir_intrinsic_image_size)
+break;
+
/* Set the address argument, extending the coordinate vector to four
* components.
*/
@@ -721,11 +735,6 @@ nir_visitor::visit(ir_call *ir)
instr-src[3] = evaluate_rvalue((ir_dereference *)param);
param = param-get_next();
}
-
- /* Set the intrinsic destination. */
- if (ir-return_deref)
-nir_ssa_dest_init(instr-instr, instr-dest,
- ir-return_deref-type-vector_elements, NULL);
break;
}
case nir_intrinsic_memory_barrier:
diff --git a/src/glsl/nir/nir_intrinsics.h b/src/glsl/nir/nir_intrinsics.h
index bc6e6b8..6c7a61a 100644
--- a/src/glsl/nir/nir_intrinsics.h
+++ b/src/glsl/nir/nir_intrinsics.h
@@ -123,6 +123,8 @@ INTRINSIC(image_atomic_or, 3, ARR(4, 1, 1), true, 1, 1, 0,
0)
INTRINSIC(image_atomic_xor, 3, ARR(4, 1, 1), true, 1, 1, 0, 0)
INTRINSIC(image_atomic_exchange, 3, ARR(4, 1, 1), true, 1, 1, 0, 0)
INTRINSIC(image_atomic_comp_swap, 4, ARR(4, 1, 1, 1), true, 1, 1, 0, 0)
+INTRINSIC(image_size, 0, ARR(), true, 4, 1, 0,
+ NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
#define SYSTEM_VALUE(name, components) \
INTRINSIC(load_##name, 0, ARR(), true, components, 0, 0, \
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Mesa (master): glsl: add support for the imageSize builtin
Module: Mesa
Branch: master
Commit: 58a8689717a5965919934d1b4b44b4eef0a6bf64
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=58a8689717a5965919934d1b4b44b4eef0a6bf64
Author: Martin Peres martin.pe...@linux.intel.com
Date: Mon Apr 27 19:25:34 2015 +0300
glsl: add support for the imageSize builtin
The code is heavily inspired from Francisco Jerez's code supporting the
image_load_store extension.
Backends willing to support this builtin should handle
__intrinsic_image_size.
v2: Based on the review of Ilia Mirkin
- Enable the extension for GLES 3.1
- Fix indentation
- Fix the return type (float to int, number of components for CubeImages)
- Add a warning related to GLES 3.1
v3: Based on the review of Francisco Jerez
- Refactor the code to share both add_image_function and _image with the other
image-related functions
v4: Based on Topi Pohjolainen's comments
- Do not add parenthesis for the return value
v5: based on Francisco Jerez's comments:
- Fix a few indent issues
- Reduce the size of a condition by testing the dimension and array properties
instead of enumerating all the formats.
Signed-off-by: Martin Peres martin.pe...@linux.intel.com
Reviewed-by: Francisco Jerez curroje...@riseup.net
---
src/glsl/builtin_functions.cpp | 108 ++--
1 file changed, 92 insertions(+), 16 deletions(-)
diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index 6481599..05dbe2e 100644
--- a/src/glsl/builtin_functions.cpp
+++ b/src/glsl/builtin_functions.cpp
@@ -413,6 +413,13 @@ shader_image_atomic(const _mesa_glsl_parse_state *state)
}
static bool
+shader_image_size(const _mesa_glsl_parse_state *state)
+{
+ return state-is_version(430, 310) ||
+ state-ARB_shader_image_size_enable;
+}
+
+static bool
gs_streams(const _mesa_glsl_parse_state *state)
{
return gpu_shader5(state) gs_only(state);
@@ -506,6 +513,11 @@ private:
/** Create a new function and add the given signatures. */
void add_function(const char *name, ...);
+ typedef ir_function_signature
*(builtin_builder::*image_prototype_ctr)(const glsl_type *image_type,
+
const char *intrinsic_name,
+
unsigned num_arguments,
+
unsigned flags);
+
enum image_function_flags {
IMAGE_FUNCTION_EMIT_STUB = (1 0),
IMAGE_FUNCTION_RETURNS_VOID = (1 1),
@@ -522,6 +534,7 @@ private:
*/
void add_image_function(const char *name,
const char *intrinsic_name,
+ image_prototype_ctr prototype,
unsigned num_arguments,
unsigned flags);
@@ -723,7 +736,12 @@ private:
const char *intrinsic_name,
unsigned num_arguments,
unsigned flags);
- ir_function_signature *_image(const glsl_type *image_type,
+ ir_function_signature *_image_size_prototype(const glsl_type *image_type,
+const char *intrinsic_name,
+unsigned num_arguments,
+unsigned flags);
+ ir_function_signature *_image(image_prototype_ctr prototype,
+ const glsl_type *image_type,
const char *intrinsic_name,
unsigned num_arguments,
unsigned flags);
@@ -2567,6 +2585,7 @@ builtin_builder::add_function(const char *name, ...)
void
builtin_builder::add_image_function(const char *name,
const char *intrinsic_name,
+image_prototype_ctr prototype,
unsigned num_arguments,
unsigned flags)
{
@@ -2605,12 +2624,13 @@ builtin_builder::add_image_function(const char *name,
glsl_type::uimage2DMS_type,
glsl_type::uimage2DMSArray_type
};
+
ir_function *f = new(mem_ctx) ir_function(name);
for (unsigned i = 0; i ARRAY_SIZE(types); ++i) {
if (types[i]-sampler_type != GLSL_TYPE_FLOAT ||
(flags IMAGE_FUNCTION_SUPPORTS_FLOAT_DATA_TYPE))
- f-add_signature(_image(types[i], intrinsic_name,
+ f-add_signature(_image(prototype, types[i], intrinsic_name,
num_arguments, flags));
}
@@ -2623,13 +2643,15 @@ builtin_builder::add_image_functions(bool glsl)
const unsigned flags = (glsl ? IMAGE_FUNCTION_EMIT_STUB : 0);
add_image_function(glsl ? imageLoad : __intrinsic_image_load,
- __intrinsic_image_load, 0,
-
Mesa (master): i965: handle nir_intrinsic_image_size
Module: Mesa
Branch: master
Commit: 50db9c1db645c1a4d5777d2cacfd7ac74ebbe544
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=50db9c1db645c1a4d5777d2cacfd7ac74ebbe544
Author: Martin Peres martin.pe...@linux.intel.com
Date: Wed Apr 29 12:39:16 2015 +0300
i965: handle nir_intrinsic_image_size
v2, Review from Francisco Jerez:
- avoid the camelCase for the booleans
- init the booleans using the sampler type
- force the initialization of all the components of the output register
v3:
- Rename a variable from CubeMapArray to CubeArray to re-use GLSL's name (Ilia)
- Fix some indentation and drop parenthesis (Topi)
- Fix a signed/unsigned comparaison warning
Signed-off-by: Martin Peres martin.pe...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 46 ++
1 file changed, 46 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index ce4153d..12471fb 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -1406,6 +1406,52 @@ fs_visitor::nir_emit_intrinsic(const fs_builder bld,
nir_intrinsic_instr *instr
break;
}
+ case nir_intrinsic_image_size: {
+ /* Get the referenced image variable and type. */
+ const nir_variable *var = instr-variables[0]-var;
+ const glsl_type *type = var-type-without_array();
+ const brw_reg_type base_type = get_image_base_type(type);
+
+ /* Get the size of the image. */
+ const fs_reg image = get_nir_image_deref(instr-variables[0]);
+ const fs_reg size = offset(image, bld, BRW_IMAGE_PARAM_SIZE_OFFSET);
+
+ /* For 1DArray image types, the array index is stored in the Z component.
+ * Fix this by swizzling the Z component to the Y component.
+ */
+ const bool is_1d_array_image =
+ type-sampler_dimensionality == GLSL_SAMPLER_DIM_1D
+ type-sampler_array;
+
+ /* For CubeArray images, we should count the number of cubes instead
+ * of the number of faces. Fix it by dividing the (Z component) by 6.
+ */
+ const bool is_cube_array_image =
+ type-sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE
+ type-sampler_array;
+
+ /* Copy all the components. */
+ const nir_intrinsic_info *info = nir_intrinsic_infos[instr-intrinsic];
+ for (unsigned c = 0; c info-dest_components; ++c) {
+ if ((int)c = type-coordinate_components()) {
+ bld.MOV(offset(retype(dest, BRW_REGISTER_TYPE_D), bld, c),
+ fs_reg(1));
+ } else if (c == 1 is_1d_array_image) {
+bld.MOV(offset(retype(dest, base_type), bld, c),
+offset(size, bld, 2));
+ } else if (c == 2 is_cube_array_image) {
+bld.emit(SHADER_OPCODE_INT_QUOTIENT,
+ offset(retype(dest, base_type), bld, c),
+ offset(size, bld, c), fs_reg(6));
+ } else {
+bld.MOV(offset(retype(dest, base_type), bld, c),
+offset(size, bld, c));
+ }
+ }
+
+ break;
+ }
+
case nir_intrinsic_load_front_face:
bld.MOV(retype(dest, BRW_REGISTER_TYPE_D),
*emit_frontfacing_interpolation());
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Mesa (master): main: add extension GL_ARB_shader_image_size
Module: Mesa
Branch: master
Commit: 3d93f65ef2dbecbf615ee8041d92354ae660d71b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d93f65ef2dbecbf615ee8041d92354ae660d71b
Author: Martin Peres martin.pe...@linux.intel.com
Date: Mon Apr 27 20:05:14 2015 +0300
main: add extension GL_ARB_shader_image_size
Reviewed-by: Edward O'Callaghan eocallag...@alterapraxis.com
Reviewed-by: Francisco Jerez curroje...@riseup.net
Signed-off-by: Martin Peres martin.pe...@linux.intel.com
---
src/glsl/glcpp/glcpp-parse.y|3 +++
src/glsl/glsl_parser_extras.cpp |1 +
src/glsl/glsl_parser_extras.h |2 ++
src/mesa/main/extensions.c |1 +
src/mesa/main/mtypes.h |1 +
5 files changed, 8 insertions(+)
diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
index dd5ec2a..18e50af 100644
--- a/src/glsl/glcpp/glcpp-parse.y
+++ b/src/glsl/glcpp/glcpp-parse.y
@@ -2478,6 +2478,9 @@ _glcpp_parser_handle_version_declaration(glcpp_parser_t
*parser, intmax_t versio
if (extensions-ARB_shader_image_load_store)
add_builtin_define(parser, GL_ARB_shader_image_load_store,
1);
+ if (extensions-ARB_shader_image_size)
+ add_builtin_define(parser, GL_ARB_shader_image_size, 1);
+
if (extensions-ARB_derivative_control)
add_builtin_define(parser, GL_ARB_derivative_control, 1);
diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp
index 82b92b1..6440a96 100644
--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -599,6 +599,7 @@ static const _mesa_glsl_extension
_mesa_glsl_supported_extensions[] = {
EXT(ARB_shader_atomic_counters, true, false,
ARB_shader_atomic_counters),
EXT(ARB_shader_bit_encoding, true, false,
ARB_shader_bit_encoding),
EXT(ARB_shader_image_load_store, true, false,
ARB_shader_image_load_store),
+ EXT(ARB_shader_image_size,true, false,
ARB_shader_image_size),
EXT(ARB_shader_precision, true, false,
ARB_shader_precision),
EXT(ARB_shader_stencil_export,true, false,
ARB_shader_stencil_export),
EXT(ARB_shader_storage_buffer_object, true, false,
ARB_shader_storage_buffer_object),
diff --git a/src/glsl/glsl_parser_extras.h b/src/glsl/glsl_parser_extras.h
index e3cdbc5..e2145be 100644
--- a/src/glsl/glsl_parser_extras.h
+++ b/src/glsl/glsl_parser_extras.h
@@ -500,6 +500,8 @@ struct _mesa_glsl_parse_state {
bool ARB_shader_bit_encoding_warn;
bool ARB_shader_image_load_store_enable;
bool ARB_shader_image_load_store_warn;
+ bool ARB_shader_image_size_enable;
+ bool ARB_shader_image_size_warn;
bool ARB_shader_precision_enable;
bool ARB_shader_precision_warn;
bool ARB_shader_stencil_export_enable;
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index 017de2d..4a3c231 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
@@ -153,6 +153,7 @@ static const struct extension extension_table[] = {
{ GL_ARB_shader_atomic_counters,
o(ARB_shader_atomic_counters), GL, 2011 },
{ GL_ARB_shader_bit_encoding, o(ARB_shader_bit_encoding),
GL, 2010 },
{ GL_ARB_shader_image_load_store,
o(ARB_shader_image_load_store), GL, 2011 },
+ { GL_ARB_shader_image_size, o(ARB_shader_image_size),
GL, 2012 },
{ GL_ARB_shader_objects, o(dummy_true),
GL, 2002 },
{ GL_ARB_shader_precision,o(ARB_shader_precision),
GL, 2010 },
{ GL_ARB_shader_stencil_export,
o(ARB_shader_stencil_export), GL, 2009 },
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 23afdbd..5031b08 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -3760,6 +3760,7 @@ struct gl_extensions
GLboolean ARB_shader_atomic_counters;
GLboolean ARB_shader_bit_encoding;
GLboolean ARB_shader_image_load_store;
+ GLboolean ARB_shader_image_size;
GLboolean ARB_shader_precision;
GLboolean ARB_shader_stencil_export;
GLboolean ARB_shader_storage_buffer_object;
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Mesa (master): i965: enable GL_ARB_shader_image_size
Module: Mesa Branch: master Commit: e5851cff45169f4e635299da4ed5b41aeb0d2f83 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5851cff45169f4e635299da4ed5b41aeb0d2f83 Author: Martin Peres martin.pe...@linux.intel.com Date: Wed Apr 29 12:42:16 2015 +0300 i965: enable GL_ARB_shader_image_size Signed-off-by: Martin Peres martin.pe...@linux.intel.com --- docs/GL3.txt |4 ++-- docs/relnotes/11.0.0.html|1 + src/mesa/drivers/dri/i965/intel_extensions.c |1 + 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/docs/GL3.txt b/docs/GL3.txt index 4bff4da..331b2da 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -163,7 +163,7 @@ GL 4.3, GLSL 4.30: GL_ARB_multi_draw_indirect DONE (i965, nvc0, r600, radeonsi, llvmpipe, softpipe) GL_ARB_program_interface_query DONE (all drivers) GL_ARB_robust_buffer_access_behavior not started - GL_ARB_shader_image_size in progress (Martin Peres) + GL_ARB_shader_image_size DONE (i965) GL_ARB_shader_storage_buffer_object in progress (Iago Toral, Samuel Iglesias) GL_ARB_stencil_texturing DONE (i965/gen8+, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe) GL_ARB_texture_buffer_range DONE (nv50, nvc0, i965, r600, radeonsi, llvmpipe) @@ -211,7 +211,7 @@ GLES3.1, GLSL ES 3.1 GL_ARB_program_interface_query DONE (all drivers) GL_ARB_shader_atomic_countersDONE (i965) GL_ARB_shader_image_load_store DONE (i965) - GL_ARB_shader_image_size in progress (Martin Peres) + GL_ARB_shader_image_size DONE (i965) GL_ARB_shader_storage_buffer_object in progress (Iago Toral, Samuel Iglesias) GL_ARB_shading_language_packing DONE (all drivers) GL_ARB_separate_shader_objects DONE (all drivers) diff --git a/docs/relnotes/11.0.0.html b/docs/relnotes/11.0.0.html index 447e35e..7e4b09d 100644 --- a/docs/relnotes/11.0.0.html +++ b/docs/relnotes/11.0.0.html @@ -56,6 +56,7 @@ Note: some of the new features are only available with certain drivers. liGL_ARB_gpu_shader_fp64 on llvmpipe, radeonsi/li liGL_ARB_shader_image_load_store on i965/li liGL_ARB_shader_precision on radeonsi, nvc0/li +liGL_ARB_shader_image_size on i965/li liGL_ARB_shader_stencil_export on llvmpipe/li liGL_ARB_shader_subroutine on core profile all drivers/li liGL_ARB_tessellation_shader on nvc0, radeonsi/li diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 0da528b..4365b71 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -326,6 +326,7 @@ intelInitExtensions(struct gl_context *ctx) ctx-Extensions.ARB_gpu_shader5 = true; ctx-Extensions.ARB_shader_atomic_counters = true; ctx-Extensions.ARB_shader_image_load_store = true; + ctx-Extensions.ARB_shader_image_size = true; ctx-Extensions.ARB_texture_compression_bptc = true; ctx-Extensions.ARB_texture_view = true; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): Revert mesa/formats: refactor by collapsing cases in switch statement by type
Module: Mesa Branch: master Commit: 29e953b07b8c1e4d27f53c4a1430154a3d67f896 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=29e953b07b8c1e4d27f53c4a1430154a3d67f896 Author: Nanley Chery nanley.g.ch...@intel.com Date: Thu Aug 20 18:00:20 2015 -0700 Revert mesa/formats: refactor by collapsing cases in switch statement by type This reverts commit ffe6c6ad5f719dedd1b6b95e8590e3f20b23d340. _mesa_format_num_components() does not include the padding bits in mesa formats containing 'X' channels. This could cause mipmap generation for certain uncompressed formats to underestimate the number of channels in the source image by 1. Signed-off-by: Nanley Chery nanley.g.ch...@intel.com --- src/mesa/main/formats.c | 152 +-- 1 file changed, 135 insertions(+), 17 deletions(-) diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c index a55341d..8c7e6ad 100644 --- a/src/mesa/main/formats.c +++ b/src/mesa/main/formats.c @@ -1013,10 +1013,13 @@ _mesa_format_to_type_and_comps(mesa_format format, case MESA_FORMAT_R8G8B8X8_UNORM: case MESA_FORMAT_B8G8R8X8_UNORM: case MESA_FORMAT_X8R8G8B8_UNORM: + *datatype = GL_UNSIGNED_BYTE; + *comps = 4; + return; case MESA_FORMAT_BGR_UNORM8: case MESA_FORMAT_RGB_UNORM8: *datatype = GL_UNSIGNED_BYTE; - *comps = _mesa_format_num_components(format); + *comps = 3; return; case MESA_FORMAT_B5G6R5_UNORM: case MESA_FORMAT_R5G6B5_UNORM: @@ -1065,12 +1068,16 @@ _mesa_format_to_type_and_comps(mesa_format format, case MESA_FORMAT_A16L16_UNORM: case MESA_FORMAT_R16G16_UNORM: case MESA_FORMAT_G16R16_UNORM: + *datatype = GL_UNSIGNED_SHORT; + *comps = 2; + return; + case MESA_FORMAT_R_UNORM16: case MESA_FORMAT_A_UNORM16: case MESA_FORMAT_L_UNORM16: case MESA_FORMAT_I_UNORM16: *datatype = GL_UNSIGNED_SHORT; - *comps = _mesa_format_num_components(format); + *comps = 1; return; case MESA_FORMAT_R3G3B2_UNORM: @@ -1078,6 +1085,10 @@ _mesa_format_to_type_and_comps(mesa_format format, *comps = 3; return; case MESA_FORMAT_A4B4G4R4_UNORM: + *datatype = GL_UNSIGNED_SHORT_4_4_4_4; + *comps = 4; + return; + case MESA_FORMAT_R4G4B4A4_UNORM: *datatype = GL_UNSIGNED_SHORT_4_4_4_4; *comps = 4; @@ -1088,6 +1099,9 @@ _mesa_format_to_type_and_comps(mesa_format format, return; case MESA_FORMAT_A2B10G10R10_UNORM: case MESA_FORMAT_A2B10G10R10_UINT: + *datatype = GL_UNSIGNED_INT_10_10_10_2; + *comps = 4; + return; case MESA_FORMAT_A2R10G10B10_UNORM: case MESA_FORMAT_A2R10G10B10_UINT: *datatype = GL_UNSIGNED_INT_10_10_10_2; @@ -1130,7 +1144,15 @@ _mesa_format_to_type_and_comps(mesa_format format, return; case MESA_FORMAT_Z24_UNORM_X8_UINT: + *datatype = GL_UNSIGNED_INT; + *comps = 1; + return; + case MESA_FORMAT_X8_UINT_Z24_UNORM: + *datatype = GL_UNSIGNED_INT; + *comps = 1; + return; + case MESA_FORMAT_Z_UNORM32: *datatype = GL_UNSIGNED_INT; *comps = 1; @@ -1150,14 +1172,20 @@ _mesa_format_to_type_and_comps(mesa_format format, case MESA_FORMAT_A_SNORM8: case MESA_FORMAT_L_SNORM8: case MESA_FORMAT_I_SNORM8: + *datatype = GL_BYTE; + *comps = 1; + return; case MESA_FORMAT_R8G8_SNORM: case MESA_FORMAT_L8A8_SNORM: case MESA_FORMAT_A8L8_SNORM: + *datatype = GL_BYTE; + *comps = 2; + return; case MESA_FORMAT_A8B8G8R8_SNORM: case MESA_FORMAT_R8G8B8A8_SNORM: case MESA_FORMAT_X8B8G8R8_SNORM: *datatype = GL_BYTE; - *comps = _mesa_format_num_components(format); + *comps = 4; return; case MESA_FORMAT_RGBA_UNORM16: @@ -1169,24 +1197,42 @@ _mesa_format_to_type_and_comps(mesa_format format, case MESA_FORMAT_A_SNORM16: case MESA_FORMAT_L_SNORM16: case MESA_FORMAT_I_SNORM16: + *datatype = GL_SHORT; + *comps = 1; + return; case MESA_FORMAT_R16G16_SNORM: case MESA_FORMAT_LA_SNORM16: + *datatype = GL_SHORT; + *comps = 2; + return; case MESA_FORMAT_RGB_SNORM16: + *datatype = GL_SHORT; + *comps = 3; + return; case MESA_FORMAT_RGBA_SNORM16: *datatype = GL_SHORT; - *comps = _mesa_format_num_components(format); + *comps = 4; return; case MESA_FORMAT_BGR_SRGB8: + *datatype = GL_UNSIGNED_BYTE; + *comps = 3; + return; case MESA_FORMAT_A8B8G8R8_SRGB: case MESA_FORMAT_B8G8R8A8_SRGB: case MESA_FORMAT_A8R8G8B8_SRGB: case MESA_FORMAT_R8G8B8A8_SRGB: + *datatype = GL_UNSIGNED_BYTE; + *comps = 4; + return; case MESA_FORMAT_L_SRGB8: + *datatype = GL_UNSIGNED_BYTE; + *comps = 1; + return; case MESA_FORMAT_L8A8_SRGB: case MESA_FORMAT_A8L8_SRGB: *datatype = GL_UNSIGNED_BYTE; - *comps = _mesa_format_num_components(format);
Mesa (master): i965: Use NIR by default for vertex shaders
Module: Mesa
Branch: master
Commit: bbf8291bf869e219bd0e71063bf26a060682a000
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bbf8291bf869e219bd0e71063bf26a060682a000
Author: Jason Ekstrand jason.ekstr...@intel.com
Date: Mon Aug 3 08:17:42 2015 -0700
i965: Use NIR by default for vertex shaders
Shader-db results for vec4 on i965:
total instructions in shared programs: 1499894 - 1502261 (0.16%)
instructions in affected programs: 1414224 - 1416591 (0.17%)
helped:2434
HURT: 10543
GAINED:1
LOST: 0
Shader-db results for vec4 on g4x:
total instructions in shared programs: 1437411 - 1439779 (0.16%)
instructions in affected programs: 1362402 - 1364770 (0.17%)
helped:2434
HURT: 10544
GAINED:0
LOST: 0
Shader-db results for vec4 on Iron Lake:
total instructions in shared programs: 1437214 - 1439593 (0.17%)
instructions in affected programs: 1362205 - 1364584 (0.17%)
helped:2433
HURT: 10544
GAINED:1
LOST: 0
Shader-db results for vec4 on Sandy Bridge:
total instructions in shared programs: 2022092 - 1941570 (-3.98%)
instructions in affected programs: 1886838 - 1806316 (-4.27%)
helped:7510
HURT: 10737
GAINED:0
LOST: 0
Shader-db results for vec4 on Ivy Bridge:
total instructions in shared programs: 1853749 - 1804960 (-2.63%)
instructions in affected programs: 1686736 - 1637947 (-2.89%)
helped:6735
HURT: 11101
GAINED:0
LOST: 0
Shader-db results for vec4 on Haswell:
total instructions in shared programs: 1853749 - 1804960 (-2.63%)
instructions in affected programs: 1686736 - 1637947 (-2.89%)
helped:6735
HURT: 11101
GAINED:0
LOST: 0
Signed-off-by: Jason Ekstrand jason.ekstr...@intel.com
Acked-by: Kenneth Graunke kenn...@whitecape.org
Acked-by: Matt Turner matts...@gmail.com
---
src/mesa/drivers/dri/i965/brw_shader.cpp |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 6b92806..14f647d 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -122,7 +122,7 @@ brw_compiler_create(void *mem_ctx, const struct
brw_device_info *devinfo)
compiler-glsl_compiler_options[MESA_SHADER_VERTEX].OptimizeForAOS = true;
compiler-glsl_compiler_options[MESA_SHADER_GEOMETRY].OptimizeForAOS = true;
- if (compiler-scalar_vs || brw_env_var_as_boolean(INTEL_USE_NIR, false)) {
+ if (compiler-scalar_vs || brw_env_var_as_boolean(INTEL_USE_NIR, true)) {
if (compiler-scalar_vs) {
/* If we're using the scalar backend for vertex shaders, we need to
* configure these accordingly.
@@ -135,7 +135,7 @@ brw_compiler_create(void *mem_ctx, const struct
brw_device_info *devinfo)
compiler-glsl_compiler_options[MESA_SHADER_VERTEX].NirOptions =
nir_options;
}
- if (brw_env_var_as_boolean(INTEL_USE_NIR, false)) {
+ if (brw_env_var_as_boolean(INTEL_USE_NIR, true)) {
compiler-glsl_compiler_options[MESA_SHADER_GEOMETRY].NirOptions =
nir_options;
}
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Mesa (master): nv50/ir: pre-compute BFE arg when both bits and offset are imm
Module: Mesa
Branch: master
Commit: 8483577f6b393c26dc21f6693e44760404ba6fcb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8483577f6b393c26dc21f6693e44760404ba6fcb
Author: Ilia Mirkin imir...@alum.mit.edu
Date: Thu Aug 20 22:13:48 2015 -0400
nv50/ir: pre-compute BFE arg when both bits and offset are imm
Due to a quirk in how the nv50 opt passes run, the algebraic
optimization that looks for these BFE's happens before the constant
folding pass. Rearranging these passes isn't a great idea, but this is
easy enough to fix. Allows a following cvt to eliminate the bfe in
certain situations.
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 4847a0f..f153674 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -2990,9 +2990,15 @@ Converter::handleInstruction(const struct
tgsi_full_instruction *insn)
case TGSI_OPCODE_UBFE:
FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
src0 = fetchSrc(0, c);
- src1 = fetchSrc(1, c);
- src2 = fetchSrc(2, c);
- mkOp3(OP_INSBF, TYPE_U32, src1, src2, mkImm(0x808), src1);
+ if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE
+ tgsi.getSrc(2).getFile() == TGSI_FILE_IMMEDIATE) {
+src1 = loadImm(NULL, tgsi.getSrc(2).getValueU32(c, info) 8 |
+ tgsi.getSrc(1).getValueU32(c, info));
+ } else {
+src1 = fetchSrc(1, c);
+src2 = fetchSrc(2, c);
+mkOp3(OP_INSBF, TYPE_U32, src1, src2, mkImm(0x808), src1);
+ }
mkOp2(OP_EXTBF, dstTy, dst0[c], src0, src1);
}
break;
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Mesa (master): glsl: expose textureQueryLod in GLSL 4.00+ fragment shaders
Module: Mesa
Branch: master
Commit: ecebd3dbfcb769b44e99733279c8fb0745818708
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ecebd3dbfcb769b44e99733279c8fb0745818708
Author: Ilia Mirkin imir...@alum.mit.edu
Date: Wed Aug 19 18:43:47 2015 -0400
glsl: expose textureQueryLod in GLSL 4.00+ fragment shaders
See issue from the ARB_texture_query_lod spec for LOD vs Lod confusion:
(3) The core specification uses the Lod spelling, not LOD. Should
this extension be modified to use Lod?
RESOLVED: The Lod spelling is the correct spelling for the core
specification and the preferred spelling for use. However, use of
LOD also exists, as the extension predated the core specification,
so this extension won't remove use of LOD.
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
Reviewed-by: Timothy Arceri t_arc...@yahoo.com.au
---
src/glsl/builtin_functions.cpp | 119 +++-
1 file changed, 82 insertions(+), 37 deletions(-)
diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index 05dbe2e..57bed86 100644
--- a/src/glsl/builtin_functions.cpp
+++ b/src/glsl/builtin_functions.cpp
@@ -136,6 +136,13 @@ v140(const _mesa_glsl_parse_state *state)
}
static bool
+v400_fs_only(const _mesa_glsl_parse_state *state)
+{
+ return state-is_version(400, 0)
+ state-stage == MESA_SHADER_FRAGMENT;
+}
+
+static bool
es31(const _mesa_glsl_parse_state *state)
{
return state-is_version(0, 310);
@@ -691,7 +698,7 @@ private:
const glsl_type *stream_type);
B0(barrier)
- B2(textureQueryLod);
+ BA2(textureQueryLod);
B1(textureQueryLevels);
B1(dFdx);
B1(dFdy);
@@ -1977,40 +1984,77 @@ builtin_builder::create_builtins()
add_function(barrier, _barrier(), NULL);
add_function(textureQueryLOD,
-_textureQueryLod(glsl_type::sampler1D_type,
glsl_type::float_type),
-_textureQueryLod(glsl_type::isampler1D_type,
glsl_type::float_type),
-_textureQueryLod(glsl_type::usampler1D_type,
glsl_type::float_type),
-
-_textureQueryLod(glsl_type::sampler2D_type,
glsl_type::vec2_type),
-_textureQueryLod(glsl_type::isampler2D_type,
glsl_type::vec2_type),
-_textureQueryLod(glsl_type::usampler2D_type,
glsl_type::vec2_type),
-
-_textureQueryLod(glsl_type::sampler3D_type,
glsl_type::vec3_type),
-_textureQueryLod(glsl_type::isampler3D_type,
glsl_type::vec3_type),
-_textureQueryLod(glsl_type::usampler3D_type,
glsl_type::vec3_type),
-
-_textureQueryLod(glsl_type::samplerCube_type,
glsl_type::vec3_type),
-_textureQueryLod(glsl_type::isamplerCube_type,
glsl_type::vec3_type),
-_textureQueryLod(glsl_type::usamplerCube_type,
glsl_type::vec3_type),
-
-_textureQueryLod(glsl_type::sampler1DArray_type,
glsl_type::float_type),
-_textureQueryLod(glsl_type::isampler1DArray_type,
glsl_type::float_type),
-_textureQueryLod(glsl_type::usampler1DArray_type,
glsl_type::float_type),
-
-_textureQueryLod(glsl_type::sampler2DArray_type,
glsl_type::vec2_type),
-_textureQueryLod(glsl_type::isampler2DArray_type,
glsl_type::vec2_type),
-_textureQueryLod(glsl_type::usampler2DArray_type,
glsl_type::vec2_type),
-
-_textureQueryLod(glsl_type::samplerCubeArray_type,
glsl_type::vec3_type),
-_textureQueryLod(glsl_type::isamplerCubeArray_type,
glsl_type::vec3_type),
-_textureQueryLod(glsl_type::usamplerCubeArray_type,
glsl_type::vec3_type),
-
-_textureQueryLod(glsl_type::sampler1DShadow_type,
glsl_type::float_type),
-_textureQueryLod(glsl_type::sampler2DShadow_type,
glsl_type::vec2_type),
-_textureQueryLod(glsl_type::samplerCubeShadow_type,
glsl_type::vec3_type),
-_textureQueryLod(glsl_type::sampler1DArrayShadow_type,
glsl_type::float_type),
-_textureQueryLod(glsl_type::sampler2DArrayShadow_type,
glsl_type::vec2_type),
-_textureQueryLod(glsl_type::samplerCubeArrayShadow_type,
glsl_type::vec3_type),
+_textureQueryLod(texture_query_lod, glsl_type::sampler1D_type,
glsl_type::float_type),
+_textureQueryLod(texture_query_lod,
glsl_type::isampler1D_type, glsl_type::float_type),
+_textureQueryLod(texture_query_lod,
glsl_type::usampler1D_type, glsl_type::float_type),
+
+_textureQueryLod(texture_query_lod, glsl_type::sampler2D_type,
glsl_type::vec2_type),
+_textureQueryLod(texture_query_lod,
glsl_type::isampler2D_type, glsl_type::vec2_type),
+_textureQueryLod(texture_query_lod,
glsl_type::usampler2D_type, glsl_type::vec2_type),
+
+
Mesa (master): glsl: check if return_deref in lower_subroutine_visitor:: visit_leave isn't NULL
Module: Mesa Branch: master Commit: 6921f170b62d9f9c0e5bd2cbc15395addba8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6921f170b62d9f9c0e5bd2cbc15395addba8 Author: Kai Wasserbäch k...@dev.carbon-project.org Date: Fri Aug 14 14:49:43 2015 +0200 glsl: check if return_deref in lower_subroutine_visitor::visit_leave isn't NULL Fixes a crash in Piglit's spec@arb_shader_subroutine@lin...@no-mutual-recursion.vert for me. Signed-off-by: Kai Wasserbäch k...@dev.carbon-project.org Reviewed-by: Dave Airlie airl...@redhat.com Signed-off-by: Dave Airlie airl...@redhat.com --- src/glsl/lower_subroutine.cpp |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/glsl/lower_subroutine.cpp b/src/glsl/lower_subroutine.cpp index b29912a..c1aed61 100644 --- a/src/glsl/lower_subroutine.cpp +++ b/src/glsl/lower_subroutine.cpp @@ -98,7 +98,7 @@ lower_subroutine_visitor::visit_leave(ir_call *ir) else last_branch = if_tree(equal(subr_to_int(var), lc), new_call, last_branch); - if (s 0) + if (return_deref s 0) return_deref = return_deref-clone(mem_ctx, NULL); } if (last_branch) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600: Rewrite r600_shader_selector_key() to use a switch stmt
Module: Mesa
Branch: master
Commit: e2145de74d6333f099613c595c5c46f79f54e59f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2145de74d6333f099613c595c5c46f79f54e59f
Author: Edward O'Callaghan eocallag...@alterapraxis.com
Date: Wed Aug 19 18:58:46 2015 +1000
r600: Rewrite r600_shader_selector_key() to use a switch stmt
Signed-off-by: Edward O'Callaghan eocallag...@alterapraxis.com
Reviewed-by: Marek Olšák marek.ol...@amd.com
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/r600/r600_state_common.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index aa4a8d0..c7445b8 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -709,7 +709,18 @@ static inline struct r600_shader_key
r600_shader_selector_key(struct pipe_contex
struct r600_shader_key key;
memset(key, 0, sizeof(key));
- if (sel-type == PIPE_SHADER_FRAGMENT) {
+ switch (sel-type) {
+ case PIPE_SHADER_VERTEX: {
+ key.vs_as_es = (rctx-gs_shader != NULL);
+ if (rctx-ps_shader-current-shader.gs_prim_id_input
!rctx-gs_shader) {
+ key.vs_as_gs_a = true;
+ key.vs_prim_id_out =
rctx-ps_shader-current-shader.input[rctx-ps_shader-current-shader.ps_prim_id_input].spi_sid;
+ }
+ break;
+ }
+ case PIPE_SHADER_GEOMETRY:
+ break;
+ case PIPE_SHADER_FRAGMENT: {
key.color_two_side = rctx-rasterizer
rctx-rasterizer-two_side;
key.alpha_to_one = rctx-alpha_to_one
rctx-rasterizer
rctx-rasterizer-multisample_enable
@@ -718,13 +729,12 @@ static inline struct r600_shader_key
r600_shader_selector_key(struct pipe_contex
/* Dual-source blending only makes sense with nr_cbufs == 1. */
if (key.nr_cbufs == 1 rctx-dual_src_blend)
key.nr_cbufs = 2;
- } else if (sel-type == PIPE_SHADER_VERTEX) {
- key.vs_as_es = (rctx-gs_shader != NULL);
- if (rctx-ps_shader-current-shader.gs_prim_id_input
!rctx-gs_shader) {
- key.vs_as_gs_a = true;
- key.vs_prim_id_out =
rctx-ps_shader-current-shader.input[rctx-ps_shader-current-shader.ps_prim_id_input].spi_sid;
- }
+ break;
}
+ default:
+ assert(0);
+ }
+
return key;
}
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Mesa (master): r600g: Fix handling of TGSI_OPCODE_ARR with SB
Module: Mesa
Branch: master
Commit: 4237dfb97815a50de7be464a0d62bd19e62d17b7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4237dfb97815a50de7be464a0d62bd19e62d17b7
Author: Glenn Kennard glenn.kenn...@gmail.com
Date: Thu Aug 13 20:30:07 2015 +0200
r600g: Fix handling of TGSI_OPCODE_ARR with SB
FLT_TO_INT goes in the vector pipes on evergreen/NI,
not the trans unit as on earlier chips.
Signed-off-by: Glenn Kennard glenn.kenn...@gmail.com
Reviewed-by: Dave Airlie airl...@redhat.com
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/r600/r600_isa.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/r600_isa.h
b/src/gallium/drivers/r600/r600_isa.h
index 381f06d..fdbe1c0 100644
--- a/src/gallium/drivers/r600/r600_isa.h
+++ b/src/gallium/drivers/r600/r600_isa.h
@@ -262,7 +262,7 @@ static const struct alu_op_info alu_op_table[] = {
{PRED_SETNE_PUSH_INT, 2, { 0x4D, 0x4D },{ AF_VS,
AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_NE | AF_INT_CMP },
{PRED_SETLT_PUSH_INT, 2, { 0x4E, 0x4E },{ AF_VS,
AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_LT | AF_INT_CMP },
{PRED_SETLE_PUSH_INT, 2, { 0x4F, 0x4F },{ AF_VS,
AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_LE | AF_INT_CMP },
- {FLT_TO_INT,1, { 0x6B, 0x50 },{ AF_S,
AF_S, AF_VS, AF_VS}, AF_INT_DST | AF_CVT },
+ {FLT_TO_INT,1, { 0x6B, 0x50 },{ AF_S,
AF_S, AF_V, AF_V}, AF_INT_DST | AF_CVT },
{BFREV_INT, 1, { -1, 0x51 },{ 0,
0, AF_VS, AF_VS}, AF_INT_DST },
{ADDC_UINT, 2, { -1, 0x52 },{ 0,
0, AF_VS, AF_VS}, AF_UINT_DST },
{SUBB_UINT, 2, { -1, 0x53 },{ 0,
0, AF_VS, AF_VS}, AF_UINT_DST },
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Mesa (master): r600: Turn 'r600_shader_key' struct into union
Module: Mesa
Branch: master
Commit: 7a32652231f96eac14c4bfce02afe77b4132fb77
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a32652231f96eac14c4bfce02afe77b4132fb77
Author: Edward O'Callaghan eocallag...@alterapraxis.com
Date: Wed Aug 19 18:58:47 2015 +1000
r600: Turn 'r600_shader_key' struct into union
This struct was getting a bit crowded, following the lead of
radeonsi, mirror the idea of having sub-structures for each
shader type. Turning 'r600_shader_key' into an union saves
some trivial memory and CPU cycles for the shader keys.
[airlied: drop as_ls, and reorder so larger fields at start.]
Signed-off-by: Edward O'Callaghan eocallag...@alterapraxis.com
Reviewed-by: Marek Olšák marek.ol...@amd.com
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/r600/r600_pipe.h |4 ++--
src/gallium/drivers/r600/r600_shader.c | 30 +-
src/gallium/drivers/r600/r600_shader.h | 20 ++---
src/gallium/drivers/r600/r600_state_common.c | 26 +++---
4 files changed, 42 insertions(+), 38 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 9b66105..384ba80 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -90,7 +90,7 @@
struct r600_context;
struct r600_bytecode;
-struct r600_shader_key;
+union r600_shader_key;
/* This is an atom containing GPU commands that never change.
* This is supposed to be copied directly into the CS. */
@@ -643,7 +643,7 @@ void r600_resource_copy_region(struct pipe_context *ctx,
/* r600_shader.c */
int r600_pipe_shader_create(struct pipe_context *ctx,
struct r600_pipe_shader *shader,
- struct r600_shader_key key);
+ union r600_shader_key key);
void r600_pipe_shader_destroy(struct pipe_context *ctx, struct
r600_pipe_shader *shader);
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 8d1f95a..6cbfd1b 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -62,7 +62,7 @@ The compiler must issue the source argument to slots z, y,
and x
static int r600_shader_from_tgsi(struct r600_context *rctx,
struct r600_pipe_shader *pipeshader,
-struct r600_shader_key key);
+union r600_shader_key key);
static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
@@ -133,7 +133,7 @@ static int store_shader(struct pipe_context *ctx,
int r600_pipe_shader_create(struct pipe_context *ctx,
struct r600_pipe_shader *shader,
- struct r600_shader_key key)
+ union r600_shader_key key)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_shader_selector *sel = shader-selector;
@@ -141,7 +141,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
bool dump = r600_can_dump_shader(rctx-screen-b, sel-tokens);
unsigned use_sb = !(rctx-screen-b.debug_flags DBG_NO_SB);
unsigned sb_disasm = use_sb || (rctx-screen-b.debug_flags
DBG_SB_DISASM);
- unsigned export_shader = key.vs_as_es;
+ unsigned export_shader = key.vs.as_es;
shader-shader.bc.isa = rctx-isa;
@@ -1802,7 +1802,7 @@ static int emit_gs_ring_writes(struct r600_shader_ctx
*ctx, bool ind)
static int r600_shader_from_tgsi(struct r600_context *rctx,
struct r600_pipe_shader *pipeshader,
-struct r600_shader_key key)
+union r600_shader_key key)
{
struct r600_screen *rscreen = rctx-screen;
struct r600_shader *shader = pipeshader-shader;
@@ -1816,7 +1816,7 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
unsigned opcode;
int i, j, k, r = 0;
int next_param_base = 0, next_clip_base;
- int max_color_exports = MAX2(key.nr_cbufs, 1);
+ int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
/* Declarations used by llvm code */
bool use_llvm = false;
bool indirect_gprs;
@@ -1830,8 +1830,8 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
ctx.shader = shader;
ctx.native_integers = true;
- shader-vs_as_gs_a = key.vs_as_gs_a;
- shader-vs_as_es = key.vs_as_es;
+ shader-vs_as_gs_a = key.vs.as_gs_a;
+ shader-vs_as_es = key.vs.as_es;
r600_bytecode_init(ctx.bc, rscreen-b.chip_class, rscreen-b.family,
rscreen-has_compressed_msaa_texturing);
@@ -1844,9 +1844,9 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
shader-processor_type = ctx.type;
ctx.bc-type = shader-processor_type;
- ring_outputs =
Mesa (10.6): nv50,nvc0: take level into account when doing eng2d multi-layer blits
Module: Mesa
Branch: 10.6
Commit: 69649ea637c0729b72969b1f466d86708b95bccc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=69649ea637c0729b72969b1f466d86708b95bccc
Author: Ilia Mirkin imir...@alum.mit.edu
Date: Sat Aug 15 22:05:15 2015 -0400
nv50,nvc0: take level into account when doing eng2d multi-layer blits
This fixes arb_get_texture_sub_image-get, and any situation where the 2d
engine was being used for multi-layer blits to a non-0 level.
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
Cc: 10.6 mesa-sta...@lists.freedesktop.org
(cherry picked from commit 2514c78fba507ca8ab94d2e6de553b8b20d653d2)
---
src/gallium/drivers/nouveau/nv50/nv50_surface.c | 14 ++
src/gallium/drivers/nouveau/nvc0/nvc0_surface.c | 14 ++
2 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
index dc9852d..8c9176f 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
@@ -1387,18 +1387,24 @@ nv50_blit_eng2d(struct nv50_context *nv50, const struct
pipe_blit_info *info)
PUSH_DATA (push, info-dst.box.z + i);
} else {
const unsigned z = info-dst.box.z + i;
+const uint64_t address = dst-base.address +
+ dst-level[info-dst.level].offset +
+ z * dst-layer_stride;
BEGIN_NV04(push, NV50_2D(DST_ADDRESS_HIGH), 2);
-PUSH_DATAh(push, dst-base.address + z * dst-layer_stride);
-PUSH_DATA (push, dst-base.address + z * dst-layer_stride);
+PUSH_DATAh(push, address);
+PUSH_DATA (push, address);
}
if (src-layout_3d) {
/* not possible because of depth tiling */
assert(0);
} else {
const unsigned z = info-src.box.z + i;
+const uint64_t address = src-base.address +
+ src-level[info-src.level].offset +
+ z * src-layer_stride;
BEGIN_NV04(push, NV50_2D(SRC_ADDRESS_HIGH), 2);
-PUSH_DATAh(push, src-base.address + z * src-layer_stride);
-PUSH_DATA (push, src-base.address + z * src-layer_stride);
+PUSH_DATAh(push, address);
+PUSH_DATA (push, address);
}
BEGIN_NV04(push, NV50_2D(BLIT_SRC_Y_INT), 1); /* trigger */
PUSH_DATA (push, srcy 32);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
index ac4dd25..44fe1b0 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
@@ -1336,18 +1336,24 @@ nvc0_blit_eng2d(struct nvc0_context *nvc0, const struct
pipe_blit_info *info)
PUSH_DATA (push, info-dst.box.z + i);
} else {
const unsigned z = info-dst.box.z + i;
+const uint64_t address = dst-base.address +
+ dst-level[info-dst.level].offset +
+ z * dst-layer_stride;
BEGIN_NVC0(push, NVC0_2D(DST_ADDRESS_HIGH), 2);
-PUSH_DATAh(push, dst-base.address + z * dst-layer_stride);
-PUSH_DATA (push, dst-base.address + z * dst-layer_stride);
+PUSH_DATAh(push, address);
+PUSH_DATA (push, address);
}
if (src-layout_3d) {
/* not possible because of depth tiling */
assert(0);
} else {
const unsigned z = info-src.box.z + i;
+const uint64_t address = src-base.address +
+ src-level[info-src.level].offset +
+ z * src-layer_stride;
BEGIN_NVC0(push, NVC0_2D(SRC_ADDRESS_HIGH), 2);
-PUSH_DATAh(push, src-base.address + z * src-layer_stride);
-PUSH_DATA (push, src-base.address + z * src-layer_stride);
+PUSH_DATAh(push, address);
+PUSH_DATA (push, address);
}
BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_Y_INT), 1); /* trigger */
PUSH_DATA (push, srcy 32);
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Mesa (10.6): radeonsi: fix polygon offset scale
Module: Mesa
Branch: 10.6
Commit: e7e38e11c3ec7ae03d46451ce45b7226a56ac25c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7e38e11c3ec7ae03d46451ce45b7226a56ac25c
Author: Marek Olšák marek.ol...@amd.com
Date: Tue Aug 11 22:36:51 2015 +0200
radeonsi: fix polygon offset scale
The value was copied from r300g, which uses 1/12 subpixels, but this hw
uses 1/16 subpixels.
Fixes piglit: gl-1.4-polygon-offset (formerly a glean test)
Reviewed-by: Michel Dänzer michel.daen...@amd.com
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit bfac8ba9d32be351277c7ea814ac9848bdcb1f16)
---
src/gallium/drivers/radeonsi/si_state.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 7f0fdd5..4d38a32 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -634,7 +634,7 @@ static void *si_create_rs_state(struct pipe_context *ctx,
/* offset */
rs-offset_units = state-offset_units;
- rs-offset_scale = state-offset_scale * 12.0f;
+ rs-offset_scale = state-offset_scale * 16.0f;
tmp = S_0286D4_FLAT_SHADE_ENA(1);
if (state-sprite_coord_enable) {
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Mesa (10.6): meta/copy_image: Stash off the scissor
Module: Mesa Branch: 10.6 Commit: 3ebf4afbf704dd7f4b537694a6641de32f856669 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ebf4afbf704dd7f4b537694a6641de32f856669 Author: Jason Ekstrand jason.ekstr...@intel.com Date: Thu Jul 23 17:26:56 2015 -0700 meta/copy_image: Stash off the scissor The meta CopyImageSubData path uses BlitFramebuffers to do the actual copy. The only thing that can affect BlitFramebuffers other than the currently bound framebuffers is the scissor so we need to save that off and reset it. If we don't do this, applications that use a scissor together with CopyImageSubData will get accidentally scissored copies. Tested-by: Markus Wick markus at selfnet.de Reviewed-by: Anuj Phogat anuj.pho...@gmail.com (cherry picked from commit 736c6f3cfc2c69e3c29268d4ebb7110dd36ac97f) --- src/mesa/drivers/common/meta_copy_image.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/common/meta_copy_image.c b/src/mesa/drivers/common/meta_copy_image.c index 1729766..149ed18 100644 --- a/src/mesa/drivers/common/meta_copy_image.c +++ b/src/mesa/drivers/common/meta_copy_image.c @@ -138,8 +138,8 @@ _mesa_meta_CopyImageSubData_uncompressed(struct gl_context *ctx, goto cleanup; } - /* We really only need to stash the bound framebuffers. */ - _mesa_meta_begin(ctx, 0); + /* We really only need to stash the bound framebuffers and scissor. */ + _mesa_meta_begin(ctx, MESA_META_SCISSOR); _mesa_GenFramebuffers(2, fbos); _mesa_BindFramebuffer(GL_READ_FRAMEBUFFER, fbos[0]); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (10.6): r600g: allow setting geometry shader sampler states
Module: Mesa
Branch: 10.6
Commit: 23bbe418fcce69447fb425012e9ac8d149fb5455
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=23bbe418fcce69447fb425012e9ac8d149fb5455
Author: Marek Olšák marek.ol...@amd.com
Date: Tue Aug 11 21:37:59 2015 +0200
r600g: allow setting geometry shader sampler states
We were ignoring them. This is both hilarious and sad.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Edward O'Callaghan eocallaghan at alterapraxis.com
Reviewed-by: Alex Deucher alexander.deuc...@amd.com
(cherry picked from commit 8c0b943e87b48e7359230825cc06fbdd059a9e58)
---
src/gallium/drivers/r600/r600_state_common.c |5 -
1 file changed, 5 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 13dc9ee..baba849 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -399,11 +399,6 @@ static void r600_bind_sampler_states(struct pipe_context
*pipe,
assert(start == 0); /* XXX fix below */
- if (shader != PIPE_SHADER_VERTEX
- shader != PIPE_SHADER_FRAGMENT) {
- return;
- }
-
for (i = 0; i count; i++) {
struct r600_pipe_sampler_state *rstate = rstates[i];
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Mesa (10.6): glx: Fix __glXWireToEvent for BufferSwapComplete
Module: Mesa Branch: 10.6 Commit: e57c526b8705d06f305b3d758edd0312316650a1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e57c526b8705d06f305b3d758edd0312316650a1 Author: Adam Jackson a...@redhat.com Date: Fri Jul 31 11:32:58 2015 -0400 glx: Fix __glXWireToEvent for BufferSwapComplete In the DRI2 path this event is magically synthesized from the corresponding DRI2 event, but with Present, the server sends us the event itself. The DRI2 path fills in the serial number, send_event, and display fields of the XEvent struct that the app sees, but the Present path did not. This is likely related to a class of crashes seen in gtk/clutter apps: https://bugzilla.redhat.com/attachment.cgi?id=1032631 Note that the crashing instruction is looking up the lock_fns slot in the Display *, and %rdi (holding the Display *) is 0x1. Cc: mesa-sta...@lists.freedesktop.org Signed-off-by: Adam Jackson a...@redhat.com Reviewed-by: Eric Anholt e...@anholt.net (cherry picked from commit 8f7ebcb6fad53ea6d2f80fc5b7a046db07690032) --- src/glx/glxext.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/src/glx/glxext.c b/src/glx/glxext.c index fdc24d4..dc87fb9 100644 --- a/src/glx/glxext.c +++ b/src/glx/glxext.c @@ -138,6 +138,9 @@ __glXWireToEvent(Display *dpy, XEvent *event, xEvent *wire) if (!glxDraw) return False; + aevent-serial = _XSetLastRequestRead(dpy, (xGenericReply *) wire); + aevent-send_event = (awire-type 0x80) != 0; + aevent-display = dpy; aevent-event_type = awire-event_type; aevent-drawable = glxDraw-xDrawable; aevent-ust = ((CARD64)awire-ust_hi 32) | awire-ust_lo; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (10.6): mesa/formats: don't byteswap when building array formats
Module: Mesa
Branch: 10.6
Commit: b7a8003c588d928c1be224b595a1c43c76f67de6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7a8003c588d928c1be224b595a1c43c76f67de6
Author: Oded Gabbay oded.gab...@gmail.com
Date: Wed Aug 12 18:22:53 2015 +0300
mesa/formats: don't byteswap when building array formats
Because we build here an array format, we don't need to swap the
bytes for big endian.
If it isn't an array format, the bytes will be swapped in
_mesa_format_convert.
v2: remove temp variable
Signed-off-by: Oded Gabbay oded.gab...@gmail.com
Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com
Cc: 10.5 10.6 mesa-sta...@lists.freedesktop.org
(cherry picked from commit 5f1d5b1c7857f8680b47a7a450ee9e4530e22c6f)
---
src/mesa/main/glformats.c | 14 +++---
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index 8ced579..4fc85ab 100644
--- a/src/mesa/main/glformats.c
+++ b/src/mesa/main/glformats.c
@@ -2570,8 +2570,6 @@ get_swizzle_from_gl_format(GLenum format, uint8_t
*swizzle)
uint32_t
_mesa_format_from_format_and_type(GLenum format, GLenum type)
{
- mesa_array_format array_format;
-
bool is_array_format = true;
uint8_t swizzle[4];
bool normalized = false, is_float = false, is_signed = false;
@@ -2627,15 +2625,9 @@ _mesa_format_from_format_and_type(GLenum format, GLenum
type)
normalized = !_mesa_is_enum_format_integer(format);
num_channels = _mesa_components_in_format(format);
- array_format =
- MESA_ARRAY_FORMAT(type_size, is_signed, is_float,
- normalized, num_channels,
- swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
-
- if (!_mesa_little_endian())
- array_format = _mesa_array_format_flip_channels(array_format);
-
- return array_format;
+ return MESA_ARRAY_FORMAT(type_size, is_signed, is_float,
+ normalized, num_channels,
+ swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
}
/* Otherwise this is not an array format, so return the mesa_format
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Mesa (10.6): mesa: clear existing swizzle info before bitwise-OR
Module: Mesa
Branch: 10.6
Commit: d706b00522e23704ea1cee91fd0d5e7dedccca9e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d706b00522e23704ea1cee91fd0d5e7dedccca9e
Author: Oded Gabbay oded.gab...@gmail.com
Date: Tue Aug 4 21:39:32 2015 +0300
mesa: clear existing swizzle info before bitwise-OR
This patch fixes a bug in big-endian treatment, where the previous
swizzle info wasn't cleared before a new swizzle info was inserted into
the format field using a bitwise-OR operation.
v2: use MESA_ARRAY_FORMAT_SWIZZLE_*_MASK instead of numeric constants
v3: align according to coding style
Signed-off-by: Oded Gabbay oded.gab...@gmail.com
CC: 10.5 10.6 mesa-sta...@lists.freedesktop.org
Reviewed-by: Emil Velikov emil.l.veli...@gmail.com
Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com
(cherry picked from commit 2ac171a7db4e4ad2fa902e62bf18bc1f67e91643)
---
src/mesa/main/formats.h |5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/main/formats.h b/src/mesa/main/formats.h
index 7e451ca..d938e6a 100644
--- a/src/mesa/main/formats.h
+++ b/src/mesa/main/formats.h
@@ -191,6 +191,11 @@ static inline void
_mesa_array_format_set_swizzle(mesa_array_format *f,
int32_t x, int32_t y, int32_t z, int32_t w)
{
+ *f = ~(MESA_ARRAY_FORMAT_SWIZZLE_X_MASK |
+ MESA_ARRAY_FORMAT_SWIZZLE_Y_MASK |
+ MESA_ARRAY_FORMAT_SWIZZLE_Z_MASK |
+ MESA_ARRAY_FORMAT_SWIZZLE_W_MASK);
+
*f |= ((x 8 ) MESA_ARRAY_FORMAT_SWIZZLE_X_MASK) |
((y 11) MESA_ARRAY_FORMAT_SWIZZLE_Y_MASK) |
((z 14) MESA_ARRAY_FORMAT_SWIZZLE_Z_MASK) |
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Mesa (10.6): nouveau: no need to do tnl wakeup, state updates are always hooked up
Module: Mesa Branch: 10.6 Commit: 0a7202385d6c129164feb151deec99a0e43ed7bf URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a7202385d6c129164feb151deec99a0e43ed7bf Author: Ilia Mirkin imir...@alum.mit.edu Date: Mon Aug 10 17:41:36 2015 -0400 nouveau: no need to do tnl wakeup, state updates are always hooked up A TNL state update now requires a DrawBuffer to be set, which it isn't early on in context creation. Since we init swtnl from context init, this caused crashes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91570 Signed-off-by: Ilia Mirkin imir...@alum.mit.edu Cc: 10.6 mesa-sta...@lists.freedesktop.org (cherry picked from commit 3fa1ca34cc0134bd16b3315a0695703c9f684bd4) --- src/mesa/drivers/dri/nouveau/nouveau_swtnl_t.c |1 - src/mesa/drivers/dri/nouveau/nv04_render.c |1 - 2 files changed, 2 deletions(-) diff --git a/src/mesa/drivers/dri/nouveau/nouveau_swtnl_t.c b/src/mesa/drivers/dri/nouveau/nouveau_swtnl_t.c index 0753c3a..755de2c 100644 --- a/src/mesa/drivers/dri/nouveau/nouveau_swtnl_t.c +++ b/src/mesa/drivers/dri/nouveau/nouveau_swtnl_t.c @@ -338,7 +338,6 @@ TAG(swtnl_init)(struct gl_context *ctx) NUM_VERTEX_ATTRS * 4 * sizeof(GLfloat)); _tnl_need_projected_coords(ctx, GL_FALSE); _tnl_allow_vertex_fog(ctx, GL_FALSE); - _tnl_wakeup(ctx); swtnl_alloc_vertices(ctx); } diff --git a/src/mesa/drivers/dri/nouveau/nv04_render.c b/src/mesa/drivers/dri/nouveau/nv04_render.c index 30e9f9a..3b7f782 100644 --- a/src/mesa/drivers/dri/nouveau/nv04_render.c +++ b/src/mesa/drivers/dri/nouveau/nv04_render.c @@ -285,7 +285,6 @@ nv04_render_init(struct gl_context *ctx) _tnl_init_vertices(ctx, tnl-vb.Size, NUM_VERTEX_ATTRS * 4 * sizeof(GLfloat)); _tnl_allow_pixel_fog(ctx, GL_FALSE); - _tnl_wakeup(ctx); } void ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (10.6): glsl: avoid compiler' s segfault when processing operators with void arguments
Module: Mesa
Branch: 10.6
Commit: 4a2a49040e6891355a80b582932c5a3cffaa3c16
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a2a49040e6891355a80b582932c5a3cffaa3c16
Author: Renaud Gaubert ren...@lse.epita.fr
Date: Sat Jul 11 19:38:10 2015 +0200
glsl: avoid compiler's segfault when processing operators with void arguments
This is done by returning an rvalue of type void in the
ast_function_expression::hir function instead of a void expression.
This produces (in the case of the ternary) an hir with a call
to the void returning function and an assignment of a void variable
which will be optimized out (the assignment) during the optimization
pass.
This fix results in having a valid subexpression in the many
different cases where the subexpressions are functions whose
return values are void.
Thus preventing to dereference NULL in the following cases:
* binary operator
* unary operators
* ternary operator
* comparison operators (except equal and nequal operator)
Equal and nequal had to be handled as a special case because
instead of segfaulting on a forbidden syntax it was now accepting
expressions with a void return value on either (or both) side of
the expression.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85252
Signed-off-by: Renaud Gaubert ren...@lse.epita.fr
Reviewed-by: Gabriel Laskar gabr...@lse.epita.fr
Reviewed-by: Samuel Iglesias Gonsalvez sigles...@igalia.com
(cherry picked from commit 7b9ebf879b6f35038996805a641667f00d93c4b7)
Nominated-by: Mark Janes mark.a.ja...@intel.com
---
src/glsl/ast_function.cpp |9 -
src/glsl/ast_to_hir.cpp |9 -
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/src/glsl/ast_function.cpp b/src/glsl/ast_function.cpp
index 7583613..8d2c801 100644
--- a/src/glsl/ast_function.cpp
+++ b/src/glsl/ast_function.cpp
@@ -1773,7 +1773,14 @@ ast_function_expression::hir(exec_list *instructions,
/* an error has already been emitted */
value = ir_rvalue::error_value(ctx);
} else {
-value = generate_call(instructions, sig, actual_parameters, state);
+ value = generate_call(instructions, sig, actual_parameters, state);
+ if (!value) {
+ir_variable *const tmp = new(ctx) ir_variable(glsl_type::void_type,
+ void_var,
+ ir_var_temporary);
+instructions-push_tail(tmp);
+value = new(ctx) ir_dereference_variable(tmp);
+ }
}
return value;
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index a0154f1..05d00d8 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -1270,7 +1270,14 @@ ast_expression::do_hir(exec_list *instructions,
*applied to one operand that can make them match, in which
*case this conversion is done.
*/
- if ((!apply_implicit_conversion(op[0]-type, op[1], state)
+
+ if (op[0]-type == glsl_type::void_type || op[1]-type ==
glsl_type::void_type) {
+ _mesa_glsl_error( loc, state, `%s': wrong operand types:
+ no operation `%1$s' exists that takes a left-hand
+ operand of type 'void' or a right operand of type
+ 'void', (this-oper == ast_equal) ? == : !=);
+ error_emitted = true;
+ } else if ((!apply_implicit_conversion(op[0]-type, op[1], state)
!apply_implicit_conversion(op[1]-type, op[0], state))
|| (op[0]-type != op[1]-type)) {
_mesa_glsl_error( loc, state, operands of `%s' must have the same
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Mesa (10.6): egl/x11: don't abort when creating a DRI2 drawable fails
Module: Mesa
Branch: 10.6
Commit: 16c65ec37f5554041fa3dd8238d435041ac38526
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=16c65ec37f5554041fa3dd8238d435041ac38526
Author: Frank Binns frank.bi...@imgtec.com
Date: Tue Aug 4 14:32:45 2015 +0100
egl/x11: don't abort when creating a DRI2 drawable fails
When calling either eglCreateWindowSurface or eglCreatePixmapSurface it
was possible for an application to be aborted as a result of it failing
to create a DRI2 drawable on the server. This could happen due to an
application passing in an invalid native drawable handle, for example.
v2: Handle the case where an error has been set on the connection
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Frank Binns frank.bi...@imgtec.com
Reviewed-by: Emil Velikov emil.l.veli...@gmail.com
(cherry picked from commit 9a4eae61c24858d69d731d63b141d2acaed40d69)
---
src/egl/drivers/dri2/platform_x11.c | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/src/egl/drivers/dri2/platform_x11.c
b/src/egl/drivers/dri2/platform_x11.c
index 809974b..66342c1 100644
--- a/src/egl/drivers/dri2/platform_x11.c
+++ b/src/egl/drivers/dri2/platform_x11.c
@@ -273,7 +273,25 @@ dri2_x11_create_surface(_EGLDriver *drv, _EGLDisplay
*disp, EGLint type,
}
if (dri2_dpy-dri2) {
- xcb_dri2_create_drawable (dri2_dpy-conn, dri2_surf-drawable);
+ xcb_void_cookie_t cookie;
+ int conn_error;
+
+ cookie = xcb_dri2_create_drawable_checked(dri2_dpy-conn,
+dri2_surf-drawable);
+ error = xcb_request_check(dri2_dpy-conn, cookie);
+ conn_error = xcb_connection_has_error(dri2_dpy-conn);
+ if (conn_error || error != NULL) {
+ if (type == EGL_PBUFFER_BIT || conn_error || error-error_code ==
BadAlloc)
+_eglError(EGL_BAD_ALLOC, xcb_dri2_create_drawable_checked);
+ else if (type == EGL_WINDOW_BIT)
+_eglError(EGL_BAD_NATIVE_WINDOW,
+ xcb_dri2_create_drawable_checked);
+ else
+_eglError(EGL_BAD_NATIVE_PIXMAP,
+ xcb_dri2_create_drawable_checked);
+ free(error);
+ goto cleanup_dri_drawable;
+ }
} else {
if (type == EGL_PBUFFER_BIT) {
dri2_surf-depth = _eglGetConfigKey(conf, EGL_BUFFER_SIZE);
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Mesa (10.6): mesa/formats: Only do byteswapping for packed formats
Module: Mesa
Branch: 10.6
Commit: c364a00cf957f4e0b5e4d039f1736f54c57e7fde
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c364a00cf957f4e0b5e4d039f1736f54c57e7fde
Author: Jason Ekstrand jason.ekstr...@intel.com
Date: Sat Aug 8 09:00:21 2015 -0700
mesa/formats: Only do byteswapping for packed formats
Reviewed-by: Iago Toral ito...@igalia.com
Cc: 10.6 10.5 mesa-sta...@lists.freedesktop.org
(cherry picked from commit 3941539179b72fe25b6dffd1aacc0722d198a5ca)
---
src/mesa/main/formats.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index 8af44e9..99a5ad3 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -372,10 +372,10 @@ uint32_t
_mesa_format_to_array_format(mesa_format format)
{
const struct gl_format_info *info = _mesa_get_format_info(format);
- if (_mesa_little_endian())
- return info-ArrayFormat;
- else
+ if (!_mesa_little_endian() info-Layout == MESA_FORMAT_LAYOUT_PACKED)
return _mesa_array_format_flip_channels(info-ArrayFormat);
+ else
+ return info-ArrayFormat;
}
static struct hash_table *format_array_format_table;
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Mesa (10.6): r600g: fix polygon offset scale
Module: Mesa
Branch: 10.6
Commit: f40be8799671e1195274ae846cd329d7a71c80bb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f40be8799671e1195274ae846cd329d7a71c80bb
Author: Marek Olšák marek.ol...@amd.com
Date: Tue Aug 11 22:36:51 2015 +0200
r600g: fix polygon offset scale
The value was copied from r300g, which uses 1/12 subpixels, but this hw
uses 1/16 subpixels.
Should fix piglit: gl-1.4-polygon-offset (formerly a glean test)
(untested, ported from radeonsi)
Reviewed-by: Edward O'Callaghan eocallaghan at alterapraxis.com
Reviewed-by: Alex Deucher alexander.deuc...@amd.com
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit d335aad11b208bcdcc75a99d4b6c5fc8b69ce368)
---
src/gallium/drivers/r600/evergreen_state.c |2 +-
src/gallium/drivers/r600/r600_state.c |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 3256332..a7c705d 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -485,7 +485,7 @@ static void *evergreen_create_rs_state(struct pipe_context
*ctx,
/* offset */
rs-offset_units = state-offset_units;
- rs-offset_scale = state-offset_scale * 12.0f;
+ rs-offset_scale = state-offset_scale * 16.0f;
rs-offset_enable = state-offset_point || state-offset_line ||
state-offset_tri;
if (state-point_size_per_vertex) {
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 960dfce..254201e 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -473,7 +473,7 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
/* offset */
rs-offset_units = state-offset_units;
- rs-offset_scale = state-offset_scale * 12.0f;
+ rs-offset_scale = state-offset_scale * 16.0f;
rs-offset_enable = state-offset_point || state-offset_line ||
state-offset_tri;
if (state-point_size_per_vertex) {
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Mesa (10.6): mesa/formats: Don't flip channels of null array formats
Module: Mesa
Branch: 10.6
Commit: d18593b4160d75d21e8e5849aeb021514bd77b35
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d18593b4160d75d21e8e5849aeb021514bd77b35
Author: Jason Ekstrand jason.ekstr...@intel.com
Date: Mon Aug 10 01:32:23 2015 -0700
mesa/formats: Don't flip channels of null array formats
Before, if we encountered an array format of 0 on a BE system, we would
flip all the channels even though it's an invalid format. This would
result in a mostly invalid format with a swizzle of or . Instead,
we should just return 0 if the array format stashed in the format info is
invalid.
Cc: 10.6 10.5 mesa-sta...@lists.freedesktop.org
(cherry picked from commit e3eb91af804f449005a2ff535c805eaa1d579d99)
---
src/mesa/main/formats.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index a20a41d..bedab99 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -380,7 +380,8 @@ uint32_t
_mesa_format_to_array_format(mesa_format format)
{
const struct gl_format_info *info = _mesa_get_format_info(format);
- if (!_mesa_little_endian() info-Layout == MESA_FORMAT_LAYOUT_PACKED)
+ if (info-ArrayFormat !_mesa_little_endian()
+ info-Layout == MESA_FORMAT_LAYOUT_PACKED)
return _mesa_array_format_flip_channels(info-ArrayFormat);
else
return info-ArrayFormat;
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Mesa (10.6): radeonsi: add new OLAND pci id
Module: Mesa Branch: 10.6 Commit: e5a198e4dd4771621e70f8a4c8f685e05a3cb22f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5a198e4dd4771621e70f8a4c8f685e05a3cb22f Author: Alex Deucher alexander.deuc...@amd.com Date: Mon Aug 10 15:35:21 2015 -0400 radeonsi: add new OLAND pci id Reviewed-by: Edward O'Callaghan eocallag...@alterapraxis.com Reviewed-by: Michel Dänzer michel.daen...@amd.com Signed-off-by: Alex Deucher alexander.deuc...@amd.com Cc: mesa-sta...@lists.freedesktop.org (cherry picked from commit 87cea61b9e2681e5365e989c7fa7a0298e4005fa) --- include/pci_ids/radeonsi_pci_ids.h |1 + 1 file changed, 1 insertion(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index cd5da99..f451b7d 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -63,6 +63,7 @@ CHIPSET(0x6608, OLAND_6608, OLAND) CHIPSET(0x6610, OLAND_6610, OLAND) CHIPSET(0x6611, OLAND_6611, OLAND) CHIPSET(0x6613, OLAND_6613, OLAND) +CHIPSET(0x6617, OLAND_6617, OLAND) CHIPSET(0x6620, OLAND_6620, OLAND) CHIPSET(0x6621, OLAND_6621, OLAND) CHIPSET(0x6623, OLAND_6623, OLAND) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (10.6): i965/bdw: Fix setting the instancing state for the SGVS element
Module: Mesa
Branch: 10.6
Commit: e9ab083702fb6be6444224074632b0d36e6a16da
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9ab083702fb6be6444224074632b0d36e6a16da
Author: Neil Roberts n...@linux.intel.com
Date: Mon Jul 13 18:01:13 2015 +0100
i965/bdw: Fix setting the instancing state for the SGVS element
When gl_VertexID or gl_InstanceID is used a 3DSTATE_VF_SGVS
instruction is sent to create a sort of element to store the generated
values. The last instruction in this chunk of code looks like it was
trying to set the instancing state for the element using the
3DSTATE_VF_INSTANCING instruction. However it was sending
brw-vb.nr_buffers instead of the element index. This instruction is
supposed to take an element index and that is how it is used further
down in the function so the previous code looks wrong. Perhaps
previously the number of buffers coincidentally matched the number of
enabled elements so the value was generally correct anyway. In a
subsequent patch I want to change a bit how it chooses the SGVS
element index so this needs to be fixed.
v2 [by Ben]
Remove stable 10.5 stable tag (it's too late now)
Commit update as follows:
The number of vertex buffers emitted is always = the number of vertex elements.
To maximize reuse (actually, to minimize relocations - according to the code
comments), a vertex buffer is only emitted once, even when we setup multiple
components (3DSTATE_VERTEX_ELEMENT) from that buffer. This meant that the
previous code would use the wrong indexed element for these reuse cases. This
patch by itself prevents hangs on BSW in the linked bug. It doesn't make the
test pass, the remaining patches are needed for that.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91610
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Reviewed-by: Ben Widawsky b...@bwidawsk.net
Tested-by: Mark Janes mark.a.ja...@intel.com
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit c03247bae010dfd81a08572a32067e9ea8637f63)
---
src/mesa/drivers/dri/i965/gen8_draw_upload.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_draw_upload.c
b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
index 1af90ec..f7d9952 100644
--- a/src/mesa/drivers/dri/i965/gen8_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
@@ -74,7 +74,7 @@ gen8_emit_vertices(struct brw_context *brw)
BEGIN_BATCH(3);
OUT_BATCH(_3DSTATE_VF_INSTANCING 16 | (3 - 2));
- OUT_BATCH(brw-vb.nr_buffers | GEN8_VF_INSTANCING_ENABLE);
+ OUT_BATCH(vue | GEN8_VF_INSTANCING_ENABLE);
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
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Mesa (10.6): mesa/formats: Fix swizzle flipping for big-endian targets
Module: Mesa
Branch: 10.6
Commit: 096282a662a303c24f5de5d8a0eeb16239f0c537
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=096282a662a303c24f5de5d8a0eeb16239f0c537
Author: Jason Ekstrand jason.ekstr...@intel.com
Date: Sun Aug 9 23:45:44 2015 -0700
mesa/formats: Fix swizzle flipping for big-endian targets
The swizzle defines where in the format you should look for any given
channel. When we flip the format around for BE targets, we need to change
the destinations of the swizzles, not the sources. For example, say the
format is an RGBX format with a swizzle of xyz1 on LE. Then it should be
wzy1 on BE; however, the code as it was before, would have made it 1zyx on
BE which is clearly wrong.
Reviewed-by: Iago Toral ito...@igalia.com
Reviewed-by: Oded Gabbay oded.gab...@gmail.com
Cc: 10.6 10.5 mesa-sta...@lists.freedesktop.org
(cherry picked from commit 28d1a506c8d09fa66170978c85566c34cbf1cc0a)
---
src/mesa/main/formats.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index 99a5ad3..a20a41d 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -354,14 +354,22 @@ _mesa_array_format_flip_channels(mesa_array_format format)
return format;
if (num_channels == 2) {
- _mesa_array_format_set_swizzle(format, swizzle[1], swizzle[0],
- swizzle[2], swizzle[3]);
+ /* Assert that the swizzle makes sense for 2 channels */
+ for (unsigned i = 0; i 4; i++)
+ assert(swizzle[i] != 2 swizzle[i] != 3);
+
+ static const uint8_t flip_xy[6] = { 1, 0, 2, 3, 4, 5 };
+ _mesa_array_format_set_swizzle(format,
+ flip_xy[swizzle[0]], flip_xy[swizzle[1]],
+ flip_xy[swizzle[2]], flip_xy[swizzle[3]]);
return format;
}
if (num_channels == 4) {
- _mesa_array_format_set_swizzle(format, swizzle[3], swizzle[2],
- swizzle[1], swizzle[0]);
+ static const uint8_t flip[6] = { 3, 2, 1, 0, 4, 5 };
+ _mesa_array_format_set_swizzle(format,
+ flip[swizzle[0]], flip[swizzle[1]],
+ flip[swizzle[2]], flip[swizzle[3]]);
return format;
}
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Mesa (10.6): vc4: add missing nir include, to fix the build
Module: Mesa Branch: 10.6 Commit: d02bb82d52da5029ae2e2cb77f6d2568f5ed425b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d02bb82d52da5029ae2e2cb77f6d2568f5ed425b Author: Emil Velikov emil.l.veli...@gmail.com Date: Fri Jul 17 12:52:27 2015 +0100 vc4: add missing nir include, to fix the build Cc: 10.6 mesa-sta...@lists.freedesktop.org Signed-off-by: Emil Velikov emil.l.veli...@gmail.com Reviewed-by: Eric Anholt e...@anholt.net (cherry picked from commit 75ce7919d6496981013a21a7055c668e47e7bed2) --- src/gallium/drivers/vc4/Makefile.am |1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/vc4/Makefile.am b/src/gallium/drivers/vc4/Makefile.am index 3fc591f..3e9f184 100644 --- a/src/gallium/drivers/vc4/Makefile.am +++ b/src/gallium/drivers/vc4/Makefile.am @@ -30,6 +30,7 @@ SIM_LDFLAGS = -lsimpenrose endif AM_CFLAGS = \ + -I$(top_builddir)/src/glsl/nir \ $(LIBDRM_CFLAGS) \ $(GALLIUM_DRIVER_CFLAGS) \ $(SIM_CFLAGS) \ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (10.6): gm107/ir: indirect handle goes first on maxwell also
Module: Mesa
Branch: 10.6
Commit: 0a831196665f8a9c2c5001f9c1890e073bac9f14
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a831196665f8a9c2c5001f9c1890e073bac9f14
Author: Ilia Mirkin imir...@alum.mit.edu
Date: Fri Aug 14 14:10:36 2015 -0400
gm107/ir: indirect handle goes first on maxwell also
Fixes fs-simple-texture-size.shader_test
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
Cc: 10.6 mesa-sta...@lists.freedesktop.org
(cherry picked from commit b346a84e270a50f0a8f1a6e474a51da04dd72f0e)
---
.../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index e71fa11..3fd19a9 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -987,14 +987,10 @@ NVC0LoweringPass::handleTXQ(TexInstruction *txq)
txq-tex.r = 0xff;
txq-tex.s = 0x1f;
- if (chipset NVISA_GM107_CHIPSET) {
- txq-setIndirectR(NULL);
- txq-moveSources(0, 1);
- txq-setSrc(0, hnd);
- txq-tex.rIndirectSrc = 0;
- } else {
- txq-setIndirectR(hnd);
- }
+ txq-setIndirectR(NULL);
+ txq-moveSources(0, 1);
+ txq-setSrc(0, hnd);
+ txq-tex.rIndirectSrc = 0;
}
return true;
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Mesa (10.6): radeonsi: properly set the raster_config for KV
Module: Mesa
Branch: 10.6
Commit: 20bb0a771dded700ba1b213256bf47dfedbdfd77
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=20bb0a771dded700ba1b213256bf47dfedbdfd77
Author: Alex Deucher alexander.deuc...@amd.com
Date: Wed Jun 10 11:39:30 2015 -0400
radeonsi: properly set the raster_config for KV
This enables the second RB on asics that support it which
should boost performance.
Reviewed-by: Marek Olšák marek.ol...@amd.com
Signed-off-by: Alex Deucher alexander.deuc...@amd.com
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit 649975e7162cc4ee0586ee76d24321cd7250581f)
---
src/gallium/drivers/radeonsi/si_state.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 4d38a32..fb6dba2 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3023,6 +3023,7 @@ si_write_harvested_raster_configs(struct si_context *sctx,
void si_init_config(struct si_context *sctx)
{
+ unsigned num_rb = sctx-screen-b.info.r600_num_backends;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
if (pm4 == NULL)
@@ -3071,14 +3072,17 @@ void si_init_config(struct si_context *sctx)
si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
0x002e);
break;
case CHIP_KAVERI:
- /* XXX todo */
+ if (num_rb 1)
+ si_pm4_set_reg(pm4,
R_028350_PA_SC_RASTER_CONFIG, 0x0002);
+ else
+ si_pm4_set_reg(pm4,
R_028350_PA_SC_RASTER_CONFIG, 0x);
+ si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
0x);
+ break;
case CHIP_KABINI:
- /* XXX todo */
case CHIP_MULLINS:
- /* XXX todo */
default:
- si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0);
- si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0);
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
0x);
+ si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
0x);
break;
}
} else {
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Mesa (master): i965: Fix handle nir_intrinsic_image_size
Module: Mesa
Branch: master
Commit: 56ebd3314bfc5895fab47586fc8cda024aac4fd8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=56ebd3314bfc5895fab47586fc8cda024aac4fd8
Author: Martin Peres martin.pe...@linux.intel.com
Date: Thu Aug 20 15:15:56 2015 +0300
i965: Fix handle nir_intrinsic_image_size
I pushed a half-baked version of i965: handle nir_intrinsic_image_size by
accident. Not having the Reviewed-by: tags on the last two commits should
have been a red flag but I somehow missed it after the QA check.
This patch should fix image-size for non-int images. I will add support to
the piglit test for all the other image types.
Sorry for the noise.
Signed-off-by: Martin Peres martin.pe...@linux.intel.com
Reviewed-by: Francisco Jerez curroje...@riseup.net
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp |7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 12471fb..c726c72 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -1410,7 +1410,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder bld,
nir_intrinsic_instr *instr
/* Get the referenced image variable and type. */
const nir_variable *var = instr-variables[0]-var;
const glsl_type *type = var-type-without_array();
- const brw_reg_type base_type = get_image_base_type(type);
/* Get the size of the image. */
const fs_reg image = get_nir_image_deref(instr-variables[0]);
@@ -1437,14 +1436,14 @@ fs_visitor::nir_emit_intrinsic(const fs_builder bld,
nir_intrinsic_instr *instr
bld.MOV(offset(retype(dest, BRW_REGISTER_TYPE_D), bld, c),
fs_reg(1));
} else if (c == 1 is_1d_array_image) {
-bld.MOV(offset(retype(dest, base_type), bld, c),
+bld.MOV(offset(retype(dest, BRW_REGISTER_TYPE_D), bld, c),
offset(size, bld, 2));
} else if (c == 2 is_cube_array_image) {
bld.emit(SHADER_OPCODE_INT_QUOTIENT,
- offset(retype(dest, base_type), bld, c),
+ offset(retype(dest, BRW_REGISTER_TYPE_D), bld, c),
offset(size, bld, c), fs_reg(6));
} else {
-bld.MOV(offset(retype(dest, base_type), bld, c),
+bld.MOV(offset(retype(dest, BRW_REGISTER_TYPE_D), bld, c),
offset(size, bld, c));
}
}
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Mesa (master): nvc0/ir: don' t require AND when the high byte is being addressed
Module: Mesa
Branch: master
Commit: 9ebe7dc09479d9a8df2733ef96525a2b5e758f6d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ebe7dc09479d9a8df2733ef96525a2b5e758f6d
Author: Ilia Mirkin imir...@alum.mit.edu
Date: Tue Aug 18 22:53:11 2015 -0400
nvc0/ir: don't require AND when the high byte is being addressed
unpackUnorm* lowering doesn't AND the high byte/word as it's
unnecessary. Detect that situation as well.
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 12
1 file changed, 12 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index ef286c0..cf83c19 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1532,6 +1532,7 @@ AlgebraicOpt::handleCVT_NEG(Instruction *cvt)
// CVT(EXTBF(x, byte/word))
// CVT(AND(bytemask, x))
// CVT(AND(bytemask, SHR(x, 8/16/24)))
+// CVT(SHR(x, 16/24))
void
AlgebraicOpt::handleCVT_EXTBF(Instruction *cvt)
{
@@ -1578,6 +1579,17 @@ AlgebraicOpt::handleCVT_EXTBF(Instruction *cvt)
arg = shift-getSrc(0);
offset = imm1.reg.data.u32;
}
+ } else if (insn-op == OP_SHR insn-src(1).getImmediate(imm0)) {
+ arg = insn-getSrc(0);
+ if (imm0.reg.data.u32 == 24) {
+ width = 8;
+ offset = 24;
+ } else if (imm0.reg.data.u32 == 16) {
+ width = 16;
+ offset = 16;
+ } else {
+ return;
+ }
}
if (!arg)
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Mesa (master): nv50/ir: Handle OP_CVT when folding constant expressions
Module: Mesa
Branch: master
Commit: 3e6adbd761f72b612aba57fd86bb5203aae07133
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e6adbd761f72b612aba57fd86bb5203aae07133
Author: Tobias Klausmann tobias.johannes.klausm...@mni.thm.de
Date: Sun Jan 11 22:40:22 2015 +0100
nv50/ir: Handle OP_CVT when folding constant expressions
[imirkin: handle more type combinations, use macro]
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 78
1 file changed, 78 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 6bef353..b01ef41 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1132,6 +1132,84 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue
imm0, int s)
i-op = OP_MOV;
break;
}
+ case OP_CVT: {
+ Storage res;
+
+ // TODO: handle 64-bit values properly
+ if (typeSizeof(i-dType) == 8 || typeSizeof(i-sType) == 8)
+ return;
+
+ // TODO: handle single byte/word extractions
+ if (i-subOp)
+ return;
+
+ bld.setPosition(i, true); /* make sure bld is init'ed */
+
+#define CASE(type, dst, fmin, fmax, imin, imax, umin, umax) \
+ case type: \
+ switch (i-sType) { \
+ case TYPE_F32: \
+ res.data.dst = util_iround(i-saturate ? \
+CLAMP(imm0.reg.data.f32, fmin, fmax) : \
+imm0.reg.data.f32); \
+ break; \
+ case TYPE_S32: \
+ res.data.dst = i-saturate ? \
+CLAMP(imm0.reg.data.s32, imin, imax) : \
+imm0.reg.data.s32; \
+ break; \
+ case TYPE_U32: \
+ res.data.dst = i-saturate ? \
+CLAMP(imm0.reg.data.u32, umin, umax) : \
+imm0.reg.data.u32; \
+ break; \
+ case TYPE_S16: \
+ res.data.dst = i-saturate ? \
+CLAMP(imm0.reg.data.s16, imin, imax) : \
+imm0.reg.data.s16; \
+ break; \
+ case TYPE_U16: \
+ res.data.dst = i-saturate ? \
+CLAMP(imm0.reg.data.u16, umin, umax) : \
+imm0.reg.data.u16; \
+ break; \
+ default: return; \
+ } \
+ i-setSrc(0, bld.mkImm(res.data.dst)); \
+ break
+
+ switch(i-dType) {
+ CASE(TYPE_U16, u16, 0, UINT16_MAX, 0, UINT16_MAX, 0, UINT16_MAX);
+ CASE(TYPE_S16, s16, INT16_MIN, INT16_MAX, INT16_MIN, INT16_MAX, 0,
INT16_MAX);
+ CASE(TYPE_U32, u32, 0, UINT32_MAX, 0, INT32_MAX, 0, UINT32_MAX);
+ CASE(TYPE_S32, s32, INT32_MIN, INT32_MAX, INT32_MIN, INT32_MAX, 0,
INT32_MAX);
+ case TYPE_F32:
+ switch (i-sType) {
+ case TYPE_F32:
+res.data.f32 = i-saturate ?
+ CLAMP(imm0.reg.data.f32, 0.0f, 1.0f) :
+ imm0.reg.data.f32;
+break;
+ case TYPE_U16: res.data.f32 = (float) imm0.reg.data.u16; break;
+ case TYPE_U32: res.data.f32 = (float) imm0.reg.data.u32; break;
+ case TYPE_S16: res.data.f32 = (float) imm0.reg.data.s16; break;
+ case TYPE_S32: res.data.f32 = (float) imm0.reg.data.s32; break;
+ default:
+return;
+ }
+ i-setSrc(0, bld.mkImm(res.data.f32));
+ break;
+ default:
+ return;
+ }
+#undef CASE
+
+ i-setType(i-dType); /* Remove i-sType, which we don't need anymore */
+ i-op = OP_MOV;
+ i-saturate = 0;
+ i-src(0).mod = Modifier(0); /* Clear the already applied modifier */
+ break;
+ }
default:
return;
}
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Mesa (master): nvc0/ir: undo more shifts still by allowing a pre-SHL to occur
Module: Mesa
Branch: master
Commit: f5b926183ded75661ab3f786ac1739b1f912c6c5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5b926183ded75661ab3f786ac1739b1f912c6c5
Author: Ilia Mirkin imir...@alum.mit.edu
Date: Tue Aug 18 23:16:32 2015 -0400
nvc0/ir: undo more shifts still by allowing a pre-SHL to occur
This happens with unpackSnorm lowering. There's yet another
bitfield-extract behind it, but there's too much variation to be worth
cutting through.
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 48 ++--
1 file changed, 33 insertions(+), 15 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index cf83c19..6bef353 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1537,14 +1537,14 @@ void
AlgebraicOpt::handleCVT_EXTBF(Instruction *cvt)
{
Instruction *insn = cvt-getSrc(0)-getInsn();
- ImmediateValue imm0, imm1;
+ ImmediateValue imm;
Value *arg = NULL;
unsigned width, offset;
if ((cvt-sType != TYPE_U32 cvt-sType != TYPE_S32) || !insn)
return;
- if (insn-op == OP_EXTBF insn-src(1).getImmediate(imm0)) {
- width = (imm0.reg.data.u32 8) 0xff;
- offset = imm0.reg.data.u32 0xff;
+ if (insn-op == OP_EXTBF insn-src(1).getImmediate(imm)) {
+ width = (imm.reg.data.u32 8) 0xff;
+ offset = imm.reg.data.u32 0xff;
arg = insn-getSrc(0);
if (width != 8 width != 16)
@@ -1555,16 +1555,16 @@ AlgebraicOpt::handleCVT_EXTBF(Instruction *cvt)
return;
} else if (insn-op == OP_AND) {
int s;
- if (insn-src(0).getImmediate(imm0))
+ if (insn-src(0).getImmediate(imm))
s = 0;
- else if (insn-src(1).getImmediate(imm0))
+ else if (insn-src(1).getImmediate(imm))
s = 1;
else
return;
- if (imm0.reg.data.u32 == 0xff)
+ if (imm.reg.data.u32 == 0xff)
width = 8;
- else if (imm0.reg.data.u32 == 0x)
+ else if (imm.reg.data.u32 == 0x)
width = 16;
else
return;
@@ -1573,18 +1573,21 @@ AlgebraicOpt::handleCVT_EXTBF(Instruction *cvt)
Instruction *shift = arg-getInsn();
offset = 0;
if (shift shift-op == OP_SHR
- shift-src(1).getImmediate(imm1)
- ((width == 8 (imm1.reg.data.u32 0x7) == 0) ||
- (width == 16 (imm1.reg.data.u32 0xf) == 0))) {
+ shift-sType == cvt-sType
+ shift-src(1).getImmediate(imm)
+ ((width == 8 (imm.reg.data.u32 0x7) == 0) ||
+ (width == 16 (imm.reg.data.u32 0xf) == 0))) {
arg = shift-getSrc(0);
- offset = imm1.reg.data.u32;
+ offset = imm.reg.data.u32;
}
- } else if (insn-op == OP_SHR insn-src(1).getImmediate(imm0)) {
+ } else if (insn-op == OP_SHR
+ insn-sType == cvt-sType
+ insn-src(1).getImmediate(imm)) {
arg = insn-getSrc(0);
- if (imm0.reg.data.u32 == 24) {
+ if (imm.reg.data.u32 == 24) {
width = 8;
offset = 24;
- } else if (imm0.reg.data.u32 == 16) {
+ } else if (imm.reg.data.u32 == 16) {
width = 16;
offset = 16;
} else {
@@ -1595,6 +1598,21 @@ AlgebraicOpt::handleCVT_EXTBF(Instruction *cvt)
if (!arg)
return;
+ // Irrespective of what came earlier, we can undo a shift on the argument
+ // by adjusting the offset.
+ Instruction *shift = arg-getInsn();
+ if (shift shift-op == OP_SHL
+ shift-src(1).getImmediate(imm)
+ ((width == 8 (imm.reg.data.u32 0x7) == 0) ||
+(width == 16 (imm.reg.data.u32 0xf) == 0))
+ imm.reg.data.u32 = offset) {
+ arg = shift-getSrc(0);
+ offset -= imm.reg.data.u32;
+ }
+
+ // The unpackSnorm lowering still leaves a few shifts behind, but it's too
+ // annoying to detect them.
+
if (width == 8) {
cvt-sType = cvt-sType == TYPE_U32 ? TYPE_U8 : TYPE_S8;
} else {
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Mesa (master): nv50/ir: support different unordered_set implementations
Module: Mesa
Branch: master
Commit: 2a4af36517333ef61d5f7ca2264fec3f49ee3662
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a4af36517333ef61d5f7ca2264fec3f49ee3662
Author: Chih-Wei Huang cwhu...@android-x86.org
Date: Sat Jun 20 02:00:15 2015 +0800
nv50/ir: support different unordered_set implementations
If build with C++11 standard, use std::unordered_set.
Otherwise if build on old Android version with stlport,
use std::tr1::unordered_set with a wrapper class.
Otherwise use std::tr1::unordered_set.
Signed-off-by: Chih-Wei Huang cwhu...@linux.org.tw
Reviewed-by: Ilia Mirkin imir...@alum.mit.edu
---
src/gallium/drivers/nouveau/codegen/nv50_ir.h |8 ++--
.../nouveau/codegen/nv50_ir_lowering_nvc0.cpp |4 +-
.../nouveau/codegen/nv50_ir_lowering_nvc0.h|4 +-
src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp |5 +-
.../drivers/nouveau/codegen/unordered_set.h| 48
5 files changed, 57 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
index 3ddaeaf..ba1b085 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
@@ -29,8 +29,8 @@
#include deque
#include list
#include vector
-#include tr1/unordered_set
+#include codegen/unordered_set.h
#include codegen/nv50_ir_util.h
#include codegen/nv50_ir_graph.h
@@ -585,10 +585,10 @@ public:
static inline Value *get(Iterator);
- std::tr1::unordered_setValueRef * uses;
+ unordered_setValueRef * uses;
std::listValueDef * defs;
- typedef std::tr1::unordered_setValueRef *::iterator UseIterator;
- typedef std::tr1::unordered_setValueRef *::const_iterator UseCIterator;
+ typedef unordered_setValueRef *::iterator UseIterator;
+ typedef unordered_setValueRef *::const_iterator UseCIterator;
typedef std::listValueDef *::iterator DefIterator;
typedef std::listValueDef *::const_iterator DefCIterator;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index c3c302d..b1f4065 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -224,7 +224,7 @@ NVC0LegalizePostRA::findFirstUses(
const Instruction *texi,
const Instruction *insn,
std::listTexUse uses,
- std::tr1::unordered_setconst Instruction * visited)
+ unordered_setconst Instruction * visited)
{
for (int d = 0; insn-defExists(d); ++d) {
Value *v = insn-getDef(d);
@@ -323,7 +323,7 @@ NVC0LegalizePostRA::insertTextureBarriers(Function *fn)
if (!uses)
return false;
for (size_t i = 0; i texes.size(); ++i) {
- std::tr1::unordered_setconst Instruction * visited;
+ unordered_setconst Instruction * visited;
findFirstUses(texes[i], texes[i], uses[i], visited);
}
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
index 13fa83a..2ce52e5 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
@@ -20,8 +20,6 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include tr1/unordered_set
-
#include codegen/nv50_ir.h
#include codegen/nv50_ir_build_util.h
@@ -73,7 +71,7 @@ private:
inline bool insnDominatedBy(const Instruction *, const Instruction *) const;
void findFirstUses(const Instruction *tex, const Instruction *def,
std::listTexUse,
- std::tr1::unordered_setconst Instruction *);
+ unordered_setconst Instruction *);
void findOverwritingDefs(const Instruction *tex, Instruction *insn,
const BasicBlock *term,
std::listTexUse);
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index 78bc97f..0cd21cf 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
@@ -25,7 +25,6 @@
#include stack
#include limits
-#include tr1/unordered_set
namespace nv50_ir {
@@ -1551,7 +1550,7 @@ SpillCodeInserter::run(const std::listValuePair lst)
// Keep track of which instructions to delete later. Deleting them
// inside the loop is unsafe since a single instruction may have
// multiple destinations that all need to be spilled (like OP_SPLIT).
- std::tr1::unordered_setInstruction * to_del;
+ unordered_setInstruction * to_del;
for (Value::DefIterator d = lval-defs.begin(); d != lval-defs.end();
++d) {
@@ -1593,7 +1592,7 @@ SpillCodeInserter::run(const std::listValuePair lst)
}
}
- for (std::tr1::unordered_setInstruction *::const_iterator
Mesa (master): nvc0/ir: detect i2f/i2i which operate on specific bytes/ words
Module: Mesa
Branch: master
Commit: 63cb85e567ad1025ee990b38f43c2f1ef811821b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=63cb85e567ad1025ee990b38f43c2f1ef811821b
Author: Ilia Mirkin imir...@alum.mit.edu
Date: Tue Aug 18 21:09:12 2015 -0400
nvc0/ir: detect i2f/i2i which operate on specific bytes/words
Some Unigine shaders have been observed to unpack bytes out of 32-bit
integers and convert them to floats. I2F/I2I can handle this sort of
thing directly. Detect the handleable situations.
This misses 16-bit word capabilities in nv50, but I haven't seen shaders
that would actually make use of that.
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
.../drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp |1 +
.../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp |2 +
.../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp |4 +
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 79 +++-
4 files changed, 82 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
index f06056f..8f15429 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
@@ -933,6 +933,7 @@ CodeEmitterGK110::emitCVT(const Instruction *i)
code[0] |= typeSizeofLog2(dType) 10;
code[0] |= typeSizeofLog2(i-sType) 12;
+ code[1] |= i-subOp 12;
if (isSignedIntType(dType))
code[0] |= 0x4000;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index ef5c87d..6e22788 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
@@ -818,6 +818,7 @@ CodeEmitterGM107::emitI2F()
emitField(0x31, 1, (insn-op == OP_ABS) || insn-src(0).mod.abs());
emitCC (0x2f);
emitField(0x2d, 1, (insn-op == OP_NEG) || insn-src(0).mod.neg());
+ emitField(0x29, 2, insn-subOp);
emitRND (0x27, rnd, -1);
emitField(0x0d, 1, isSignedType(insn-sType));
emitField(0x0a, 2, util_logbase2(typeSizeof(insn-sType)));
@@ -850,6 +851,7 @@ CodeEmitterGM107::emitI2I()
emitField(0x31, 1, (insn-op == OP_ABS) || insn-src(0).mod.abs());
emitCC (0x2f);
emitField(0x2d, 1, (insn-op == OP_NEG) || insn-src(0).mod.neg());
+ emitField(0x29, 2, insn-subOp);
emitField(0x0d, 1, isSignedType(insn-sType));
emitField(0x0c, 1, isSignedType(insn-dType));
emitField(0x0a, 2, util_logbase2(typeSizeof(insn-sType)));
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index 5703712..6bf5219 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -1020,6 +1020,10 @@ CodeEmitterNVC0::emitCVT(Instruction *i)
code[0] |= util_logbase2(typeSizeof(dType)) 20;
code[0] |= util_logbase2(typeSizeof(i-sType)) 23;
+ // for 8/16 source types, the byte/word is in subOp. word 1 is
+ // represented as 2.
+ code[1] |= i-subOp 0x17;
+
if (sat)
code[0] |= 0x20;
if (abs)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 83b884b..ef286c0 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1238,7 +1238,8 @@ private:
void handleRCP(Instruction *);
void handleSLCT(Instruction *);
void handleLOGOP(Instruction *);
- void handleCVT(Instruction *);
+ void handleCVT_NEG(Instruction *);
+ void handleCVT_EXTBF(Instruction *);
void handleSUCLAMP(Instruction *);
BuildUtil bld;
@@ -1489,12 +1490,12 @@ AlgebraicOpt::handleLOGOP(Instruction *logop)
// nv50:
// F2I(NEG(I2F(ABS(SET
void
-AlgebraicOpt::handleCVT(Instruction *cvt)
+AlgebraicOpt::handleCVT_NEG(Instruction *cvt)
{
+ Instruction *insn = cvt-getSrc(0)-getInsn();
if (cvt-sType != TYPE_F32 ||
cvt-dType != TYPE_S32 || cvt-src(0).mod != Modifier(0))
return;
- Instruction *insn = cvt-getSrc(0)-getInsn();
if (!insn || insn-op != OP_NEG || insn-dType != TYPE_F32)
return;
if (insn-src(0).mod != Modifier(0))
@@ -1524,6 +1525,74 @@ AlgebraicOpt::handleCVT(Instruction *cvt)
delete_Instruction(prog, cvt);
}
+// Some shaders extract packed bytes out of words and convert them to
+// e.g. float. The Fermi+ CVT instruction can extract those directly, as can
+// nv50 for word sizes.
+//
+// CVT(EXTBF(x, byte/word))
+// CVT(AND(bytemask, x))
+// CVT(AND(bytemask, SHR(x, 8/16/24)))
+void
+AlgebraicOpt::handleCVT_EXTBF(Instruction *cvt)
+{
+ Instruction *insn = cvt-getSrc(0)-getInsn();
+ ImmediateValue imm0, imm1;
+ Value *arg = NULL;
+ unsigned width, offset;
+ if
Mesa (master): nvc0/ir: detect AND/SHR pairs and convert into EXTBF
Module: Mesa
Branch: master
Commit: 51499bb5ff5626b893383545c494c7f808763404
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=51499bb5ff5626b893383545c494c7f808763404
Author: Ilia Mirkin imir...@alum.mit.edu
Date: Tue Aug 18 21:07:33 2015 -0400
nvc0/ir: detect AND/SHR pairs and convert into EXTBF
Some shaders appear to extract bits using shift/and combos. Detect
(some) of those and convert to EXTBF instead.
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 66 ++--
1 file changed, 46 insertions(+), 20 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index cea96dc..83b884b 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1023,27 +1023,53 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue
imm0, int s)
case OP_AND:
{
- CmpInstruction *cmp = i-getSrc(t)-getInsn()-asCmp();
- if (!cmp || cmp-op == OP_SLCT || cmp-getDef(0)-refCount() 1)
- return;
- if (!prog-getTarget()-isOpSupported(cmp-op, TYPE_F32))
- return;
- if (imm0.reg.data.f32 != 1.0)
- return;
- if (i-getSrc(t)-getInsn()-dType != TYPE_U32)
- return;
+ Instruction *src = i-getSrc(t)-getInsn();
+ ImmediateValue imm1;
+ if (imm0.reg.data.u32 == 0) {
+ i-op = OP_MOV;
+ i-setSrc(0, new_ImmediateValue(prog, 0u));
+ i-src(0).mod = Modifier(0);
+ i-setSrc(1, NULL);
+ } else if (imm0.reg.data.u32 == ~0U) {
+ i-op = i-src(t).mod.getOp();
+ if (t) {
+i-setSrc(0, i-getSrc(t));
+i-src(0).mod = i-src(t).mod;
+ }
+ i-setSrc(1, NULL);
+ } else if (src-asCmp()) {
+ CmpInstruction *cmp = src-asCmp();
+ if (!cmp || cmp-op == OP_SLCT || cmp-getDef(0)-refCount() 1)
+return;
+ if (!prog-getTarget()-isOpSupported(cmp-op, TYPE_F32))
+return;
+ if (imm0.reg.data.f32 != 1.0)
+return;
+ if (cmp-dType != TYPE_U32)
+return;
- i-getSrc(t)-getInsn()-dType = TYPE_F32;
- if (i-src(t).mod != Modifier(0)) {
- assert(i-src(t).mod == Modifier(NV50_IR_MOD_NOT));
- i-src(t).mod = Modifier(0);
- cmp-setCond = inverseCondCode(cmp-setCond);
- }
- i-op = OP_MOV;
- i-setSrc(s, NULL);
- if (t) {
- i-setSrc(0, i-getSrc(t));
- i-setSrc(t, NULL);
+ cmp-dType = TYPE_F32;
+ if (i-src(t).mod != Modifier(0)) {
+assert(i-src(t).mod == Modifier(NV50_IR_MOD_NOT));
+i-src(t).mod = Modifier(0);
+cmp-setCond = inverseCondCode(cmp-setCond);
+ }
+ i-op = OP_MOV;
+ i-setSrc(s, NULL);
+ if (t) {
+i-setSrc(0, i-getSrc(t));
+i-setSrc(t, NULL);
+ }
+ } else if (prog-getTarget()-isOpSupported(OP_EXTBF, TYPE_U32)
+ src-op == OP_SHR
+ src-src(1).getImmediate(imm1)
+ i-src(t).mod == Modifier(0)
+ util_is_power_of_two(imm0.reg.data.u32 + 1)) {
+ // low byte = offset, high byte = width
+ uint32_t ext = (util_last_bit(imm0.reg.data.u32) 8) |
imm1.reg.data.u32;
+ i-op = OP_EXTBF;
+ i-setSrc(0, src-getSrc(0));
+ i-setSrc(1, new_ImmediateValue(prog, ext));
}
}
break;
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