Mesa (master): i965/fs: Rework uniform handling
Module: Mesa
Branch: master
Commit: 259f7291de2387aa3ac5f856b39b7b934a1d8e7d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=259f7291de2387aa3ac5f856b39b7b934a1d8e7d
Author: Jason Ekstrand jason.ekstr...@intel.com
Date: Tue Aug 18 12:00:15 2015 -0700
i965/fs: Rework uniform handling
Previously, we treated the entire UNIFORM file as if it had two elements:
One for direct things and one for indirect. This is substantially
different from how the old visitor code handled it where each element was
effectively its own uniform. This commit makes the NIR path more like the
old ir_visitor path where each uniform is separate. This should allow us
to more easily make decisions about what to push.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_fs.h |3 ---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 30 --
src/mesa/drivers/dri/i965/brw_nir.c |7 +++
3 files changed, 11 insertions(+), 29 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 6d18929..6bca762 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -318,9 +318,6 @@ public:
/** Number of uniform variable components visited. */
unsigned uniforms;
- /** Total number of direct uniforms we can get from NIR */
- unsigned num_direct_uniforms;
-
/** Byte-offset for the next available spot in the scratch space buffer. */
unsigned last_scratch;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index ad51d80..a62dbb8 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -175,19 +175,9 @@ fs_visitor::nir_setup_outputs(nir_shader *shader)
void
fs_visitor::nir_setup_uniforms(nir_shader *shader)
{
- num_direct_uniforms = shader-num_direct_uniforms;
-
if (dispatch_width != 8)
return;
- /* We split the uniform register file in half. The first half is
-* entirely direct uniforms. The second half is indirect.
-*/
- if (num_direct_uniforms 0)
- param_size[0] = num_direct_uniforms;
- if (shader-num_uniforms num_direct_uniforms)
- param_size[num_direct_uniforms] = shader-num_uniforms -
num_direct_uniforms;
-
uniforms = shader-num_uniforms;
if (shader_prog) {
@@ -200,15 +190,19 @@ fs_visitor::nir_setup_uniforms(nir_shader *shader)
nir_setup_builtin_uniform(var);
else
nir_setup_uniform(var);
+
+ param_size[var-data.driver_location] = type_size_scalar(var-type);
}
} else {
- /* prog_to_nir doesn't create uniform variables; set param up directly.
*/
+ /* prog_to_nir only creates a single giant uniform variable so we can
+ * just set param up directly. */
for (unsigned p = 0; p prog-Parameters-NumParameters; p++) {
for (unsigned int i = 0; i 4; i++) {
stage_prog_data-param[4 * p + i] =
prog-Parameters-ParameterValues[p][i];
}
}
+ param_size[0] = prog-Parameters-NumParameters * 4;
}
}
@@ -1504,21 +1498,13 @@ fs_visitor::nir_emit_intrinsic(const fs_builder bld,
nir_intrinsic_instr *instr
has_indirect = true;
/* fallthrough */
case nir_intrinsic_load_uniform: {
- unsigned index = instr-const_index[0] + instr-const_index[1];
-
- fs_reg uniform_reg;
- if (index num_direct_uniforms) {
- uniform_reg = fs_reg(UNIFORM, 0);
- } else {
- uniform_reg = fs_reg(UNIFORM, num_direct_uniforms);
- index -= num_direct_uniforms;
- }
+ fs_reg uniform_reg(UNIFORM, instr-const_index[0]);
+ uniform_reg.reg_offset = instr-const_index[1];
for (unsigned j = 0; j instr-num_components; j++) {
- fs_reg src = offset(retype(uniform_reg, dest.type), bld, index);
+ fs_reg src = offset(retype(uniform_reg, dest.type), bld, j);
if (has_indirect)
src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr-src[0]));
- index++;
bld.MOV(dest, src);
dest = offset(dest, bld, 1);
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c
b/src/mesa/drivers/dri/i965/brw_nir.c
index 3d04363..dfac44f 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -111,10 +111,9 @@ brw_create_nir(struct brw_context *brw,
nir_optimize(nir, is_scalar);
if (is_scalar) {
- nir_assign_var_locations_direct_first(nir, nir-uniforms,
-nir-num_direct_uniforms,
-nir-num_uniforms,
-type_size_scalar);
+ nir_assign_var_locations(nir-uniforms,
+ nir-num_uniforms,
+ type_size_scalar);
nir_assign_var_locations(nir-inputs, nir-num_inputs,
Mesa (master): nir: Pass a type_size() function pointer into nir_lower_io( ).
Module: Mesa
Branch: master
Commit: 6c33d6bbf9b54784e4498a81c73b712dca5dd737
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c33d6bbf9b54784e4498a81c73b712dca5dd737
Author: Kenneth Graunke kenn...@whitecape.org
Date: Wed Aug 12 14:29:25 2015 -0700
nir: Pass a type_size() function pointer into nir_lower_io().
Previously, there were four type_size() functions in play - the i965
compiler backend defined scalar and vec4 type_size() functions, and
nir_lower_io contained its own similar functions.
In fact, the i965 driver used nir_lower_io() and then looped over the
components using its own type_size - meaning both were in play. The
two are /basically/ the same, but not exactly in obscure cases like
subroutines and images.
This patch removes nir_lower_io's functions, and instead makes the
driver supply a function pointer. This gives the driver ultimate
flexibility in deciding how it wants to count things, reduces code
duplication, and improves consistency.
v2 (Jason Ekstrand):
- One side-effect of passing in a function pointer is that nir_lower_io is
now aware of and properly allocates space for image uniforms, allowing
us to drop hacks in the backend
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com
v2 Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/glsl/nir/nir.h |8 +-
src/glsl/nir/nir_lower_io.c | 118 --
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 13 +---
src/mesa/drivers/dri/i965/brw_nir.c | 16 ++--
4 files changed, 31 insertions(+), 124 deletions(-)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index d19a190..e357f93 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -1632,15 +1632,15 @@ void nir_lower_locals_to_regs(nir_shader *shader);
void nir_assign_var_locations(struct exec_list *var_list,
unsigned *size,
- bool is_scalar);
+ int (*type_size)(const struct glsl_type *));
void nir_assign_var_locations_direct_first(nir_shader *shader,
struct exec_list *var_list,
unsigned *direct_size,
unsigned *size,
- bool is_scalar);
-
-void nir_lower_io(nir_shader *shader, bool is_scalar);
+ int (*type_size)(const struct
glsl_type *));
+void nir_lower_io(nir_shader *shader,
+ int (*type_size)(const struct glsl_type *));
void nir_lower_vars_to_ssa(nir_shader *shader);
void nir_remove_dead_variables(nir_shader *shader);
diff --git a/src/glsl/nir/nir_lower_io.c b/src/glsl/nir/nir_lower_io.c
index d33aefe..15a4edc 100644
--- a/src/glsl/nir/nir_lower_io.c
+++ b/src/glsl/nir/nir_lower_io.c
@@ -37,99 +37,12 @@
struct lower_io_state {
nir_builder builder;
void *mem_ctx;
- bool is_scalar;
+ int (*type_size)(const struct glsl_type *type);
};
-static int
-type_size_vec4(const struct glsl_type *type)
-{
- unsigned int i;
- int size;
-
- switch (glsl_get_base_type(type)) {
- case GLSL_TYPE_UINT:
- case GLSL_TYPE_INT:
- case GLSL_TYPE_FLOAT:
- case GLSL_TYPE_BOOL:
- if (glsl_type_is_matrix(type)) {
- return glsl_get_matrix_columns(type);
- } else {
- return 1;
- }
- case GLSL_TYPE_ARRAY:
- return type_size_vec4(glsl_get_array_element(type)) *
glsl_get_length(type);
- case GLSL_TYPE_STRUCT:
- size = 0;
- for (i = 0; i glsl_get_length(type); i++) {
- size += type_size_vec4(glsl_get_struct_field(type, i));
- }
- return size;
- case GLSL_TYPE_SUBROUTINE:
- return 1;
- case GLSL_TYPE_SAMPLER:
- return 0;
- case GLSL_TYPE_ATOMIC_UINT:
- return 0;
- case GLSL_TYPE_IMAGE:
- case GLSL_TYPE_VOID:
- case GLSL_TYPE_DOUBLE:
- case GLSL_TYPE_ERROR:
- case GLSL_TYPE_INTERFACE:
- unreachable(not reached);
- }
-
- return 0;
-}
-
-static unsigned
-type_size_scalar(const struct glsl_type *type)
-{
- unsigned int size, i;
-
- switch (glsl_get_base_type(type)) {
- case GLSL_TYPE_UINT:
- case GLSL_TYPE_INT:
- case GLSL_TYPE_FLOAT:
- case GLSL_TYPE_BOOL:
- return glsl_get_components(type);
- case GLSL_TYPE_ARRAY:
- return type_size_scalar(glsl_get_array_element(type)) *
glsl_get_length(type);
- case GLSL_TYPE_STRUCT:
- size = 0;
- for (i = 0; i glsl_get_length(type); i++) {
- size += type_size_scalar(glsl_get_struct_field(type, i));
- }
- return size;
- case GLSL_TYPE_SUBROUTINE:
- return 1;
- case GLSL_TYPE_SAMPLER:
- return 0;
- case GLSL_TYPE_ATOMIC_UINT:
- return 0;
- case GLSL_TYPE_INTERFACE:
- return 0;
- case GLSL_TYPE_IMAGE:
- return 0;
- case GLSL_TYPE_VOID:
- case GLSL_TYPE_ERROR:
- case
Mesa (master): prog_to_nir: Don't allocate nir_variable with type vec4[0] for uniforms.
Module: Mesa
Branch: master
Commit: a23f82053d18c2f7d78e28551368437ded4c1a03
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a23f82053d18c2f7d78e28551368437ded4c1a03
Author: Kenneth Graunke kenn...@whitecape.org
Date: Mon Aug 24 16:39:24 2015 -0700
prog_to_nir: Don't allocate nir_variable with type vec4[0] for uniforms.
If there are no parameters, we don't need to create a nir_variable to
hold them...and allocating an array of length 0 is pretty bogus.
Should avoid i965 backend assertions in future patches Jason and I are
working on.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com
---
src/mesa/program/prog_to_nir.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/src/mesa/program/prog_to_nir.c b/src/mesa/program/prog_to_nir.c
index d54f934..9d4af12 100644
--- a/src/mesa/program/prog_to_nir.c
+++ b/src/mesa/program/prog_to_nir.c
@@ -166,6 +166,8 @@ ptn_get_src(struct ptn_compile *c, const struct
prog_src_register *prog_src)
}
/* FALLTHROUGH */
case PROGRAM_STATE_VAR: {
+ assert(c-parameters != NULL);
+
nir_intrinsic_instr *load =
nir_intrinsic_instr_create(b-shader, nir_intrinsic_load_var);
nir_ssa_dest_init(load-instr, load-dest, 4, NULL);
@@ -1088,13 +1090,15 @@ prog_to_nir(const struct gl_program *prog,
goto fail;
c-prog = prog;
- c-parameters = rzalloc(s, nir_variable);
- c-parameters-type = glsl_array_type(glsl_vec4_type(),
-prog-Parameters-NumParameters);
- c-parameters-name = parameters;
- c-parameters-data.read_only = true;
- c-parameters-data.mode = nir_var_uniform;
- exec_list_push_tail(s-uniforms, c-parameters-node);
+ if (prog-Parameters-NumParameters 0) {
+ c-parameters = rzalloc(s, nir_variable);
+ c-parameters-type =
+ glsl_array_type(glsl_vec4_type(), prog-Parameters-NumParameters);
+ c-parameters-name = parameters;
+ c-parameters-data.read_only = true;
+ c-parameters-data.mode = nir_var_uniform;
+ exec_list_push_tail(s-uniforms, c-parameters-node);
+ }
nir_function *func = nir_function_create(s, main);
nir_function_overload *overload = nir_function_overload_create(func);
___
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Mesa (master): i965: Rename setup_vector_uniform_values to setup_vec4_uniform_value
Module: Mesa
Branch: master
Commit: 8d8b8f58540abbdb8a006a38830a08346a0edf34
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d8b8f58540abbdb8a006a38830a08346a0edf34
Author: Jason Ekstrand jason.ekstr...@intel.com
Date: Wed Aug 19 09:56:57 2015 -0700
i965: Rename setup_vector_uniform_values to setup_vec4_uniform_value
The new name more accurately represents what it does: Set up a single vec4
uniform value.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_fs.cpp |3 ++-
src/mesa/drivers/dri/i965/brw_fs.h |4 ++--
src/mesa/drivers/dri/i965/brw_shader.cpp | 12 ++--
src/mesa/drivers/dri/i965/brw_shader.h |4 ++--
src/mesa/drivers/dri/i965/brw_vec4.h |4 ++--
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |8
6 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 82cb499..47cc167 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -943,7 +943,8 @@ fs_visitor::import_uniforms(fs_visitor *v)
}
void
-fs_visitor::setup_vector_uniform_values(const gl_constant_value *values,
unsigned n)
+fs_visitor::setup_vec4_uniform_value(const gl_constant_value *values,
+ unsigned n)
{
static const gl_constant_value zero = { 0 };
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 975183e..1a56c2a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -291,8 +291,8 @@ public:
struct brw_reg interp_reg(int location, int channel);
- virtual void setup_vector_uniform_values(const gl_constant_value *values,
-unsigned n);
+ virtual void setup_vec4_uniform_value(const gl_constant_value *values,
+ unsigned n);
int implied_mrf_writes(fs_inst *inst);
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 14f647d..ddd70a3 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -1431,17 +1431,17 @@ backend_shader::setup_image_uniform_values(const
gl_uniform_storage *storage)
/* Upload the brw_image_param structure. The order is expected to match
* the BRW_IMAGE_PARAM_*_OFFSET defines.
*/
- setup_vector_uniform_values(
+ setup_vec4_uniform_value(
(const gl_constant_value *)param-surface_idx, 1);
- setup_vector_uniform_values(
+ setup_vec4_uniform_value(
(const gl_constant_value *)param-offset, 2);
- setup_vector_uniform_values(
+ setup_vec4_uniform_value(
(const gl_constant_value *)param-size, 3);
- setup_vector_uniform_values(
+ setup_vec4_uniform_value(
(const gl_constant_value *)param-stride, 4);
- setup_vector_uniform_values(
+ setup_vec4_uniform_value(
(const gl_constant_value *)param-tiling, 3);
- setup_vector_uniform_values(
+ setup_vec4_uniform_value(
(const gl_constant_value *)param-swizzling, 2);
brw_mark_surface_used(
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h
b/src/mesa/drivers/dri/i965/brw_shader.h
index 2cc97f2..933869a 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -270,8 +270,8 @@ public:
virtual void invalidate_live_intervals() = 0;
- virtual void setup_vector_uniform_values(const gl_constant_value *values,
-unsigned n) = 0;
+ virtual void setup_vec4_uniform_value(const gl_constant_value *values,
+ unsigned n) = 0;
void setup_image_uniform_values(const gl_uniform_storage *storage);
};
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 341c516..f8f31fc 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -177,8 +177,8 @@ public:
void fail(const char *msg, ...);
void setup_uniform_clipplane_values(gl_clip_plane *clip_planes);
- virtual void setup_vector_uniform_values(const gl_constant_value *values,
-unsigned n);
+ virtual void setup_vec4_uniform_value(const gl_constant_value *values,
+ unsigned n);
void setup_uniform_values(ir_variable *ir);
void setup_builtin_uniform_values(ir_variable *ir);
int setup_uniforms(int payload_reg);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 9062bcc..64d4abe 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -696,8 +696,8 @@ dst_reg::dst_reg(class vec4_visitor
Mesa (master): nir/lower_io: Remove assign_var_locations_direct_first
Module: Mesa
Branch: master
Commit: c999a58f50578a826a66e2d95334245b6c4c9559
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c999a58f50578a826a66e2d95334245b6c4c9559
Author: Jason Ekstrand jason.ekstr...@intel.com
Date: Tue Aug 18 14:45:35 2015 -0700
nir/lower_io: Remove assign_var_locations_direct_first
This is no longer used so we might as well get rid of it.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/glsl/nir/nir.h |8 -
src/glsl/nir/nir_lower_io.c | 74 ---
2 files changed, 82 deletions(-)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index e357f93..011a80a 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -1474,9 +1474,6 @@ typedef struct nir_shader {
* access plus one
*/
unsigned num_inputs, num_uniforms, num_outputs;
-
- /** the number of uniforms that are only accessed directly */
- unsigned num_direct_uniforms;
} nir_shader;
#define nir_foreach_overload(shader, overload)\
@@ -1633,11 +1630,6 @@ void nir_lower_locals_to_regs(nir_shader *shader);
void nir_assign_var_locations(struct exec_list *var_list,
unsigned *size,
int (*type_size)(const struct glsl_type *));
-void nir_assign_var_locations_direct_first(nir_shader *shader,
- struct exec_list *var_list,
- unsigned *direct_size,
- unsigned *size,
- int (*type_size)(const struct
glsl_type *));
void nir_lower_io(nir_shader *shader,
int (*type_size)(const struct glsl_type *));
diff --git a/src/glsl/nir/nir_lower_io.c b/src/glsl/nir/nir_lower_io.c
index 70645b6..c9697e7 100644
--- a/src/glsl/nir/nir_lower_io.c
+++ b/src/glsl/nir/nir_lower_io.c
@@ -76,80 +76,6 @@ deref_has_indirect(nir_deref_var *deref)
return false;
}
-static bool
-mark_indirect_uses_block(nir_block *block, void *void_state)
-{
- struct set *indirect_set = void_state;
-
- nir_foreach_instr(block, instr) {
- if (instr-type != nir_instr_type_intrinsic)
- continue;
-
- nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
-
- for (unsigned i = 0;
- i nir_intrinsic_infos[intrin-intrinsic].num_variables; i++) {
- if (deref_has_indirect(intrin-variables[i]))
-_mesa_set_add(indirect_set, intrin-variables[i]-var);
- }
- }
-
- return true;
-}
-
-/* Identical to nir_assign_var_locations_packed except that it assigns
- * locations to the variables that are used 100% directly first and then
- * assigns locations to variables that are used indirectly.
- */
-void
-nir_assign_var_locations_direct_first(nir_shader *shader,
- struct exec_list *var_list,
- unsigned *direct_size,
- unsigned *size,
- int (*type_size)(const struct glsl_type
*))
-{
- struct set *indirect_set = _mesa_set_create(NULL, _mesa_hash_pointer,
- _mesa_key_pointer_equal);
-
- nir_foreach_overload(shader, overload) {
- if (overload-impl)
- nir_foreach_block(overload-impl, mark_indirect_uses_block,
- indirect_set);
- }
-
- unsigned location = 0;
-
- foreach_list_typed(nir_variable, var, node, var_list) {
- if ((var-data.mode == nir_var_uniform || var-data.mode ==
nir_var_shader_storage)
- var-interface_type != NULL)
- continue;
-
- if (_mesa_set_search(indirect_set, var))
- continue;
-
- var-data.driver_location = location;
- location += type_size(var-type);
- }
-
- *direct_size = location;
-
- foreach_list_typed(nir_variable, var, node, var_list) {
- if ((var-data.mode == nir_var_uniform || var-data.mode ==
nir_var_shader_storage)
- var-interface_type != NULL)
- continue;
-
- if (!_mesa_set_search(indirect_set, var))
- continue;
-
- var-data.driver_location = location;
- location += type_size(var-type);
- }
-
- *size = location;
-
- _mesa_set_destroy(indirect_set, NULL);
-}
-
static unsigned
get_io_offset(nir_deref_var *deref, nir_instr *instr, nir_src *indirect,
struct lower_io_state *state)
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Mesa (master): nir/intrinsics: Add a second const index to load_uniform
Module: Mesa
Branch: master
Commit: 0db8e87b4a16b123f7c0b44d54f23b535a136ee6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0db8e87b4a16b123f7c0b44d54f23b535a136ee6
Author: Jason Ekstrand jason.ekstr...@intel.com
Date: Tue Aug 18 11:18:55 2015 -0700
nir/intrinsics: Add a second const index to load_uniform
In the i965 backend, we want to be able to pull apart the uniforms and
push some of them into the shader through a different path. In order to do
this effectively, we need to know which variable is actually being referred
to by a given uniform load. Previously, it was completely flattened by
nir_lower_io which made things difficult. This adds more information to
the intrinsic to make this easier for us.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/glsl/nir/nir_intrinsics.h | 28 +---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp |2 +-
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp |2 +-
3 files changed, 19 insertions(+), 13 deletions(-)
diff --git a/src/glsl/nir/nir_intrinsics.h b/src/glsl/nir/nir_intrinsics.h
index 6c7a61a..ed309b6 100644
--- a/src/glsl/nir/nir_intrinsics.h
+++ b/src/glsl/nir/nir_intrinsics.h
@@ -141,11 +141,17 @@ SYSTEM_VALUE(sample_mask_in, 1)
SYSTEM_VALUE(invocation_id, 1)
/*
- * The first and only index is the base address to load from. Indirect
- * loads have an additional register input, which is added to the constant
- * address to compute the final address to load from. For UBO's (and
- * SSBO's), the first source is the (possibly constant) UBO buffer index
- * and the indirect (if it exists) is the second source.
+ * The format of the indices depends on the type of the load. For uniforms,
+ * the first index is the base address and the second index is an offset that
+ * should be added to the base address. (This way you can determine in the
+ * back-end which variable is being accessed even in an array.) For inputs,
+ * the one and only index corresponds to the attribute slot. UBO loads also
+ * have a single index which is the base address to load from.
+ *
+ * UBO loads have a (possibly constant) source which is the UBO buffer index.
+ * For each type of load, the _indirect variant has one additional source
+ * (the second in the case of UBO's) that is the is an indirect to be added to
+ * the constant address or base offset to compute the final offset.
*
* For vector backends, the address is in terms of one vec4, and so each array
* element is +4 scalar components from the previous array element. For scalar
@@ -153,14 +159,14 @@ SYSTEM_VALUE(invocation_id, 1)
* elements begin immediately after the previous array element.
*/
-#define LOAD(name, extra_srcs, flags) \
- INTRINSIC(load_##name, extra_srcs, ARR(1), true, 0, 0, 1, flags) \
+#define LOAD(name, extra_srcs, indices, flags) \
+ INTRINSIC(load_##name, extra_srcs, ARR(1), true, 0, 0, indices, flags) \
INTRINSIC(load_##name##_indirect, extra_srcs + 1, ARR(1, 1), \
- true, 0, 0, 1, flags)
+ true, 0, 0, indices, flags)
-LOAD(uniform, 0, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
-LOAD(ubo, 1, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
-LOAD(input, 0, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
+LOAD(uniform, 0, 2, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
+LOAD(ubo, 1, 1, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
+LOAD(input, 0, 1, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
/* LOAD(ssbo, 1, 0) */
/*
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index b32f8a7..ad51d80 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -1504,7 +1504,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder bld,
nir_intrinsic_instr *instr
has_indirect = true;
/* fallthrough */
case nir_intrinsic_load_uniform: {
- unsigned index = instr-const_index[0];
+ unsigned index = instr-const_index[0] + instr-const_index[1];
fs_reg uniform_reg;
if (index num_direct_uniforms) {
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 4f689df..9e52229 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -570,7 +570,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
has_indirect = true;
/* fallthrough */
case nir_intrinsic_load_uniform: {
- int uniform = instr-const_index[0];
+ int uniform = instr-const_index[0] + instr-const_index[1];
dest = get_nir_dest(instr-dest);
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Mesa (master): i965: Make setup_vec4_uniform_value and _image_uniform_values take an offset
Module: Mesa
Branch: master
Commit: c56899f41a904762225267cb9c543a0abd901ad5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c56899f41a904762225267cb9c543a0abd901ad5
Author: Jason Ekstrand jason.ekstr...@intel.com
Date: Wed Aug 19 10:32:32 2015 -0700
i965: Make setup_vec4_uniform_value and _image_uniform_values take an offset
This way they don't implicitly increment the uniforms variable and don't
have to be called in-sequence during uniform setup.
Reviewed-by: Francisco Jerez curroje...@riseup.net
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_fs.cpp |7 ---
src/mesa/drivers/dri/i965/brw_fs.h |3 ++-
src/mesa/drivers/dri/i965/brw_fs_nir.cpp |7 +--
src/mesa/drivers/dri/i965/brw_shader.cpp | 16 +---
src/mesa/drivers/dri/i965/brw_shader.h |6 --
src/mesa/drivers/dri/i965/brw_vec4.h |3 ++-
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 18 --
7 files changed, 38 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 47cc167..6ee9f3a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -943,16 +943,17 @@ fs_visitor::import_uniforms(fs_visitor *v)
}
void
-fs_visitor::setup_vec4_uniform_value(const gl_constant_value *values,
+fs_visitor::setup_vec4_uniform_value(unsigned param_offset,
+ const gl_constant_value *values,
unsigned n)
{
static const gl_constant_value zero = { 0 };
for (unsigned i = 0; i n; ++i)
- stage_prog_data-param[uniforms++] = values[i];
+ stage_prog_data-param[param_offset + i] = values[i];
for (unsigned i = n; i 4; ++i)
- stage_prog_data-param[uniforms++] = zero;
+ stage_prog_data-param[param_offset + i] = zero;
}
fs_reg *
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 1a56c2a..9484e63 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -291,7 +291,8 @@ public:
struct brw_reg interp_reg(int location, int channel);
- virtual void setup_vec4_uniform_value(const gl_constant_value *values,
+ virtual void setup_vec4_uniform_value(unsigned param_offset,
+ const gl_constant_value *values,
unsigned n);
int implied_mrf_writes(fs_inst *inst);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index c726c72..5f26931 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -244,10 +244,13 @@ fs_visitor::nir_setup_uniform(nir_variable *var)
* space for them here at the end of the parameter array.
*/
var-data.driver_location = uniforms;
- param_size[uniforms] =
+ unsigned size =
BRW_IMAGE_PARAM_SIZE * MAX2(storage-array_elements, 1);
- setup_image_uniform_values(storage);
+ setup_image_uniform_values(uniforms, storage);
+
+ param_size[uniforms] = size;
+ uniforms += size;
} else {
unsigned slots = storage-type-component_slots();
if (storage-array_elements)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index ddd70a3..445764d 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -1420,7 +1420,8 @@
backend_shader::assign_common_binding_table_offsets(uint32_t next_binding_table_
}
void
-backend_shader::setup_image_uniform_values(const gl_uniform_storage *storage)
+backend_shader::setup_image_uniform_values(unsigned param_offset,
+ const gl_uniform_storage *storage)
{
const unsigned stage = _mesa_program_enum_to_shader_stage(prog-Target);
@@ -1431,18 +1432,19 @@ backend_shader::setup_image_uniform_values(const
gl_uniform_storage *storage)
/* Upload the brw_image_param structure. The order is expected to match
* the BRW_IMAGE_PARAM_*_OFFSET defines.
*/
- setup_vec4_uniform_value(
+ setup_vec4_uniform_value(param_offset +
BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
(const gl_constant_value *)param-surface_idx, 1);
- setup_vec4_uniform_value(
+ setup_vec4_uniform_value(param_offset + BRW_IMAGE_PARAM_OFFSET_OFFSET,
(const gl_constant_value *)param-offset, 2);
- setup_vec4_uniform_value(
+ setup_vec4_uniform_value(param_offset + BRW_IMAGE_PARAM_SIZE_OFFSET,
(const gl_constant_value *)param-size, 3);
- setup_vec4_uniform_value(
+ setup_vec4_uniform_value(param_offset + BRW_IMAGE_PARAM_STRIDE_OFFSET,
(const gl_constant_value *)param-stride, 4);
-
Mesa (master): i965: Move type_size() methods out of visitor classes.
Module: Mesa
Branch: master
Commit: 640c472fd075814972b1276c5b0ed3a769aacda5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=640c472fd075814972b1276c5b0ed3a769aacda5
Author: Kenneth Graunke kenn...@whitecape.org
Date: Wed Aug 12 14:19:17 2015 -0700
i965: Move type_size() methods out of visitor classes.
I want to use C function pointers to these, and they don't use anything
in the visitor classes anyway.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 10 -
src/mesa/drivers/dri/i965/brw_fs.h |1 -
src/mesa/drivers/dri/i965/brw_fs_nir.cpp |2 +-
src/mesa/drivers/dri/i965/brw_shader.h |3 +++
src/mesa/drivers/dri/i965/brw_vec4.h |1 -
src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp |4 ++--
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp |8
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 26
8 files changed, 28 insertions(+), 27 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 6ee9f3a..68bcbd0 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -455,8 +455,8 @@ fs_reg::component_size(unsigned width) const
return MAX2(width * stride, 1) * type_sz(type);
}
-int
-fs_visitor::type_size(const struct glsl_type *type)
+extern C int
+type_size_scalar(const struct glsl_type *type)
{
unsigned int size, i;
@@ -467,11 +467,11 @@ fs_visitor::type_size(const struct glsl_type *type)
case GLSL_TYPE_BOOL:
return type-components();
case GLSL_TYPE_ARRAY:
- return type_size(type-fields.array) * type-length;
+ return type_size_scalar(type-fields.array) * type-length;
case GLSL_TYPE_STRUCT:
size = 0;
for (i = 0; i type-length; i++) {
-size += type_size(type-fields.structure[i].type);
+size += type_size_scalar(type-fields.structure[i].type);
}
return size;
case GLSL_TYPE_SAMPLER:
@@ -906,7 +906,7 @@ fs_reg
fs_visitor::vgrf(const glsl_type *const type)
{
int reg_width = dispatch_width / 8;
- return fs_reg(GRF, alloc.allocate(type_size(type) * reg_width),
+ return fs_reg(GRF, alloc.allocate(type_size_scalar(type) * reg_width),
brw_type_for_base_type(type));
}
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 9484e63..6d18929 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -112,7 +112,6 @@ public:
void swizzle_result(ir_texture_opcode op, int dest_components,
fs_reg orig_val, uint32_t sampler);
- int type_size(const struct glsl_type *type);
fs_inst *get_instruction_generating_reg(fs_inst *start,
fs_inst *end,
const fs_reg reg);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 5f26931..6dda299 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -131,7 +131,7 @@ fs_visitor::nir_setup_outputs(nir_shader *shader)
switch (stage) {
case MESA_SHADER_VERTEX:
- for (int i = 0; i ALIGN(type_size(var-type), 4) / 4; i++) {
+ for (int i = 0; i ALIGN(type_size_scalar(var-type), 4) / 4; i++) {
int output = var-data.location + i;
this-outputs[output] = offset(reg, bld, 4 * i);
this-output_components[output] = vector_elements;
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h
b/src/mesa/drivers/dri/i965/brw_shader.h
index d449ffa..f4d 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -309,6 +309,9 @@ bool brw_cs_precompile(struct gl_context *ctx,
struct gl_shader_program *shader_prog,
struct gl_program *prog);
+int type_size_scalar(const struct glsl_type *type);
+int type_size_vec4(const struct glsl_type *type);
+
#ifdef __cplusplus
}
#endif
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index b21f8dc..59a8397 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -410,7 +410,6 @@ public:
void visit_atomic_counter_intrinsic(ir_call *ir);
- int type_size(const struct glsl_type *type);
bool is_high_sampler(src_reg sampler);
virtual void emit_nir_code();
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp
index d85fb6f..8a8dd57 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp
@@ -44,7 +44,7 @@ vec4_gs_visitor::nir_setup_inputs(nir_shader *shader)
*/
assert(var-type-length
Mesa (master): nir/lower_io: Separate driver_location and base offset for uniforms
Module: Mesa
Branch: master
Commit: ce5e9139aa1eee78e9154ded84b724b0cecbece7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ce5e9139aa1eee78e9154ded84b724b0cecbece7
Author: Jason Ekstrand jason.ekstr...@intel.com
Date: Tue Aug 18 11:20:40 2015 -0700
nir/lower_io: Separate driver_location and base offset for uniforms
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/glsl/nir/nir_lower_io.c |9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/glsl/nir/nir_lower_io.c b/src/glsl/nir/nir_lower_io.c
index 15a4edc..70645b6 100644
--- a/src/glsl/nir/nir_lower_io.c
+++ b/src/glsl/nir/nir_lower_io.c
@@ -244,9 +244,14 @@ nir_lower_io_block(nir_block *block, void *void_state)
nir_src indirect;
unsigned offset = get_io_offset(intrin-variables[0],
intrin-instr, indirect, state);
- offset += intrin-variables[0]-var-data.driver_location;
- load-const_index[0] = offset;
+ unsigned location = intrin-variables[0]-var-data.driver_location;
+ if (mode == nir_var_uniform) {
+load-const_index[0] = location;
+load-const_index[1] = offset;
+ } else {
+load-const_index[0] = location + offset;
+ }
if (has_indirect)
load-src[0] = indirect;
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Mesa (master): i965/fs: Combine assign_constant_locations and move_uniform_array_access_to_pull_constants
Module: Mesa
Branch: master
Commit: dfacae3a56463e2df3a67e245f868e9f2be64dcd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dfacae3a56463e2df3a67e245f868e9f2be64dcd
Author: Jason Ekstrand jason.ekstr...@intel.com
Date: Tue Aug 18 17:04:53 2015 -0700
i965/fs: Combine assign_constant_locations and
move_uniform_array_access_to_pull_constants
The comment above move_uniform_array_access_to_pull_constants was
completely bogus because it has nothing to do with lowering instructions.
Instead, it's assiging locations of pull constants.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 40 ++
src/mesa/drivers/dri/i965/brw_fs.h |1 -
2 files changed, 11 insertions(+), 30 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 68bcbd0..8f2056ee 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1766,21 +1766,21 @@ fs_visitor::compact_virtual_grfs()
return progress;
}
-/*
- * Implements array access of uniforms by inserting a
- * PULL_CONSTANT_LOAD instruction.
+/**
+ * Assign UNIFORM file registers to either push constants or pull constants.
*
- * Unlike temporary GRF array access (where we don't support it due to
- * the difficulty of doing relative addressing on instruction
- * destinations), we could potentially do array access of uniforms
- * that were loaded in GRF space as push constants. In real-world
- * usage we've seen, though, the arrays being used are always larger
- * than we could load as push constants, so just always move all
- * uniform array access out to a pull constant buffer.
+ * We allow a fragment shader to have more than the specified minimum
+ * maximum number of fragment shader uniform components (64). If
+ * there are too many of these, they'd fill up all of register space.
+ * So, this will push some of them out to the pull constant buffer and
+ * update the program to load them. We also use pull constants for all
+ * indirect constant loads because we don't support indirect accesses in
+ * registers yet.
*/
void
-fs_visitor::move_uniform_array_access_to_pull_constants()
+fs_visitor::assign_constant_locations()
{
+ /* Only the first compile (SIMD8 mode) gets to decide on locations. */
if (dispatch_width != 8)
return;
@@ -1817,23 +1817,6 @@ fs_visitor::move_uniform_array_access_to_pull_constants()
}
}
}
-}
-
-/**
- * Assign UNIFORM file registers to either push constants or pull constants.
- *
- * We allow a fragment shader to have more than the specified minimum
- * maximum number of fragment shader uniform components (64). If
- * there are too many of these, they'd fill up all of register space.
- * So, this will push some of them out to the pull constant buffer and
- * update the program to load them.
- */
-void
-fs_visitor::assign_constant_locations()
-{
- /* Only the first compile (SIMD8 mode) gets to decide on locations. */
- if (dispatch_width != 8)
- return;
/* Find which UNIFORM registers are still in use. */
bool is_live[uniforms];
@@ -4805,7 +4788,6 @@ fs_visitor::optimize()
split_virtual_grfs();
- move_uniform_array_access_to_pull_constants();
assign_constant_locations();
demote_pull_constants();
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 6bca762..31f39fe 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -146,7 +146,6 @@ public:
void spill_reg(int spill_reg);
void split_virtual_grfs();
bool compact_virtual_grfs();
- void move_uniform_array_access_to_pull_constants();
void assign_constant_locations();
void demote_pull_constants();
void invalidate_live_intervals();
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Mesa (master): i965/vec4_nir: Get rid of the uniform_driver_location tracking
Module: Mesa
Branch: master
Commit: cfa056c6a5eadf87f92a71346c02a080e302
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cfa056c6a5eadf87f92a71346c02a080e302
Author: Jason Ekstrand jason.ekstr...@intel.com
Date: Tue Aug 18 11:42:02 2015 -0700
i965/vec4_nir: Get rid of the uniform_driver_location tracking
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_vec4.h |1 -
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 22 +++---
2 files changed, 3 insertions(+), 20 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 59a8397..673a29e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -447,7 +447,6 @@ public:
dst_reg *nir_locals;
dst_reg *nir_ssa_values;
src_reg *nir_inputs;
- unsigned *nir_uniform_driver_location;
dst_reg *nir_system_values;
protected:
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 9e52229..59e440a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -132,9 +132,6 @@ vec4_visitor::nir_setup_uniforms(nir_shader *shader)
{
uniforms = 0;
- nir_uniform_driver_location =
- rzalloc_array(mem_ctx, unsigned, this-uniform_array_size);
-
if (shader_prog) {
foreach_list_typed(nir_variable, var, node, shader-uniforms) {
/* UBO's, atomics and samplers don't take up space in the
@@ -182,7 +179,6 @@ vec4_visitor::nir_setup_uniforms(nir_shader *shader)
stage_prog_data-param[uniforms * 4 + i] = zero;
}
- nir_uniform_driver_location[uniforms] = var-data.driver_location;
uniforms++;
}
}
@@ -230,7 +226,6 @@ vec4_visitor::nir_setup_uniform(nir_variable *var)
stage_prog_data-param[uniforms * 4 + i] = zero;
}
- nir_uniform_driver_location[uniforms] = var-data.driver_location;
uniforms++;
}
}
@@ -263,7 +258,6 @@ vec4_visitor::nir_setup_builtin_uniform(nir_variable *var)
(var-type-is_scalar() || var-type-is_vector() ||
var-type-is_matrix() ? var-type-vector_elements : 4);
- nir_uniform_driver_location[uniforms] = var-data.driver_location;
uniforms++;
}
}
@@ -570,24 +564,14 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr)
has_indirect = true;
/* fallthrough */
case nir_intrinsic_load_uniform: {
- int uniform = instr-const_index[0] + instr-const_index[1];
-
dest = get_nir_dest(instr-dest);
- if (has_indirect) {
- /* Split addressing into uniform and offset */
- int offset = uniform - nir_uniform_driver_location[uniform];
- assert(offset = 0);
-
- uniform -= offset;
- assert(uniform = 0);
+ src = src_reg(dst_reg(UNIFORM, instr-const_index[0]));
+ src.reg_offset = instr-const_index[1];
- src = src_reg(dst_reg(UNIFORM, uniform));
- src.reg_offset = offset;
+ if (has_indirect) {
src_reg tmp = get_nir_src(instr-src[0], BRW_REGISTER_TYPE_D, 1);
src.reladdr = new(mem_ctx) src_reg(tmp);
- } else {
- src = src_reg(dst_reg(UNIFORM, uniform));
}
emit(MOV(dest, src));
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Mesa (master): gallium/auxiliary: optimize rgb9e5 helper some more
Module: Mesa
Branch: master
Commit: 48e6404c04da6c9655d7a8b625830d0d40f393ae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=48e6404c04da6c9655d7a8b625830d0d40f393ae
Author: Roland Scheidegger srol...@vmware.com
Date: Sun Aug 9 02:50:10 2015 +0200
gallium/auxiliary: optimize rgb9e5 helper some more
I used this as some testing ground for investigating some compiler
bits initially (e.g. lrint calls etc.), figured I could do much better
in the end just for fun...
This is mathematically equivalent, but uses some tricks to avoid
doubles and also replaces some float math with ints. Good for another
performance doubling or so. As a side note, some quick tests show that
llvm's loop vectorizer would be able to properly vectorize this version
(which it failed to do earlier due to doubles, producing a mess), giving
another 3 times performance increase with sse2 (more with sse4.1), but this
may not apply to mesa.
No piglit change.
Acked-by: Marek Olšák marek.ol...@amd.com
---
src/gallium/auxiliary/util/u_format_rgb9e5.h | 87 +-
1 file changed, 42 insertions(+), 45 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_format_rgb9e5.h
b/src/gallium/auxiliary/util/u_format_rgb9e5.h
index d11bfa8..21feba7 100644
--- a/src/gallium/auxiliary/util/u_format_rgb9e5.h
+++ b/src/gallium/auxiliary/util/u_format_rgb9e5.h
@@ -74,62 +74,59 @@ typedef union {
} field;
} rgb9e5;
-static inline float rgb9e5_ClampRange(float x)
-{
- if (x 0.0f) {
- if (x = MAX_RGB9E5) {
- return MAX_RGB9E5;
- } else {
- return x;
- }
- } else {
- /* NaN gets here too since comparisons with NaN always fail! */
- return 0.0f;
- }
-}
-/* Ok, FloorLog2 is not correct for the denorm and zero values, but we
- are going to do a max of this value with the minimum rgb9e5 exponent
- that will hide these problem cases. */
-static inline int rgb9e5_FloorLog2(float x)
+static inline int rgb9e5_ClampRange(float x)
{
float754 f;
-
+ float754 max;
f.value = x;
- return (f.field.biasedexponent - 127);
+ max.value = MAX_RGB9E5;
+
+ if (f.raw 0x7f80)
+ /* catches neg, NaNs */
+ return 0;
+ else if (f.raw = max.raw)
+ return max.raw;
+ else
+ return f.raw;
}
static inline unsigned float3_to_rgb9e5(const float rgb[3])
{
rgb9e5 retval;
- float maxrgb;
- int rm, gm, bm;
- float rc, gc, bc;
- int exp_shared, maxm;
+ int rm, gm, bm, exp_shared;
float754 revdenom = {0};
-
- rc = rgb9e5_ClampRange(rgb[0]);
- gc = rgb9e5_ClampRange(rgb[1]);
- bc = rgb9e5_ClampRange(rgb[2]);
-
- maxrgb = MAX3(rc, gc, bc);
- exp_shared = MAX2(-RGB9E5_EXP_BIAS - 1, rgb9e5_FloorLog2(maxrgb)) + 1 +
RGB9E5_EXP_BIAS;
+ float754 rc, bc, gc, maxrgb;
+
+ rc.raw = rgb9e5_ClampRange(rgb[0]);
+ gc.raw = rgb9e5_ClampRange(rgb[1]);
+ bc.raw = rgb9e5_ClampRange(rgb[2]);
+ maxrgb.raw = MAX3(rc.raw, gc.raw, bc.raw);
+
+ /*
+* Compared to what the spec suggests, instead of conditionally adjusting
+* the exponent after the fact do it here by doing the equivalent of +0.5 -
+* the int add will spill over into the exponent in this case.
+*/
+ maxrgb.raw += maxrgb.raw (1 (23-9));
+ exp_shared = MAX2((maxrgb.raw 23), -RGB9E5_EXP_BIAS - 1 + 127) +
+1 + RGB9E5_EXP_BIAS - 127;
+ revdenom.field.biasedexponent = 127 - (exp_shared - RGB9E5_EXP_BIAS -
+ RGB9E5_MANTISSA_BITS) + 1;
assert(exp_shared = RGB9E5_MAX_VALID_BIASED_EXP);
- assert(exp_shared = 0);
- revdenom.field.biasedexponent = 127 - (exp_shared - RGB9E5_EXP_BIAS -
RGB9E5_MANTISSA_BITS);
-
- maxm = (int) (maxrgb * revdenom.value + 0.5);
- if (maxm == MAX_RGB9E5_MANTISSA + 1) {
- revdenom.value *= 0.5f;
- exp_shared += 1;
- assert(exp_shared = RGB9E5_MAX_VALID_BIASED_EXP);
- } else {
- assert(maxm = MAX_RGB9E5_MANTISSA);
- }
-
- rm = (int) (rc * revdenom.value + 0.5);
- gm = (int) (gc * revdenom.value + 0.5);
- bm = (int) (bc * revdenom.value + 0.5);
+
+ /*
+* The spec uses strict round-up behavior (d3d10 disagrees, but in any case
+* must match what is done above for figuring out exponent).
+* We avoid the doubles ((int) rc * revdenom + 0.5) by doing the rounding
+* ourselves (revdenom was adjusted by +1, above).
+*/
+ rm = (int) (rc.value * revdenom.value);
+ gm = (int) (gc.value * revdenom.value);
+ bm = (int) (bc.value * revdenom.value);
+ rm = (rm 1) + (rm 1);
+ gm = (gm 1) + (gm 1);
+ bm = (bm 1) + (bm 1);
assert(rm = MAX_RGB9E5_MANTISSA);
assert(gm = MAX_RGB9E5_MANTISSA);
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Mesa (master): gallium/auxiliary: optimize rgb9e5 helper a bit
Module: Mesa
Branch: master
Commit: 941346a80323c9419b70e3987b900a69ebb08fb4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=941346a80323c9419b70e3987b900a69ebb08fb4
Author: Roland Scheidegger srol...@vmware.com
Date: Sun Aug 9 02:03:33 2015 +0200
gallium/auxiliary: optimize rgb9e5 helper a bit
This code (lifted straight from the extension) was doing things the most
inefficient way you could think of.
This drops some of the more expensive float operations, in particular
- int-cast floors (pointless, values always positive)
- 2 raised to (signed) integers (replace with simple exponent manipulation),
getting rid of a misguided comment in the process (implement with table...)
- float division (replace with mul of reverse of those exponents)
This is like 3 times faster (measured for float3_to_rgb9e5), though it depends
(e.g. llvm is clever enough to replace exp2 with ldexp whereas gcc is not,
division is not too bad on cpus with early-exit divs).
Note that keeping the double math for now (float x + 0.5), as the results may
otherwise differ.
Acked-by: Marek Olšák marek.ol...@amd.com
---
src/gallium/auxiliary/util/u_format_rgb9e5.h | 35 +-
1 file changed, 17 insertions(+), 18 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_format_rgb9e5.h
b/src/gallium/auxiliary/util/u_format_rgb9e5.h
index 59fc291..d11bfa8 100644
--- a/src/gallium/auxiliary/util/u_format_rgb9e5.h
+++ b/src/gallium/auxiliary/util/u_format_rgb9e5.h
@@ -21,7 +21,8 @@
* DEALINGS IN THE SOFTWARE.
*/
-/* Copied from EXT_texture_shared_exponent and edited. */
+/* Copied from EXT_texture_shared_exponent and edited, getting rid of
+ * expensive float math bits too. */
#ifndef RGB9E5_H
#define RGB9E5_H
@@ -39,7 +40,6 @@
#define RGB9E5_MANTISSA_VALUES (1RGB9E5_MANTISSA_BITS)
#define MAX_RGB9E5_MANTISSA (RGB9E5_MANTISSA_VALUES-1)
#define MAX_RGB9E5
(((float)MAX_RGB9E5_MANTISSA)/RGB9E5_MANTISSA_VALUES * (1MAX_RGB9E5_EXP))
-#define EPSILON_RGB9E5 ((1.0/RGB9E5_MANTISSA_VALUES) /
(1RGB9E5_EXP_BIAS))
typedef union {
unsigned int raw;
@@ -84,7 +84,7 @@ static inline float rgb9e5_ClampRange(float x)
}
} else {
/* NaN gets here too since comparisons with NaN always fail! */
- return 0.0;
+ return 0.0f;
}
}
@@ -106,31 +106,30 @@ static inline unsigned float3_to_rgb9e5(const float
rgb[3])
int rm, gm, bm;
float rc, gc, bc;
int exp_shared, maxm;
- double denom;
+ float754 revdenom = {0};
rc = rgb9e5_ClampRange(rgb[0]);
gc = rgb9e5_ClampRange(rgb[1]);
bc = rgb9e5_ClampRange(rgb[2]);
maxrgb = MAX3(rc, gc, bc);
- exp_shared = MAX2(-RGB9E5_EXP_BIAS-1, rgb9e5_FloorLog2(maxrgb)) + 1 +
RGB9E5_EXP_BIAS;
+ exp_shared = MAX2(-RGB9E5_EXP_BIAS - 1, rgb9e5_FloorLog2(maxrgb)) + 1 +
RGB9E5_EXP_BIAS;
assert(exp_shared = RGB9E5_MAX_VALID_BIASED_EXP);
assert(exp_shared = 0);
- /* This exp2 function could be replaced by a table. */
- denom = exp2(exp_shared - RGB9E5_EXP_BIAS - RGB9E5_MANTISSA_BITS);
+ revdenom.field.biasedexponent = 127 - (exp_shared - RGB9E5_EXP_BIAS -
RGB9E5_MANTISSA_BITS);
- maxm = (int) floor(maxrgb / denom + 0.5);
- if (maxm == MAX_RGB9E5_MANTISSA+1) {
- denom *= 2;
+ maxm = (int) (maxrgb * revdenom.value + 0.5);
+ if (maxm == MAX_RGB9E5_MANTISSA + 1) {
+ revdenom.value *= 0.5f;
exp_shared += 1;
assert(exp_shared = RGB9E5_MAX_VALID_BIASED_EXP);
} else {
assert(maxm = MAX_RGB9E5_MANTISSA);
}
- rm = (int) floor(rc / denom + 0.5);
- gm = (int) floor(gc / denom + 0.5);
- bm = (int) floor(bc / denom + 0.5);
+ rm = (int) (rc * revdenom.value + 0.5);
+ gm = (int) (gc * revdenom.value + 0.5);
+ bm = (int) (bc * revdenom.value + 0.5);
assert(rm = MAX_RGB9E5_MANTISSA);
assert(gm = MAX_RGB9E5_MANTISSA);
@@ -151,15 +150,15 @@ static inline void rgb9e5_to_float3(unsigned rgb, float
retval[3])
{
rgb9e5 v;
int exponent;
- float scale;
+ float754 scale = {0};
v.raw = rgb;
exponent = v.field.biasedexponent - RGB9E5_EXP_BIAS - RGB9E5_MANTISSA_BITS;
- scale = exp2f(exponent);
+ scale.field.biasedexponent = exponent + 127;
- retval[0] = v.field.r * scale;
- retval[1] = v.field.g * scale;
- retval[2] = v.field.b * scale;
+ retval[0] = v.field.r * scale.value;
+ retval[1] = v.field.g * scale.value;
+ retval[2] = v.field.b * scale.value;
}
#endif
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Mesa (master): mesa/formats: pass correct parameter to _mesa_is_format_compressed
Module: Mesa Branch: master Commit: 73e5adc4b2bf082addd1ae76fb23c2773887162b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=73e5adc4b2bf082addd1ae76fb23c2773887162b Author: Dave Airlie airl...@redhat.com Date: Wed Aug 26 10:37:09 2015 +1000 mesa/formats: pass correct parameter to _mesa_is_format_compressed commit 26c549e69d12e44e2e36c09764ce2cceab262a1b Author: Nanley Chery nanley.g.ch...@intel.com Date: Fri Jul 31 10:26:36 2015 -0700 mesa/formats: remove compressed formats from matching function caused a regression in my CTS testing, this looks like a clear thinko. Reviewed-by: Nanley Chery nanley.g.ch...@intel.com sSigned-off-by: Dave Airlie airl...@redhat.com --- src/mesa/main/formats.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c index 8dd07d8..34a4434 100644 --- a/src/mesa/main/formats.c +++ b/src/mesa/main/formats.c @@ -1979,7 +1979,7 @@ _mesa_format_matches_format_and_type(mesa_format mesa_format, case MESA_FORMAT_X8R8G8B8_SRGB: return GL_FALSE; default: - assert(_mesa_is_format_compressed(format)); + assert(_mesa_is_format_compressed(mesa_format)); if (error) *error = GL_INVALID_ENUM; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa/es3.1: Allow GL_COMPUTE_WORK_GROUP_SIZE for OpenGL ES 3.1
Module: Mesa
Branch: master
Commit: ae8d0e7abef27b25637ee25b857c44f13aef0d11
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae8d0e7abef27b25637ee25b857c44f13aef0d11
Author: Marta Lofstedt marta.lofst...@intel.com
Date: Wed Aug 19 15:30:33 2015 +0200
mesa/es3.1: Allow GL_COMPUTE_WORK_GROUP_SIZE for OpenGL ES 3.1
According to OpenGL ES specification section 7.12,
GL_COMPUTE_WORK_GROUP_SIZE, is supported by the
glGetProgramiv function.
Signed-off-by: Marta Lofstedt marta.lofst...@intel.com
Reviewed-by: Tapani Pälli tapani.pa...@intel.com
---
src/mesa/main/shaderapi.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index b227c17..0e0e0d6 100644
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -756,7 +756,7 @@ get_programiv(struct gl_context *ctx, GLuint program,
GLenum pname,
return;
case GL_COMPUTE_WORK_GROUP_SIZE: {
int i;
- if (!_mesa_is_desktop_gl(ctx) || !ctx-Extensions.ARB_compute_shader)
+ if (!_mesa_has_compute_shaders(ctx))
break;
if (!shProg-LinkStatus) {
_mesa_error(ctx, GL_INVALID_OPERATION, glGetProgramiv(program not
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Mesa (master): mesa/es3.1: Enable getting MAX_COMPUTE_WORK_GROUP_ values for OpenGL ES 3.1
Module: Mesa Branch: master Commit: c2a766880d6a92a0b7b3411062f61090d77f65c0 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2a766880d6a92a0b7b3411062f61090d77f65c0 Author: Marta Lofstedt marta.lofst...@intel.com Date: Wed Aug 19 15:33:21 2015 +0200 mesa/es3.1: Enable getting MAX_COMPUTE_WORK_GROUP_ values for OpenGL ES 3.1 According to the OpenGL ES 3.1 specification chapter 17, the MAX_COMPUTE_WORK_GROUP_COUNT and MAX_COMPUTE_WORK_GROUP_SIZE is available for glGetIntegeri_v. Signed-off-by: Marta Lofstedt marta.lofst...@linux.intel.com Reviewed-by: Tapani Pälli tapani.pa...@intel.com --- src/mesa/main/get.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c index 307a5ff..c691997 100644 --- a/src/mesa/main/get.c +++ b/src/mesa/main/get.c @@ -2049,7 +2049,7 @@ find_value_indexed(const char *func, GLenum pname, GLuint index, union value *v) return TYPE_INT; case GL_MAX_COMPUTE_WORK_GROUP_COUNT: - if (!_mesa_is_desktop_gl(ctx) || !ctx-Extensions.ARB_compute_shader) + if (!_mesa_has_compute_shaders(ctx)) goto invalid_enum; if (index = 3) goto invalid_value; @@ -2057,7 +2057,7 @@ find_value_indexed(const char *func, GLenum pname, GLuint index, union value *v) return TYPE_INT; case GL_MAX_COMPUTE_WORK_GROUP_SIZE: - if (!_mesa_is_desktop_gl(ctx) || !ctx-Extensions.ARB_compute_shader) + if (!_mesa_has_compute_shaders(ctx)) goto invalid_enum; if (index = 3) goto invalid_value; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa: GetTexLevelParameter{if}v changes for OpenGL ES 3.1
Module: Mesa
Branch: master
Commit: e0c2ea03377b52058324f735f7e1f55bb9d29750
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e0c2ea03377b52058324f735f7e1f55bb9d29750
Author: Tapani Pälli tapani.pa...@intel.com
Date: Tue Jul 28 11:25:35 2015 +0300
mesa: GetTexLevelParameter{if}v changes for OpenGL ES 3.1
Patch refactors existing parameters check to first check common enums
between desktop GL and GLES 3.1 and modifies get_tex_level_parameter_image
to be compatible with enums specified in 3.1.
v2: remove extra is_gles31() checks (suggested by Ilia)
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com (v1)
Reviewed-by: Marta Lofstedt marta.lofst...@intel.com (v1)
Reviewed-by: Ilia Mirkin imir...@alum.mit.edu
---
src/mesa/main/texparam.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/src/mesa/main/texparam.c b/src/mesa/main/texparam.c
index 16739f1..72d3611 100644
--- a/src/mesa/main/texparam.c
+++ b/src/mesa/main/texparam.c
@@ -1208,20 +1208,34 @@ static GLboolean
legal_get_tex_level_parameter_target(struct gl_context *ctx, GLenum target,
bool dsa)
{
+ /* Common targets for desktop GL and GLES 3.1. */
switch (target) {
- case GL_TEXTURE_1D:
- case GL_PROXY_TEXTURE_1D:
case GL_TEXTURE_2D:
- case GL_PROXY_TEXTURE_2D:
case GL_TEXTURE_3D:
- case GL_PROXY_TEXTURE_3D:
return GL_TRUE;
+ case GL_TEXTURE_2D_ARRAY_EXT:
+ return ctx-Extensions.EXT_texture_array;
case GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB:
case GL_TEXTURE_CUBE_MAP_NEGATIVE_X_ARB:
case GL_TEXTURE_CUBE_MAP_POSITIVE_Y_ARB:
case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y_ARB:
case GL_TEXTURE_CUBE_MAP_POSITIVE_Z_ARB:
case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB:
+ return ctx-Extensions.ARB_texture_cube_map;
+ case GL_TEXTURE_2D_MULTISAMPLE:
+ return ctx-Extensions.ARB_texture_multisample;
+ }
+
+ if (!_mesa_is_desktop_gl(ctx))
+ return GL_FALSE;
+
+ /* Rest of the desktop GL targets. */
+ switch (target) {
+ case GL_TEXTURE_1D:
+ case GL_PROXY_TEXTURE_1D:
+ case GL_PROXY_TEXTURE_2D:
+ case GL_PROXY_TEXTURE_3D:
+ return GL_TRUE;
case GL_PROXY_TEXTURE_CUBE_MAP_ARB:
return ctx-Extensions.ARB_texture_cube_map;
case GL_TEXTURE_CUBE_MAP_ARRAY_ARB:
@@ -1232,7 +1246,6 @@ legal_get_tex_level_parameter_target(struct gl_context
*ctx, GLenum target,
return ctx-Extensions.NV_texture_rectangle;
case GL_TEXTURE_1D_ARRAY_EXT:
case GL_PROXY_TEXTURE_1D_ARRAY_EXT:
- case GL_TEXTURE_2D_ARRAY_EXT:
case GL_PROXY_TEXTURE_2D_ARRAY_EXT:
return ctx-Extensions.EXT_texture_array;
case GL_TEXTURE_BUFFER:
@@ -1254,7 +1267,6 @@ legal_get_tex_level_parameter_target(struct gl_context
*ctx, GLenum target,
* target may also be TEXTURE_BUFFER, indicating the texture buffer.
*/
return ctx-API == API_OPENGL_CORE ctx-Version = 31;
- case GL_TEXTURE_2D_MULTISAMPLE:
case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
case GL_PROXY_TEXTURE_2D_MULTISAMPLE:
case GL_PROXY_TEXTURE_2D_MULTISAMPLE_ARRAY:
___
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Mesa (master): nir: Use nir_shader::stage rather than passing it around.
Module: Mesa
Branch: master
Commit: 5f14c417c86ced1847746c64d4db54c7e5ddc187
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f14c417c86ced1847746c64d4db54c7e5ddc187
Author: Kenneth Graunke kenn...@whitecape.org
Date: Tue Aug 18 01:53:29 2015 -0700
nir: Use nir_shader::stage rather than passing it around.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/glsl/nir/glsl_to_nir.cpp| 10 --
src/glsl/nir/nir.h |3 +--
src/glsl/nir/nir_lower_samplers.cpp |6 +++---
src/mesa/drivers/dri/i965/brw_nir.c |2 +-
4 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp
index 9cc065f..5fb4ee2 100644
--- a/src/glsl/nir/glsl_to_nir.cpp
+++ b/src/glsl/nir/glsl_to_nir.cpp
@@ -44,7 +44,7 @@ namespace {
class nir_visitor : public ir_visitor
{
public:
- nir_visitor(nir_shader *shader, gl_shader_stage stage);
+ nir_visitor(nir_shader *shader);
~nir_visitor();
virtual void visit(ir_variable *);
@@ -85,7 +85,6 @@ private:
bool supports_ints;
nir_shader *shader;
- gl_shader_stage stage;
nir_function_impl *impl;
exec_list *cf_node_list;
nir_instr *result; /* result of the expression tree last visited */
@@ -134,7 +133,7 @@ glsl_to_nir(struct gl_shader *sh, const
nir_shader_compiler_options *options)
{
nir_shader *shader = nir_shader_create(NULL, sh-Stage, options);
- nir_visitor v1(shader, sh-Stage);
+ nir_visitor v1(shader);
nir_function_visitor v2(v1);
v2.run(sh-ir);
visit_exec_list(sh-ir, v1);
@@ -142,11 +141,10 @@ glsl_to_nir(struct gl_shader *sh, const
nir_shader_compiler_options *options)
return shader;
}
-nir_visitor::nir_visitor(nir_shader *shader, gl_shader_stage stage)
+nir_visitor::nir_visitor(nir_shader *shader)
{
this-supports_ints = shader-options-native_integers;
this-shader = shader;
- this-stage = stage;
this-is_global = true;
this-var_table = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
_mesa_key_pointer_equal);
@@ -263,7 +261,7 @@ nir_visitor::visit(ir_variable *ir)
break;
case ir_var_shader_in:
- if (stage == MESA_SHADER_FRAGMENT
+ if (shader-stage == MESA_SHADER_FRAGMENT
ir-data.location == VARYING_SLOT_FACE) {
/* For whatever reason, GLSL IR makes gl_FrontFacing an input */
var-data.location = SYSTEM_VALUE_FRONT_FACE;
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 308298a..40871f7 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -1648,8 +1648,7 @@ void nir_lower_load_const_to_scalar(nir_shader *shader);
void nir_lower_phis_to_scalar(nir_shader *shader);
void nir_lower_samplers(nir_shader *shader,
-const struct gl_shader_program *shader_program,
-gl_shader_stage stage);
+const struct gl_shader_program *shader_program);
void nir_lower_system_values(nir_shader *shader);
void nir_lower_tex_projector(nir_shader *shader);
diff --git a/src/glsl/nir/nir_lower_samplers.cpp
b/src/glsl/nir/nir_lower_samplers.cpp
index 7a0b0a0..9583b45 100644
--- a/src/glsl/nir/nir_lower_samplers.cpp
+++ b/src/glsl/nir/nir_lower_samplers.cpp
@@ -168,11 +168,11 @@ lower_impl(nir_function_impl *impl, const struct
gl_shader_program *shader_progr
}
extern C void
-nir_lower_samplers(nir_shader *shader, const struct gl_shader_program
*shader_program,
- gl_shader_stage stage)
+nir_lower_samplers(nir_shader *shader,
+ const struct gl_shader_program *shader_program)
{
nir_foreach_overload(shader, overload) {
if (overload-impl)
- lower_impl(overload-impl, shader_program, stage);
+ lower_impl(overload-impl, shader_program, shader-stage);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c
b/src/mesa/drivers/dri/i965/brw_nir.c
index dfac44f..8c6d28a 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -136,7 +136,7 @@ brw_create_nir(struct brw_context *brw,
nir_validate_shader(nir);
if (shader_prog) {
- nir_lower_samplers(nir, shader_prog, stage);
+ nir_lower_samplers(nir, shader_prog);
nir_validate_shader(nir);
}
___
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Mesa (master): prog_to_nir: Use nir_builder_insert() rather than poking at cf_list.
Module: Mesa
Branch: master
Commit: 78856194c191bf5dc9e28c13b6d4c4d89b3206c1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=78856194c191bf5dc9e28c13b6d4c4d89b3206c1
Author: Kenneth Graunke kenn...@whitecape.org
Date: Thu Aug 6 07:39:34 2015 -0700
prog_to_nir: Use nir_builder_insert() rather than poking at cf_list.
I intend to remove nir_builder::cf_node_list, so I can't have this code
poking at it directly. The proper way is to set the insertion point and
then simply insert things there.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/program/prog_to_nir.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/mesa/program/prog_to_nir.c b/src/mesa/program/prog_to_nir.c
index 29ff638..d96b7bc 100644
--- a/src/mesa/program/prog_to_nir.c
+++ b/src/mesa/program/prog_to_nir.c
@@ -143,7 +143,7 @@ ptn_get_src(struct ptn_compile *c, const struct
prog_src_register *prog_src)
load-variables[0] = nir_deref_var_create(load,
c-input_vars[prog_src-Index]);
nir_ssa_dest_init(load-instr, load-dest, 4, NULL);
- nir_instr_insert_after_cf_list(b-cf_node_list, load-instr);
+ nir_builder_instr_insert(b, load-instr);
src.src = nir_src_for_ssa(load-dest.ssa);
break;
@@ -203,7 +203,7 @@ ptn_get_src(struct ptn_compile *c, const struct
prog_src_register *prog_src)
deref_arr-base_offset = prog_src-Index;
}
- nir_instr_insert_after_cf_list(b-cf_node_list, load-instr);
+ nir_builder_instr_insert(b, load-instr);
src.src = nir_src_for_ssa(load-dest.ssa);
break;
@@ -253,7 +253,7 @@ ptn_get_src(struct ptn_compile *c, const struct
prog_src_register *prog_src)
mov-dest.write_mask = 0x1;
mov-src[0] = src;
mov-src[0].swizzle[0] = swizzle;
-nir_instr_insert_after_cf_list(b-cf_node_list, mov-instr);
+nir_builder_instr_insert(b, mov-instr);
chans[i] = mov-dest.dest.ssa;
}
@@ -281,7 +281,7 @@ ptn_alu(nir_builder *b, nir_op op, nir_alu_dest dest,
nir_ssa_def **src)
instr-src[i].src = nir_src_for_ssa(src[i]);
instr-dest = dest;
- nir_instr_insert_after_cf_list(b-cf_node_list, instr-instr);
+ nir_builder_instr_insert(b, instr-instr);
}
static void
@@ -300,7 +300,7 @@ ptn_move_dest_masked(nir_builder *b, nir_alu_dest dest,
mov-src[0].src = nir_src_for_ssa(def);
for (unsigned i = def-num_components; i 4; i++)
mov-src[0].swizzle[i] = def-num_components - 1;
- nir_instr_insert_after_cf_list(b-cf_node_list, mov-instr);
+ nir_builder_instr_insert(b, mov-instr);
}
static void
@@ -561,7 +561,7 @@ ptn_kil(nir_builder *b, nir_alu_dest dest, nir_ssa_def
**src)
nir_intrinsic_instr *discard =
nir_intrinsic_instr_create(b-shader, nir_intrinsic_discard_if);
discard-src[0] = nir_src_for_ssa(cmp);
- nir_instr_insert_after_cf_list(b-cf_node_list, discard-instr);
+ nir_builder_instr_insert(b, discard-instr);
}
static void
@@ -688,7 +688,7 @@ ptn_tex(nir_builder *b, nir_alu_dest dest, nir_ssa_def
**src,
assert(src_number == num_srcs);
nir_ssa_dest_init(instr-instr, instr-dest, 4, NULL);
- nir_instr_insert_after_cf_list(b-cf_node_list, instr-instr);
+ nir_builder_instr_insert(b, instr-instr);
/* Resolve the writemask on the texture op. */
ptn_move_dest(b, dest, instr-dest.ssa);
@@ -944,7 +944,7 @@ ptn_add_output_stores(struct ptn_compile *c)
} else {
store-src[0].reg.reg = c-output_regs[var-data.location];
}
- nir_instr_insert_after_cf_list(c-build.cf_node_list, store-instr);
+ nir_builder_instr_insert(b, store-instr);
}
}
@@ -988,7 +988,7 @@ setup_registers_and_variables(struct ptn_compile *c)
load_x-num_components = 1;
load_x-variables[0] = nir_deref_var_create(load_x, var);
nir_ssa_dest_init(load_x-instr, load_x-dest, 1, NULL);
-nir_instr_insert_after_cf_list(b-cf_node_list, load_x-instr);
+nir_builder_instr_insert(b, load_x-instr);
nir_ssa_def *f001 = nir_vec4(b, load_x-dest.ssa,
nir_imm_float(b, 0.0),
nir_imm_float(b, 0.0),
nir_imm_float(b, 1.0));
@@ -1004,7 +1004,7 @@ setup_registers_and_variables(struct ptn_compile *c)
store-num_components = 4;
store-variables[0] = nir_deref_var_create(store, fullvar);
store-src[0] = nir_src_for_ssa(f001);
-nir_instr_insert_after_cf_list(b-cf_node_list, store-instr);
+nir_builder_instr_insert(b, store-instr);
/* Insert the real input into the list so the driver has real
* inputs, but set c-input_vars[i] to the temporary so we use
@@ -1108,7 +1108,7 @@ prog_to_nir(const struct gl_program *prog,
c-build.shader = s;
c-build.impl = impl;
- c-build.cf_node_list =
Mesa (master): gallium/ttn: Use nir_builder_insert() rather than poking at cf_list.
Module: Mesa
Branch: master
Commit: 1bec29d04d970b4d60a8c60252313f25bebfe024
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1bec29d04d970b4d60a8c60252313f25bebfe024
Author: Kenneth Graunke kenn...@whitecape.org
Date: Thu Aug 6 07:44:35 2015 -0700
gallium/ttn: Use nir_builder_insert() rather than poking at cf_list.
I intend to remove nir_builder::cf_node_list, so I can't have this code
poking at it directly. The proper way is to set the insertion point and
then simply insert things there.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Eric Anholt e...@anholt.net
---
src/gallium/auxiliary/nir/tgsi_to_nir.c | 32 +++
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c
b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index ecba0d7..278d5e9 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -308,7 +308,7 @@ ttn_emit_immediate(struct ttn_compile *c)
for (i = 0; i 4; i++)
load_const-value.u[i] = tgsi_imm-u[i].Uint;
- nir_instr_insert_after_cf_list(b-cf_node_list, load_const-instr);
+ nir_builder_instr_insert(b, load_const-instr);
}
static nir_src
@@ -364,7 +364,7 @@ ttn_src_for_file_and_index(struct ttn_compile *c, unsigned
file, unsigned index,
load-variables[0] = ttn_array_deref(c, load, var, offset, indirect);
nir_ssa_dest_init(load-instr, load-dest, 4, NULL);
- nir_instr_insert_after_cf_list(b-cf_node_list, load-instr);
+ nir_builder_instr_insert(b, load-instr);
src = nir_src_for_ssa(load-dest.ssa);
@@ -415,7 +415,7 @@ ttn_src_for_file_and_index(struct ttn_compile *c, unsigned
file, unsigned index,
load-num_components = ncomp;
nir_ssa_dest_init(load-instr, load-dest, ncomp, NULL);
- nir_instr_insert_after_cf_list(b-cf_node_list, load-instr);
+ nir_builder_instr_insert(b, load-instr);
src = nir_src_for_ssa(load-dest.ssa);
break;
@@ -477,7 +477,7 @@ ttn_src_for_file_and_index(struct ttn_compile *c, unsigned
file, unsigned index,
srcn++;
}
nir_ssa_dest_init(load-instr, load-dest, 4, NULL);
- nir_instr_insert_after_cf_list(b-cf_node_list, load-instr);
+ nir_builder_instr_insert(b, load-instr);
src = nir_src_for_ssa(load-dest.ssa);
break;
@@ -553,7 +553,7 @@ ttn_get_dest(struct ttn_compile *c, struct
tgsi_full_dst_register *tgsi_fdst)
load-dest = nir_dest_for_reg(reg);
- nir_instr_insert_after_cf_list(b-cf_node_list, load-instr);
+ nir_builder_instr_insert(b, load-instr);
} else {
assert(!tgsi_dst-Indirect);
dest.dest.reg.reg = c-temp_regs[index].reg;
@@ -668,7 +668,7 @@ ttn_alu(nir_builder *b, nir_op op, nir_alu_dest dest,
nir_ssa_def **src)
instr-src[i].src = nir_src_for_ssa(src[i]);
instr-dest = dest;
- nir_instr_insert_after_cf_list(b-cf_node_list, instr-instr);
+ nir_builder_instr_insert(b, instr-instr);
}
static void
@@ -684,7 +684,7 @@ ttn_move_dest_masked(nir_builder *b, nir_alu_dest dest,
mov-src[0].src = nir_src_for_ssa(def);
for (unsigned i = def-num_components; i 4; i++)
mov-src[0].swizzle[i] = def-num_components - 1;
- nir_instr_insert_after_cf_list(b-cf_node_list, mov-instr);
+ nir_builder_instr_insert(b, mov-instr);
}
static void
@@ -903,7 +903,7 @@ ttn_kill(nir_builder *b, nir_op op, nir_alu_dest dest,
nir_ssa_def **src)
{
nir_intrinsic_instr *discard =
nir_intrinsic_instr_create(b-shader, nir_intrinsic_discard);
- nir_instr_insert_after_cf_list(b-cf_node_list, discard-instr);
+ nir_builder_instr_insert(b, discard-instr);
}
static void
@@ -913,7 +913,7 @@ ttn_kill_if(nir_builder *b, nir_op op, nir_alu_dest dest,
nir_ssa_def **src)
nir_intrinsic_instr *discard =
nir_intrinsic_instr_create(b-shader, nir_intrinsic_discard_if);
discard-src[0] = nir_src_for_ssa(cmp);
- nir_instr_insert_after_cf_list(b-cf_node_list, discard-instr);
+ nir_builder_instr_insert(b, discard-instr);
}
static void
@@ -977,14 +977,14 @@ static void
ttn_cont(nir_builder *b)
{
nir_jump_instr *instr = nir_jump_instr_create(b-shader, nir_jump_continue);
- nir_instr_insert_after_cf_list(b-cf_node_list, instr-instr);
+ nir_builder_instr_insert(b, instr-instr);
}
static void
ttn_brk(nir_builder *b)
{
nir_jump_instr *instr = nir_jump_instr_create(b-shader, nir_jump_break);
- nir_instr_insert_after_cf_list(b-cf_node_list, instr-instr);
+ nir_builder_instr_insert(b, instr-instr);
}
static void
@@ -1280,7 +1280,7 @@ ttn_tex(struct ttn_compile *c, nir_alu_dest dest,
nir_ssa_def **src)
assert(src_number == num_srcs);
nir_ssa_dest_init(instr-instr, instr-dest, 4, NULL);
- nir_instr_insert_after_cf_list(b-cf_node_list, instr-instr);
+ nir_builder_instr_insert(b, instr-instr);
/* Resolve the writemask on the texture
Mesa (master): nir: Store gl_shader_stage in nir_shader.
Module: Mesa
Branch: master
Commit: d4d5b430a52aab148c8697deaedd8864e1749f3c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4d5b430a52aab148c8697deaedd8864e1749f3c
Author: Kenneth Graunke kenn...@whitecape.org
Date: Tue Aug 18 01:48:34 2015 -0700
nir: Store gl_shader_stage in nir_shader.
This makes it easy for NIR passes to inspect what kind of shader they're
operating on.
Thanks to Michel Dänzer for helping me figure out where TGSI stores the
shader stage information.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/gallium/auxiliary/nir/tgsi_to_nir.c | 25 +
src/glsl/nir/glsl_to_nir.cpp|2 +-
src/glsl/nir/nir.c |6 +-
src/glsl/nir/nir.h |4
src/mesa/program/prog_to_nir.c |4 +++-
5 files changed, 34 insertions(+), 7 deletions(-)
diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c
b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index 969e613..ecba0d7 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -1765,6 +1765,21 @@ ttn_add_output_stores(struct ttn_compile *c)
}
}
+static gl_shader_stage
+tgsi_processor_to_shader_stage(unsigned processor)
+{
+ switch (processor) {
+ case TGSI_PROCESSOR_FRAGMENT: return MESA_SHADER_FRAGMENT;
+ case TGSI_PROCESSOR_VERTEX:return MESA_SHADER_VERTEX;
+ case TGSI_PROCESSOR_GEOMETRY: return MESA_SHADER_GEOMETRY;
+ case TGSI_PROCESSOR_TESS_CTRL: return MESA_SHADER_TESS_CTRL;
+ case TGSI_PROCESSOR_TESS_EVAL: return MESA_SHADER_TESS_EVAL;
+ case TGSI_PROCESSOR_COMPUTE: return MESA_SHADER_COMPUTE;
+ default:
+ unreachable(invalid TGSI processor);
+ };
+}
+
struct nir_shader *
tgsi_to_nir(const void *tgsi_tokens,
const nir_shader_compiler_options *options)
@@ -1776,7 +1791,12 @@ tgsi_to_nir(const void *tgsi_tokens,
int ret;
c = rzalloc(NULL, struct ttn_compile);
- s = nir_shader_create(NULL, options);
+
+ tgsi_scan_shader(tgsi_tokens, scan);
+ c-scan = scan;
+
+ s = nir_shader_create(NULL, tgsi_processor_to_shader_stage(scan.processor),
+ options);
nir_function *func = nir_function_create(s, main);
nir_function_overload *overload = nir_function_overload_create(func);
@@ -1785,9 +1805,6 @@ tgsi_to_nir(const void *tgsi_tokens,
nir_builder_init(c-build, impl);
nir_builder_insert_after_cf_list(c-build, impl-body);
- tgsi_scan_shader(tgsi_tokens, scan);
- c-scan = scan;
-
s-num_inputs = scan.file_max[TGSI_FILE_INPUT] + 1;
s-num_uniforms = scan.const_file_max[0] + 1;
s-num_outputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp
index 614d1dd..9cc065f 100644
--- a/src/glsl/nir/glsl_to_nir.cpp
+++ b/src/glsl/nir/glsl_to_nir.cpp
@@ -132,7 +132,7 @@ private:
nir_shader *
glsl_to_nir(struct gl_shader *sh, const nir_shader_compiler_options *options)
{
- nir_shader *shader = nir_shader_create(NULL, options);
+ nir_shader *shader = nir_shader_create(NULL, sh-Stage, options);
nir_visitor v1(shader, sh-Stage);
nir_function_visitor v2(v1);
diff --git a/src/glsl/nir/nir.c b/src/glsl/nir/nir.c
index 5115f24..77cc4f0 100644
--- a/src/glsl/nir/nir.c
+++ b/src/glsl/nir/nir.c
@@ -30,7 +30,9 @@
#include assert.h
nir_shader *
-nir_shader_create(void *mem_ctx, const nir_shader_compiler_options *options)
+nir_shader_create(void *mem_ctx,
+ gl_shader_stage stage,
+ const nir_shader_compiler_options *options)
{
nir_shader *shader = ralloc(mem_ctx, nir_shader);
@@ -50,6 +52,8 @@ nir_shader_create(void *mem_ctx, const
nir_shader_compiler_options *options)
shader-num_outputs = 0;
shader-num_uniforms = 0;
+ shader-stage = stage;
+
return shader;
}
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 011a80a..308298a 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -1474,6 +1474,9 @@ typedef struct nir_shader {
* access plus one
*/
unsigned num_inputs, num_uniforms, num_outputs;
+
+ /** The shader stage, such as MESA_SHADER_VERTEX. */
+ gl_shader_stage stage;
} nir_shader;
#define nir_foreach_overload(shader, overload)\
@@ -1482,6 +1485,7 @@ typedef struct nir_shader {
(func)-overload_list)
nir_shader *nir_shader_create(void *mem_ctx,
+ gl_shader_stage stage,
const nir_shader_compiler_options *options);
/** creates a register, including assigning it an index and adding it to the
list */
diff --git a/src/mesa/program/prog_to_nir.c b/src/mesa/program/prog_to_nir.c
index 9d4af12..29ff638 100644
--- a/src/mesa/program/prog_to_nir.c
+++ b/src/mesa/program/prog_to_nir.c
@@ -33,6 +33,7 @@
#include
Mesa (master): mesa/texgetimage: fix missing stencil check
Module: Mesa
Branch: master
Commit: c1452983b44cc8ee238b8c7e2cfca1105c707487
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c1452983b44cc8ee238b8c7e2cfca1105c707487
Author: Dave Airlie airl...@redhat.com
Date: Mon Aug 24 09:52:12 2015 +1000
mesa/texgetimage: fix missing stencil check
GetTexImage can read to stencil8 but only from
a stencil or depthstencil textures.
This fixes a bunch of failures in CTS
GL33-CTS.gtf32.GL3Tests.packed_pixels
Reviewed-by: Marek Olšák marek.ol...@amd.com
Cc: 11.0 mesa-sta...@lists.freedesktop.org
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/mesa/main/texgetimage.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/src/mesa/main/texgetimage.c b/src/mesa/main/texgetimage.c
index 3c1e166..f62553d 100644
--- a/src/mesa/main/texgetimage.c
+++ b/src/mesa/main/texgetimage.c
@@ -1213,6 +1213,13 @@ getteximage_error_check(struct gl_context *ctx,
%s(format=GL_STENCIL_INDEX), caller);
return true;
}
+ else if (_mesa_is_stencil_format(format)
+!_mesa_is_depthstencil_format(baseFormat)
+!_mesa_is_stencil_format(baseFormat)) {
+ _mesa_error(ctx, GL_INVALID_OPERATION,
+ %s(format mismatch), caller);
+ return true;
+ }
else if (_mesa_is_ycbcr_format(format)
!_mesa_is_ycbcr_format(baseFormat)) {
_mesa_error(ctx, GL_INVALID_OPERATION,
___
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mesa-commit@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa/formats: make format testing a gtest
Module: Mesa
Branch: master
Commit: 8e581747d2342950ff44488064eef53768b3ae82
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e581747d2342950ff44488064eef53768b3ae82
Author: Nanley Chery nanley.g.ch...@intel.com
Date: Tue Aug 18 12:42:57 2015 -0700
mesa/formats: make format testing a gtest
We currently check that our format info table is sane during context
initialization in debug builds. Perform this check during
`make check` instead. This enables format testing in release builds
and removes the requirement of an exhuastive switch for
_mesa_uncompressed_format_to_type_and_comps().
v2. indentation and conditional inclusion fixes (Chad).
allow tests to continue running if any format fails
and display the failing format name.
Reviewed-by: Chad Versace chad.vers...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/context.c |4 -
src/mesa/main/formats.c | 155 +-
src/mesa/main/tests/Makefile.am |1 +
src/mesa/main/tests/mesa_formats.cpp | 132 +
4 files changed, 137 insertions(+), 155 deletions(-)
diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index 888c461..be542dd 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -402,10 +402,6 @@ one_time_init( struct gl_context *ctx )
PACKAGE_VERSION, __DATE__, __TIME__);
}
#endif
-
-#ifdef DEBUG
- _mesa_test_formats();
-#endif
}
/* per-API one-time init */
diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index 5e1d9a6..54d87c7 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -83,6 +83,7 @@ static const struct gl_format_info *
_mesa_get_format_info(mesa_format format)
{
const struct gl_format_info *info = format_info[format];
+ STATIC_ASSERT(ARRAY_SIZE(format_info) == MESA_FORMAT_COUNT);
assert(info-Name == format);
return info;
}
@@ -864,118 +865,6 @@ _mesa_format_row_stride(mesa_format format, GLsizei width)
}
-/**
- * Debug/test: check that all uncompressed formats are handled in the
- * _mesa_uncompressed_format_to_type_and_comps() function. When new pixel
- * formats are added to Mesa, that function needs to be updated.
- * This is a no-op after the first call.
- */
-static void
-check_format_to_type_and_comps(void)
-{
- mesa_format f;
-
- for (f = MESA_FORMAT_NONE + 1; f MESA_FORMAT_COUNT; f++) {
- GLenum datatype = 0;
- GLuint comps = 0;
- /* This function will emit a problem/warning if the format is
- * not handled.
- */
- if (!_mesa_is_format_compressed(f))
- _mesa_uncompressed_format_to_type_and_comps(f, datatype, comps);
- }
-}
-
-/**
- * Do sanity checking of the format info table.
- */
-void
-_mesa_test_formats(void)
-{
- GLuint i;
-
- STATIC_ASSERT(ARRAY_SIZE(format_info) == MESA_FORMAT_COUNT);
-
- for (i = 0; i MESA_FORMAT_COUNT; i++) {
- const struct gl_format_info *info = _mesa_get_format_info(i);
- assert(info);
-
- assert(info-Name == i);
-
- if (info-Name == MESA_FORMAT_NONE)
- continue;
-
- if (info-BlockWidth == 1 info-BlockHeight == 1) {
- if (info-RedBits 0) {
-GLuint t = info-RedBits + info-GreenBits
- + info-BlueBits + info-AlphaBits;
-assert(t / 8 = info-BytesPerBlock);
-(void) t;
- }
- }
-
- assert(info-DataType == GL_UNSIGNED_NORMALIZED ||
- info-DataType == GL_SIGNED_NORMALIZED ||
- info-DataType == GL_UNSIGNED_INT ||
- info-DataType == GL_INT ||
- info-DataType == GL_FLOAT ||
- /* Z32_FLOAT_X24S8 has DataType of GL_NONE */
- info-DataType == GL_NONE);
-
- if (info-BaseFormat == GL_RGB) {
- assert(info-RedBits 0);
- assert(info-GreenBits 0);
- assert(info-BlueBits 0);
- assert(info-AlphaBits == 0);
- assert(info-LuminanceBits == 0);
- assert(info-IntensityBits == 0);
- }
- else if (info-BaseFormat == GL_RGBA) {
- assert(info-RedBits 0);
- assert(info-GreenBits 0);
- assert(info-BlueBits 0);
- assert(info-AlphaBits 0);
- assert(info-LuminanceBits == 0);
- assert(info-IntensityBits == 0);
- }
- else if (info-BaseFormat == GL_RG) {
- assert(info-RedBits 0);
- assert(info-GreenBits 0);
- assert(info-BlueBits == 0);
- assert(info-AlphaBits == 0);
- assert(info-LuminanceBits == 0);
- assert(info-IntensityBits == 0);
- }
- else if (info-BaseFormat == GL_RED) {
- assert(info-RedBits 0);
- assert(info-GreenBits == 0);
- assert(info-BlueBits == 0);
- assert(info-AlphaBits == 0);
- assert(info-LuminanceBits == 0);
- assert(info-IntensityBits == 0);
- }
- else if (info-BaseFormat ==
Mesa (master): mesa/formats: remove compressed formats from matching function
Module: Mesa
Branch: master
Commit: 26c549e69d12e44e2e36c09764ce2cceab262a1b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=26c549e69d12e44e2e36c09764ce2cceab262a1b
Author: Nanley Chery nanley.g.ch...@intel.com
Date: Fri Jul 31 10:26:36 2015 -0700
mesa/formats: remove compressed formats from matching function
All compressed formats return GL_FALSE and there isn't any evidence to
support that this behaviour would change. Remove all switch cases for
compressed formats.
v2. Since the exhaustive switch is removed, add a gtest to ensure
all formats are handled.
v3. Ensure that GL_NO_ERROR is set before returning.
v4. Fix an arg to _mesa_uncompressed_format_to_type_and_comps();
fix formatting and misc improvements (Chad).
Reviewed-by: Chad Versace chad.vers...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i915/intel_pixel_read.c |2 +-
src/mesa/drivers/dri/i915/intel_tex_image.c |2 +-
src/mesa/main/formats.c | 58 +-
src/mesa/main/formats.h |2 +-
src/mesa/main/readpix.c |2 +-
src/mesa/main/tests/mesa_formats.cpp |9 +++-
src/mesa/main/texgetimage.c |2 +-
src/mesa/main/texstore.c |2 +-
src/mesa/state_tracker/st_cb_readpixels.c|2 +-
src/mesa/state_tracker/st_cb_texture.c |6 +--
src/mesa/state_tracker/st_format.c |2 +-
src/mesa/swrast/s_drawpix.c |2 +-
12 files changed, 31 insertions(+), 60 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/intel_pixel_read.c
b/src/mesa/drivers/dri/i915/intel_pixel_read.c
index 149e921..e6fa8f2 100644
--- a/src/mesa/drivers/dri/i915/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/i915/intel_pixel_read.c
@@ -91,7 +91,7 @@ do_blit_readpixels(struct gl_context * ctx,
if (ctx-_ImageTransferState ||
!_mesa_format_matches_format_and_type(irb-mt-format, format, type,
- false)) {
+ false, NULL)) {
DBG(%s - bad format for blit\n, __func__);
return false;
}
diff --git a/src/mesa/drivers/dri/i915/intel_tex_image.c
b/src/mesa/drivers/dri/i915/intel_tex_image.c
index 0a213e9..5ab60d1 100644
--- a/src/mesa/drivers/dri/i915/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i915/intel_tex_image.c
@@ -134,7 +134,7 @@ try_pbo_upload(struct gl_context *ctx,
}
if (!_mesa_format_matches_format_and_type(intelImage-mt-format,
- format, type, false)) {
+ format, type, false, NULL)) {
DBG(%s: format mismatch (upload to %s with format 0x%x, type 0x%x)\n,
__func__, _mesa_get_format_name(intelImage-mt-format),
format, type);
diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index 54d87c7..8dd07d8 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -1420,20 +1420,26 @@ _mesa_uncompressed_format_to_type_and_comps(mesa_format
format,
* \param format the user-specified image format
* \param type the user-specified image datatype
* \param swapBytes typically the current pixel pack/unpack byteswap state
+ * \param[out] error GL_NO_ERROR if format is an expected input.
+ * GL_INVALID_ENUM if format is an unexpected input.
* \return GL_TRUE if the formats match, GL_FALSE otherwise.
*/
GLboolean
_mesa_format_matches_format_and_type(mesa_format mesa_format,
GLenum format, GLenum type,
- GLboolean swapBytes)
+GLboolean swapBytes, GLenum *error)
{
const GLboolean littleEndian = _mesa_little_endian();
+ if (error)
+ *error = GL_NO_ERROR;
/* Note: When reading a GL format/type combination, the format lists channel
* assignments from most significant channel in the type to least
* significant. A type with _REV indicates that the assignments are
* swapped, so they are listed from least significant to most significant.
*
+* Compressed formats will fall through and return GL_FALSE.
+*
* For sanity, please keep this switch statement ordered the same as the
* enums in formats.h.
*/
@@ -1694,26 +1700,6 @@ _mesa_format_matches_format_and_type(mesa_format
mesa_format,
case MESA_FORMAT_S_UINT8:
return format == GL_STENCIL_INDEX type == GL_UNSIGNED_BYTE;
- case MESA_FORMAT_SRGB_DXT1:
- case MESA_FORMAT_SRGBA_DXT1:
- case MESA_FORMAT_SRGBA_DXT3:
- case MESA_FORMAT_SRGBA_DXT5:
- return GL_FALSE;
-
- case MESA_FORMAT_RGB_FXT1:
- case MESA_FORMAT_RGBA_FXT1:
- case MESA_FORMAT_RGB_DXT1:
- case MESA_FORMAT_RGBA_DXT1:
- case MESA_FORMAT_RGBA_DXT3:
- case MESA_FORMAT_RGBA_DXT5:
- return GL_FALSE;
-
- case MESA_FORMAT_BPTC_RGBA_UNORM:
-
Mesa (master): mesa/teximage: Add GL error parameter to _mesa_target_can_be_compressed
Module: Mesa
Branch: master
Commit: 1d2a844e7d55645ea3d24fb589bec03695b3d2b1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d2a844e7d55645ea3d24fb589bec03695b3d2b1
Author: Nanley Chery nanley.g.ch...@intel.com
Date: Fri Aug 21 13:09:08 2015 -0700
mesa/teximage: Add GL error parameter to _mesa_target_can_be_compressed
Enables _mesa_target_can_be_compressed to return the appropriate GL error
depending on it's inputs. Use the parameter to return the appropriate GL error
for ETC2 formats on GLES3.
Suggested-by: Chad Versace chad.vers...@intel.com
Reviewed-by: Chad Versace chad.vers...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/teximage.c | 90 ++--
src/mesa/main/teximage.h |2 +-
src/mesa/main/texstorage.c | 20 +++---
3 files changed, 68 insertions(+), 44 deletions(-)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 6a5489e..274ecad 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -1785,18 +1785,36 @@ compressedteximage_only_format(const struct gl_context
*ctx, GLenum format)
}
+/* Writes to an GL error pointer if non-null and returns whether or not the
+ * error is GL_NO_ERROR */
+static bool
+write_error(GLenum *err_ptr, GLenum error)
+{
+ if (err_ptr)
+ *err_ptr = error;
+
+ return error == GL_NO_ERROR;
+}
+
/**
* Helper function to determine whether a target and specific compression
- * format are supported.
+ * format are supported. The error parameter returns GL_NO_ERROR if the
+ * target can be compressed. Otherwise it returns either GL_INVALID_OPERATION
+ * or GL_INVALID_ENUM, whichever is more appropriate.
*/
GLboolean
_mesa_target_can_be_compressed(const struct gl_context *ctx, GLenum target,
- GLenum intFormat)
+ GLenum intFormat, GLenum *error)
{
+ GLboolean target_can_be_compresed = GL_FALSE;
+ mesa_format format = _mesa_glenum_to_compressed_format(intFormat);
+ enum mesa_format_layout layout = _mesa_get_format_layout(format);
+
switch (target) {
case GL_TEXTURE_2D:
case GL_PROXY_TEXTURE_2D:
- return GL_TRUE; /* true for any compressed format so far */
+ target_can_be_compresed = GL_TRUE; /* true for any compressed format so
far */
+ break;
case GL_PROXY_TEXTURE_CUBE_MAP:
case GL_TEXTURE_CUBE_MAP:
case GL_TEXTURE_CUBE_MAP_POSITIVE_X:
@@ -1805,26 +1823,46 @@ _mesa_target_can_be_compressed(const struct gl_context
*ctx, GLenum target,
case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y:
case GL_TEXTURE_CUBE_MAP_POSITIVE_Z:
case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z:
- return ctx-Extensions.ARB_texture_cube_map;
+ target_can_be_compresed = ctx-Extensions.ARB_texture_cube_map;
+ break;
case GL_PROXY_TEXTURE_2D_ARRAY_EXT:
case GL_TEXTURE_2D_ARRAY_EXT:
- return ctx-Extensions.EXT_texture_array;
+ target_can_be_compresed = ctx-Extensions.EXT_texture_array;
+ break;
case GL_PROXY_TEXTURE_CUBE_MAP_ARRAY:
case GL_TEXTURE_CUBE_MAP_ARRAY:
- return ctx-Extensions.ARB_texture_cube_map_array;
+ /* From section 3.8.6, page 146 of OpenGL ES 3.0 spec:
+ *
+ *The ETC2/EAC texture compression algorithm supports only
+ * two-dimensional images. If internalformat is an ETC2/EAC format,
+ * glCompressedTexImage3D will generate an INVALID_OPERATION error if
+ * target is not TEXTURE_2D_ARRAY.
+ *
+ * This should also be applicable for glTexStorage3D(). Other available
+ * targets for these functions are: TEXTURE_3D and
TEXTURE_CUBE_MAP_ARRAY.
+ */
+ if (layout == MESA_FORMAT_LAYOUT_ETC2 _mesa_is_gles3(ctx))
+return write_error(error, GL_INVALID_OPERATION);
+
+ target_can_be_compresed = ctx-Extensions.ARB_texture_cube_map_array;
+ break;
case GL_TEXTURE_3D:
- switch (intFormat) {
- case GL_COMPRESSED_RGBA_BPTC_UNORM:
- case GL_COMPRESSED_SRGB_ALPHA_BPTC_UNORM:
- case GL_COMPRESSED_RGB_BPTC_SIGNED_FLOAT:
- case GL_COMPRESSED_RGB_BPTC_UNSIGNED_FLOAT:
- return ctx-Extensions.ARB_texture_compression_bptc;
- default:
- return GL_FALSE;
+
+ /* See ETC2/EAC comment in switch case GL_TEXTURE_CUBE_MAP_ARRAY. */
+ if (layout == MESA_FORMAT_LAYOUT_ETC2 _mesa_is_gles3(ctx))
+ return write_error(error, GL_INVALID_OPERATION);
+
+ if (layout == MESA_FORMAT_LAYOUT_BPTC) {
+ target_can_be_compresed =
ctx-Extensions.ARB_texture_compression_bptc;
+ break;
}
+
+ break;
default:
- return GL_FALSE;
+ break;
}
+ return write_error(error,
+ target_can_be_compresed ? GL_NO_ERROR : GL_INVALID_ENUM);
}
@@ -2284,8 +2322,9 @@ texture_error_check( struct gl_context *ctx,
/* additional checks for compressed textures */
if (_mesa_is_compressed_format(ctx,
Mesa (master): freedreno/ir3: fix compile break after splitting out nir_control_flow.h
Module: Mesa Branch: master Commit: 0ab29751b62680cd77195bb33cf18068bd73f2f3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ab29751b62680cd77195bb33cf18068bd73f2f3 Author: Rob Clark robcl...@freedesktop.org Date: Tue Aug 25 08:17:30 2015 -0400 freedreno/ir3: fix compile break after splitting out nir_control_flow.h The commit: commit b49371b8ede380f10ea3ab333246a3b01ac6aca5 Author: Connor Abbott cwabbo...@gmail.com AuthorDate: Tue Jul 21 19:54:18 2015 -0700 nir: move control flow modification to its own file split out some control flow related APIs into a separate header, but did not update drivers. Signed-off-by: Rob Clark robcl...@freedesktop.org --- src/gallium/drivers/freedreno/ir3/ir3_nir_lower_if_else.c |1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/freedreno/ir3/ir3_nir_lower_if_else.c b/src/gallium/drivers/freedreno/ir3/ir3_nir_lower_if_else.c index dc9e462..bed7b7b 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_nir_lower_if_else.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_nir_lower_if_else.c @@ -29,6 +29,7 @@ #include ir3_nir.h #include glsl/nir/nir_builder.h +#include glsl/nir/nir_control_flow.h /* Based on nir_opt_peephole_select, and hacked up to more aggressively * flatten anything that can be flattened ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): freedreno/ir3: fix compile break after fxn- start_block removal
Module: Mesa Branch: master Commit: 8b2d0bb844e4c9b6141f68431b6e6dc135eb3503 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b2d0bb844e4c9b6141f68431b6e6dc135eb3503 Author: Rob Clark robcl...@freedesktop.org Date: Tue Aug 25 08:13:04 2015 -0400 freedreno/ir3: fix compile break after fxn-start_block removal The commit: commit 8e0d4ef3410ea07d9621df3e083bc3e7c1ad2ab0 Author: Kenneth Graunke kenn...@whitecape.org AuthorDate: Thu Aug 6 18:18:40 2015 -0700 nir: Delete the nir_function_impl::start_block field. removed the start_block field without fixing up drivers.. Signed-off-by: Rob Clark robcl...@freedesktop.org --- src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c index 13c395f..071901a 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c @@ -2312,7 +2312,7 @@ emit_instructions(struct ir3_compile *ctx) ctx-ir = ir3_create(ctx-compiler, ninputs, noutputs); /* Create inputs in first block: */ - ctx-block = get_block(ctx, fxn-start_block); + ctx-block = get_block(ctx, nir_start_block(fxn)); ctx-in_block = ctx-block; list_addtail(ctx-block-node, ctx-ir-block_list); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
