Mesa (master): i965/fs: The barrier send uses only 1 payload register

2015-09-15 Thread Jordan Justen 
Module: Mesa
Branch: master
Commit: 47e18a595731c054ac254e26066e6dea804f34e8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=47e18a595731c054ac254e26066e6dea804f34e8

Author: Jordan Justen 
Date:   Tue Sep 15 14:01:17 2015 -0700

i965/fs: The barrier send uses only 1 payload register

When preparing the barrier payload, the instructions should operate in
simd8 mode since we only use 1 payload register.

fs_inst::regs_read is also updated to indicate that it only reads one
register for SHADER_OPCODE_BARRIER.

These issues were flagged by:

commit cadd7dd384b33a779d46bd664f456bed4a21a5b7
Author: Jason Ekstrand 
Date:   Thu Jul 2 15:41:02 2015 -0700

i965/fs: Add a very basic validation pass

Signed-off-by: Jordan Justen 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_fs.cpp |1 +
 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |6 --
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 63bee0a..b4d0567 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -797,6 +797,7 @@ fs_inst::regs_read(int arg) const
   break;
 
case CS_OPCODE_CS_TERMINATE:
+   case SHADER_OPCODE_BARRIER:
   return 1;
 
default:
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 8b61c86..b85b52b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1045,12 +1045,14 @@ fs_visitor::emit_barrier()
 
fs_reg payload = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
 
+   const fs_builder pbld = bld.exec_all().group(8, 0);
+
/* Clear the message payload */
-   bld.exec_all().MOV(payload, fs_reg(0u));
+   pbld.MOV(payload, fs_reg(0u));
 
/* Copy bits 27:24 of r0.2 (barrier id) to the message payload reg.2 */
fs_reg r0_2 = fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD));
-   bld.exec_all().AND(component(payload, 2), r0_2, fs_reg(0x0f00u));
+   pbld.AND(component(payload, 2), r0_2, fs_reg(0x0f00u));
 
/* Emit a gateway "barrier" message using the payload we set up, followed
 * by a wait instruction.

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Mesa (master): nir/builder: Use a normal temporary array in nir_channel

2015-09-15 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: cb503c322754dd9dba016e703cf8b30177ed157b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb503c322754dd9dba016e703cf8b30177ed157b

Author: Jason Ekstrand 
Date:   Tue Sep 15 12:09:06 2015 -0700

nir/builder: Use a normal temporary array in nir_channel

C++ gets cranky if we take references of temporaries.  This isn't a problem
yet in master because nir_builder is never used from C++.  However, it will
be in the future so we should fix it now.

Reviewed-by: Rob Clark 

---

 src/glsl/nir/nir_builder.h |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/glsl/nir/nir_builder.h b/src/glsl/nir/nir_builder.h
index cf50f69..44134cf 100644
--- a/src/glsl/nir/nir_builder.h
+++ b/src/glsl/nir/nir_builder.h
@@ -219,7 +219,8 @@ nir_swizzle(nir_builder *build, nir_ssa_def *src, unsigned 
swiz[4],
 static inline nir_ssa_def *
 nir_channel(nir_builder *b, nir_ssa_def *def, int c)
 {
-   return nir_swizzle(b, def, (unsigned[4]){c, c, c, c}, 1, false);
+   unsigned swizzle[4] = {c, c, c, c};
+   return nir_swizzle(b, def, swizzle, 1, false);
 }
 
 /**

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Mesa (master): docs: document INTEL_DEBUG 'optimizer' envvar

2015-09-15 Thread Samuel Iglesias Gonsálvez 
Module: Mesa
Branch: master
Commit: a26e82b81dc3cebf13c8fd418d87977f2ab2dbb5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a26e82b81dc3cebf13c8fd418d87977f2ab2dbb5

Author: Alejandro Piñeiro 
Date:   Mon Sep 14 20:16:25 2015 +0200

docs: document INTEL_DEBUG 'optimizer' envvar

Reviewed-by: Matt Turner 

---

 docs/envvars.html |1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/envvars.html b/docs/envvars.html
index c0d5a51..bdfe999 100644
--- a/docs/envvars.html
+++ b/docs/envvars.html
@@ -153,6 +153,7 @@ See the Xlib software driver 
page for details.
no16 - suppress generation of 16-wide fragment shaders. useful for 
debugging broken shaders
blorp - emit messages about the blorp operations (blits  
clears)
nodualobj - suppress generation of dual-object geometry shader code
+   optimizer - dump shader assembly to files at each optimization pass and 
iteration that make progress
 
 
 

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Mesa (master): i965/fs: Set output_components for lowered clip distance outputs

2015-09-15 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: f55836f5671de5381a609c8d45601e2a92c803ce
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f55836f5671de5381a609c8d45601e2a92c803ce

Author: Jason Ekstrand 
Date:   Mon Sep 14 15:09:00 2015 -0700

i965/fs: Set output_components for lowered clip distance outputs

Reviewed-by: Kristian Høgsberg 

---

 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 5cb794b..cea16e0 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -840,7 +840,9 @@ void fs_visitor::compute_clip_distance(gl_clip_plane 
*clip_planes)
const fs_builder abld = bld.annotate("user clip distances");
 
this->outputs[VARYING_SLOT_CLIP_DIST0] = vgrf(glsl_type::vec4_type);
+   this->output_components[VARYING_SLOT_CLIP_DIST0] = 4;
this->outputs[VARYING_SLOT_CLIP_DIST1] = vgrf(glsl_type::vec4_type);
+   this->output_components[VARYING_SLOT_CLIP_DIST1] = 4;
 
for (int i = 0; i < key->nr_userclip_plane_consts; i++) {
   fs_reg u = userplane[i];

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Mesa (master): i965/fs: Only read output_components many components when writing an output

2015-09-15 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: 51824000541d8df9f870cbe0823a3835c9403bff
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=51824000541d8df9f870cbe0823a3835c9403bff

Author: Jason Ekstrand 
Date:   Mon Sep 14 14:18:13 2015 -0700

i965/fs: Only read output_components many components when writing an output

Reviewed-by: Kristian Høgsberg 

---

 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index cea16e0..8b61c86 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -974,8 +974,10 @@ fs_visitor::emit_urb_writes()
sources[length++] = reg;
 }
  } else {
-for (int i = 0; i < 4; i++)
+for (int i = 0; i < output_components[varying]; i++)
sources[length++] = offset(this->outputs[varying], bld, i);
+for (int i = output_components[varying]; i < 4; i++)
+   sources[length++] = fs_reg(0);
  }
  break;
   }

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Mesa (master): i965/fs_surface_builder: Only apply predicate to components that exist

2015-09-15 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: 0c6df7a1cb59336aed660e90be0c6aca4591
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c6df7a1cb59336aed660e90be0c6aca4591

Author: Jason Ekstrand 
Date:   Mon Sep 14 15:36:24 2015 -0700

i965/fs_surface_builder: Only apply predicate to components that exist

In certain conditions, we have to do bounds-checking in the shader for
image_load_store.  The way this works for image loads is that we do a
predicated load and then emit a series of selects, one per component,
that gives us 0 or the loaded value depending on whether or not you're
in bounds.  However, we were hard-coding 4 components which may not be
correct.  Instead, we should be using size which is the number of
components read.

Reviewed-by: Francisco Jerez 

---

 src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp
index 727e8d1..88f22fa 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp
@@ -905,7 +905,7 @@ namespace brw {
 tmp = emit_untyped_read(bld, image, laddr, 1, size, pred);
 
 /* An out of bounds surface access should give zero as result. */
-for (unsigned c = 0; c < 4; ++c)
+for (unsigned c = 0; c < size; ++c)
set_predicate(pred, bld.SEL(offset(tmp, bld, c),
offset(tmp, bld, c), fs_reg(0)));
  }

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Mesa (master): i965/fs: Add a very basic validation pass

2015-09-15 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: cadd7dd384b33a779d46bd664f456bed4a21a5b7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cadd7dd384b33a779d46bd664f456bed4a21a5b7

Author: Jason Ekstrand 
Date:   Thu Jul  2 15:41:02 2015 -0700

i965/fs: Add a very basic validation pass

Currently the validation pass only validates that regs_read and
regs_written are consistent with the sizes of VGRF's.  We can add more as
we find it to be useful.

Reviewed-by: Matt Turner 

---

 src/mesa/drivers/dri/i965/Makefile.sources|1 +
 src/mesa/drivers/dri/i965/brw_fs.cpp  |   10 +
 src/mesa/drivers/dri/i965/brw_fs.h|1 +
 src/mesa/drivers/dri/i965/brw_fs_validate.cpp |   57 +
 4 files changed, 69 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index b53802c..2ef392a 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -62,6 +62,7 @@ i965_FILES = \
brw_fs_sel_peephole.cpp \
brw_fs_surface_builder.cpp \
brw_fs_surface_builder.h \
+   brw_fs_validate.cpp \
brw_fs_vector_splitting.cpp \
brw_fs_visitor.cpp \
brw_gs.c \
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index b9f1051..63bee0a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -4781,6 +4781,9 @@ fs_visitor::calculate_register_pressure()
 void
 fs_visitor::optimize()
 {
+   /* Start by validating the shader we currently have. */
+   validate();
+
/* bld is the common builder object pointing at the end of the program we
 * used to translate it into i965 IR.  For the optimization and lowering
 * passes coming next, any code added after the end of the program without
@@ -4797,7 +4800,10 @@ fs_visitor::optimize()
assign_constant_locations();
demote_pull_constants();
 
+   validate();
+
split_virtual_grfs();
+   validate();
 
 #define OPT(pass, args...) ({   \
   pass_num++;   \
@@ -4811,6 +4817,8 @@ fs_visitor::optimize()
  backend_shader::dump_instructions(filename);   \
   } \
 \
+  validate();   \
+\
   progress = progress || this_progress; \
   this_progress;\
})
@@ -4872,6 +4880,8 @@ fs_visitor::optimize()
OPT(lower_integer_multiplication);
 
lower_uniform_pull_constant_loads();
+
+   validate();
 }
 
 /**
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
b/src/mesa/drivers/dri/i965/brw_fs.h
index 5880f69..1886dd8 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -151,6 +151,7 @@ public:
void invalidate_live_intervals();
void calculate_live_intervals();
void calculate_register_pressure();
+   void validate();
bool opt_algebraic();
bool opt_redundant_discard_jumps();
bool opt_cse();
diff --git a/src/mesa/drivers/dri/i965/brw_fs_validate.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_validate.cpp
new file mode 100644
index 000..d0e04f3
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_fs_validate.cpp
@@ -0,0 +1,57 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+/** @file brw_fs_validate.cpp
+ *
+ * Implements a pass that validates various invariants of the IR.  The current
+ * pass only validates that GRF's uses are sane.

Mesa (master): gallium/svga: Enable PIPE_FORMAT_L8_UNORM for vgpu10

2015-09-15 Thread Thomas Hellstrom 
Module: Mesa
Branch: master
Commit: edfb7ed1099cc8b6bebc2f1cb0b7b71bdcdbedeb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=edfb7ed1099cc8b6bebc2f1cb0b7b71bdcdbedeb

Author: Thomas Hellstrom 
Date:   Mon Sep 14 23:40:07 2015 -0700

gallium/svga: Enable PIPE_FORMAT_L8_UNORM for vgpu10

It's extensively used by XA for a8- and planar yuv component surfaces.
This fixes broken XA yuv blits using vgpu10 contexts.

Signed-off-by: Thomas Hellstrom 
Reviewed-by: Brian Paul 

---

 src/gallium/drivers/svga/svga_format.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/svga/svga_format.c 
b/src/gallium/drivers/svga/svga_format.c
index 67f6e51..28b8064 100644
--- a/src/gallium/drivers/svga/svga_format.c
+++ b/src/gallium/drivers/svga/svga_format.c
@@ -56,7 +56,7 @@ static const struct vgpu10_format_entry 
format_conversion_table[] =
{ PIPE_FORMAT_B4G4R4A4_UNORM,SVGA3D_FORMAT_INVALID,  
SVGA3D_A4R4G4B4, 0 },
{ PIPE_FORMAT_B5G6R5_UNORM,  SVGA3D_FORMAT_INVALID,  
SVGA3D_B5G6R5_UNORM, 0 },
{ PIPE_FORMAT_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM,   
SVGA3D_R10G10B10A2_UNORM,0 },
-   { PIPE_FORMAT_L8_UNORM,  SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },
+   { PIPE_FORMAT_L8_UNORM,  SVGA3D_FORMAT_INVALID,  
SVGA3D_LUMINANCE8,   0 },
{ PIPE_FORMAT_A8_UNORM,  SVGA3D_FORMAT_INVALID,  
SVGA3D_A8_UNORM, 0 },
{ PIPE_FORMAT_I8_UNORM,  SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },
{ PIPE_FORMAT_L8A8_UNORM,SVGA3D_FORMAT_INVALID,  
SVGA3D_FORMAT_INVALID,   0 },

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Mesa (master): egl/dri2/drm: compact existing device mgmt

2015-09-15 Thread Emil Velikov 
Module: Mesa
Branch: master
Commit: bd5bcb5b8ca043a3908d7a70ab1193efc1db278d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd5bcb5b8ca043a3908d7a70ab1193efc1db278d

Author: Emil Velikov 
Date:   Mon Sep  7 09:53:53 2015 +0100

egl/dri2/drm: compact existing device mgmt

Move the fcntl(dupfd_cloexec) to the else branch where it belongs.
Otherwise it's not immediately obvious that the code is hit, only when
an existing device is used.

Signed-off-by: Emil Velikov 
Reviewed-by: Boyan Ding 

---

 src/egl/drivers/dri2/platform_drm.c |   10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_drm.c 
b/src/egl/drivers/dri2/platform_drm.c
index 7e97280..050c309 100644
--- a/src/egl/drivers/dri2/platform_drm.c
+++ b/src/egl/drivers/dri2/platform_drm.c
@@ -624,6 +624,10 @@ dri2_initialize_drm(_EGLDriver *drv, _EGLDisplay *disp)
   gbm = gbm_create_device(fd);
   if (gbm == NULL)
  goto cleanup;
+   } else {
+  fd = fcntl(gbm_device_get_fd(gbm), F_DUPFD_CLOEXEC, 3);
+  if (fd < 0)
+ goto cleanup;
}
 
if (strcmp(gbm_device_get_backend_name(gbm), "drm") != 0)
@@ -633,12 +637,6 @@ dri2_initialize_drm(_EGLDriver *drv, _EGLDisplay *disp)
if (dri2_dpy->gbm_dri->base.type != GBM_DRM_DRIVER_TYPE_DRI)
   goto cleanup;
 
-   if (fd < 0) {
-  fd = fcntl(gbm_device_get_fd(gbm), F_DUPFD_CLOEXEC, 3);
-  if (fd < 0)
- goto cleanup;
-   }
-
dri2_dpy->fd = fd;
dri2_dpy->device_name = loader_get_device_name_for_fd(dri2_dpy->fd);
dri2_dpy->driver_name = strdup(dri2_dpy->gbm_dri->base.driver_name);

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Mesa (master): gbm: convert gbm bo format to fourcc format on dma-buf import

2015-09-15 Thread Emil Velikov 
Module: Mesa
Branch: master
Commit: 4bf151e66279da00655cec02aadb52c9c6583213
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4bf151e66279da00655cec02aadb52c9c6583213

Author: Ray Strode 
Date:   Fri Aug 28 14:50:21 2015 -0400

gbm: convert gbm bo format to fourcc format on dma-buf import

At the moment if a gbm buffer is imported and the gbm buffer
has an old-style GBM_BO_FORMAT format, the import will crash,
since it's passed directly to DRI functions that expect
a fourcc format (as provided by the newer GBM_FORMAT
definitions)

This commit addresses the problem in two ways:

1) it prevents invalid formats from leading to a crash by
returning EINVAL if the image couldn't be created

2) it translates GBM_BO_FORMAT formats into the comparable
GBM_FORMAT formats.

Reference: https://bugzilla.gnome.org/show_bug.cgi?id=753531
CC: "10.6 11.0" 
Reviewed-by: Emil Velikov 
Reviewed-by: Kristian Høgsberg 

---

 src/gbm/backends/dri/gbm_dri.c |   18 +-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/src/gbm/backends/dri/gbm_dri.c b/src/gbm/backends/dri/gbm_dri.c
index ccc3cc6..57cdeac 100644
--- a/src/gbm/backends/dri/gbm_dri.c
+++ b/src/gbm/backends/dri/gbm_dri.c
@@ -706,14 +706,30 @@ gbm_dri_bo_import(struct gbm_device *gbm,
{
   struct gbm_import_fd_data *fd_data = buffer;
   int stride = fd_data->stride, offset = 0;
+  int dri_format;
+
+  switch (fd_data->format) {
+  case GBM_BO_FORMAT_XRGB:
+ dri_format = GBM_FORMAT_XRGB;
+ break;
+  case GBM_BO_FORMAT_ARGB:
+ dri_format = GBM_FORMAT_ARGB;
+ break;
+  default:
+ dri_format = fd_data->format;
+  }
 
   image = dri->image->createImageFromFds(dri->screen,
  fd_data->width,
  fd_data->height,
- fd_data->format,
+ dri_format,
  _data->fd, 1,
  , ,
  NULL);
+  if (image == NULL) {
+ errno = EINVAL;
+ return NULL;
+  }
   gbm_format = fd_data->format;
   break;
}

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Mesa (master): mesa/extensions: restrict luminance alpha formats to API_OPENGL_COMPAT

2015-09-15 Thread Nanley Chery 
Module: Mesa
Branch: master
Commit: fe796a18319d791f3ed3865761452474b1c0477f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fe796a18319d791f3ed3865761452474b1c0477f

Author: Nanley Chery 
Date:   Thu Aug 27 16:05:22 2015 -0700

mesa/extensions: restrict luminance alpha formats to API_OPENGL_COMPAT

According the GL 3.1 spec, luminance alpha formats are deprecated.

Reviewed-by: Anuj Phogat 
Signed-off-by: Nanley Chery 

---

 src/mesa/main/extensions.c |4 ++--
 src/mesa/main/teximage.c   |6 --
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index 1f7d542..b2c88c3 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
@@ -263,7 +263,7 @@ static const struct extension extension_table[] = {
{ "GL_EXT_texture_compression_dxt1",
o(ANGLE_texture_compression_dxt),   GL | ES1 | ES2, 2004 },
{ "GL_ANGLE_texture_compression_dxt3",  
o(ANGLE_texture_compression_dxt),   GL | ES1 | ES2, 2011 },
{ "GL_ANGLE_texture_compression_dxt5",  
o(ANGLE_texture_compression_dxt),   GL | ES1 | ES2, 2011 },
-   { "GL_EXT_texture_compression_latc",
o(EXT_texture_compression_latc),GL, 2006 },
+   { "GL_EXT_texture_compression_latc",
o(EXT_texture_compression_latc),GLL,2006 },
{ "GL_EXT_texture_compression_rgtc",
o(ARB_texture_compression_rgtc),GL, 2004 },
{ "GL_EXT_texture_compression_s3tc",
o(EXT_texture_compression_s3tc),GL, 2000 },
{ "GL_EXT_texture_cube_map",o(ARB_texture_cube_map),
GLL,2001 },
@@ -366,7 +366,7 @@ static const struct extension extension_table[] = {
{ "GL_ATI_draw_buffers",o(dummy_true),  
GLL,2002 },
{ "GL_ATI_fragment_shader", o(ATI_fragment_shader), 
GLL,2001 },
{ "GL_ATI_separate_stencil",o(ATI_separate_stencil),
GLL,2006 },
-   { "GL_ATI_texture_compression_3dc", 
o(ATI_texture_compression_3dc), GL, 2004 },
+   { "GL_ATI_texture_compression_3dc", 
o(ATI_texture_compression_3dc), GLL,2004 },
{ "GL_ATI_texture_env_combine3",
o(ATI_texture_env_combine3),GLL,2002 },
{ "GL_ATI_texture_float",   o(ARB_texture_float),   
GL, 2002 },
{ "GL_ATI_texture_mirror_once", o(ATI_texture_mirror_once), 
GL, 2006 },
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index bfb0858..ff844cd 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -534,7 +534,8 @@ _mesa_base_tex_format( struct gl_context *ctx, GLint 
internalFormat )
   }
}
 
-   if (ctx->Extensions.EXT_texture_compression_latc) {
+   if (ctx->API == API_OPENGL_COMPAT &&
+   ctx->Extensions.EXT_texture_compression_latc) {
   switch (internalFormat) {
   case GL_COMPRESSED_LUMINANCE_LATC1_EXT:
   case GL_COMPRESSED_SIGNED_LUMINANCE_LATC1_EXT:
@@ -547,7 +548,8 @@ _mesa_base_tex_format( struct gl_context *ctx, GLint 
internalFormat )
   }
}
 
-   if (ctx->Extensions.ATI_texture_compression_3dc) {
+   if (ctx->API == API_OPENGL_COMPAT &&
+   ctx->Extensions.ATI_texture_compression_3dc) {
   switch (internalFormat) {
   case GL_COMPRESSED_LUMINANCE_ALPHA_3DC_ATI:
  return GL_LUMINANCE_ALPHA;

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Mesa (master): mesa/teximage: restrict GL_ETC1_RGB8_OES support to GLES

2015-09-15 Thread Nanley Chery 
Module: Mesa
Branch: master
Commit: 82007936491d5fb99cdc5ea18c076e8a896a4a1e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=82007936491d5fb99cdc5ea18c076e8a896a4a1e

Author: Nanley Chery 
Date:   Thu Aug 27 16:05:22 2015 -0700

mesa/teximage: restrict GL_ETC1_RGB8_OES support to GLES

According to the extensions table and our glext headers,
OES_compressed_ETC1_RGB8_texture is only supported in
GLES1 and GLES2. Since we may give users a GLES3 context
when a GLES2 context is requested, we also allow this
extension for GLES3 as well.

Reviewed-by: Anuj Phogat 
Signed-off-by: Nanley Chery 

---

 src/mesa/main/teximage.c |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index ff844cd..2a4d29d 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -558,7 +558,8 @@ _mesa_base_tex_format( struct gl_context *ctx, GLint 
internalFormat )
   }
}
 
-   if (ctx->Extensions.OES_compressed_ETC1_RGB8_texture) {
+   if (_mesa_is_gles(ctx) &&
+  ctx->Extensions.OES_compressed_ETC1_RGB8_texture) {
   switch (internalFormat) {
   case GL_ETC1_RGB8_OES:
  return GL_RGB;

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Mesa (master): mesa/extensions: restrict GL_OES_EGL_image to GLES

2015-09-15 Thread Nanley Chery 
Module: Mesa
Branch: master
Commit: 48961fa3ba37999a6f8fd812458b735e39604a95
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=48961fa3ba37999a6f8fd812458b735e39604a95

Author: Nanley Chery 
Date:   Thu Sep 10 10:48:46 2015 -0700

mesa/extensions: restrict GL_OES_EGL_image to GLES

Driver vendors do this as well. The extension specification
lists GLES 1.1 or 2.0 as requirements.

Reviewed-by: Chad Versace 
Signed-off-by: Nanley Chery 

---

 src/mesa/main/extensions.c |3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index b2c88c3..767c50e 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
@@ -307,8 +307,7 @@ static const struct extension extension_table[] = {
{ "GL_OES_depth_texture_cube_map",  
o(OES_depth_texture_cube_map), ES2, 2012 },
{ "GL_OES_draw_texture",o(OES_draw_texture),
 ES1,   2004 },
{ "GL_OES_EGL_sync",o(dummy_true),  
 ES1 | ES2, 2010 },
-   /*  FIXME: Mesa expects GL_OES_EGL_image to be available in OpenGL 
contexts. */
-   { "GL_OES_EGL_image",   o(OES_EGL_image),   
GL | ES1 | ES2, 2006 },
+   { "GL_OES_EGL_image",   o(OES_EGL_image),   
 ES1 | ES2, 2006 },
{ "GL_OES_EGL_image_external",  o(OES_EGL_image_external),  
 ES1 | ES2, 2010 },
{ "GL_OES_element_index_uint",  o(dummy_true),  
 ES1 | ES2, 2005 },
{ "GL_OES_fbo_render_mipmap",   o(dummy_true),  
 ES1 | ES2, 2005 },

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Mesa (master): nir/lower_vec_to_movs: Coalesce movs on-the-fly when possible

2015-09-15 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: 2458ea95c5676807a064f24ec720f12506975402
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2458ea95c5676807a064f24ec720f12506975402

Author: Jason Ekstrand 
Date:   Wed Sep  9 14:40:06 2015 -0700

nir/lower_vec_to_movs: Coalesce movs on-the-fly when possible

The old pass blindly inserted a bunch of moves into the shader with no
concern for whether or not it was really needed.  This adds code to try and
coalesce into the destination of the instruction providing the value.

Shader-db results for vec4 shaders on Haswell:

   total instructions in shared programs: 1754420 -> 1747753 (-0.38%)
   instructions in affected programs: 231230 -> 224563 (-2.88%)
   helped:1017
   HURT:  2

This approach is heavily based on a different patch by Eduardo Lima Mitev
.  Eduardo's patch did this in a separate pass as opposed
to integrating it into nir_lower_vec_to_movs.

Reviewed-by: Eduardo Lima Mitev 

---

 src/glsl/nir/nir_lower_vec_to_movs.c |   85 ++
 1 file changed, 85 insertions(+)

diff --git a/src/glsl/nir/nir_lower_vec_to_movs.c 
b/src/glsl/nir/nir_lower_vec_to_movs.c
index 29dd0ca..9ff86ea 100644
--- a/src/glsl/nir/nir_lower_vec_to_movs.c
+++ b/src/glsl/nir/nir_lower_vec_to_movs.c
@@ -79,6 +79,88 @@ insert_mov(nir_alu_instr *vec, unsigned start_idx, 
nir_shader *shader)
return mov->dest.write_mask;
 }
 
+/* Attempts to coalesce the "move" from the given source of the vec to the
+ * destination of the instruction generating the value. If, for whatever
+ * reason, we cannot coalesce the mmove, it does nothing and returns 0.  We
+ * can then call insert_mov as normal.
+ */
+static unsigned
+try_coalesce(nir_alu_instr *vec, unsigned start_idx, nir_shader *shader)
+{
+   assert(start_idx < nir_op_infos[vec->op].num_inputs);
+
+   /* We will only even try if the source is SSA */
+   if (!vec->src[start_idx].src.is_ssa)
+  return 0;
+
+   assert(vec->src[start_idx].src.ssa);
+
+   /* If we are going to do a reswizzle, then the vecN operation must be the
+* only use of the source value.  We also can't have any source modifiers.
+*/
+   nir_foreach_use(vec->src[start_idx].src.ssa, src) {
+  if (src->parent_instr != >instr)
+ return 0;
+
+  nir_alu_src *alu_src = exec_node_data(nir_alu_src, src, src);
+  if (alu_src->abs || alu_src->negate)
+ return 0;
+   }
+
+   if (!list_empty(>src[start_idx].src.ssa->if_uses))
+  return 0;
+
+   if (vec->src[start_idx].src.ssa->parent_instr->type != nir_instr_type_alu)
+  return 0;
+
+   nir_alu_instr *src_alu =
+  nir_instr_as_alu(vec->src[start_idx].src.ssa->parent_instr);
+
+   /* We only care about being able to re-swizzle the instruction if it is
+* something that we can reswizzle.  It must be per-component.
+*/
+   if (nir_op_infos[src_alu->op].output_size != 0)
+  return 0;
+
+   /* If we are going to reswizzle the instruction, we can't have any
+* non-per-component sources either.
+*/
+   for (unsigned j = 0; j < nir_op_infos[src_alu->op].num_inputs; j++)
+  if (nir_op_infos[src_alu->op].input_sizes[j] != 0)
+ return 0;
+
+   /* Stash off all of the ALU instruction's swizzles. */
+   uint8_t swizzles[4][4];
+   for (unsigned j = 0; j < nir_op_infos[src_alu->op].num_inputs; j++)
+  for (unsigned i = 0; i < 4; i++)
+ swizzles[j][i] = src_alu->src[j].swizzle[i];
+
+   unsigned write_mask = 0;
+   for (unsigned i = start_idx; i < 4; i++) {
+  if (!(vec->dest.write_mask & (1 << i)))
+ continue;
+
+  if (!vec->src[i].src.is_ssa ||
+  vec->src[i].src.ssa != _alu->dest.dest.ssa)
+ continue;
+
+  /* At this point, the give vec source matchese up with the ALU
+   * instruction so we can re-swizzle that component to match.
+   */
+  write_mask |= 1 << i;
+  for (unsigned j = 0; j < nir_op_infos[src_alu->op].num_inputs; j++)
+ src_alu->src[j].swizzle[i] = swizzles[j][vec->src[i].swizzle[0]];
+
+  /* Clear the no longer needed vec source */
+  nir_instr_rewrite_src(>instr, >src[i].src, NIR_SRC_INIT);
+   }
+
+   nir_instr_rewrite_dest(_alu->instr, _alu->dest.dest, 
vec->dest.dest);
+   src_alu->dest.write_mask = write_mask;
+
+   return write_mask;
+}
+
 static bool
 lower_vec_to_movs_block(nir_block *block, void *void_impl)
 {
@@ -133,6 +215,9 @@ lower_vec_to_movs_block(nir_block *block, void *void_impl)
 continue;
 
  if (!(finished_write_mask & (1 << i)))
+finished_write_mask |= try_coalesce(vec, i, shader);
+
+ if (!(finished_write_mask & (1 << i)))
 finished_write_mask |= insert_mov(vec, i, shader);
   }
 

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Mesa (master): nir: Add a fdot instruction that replicates the result to a vec4

2015-09-15 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: 47739c7df430664c3a998163a1e8a4a5e1901691
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=47739c7df430664c3a998163a1e8a4a5e1901691

Author: Jason Ekstrand 
Date:   Thu Sep 10 10:51:46 2015 -0700

nir: Add a fdot instruction that replicates the result to a vec4

Fortunately, nir_constant_expr already auto-splats if "dst" never shows up
in the constant expression field so we don't need to do anything there.

Reviewed-by: Connor Abbott 
Reviewed-by: Eduardo Lima Mitev 

---

 src/glsl/nir/nir.h|6 ++
 src/glsl/nir/nir_opcodes.py   |3 +++
 src/glsl/nir/nir_opt_algebraic.py |3 +++
 3 files changed, 12 insertions(+)

diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 3f693b1..4e4543a 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -1434,6 +1434,12 @@ typedef struct nir_shader_compiler_options {
/* lower {slt,sge,seq,sne} to {flt,fge,feq,fne} + b2f: */
bool lower_scmp;
 
+   /* Does the native fdot instruction replicate its result for four
+* components?  If so, then opt_algebraic_late will turn all fdotN
+* instructions into fdot_replicatedN instructions.
+*/
+   bool fdot_replicates;
+
/**
 * Does the driver support real 32-bit integers?  (Otherwise, integers
 * are simulated by floats.)
diff --git a/src/glsl/nir/nir_opcodes.py b/src/glsl/nir/nir_opcodes.py
index df5b7e2..495d109 100644
--- a/src/glsl/nir/nir_opcodes.py
+++ b/src/glsl/nir/nir_opcodes.py
@@ -453,6 +453,9 @@ binop("fxor", tfloat, commutative,
 binop_reduce("fdot", 1, tfloat, tfloat, "{src0} * {src1}", "{src0} + {src1}",
  "{src}")
 
+binop_reduce("fdot_replicated", 4, tfloat, tfloat,
+ "{src0} * {src1}", "{src0} + {src1}", "{src}")
+
 binop("fmin", tfloat, "", "fminf(src0, src1)")
 binop("imin", tint, commutative + associative, "src1 > src0 ? src0 : src1")
 binop("umin", tunsigned, commutative + associative, "src1 > src0 ? src0 : 
src1")
diff --git a/src/glsl/nir/nir_opt_algebraic.py 
b/src/glsl/nir/nir_opt_algebraic.py
index 226e0a8..acc3b04 100644
--- a/src/glsl/nir/nir_opt_algebraic.py
+++ b/src/glsl/nir/nir_opt_algebraic.py
@@ -240,6 +240,9 @@ late_optimizations = [
(('fge', ('fadd', a, b), 0.0), ('fge', a, ('fneg', b))),
(('feq', ('fadd', a, b), 0.0), ('feq', a, ('fneg', b))),
(('fne', ('fadd', a, b), 0.0), ('fne', a, ('fneg', b))),
+   (('fdot2', a, b), ('fdot_replicated2', a, b), 'options->fdot_replicates'),
+   (('fdot3', a, b), ('fdot_replicated3', a, b), 'options->fdot_replicates'),
+   (('fdot4', a, b), ('fdot_replicated4', a, b), 'options->fdot_replicates'),
 ]
 
 print nir_algebraic.AlgebraicPass("nir_opt_algebraic", optimizations).render()

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Mesa (master): nir/lower_vec_to_movs: Get rid of start_idx and swizzle compacting

2015-09-15 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: 2b2f1f16a04dfba4e02a7f331befb5bd94d4a1be
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b2f1f16a04dfba4e02a7f331befb5bd94d4a1be

Author: Jason Ekstrand 
Date:   Wed Sep  9 14:47:28 2015 -0700

nir/lower_vec_to_movs: Get rid of start_idx and swizzle compacting

Previously, we did this thing with keeping track of a separate start_idx
which was different from the iteration variable.  I think this was a relic
of the way that GLSL IR implements writemasks.  In NIR, if a given bit in
the writemask is unset then that channel is just "unused", not missing.  In
particular, a vec4 operation with a writemask of 0xd will use sources 0, 2,
and 3 and leave source 1 alone.  We can simplify things a good deal (and
make them correct) by removing this "compacting" step.

Reviewed-by: Eduardo Lima Mitev 
Reviewed-by: Eric Anholt 

---

 src/glsl/nir/nir_lower_vec_to_movs.c |   33 +
 1 file changed, 13 insertions(+), 20 deletions(-)

diff --git a/src/glsl/nir/nir_lower_vec_to_movs.c 
b/src/glsl/nir/nir_lower_vec_to_movs.c
index 993a108..29dd0ca 100644
--- a/src/glsl/nir/nir_lower_vec_to_movs.c
+++ b/src/glsl/nir/nir_lower_vec_to_movs.c
@@ -53,29 +53,25 @@ src_matches_dest_reg(nir_dest *dest, nir_src *src)
  * which ones have been processed.
  */
 static unsigned
-insert_mov(nir_alu_instr *vec, unsigned start_channel,
-   unsigned start_src_idx, nir_shader *shader)
+insert_mov(nir_alu_instr *vec, unsigned start_idx, nir_shader *shader)
 {
-   unsigned src_idx = start_src_idx;
-   assert(src_idx < nir_op_infos[vec->op].num_inputs);
+   assert(start_idx < nir_op_infos[vec->op].num_inputs);
 
nir_alu_instr *mov = nir_alu_instr_create(shader, nir_op_imov);
-   nir_alu_src_copy(>src[0], >src[src_idx], mov);
+   nir_alu_src_copy(>src[0], >src[start_idx], mov);
nir_alu_dest_copy(>dest, >dest, mov);
 
-   mov->dest.write_mask = (1u << start_channel);
-   mov->src[0].swizzle[start_channel] = vec->src[src_idx].swizzle[0];
-   src_idx++;
+   mov->dest.write_mask = (1u << start_idx);
+   mov->src[0].swizzle[start_idx] = vec->src[start_idx].swizzle[0];
 
-   for (unsigned i = start_channel + 1; i < 4; i++) {
+   for (unsigned i = start_idx + 1; i < 4; i++) {
   if (!(vec->dest.write_mask & (1 << i)))
  continue;
 
-  if (nir_srcs_equal(vec->src[src_idx].src, vec->src[start_src_idx].src)) {
+  if (nir_srcs_equal(vec->src[i].src, vec->src[start_idx].src)) {
  mov->dest.write_mask |= (1 << i);
- mov->src[0].swizzle[i] = vec->src[src_idx].swizzle[0];
+ mov->src[0].swizzle[i] = vec->src[i].swizzle[0];
   }
-  src_idx++;
}
 
nir_instr_insert_before(>instr, >instr);
@@ -121,26 +117,23 @@ lower_vec_to_movs_block(nir_block *block, void *void_impl)
* destination reg, in case other values we're populating in the dest
* might overwrite them.
*/
-  for (unsigned i = 0, src_idx = 0; i < 4; i++) {
+  for (unsigned i = 0; i < 4; i++) {
  if (!(vec->dest.write_mask & (1 << i)))
 continue;
 
- if (src_matches_dest_reg(>dest.dest, >src[src_idx].src)) {
-finished_write_mask |= insert_mov(vec, i, src_idx, shader);
+ if (src_matches_dest_reg(>dest.dest, >src[i].src)) {
+finished_write_mask |= insert_mov(vec, i, shader);
 break;
  }
- src_idx++;
   }
 
   /* Now, emit MOVs for all the other src channels. */
-  for (unsigned i = 0, src_idx = 0; i < 4; i++) {
+  for (unsigned i = 0; i < 4; i++) {
  if (!(vec->dest.write_mask & (1 << i)))
 continue;
 
  if (!(finished_write_mask & (1 << i)))
-finished_write_mask |= insert_mov(vec, i, src_idx, shader);
-
- src_idx++;
+finished_write_mask |= insert_mov(vec, i, shader);
   }
 
   nir_instr_remove(>instr);

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Mesa (master): nir/lower_vec_to_movs: Handle partially SSA shaders

2015-09-15 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: c3f8cde964f9850c86469a06d5eedf4e783cbf5c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c3f8cde964f9850c86469a06d5eedf4e783cbf5c

Author: Jason Ekstrand 
Date:   Wed Sep  9 13:42:14 2015 -0700

nir/lower_vec_to_movs: Handle partially SSA shaders

v2 (Jason Ekstrand):
 - Use nir_instr_rewrite_dest
 - Pass the impl directly into lower_vec_to_movs_block

Reviewed-by: Eduardo Lima Mitev 

---

 src/glsl/nir/nir_lower_vec_to_movs.c |   21 +++--
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/src/glsl/nir/nir_lower_vec_to_movs.c 
b/src/glsl/nir/nir_lower_vec_to_movs.c
index 25a6f7d..993a108 100644
--- a/src/glsl/nir/nir_lower_vec_to_movs.c
+++ b/src/glsl/nir/nir_lower_vec_to_movs.c
@@ -84,8 +84,11 @@ insert_mov(nir_alu_instr *vec, unsigned start_channel,
 }
 
 static bool
-lower_vec_to_movs_block(nir_block *block, void *shader)
+lower_vec_to_movs_block(nir_block *block, void *void_impl)
 {
+   nir_function_impl *impl = void_impl;
+   nir_shader *shader = impl->overload->function->shader;
+
nir_foreach_instr_safe(block, instr) {
   if (instr->type != nir_instr_type_alu)
  continue;
@@ -101,8 +104,16 @@ lower_vec_to_movs_block(nir_block *block, void *shader)
  continue; /* The loop */
   }
 
-  /* Since we insert multiple MOVs, we have to be non-SSA. */
-  assert(!vec->dest.dest.is_ssa);
+  if (vec->dest.dest.is_ssa) {
+ /* Since we insert multiple MOVs, we have a register destination. */
+ nir_register *reg = nir_local_reg_create(impl);
+ reg->num_components = vec->dest.dest.ssa.num_components;
+
+ nir_ssa_def_rewrite_uses(>dest.dest.ssa, nir_src_for_reg(reg));
+
+ nir_instr_rewrite_dest(>instr, >dest.dest,
+nir_dest_for_reg(reg));
+  }
 
   unsigned finished_write_mask = 0;
 
@@ -142,9 +153,7 @@ lower_vec_to_movs_block(nir_block *block, void *shader)
 static void
 nir_lower_vec_to_movs_impl(nir_function_impl *impl)
 {
-   nir_shader *shader = impl->overload->function->shader;
-
-   nir_foreach_block(impl, lower_vec_to_movs_block, shader);
+   nir_foreach_block(impl, lower_vec_to_movs_block, impl);
 }
 
 void

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Mesa (master): i965/vec4_nir: Use partial SSA form rather than full non-SSA

2015-09-15 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: c951bb83056724df02ba7e6fe2dfa720c0f45c1f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c951bb83056724df02ba7e6fe2dfa720c0f45c1f

Author: Jason Ekstrand 
Date:   Wed Sep  9 13:55:39 2015 -0700

i965/vec4_nir: Use partial SSA form rather than full non-SSA

We made this switch in the FS backend some time ago and it seems to make a
number of things a bit easier.  In particular, supporting SSA values takes
very little work in the backend and allows us to take advantage of the
majority of the SSA information even after we've gotten rid of Phi nodes.

Reviewed-by: Eduardo Lima Mitev 

---

 src/mesa/drivers/dri/i965/brw_nir.c|2 +-
 src/mesa/drivers/dri/i965/brw_vec4.h   |1 +
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp |   21 ++---
 3 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_nir.c 
b/src/mesa/drivers/dri/i965/brw_nir.c
index 8f3edc5..f326b23 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -183,7 +183,7 @@ brw_create_nir(struct brw_context *brw,
   nir_print_shader(nir, stderr);
}
 
-   nir_convert_from_ssa(nir, is_scalar);
+   nir_convert_from_ssa(nir, true);
nir_validate_shader(nir);
 
if (!is_scalar) {
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 01c6e84..de74ec9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -423,6 +423,7 @@ public:
virtual void nir_emit_alu(nir_alu_instr *instr);
virtual void nir_emit_jump(nir_jump_instr *instr);
virtual void nir_emit_texture(nir_tex_instr *instr);
+   virtual void nir_emit_undef(nir_ssa_undef_instr *instr);
 
dst_reg get_nir_dest(nir_dest dest, enum brw_reg_type type);
dst_reg get_nir_dest(nir_dest dest, nir_alu_type type);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 175d92b..144f9e5 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -367,6 +367,10 @@ vec4_visitor::nir_emit_instr(nir_instr *instr)
   nir_emit_texture(nir_instr_as_tex(instr));
   break;
 
+   case nir_instr_type_ssa_undef:
+  nir_emit_undef(nir_instr_as_ssa_undef(instr));
+  break;
+
default:
   fprintf(stderr, "VS instruction not yet implemented by NIR->vec4\n");
   break;
@@ -393,9 +397,14 @@ dst_reg_for_nir_reg(vec4_visitor *v, nir_register *nir_reg,
 dst_reg
 vec4_visitor::get_nir_dest(nir_dest dest)
 {
-   assert(!dest.is_ssa);
-   return dst_reg_for_nir_reg(this, dest.reg.reg, dest.reg.base_offset,
-  dest.reg.indirect);
+   if (dest.is_ssa) {
+  dst_reg dst = dst_reg(GRF, alloc.allocate(1));
+  nir_ssa_values[dest.ssa.index] = dst;
+  return dst;
+   } else {
+  return dst_reg_for_nir_reg(this, dest.reg.reg, dest.reg.base_offset,
+ dest.reg.indirect);
+   }
 }
 
 dst_reg
@@ -1529,4 +1538,10 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
 mcs, is_cube_array, sampler, sampler_reg);
 }
 
+void
+vec4_visitor::nir_emit_undef(nir_ssa_undef_instr *instr)
+{
+   nir_ssa_values[instr->def.index] = dst_reg(GRF, alloc.allocate(1));
+}
+
 }

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Mesa (master): i965/vec4: Use the replicated fdot instruction in NIR

2015-09-15 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: a88ce0c1c4c1f77209b71d5a6858f952642f385a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a88ce0c1c4c1f77209b71d5a6858f952642f385a

Author: Jason Ekstrand 
Date:   Thu Sep 10 11:08:15 2015 -0700

i965/vec4: Use the replicated fdot instruction in NIR

Reviewed-by: Connor Abbott 
Reviewed-by: Eduardo Lima Mitev 

---

 src/mesa/drivers/dri/i965/brw_shader.cpp   |8 
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp |6 +++---
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp 
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index cf9aa23..eed73fb 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -96,6 +96,14 @@ brw_compiler_create(void *mem_ctx, const struct 
brw_device_info *devinfo)
 */
nir_options->lower_ffma = true;
nir_options->lower_sub = true;
+   /* In the vec4 backend, our dpN instruction replicates its result to all
+* the components of a vec4.  We would like NIR to give us replicated fdot
+* instructions because it can optimize better for us.
+*
+* For the FS backend, it should be lowered away by the scalarizing pass so
+* we should never see fdot anyway.
+*/
+   nir_options->fdot_replicates = true;
 
/* We want the GLSL compiler to emit code that uses condition codes */
for (int i = 0; i < MESA_SHADER_STAGES; i++) {
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 144f9e5..482fce2 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -1254,17 +1254,17 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
   inst->predicate = BRW_PREDICATE_NORMAL;
   break;
 
-   case nir_op_fdot2:
+   case nir_op_fdot_replicated2:
   inst = emit(BRW_OPCODE_DP2, dst, op[0], op[1]);
   inst->saturate = instr->dest.saturate;
   break;
 
-   case nir_op_fdot3:
+   case nir_op_fdot_replicated3:
   inst = emit(BRW_OPCODE_DP3, dst, op[0], op[1]);
   inst->saturate = instr->dest.saturate;
   break;
 
-   case nir_op_fdot4:
+   case nir_op_fdot_replicated4:
   inst = emit(BRW_OPCODE_DP4, dst, op[0], op[1]);
   inst->saturate = instr->dest.saturate;
   break;

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Mesa (master): nir/lower_vec_to_movs: Coalesce into destinations of fdot instructions

2015-09-15 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: 29348631fe7bf732a38856ea842cfc7aa2263468
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=29348631fe7bf732a38856ea842cfc7aa2263468

Author: Jason Ekstrand 
Date:   Wed Sep  9 17:18:55 2015 -0700

nir/lower_vec_to_movs: Coalesce into destinations of fdot instructions

Now that we have a replicating fdot instruction, we can actually coalesce
into the destinations of vec4 instructions.  We couldn't really do this
before because, if the destination had to end up in .z, we couldn't
reswizzle the instruction.  With a replicated destination, the result ends
up in all channels so we can just set the writemask and we're done.

Shader-db results for vec4 programs on Haswell:

   total instructions in shared programs: 1747753 -> 1746280 (-0.08%)
   instructions in affected programs: 143274 -> 141801 (-1.03%)
   helped:667
   HURT:  0

It turns out that dot-products matter...

Reviewed-by: Eduardo Lima Mitev 

---

 src/glsl/nir/nir_lower_vec_to_movs.c |   49 +-
 1 file changed, 36 insertions(+), 13 deletions(-)

diff --git a/src/glsl/nir/nir_lower_vec_to_movs.c 
b/src/glsl/nir/nir_lower_vec_to_movs.c
index 9ff86ea..2cb0457 100644
--- a/src/glsl/nir/nir_lower_vec_to_movs.c
+++ b/src/glsl/nir/nir_lower_vec_to_movs.c
@@ -79,6 +79,14 @@ insert_mov(nir_alu_instr *vec, unsigned start_idx, 
nir_shader *shader)
return mov->dest.write_mask;
 }
 
+static bool
+has_replicated_dest(nir_alu_instr *alu)
+{
+   return alu->op == nir_op_fdot_replicated2 ||
+  alu->op == nir_op_fdot_replicated3 ||
+  alu->op == nir_op_fdot_replicated4;
+}
+
 /* Attempts to coalesce the "move" from the given source of the vec to the
  * destination of the instruction generating the value. If, for whatever
  * reason, we cannot coalesce the mmove, it does nothing and returns 0.  We
@@ -116,19 +124,28 @@ try_coalesce(nir_alu_instr *vec, unsigned start_idx, 
nir_shader *shader)
nir_alu_instr *src_alu =
   nir_instr_as_alu(vec->src[start_idx].src.ssa->parent_instr);
 
-   /* We only care about being able to re-swizzle the instruction if it is
-* something that we can reswizzle.  It must be per-component.
-*/
-   if (nir_op_infos[src_alu->op].output_size != 0)
-  return 0;
-
-   /* If we are going to reswizzle the instruction, we can't have any
-* non-per-component sources either.
-*/
-   for (unsigned j = 0; j < nir_op_infos[src_alu->op].num_inputs; j++)
-  if (nir_op_infos[src_alu->op].input_sizes[j] != 0)
+   if (has_replicated_dest(src_alu)) {
+  /* The fdot instruction is special: It replicates its result to all
+   * components.  This means that we can always rewrite its destination
+   * and we don't need to swizzle anything.
+   */
+   } else {
+  /* We only care about being able to re-swizzle the instruction if it is
+   * something that we can reswizzle.  It must be per-component.  The one
+   * exception to this is the fdotN instructions which implicitly splat
+   * their result out to all channels.
+   */
+  if (nir_op_infos[src_alu->op].output_size != 0)
  return 0;
 
+  /* If we are going to reswizzle the instruction, we can't have any
+   * non-per-component sources either.
+   */
+  for (unsigned j = 0; j < nir_op_infos[src_alu->op].num_inputs; j++)
+ if (nir_op_infos[src_alu->op].input_sizes[j] != 0)
+return 0;
+   }
+
/* Stash off all of the ALU instruction's swizzles. */
uint8_t swizzles[4][4];
for (unsigned j = 0; j < nir_op_infos[src_alu->op].num_inputs; j++)
@@ -148,8 +165,14 @@ try_coalesce(nir_alu_instr *vec, unsigned start_idx, 
nir_shader *shader)
* instruction so we can re-swizzle that component to match.
*/
   write_mask |= 1 << i;
-  for (unsigned j = 0; j < nir_op_infos[src_alu->op].num_inputs; j++)
- src_alu->src[j].swizzle[i] = swizzles[j][vec->src[i].swizzle[0]];
+  if (has_replicated_dest(src_alu)) {
+ /* Since the destination is a single replicated value, we don't need
+  * to do any reswizzling
+  */
+  } else {
+ for (unsigned j = 0; j < nir_op_infos[src_alu->op].num_inputs; j++)
+src_alu->src[j].swizzle[i] = swizzles[j][vec->src[i].swizzle[0]];
+  }
 
   /* Clear the no longer needed vec source */
   nir_instr_rewrite_src(>instr, >src[i].src, NIR_SRC_INIT);

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Mesa (master): nir/lower_vec_to_movs: Pass the shader around directly

2015-09-15 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: b7eeced3c724bf5de05290551ced8621ce2c7c52
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7eeced3c724bf5de05290551ced8621ce2c7c52

Author: Jason Ekstrand 
Date:   Wed Sep  9 12:58:58 2015 -0700

nir/lower_vec_to_movs: Pass the shader around directly

Previously, we were passing the shader around, we were just calling it
"mem_ctx".  However, the nir_shader is (and must be for the purposes of
mark-and-sweep) the mem_ctx so we might as well pass it around explicitly.

Reviewed-by: Eduardo Lima Mitev 

---

 src/glsl/nir/nir_lower_vec_to_movs.c |   14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/glsl/nir/nir_lower_vec_to_movs.c 
b/src/glsl/nir/nir_lower_vec_to_movs.c
index b7f096d..25a6f7d 100644
--- a/src/glsl/nir/nir_lower_vec_to_movs.c
+++ b/src/glsl/nir/nir_lower_vec_to_movs.c
@@ -54,12 +54,12 @@ src_matches_dest_reg(nir_dest *dest, nir_src *src)
  */
 static unsigned
 insert_mov(nir_alu_instr *vec, unsigned start_channel,
-unsigned start_src_idx, void *mem_ctx)
+   unsigned start_src_idx, nir_shader *shader)
 {
unsigned src_idx = start_src_idx;
assert(src_idx < nir_op_infos[vec->op].num_inputs);
 
-   nir_alu_instr *mov = nir_alu_instr_create(mem_ctx, nir_op_imov);
+   nir_alu_instr *mov = nir_alu_instr_create(shader, nir_op_imov);
nir_alu_src_copy(>src[0], >src[src_idx], mov);
nir_alu_dest_copy(>dest, >dest, mov);
 
@@ -84,7 +84,7 @@ insert_mov(nir_alu_instr *vec, unsigned start_channel,
 }
 
 static bool
-lower_vec_to_movs_block(nir_block *block, void *mem_ctx)
+lower_vec_to_movs_block(nir_block *block, void *shader)
 {
nir_foreach_instr_safe(block, instr) {
   if (instr->type != nir_instr_type_alu)
@@ -115,7 +115,7 @@ lower_vec_to_movs_block(nir_block *block, void *mem_ctx)
 continue;
 
  if (src_matches_dest_reg(>dest.dest, >src[src_idx].src)) {
-finished_write_mask |= insert_mov(vec, i, src_idx, mem_ctx);
+finished_write_mask |= insert_mov(vec, i, src_idx, shader);
 break;
  }
  src_idx++;
@@ -127,7 +127,7 @@ lower_vec_to_movs_block(nir_block *block, void *mem_ctx)
 continue;
 
  if (!(finished_write_mask & (1 << i)))
-finished_write_mask |= insert_mov(vec, i, src_idx, mem_ctx);
+finished_write_mask |= insert_mov(vec, i, src_idx, shader);
 
  src_idx++;
   }
@@ -142,7 +142,9 @@ lower_vec_to_movs_block(nir_block *block, void *mem_ctx)
 static void
 nir_lower_vec_to_movs_impl(nir_function_impl *impl)
 {
-   nir_foreach_block(impl, lower_vec_to_movs_block, ralloc_parent(impl));
+   nir_shader *shader = impl->overload->function->shader;
+
+   nir_foreach_block(impl, lower_vec_to_movs_block, shader);
 }
 
 void

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Mesa (master): freedreno/a4xx: more texture formats

2015-09-15 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: 18385bc3ac867bf7fb4070fe0f90bdf8e3e515a4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=18385bc3ac867bf7fb4070fe0f90bdf8e3e515a4

Author: Rob Clark 
Date:   Mon Sep 14 15:15:06 2015 -0400

freedreno/a4xx: more texture formats

Signed-off-by: Rob Clark 

---

 src/gallium/drivers/freedreno/a4xx/fd4_format.c |   15 ---
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_format.c 
b/src/gallium/drivers/freedreno/a4xx/fd4_format.c
index 6c9e217..847d4fb 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_format.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_format.c
@@ -89,13 +89,14 @@ static struct fd4_format formats[PIPE_FORMAT_COUNT] = {
_T(L8_UNORM,   8_UNORM, R8_UNORM, WZYX),
_T(I8_UNORM,   8_UNORM, NONE, WZYX),
 
-   /* NOTE: should be TFMT_8_UINT (which then gets remapped to
-* TFMT_8_UNORM for mem2gmem in _gmem_restore_format()), but
-* we don't know TFMT_8_UINT yet.. so just use TFMT_8_UNORM
-* for now.. sampling from stencil as a texture might not
-* work right, but at least should be fine for zsbuf..
-*/
-   _T(S8_UINT,8_UNORM,  R8_UNORM, WZYX),
+   _T(A8_UINT,8_UINT,  NONE, WZYX),
+   _T(A8_SINT,8_SINT,  NONE, WZYX),
+   _T(L8_UINT,8_UINT,  NONE, WZYX),
+   _T(L8_SINT,8_SINT,  NONE, WZYX),
+   _T(I8_UINT,8_UINT,  NONE, WZYX),
+   _T(I8_SINT,8_SINT,  NONE, WZYX),
+
+   _T(S8_UINT,8_UINT,  R8_UNORM, WZYX),
 
/* 16-bit */
V_(R16_UNORM,   16_UNORM, NONE, WZYX),

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Mesa (master): freedreno/a4xx: wire up texture clamp lowering

2015-09-15 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: f8222724f539b9e16affc0f4ddd95cfda27293a5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f8222724f539b9e16affc0f4ddd95cfda27293a5

Author: Rob Clark 
Date:   Tue Sep 15 17:25:25 2015 -0400

freedreno/a4xx: wire up texture clamp lowering

Signed-off-by: Rob Clark 

---

 src/gallium/drivers/freedreno/a4xx/fd4_texture.c |   99 +-
 src/gallium/drivers/freedreno/a4xx/fd4_texture.h |1 +
 2 files changed, 80 insertions(+), 20 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_texture.c 
b/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
index 213b29c..5ee022b 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
@@ -35,32 +35,31 @@
 #include "fd4_texture.h"
 #include "fd4_format.h"
 
-/* TODO do we need to emulate clamp-to-edge like a3xx? */
 static enum a4xx_tex_clamp
-tex_clamp(unsigned wrap)
+tex_clamp(unsigned wrap, bool clamp_to_edge)
 {
-   /* hardware probably supports more, but we can't coax all the
-* wrap/clamp modes out of the GLESv2 blob driver.
-*
-* TODO once we have basics working, go back and just try
-* different values and see what happens
-*/
+   /* Hardware does not support _CLAMP, but we emulate it: */
+   if (wrap == PIPE_TEX_WRAP_CLAMP) {
+   wrap = (clamp_to_edge) ?
+   PIPE_TEX_WRAP_CLAMP_TO_EDGE : 
PIPE_TEX_WRAP_CLAMP_TO_BORDER;
+   }
+
switch (wrap) {
case PIPE_TEX_WRAP_REPEAT:
return A4XX_TEX_REPEAT;
-   case PIPE_TEX_WRAP_CLAMP:
case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
return A4XX_TEX_CLAMP_TO_EDGE;
-   case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
-// TODO
-// return A4XX_TEX_CLAMP_TO_BORDER;
-   case PIPE_TEX_WRAP_MIRROR_CLAMP:
-   case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
-// TODO
-// return A4XX_TEX_MIRROR_CLAMP;
+   /* only works for PoT.. need to emulate otherwise! */
+   return A4XX_TEX_MIRROR_CLAMP;
case PIPE_TEX_WRAP_MIRROR_REPEAT:
return A4XX_TEX_MIRROR_REPEAT;
+   case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
+   case PIPE_TEX_WRAP_MIRROR_CLAMP:
+   case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
+   /* these two we could perhaps emulate, but we currently
+* just don't advertise PIPE_CAP_TEXTURE_MIRROR_CLAMP
+*/
default:
DBG("invalid wrap: %u", wrap);
return 0;
@@ -88,6 +87,7 @@ fd4_sampler_state_create(struct pipe_context *pctx,
struct fd4_sampler_stateobj *so = CALLOC_STRUCT(fd4_sampler_stateobj);
unsigned aniso = util_last_bit(MIN2(cso->max_anisotropy >> 1, 8));
bool miplinear = false;
+   bool clamp_to_edge;
 
if (!so)
return NULL;
@@ -97,14 +97,29 @@ fd4_sampler_state_create(struct pipe_context *pctx,
 
so->base = *cso;
 
+   /*
+* For nearest filtering, _CLAMP means _CLAMP_TO_EDGE;  for linear
+* filtering, _CLAMP means _CLAMP_TO_BORDER while additionally
+* clamping the texture coordinates to [0.0, 1.0].
+*
+* The clamping will be taken care of in the shaders.  There are two
+* filters here, but let the minification one has a say.
+*/
+   clamp_to_edge = (cso->min_img_filter == PIPE_TEX_FILTER_NEAREST);
+   if (!clamp_to_edge) {
+   so->saturate_s = (cso->wrap_s == PIPE_TEX_WRAP_CLAMP);
+   so->saturate_t = (cso->wrap_t == PIPE_TEX_WRAP_CLAMP);
+   so->saturate_r = (cso->wrap_r == PIPE_TEX_WRAP_CLAMP);
+   }
+
so->texsamp0 =
COND(miplinear, A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR) |
A4XX_TEX_SAMP_0_XY_MAG(tex_filter(cso->mag_img_filter, aniso)) |
A4XX_TEX_SAMP_0_XY_MIN(tex_filter(cso->min_img_filter, aniso)) |
A4XX_TEX_SAMP_0_ANISO(aniso) |
-   A4XX_TEX_SAMP_0_WRAP_S(tex_clamp(cso->wrap_s)) |
-   A4XX_TEX_SAMP_0_WRAP_T(tex_clamp(cso->wrap_t)) |
-   A4XX_TEX_SAMP_0_WRAP_R(tex_clamp(cso->wrap_r));
+   A4XX_TEX_SAMP_0_WRAP_S(tex_clamp(cso->wrap_s, clamp_to_edge)) |
+   A4XX_TEX_SAMP_0_WRAP_T(tex_clamp(cso->wrap_t, clamp_to_edge)) |
+   A4XX_TEX_SAMP_0_WRAP_R(tex_clamp(cso->wrap_r, clamp_to_edge));
 
so->texsamp1 =
 // COND(miplinear, A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR) |
@@ -122,6 +137,50 @@ fd4_sampler_state_create(struct pipe_context *pctx,
return so;
 }
 
+static void
+fd4_sampler_states_bind(struct pipe_context *pctx,
+   unsigned shader, unsigned start,
+   unsigned nr, void **hwcso)
+{
+   struct fd_context *ctx = fd_context(pctx);
+   struct fd4_context

Mesa (master): freedreno: helper for a3xx/a4xx border-colors

2015-09-15 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: 9124a49d54af5d7bd8230af4ba3eebfb167a7655
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9124a49d54af5d7bd8230af4ba3eebfb167a7655

Author: Rob Clark 
Date:   Tue Sep 15 09:23:21 2015 -0400

freedreno: helper for a3xx/a4xx border-colors

Both use the same layout for the buffer containing border-color values,
so rather than duplicating the logic in a4xx, split it out into a
helper.

Signed-off-by: Rob Clark 

---

 src/gallium/drivers/freedreno/a3xx/fd3_context.h  |   16 -
 src/gallium/drivers/freedreno/a3xx/fd3_emit.c |   53 +
 src/gallium/drivers/freedreno/freedreno_texture.c |   66 +
 src/gallium/drivers/freedreno/freedreno_texture.h |   31 ++
 4 files changed, 99 insertions(+), 67 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_context.h 
b/src/gallium/drivers/freedreno/a3xx/fd3_context.h
index 250bcf8..b4c2ebe5 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_context.h
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_context.h
@@ -73,22 +73,6 @@ struct fd3_context {
 */
struct fd_vertex_state blit_vbuf_state;
 
-
-   /*
-* Border color layout *appears* to be as arrays of 0x40 byte
-* elements, with frag shader elements starting at (16 x 0x40).
-* But at some point I should probably experiment more with
-* samplers in vertex shaders to be sure.  Unclear about why
-* there is this offset when there are separate VS and FS base
-* addr regs.
-*
-* The first 8 bytes of each entry are the requested border
-* color in fp16.  Unclear about the rest.. could be used for
-* other formats, or could simply be for aligning the pitch
-* to 32 pixels.
-*/
-#define BORDERCOLOR_SIZE 0x40
-
struct u_upload_mgr *border_color_uploader;
struct pipe_resource *border_color_buf;
 
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c 
b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
index 6f514ed..b81bc5a 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
@@ -149,6 +149,8 @@ emit_textures(struct fd_context *ctx, struct fd_ringbuffer 
*ring,
_ctx->border_color_buf,
);
 
+   fd_setup_border_colors(tex, ptr, tex_off[sb]);
+
if (tex->num_samplers > 0) {
/* output sampler state: */
OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
@@ -163,57 +165,6 @@ emit_textures(struct fd_context *ctx, struct fd_ringbuffer 
*ring,
const struct fd3_sampler_stateobj *sampler = 
tex->samplers[i] ?
fd3_sampler_stateobj(tex->samplers[i]) :
_sampler;
-   uint16_t *bcolor = (uint16_t *)((uint8_t *)ptr +
-   (BORDERCOLOR_SIZE * tex_off[sb]) +
-   (BORDERCOLOR_SIZE * i));
-   uint32_t *bcolor32 = (uint32_t *)[16];
-
-   /*
-* XXX HACK ALERT XXX
-*
-* The border colors need to be swizzled in a particular
-* format-dependent order. Even though samplers don't 
know about
-* formats, we can assume that with a GL state tracker, 
there's a
-* 1:1 correspondence between sampler and texture. Take 
advantage
-* of that knowledge.
-*/
-   if (i < tex->num_textures && tex->textures[i]) {
-   const struct util_format_description *desc =
-   
util_format_description(tex->textures[i]->format);
-   for (j = 0; j < 4; j++) {
-   if (desc->swizzle[j] >= 4)
-   continue;
-
-   const struct 
util_format_channel_description *chan =
-   
>channel[desc->swizzle[j]];
-   int size = chan->size;
-
-   /* The Z16 texture format we use seems 
to look in the
-* 32-bit border color slots
-*/
-   if (desc->colorspace == 
UTIL_FORMAT_COLORSPACE_ZS)
-   size = 32;
-
-   /* Formats like R11G11B10 or RGB9_E5 
don't specify
-* per-channel sizes properly.
-*/
-   if

Mesa (master): freedreno: update generated headers

2015-09-15 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: 76977222af3dcf6c0915830c7b7af06505f8cd9a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=76977222af3dcf6c0915830c7b7af06505f8cd9a

Author: Rob Clark 
Date:   Mon Sep 14 16:59:36 2015 -0400

freedreno: update generated headers

Signed-off-by: Rob Clark 

---

 src/gallium/drivers/freedreno/a2xx/a2xx.xml.h |6 +++---
 src/gallium/drivers/freedreno/a3xx/a3xx.xml.h |   23 +
 src/gallium/drivers/freedreno/a4xx/a4xx.xml.h |9 
 src/gallium/drivers/freedreno/adreno_common.xml.h |   10 ++---
 src/gallium/drivers/freedreno/adreno_pm4.xml.h|6 +++---
 5 files changed, 37 insertions(+), 17 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h 
b/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
index dd48956..2853787 100644
--- a/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
+++ b/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
@@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from 
are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml   (
364 bytes, from 2015-05-20 20:03:07)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   
1453 bytes, from 2015-05-20 20:03:07)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml  (  
32901 bytes, from 2015-05-20 20:03:14)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  
10551 bytes, from 2015-05-20 20:03:14)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  
10755 bytes, from 2015-09-14 20:46:55)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml(  
14968 bytes, from 2015-05-20 20:12:27)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml  (  
67120 bytes, from 2015-08-14 23:22:03)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml  (  
63915 bytes, from 2015-08-24 16:56:28)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml  (  
67771 bytes, from 2015-09-14 20:46:55)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml  (  
63970 bytes, from 2015-09-14 20:50:12)
 
 Copyright (C) 2013-2015 by the following authors:
 - Rob Clark  (robclark)
diff --git a/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h 
b/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
index a157dc3..4bbcb33 100644
--- a/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
+++ b/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
@@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from 
are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml   (
364 bytes, from 2015-05-20 20:03:07)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   
1453 bytes, from 2015-05-20 20:03:07)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml  (  
32901 bytes, from 2015-05-20 20:03:14)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  
10551 bytes, from 2015-05-20 20:03:14)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  
10755 bytes, from 2015-09-14 20:46:55)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml(  
14968 bytes, from 2015-05-20 20:12:27)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml  (  
67120 bytes, from 2015-08-14 23:22:03)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml  (  
63915 bytes, from 2015-08-24 16:56:28)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml  (  
67771 bytes, from 2015-09-14 20:46:55)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml  (  
63970 bytes, from 2015-09-14 20:50:12)
 
 Copyright (C) 2013-2015 by the following authors:
 - Rob Clark  (robclark)
@@ -280,6 +280,8 @@ enum a3xx_rb_blend_opcode {
 enum a3xx_intp_mode {
SMOOTH = 0,
FLAT = 1,
+   ZERO = 2,
+   ONE = 3,
 };
 
 enum a3xx_repl_mode {
@@ -684,6 +686,12 @@ static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t 
i0) { return 0x0460
 #define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD  0x0080
 #define A3XX_GRAS_CL_CLIP_CNTL_WCOORD  0x0100
 #define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE   0x0200
+#define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK  0x1c00
+#define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT 26
+static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t 
val)
+{
+   return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & 
A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK;
+}
 
 #define REG_A3XX_GRAS_CL_GB_CLIP_ADJ   0x2044
 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK0x03ff
@@ -774,7 +782,7 @@ static inline uint32_t

Mesa (master): freedreno/a4xx: border-color support

2015-09-15 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: d85267c4bb5416dc3fbac7798b4bb68247340508
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d85267c4bb5416dc3fbac7798b4bb68247340508

Author: Rob Clark 
Date:   Tue Sep 15 17:25:47 2015 -0400

freedreno/a4xx: border-color support

Signed-off-by: Rob Clark 

---

 src/gallium/drivers/freedreno/a4xx/fd4_context.c |5 +
 src/gallium/drivers/freedreno/a4xx/fd4_context.h |5 +
 src/gallium/drivers/freedreno/a4xx/fd4_emit.c|   20 +++-
 src/gallium/drivers/freedreno/a4xx/fd4_texture.c |3 ++-
 4 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_context.c 
b/src/gallium/drivers/freedreno/a4xx/fd4_context.c
index 625512c..e53e0c5 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_context.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_context.c
@@ -55,6 +55,8 @@ fd4_context_destroy(struct pipe_context *pctx)
pipe_resource_reference(_ctx->solid_vbuf, NULL);
pipe_resource_reference(_ctx->blit_texcoord_vbuf, NULL);
 
+   u_upload_destroy(fd4_ctx->border_color_uploader);
+
fd_context_destroy(pctx);
 }
 
@@ -169,5 +171,8 @@ fd4_context_create(struct pipe_screen *pscreen, void *priv, 
unsigned flags)
 
fd4_query_context_init(pctx);
 
+   fd4_ctx->border_color_uploader = u_upload_create(pctx, 4096,
+   2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE, 0);
+
return pctx;
 }
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_context.h 
b/src/gallium/drivers/freedreno/a4xx/fd4_context.h
index af94756..074c5a7 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_context.h
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_context.h
@@ -29,6 +29,8 @@
 #ifndef FD4_CONTEXT_H_
 #define FD4_CONTEXT_H_
 
+#include "util/u_upload_mgr.h"
+
 #include "freedreno_drmif.h"
 
 #include "freedreno_context.h"
@@ -70,6 +72,9 @@ struct fd4_context {
 */
struct fd_vertex_state blit_vbuf_state;
 
+   struct u_upload_mgr *border_color_uploader;
+   struct pipe_resource *border_color_buf;
+
/* if *any* of bits are set in {v,f}saturate_{s,t,r} */
bool vsaturate, fsaturate;
 
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c 
b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
index b75be29..5f36cef 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
@@ -124,7 +124,20 @@ static void
 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
enum adreno_state_block sb, struct fd_texture_stateobj *tex)
 {
-   unsigned i;
+   static const uint32_t bcolor_reg[] = {
+   [SB_VERT_TEX] = 
REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
+   [SB_FRAG_TEX] = 
REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
+   };
+   struct fd4_context *fd4_ctx = fd4_context(ctx);
+   unsigned i, off;
+   void *ptr;
+
+   u_upload_alloc(fd4_ctx->border_color_uploader,
+   0, 2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE, ,
+   _ctx->border_color_buf,
+   );
+
+   fd_setup_border_colors(tex, ptr, 0);
 
if (tex->num_samplers > 0) {
int num_samplers;
@@ -190,6 +203,11 @@ emit_textures(struct fd_context *ctx, struct fd_ringbuffer 
*ring,
OUT_RING(ring, 0x);
}
}
+
+   OUT_PKT0(ring, bcolor_reg[sb], 1);
+   OUT_RELOC(ring, fd_resource(fd4_ctx->border_color_buf)->bo, off, 0, 0);
+
+   u_upload_unmap(fd4_ctx->border_color_uploader);
 }
 
 /* emit texture state for mem->gmem restore operation.. eventually it would
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_texture.c 
b/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
index 5ee022b..dbff5a7 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
@@ -49,12 +49,13 @@ tex_clamp(unsigned wrap, bool clamp_to_edge)
return A4XX_TEX_REPEAT;
case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
return A4XX_TEX_CLAMP_TO_EDGE;
+   case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
+   return A4XX_TEX_CLAMP_TO_BORDER;
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
/* only works for PoT.. need to emulate otherwise! */
return A4XX_TEX_MIRROR_CLAMP;
case PIPE_TEX_WRAP_MIRROR_REPEAT:
return A4XX_TEX_MIRROR_REPEAT;
-   case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
case PIPE_TEX_WRAP_MIRROR_CLAMP:
case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
/* these two we could perhaps emulate, but we currently

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Mesa (master): egl/dri2: don't leak the fd on dri2_terminate

2015-09-15 Thread Emil Velikov 
Module: Mesa
Branch: master
Commit: a1ac742f709089eabad59b4da484799091203d91
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1ac742f709089eabad59b4da484799091203d91

Author: Emil Velikov 
Date:   Thu Sep 10 14:41:38 2015 +0100

egl/dri2: don't leak the fd on dri2_terminate

Currently the check was incorrect as it did not consider the (unlikely)
case of fd == 0. In order to fix this we should first correctly
initialize it to -1, as the swrast implementations leave it set to zero
(props to calloc()).

Signed-off-by: Emil Velikov 
Reviewed-by: Boyan Ding 

---

 src/egl/drivers/dri2/egl_dri2.c |2 +-
 src/egl/drivers/dri2/platform_wayland.c |1 +
 src/egl/drivers/dri2/platform_x11.c |1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index eb56113..1740ee3 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -786,7 +786,7 @@ dri2_terminate(_EGLDriver *drv, _EGLDisplay *disp)
 
if (dri2_dpy->own_dri_screen)
   dri2_dpy->core->destroyScreen(dri2_dpy->dri_screen);
-   if (dri2_dpy->fd)
+   if (dri2_dpy->fd >= 0)
   close(dri2_dpy->fd);
if (dri2_dpy->driver)
   dlclose(dri2_dpy->driver);
diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index dbc64ba..6cf5461 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -1804,6 +1804,7 @@ dri2_initialize_wayland_swrast(_EGLDriver *drv, 
_EGLDisplay *disp)
if (roundtrip(dri2_dpy) < 0 || dri2_dpy->formats == 0)
   goto cleanup_shm;
 
+   dri2_dpy->fd = -1;
dri2_dpy->driver_name = strdup("swrast");
if (!dri2_load_driver_swrast(disp))
   goto cleanup_shm;
diff --git a/src/egl/drivers/dri2/platform_x11.c 
b/src/egl/drivers/dri2/platform_x11.c
index bf7d2be..7991fc2 100644
--- a/src/egl/drivers/dri2/platform_x11.c
+++ b/src/egl/drivers/dri2/platform_x11.c
@@ -1161,6 +1161,7 @@ dri2_initialize_x11_swrast(_EGLDriver *drv, _EGLDisplay 
*disp)
 * Every hardware driver_name is set using strdup. Doing the same in
 * here will allow is to simply free the memory at dri2_terminate().
 */
+   dri2_dpy->fd = -1;
dri2_dpy->driver_name = strdup("swrast");
if (!dri2_load_driver_swrast(disp))
   goto cleanup_conn;

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Mesa (master): egl/dri2: Close file descriptor on error.

2015-09-15 Thread Emil Velikov 
Module: Mesa
Branch: master
Commit: e4f0d26c8c3c092a09fb65184ab080de4e38373e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e4f0d26c8c3c092a09fb65184ab080de4e38373e

Author: Matt Turner 
Date:   Wed Jul 15 09:00:41 2015 -0700

egl/dri2: Close file descriptor on error.

v2: [Emil Velikov]
Rework the error path to a common goto, close only if we own the fd.
v3; [Emil Velikov]
Always close the fd (we either opened the device or dup'd) (Boyan, Ian)

Signed-off-by: Emil Velikov 
Reviewed-by: Boyan Ding 

---

 src/egl/drivers/dri2/platform_drm.c |   27 ++-
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_drm.c 
b/src/egl/drivers/dri2/platform_drm.c
index eda5087..7e97280 100644
--- a/src/egl/drivers/dri2/platform_drm.c
+++ b/src/egl/drivers/dri2/platform_drm.c
@@ -623,26 +623,20 @@ dri2_initialize_drm(_EGLDriver *drv, _EGLDisplay *disp)
   dri2_dpy->own_device = 1;
   gbm = gbm_create_device(fd);
   if (gbm == NULL)
- return EGL_FALSE;
+ goto cleanup;
}
 
-   if (strcmp(gbm_device_get_backend_name(gbm), "drm") != 0) {
-  free(dri2_dpy);
-  return EGL_FALSE;
-   }
+   if (strcmp(gbm_device_get_backend_name(gbm), "drm") != 0)
+  goto cleanup;
 
dri2_dpy->gbm_dri = gbm_dri_device(gbm);
-   if (dri2_dpy->gbm_dri->base.type != GBM_DRM_DRIVER_TYPE_DRI) {
-  free(dri2_dpy);
-  return EGL_FALSE;
-   }
+   if (dri2_dpy->gbm_dri->base.type != GBM_DRM_DRIVER_TYPE_DRI)
+  goto cleanup;
 
if (fd < 0) {
   fd = fcntl(gbm_device_get_fd(gbm), F_DUPFD_CLOEXEC, 3);
-  if (fd < 0) {
- free(dri2_dpy);
- return EGL_FALSE;
-  }
+  if (fd < 0)
+ goto cleanup;
}
 
dri2_dpy->fd = fd;
@@ -727,4 +721,11 @@ dri2_initialize_drm(_EGLDriver *drv, _EGLDisplay *disp)
dri2_dpy->vtbl = _drm_display_vtbl;
 
return EGL_TRUE;
+
+cleanup:
+   if (fd >= 0)
+  close(fd);
+
+   free(dri2_dpy);
+   return EGL_FALSE;
 }

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