Mesa (master): glsl: fix ir_constant::equals() for doubles

[Iago Toral Quiroga]

Module: Mesa
Branch: master
Commit: f1ba0a5ea0faf331be9fa28fd6d43a3ff061b735
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f1ba0a5ea0faf331be9fa28fd6d43a3ff061b735

Author: Connor Abbott 
Date:   Fri Aug 14 11:58:45 2015 -0700

glsl: fix ir_constant::equals() for doubles

Reviewed-by: Timothy Arceri 
Reviewed-by: Edward O'Callaghan 

---

 src/glsl/ir_equals.cpp |9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/glsl/ir_equals.cpp b/src/glsl/ir_equals.cpp
index 5f0785e..aafcd1f 100644
--- a/src/glsl/ir_equals.cpp
+++ b/src/glsl/ir_equals.cpp
@@ -58,8 +58,13 @@ ir_constant::equals(const ir_instruction *ir, enum 
ir_node_type) const
   return false;
 
for (unsigned i = 0; i < type->components(); i++) {
-  if (value.u[i] != other->value.u[i])
- return false;
+  if (type->base_type == GLSL_TYPE_DOUBLE) {
+ if (value.d[i] != other->value.d[i])
+return false;
+  } else {
+ if (value.u[i] != other->value.u[i])
+return false;
+  }
}
 
return true;

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Mesa (master): nir: fix constant folding of bfi

[Iago Toral Quiroga]

Module: Mesa
Branch: master
Commit: 7820b2c071ec974d824c9b6dc3a0dd0ad1b77444
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7820b2c071ec974d824c9b6dc3a0dd0ad1b77444

Author: Connor Abbott 
Date:   Tue Aug  4 14:04:34 2015 -0700

nir: fix constant folding of bfi

Reviewed-by: Edward O'Callaghan 

---

 src/glsl/nir/nir_opcodes.py |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/glsl/nir/nir_opcodes.py b/src/glsl/nir/nir_opcodes.py
index 3c0f1da..729f695 100644
--- a/src/glsl/nir/nir_opcodes.py
+++ b/src/glsl/nir/nir_opcodes.py
@@ -563,7 +563,7 @@ opcode("bcsel", 0, tunsigned, [0, 0, 0],
   [tbool, tunsigned, tunsigned], "", "src0 ? src1 : src2")
 
 triop("bfi", tunsigned, """
-unsigned mask = src0, insert = src1 & mask, base = src2;
+unsigned mask = src0, insert = src1, base = src2;
 if (mask == 0) {
dst = base;
 } else {
@@ -572,7 +572,7 @@ if (mask == 0) {
   tmp >>= 1;
   insert <<= 1;
}
-   dst = (base & ~mask) | insert;
+   dst = (base & ~mask) | (insert & mask);
 }
 """)
 

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Mesa (master): glsl: fix isinf() for doubles

[Iago Toral Quiroga]

Module: Mesa
Branch: master
Commit: 84ed3819a42042757a32cae4260c26c4fb3b673c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=84ed3819a42042757a32cae4260c26c4fb3b673c

Author: Connor Abbott 
Date:   Fri Aug 14 11:58:07 2015 -0700

glsl: fix isinf() for doubles

Reviewed-by: Timothy Arceri 
Reviewed-by: Edward O'Callaghan 

---

 src/glsl/builtin_functions.cpp |   11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index eb438d9..1824b83 100644
--- a/src/glsl/builtin_functions.cpp
+++ b/src/glsl/builtin_functions.cpp
@@ -3573,7 +3573,16 @@ builtin_builder::_isinf(builtin_available_predicate 
avail, const glsl_type *type
 
ir_constant_data infinities;
for (int i = 0; i < type->vector_elements; i++) {
-  infinities.f[i] = INFINITY;
+  switch (type->base_type) {
+  case GLSL_TYPE_FLOAT:
+ infinities.f[i] = INFINITY;
+ break;
+  case GLSL_TYPE_DOUBLE:
+ infinities.d[i] = INFINITY;
+ break;
+  default:
+ unreachable("unknown type");
+  }
}
 
body.emit(ret(equal(abs(x), imm(type, infinities;

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Mesa (master): mesa/extensions: Sort the extension table alphabetically

[Nanley Chery]

Module: Mesa
Branch: master
Commit: f030227f4643ae7e832545dfa3c3db472e00ab65
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f030227f4643ae7e832545dfa3c3db472e00ab65

Author: Nanley Chery 
Date:   Wed Nov 18 15:01:43 2015 -0800

mesa/extensions: Sort the extension table alphabetically

Make it easier to determine where to add new extensions.
Performed with the vim sort command.

v2: Insert newline after last #define (Matt)

Signed-off-by: Nanley Chery 
Reviewed-by: Matt Turner 

---

 src/mesa/main/extensions_table.h |  174 --
 1 file changed, 93 insertions(+), 81 deletions(-)

diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index 7b5cc7b..2075168 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -1,8 +1,31 @@
+/* The extension table is alphabetically sorted by the extension name string 
column. */
+
 #define GLL 0
 #define GLC 0
 #define ES1 0
 #define ES2 0
 #define  x ~0
+
+EXT(3DFX_texture_compression_FXT1   , TDFX_texture_compression_FXT1
  , GLL, GLC,  x ,  x , 1999)
+
+EXT(AMD_conservative_depth  , ARB_conservative_depth   
  , GLL, GLC,  x ,  x , 2009)
+EXT(AMD_draw_buffers_blend  , ARB_draw_buffers_blend   
  , GLL, GLC,  x ,  x , 2009)
+EXT(AMD_performance_monitor , AMD_performance_monitor  
  , GLL, GLC,  x ,  x , 2007)
+EXT(AMD_pinned_memory   , AMD_pinned_memory
  , GLL, GLC,  x ,  x , 2013)
+EXT(AMD_seamless_cubemap_per_texture, AMD_seamless_cubemap_per_texture 
  , GLL, GLC,  x ,  x , 2009)
+EXT(AMD_shader_stencil_export   , ARB_shader_stencil_export
  , GLL, GLC,  x ,  x , 2009)
+EXT(AMD_shader_trinary_minmax   , dummy_true   
  , GLL, GLC,  x ,  x , 2012)
+EXT(AMD_vertex_shader_layer , AMD_vertex_shader_layer  
  ,  x , GLC,  x ,  x , 2012)
+EXT(AMD_vertex_shader_viewport_index, AMD_vertex_shader_viewport_index 
  ,  x , GLC,  x ,  x , 2012)
+
+EXT(ANGLE_texture_compression_dxt3  , ANGLE_texture_compression_dxt
  , GLL, GLC, ES1, ES2, 2011)
+EXT(ANGLE_texture_compression_dxt5  , ANGLE_texture_compression_dxt
  , GLL, GLC, ES1, ES2, 2011)
+
+EXT(APPLE_object_purgeable  , APPLE_object_purgeable   
  , GLL, GLC,  x ,  x , 2006)
+EXT(APPLE_packed_pixels , dummy_true   
  , GLL,  x ,  x ,  x , 2002)
+EXT(APPLE_texture_max_level , dummy_true   
  ,  x ,  x , ES1, ES2, 2009)
+EXT(APPLE_vertex_array_object   , dummy_true   
  , GLL,  x ,  x ,  x , 2002)
+
 EXT(ARB_ES2_compatibility   , ARB_ES2_compatibility
  , GLL, GLC,  x ,  x , 2009)
 EXT(ARB_ES3_compatibility   , ARB_ES3_compatibility
  , GLL, GLC,  x ,  x , 2012)
 EXT(ARB_arrays_of_arrays, ARB_arrays_of_arrays 
  , GLL, GLC,  x ,  x , 2012)
@@ -16,9 +39,9 @@ EXT(ARB_color_buffer_float  , 
ARB_color_buffer_float
 EXT(ARB_compressed_texture_pixel_storage, dummy_true   
  , GLL, GLC,  x ,  x , 2011)
 EXT(ARB_compute_shader  , ARB_compute_shader   
  , GLL, GLC,  x ,  x , 2012)
 EXT(ARB_conditional_render_inverted , ARB_conditional_render_inverted  
  , GLL, GLC,  x ,  x , 2014)
+EXT(ARB_conservative_depth  , ARB_conservative_depth   
  , GLL, GLC,  x ,  x , 2011)
 EXT(ARB_copy_buffer , dummy_true   
  , GLL, GLC,  x ,  x , 2008)
 EXT(ARB_copy_image  , ARB_copy_image   
  , GLL, GLC,  x ,  x , 2012)
-EXT(ARB_conservative_depth  , ARB_conservative_depth   
  , GLL, GLC,  x ,  x , 2011)
 EXT(ARB_debug_output, dummy_true   
  , GLL, GLC,  x ,  x , 2009)
 EXT(ARB_depth_buffer_float  , ARB_depth_buffer_float   
  , GLL, GLC,  x ,  x , 2008)
 EXT(ARB_depth_clamp , ARB_depth_clamp  
  , GLL, GLC,  x ,  x , 2003)
@@ -56,8 +79,8 @@ EXT(ARB_multi_bind  , dummy_true
 EXT(ARB_multi_draw_indirect , ARB_draw_indirect
  ,  x , GLC,  x ,  x , 2012)
 EXT(ARB_multisample , dummy_true   
  , GLL,  x ,  x ,  x , 1994)
 EXT(ARB_multitexture, dummy_true   
  , GLL,  x ,  x ,  x , 1998)
-EXT(ARB_occlusion_query2, ARB_occlusion_query2   

Mesa (master): i965/vec4: Replace src_reg(imm) constructors with brw_imm_* ().

[Matt Turner]

Module: Mesa
Branch: master
Commit: f9a9ba5eac2f1934bd7fecc92cd309f22411164b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9a9ba5eac2f1934bd7fecc92cd309f22411164b

Author: Matt Turner 
Date:   Mon Nov  2 12:12:44 2015 -0800

i965/vec4: Replace src_reg(imm) constructors with brw_imm_*().

Cuts 1.5k of .text.

Reviewed-by: Emil Velikov 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_ir_vec4.h|5 --
 src/mesa/drivers/dri/i965/brw_vec4.cpp |   67 +++---
 src/mesa/drivers/dri/i965/brw_vec4_builder.h   |2 +-
 src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp  |   38 
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp |   78 
 .../drivers/dri/i965/brw_vec4_surface_builder.cpp  |8 +-
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |   94 ++--
 src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp  |   20 ++---
 src/mesa/drivers/dri/i965/gen6_gs_visitor.cpp  |   78 
 .../dri/i965/test_vec4_cmod_propagation.cpp|   38 
 .../dri/i965/test_vec4_copy_propagation.cpp|2 +-
 .../dri/i965/test_vec4_register_coalesce.cpp   |4 +-
 12 files changed, 195 insertions(+), 239 deletions(-)

Diff:   
http://cgit.freedesktop.org/mesa/mesa/diff/?id=f9a9ba5eac2f1934bd7fecc92cd309f22411164b
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Mesa (master): i965/fs: Use brw_imm_uw().

[Matt Turner]

Module: Mesa
Branch: master
Commit: 9b978046eb1d1657060365e8dcde4aad41b50af9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b978046eb1d1657060365e8dcde4aad41b50af9

Author: Matt Turner 
Date:   Mon Nov  2 11:28:35 2015 -0800

i965/fs: Use brw_imm_uw().

W/UW immediates are 16-bits, but those 16-bits must be replicated
in the high 16-bits of the 32-bit field.

Remove the useless W/UW immediate saturating code, since we'll now be
using the appropriate immediate (and W/UW immediates in the IR can now
no longer be larger than 16-bits).

Reviewed-by: Emil Velikov 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_fs_nir.cpp |3 +--
 src/mesa/drivers/dri/i965/brw_shader.cpp |8 ++--
 2 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 8364bbf..3394e4a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -454,8 +454,7 @@ fs_visitor::optimize_frontfacing_ternary(nir_alu_instr 
*instr,
   tmp.subreg_offset = 2;
   tmp.stride = 2;
 
-  fs_inst *or_inst = bld.OR(tmp, g0, brw_imm_d(0x3f80));
-  or_inst->src[1].type = BRW_REGISTER_TYPE_UW;
+  bld.OR(tmp, g0, brw_imm_uw(0x3f80));
 
   tmp.type = BRW_REGISTER_TYPE_D;
   tmp.subreg_offset = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp 
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index d221648..7a236cd 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -561,16 +561,12 @@ brw_saturate_immediate(enum brw_reg_type type, struct 
brw_reg *reg)
switch (type) {
case BRW_REGISTER_TYPE_UD:
case BRW_REGISTER_TYPE_D:
+   case BRW_REGISTER_TYPE_UW:
+   case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_UQ:
case BRW_REGISTER_TYPE_Q:
   /* Nothing to do. */
   return false;
-   case BRW_REGISTER_TYPE_UW:
-  sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
-  break;
-   case BRW_REGISTER_TYPE_W:
-  sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
-  break;
case BRW_REGISTER_TYPE_F:
   sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
   break;

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Mesa (master): i965: Make brw_imm_vf4() take 8-bit restricted floats.

[Matt Turner]

Module: Mesa
Branch: master
Commit: c15a407eb49d3b26bdbf039816636adb184c276a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c15a407eb49d3b26bdbf039816636adb184c276a

Author: Matt Turner 
Date:   Mon Nov  2 10:29:45 2015 -0800

i965: Make brw_imm_vf4() take 8-bit restricted floats.

This partially reverts commit bbf8239f92ecd79431dfa41402e1c85318e7267f.

I didn't like that commit to begin with -- computing things at compile
time is fine -- but for purposes of verifying that the resulting values
are correct, looking up 0x00 and 0x30 in a table is a lot better than
evaluating a recursive function.

Anyway, by making brw_imm_vf4() take the actual 8-bit restricted floats
directly (instead of only integral values that would be converted to
restricted float), we can use this function as a replacement for the
vector float src_reg/fs_reg constructors.

brw_float_to_vf() is not currently an inline function, so it will not be
evaluated at compile time. I'll address that in a follow-up patch.

Reviewed-by: Emil Velikov 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_clip_util.c |5 +++-
 src/mesa/drivers/dri/i965/brw_reg.h   |   38 ++---
 2 files changed, 11 insertions(+), 32 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c 
b/src/mesa/drivers/dri/i965/brw_clip_util.c
index 40ad144..73ba85e 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_util.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_util.c
@@ -224,7 +224,10 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
   vec1(t_nopersp),
   brw_imm_f(0));
   brw_IF(p, BRW_EXECUTE_1);
-  brw_MOV(p, t_nopersp, brw_imm_vf4(1, 0, 0, 0));
+  brw_MOV(p, t_nopersp, brw_imm_vf4(brw_float_to_vf(1.0),
+brw_float_to_vf(0.0),
+brw_float_to_vf(0.0),
+brw_float_to_vf(0.0)));
   brw_ENDIF(p);
 
   /* Now compute t_nopersp = t_nopersp.y/t_nopersp.x and broadcast it. */
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h 
b/src/mesa/drivers/dri/i965/brw_reg.h
index 3da83b4..e34e7ea 100644
--- a/src/mesa/drivers/dri/i965/brw_reg.h
+++ b/src/mesa/drivers/dri/i965/brw_reg.h
@@ -43,7 +43,6 @@
 #define BRW_REG_H
 
 #include 
-#include "main/imports.h"
 #include "main/compiler.h"
 #include "main/macros.h"
 #include "program/prog_instruction.h"
@@ -638,38 +637,15 @@ brw_imm_vf(unsigned v)
return imm;
 }
 
-/**
- * Convert an integer into a "restricted" 8-bit float, used in vector
- * immediates.  The 8-bit floating point format has a sign bit, an
- * excess-3 3-bit exponent, and a 4-bit mantissa.  All integer values
- * from -31 to 31 can be represented exactly.
- */
-static inline uint8_t
-int_to_float8(int x)
-{
-   if (x == 0) {
-  return 0;
-   } else if (x < 0) {
-  return 1 << 7 | int_to_float8(-x);
-   } else {
-  const unsigned exponent = _mesa_logbase2(x);
-  const unsigned mantissa = (x - (1 << exponent)) << (4 - exponent);
-  assert(exponent <= 4);
-  return (exponent + 3) << 4 | mantissa;
-   }
-}
-
-/**
- * Construct a floating-point packed vector immediate from its integer
- * values. \sa int_to_float8()
- */
 static inline struct brw_reg
-brw_imm_vf4(int v0, int v1, int v2, int v3)
+brw_imm_vf4(unsigned v0, unsigned v1, unsigned v2, unsigned v3)
 {
-   return brw_imm_vf((int_to_float8(v0) << 0) |
- (int_to_float8(v1) << 8) |
- (int_to_float8(v2) << 16) |
- (int_to_float8(v3) << 24));
+   struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
+   imm.vstride = BRW_VERTICAL_STRIDE_0;
+   imm.width = BRW_WIDTH_4;
+   imm.hstride = BRW_HORIZONTAL_STRIDE_1;
+   imm.ud = ((v0 << 0) | (v1 << 8) | (v2 << 16) | (v3 << 24));
+   return imm;
 }
 
 

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Mesa (master): mesa: Add test for sorted extension table

[Nanley Chery]

Module: Mesa
Branch: master
Commit: e8c5ef3ecaafae0ad6c300019c489401a9af714c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8c5ef3ecaafae0ad6c300019c489401a9af714c

Author: Nanley Chery 
Date:   Wed Nov 18 15:01:44 2015 -0800

mesa: Add test for sorted extension table

Enable developers to know if the table's alphabetical sorting
is maintained or lost.

v2: Move "*" next to pointer name (Matt)
Include extensions_table.h instead of extensions.h (Ian)
Remove extra " *" in comment (Ian)

Signed-off-by: Nanley Chery 
Reviewed-by: Matt Turner 

---

 src/mesa/main/tests/Makefile.am |1 +
 src/mesa/main/tests/mesa_extensions.cpp |   51 +++
 2 files changed, 52 insertions(+)

diff --git a/src/mesa/main/tests/Makefile.am b/src/mesa/main/tests/Makefile.am
index bd7ab73..d6977e2 100644
--- a/src/mesa/main/tests/Makefile.am
+++ b/src/mesa/main/tests/Makefile.am
@@ -27,6 +27,7 @@ AM_CPPFLAGS += -DHAVE_SHARED_GLAPI
 main_test_SOURCES +=   \
dispatch_sanity.cpp \
mesa_formats.cpp\
+   mesa_extensions.cpp \
program_state_string.cpp
 
 main_test_LDADD += \
diff --git a/src/mesa/main/tests/mesa_extensions.cpp 
b/src/mesa/main/tests/mesa_extensions.cpp
new file mode 100644
index 000..0c7addd
--- /dev/null
+++ b/src/mesa/main/tests/mesa_extensions.cpp
@@ -0,0 +1,51 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+ * \name mesa_extensions.cpp
+ *
+ * Verify that the extensions table is sorted.
+ */
+
+#include 
+#include "util/macros.h"
+
+/**
+ * Debug/test: verify the extension table is alphabetically sorted.
+ */
+TEST(MesaExtensionsTest, AlphabeticallySorted)
+{
+   const char *ext_names[] = {
+   #define EXT(name_str, ...) #name_str,
+   #include "main/extensions_table.h"
+   #undef EXT
+   };
+
+   for (unsigned i = 0; i < ARRAY_SIZE(ext_names) - 1; ++i) {
+  const char *current_str = ext_names[i];
+  const char *next_str = ext_names[i+1];
+
+  /* We expect the extension table to be alphabetically sorted */
+  ASSERT_LT(strcmp(current_str, next_str), 0);
+   }
+}

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Mesa (master): i965/fs: Replace fs_reg(imm) constructors with brw_imm_*().

[Matt Turner]

Module: Mesa
Branch: master
Commit: 3ccc41ecfc5e9345a1c291748d8840984f7413ae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ccc41ecfc5e9345a1c291748d8840984f7413ae

Author: Matt Turner 
Date:   Mon Nov  2 11:26:16 2015 -0800

i965/fs: Replace fs_reg(imm) constructors with brw_imm_*().

Cuts 10k of .text, of which only 776 bytes are the fs_reg constructor
implementations themselves.

   text data  bss  dec  hex  filename
5204535   21411227784  5446431   531b1f  i965_dri.so before
5193977   21411227784  5435873   52f1e1  i965_dri.so after

Reviewed-by: Emil Velikov 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp|2 +-
 src/mesa/drivers/dri/i965/brw_fs.cpp   |  100 -
 src/mesa/drivers/dri/i965/brw_fs_builder.h |4 +-
 .../drivers/dri/i965/brw_fs_combine_constants.cpp  |2 +-
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp   |  150 ++--
 .../drivers/dri/i965/brw_fs_surface_builder.cpp|   49 +++
 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp   |   42 +++---
 src/mesa/drivers/dri/i965/brw_ir_fs.h  |5 -
 .../drivers/dri/i965/test_fs_cmod_propagation.cpp  |   30 ++--
 9 files changed, 167 insertions(+), 217 deletions(-)

Diff:   
http://cgit.freedesktop.org/mesa/mesa/diff/?id=3ccc41ecfc5e9345a1c291748d8840984f7413ae
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Mesa (master): i965: Drop IMM fs_reg/src_reg -> brw_reg conversions.

[Matt Turner]

Module: Mesa
Branch: master
Commit: a5b3115f0a9ede775b332b1a669de570668e871c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5b3115f0a9ede775b332b1a669de570668e871c

Author: Matt Turner 
Date:   Mon Nov  2 12:25:24 2015 -0800

i965: Drop IMM fs_reg/src_reg -> brw_reg conversions.

The previous two commits make this unnecessary.

Reviewed-by: Emil Velikov 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_fs_generator.cpp |   32 +---
 src/mesa/drivers/dri/i965/brw_vec4.cpp |6 +
 2 files changed, 2 insertions(+), 36 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index e5a286a..77969c4 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -89,39 +89,9 @@ brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen)
   brw_reg.abs = reg->abs;
   brw_reg.negate = reg->negate;
   break;
-   case IMM:
-  assert(reg->stride == ((reg->type == BRW_REGISTER_TYPE_V ||
-  reg->type == BRW_REGISTER_TYPE_UV ||
-  reg->type == BRW_REGISTER_TYPE_VF) ? 1 : 0));
-
-  switch (reg->type) {
-  case BRW_REGISTER_TYPE_F:
-brw_reg = brw_imm_f(reg->f);
-break;
-  case BRW_REGISTER_TYPE_D:
-brw_reg = brw_imm_d(reg->d);
-break;
-  case BRW_REGISTER_TYPE_UD:
-brw_reg = brw_imm_ud(reg->ud);
-break;
-  case BRW_REGISTER_TYPE_W:
-brw_reg = brw_imm_w(reg->d);
-break;
-  case BRW_REGISTER_TYPE_UW:
-brw_reg = brw_imm_uw(reg->ud);
-break;
-  case BRW_REGISTER_TYPE_VF:
- brw_reg = brw_imm_vf(reg->ud);
- break;
-  case BRW_REGISTER_TYPE_V:
- brw_reg = brw_imm_v(reg->ud);
- break;
-  default:
-unreachable("not reached");
-  }
-  break;
case ARF:
case FIXED_GRF:
+   case IMM:
   brw_reg = *static_cast(reg);
   break;
case BAD_FILE:
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 06b7077..44893e3 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1719,11 +1719,6 @@ vec4_visitor::convert_to_hw_regs()
 reg.negate = src.negate;
 break;
 
- case IMM:
-reg = brw_imm_reg(src.type);
-reg.ud = src.ud;
-break;
-
  case UNIFORM:
 reg = stride(brw_vec4_grf(prog_data->base.dispatch_grf_start_reg +
   (src.nr + src.reg_offset) / 2,
@@ -1740,6 +1735,7 @@ vec4_visitor::convert_to_hw_regs()
 
  case ARF:
  case FIXED_GRF:
+ case IMM:
 continue;
 
  case BAD_FILE:

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Mesa (master): nv50: add NV84_3D macro

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: 9e40a621c177d595ffd1cf094246219e7067d768
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e40a621c177d595ffd1cf094246219e7067d768

Author: Samuel Pitoiset 
Date:   Thu Nov 19 09:51:02 2015 +0100

nv50: add NV84_3D macro

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Ilia Mirkin 

---

 src/gallium/drivers/nouveau/nv50/nv50_screen.c |2 +-
 src/gallium/drivers/nouveau/nv50/nv50_vbo.c|4 ++--
 src/gallium/drivers/nouveau/nv50/nv50_winsys.h |1 +
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 4e7201d..cc7984d 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -686,7 +686,7 @@ nv50_screen_init_hwctx(struct nv50_screen *screen)
BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
PUSH_DATA (push, 0);
if (screen->base.class_3d >= NV84_3D_CLASS) {
-  BEGIN_NV04(push, SUBC_3D(NV84_3D_VERTEX_ID_BASE), 1);
+  BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
   PUSH_DATA (push, 0);
}
 
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c 
b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
index 9aa593f..ac0c4d9 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
@@ -487,7 +487,7 @@ nv50_draw_arrays(struct nv50_context *nv50,
   BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
   PUSH_DATA (push, 0);
   if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
- BEGIN_NV04(push, SUBC_3D(NV84_3D_VERTEX_ID_BASE), 1);
+ BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
  PUSH_DATA (push, 0);
   }
   nv50->state.index_bias = 0;
@@ -613,7 +613,7 @@ nv50_draw_elements(struct nv50_context *nv50, bool shorten,
   BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
   PUSH_DATA (push, index_bias);
   if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
- BEGIN_NV04(push, SUBC_3D(NV84_3D_VERTEX_ID_BASE), 1);
+ BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
  PUSH_DATA (push, index_bias);
   }
   nv50->state.index_bias = index_bias;
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_winsys.h 
b/src/gallium/drivers/nouveau/nv50/nv50_winsys.h
index 76f1b41..6800230 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_winsys.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_winsys.h
@@ -49,6 +49,7 @@ PUSH_REFN(struct nouveau_pushbuf *push, struct nouveau_bo 
*bo, uint32_t flags)
 
 #define SUBC_3D(m) 3, (m)
 #define NV50_3D(n) SUBC_3D(NV50_3D_##n)
+#define NV84_3D(n) SUBC_3D(NV84_3D_##n)
 #define NVA0_3D(n) SUBC_3D(NVA0_3D_##n)
 
 #define SUBC_2D(m) 4, (m)

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Mesa (master): freedreno/a4xx: fix 5_5_5_1 texture sampler format

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 769b3ab6c5111f50502f9df0e8930c8d13f475c7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=769b3ab6c5111f50502f9df0e8930c8d13f475c7

Author: Ilia Mirkin 
Date:   Thu Nov 19 01:37:14 2015 -0500

freedreno/a4xx: fix 5_5_5_1 texture sampler format

This fixes teximage-colors, fbo-generatemipmap-formats, and probably
others (in relation to the RGB5 formats, others still fail).

Signed-off-by: Ilia Mirkin 
Cc: mesa-sta...@lists.freedesktop.org

---

 src/gallium/drivers/freedreno/a4xx/a4xx.xml.h |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h 
b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
index ef4f53f..a3fb570 100644
--- a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
+++ b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
@@ -154,7 +154,7 @@ enum a4xx_vtx_fmt {
 
 enum a4xx_tex_fmt {
TFMT4_5_6_5_UNORM = 11,
-   TFMT4_5_5_5_1_UNORM = 10,
+   TFMT4_5_5_5_1_UNORM = 9,
TFMT4_4_4_4_4_UNORM = 8,
TFMT4_X8Z24_UNORM = 71,
TFMT4_10_10_10_2_UNORM = 33,

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Mesa (master): freedreno/a4xx: support lod_bias

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 0a4462ad6ee921ed805ad51e330b819b95ee90d6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a4462ad6ee921ed805ad51e330b819b95ee90d6

Author: Ilia Mirkin 
Date:   Wed Nov 18 23:54:25 2015 -0500

freedreno/a4xx: support lod_bias

The lower layers assume that we support this, and it's been core since
GL 1.4. This fixes a slew of piglit tests, especially around
tex-miplevel-selection.

Signed-off-by: Ilia Mirkin 
Cc: mesa-sta...@lists.freedesktop.org

---

 src/gallium/drivers/freedreno/a4xx/a4xx.xml.h|6 ++
 src/gallium/drivers/freedreno/a4xx/fd4_texture.c |1 +
 2 files changed, 7 insertions(+)

diff --git a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h 
b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
index 76f525c..07d0db1 100644
--- a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
+++ b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
@@ -2741,6 +2741,12 @@ static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum 
a4xx_tex_aniso val)
 {
return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & 
A4XX_TEX_SAMP_0_ANISO__MASK;
 }
+#define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff8
+#define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT19
+static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val)
+{
+   return int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) 
& A4XX_TEX_SAMP_0_LOD_BIAS__MASK;
+}
 
 #define REG_A4XX_TEX_SAMP_10x0001
 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x000e
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_texture.c 
b/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
index 297854f..886b454 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
@@ -127,6 +127,7 @@ fd4_sampler_state_create(struct pipe_context *pctx,
COND(!cso->normalized_coords, A4XX_TEX_SAMP_1_UNNORM_COORDS);
 
if (cso->min_mip_filter != PIPE_TEX_MIPFILTER_NONE) {
+   so->texsamp0 |= A4XX_TEX_SAMP_0_LOD_BIAS(cso->lod_bias);
so->texsamp1 |=
A4XX_TEX_SAMP_1_MIN_LOD(cso->min_lod) |
A4XX_TEX_SAMP_1_MAX_LOD(cso->max_lod);

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Mesa (master): freedreno/a4xx: add depth clamp and halfz clip

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: a05e5491c367cdb7db93a2cc47a839329b90e513
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a05e5491c367cdb7db93a2cc47a839329b90e513

Author: Ilia Mirkin 
Date:   Thu Nov 19 00:32:39 2015 -0500

freedreno/a4xx: add depth clamp and halfz clip

Signed-off-by: Ilia Mirkin 

---

 src/gallium/drivers/freedreno/a4xx/a4xx.xml.h   |2 ++
 src/gallium/drivers/freedreno/a4xx/fd4_rasterizer.c |5 +
 src/gallium/drivers/freedreno/freedreno_screen.c|6 ++
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h 
b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
index ec002f6..ef4f53f 100644
--- a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
+++ b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
@@ -2059,6 +2059,8 @@ static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t 
val)
 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3
0x0c8b
 
 #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x2000
+#define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE0x8000
+#define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x0040
 
 #define REG_A4XX_GRAS_CLEAR_CNTL   0x2003
 #define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x0001
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_rasterizer.c 
b/src/gallium/drivers/freedreno/a4xx/fd4_rasterizer.c
index dc7e98b..d894b6b 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_rasterizer.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_rasterizer.c
@@ -90,5 +90,10 @@ fd4_rasterizer_state_create(struct pipe_context *pctx,
if (cso->offset_tri)
so->gras_su_mode_control |= 
A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET;
 
+   if (!cso->depth_clip)
+   so->gras_cl_clip_cntl |= A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE;
+   if (cso->clip_halfz)
+   so->gras_cl_clip_cntl |= A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z;
+
return so;
 }
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c 
b/src/gallium/drivers/freedreno/freedreno_screen.c
index 8ab78d8..adb0982 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -179,6 +179,8 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
case PIPE_CAP_FAKE_SW_MSAA:
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
+   case PIPE_CAP_DEPTH_CLIP_DISABLE:
+   case PIPE_CAP_CLIP_HALFZ:
return is_a3xx(screen) || is_a4xx(screen);
 
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
@@ -192,10 +194,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
if (is_a4xx(screen)) return 16383;
return 0;
 
-   case PIPE_CAP_DEPTH_CLIP_DISABLE:
-   case PIPE_CAP_CLIP_HALFZ:
-   return is_a3xx(screen);
-
case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
case PIPE_CAP_CUBE_MAP_ARRAY:
return is_a4xx(screen);

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Mesa (master): freedreno/a4xx: allow seamless cubemap filtering to be enabled per-texture

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: b17a405609156dc554d2d7c148c02e24bfdecaca
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b17a405609156dc554d2d7c148c02e24bfdecaca

Author: Ilia Mirkin 
Date:   Thu Nov 19 00:06:46 2015 -0500

freedreno/a4xx: allow seamless cubemap filtering to be enabled per-texture

Signed-off-by: Ilia Mirkin 

---

 src/gallium/drivers/freedreno/a4xx/a4xx.xml.h|1 +
 src/gallium/drivers/freedreno/a4xx/fd4_texture.c |1 +
 src/gallium/drivers/freedreno/freedreno_screen.c |2 +-
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h 
b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
index 07d0db1..ec002f6 100644
--- a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
+++ b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
@@ -2755,6 +2755,7 @@ static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum 
adreno_compare_func val
 {
return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & 
A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
 }
+#define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x0010
 #define A4XX_TEX_SAMP_1_UNNORM_COORDS  0x0020
 #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR   0x0040
 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK  0x000fff00
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_texture.c 
b/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
index 886b454..00c257b 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
@@ -124,6 +124,7 @@ fd4_sampler_state_create(struct pipe_context *pctx,
 
so->texsamp1 =
 // COND(miplinear, A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR) |
+   COND(!cso->seamless_cube_map, 
A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF) |
COND(!cso->normalized_coords, A4XX_TEX_SAMP_1_UNNORM_COORDS);
 
if (cso->min_mip_filter != PIPE_TEX_MIPFILTER_NONE) {
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c 
b/src/gallium/drivers/freedreno/freedreno_screen.c
index 4569177..8ab78d8 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -178,6 +178,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
case PIPE_CAP_CONDITIONAL_RENDER:
case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
case PIPE_CAP_FAKE_SW_MSAA:
+   case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
return is_a3xx(screen) || is_a4xx(screen);
 
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
@@ -193,7 +194,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
 
case PIPE_CAP_DEPTH_CLIP_DISABLE:
case PIPE_CAP_CLIP_HALFZ:
-   case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
return is_a3xx(screen);
 
case PIPE_CAP_TEXTURE_FLOAT_LINEAR:

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Mesa (master): nir: add nir_var_all enum

[Rob Clark]

Module: Mesa
Branch: master
Commit: 006e4f070f08ff1e1731863940bc51de9e97b865
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=006e4f070f08ff1e1731863940bc51de9e97b865

Author: Rob Clark 
Date:   Mon Oct 19 11:57:51 2015 -0400

nir: add nir_var_all enum

Otherwise, passing -1 gets you:

  error: invalid conversion from 'int' to 'nir_variable_mode' [-fpermissive]

Signed-off-by: Rob Clark 
Reviewed-by: Jason Ekstrand 

---

 src/glsl/nir/nir.c  |4 
 src/glsl/nir/nir.h  |1 +
 src/glsl/nir/nir_lower_io.c |2 +-
 src/mesa/drivers/dri/i965/brw_nir.c |2 +-
 4 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/glsl/nir/nir.c b/src/glsl/nir/nir.c
index 93c18fb..dba18c9 100644
--- a/src/glsl/nir/nir.c
+++ b/src/glsl/nir/nir.c
@@ -107,6 +107,10 @@ void
 nir_shader_add_variable(nir_shader *shader, nir_variable *var)
 {
switch (var->data.mode) {
+   case nir_var_all:
+  assert(!"invalid mode");
+  break;
+
case nir_var_local:
   assert(!"nir_shader_add_variable cannot be used for local variables");
   break;
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index e9d722e..09eb712 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -82,6 +82,7 @@ typedef struct {
 } nir_state_slot;
 
 typedef enum {
+   nir_var_all = -1,
nir_var_shader_in,
nir_var_shader_out,
nir_var_global,
diff --git a/src/glsl/nir/nir_lower_io.c b/src/glsl/nir/nir_lower_io.c
index 00a3145..5683e69 100644
--- a/src/glsl/nir/nir_lower_io.c
+++ b/src/glsl/nir/nir_lower_io.c
@@ -197,7 +197,7 @@ nir_lower_io_block(nir_block *block, void *void_state)
 
   nir_variable_mode mode = intrin->variables[0]->var->data.mode;
 
-  if (state->mode != -1 && state->mode != mode)
+  if (state->mode != nir_var_all && state->mode != mode)
  continue;
 
   if (mode != nir_var_shader_in &&
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c 
b/src/mesa/drivers/dri/i965/brw_nir.c
index 7896f29..bd91254 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -290,7 +290,7 @@ brw_create_nir(struct brw_context *brw,
nir_assign_var_locations(>uniforms,
 >num_uniforms,
 is_scalar ? type_size_scalar : type_size_vec4);
-   OPT_V(nir_lower_io, -1, is_scalar ? type_size_scalar : type_size_vec4);
+   OPT_V(nir_lower_io, nir_var_all, is_scalar ? type_size_scalar : 
type_size_vec4);
 
OPT(nir_remove_dead_variables);
 

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Mesa (master): nir: fix missing increments of num_inputs/num_outputs

[Rob Clark]

Module: Mesa
Branch: master
Commit: c73f40c4731235153e29222eee8e12241166094a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c73f40c4731235153e29222eee8e12241166094a

Author: Rob Clark 
Date:   Wed Nov  4 16:10:52 2015 -0500

nir: fix missing increments of num_inputs/num_outputs

Note: not quite perfect, we should use type_size vfunc (in
compiler_options or nir_shader?) to determine how much we
increment num_inputs/outputs/uniforms.  But we don't have
that yet, so let's at least fix things for the existing
users of these passes.

Signed-off-by: Rob Clark 
Acked-by: Jason Ekstrand 

---

 src/glsl/nir/nir_lower_clip.c|2 ++
 src/glsl/nir/nir_lower_two_sided_color.c |2 ++
 2 files changed, 4 insertions(+)

diff --git a/src/glsl/nir/nir_lower_clip.c b/src/glsl/nir/nir_lower_clip.c
index 31ccfb2..c58c778 100644
--- a/src/glsl/nir/nir_lower_clip.c
+++ b/src/glsl/nir/nir_lower_clip.c
@@ -55,9 +55,11 @@ create_clipdist_var(nir_shader *shader, unsigned drvloc,
 
if (output) {
   exec_list_push_tail(>outputs, >node);
+  shader->num_outputs++; /* TODO use type_size() */
}
else {
   exec_list_push_tail(>inputs, >node);
+  shader->num_inputs++;  /* TODO use type_size() */
}
return var;
 }
diff --git a/src/glsl/nir/nir_lower_two_sided_color.c 
b/src/glsl/nir/nir_lower_two_sided_color.c
index db519bf..6995b9d 100644
--- a/src/glsl/nir/nir_lower_two_sided_color.c
+++ b/src/glsl/nir/nir_lower_two_sided_color.c
@@ -60,6 +60,8 @@ create_input(nir_shader *shader, unsigned drvloc, 
gl_varying_slot slot)
 
exec_list_push_tail(>inputs, >node);
 
+   shader->num_inputs++; /* TODO use type_size() */
+
return var;
 }
 

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Mesa (master): nir: add nir_ssa_for_alu_src()

[Rob Clark]

Module: Mesa
Branch: master
Commit: acca6c65d3c793885b343aad17cbdbad7fbe1830
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=acca6c65d3c793885b343aad17cbdbad7fbe1830

Author: Rob Clark 
Date:   Thu Nov  5 10:23:48 2015 -0500

nir: add nir_ssa_for_alu_src()

Using something like:

   numer = nir_ssa_for_src(bld, alu->src[0].src,
   nir_ssa_alu_instr_src_components(alu, 0));

for alu src's with swizzle, like:

   vec1 ssa_10 = intrinsic load_uniform () () (0, 0)
   vec2 ssa_11 = intrinsic load_uniform () () (1, 0)
   vec2 ssa_2 = udiv ssa_10.xx, ssa_11

ends up turning into something like:

   vec1 ssa_10 = intrinsic load_uniform () () (0, 0)
   vec2 ssa_11 = intrinsic load_uniform () () (1, 0)
   vec2 ssa_13 = imov ssa_10
   ...

because nir_ssa_for_src() ignore's the original nir_alu_src's swizzle.
Instead for alu instructions, nir_src_for_alu_src() should be used to
ensure the original alu src's swizzle doesn't get lost in translation:

   vec1 ssa_10 = intrinsic load_uniform () () (0, 0)
   vec2 ssa_11 = intrinsic load_uniform () () (1, 0)
   vec2 ssa_13 = imov ssa_10.xx
   ...

v2: check for abs/neg, and re-use existing nir_alu_src

Signed-off-by: Rob Clark 
Reviewed-by: Jason Ekstrand 

---

 src/glsl/nir/nir_builder.h|   21 +
 src/glsl/nir/nir_lower_idiv.c |6 ++
 2 files changed, 23 insertions(+), 4 deletions(-)

diff --git a/src/glsl/nir/nir_builder.h b/src/glsl/nir/nir_builder.h
index 624329d..d09f929 100644
--- a/src/glsl/nir/nir_builder.h
+++ b/src/glsl/nir/nir_builder.h
@@ -259,6 +259,8 @@ nir_channel(nir_builder *b, nir_ssa_def *def, unsigned c)
 /**
  * Turns a nir_src into a nir_ssa_def * so it can be passed to
  * nir_build_alu()-based builder calls.
+ *
+ * See nir_ssa_for_alu_src() for alu instructions.
  */
 static inline nir_ssa_def *
 nir_ssa_for_src(nir_builder *build, nir_src src, int num_components)
@@ -274,6 +276,25 @@ nir_ssa_for_src(nir_builder *build, nir_src src, int 
num_components)
return nir_imov_alu(build, alu, num_components);
 }
 
+/**
+ * Similar to nir_ssa_for_src(), but for alu src's, respecting the
+ * nir_alu_src's swizzle.
+ */
+static inline nir_ssa_def *
+nir_ssa_for_alu_src(nir_builder *build, nir_alu_instr *instr, unsigned srcn)
+{
+   static uint8_t trivial_swizzle[4] = { 0, 1, 2, 3 };
+   nir_alu_src *src = >src[srcn];
+   unsigned num_components = nir_ssa_alu_instr_src_components(instr, srcn);
+
+   if (src->src.is_ssa && (src->src.ssa->num_components == num_components) &&
+   !src->abs && !src->negate &&
+   (memcmp(src->swizzle, trivial_swizzle, num_components) == 0))
+  return src->src.ssa;
+
+   return nir_imov_alu(build, *src, num_components);
+}
+
 static inline nir_ssa_def *
 nir_load_var(nir_builder *build, nir_variable *var)
 {
diff --git a/src/glsl/nir/nir_lower_idiv.c b/src/glsl/nir/nir_lower_idiv.c
index 3580ced..f64b3ea 100644
--- a/src/glsl/nir/nir_lower_idiv.c
+++ b/src/glsl/nir/nir_lower_idiv.c
@@ -52,10 +52,8 @@ convert_instr(nir_builder *bld, nir_alu_instr *alu)
 
bld->cursor = nir_before_instr(>instr);
 
-   numer = nir_ssa_for_src(bld, alu->src[0].src,
-   nir_ssa_alu_instr_src_components(alu, 0));
-   denom = nir_ssa_for_src(bld, alu->src[1].src,
-   nir_ssa_alu_instr_src_components(alu, 1));
+   numer = nir_ssa_for_alu_src(bld, alu, 0);
+   denom = nir_ssa_for_alu_src(bld, alu, 1);
 
if (is_signed) {
   af = nir_i2f(bld, numer);

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Mesa (master): nir/print: show # of uniforms/inputs/outputs

[Rob Clark]

Module: Mesa
Branch: master
Commit: fec9367deb51003ccb74aca796e759502cfedfeb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fec9367deb51003ccb74aca796e759502cfedfeb

Author: Rob Clark 
Date:   Wed Nov  4 10:05:32 2015 -0500

nir/print: show # of uniforms/inputs/outputs

Signed-off-by: Rob Clark 

---

 src/glsl/nir/nir_print.c |4 
 1 file changed, 4 insertions(+)

diff --git a/src/glsl/nir/nir_print.c b/src/glsl/nir/nir_print.c
index c4160e6..54b8cc6 100644
--- a/src/glsl/nir/nir_print.c
+++ b/src/glsl/nir/nir_print.c
@@ -983,6 +983,10 @@ nir_print_shader(nir_shader *shader, FILE *fp)
if (shader->info.label)
   fprintf(fp, "label: %s\n", shader->info.label);
 
+   fprintf(fp, "inputs: %u\n", shader->num_inputs);
+   fprintf(fp, "outputs: %u\n", shader->num_outputs);
+   fprintf(fp, "uniforms: %u\n", shader->num_uniforms);
+
nir_foreach_variable(var, >uniforms) {
   print_var_decl(var, );
}

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Mesa (master): nir/print: show shader name/label if set

[Rob Clark]

Module: Mesa
Branch: master
Commit: 01e94d8d5d32d0debf35533180bf4633a139dd63
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=01e94d8d5d32d0debf35533180bf4633a139dd63

Author: Rob Clark 
Date:   Mon Oct 26 13:29:45 2015 -0400

nir/print: show shader name/label if set

Signed-off-by: Rob Clark 
Reviewed-by: Jason Ekstrand 

---

 src/glsl/nir/nir_print.c |6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/glsl/nir/nir_print.c b/src/glsl/nir/nir_print.c
index f7f5fdf..c4160e6 100644
--- a/src/glsl/nir/nir_print.c
+++ b/src/glsl/nir/nir_print.c
@@ -977,6 +977,12 @@ nir_print_shader(nir_shader *shader, FILE *fp)
 
fprintf(fp, "shader: %s\n", gl_shader_stage_name(shader->stage));
 
+   if (shader->info.name)
+  fprintf(fp, "name: %s\n", shader->info.name);
+
+   if (shader->info.label)
+  fprintf(fp, "label: %s\n", shader->info.label);
+
nir_foreach_variable(var, >uniforms) {
   print_var_decl(var, );
}

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Mesa (master): nv50: allow using inline vertex data submit when gl_VertexID is used

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: 0cfc1304bece9cbc17a39b009956b2830c6fd2f5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0cfc1304bece9cbc17a39b009956b2830c6fd2f5

Author: Samuel Pitoiset 
Date:   Thu Nov 19 09:51:03 2015 +0100

nv50: allow using inline vertex data submit when gl_VertexID is used

The hardware can actually generates vertexid when vertices come from
a client-side buffer like when glDrawElements is used.

This doesn't fix (or break) any piglit tests but it improves the
previous attempt of Ilia (c830d19 "nv50: avoid using inline vertex
data submit when gl_VertexID is used")

The only disadvantage is that only works on G84+, but we don't really
care of that weird and old NV50 chipset.

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Ilia Mirkin 

---

 src/gallium/drivers/nouveau/nv50/nv50_program.c|3 +-
 src/gallium/drivers/nouveau/nv50/nv50_program.h|2 +-
 src/gallium/drivers/nouveau/nv50/nv50_push.c   |   42 +++-
 .../drivers/nouveau/nv50/nv50_state_validate.c |3 +-
 src/gallium/drivers/nouveau/nv50/nv50_vbo.c|   11 +
 5 files changed, 46 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.c 
b/src/gallium/drivers/nouveau/nv50/nv50_program.c
index 48057d2..a4b8ddf 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_program.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_program.c
@@ -66,7 +66,6 @@ nv50_vertprog_assign_slots(struct nv50_ir_prog_info *info)
   case TGSI_SEMANTIC_VERTEXID:
  prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_VERTEX_ID;
  prog->vp.attrs[2] |= 
NV50_3D_VP_GP_BUILTIN_ATTR_EN_VERTEX_ID_DRAW_ARRAYS_ADD_START;
- prog->vp.vertexid = 1;
  continue;
   default:
  break;
@@ -383,6 +382,8 @@ nv50_program_translate(struct nv50_program *prog, uint16_t 
chipset,
prog->max_gpr = MAX2(4, (info->bin.maxGPR >> 1) + 1);
prog->tls_space = info->bin.tlsSpace;
 
+   prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
+
if (prog->type == PIPE_SHADER_FRAGMENT) {
   if (info->prop.fp.writesDepth) {
  prog->fp.flags[0] |= NV50_3D_FP_CONTROL_EXPORTS_Z;
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.h 
b/src/gallium/drivers/nouveau/nv50/nv50_program.h
index f001670..1de5122 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_program.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_program.h
@@ -76,9 +76,9 @@ struct nv50_program {
   ubyte psiz;/* output slot of point size */
   ubyte bfc[2];  /* indices into varying for FFC (FP) or BFC (VP) */
   ubyte edgeflag;
-  ubyte vertexid;
   ubyte clpd[2]; /* output slot of clip distance[i]'s 1st component */
   ubyte clpd_nr;
+  bool need_vertex_id;
} vp;
 
struct {
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_push.c 
b/src/gallium/drivers/nouveau/nv50/nv50_push.c
index f31eaa0..cbef95d 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_push.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_push.c
@@ -24,6 +24,10 @@ struct push_context {
struct translate *translate;
 
bool primitive_restart;
+
+   bool need_vertex_id;
+   int32_t index_bias;
+
uint32_t prim;
uint32_t restart_index;
uint32_t instance_id;
@@ -74,6 +78,11 @@ emit_vertices_i08(struct push_context *ctx, unsigned start, 
unsigned count)
 
   size = ctx->vertex_words * nr;
 
+  if (unlikely(ctx->need_vertex_id)) {
+ BEGIN_NV04(ctx->push, NV84_3D(VERTEX_ID_BASE), 1);
+ PUSH_DATA (ctx->push, *elts + ctx->index_bias);
+  }
+
   BEGIN_NI04(ctx->push, NV50_3D(VERTEX_DATA), size);
 
   ctx->translate->run_elts8(ctx->translate, elts, nr, 0, ctx->instance_id,
@@ -107,6 +116,11 @@ emit_vertices_i16(struct push_context *ctx, unsigned 
start, unsigned count)
 
   size = ctx->vertex_words * nr;
 
+  if (unlikely(ctx->need_vertex_id)) {
+ BEGIN_NV04(ctx->push, NV84_3D(VERTEX_ID_BASE), 1);
+ PUSH_DATA (ctx->push, *elts + ctx->index_bias);
+  }
+
   BEGIN_NI04(ctx->push, NV50_3D(VERTEX_DATA), size);
 
   ctx->translate->run_elts16(ctx->translate, elts, nr, 0, ctx->instance_id,
@@ -140,6 +154,11 @@ emit_vertices_i32(struct push_context *ctx, unsigned 
start, unsigned count)
 
   size = ctx->vertex_words * nr;
 
+  if (unlikely(ctx->need_vertex_id)) {
+ BEGIN_NV04(ctx->push, NV84_3D(VERTEX_ID_BASE), 1);
+ PUSH_DATA (ctx->push, *elts + ctx->index_bias);
+  }
+
   BEGIN_NI04(ctx->push, NV50_3D(VERTEX_DATA), size);
 
   ctx->translate->run_elts(ctx->translate, elts, nr, 0, ctx->instance_id,
@@ -161,10 +180,18 @@ emit_vertices_i32(struct push_context *ctx, unsigned 
start, unsigned count)
 static void
 emit_vertices_seq(struct push_context *ctx, unsigned start, unsigned count)
 {
+   uint32_t elts = 0;
+
while (count) {
   unsigned push = 

Mesa (11.0): st/vaapi: fix vaapi VC-1 simple/main corruption v2

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: 71a785fc5f87d7755bfa90842cd7011be609d744
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=71a785fc5f87d7755bfa90842cd7011be609d744

Author: Boyuan Zhang 
Date:   Wed Sep 23 10:11:07 2015 +0200

st/vaapi: fix vaapi VC-1 simple/main corruption v2

Apply the start code fix only to advanced profile.

v2 (chk): add commit message

Signed-off-by: Boyuan Zhang 
Reviewed-by: Christian König 
Reviewed-by: Alex Deucher 
Cc: "10.6 11.0" 
(cherry picked from commit ed55def44febbe1662ddcc0c33a23308899ce488)

---

 src/gallium/state_trackers/va/picture.c |2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index a0d530b..e20184c 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -500,8 +500,10 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)
   bufHasStartcode(buf, 0x010b, 32))
  break;
 
+  if (context->decoder->profile == PIPE_VIDEO_PROFILE_VC1_ADVANCED) {
  buffers[num_buffers] = (void *const)_code_vc1;
  sizes[num_buffers++] = sizeof(start_code_vc1);
+  }
   break;
case PIPE_VIDEO_FORMAT_MPEG4:
   if (bufHasStartcode(buf, 0x01, 24))

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Mesa (11.0): nir/vars_to_ssa: Rework copy set handling in lower_copies_to_load_store

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: 0dd0d6696fd7760f460af87f7155ce2ae6316945
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0dd0d6696fd7760f460af87f7155ce2ae6316945

Author: Jason Ekstrand 
Date:   Thu Nov 12 18:10:22 2015 -0800

nir/vars_to_ssa: Rework copy set handling in lower_copies_to_load_store

Previously, we walked through a given deref_node's copies and, after
lowering the copy away, removed it from both the source and destination
copy sets.  This commit changes this to only remove it from the other
node's copy set (not the one we're lowering).  At the end of the loop, we
just throw away the copy set for the node we're lowering since that node no
longer has any copies.  This has two advantages:

 1) It's more efficient because we're doing potentially half as many set
search operations.

 2) It now properly handles copies from a node to itself.  Perviously, it
would delete the copy from the set when processing the destinatioon and
then assert-fail when we couldn't find it for the source.

Cc: "11.0" 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92588
Reviewed-by: Timothy Arceri 
Reviewed-by: Connor Abbott 
(cherry picked from commit 226ba889a0f820b9f4b1132e379620d2688c96e7)

---

 src/glsl/nir/nir_lower_vars_to_ssa.c |5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/glsl/nir/nir_lower_vars_to_ssa.c 
b/src/glsl/nir/nir_lower_vars_to_ssa.c
index ccb8f99..1248926 100644
--- a/src/glsl/nir/nir_lower_vars_to_ssa.c
+++ b/src/glsl/nir/nir_lower_vars_to_ssa.c
@@ -455,7 +455,8 @@ lower_copies_to_load_store(struct deref_node *node,
  struct deref_node *arg_node =
 get_deref_node(copy->variables[i], state);
 
- if (arg_node == NULL)
+ /* Only bother removing copy entries for other nodes */
+ if (arg_node == NULL || arg_node == node)
 continue;
 
  struct set_entry *arg_entry = _mesa_set_search(arg_node->copies, 
copy);
@@ -466,6 +467,8 @@ lower_copies_to_load_store(struct deref_node *node,
   nir_instr_remove(>instr);
}
 
+   node->copies = NULL;
+
return true;
 }
 

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Mesa (11.0): radeon/uvd: fix VC-1 simple/main profile decode v2

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: 6a958b0b51a79bf4f79a898db5c0277076e138d9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a958b0b51a79bf4f79a898db5c0277076e138d9

Author: Boyuan Zhang 
Date:   Wed Sep 23 10:11:08 2015 +0200

radeon/uvd: fix VC-1 simple/main profile decode v2

We just needed to set the extra width/height fields to get this working.

v2 (chk): rebased, CC stable added, commit message added, fixed coding style

Signed-off-by: Boyuan Zhang 
Signed-off-by: Christian König 
Reviewed-by: Alex Deucher 
Cc: "10.6 11.0" 
(cherry picked from commit 6bad554d98004e6c8ab46e8cbe73f3b3024e55c5)

---

 src/gallium/drivers/radeon/radeon_uvd.c   |6 ++
 src/gallium/drivers/radeon/radeon_video.c |3 +--
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_uvd.c 
b/src/gallium/drivers/radeon/radeon_uvd.c
index 81f3f45..55c216a 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -940,6 +940,12 @@ static void ruvd_end_frame(struct pipe_video_codec 
*decoder,
dec->msg->body.decode.width_in_samples = dec->base.width;
dec->msg->body.decode.height_in_samples = dec->base.height;
 
+   if ((picture->profile == PIPE_VIDEO_PROFILE_VC1_SIMPLE) ||
+   (picture->profile == PIPE_VIDEO_PROFILE_VC1_MAIN)) {
+   dec->msg->body.decode.width_in_samples = 
align(dec->msg->body.decode.width_in_samples, 16) / 16;
+   dec->msg->body.decode.height_in_samples = 
align(dec->msg->body.decode.height_in_samples, 16) / 16;
+   }
+
dec->msg->body.decode.dpb_size = dec->dpb.res->buf->size;
dec->msg->body.decode.bsd_size = bs_size;
dec->msg->body.decode.db_pitch = dec->base.width;
diff --git a/src/gallium/drivers/radeon/radeon_video.c 
b/src/gallium/drivers/radeon/radeon_video.c
index 32bfc32..f56c6cf 100644
--- a/src/gallium/drivers/radeon/radeon_video.c
+++ b/src/gallium/drivers/radeon/radeon_video.c
@@ -244,8 +244,7 @@ int rvid_get_video_param(struct pipe_screen *screen,
return codec != PIPE_VIDEO_FORMAT_MPEG4;
return true;
case PIPE_VIDEO_FORMAT_VC1:
-   /* FIXME: VC-1 simple/main profile is broken */
-   return profile == PIPE_VIDEO_PROFILE_VC1_ADVANCED;
+   return true;
case PIPE_VIDEO_FORMAT_HEVC:
/* Carrizo only supports HEVC Main */
return rscreen->family >= CHIP_CARRIZO &&

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Mesa (11.0): radeonsi: enable optimal raster config setting for fiji (v2)

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: 55325d06320dcd95f0152cb872b84fedc92fc5de
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=55325d06320dcd95f0152cb872b84fedc92fc5de

Author: Alex Deucher 
Date:   Fri Nov 13 13:00:30 2015 -0500

radeonsi: enable optimal raster config setting for fiji (v2)

Requires proper kernel tiling configuration so check the tiling
config registers.

v2: send the right version of the patch

Reviewed-by: Marek Olšák 
Signed-off-by: Alex Deucher 
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit 00f554abba8c0f3b65af94365c15109c3b858486)

---

 src/gallium/drivers/radeonsi/si_state.c |   12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 1bca645..81e1382 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3176,6 +3176,7 @@ si_write_harvested_raster_configs(struct si_context *sctx,
 
 static void si_init_config(struct si_context *sctx)
 {
+   struct si_screen *sscreen = sctx->screen;
unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
unsigned raster_config, raster_config_1;
@@ -3243,9 +3244,14 @@ static void si_init_config(struct si_context *sctx)
raster_config_1 = 0x002e;
break;
case CHIP_FIJI:
-   /* Fiji should be same as Hawaii, but that causes corruption in 
some cases */
-   raster_config = 0x1612; /* 0x3a00161a */
-   raster_config_1 = 0x002a; /* 0x002e */
+   if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x00e8) {
+   /* old kernels with old tiling config */
+   raster_config = 0x1612;
+   raster_config_1 = 0x002a;
+   } else {
+   raster_config = 0x3a00161a;
+   raster_config_1 = 0x002e;
+   }
break;
case CHIP_TONGA:
raster_config = 0x1612;

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Mesa (11.0): meta/generate_mipmap: Don't leak the sampler object

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: 0b7bdb06687453cdb9755fd19215c24659846a3b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b7bdb06687453cdb9755fd19215c24659846a3b

Author: Ian Romanick 
Date:   Tue Nov 10 12:36:58 2015 -0800

meta/generate_mipmap: Don't leak the sampler object

Signed-off-by: Ian Romanick 
Cc: "10.6 11.0" 
Reviewed-by: Anuj Phogat 
(cherry picked from commit 758f12fd98dea9a9682becf2d496bd38ef3959e5)

---

 src/mesa/drivers/common/meta_generate_mipmap.c |2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/drivers/common/meta_generate_mipmap.c 
b/src/mesa/drivers/common/meta_generate_mipmap.c
index 5dc40a2..ced4742 100644
--- a/src/mesa/drivers/common/meta_generate_mipmap.c
+++ b/src/mesa/drivers/common/meta_generate_mipmap.c
@@ -128,6 +128,8 @@ _mesa_meta_glsl_generate_mipmap_cleanup(struct 
gen_mipmap_state *mipmap)
mipmap->VAO = 0;
_mesa_DeleteBuffers(1, >VBO);
mipmap->VBO = 0;
+   _mesa_DeleteSamplers(1, >Sampler);
+   mipmap->Sampler = 0;
 
_mesa_meta_blit_shader_table_cleanup(>shaders);
 }

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Mesa (11.0): r600: initialised PGM_RESOURCES_2 for ES/GS

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: 20f0d8849597f8df016dbe99e6c7c18d5b8af0e8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=20f0d8849597f8df016dbe99e6c7c18d5b8af0e8

Author: Dave Airlie 
Date:   Thu Nov 12 08:34:18 2015 +1000

r600: initialised PGM_RESOURCES_2 for ES/GS

This fixes the corruption on rendering that we are seeing in
certain geometry shaders.

Fixes:  https://bugs.freedesktop.org/show_bug.cgi?id=91780
Reviewed-by: Alex Deucher 
Tested / Reviewed-by: Glenn Kennard 
Cc: "10.6" "11.0" 
Signed-off-by: Dave Airlie 

(cherry picked from commit df8af7d75155845d12d5a14a3a5ca644f07cb3b1)

---

 src/gallium/drivers/r600/evergreen_state.c |4 
 src/gallium/drivers/r600/evergreend.h  |2 ++
 2 files changed, 6 insertions(+)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 82530be..2dc3811 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2342,6 +2342,8 @@ static void cayman_init_atom_start_cs(struct r600_context 
*rctx)
 
r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, 
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, 
S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
+   r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, 
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
+   r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, 
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
 
/* to avoid GPU doing any preloading of constant from random address */
@@ -2781,6 +2783,8 @@ void evergreen_init_atom_start_cs(struct r600_context 
*rctx)
 
r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, 
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, 
S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
+   r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, 
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
+   r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, 
S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
 
/* to avoid GPU doing any preloading of constant from random address */
diff --git a/src/gallium/drivers/r600/evergreend.h 
b/src/gallium/drivers/r600/evergreend.h
index ad6ad43..2b83892 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -1497,6 +1497,7 @@
 #define   S_028878_UNCACHED_FIRST_INST(x)  (((x) & 0x1) << 28)
 #define   G_028878_UNCACHED_FIRST_INST(x)  (((x) >> 28) & 0x1)
 #define   C_028878_UNCACHED_FIRST_INST 0xEFFF
+#define R_02887C_SQ_PGM_RESOURCES_2_GS 0x02887C
 
 #define R_028890_SQ_PGM_RESOURCES_ES 0x028890
 #define   S_028890_NUM_GPRS(x) (((x) & 0xFF) << 0)
@@ -1511,6 +1512,7 @@
 #define   S_028890_UNCACHED_FIRST_INST(x)  (((x) & 0x1) << 28)
 #define   G_028890_UNCACHED_FIRST_INST(x)  (((x) >> 28) & 0x1)
 #define   C_028890_UNCACHED_FIRST_INST 0xEFFF
+#define R_028894_SQ_PGM_RESOURCES_2_ES 0x028894
 
 #define R_028864_SQ_PGM_RESOURCES_2_VS   0x028864
 #define   S_028864_SINGLE_ROUND(x) (((x) & 0x3) << 0)

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Mesa (11.0): llvmpipe: use simple coeffs calc for 128bit vectors

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: 0c56517d16e4589f228a48f7e99c95b494ab80d6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c56517d16e4589f228a48f7e99c95b494ab80d6

Author: Oded Gabbay 
Date:   Tue Nov  3 10:36:01 2015 +0200

llvmpipe: use simple coeffs calc for 128bit vectors

There are currently two methods in llvmpipe code to calculate coeffs to
be used as inputs for the fragment shader. The two methods use slightly
different ways to do the floating point calculations and thus produce
slightly different results.

The decision which method to use is determined by the size of the vector
that is used by the platform.

For vectors with size of more than 128bit, a single-step method is used,
in which coeffs_init_simple() + attribs_update_simple() are called.

For vectors with size of 128bit or less, a two-step method is used, in
which coeffs_init() + attribs_update() are called.

This causes some piglit tests (clip-distance-bulk-copy,
interface-vs-unnamed-to-fs-unnamed) to fail when using platforms with
128bit vectors (such as ppc64le or x86-64 without AVX).

This patch makes platforms with 128bit vectors use the single-step
method (aka "simple" method) instead of the two-step method.
This would make the resulting coeffs identical between more platforms,
make sure the piglit tests passes, and make debugging and maintainability
a bit easier as the generated LLVM IR will be the same for more platforms.

The performance impact is negligible for x86-64 without AVX, and
basically non-existent for ppc64le, as it can be seen from the following
benchmarking results:

- glxspheres, on ppc64le:

   - original code:  4.892745317 frames/sec 5.460303857 Mpixels/sec
   - with the patch: 4.932083873 frames/sec 5.504205571 Mpixels/sec
   - Additional 0.8% performance boost

- glxspheres, on x86-64 without AVX:

   - original code:  20.16418809 frames/sec 22.50323395 Mpixels/sec
   - with the patch: 20.31328989 frames/sec 22.66963152 Mpixels/sec
   - Additional 0.74% performance boost

- glmark2, on ppc64le:

  - original code:  score of 58
  - with my change: score of 57

- glmark2, on x86-64 without AVX:

  - original code:  score of 175
  - with the patch: score of 167
  - Impact of of -4.5% on performance

- OpenArena, on ppc64le:

  - original code:  3398 frames 1719.0 seconds 2.0 fps
255.0/505.9/2773.0/0.0 ms

  - with the patch: 3398 frames 1690.4 seconds 2.0 fps
241.0/497.5/2563.0/0.2 ms

  - 29 seconds faster with the patch, which is about 2%

- OpenArena, on x86-64 without AVX:

  - original code:  3398 frames 239.6 seconds 14.2 fps
38.0/70.5/719.0/14.6 ms

  - with the patch: 3398 frames 244.4 seconds 13.9 fps
38.0/71.9/697.0/14.3 ms

  - 0.3 fps slower with the patch (about 2%)

Additional details can be found at:
http://lists.freedesktop.org/archives/mesa-dev/2015-October/098635.html

Signed-off-by: Oded Gabbay 
Reviewed-by: Roland Scheidegger 
(cherry picked from commit 39b4dfe6ab1003863778a25c091c080e098833ec)

---

 src/gallium/drivers/llvmpipe/lp_bld_interp.c |7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/llvmpipe/lp_bld_interp.c 
b/src/gallium/drivers/llvmpipe/lp_bld_interp.c
index df262fa..ceac86a 100644
--- a/src/gallium/drivers/llvmpipe/lp_bld_interp.c
+++ b/src/gallium/drivers/llvmpipe/lp_bld_interp.c
@@ -746,7 +746,12 @@ lp_build_interp_soa_init(struct 
lp_build_interp_soa_context *bld,
 
pos_init(bld, x0, y0);
 
-   if (coeff_type.length > 4) {
+   /*
+* Simple method (single step interpolation) may be slower if vector length
+* is just 4, but the results are different (generally less accurate) with
+* the other method, so always use more accurate version.
+*/
+   if (1) {
   bld->simple_interp = TRUE;
   {
  /* XXX this should use a global static table */

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Mesa (11.0): mesa/copyimage: allow width/ height to not be multiples of block

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: fa527fce5c5c05cd41fee37862a2b886dc8c0380
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa527fce5c5c05cd41fee37862a2b886dc8c0380

Author: Ilia Mirkin 
Date:   Sun Nov  8 04:46:38 2015 -0500

mesa/copyimage: allow width/height to not be multiples of block

For compressed textures, the image size is not necessarily a multiple of
the block size (e.g. the last mip levels). Section 18.3.2 (Copying
Between Images) of the OpenGL 4.5 Core Profile spec says:

An INVALID_VALUE error is generated if the dimensions of either
subregion exceeds the boundaries of the corresponding image
object, or if the image format is compressed and the dimensions of
the subregion fail to meet the alignment constraints of the
format.

and Section 8.7 (Compressed Texture Images) says:

An INVALID_OPERATION error is generated if any of the following
conditions occurs:

  * width is not a multiple of four, and width + xoffset is not
equal to the value of TEXTURE_WIDTH.
  * height is not a multiple of four, and height + yoffset is not
equal to the value of TEXTURE_HEIGHT.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92860
Signed-off-by: Ilia Mirkin 
Acked-by: Alex Deucher 
Reviewed-by: Jason Ekstrand 
Reviewed-by: Ian Romanick 
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit 912babba7bf1abd3caa49f6372d581ae1afe7e84)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov 

Conflicts:
src/mesa/main/copyimage.c

---

 src/mesa/main/copyimage.c |   40 +---
 1 file changed, 37 insertions(+), 3 deletions(-)

diff --git a/src/mesa/main/copyimage.c b/src/mesa/main/copyimage.c
index 05bc50d..669ed67 100644
--- a/src/mesa/main/copyimage.c
+++ b/src/mesa/main/copyimage.c
@@ -57,6 +57,8 @@ static bool
 prepare_target(struct gl_context *ctx, GLuint name, GLenum *target, int level,
struct gl_texture_object **tex_obj,
struct gl_texture_image **tex_image, GLuint *tmp_tex,
+   GLuint *width,
+   GLuint *height,
const char *dbg_prefix)
 {
if (name == 0) {
@@ -130,6 +132,8 @@ prepare_target(struct gl_context *ctx, GLuint name, GLenum 
*target, int level,
   _mesa_BindTexture(*target, *tmp_tex);
   *tex_obj = _mesa_lookup_texture(ctx, *tmp_tex);
   *tex_image = _mesa_get_tex_image(ctx, *tex_obj, *target, 0);
+  *width = rb->Width;
+  *height = rb->Height;
 
   if (!ctx->Driver.BindRenderbufferTexImage(ctx, rb, *tex_image)) {
  _mesa_problem(ctx, "Failed to create texture from renderbuffer");
@@ -175,6 +179,9 @@ prepare_target(struct gl_context *ctx, GLuint name, GLenum 
*target, int level,
  "glCopyImageSubData(%sLevel = %u)", dbg_prefix, level);
  return false;
   }
+
+  *width = (*tex_image)->Width;
+  *height = (*tex_image)->Height;
}
 
return true;
@@ -409,6 +416,7 @@ _mesa_CopyImageSubData(GLuint srcName, GLenum srcTarget, 
GLint srcLevel,
GLuint tmpTexNames[2] = { 0, 0 };
struct gl_texture_object *srcTexObj, *dstTexObj;
struct gl_texture_image *srcTexImage, *dstTexImage;
+   GLuint src_w, src_h, dst_w, dst_h;
GLuint src_bw, src_bh, dst_bw, dst_bh;
int i;
 
@@ -429,16 +437,42 @@ _mesa_CopyImageSubData(GLuint srcName, GLenum srcTarget, 
GLint srcLevel,
}
 
if (!prepare_target(ctx, srcName, , srcLevel,
-   , , [0], "src"))
+   , , [0],
+   _w, _h, "src"))
   goto cleanup;
 
if (!prepare_target(ctx, dstName, , dstLevel,
-   , , [1], "dst"))
+   , , [1],
+   _w, _h, "dst"))
   goto cleanup;
 
_mesa_get_format_block_size(srcTexImage->TexFormat, _bw, _bh);
+
+   /* Section 18.3.2 (Copying Between Images) of the OpenGL 4.5 Core Profile
+* spec says:
+*
+*An INVALID_VALUE error is generated if the dimensions of either
+*subregion exceeds the boundaries of the corresponding image object,
+*or if the image format is compressed and the dimensions of the
+*subregion fail to meet the alignment constraints of the format.
+*
+* and Section 8.7 (Compressed Texture Images) says:
+*
+*An INVALID_OPERATION error is generated if any of the following
+*conditions occurs:
+*
+*  * width is not a multiple of four, and width + xoffset is not
+*equal to the value of TEXTURE_WIDTH.
+*  * height is not a multiple of four, and height + yoffset is not
+*equal to the value of TEXTURE_HEIGHT.
+*
+* so we take that to mean that you can copy the "last" block of a
+* compressed texture image even if it's smaller than the 

Mesa (11.0): i965/skl/gt4: Fix URB programming restriction.

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: 4b3d4ceaba7fff20938c76961075d2bce6469b8d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4b3d4ceaba7fff20938c76961075d2bce6469b8d

Author: Ben Widawsky 
Date:   Fri Nov  6 18:12:27 2015 -0800

i965/skl/gt4: Fix URB programming restriction.

The comment in the code details the restriction. Thanks to Ken for having a very
helpful conversation with me, and spotting the blurb in the link I sent him :P.

There are still stability problems for me on GT4, but this definitely helps with
some of the failures.

v2: Comment fixes

Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Jordan Justen 
Reviewed-by: Kenneth Graunke 
(cherry picked from commit 55314c5be4cbf933ab7fbd20f6aa49207e04c946)

---

 src/mesa/drivers/dri/i965/brw_device_info.c |9 +
 1 file changed, 9 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c 
b/src/mesa/drivers/dri/i965/brw_device_info.c
index 758d2f2..5a40ef0 100644
--- a/src/mesa/drivers/dri/i965/brw_device_info.c
+++ b/src/mesa/drivers/dri/i965/brw_device_info.c
@@ -336,6 +336,15 @@ static const struct brw_device_info 
brw_device_info_skl_gt3 = {
 
 static const struct brw_device_info brw_device_info_skl_gt4 = {
GEN9_FEATURES, .gt = 4,
+   /* From the "L3 Allocation and Programming" documentation:
+*
+* "URB is limited to 1008KB due to programming restrictions.  This is not a
+* restriction of the L3 implementation, but of the FF and other clients.
+* Therefore, in a GT4 implementation it is possible for the programmed
+* allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
+* only 1008KB of this will be used."
+*/
+   .urb.size = 1008 / 3,
 };
 
 static const struct brw_device_info brw_device_info_bxt = {

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Mesa (11.0): vc4: Return NULL when we can' t make our shadow for a sampler view.

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: 9bbdd99d8ceb9c1064bacff7071590f6bbe2a8ed
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9bbdd99d8ceb9c1064bacff7071590f6bbe2a8ed

Author: Eric Anholt 
Date:   Mon Nov  9 08:56:01 2015 -0800

vc4: Return NULL when we can't make our shadow for a sampler view.

I'm not sure what the caller does is appropriate (just have a NULL sampler
at this slot), but it fixes the immediate crash.

Cc: "11.0" 
(cherry picked from commit 5980389bbf98b8186ba6a06392d92b82fa9efad3)

---

 src/gallium/drivers/vc4/vc4_state.c |4 
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/drivers/vc4/vc4_state.c 
b/src/gallium/drivers/vc4/vc4_state.c
index 8a759c2..996b158 100644
--- a/src/gallium/drivers/vc4/vc4_state.c
+++ b/src/gallium/drivers/vc4/vc4_state.c
@@ -581,6 +581,10 @@ vc4_create_sampler_view(struct pipe_context *pctx, struct 
pipe_resource *prsc,
 tmpl.last_level = cso->u.tex.last_level - 
cso->u.tex.first_level;
 
 prsc = vc4_resource_create(pctx->screen, );
+if (!prsc) {
+free(so);
+return NULL;
+}
 rsc = vc4_resource(prsc);
 clone = vc4_resource(prsc);
 clone->shadow_parent = _parent->base.b;

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Mesa (11.0): cherry-ignore: add the swrast front buffer support

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: f6e19f673e921901bf5a297800ab7faeaec6d38f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f6e19f673e921901bf5a297800ab7faeaec6d38f

Author: Emil Velikov 
Date:   Wed Nov 18 18:43:23 2015 +

cherry-ignore: add the swrast front buffer support

Although a sort of a bugfix, it causes many piglit regressions and even
lockup with llvmpipe.

Signed-off-by: Emil Velikov 

---

 bin/.cherry-ignore |5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index 1b133ec..04b723a 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -1,2 +1,5 @@
 # The commit base differs greatly between 11.0 and master
-2832ca95ecce064c7d841a3a374c2179f56161be glsl: fix stream qualifier for blocks 
with an instance name
\ No newline at end of file
+2832ca95ecce064c7d841a3a374c2179f56161be glsl: fix stream qualifier for blocks 
with an instance name
+
+# Somewhat of a mixed feature/bugfix patch, causing some 200 piglit regressions
+2b676570960277d47477822ffeccc672613f9142 gallium/swrast: fix front buffer 
blitting. (v2)

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Mesa (11.0): nouveau: don't expose HEVC decoding support

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: 09a7ee2782205b7b7177c8bc805be3c5929347dd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=09a7ee2782205b7b7177c8bc805be3c5929347dd

Author: Ilia Mirkin 
Date:   Sat Nov 14 10:28:55 2015 -0500

nouveau: don't expose HEVC decoding support

Signed-off-by: Ilia Mirkin 
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit f94e1d97381ec787c2abbbcd5265252596217e33)

---

 src/gallium/drivers/nouveau/nouveau_vp3_video.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/nouveau/nouveau_vp3_video.c 
b/src/gallium/drivers/nouveau/nouveau_vp3_video.c
index f3a64b2..4652e56 100644
--- a/src/gallium/drivers/nouveau/nouveau_vp3_video.c
+++ b/src/gallium/drivers/nouveau/nouveau_vp3_video.c
@@ -437,6 +437,7 @@ nouveau_vp3_screen_get_video_param(struct pipe_screen 
*pscreen,
   /* VP3 does not support MPEG4, VP4+ do. */
   return entrypoint == PIPE_VIDEO_ENTRYPOINT_BITSTREAM &&
  profile >= PIPE_VIDEO_PROFILE_MPEG1 &&
+ profile < PIPE_VIDEO_PROFILE_HEVC_MAIN &&
  (!vp3 || codec != PIPE_VIDEO_FORMAT_MPEG4) &&
  firmware_present(pscreen, profile);
case PIPE_VIDEO_CAP_NPOT_TEXTURES:

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Mesa (11.0): vc4: Return GL_OUT_OF_MEMORY when buffer allocation fails.

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: e54ac25120dbcfaf8cedef62c74bde97d32f2046
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e54ac25120dbcfaf8cedef62c74bde97d32f2046

Author: Eric Anholt 
Date:   Fri Nov  6 11:07:25 2015 -0800

vc4: Return GL_OUT_OF_MEMORY when buffer allocation fails.

I was afraid our callers weren't prepared for this, but it looks like
at least for resource creation, mesa/st throws an error appropriately.

Cc: "11.0" 
(cherry picked from commit eb8fb0064dbde7a363c2f99466a51b346b09a029)

---

 src/gallium/drivers/vc4/vc4_bufmgr.c   |5 ++--
 src/gallium/drivers/vc4/vc4_resource.c |   46 
 2 files changed, 32 insertions(+), 19 deletions(-)

diff --git a/src/gallium/drivers/vc4/vc4_bufmgr.c 
b/src/gallium/drivers/vc4/vc4_bufmgr.c
index 4766f2e..236284f 100644
--- a/src/gallium/drivers/vc4/vc4_bufmgr.c
+++ b/src/gallium/drivers/vc4/vc4_bufmgr.c
@@ -168,8 +168,9 @@ retry:
 vc4_bo_cache_free_all(>bo_cache);
 goto retry;
 }
-fprintf(stderr, "create ioctl failure\n");
-abort();
+
+free(bo);
+return NULL;
 }
 
 screen->bo_count++;
diff --git a/src/gallium/drivers/vc4/vc4_resource.c 
b/src/gallium/drivers/vc4/vc4_resource.c
index 5d5166f..f4317e8 100644
--- a/src/gallium/drivers/vc4/vc4_resource.c
+++ b/src/gallium/drivers/vc4/vc4_resource.c
@@ -35,11 +35,12 @@
 
 static bool miptree_debug = false;
 
-static void
+static bool
 vc4_resource_bo_alloc(struct vc4_resource *rsc)
 {
 struct pipe_resource *prsc = >base.b;
 struct pipe_screen *pscreen = prsc->screen;
+struct vc4_bo *bo;
 
 if (miptree_debug) {
 fprintf(stderr, "alloc %p: size %d + offset %d -> %d\n",
@@ -51,12 +52,18 @@ vc4_resource_bo_alloc(struct vc4_resource *rsc)
 rsc->cube_map_stride * (prsc->array_size - 1));
 }
 
-vc4_bo_unreference(>bo);
-rsc->bo = vc4_bo_alloc(vc4_screen(pscreen),
-   rsc->slices[0].offset +
-   rsc->slices[0].size +
-   rsc->cube_map_stride * (prsc->array_size - 1),
-   "resource");
+bo = vc4_bo_alloc(vc4_screen(pscreen),
+  rsc->slices[0].offset +
+  rsc->slices[0].size +
+  rsc->cube_map_stride * (prsc->array_size - 1),
+  "resource");
+if (bo) {
+vc4_bo_unreference(>bo);
+rsc->bo = bo;
+return true;
+} else {
+return false;
+}
 }
 
 static void
@@ -101,21 +108,27 @@ vc4_resource_transfer_map(struct pipe_context *pctx,
 char *buf;
 
 if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
-vc4_resource_bo_alloc(rsc);
+if (vc4_resource_bo_alloc(rsc)) {
 
-/* If it might be bound as one of our vertex buffers, make
- * sure we re-emit vertex buffer state.
- */
-if (prsc->bind & PIPE_BIND_VERTEX_BUFFER)
-vc4->dirty |= VC4_DIRTY_VTXBUF;
+/* If it might be bound as one of our vertex buffers,
+ * make sure we re-emit vertex buffer state.
+ */
+if (prsc->bind & PIPE_BIND_VERTEX_BUFFER)
+vc4->dirty |= VC4_DIRTY_VTXBUF;
+} else {
+/* If we failed to reallocate, flush everything so
+ * that we don't violate any syncing requirements.
+ */
+vc4_flush(pctx);
+}
 } else if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
 if (vc4_cl_references_bo(pctx, rsc->bo)) {
 if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 prsc->last_level == 0 &&
 prsc->width0 == box->width &&
 prsc->height0 == box->height &&
-prsc->depth0 == box->depth) {
-vc4_resource_bo_alloc(rsc);
+prsc->depth0 == box->depth &&
+vc4_resource_bo_alloc(rsc)) {
 if (prsc->bind & PIPE_BIND_VERTEX_BUFFER)
 vc4->dirty |= VC4_DIRTY_VTXBUF;
 } else {
@@ -389,8 +402,7 @@ vc4_resource_create(struct pipe_screen *pscreen,
 rsc->vc4_format = get_resource_texture_format(prsc);
 
 vc4_setup_slices(rsc);
-vc4_resource_bo_alloc(rsc);
-if (!rsc->bo)
+if (!vc4_resource_bo_alloc(rsc))
 

Mesa (11.0): radeon: fix bgrx8/xrgb8 blits

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: f112696f1531cdb658ada4290120781e30df2366
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f112696f1531cdb658ada4290120781e30df2366

Author: Roland Scheidegger 
Date:   Thu Nov 12 19:33:14 2015 +0100

radeon: fix bgrx8/xrgb8 blits

Since d21320f6258b2e1780a15c1ca718963d8a15ca18 the same txformat table entries
are used for "normal" texturing as well as for blits. However, I forgot to put
in an entry for the bgrx8 (le) and xrgb8 (be) formats - the normal texturing
path can't hit them because the radeon tex format chooser will never chose
them, but we get that format from the dri buffers (at least I assume we got
it from there). This caused lots of piglit regressions (and probably lots of
trouble outside piglit too).
This fixes bug https://bugs.freedesktop.org/show_bug.cgi?id=92900.

Tested-by: Ian Romanick 
Acked-by: Alex Deucher 
Reviewed-by: Marek Olšák 
Cc: "11.0" 
(cherry picked from commit 983614dbede7b94cba1bad9f3e8627fc5e14bb91)

---

 src/mesa/drivers/dri/radeon/radeon_tex.h |2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.h 
b/src/mesa/drivers/dri/radeon/radeon_tex.h
index f8ec432..37c2fa0 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tex.h
+++ b/src/mesa/drivers/dri/radeon/radeon_tex.h
@@ -63,6 +63,8 @@ static const struct tx_table tx_table[] =
[ MESA_FORMAT_R8G8B8A8_UNORM ] = { RADEON_TXFORMAT_RGBA | 
RADEON_TXFORMAT_ALPHA_IN_MAP, 0 },
[ MESA_FORMAT_B8G8R8A8_UNORM ] = { RADEON_TXFORMAT_ARGB | 
RADEON_TXFORMAT_ALPHA_IN_MAP, 0 },
[ MESA_FORMAT_A8R8G8B8_UNORM ] = { RADEON_TXFORMAT_ARGB | 
RADEON_TXFORMAT_ALPHA_IN_MAP, 0 },
+   [ MESA_FORMAT_B8G8R8X8_UNORM ] = { RADEON_TXFORMAT_ARGB, 0 },
+   [ MESA_FORMAT_X8R8G8B8_UNORM ] = { RADEON_TXFORMAT_ARGB, 0 },
[ MESA_FORMAT_BGR_UNORM8 ] = { RADEON_TXFORMAT_ARGB, 0 },
[ MESA_FORMAT_B5G6R5_UNORM ] = { RADEON_TXFORMAT_RGB565, 0 },
[ MESA_FORMAT_R5G6B5_UNORM ] = { RADEON_TXFORMAT_RGB565, 0 },

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Mesa (11.0): r200: fix bgrx8/xrgb8 blits

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: c667a0d1d36ea72cfc0024ae4a33f1443be98362
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c667a0d1d36ea72cfc0024ae4a33f1443be98362

Author: Roland Scheidegger 
Date:   Tue Nov 17 01:04:05 2015 +0100

r200: fix bgrx8/xrgb8 blits

Since 779cabfc7d022de8b7b9bc7fdac0caffa8646c51 the same txformat table entries
are used for "normal" texturing as well as for blits. However, I forgot to put
in an entry for the bgrx8 (le) and xrgb8 (be) formats - the normal texturing
path can't hit them because the radeon tex format chooser will never chose
them, but we get that format from the dri buffers (at least I assume we got
it from there).
This is untested but essentially addressing the same bug as for radeon.
(I don't think that the second entry per le/be table is actually necessary,
but shouldn't hurt...)

Tested-by: Ian Romanick 
Acked-by: Alex Deucher 
Reviewed-by: Marek Olšák 
Cc: "11.0" 
(cherry picked from commit a2611ffe4b5f1852c59301f086b988233a1c62f3)

---

 src/mesa/drivers/dri/r200/r200_tex.h |4 
 1 file changed, 4 insertions(+)

diff --git a/src/mesa/drivers/dri/r200/r200_tex.h 
b/src/mesa/drivers/dri/r200/r200_tex.h
index a8c31b7..14f5e71 100644
--- a/src/mesa/drivers/dri/r200/r200_tex.h
+++ b/src/mesa/drivers/dri/r200/r200_tex.h
@@ -63,7 +63,9 @@ static const struct tx_table tx_table_be[] =
[ MESA_FORMAT_A8B8G8R8_UNORM ] = { R200_TXFORMAT_ABGR | 
R200_TXFORMAT_ALPHA_IN_MAP, 0 },
[ MESA_FORMAT_R8G8B8A8_UNORM ] = { R200_TXFORMAT_RGBA | 
R200_TXFORMAT_ALPHA_IN_MAP, 0 },
[ MESA_FORMAT_B8G8R8A8_UNORM ] = { R200_TXFORMAT_ARGB | 
R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+   [ MESA_FORMAT_B8G8R8X8_UNORM ] = { R200_TXFORMAT_ARGB, 0 },
[ MESA_FORMAT_A8R8G8B8_UNORM ] = { R200_TXFORMAT_ARGB | 
R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+   [ MESA_FORMAT_X8R8G8B8_UNORM ] = { R200_TXFORMAT_ARGB, 0 },
[ MESA_FORMAT_BGR_UNORM8 ] = { 0x, 0 },
[ MESA_FORMAT_B5G6R5_UNORM ] = { R200_TXFORMAT_RGB565, 0 },
[ MESA_FORMAT_R5G6B5_UNORM ] = { R200_TXFORMAT_RGB565, 0 },
@@ -91,7 +93,9 @@ static const struct tx_table tx_table_le[] =
[ MESA_FORMAT_A8B8G8R8_UNORM ] = { R200_TXFORMAT_RGBA | 
R200_TXFORMAT_ALPHA_IN_MAP, 0 },
[ MESA_FORMAT_R8G8B8A8_UNORM ] = { R200_TXFORMAT_ABGR | 
R200_TXFORMAT_ALPHA_IN_MAP, 0 },
[ MESA_FORMAT_B8G8R8A8_UNORM ] = { R200_TXFORMAT_ARGB | 
R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+   [ MESA_FORMAT_B8G8R8X8_UNORM ] = { R200_TXFORMAT_ARGB, 0 },
[ MESA_FORMAT_A8R8G8B8_UNORM ] = { R200_TXFORMAT_ARGB | 
R200_TXFORMAT_ALPHA_IN_MAP, 0 },
+   [ MESA_FORMAT_X8R8G8B8_UNORM ] = { R200_TXFORMAT_ARGB, 0 },
[ MESA_FORMAT_BGR_UNORM8 ] = { R200_TXFORMAT_ARGB, 0 },
[ MESA_FORMAT_B5G6R5_UNORM ] = { R200_TXFORMAT_RGB565, 0 },
[ MESA_FORMAT_R5G6B5_UNORM ] = { R200_TXFORMAT_RGB565, 0 },

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Mesa (11.0): meta/generate_mipmap: Only modify the draw framebuffer binding in fallback_required

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: acbaa3d0fcd2a0d357a4c7539d12877f9838548a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=acbaa3d0fcd2a0d357a4c7539d12877f9838548a

Author: Ian Romanick 
Date:   Fri Nov 13 11:58:41 2015 -0800

meta/generate_mipmap: Only modify the draw framebuffer binding in 
fallback_required

Previously GL_FRAMEBUFFER was used.  However, if GL_EXT_framebuffer_blit
is supported (note: it is supported by every Mesa driver), this is
*sometimes* an alias for GL_DRAW_FRAMEBUFFER (getters) and *sometimes*
an alias for *both* GL_DRAW_FRAMEBUFFER and GL_READ_FRAMEBUFFER
(setters).  As a result, the code saved one binding but modified both.
If the bindings were different, the GL_READ_FRAMEBUFFER would be
incorrect on exit.

Fixes the piglit fbo-generatemipmap-versus-READ_FRAMEBUFFER test.

Ideally this function would use DSA functions and not modify the binding
at all.  However, that would be a much more intrusive change because
_mesa_meta_bind_fbo_image would also need to be modified.
_mesa_meta_bind_fbo_image has a lot of callers.  Much of this code is
about to get a major rework due to bug #92363, so I don't think it
matters too much.  In fact, I discovered this bug while working on the
other bug.  Le bon temps!

Signed-off-by: Ian Romanick 
Reviewed-by: Anuj Phogat 
Cc: "10.6 11.0" 
(cherry picked from commit c40a88b6c5a698e5297957e28cccf2ce23820caa)

---

 src/mesa/drivers/common/meta_generate_mipmap.c |8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/common/meta_generate_mipmap.c 
b/src/mesa/drivers/common/meta_generate_mipmap.c
index ced4742..9d3b9b6 100644
--- a/src/mesa/drivers/common/meta_generate_mipmap.c
+++ b/src/mesa/drivers/common/meta_generate_mipmap.c
@@ -102,13 +102,13 @@ fallback_required(struct gl_context *ctx, GLenum target,
 */
if (!mipmap->FBO)
   _mesa_GenFramebuffers(1, >FBO);
-   _mesa_BindFramebuffer(GL_FRAMEBUFFER_EXT, mipmap->FBO);
+   _mesa_BindFramebuffer(GL_DRAW_FRAMEBUFFER, mipmap->FBO);
 
-   _mesa_meta_bind_fbo_image(GL_FRAMEBUFFER, GL_COLOR_ATTACHMENT0, baseImage, 
0);
+   _mesa_meta_bind_fbo_image(GL_DRAW_FRAMEBUFFER, GL_COLOR_ATTACHMENT0, 
baseImage, 0);
 
-   status = _mesa_CheckFramebufferStatus(GL_FRAMEBUFFER_EXT);
+   status = _mesa_CheckFramebufferStatus(GL_DRAW_FRAMEBUFFER);
 
-   _mesa_BindFramebuffer(GL_FRAMEBUFFER_EXT, fboSave);
+   _mesa_BindFramebuffer(GL_DRAW_FRAMEBUFFER, fboSave);
 
if (status != GL_FRAMEBUFFER_COMPLETE_EXT) {
   _mesa_perf_debug(ctx, MESA_DEBUG_SEVERITY_HIGH,

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Mesa (11.0): glsl: Allow implicit int -> uint conversions for the % operator.

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: 120559bd3042b8ab0eab3f0b3c3ab10594043d41
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=120559bd3042b8ab0eab3f0b3c3ab10594043d41

Author: Kenneth Graunke 
Date:   Thu Nov 12 13:02:05 2015 -0800

glsl: Allow implicit int -> uint conversions for the % operator.

GLSL 4.00 and GL_ARB_gpu_shader5 introduced a new int -> uint implicit
conversion rule and updated the rules for modulus to use them.  (In
earlier languages, none of the implicit conversion rules did anything
relevant, so there was no point in applying them.)

This allows expressions such as:

   int foo;
   uint bar;
   uint mod = foo % bar;

Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Kenneth Graunke 
Reviewed-by: Ian Romanick 
(cherry picked from commit 511de1a80cedc0add386dad79cce56dd68d2f611)

---

 src/glsl/ast_to_hir.cpp |   37 -
 1 file changed, 28 insertions(+), 9 deletions(-)

diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 9fdfd44..94bae57 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -482,18 +482,20 @@ bit_logic_result_type(const struct glsl_type *type_a,
 }
 
 static const struct glsl_type *
-modulus_result_type(const struct glsl_type *type_a,
-const struct glsl_type *type_b,
+modulus_result_type(ir_rvalue * _a, ir_rvalue * _b,
 struct _mesa_glsl_parse_state *state, YYLTYPE *loc)
 {
+   const glsl_type *type_a = value_a->type;
+   const glsl_type *type_b = value_b->type;
+
if (!state->check_version(130, 300, loc, "operator '%%' is reserved")) {
   return glsl_type::error_type;
}
 
-   /* From GLSL 1.50 spec, page 56:
+   /* Section 5.9 (Expressions) of the GLSL 4.00 specification says:
+*
 *"The operator modulus (%) operates on signed or unsigned integers or
-*integer vectors. The operand types must both be signed or both be
-*unsigned."
+*integer vectors."
 */
if (!type_a->is_integer()) {
   _mesa_glsl_error(loc, state, "LHS of operator %% must be an integer");
@@ -503,11 +505,28 @@ modulus_result_type(const struct glsl_type *type_a,
   _mesa_glsl_error(loc, state, "RHS of operator %% must be an integer");
   return glsl_type::error_type;
}
-   if (type_a->base_type != type_b->base_type) {
+
+   /*"If the fundamental types in the operands do not match, then the
+*conversions from section 4.1.10 "Implicit Conversions" are applied
+*to create matching types."
+*
+* Note that GLSL 4.00 (and GL_ARB_gpu_shader5) introduced implicit
+* int -> uint conversion rules.  Prior to that, there were no implicit
+* conversions.  So it's harmless to apply them universally - no implicit
+* conversions will exist.  If the types don't match, we'll receive false,
+* and raise an error, satisfying the GLSL 1.50 spec, page 56:
+*
+*"The operand types must both be signed or unsigned."
+*/
+   if (!apply_implicit_conversion(type_a, value_b, state) &&
+   !apply_implicit_conversion(type_b, value_a, state)) {
   _mesa_glsl_error(loc, state,
-   "operands of %% must have the same base type");
+   "could not implicitly convert operands to "
+   "modulus (%%) operator");
   return glsl_type::error_type;
}
+   type_a = value_a->type;
+   type_b = value_b->type;
 
/*"The operands cannot be vectors of differing size. If one operand is
 *a scalar and the other vector, then the scalar is applied component-
@@ -1267,7 +1286,7 @@ ast_expression::do_hir(exec_list *instructions,
   op[0] = this->subexpressions[0]->hir(instructions, state);
   op[1] = this->subexpressions[1]->hir(instructions, state);
 
-  type = modulus_result_type(op[0]->type, op[1]->type, state, & loc);
+  type = modulus_result_type(op[0], op[1], state, );
 
   assert(operations[this->oper] == ir_binop_mod);
 
@@ -1514,7 +1533,7 @@ ast_expression::do_hir(exec_list *instructions,
   op[0] = this->subexpressions[0]->hir(instructions, state);
   op[1] = this->subexpressions[1]->hir(instructions, state);
 
-  type = modulus_result_type(op[0]->type, op[1]->type, state, & loc);
+  type = modulus_result_type(op[0], op[1], state, );
 
   assert(operations[this->oper] == ir_binop_mod);
 

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Mesa (11.0): vc4: Add support for nir_op_uge, using the carry bit on QPU_A_SUB.

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: d425a2f26c15156cc60a1b48e59bb6fc1cdcebbf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d425a2f26c15156cc60a1b48e59bb6fc1cdcebbf

Author: Eric Anholt 
Date:   Tue Nov 10 15:37:47 2015 -0800

vc4: Add support for nir_op_uge, using the carry bit on QPU_A_SUB.

It looks like nir_lower_idiv is going to use it soon, so add support.
With Ilia's change, this fixes one case in fs-op-div-large-uint-uint (with
GL 3.0 forced on).

Cc: "11.0" 
(cherry picked from commit a4bf28178f064082d3b818d2cd48abf9075cc459)
[Emil Velikov: Resolve trivial conflicts]
Signed-off-by: Emil Velikov 

Conflicts:
src/gallium/drivers/vc4/vc4_qpu_emit.c

---

 src/gallium/drivers/vc4/vc4_opt_algebraic.c |2 ++
 src/gallium/drivers/vc4/vc4_program.c   |4 
 src/gallium/drivers/vc4/vc4_qir.c   |8 
 src/gallium/drivers/vc4/vc4_qir.h   |8 
 src/gallium/drivers/vc4/vc4_qpu_emit.c  |4 
 5 files changed, 26 insertions(+)

diff --git a/src/gallium/drivers/vc4/vc4_opt_algebraic.c 
b/src/gallium/drivers/vc4/vc4_opt_algebraic.c
index 5b43583..5b018e4 100644
--- a/src/gallium/drivers/vc4/vc4_opt_algebraic.c
+++ b/src/gallium/drivers/vc4/vc4_opt_algebraic.c
@@ -143,6 +143,8 @@ qir_opt_algebraic(struct vc4_compile *c)
 case QOP_SEL_X_Y_ZC:
 case QOP_SEL_X_Y_NS:
 case QOP_SEL_X_Y_NC:
+case QOP_SEL_X_Y_CS:
+case QOP_SEL_X_Y_CC:
 if (is_zero(c, inst->src[1])) {
 /* Replace references to a 0 uniform value
  * with the SEL_X_0 equivalent.
diff --git a/src/gallium/drivers/vc4/vc4_program.c 
b/src/gallium/drivers/vc4/vc4_program.c
index e002983..8476833 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -1055,6 +1055,10 @@ ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
 qir_SF(c, qir_SUB(c, src[0], src[1]));
 *dest = qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
 break;
+case nir_op_uge:
+qir_SF(c, qir_SUB(c, src[0], src[1]));
+*dest = qir_SEL_X_0_CC(c, qir_uniform_ui(c, ~0));
+break;
 case nir_op_ilt:
 qir_SF(c, qir_SUB(c, src[0], src[1]));
 *dest = qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
diff --git a/src/gallium/drivers/vc4/vc4_qir.c 
b/src/gallium/drivers/vc4/vc4_qir.c
index 073ba5f..50e37e8 100644
--- a/src/gallium/drivers/vc4/vc4_qir.c
+++ b/src/gallium/drivers/vc4/vc4_qir.c
@@ -62,10 +62,14 @@ static const struct qir_op_info qir_op_info[] = {
 [QOP_SEL_X_0_NC] = { "fsel_x_0_nc", 1, 1, false, true },
 [QOP_SEL_X_0_ZS] = { "fsel_x_0_zs", 1, 1, false, true },
 [QOP_SEL_X_0_ZC] = { "fsel_x_0_zc", 1, 1, false, true },
+[QOP_SEL_X_0_CS] = { "fsel_x_0_cs", 1, 1, false, true },
+[QOP_SEL_X_0_CC] = { "fsel_x_0_cc", 1, 1, false, true },
 [QOP_SEL_X_Y_NS] = { "fsel_x_y_ns", 1, 2, false, true },
 [QOP_SEL_X_Y_NC] = { "fsel_x_y_nc", 1, 2, false, true },
 [QOP_SEL_X_Y_ZS] = { "fsel_x_y_zs", 1, 2, false, true },
 [QOP_SEL_X_Y_ZC] = { "fsel_x_y_zc", 1, 2, false, true },
+[QOP_SEL_X_Y_CS] = { "fsel_x_y_cs", 1, 2, false, true },
+[QOP_SEL_X_Y_CC] = { "fsel_x_y_cc", 1, 2, false, true },
 
 [QOP_RCP] = { "rcp", 1, 1, false, true },
 [QOP_RSQ] = { "rsq", 1, 1, false, true },
@@ -193,10 +197,14 @@ qir_depends_on_flags(struct qinst *inst)
 case QOP_SEL_X_0_NC:
 case QOP_SEL_X_0_ZS:
 case QOP_SEL_X_0_ZC:
+case QOP_SEL_X_0_CS:
+case QOP_SEL_X_0_CC:
 case QOP_SEL_X_Y_NS:
 case QOP_SEL_X_Y_NC:
 case QOP_SEL_X_Y_ZS:
 case QOP_SEL_X_Y_ZC:
+case QOP_SEL_X_Y_CS:
+case QOP_SEL_X_Y_CC:
 return true;
 default:
 return false;
diff --git a/src/gallium/drivers/vc4/vc4_qir.h 
b/src/gallium/drivers/vc4/vc4_qir.h
index a2b21fa..fe8b582 100644
--- a/src/gallium/drivers/vc4/vc4_qir.h
+++ b/src/gallium/drivers/vc4/vc4_qir.h
@@ -91,11 +91,15 @@ enum qop {
 QOP_SEL_X_0_ZC,
 QOP_SEL_X_0_NS,
 QOP_SEL_X_0_NC,
+QOP_SEL_X_0_CS,
+QOP_SEL_X_0_CC,
 /* Selects the src[0] if the ns flag bit is set, otherwise src[1]. */
 QOP_SEL_X_Y_ZS,
 QOP_SEL_X_Y_ZC,
 QOP_SEL_X_Y_NS,
 QOP_SEL_X_Y_NC,
+QOP_SEL_X_Y_CS,
+QOP_SEL_X_Y_CC,
 
 QOP_FTOI,
 QOP_ITOF,
@@ -570,10 +574,14 @@ QIR_ALU1(SEL_X_0_ZS)
 QIR_ALU1(SEL_X_0_ZC)
 QIR_ALU1(SEL_X_0_NS)
 QIR_ALU1(SEL_X_0_NC)
+QIR_ALU1(SEL_X_0_CS)
+QIR_ALU1(SEL_X_0_CC)
 QIR_ALU2(SEL_X_Y_ZS)
 QIR_ALU2(SEL_X_Y_ZC)
 QIR_ALU2(SEL_X_Y_NS)
 QIR_ALU2(SEL_X_Y_NC)
+QIR_ALU2(SEL_X_Y_CS)

Mesa (11.0): winsys/radeon: Use CPU page size instead of hardcoding 4096 bytes v3

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: 312ec1946db465faca6c97b0bee07d6ecaf2f83d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=312ec1946db465faca6c97b0bee07d6ecaf2f83d

Author: Michel Dänzer 
Date:   Thu Aug 21 18:30:44 2014 +0900

winsys/radeon: Use CPU page size instead of hardcoding 4096 bytes v3

Fixes GPUVM conflicts with non-4K page size.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92738

v2: Replace sanitization of VM base address alignment with comment why
that's not necessary.
v3: Use unsigned instead of long as the type for the size_align member.
(Marek)

Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Christian König  (v1)
Reviewed-by: Marek Olšák 
(cherry picked from commit 24abbaff9ad177624c2b4906c7d94f5d91ac3cc0)

---

 src/gallium/winsys/radeon/drm/radeon_drm_bo.c |   30 -
 1 file changed, 19 insertions(+), 11 deletions(-)

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 7c19876..9fd469b 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -76,6 +76,9 @@ struct radeon_bomgr {
 bool va;
 uint64_t va_offset;
 struct list_head va_holes;
+
+/* BO size alignment */
+unsigned size_align;
 };
 
 static inline struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr)
@@ -164,8 +167,10 @@ static uint64_t radeon_bomgr_find_va(struct radeon_bomgr 
*mgr, uint64_t size, ui
 struct radeon_bo_va_hole *hole, *n;
 uint64_t offset = 0, waste = 0;
 
-alignment = MAX2(alignment, 4096);
-size = align(size, 4096);
+/* All VM address space holes will implicitly start aligned to the
+ * size alignment, so we don't need to sanitize the alignment here
+ */
+size = align(size, mgr->size_align);
 
 pipe_mutex_lock(mgr->bo_va_mutex);
 /* first look for a hole */
@@ -222,7 +227,7 @@ static void radeon_bomgr_free_va(struct radeon_bomgr *mgr, 
uint64_t va, uint64_t
 {
 struct radeon_bo_va_hole *hole;
 
-size = align(size, 4096);
+size = align(size, mgr->size_align);
 
 pipe_mutex_lock(mgr->bo_va_mutex);
 if ((va + size) == mgr->va_offset) {
@@ -333,9 +338,9 @@ static void radeon_bo_destroy(struct pb_buffer *_buf)
 pipe_mutex_destroy(bo->map_mutex);
 
 if (bo->initial_domain & RADEON_DOMAIN_VRAM)
-bo->rws->allocated_vram -= align(bo->base.size, 4096);
+bo->rws->allocated_vram -= align(bo->base.size, mgr->size_align);
 else if (bo->initial_domain & RADEON_DOMAIN_GTT)
-bo->rws->allocated_gtt -= align(bo->base.size, 4096);
+bo->rws->allocated_gtt -= align(bo->base.size, mgr->size_align);
 FREE(bo);
 }
 
@@ -620,9 +625,9 @@ static struct pb_buffer *radeon_bomgr_create_bo(struct 
pb_manager *_mgr,
 }
 
 if (rdesc->initial_domains & RADEON_DOMAIN_VRAM)
-rws->allocated_vram += align(size, 4096);
+rws->allocated_vram += align(size, mgr->size_align);
 else if (rdesc->initial_domains & RADEON_DOMAIN_GTT)
-rws->allocated_gtt += align(size, 4096);
+rws->allocated_gtt += align(size, mgr->size_align);
 
 return >base;
 }
@@ -696,6 +701,9 @@ struct pb_manager *radeon_bomgr_create(struct 
radeon_drm_winsys *rws)
 mgr->va_offset = rws->va_start;
 list_inithead(>va_holes);
 
+/* TTM aligns the BO size to the CPU page size */
+mgr->size_align = sysconf(_SC_PAGESIZE);
+
 return >base;
 }
 
@@ -858,7 +866,7 @@ radeon_winsys_bo_create(struct radeon_winsys *rws,
  * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
  * like constant/uniform buffers, can benefit from better and more reuse.
  */
-size = align(size, 4096);
+size = align(size, mgr->size_align);
 
 /* Only set one usage bit each for domains and flags, or the cache manager
  * might consider different sets of domains / flags compatible
@@ -969,7 +977,7 @@ static struct pb_buffer *radeon_winsys_bo_from_ptr(struct 
radeon_winsys *rws,
 pipe_mutex_unlock(mgr->bo_handles_mutex);
 }
 
-ws->allocated_gtt += align(bo->base.size, 4096);
+ws->allocated_gtt += align(bo->base.size, mgr->size_align);
 
 return (struct pb_buffer*)bo;
 }
@@ -1106,9 +1114,9 @@ done:
 bo->initial_domain = radeon_bo_get_initial_domain((void*)bo);
 
 if (bo->initial_domain & RADEON_DOMAIN_VRAM)
-ws->allocated_vram += align(bo->base.size, 4096);
+ws->allocated_vram += align(bo->base.size, mgr->size_align);
 else if (bo->initial_domain & RADEON_DOMAIN_GTT)
-ws->allocated_gtt += align(bo->base.size, 4096);
+ws->allocated_gtt += align(bo->base.size, mgr->size_align);
 
 return (struct pb_buffer*)bo;
 

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Mesa (11.0): radeonsi: initialize SX_PS_DOWNCONVERT to 0 on Stoney

[Emil Velikov]

Module: Mesa
Branch: 11.0
Commit: f9325a97b31fdeca74f861315a9654e006d222d5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9325a97b31fdeca74f861315a9654e006d222d5

Author: Marek Olšák 
Date:   Thu Nov  5 23:56:38 2015 +0100

radeonsi: initialize SX_PS_DOWNCONVERT to 0 on Stoney

otherwise the SX or CB blocks can go bananas

Reviewed-by: Nicolai Hähnle 
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit 40912dd91e96376517fb41bb4dc228b45fd1a01c)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov 

Conflicts:
src/gallium/drivers/radeonsi/si_state.c

---

 src/gallium/drivers/radeonsi/si_state.c |3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 6dde38c..1bca645 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3342,5 +3342,8 @@ static void si_init_config(struct si_context *sctx)
si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
}
 
+   if (sctx->b.family == CHIP_STONEY)
+   si_pm4_set_reg(pm4, R_028754_SX_PS_DOWNCONVERT, 0);
+
sctx->init_config = pm4;
 }

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Mesa (master): glsl: Add ir_samples_identical opcode

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 8343583557fbbf0e04ce8e834a71f00b219232ce
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8343583557fbbf0e04ce8e834a71f00b219232ce

Author: Ian Romanick 
Date:   Tue Nov 17 16:54:31 2015 -0800

glsl: Add ir_samples_identical opcode

Signed-off-by: Ian Romanick 
Reviewed-by: Kenneth Graunke 
Reviewed-by: Chris Forbes 

---

 src/glsl/ir.cpp|6 +-
 src/glsl/ir.h  |2 ++
 src/glsl/ir_clone.cpp  |1 +
 src/glsl/ir_equals.cpp |1 +
 src/glsl/ir_hv_accept.cpp  |1 +
 src/glsl/ir_print_visitor.cpp  |   10 ++
 src/glsl/ir_rvalue_visitor.cpp |1 +
 src/glsl/opt_tree_grafting.cpp |1 +
 src/mesa/program/ir_to_mesa.cpp|2 ++
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp |2 ++
 10 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/src/glsl/ir.cpp b/src/glsl/ir.cpp
index 80cbdbf..f47100e 100644
--- a/src/glsl/ir.cpp
+++ b/src/glsl/ir.cpp
@@ -1421,7 +1421,7 @@ ir_dereference::is_lvalue() const
 }
 
 
-static const char * const tex_opcode_strs[] = { "tex", "txb", "txl", "txd", 
"txf", "txf_ms", "txs", "lod", "tg4", "query_levels", "texture_samples" };
+static const char * const tex_opcode_strs[] = { "tex", "txb", "txl", "txd", 
"txf", "txf_ms", "txs", "lod", "tg4", "query_levels", "texture_samples", 
"samples_identical" };
 
 const char *ir_texture::opcode_string()
 {
@@ -1455,6 +1455,10 @@ ir_texture::set_sampler(ir_dereference *sampler, const 
glsl_type *type)
} else if (this->op == ir_lod) {
   assert(type->vector_elements == 2);
   assert(type->base_type == GLSL_TYPE_FLOAT);
+   } else if (this->op == ir_samples_identical) {
+  assert(type == glsl_type::bool_type);
+  assert(sampler->type->base_type == GLSL_TYPE_SAMPLER);
+  assert(sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_MS);
} else {
   assert(sampler->type->sampler_type == (int) type->base_type);
   if (sampler->type->sampler_shadow)
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index d59dee1..39156e0 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -1965,6 +1965,7 @@ enum ir_texture_opcode {
ir_tg4, /**< Texture gather */
ir_query_levels, /**< Texture levels query */
ir_texture_samples,  /**< Texture samples query */
+   ir_samples_identical, /**< Query whether all samples are definitely 
identical. */
 };
 
 
@@ -1991,6 +1992,7 @@ enum ir_texture_opcode {
  * (lod   )
  * (tg4 )
  * (query_levels  )
+ * (samples_identical  )
  */
 class ir_texture : public ir_rvalue {
 public:
diff --git a/src/glsl/ir_clone.cpp b/src/glsl/ir_clone.cpp
index a2cd672..4484cc9 100644
--- a/src/glsl/ir_clone.cpp
+++ b/src/glsl/ir_clone.cpp
@@ -223,6 +223,7 @@ ir_texture::clone(void *mem_ctx, struct hash_table *ht) 
const
case ir_lod:
case ir_query_levels:
case ir_texture_samples:
+   case ir_samples_identical:
   break;
case ir_txb:
   new_tex->lod_info.bias = this->lod_info.bias->clone(mem_ctx, ht);
diff --git a/src/glsl/ir_equals.cpp b/src/glsl/ir_equals.cpp
index aafcd1f..b86f4ea 100644
--- a/src/glsl/ir_equals.cpp
+++ b/src/glsl/ir_equals.cpp
@@ -157,6 +157,7 @@ ir_texture::equals(const ir_instruction *ir, enum 
ir_node_type ignore) const
case ir_lod:
case ir_query_levels:
case ir_texture_samples:
+   case ir_samples_identical:
   break;
case ir_txb:
   if (!lod_info.bias->equals(other->lod_info.bias, ignore))
diff --git a/src/glsl/ir_hv_accept.cpp b/src/glsl/ir_hv_accept.cpp
index 6495cc4..213992a 100644
--- a/src/glsl/ir_hv_accept.cpp
+++ b/src/glsl/ir_hv_accept.cpp
@@ -195,6 +195,7 @@ ir_texture::accept(ir_hierarchical_visitor *v)
case ir_lod:
case ir_query_levels:
case ir_texture_samples:
+   case ir_samples_identical:
   break;
case ir_txb:
   s = this->lod_info.bias->accept(v);
diff --git a/src/glsl/ir_print_visitor.cpp b/src/glsl/ir_print_visitor.cpp
index 42b03fd..fd7bc2e 100644
--- a/src/glsl/ir_print_visitor.cpp
+++ b/src/glsl/ir_print_visitor.cpp
@@ -268,6 +268,14 @@ void ir_print_visitor::visit(ir_texture *ir)
 {
fprintf(f, "(%s ", ir->opcode_string());
 
+   if (ir->op == ir_samples_identical) {
+  ir->sampler->accept(this);
+  fprintf(f, " ");
+  ir->coordinate->accept(this);
+  fprintf(f, ")");
+  return;
+   }
+
print_type(f, ir->type);
fprintf(f, " ");
 
@@ -334,6 +342,8 @@ void ir_print_visitor::visit(ir_texture *ir)
case ir_tg4:
   ir->lod_info.component->accept(this);
   break;
+   case ir_samples_identical:
+  unreachable(!"ir_samples_identical was already handled");
};
fprintf(f, ")");
 }
diff --git a/src/glsl/ir_rvalue_visitor.cpp b/src/glsl/ir_rvalue_visitor.cpp
index a6966f5..6486838 100644
--- 

Mesa (master): Import current draft of EXT_shader_samples_identical spec

[Ian Romanick]

Module: Mesa
Branch: master
Commit: b1b9f68d4cc29130d0cb6219b02e13c67c0c7f10
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1b9f68d4cc29130d0cb6219b02e13c67c0c7f10

Author: Ian Romanick 
Date:   Tue Nov 17 15:26:27 2015 -0800

Import current draft of EXT_shader_samples_identical spec

v2: Add Neil to the list of contributors.  I meant to do that before,
but Matt reminded me.

v3: Fix typos noticed by Nicolai.

Signed-off-by: Ian Romanick 
Reviewed-by: Kenneth Graunke 
Reviewed-by: Chris Forbes 

---

 docs/specs/EXT_shader_samples_identical.txt |  176 +++
 1 file changed, 176 insertions(+)

diff --git a/docs/specs/EXT_shader_samples_identical.txt 
b/docs/specs/EXT_shader_samples_identical.txt
new file mode 100644
index 000..a8a901b
--- /dev/null
+++ b/docs/specs/EXT_shader_samples_identical.txt
@@ -0,0 +1,176 @@
+Name
+
+EXT_shader_samples_identical
+
+Name Strings
+
+GL_EXT_shader_samples_identical
+
+Contact
+
+Ian Romanick, Intel (ian.d.romanick 'at' intel.com)
+
+Contributors
+
+Chris Forbes, Mesa
+Magnus Wendt, Intel
+Neil S. Roberts, Intel
+Graham Sellers, AMD
+
+Status
+
+XXX - Not complete yet.
+
+Version
+
+Last Modified Date: November 19, 2015
+Revision: 6
+
+Number
+
+TBD
+
+Dependencies
+
+OpenGL 3.2, or OpenGL ES 3.1, or ARB_texture_multisample is required.
+
+This extension is written against the OpenGL 4.5 (Core Profile)
+Specification
+
+Overview
+
+Multisampled antialiasing has become a common method for improving the
+quality of rendered images.  Multisampling differs from supersampling in
+that the color of a primitive that covers all or part of a pixel is
+resolved once, regardless of the number of samples covered.  If a large
+polygon is rendered, the colors of all samples in each interior pixel will
+be the same.  This suggests a simple compression scheme that can reduce
+the necessary memory bandwidth requirements.  In one such scheme, each
+sample is stored in a separate slice of the multisample surface.  An
+additional multisample control surface (MCS) contains a mapping from pixel
+samples to slices.
+
+If all the values stored in the MCS for a particular pixel are the same,
+then all the samples have the same value.  Applications can take advantage
+of this information to reduce the bandwidth of reading multisample
+textures.  A custom multisample resolve filter could optimize resolving
+pixels where every sample is identical by reading the color once.
+
+color = texelFetch(sampler, coordinate, 0);
+if (!textureSamplesIdenticalEXT(sampler, coordinate)) {
+for (int i = 1; i < MAX_SAMPLES; i++) {
+vec4 c = texelFetch(sampler, coordinate, i);
+
+//... accumulate c into color
+
+}
+}
+
+New Procedures and Functions
+
+None.
+
+New Tokens
+
+None.
+
+Additions to the OpenGL 4.5 (Core Profile) Specification
+
+None.
+
+Modifications to The OpenGL Shading Language Specification, Version 4.50.5
+
+Including the following line in a shader can be used to control the
+language features described in this extension:
+
+#extension GL_EXT_shader_samples_identical
+
+A new preprocessor #define is added to the OpenGL Shading Language:
+
+#define GL_EXT_shader_samples_identical
+
+Add to the table in section 8.7 "Texture Lookup Functions"
+
+Syntax:
+
+bool textureSamplesIdenticalEXT(gsampler2DMS sampler, ivec2 coord)
+
+bool textureSamplesIdenticalEXT(gsampler2DMSArray sampler,
+ivec3 coord)
+
+Description:
+
+Returns true if it can be determined that all samples within the texel
+of the multisample texture bound to  at  contain the
+same values or false if this cannot be determined."
+
+Additions to the AGL/EGL/GLX/WGL Specifications
+
+None
+
+Errors
+
+None
+
+New State
+
+None
+
+New Implementation Dependent State
+
+None
+
+Issues
+
+1) What should the new functions be called?
+
+RESOLVED: textureSamplesIdenticalEXT.  Initially
+textureAllSamplesIdenticalEXT was considered, but
+textureSamplesIdenticalEXT is more similar to the existing textureSamples
+function.
+
+2) It seems like applications could implement additional optimization if
+   they were provided with raw MCS data.  Should this extension also
+   provide that data?
+
+There are a number of challenges in providing raw MCS data.  The biggest
+problem being that the amount of MCS data depends on the number of
+samples, and that is not known at compile time.  Additionally, without new
+texelFetch functions, applications would have difficulty utilizing the
+information.
+
+Another option is to have a function that returns an array of 

Mesa (master): i965: Enable EXT_shader_samples_identical

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 99840eb983f74cd447546f7205c8c9f505ef82c8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=99840eb983f74cd447546f7205c8c9f505ef82c8

Author: Ian Romanick 
Date:   Tue Nov 17 17:57:08 2015 -0800

i965: Enable EXT_shader_samples_identical

On the vec4 backend, textureSamplesIdentical() will always return
false.  There are currently no test cases for the vec4 backend, so we
don't have much confidence in any implementation.  We also don't think
anyone is likely to miss it.

v2: Handle immediate value for MCS smarter.  Rebase on changes to
nir_texop_sampels_identical (missing second parameter).  Suggested by
Jason.

v3: Add Neil's code to handle 16x MSAA in the FS.  Also rebase on top of
f9a9ba5e.  Stub out the vec4 implementation.

Signed-off-by: Ian Romanick 
Signed-off-by: Neil Roberts 
Reviewed-by: Jason Ekstrand  [v2]
Reviewed-by: Chris Forbes  [v2]

---

 src/mesa/drivers/dri/i965/brw_fs_nir.cpp   |4 +++-
 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp   |   20 
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp |4 +++-
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |7 +++
 src/mesa/drivers/dri/i965/intel_extensions.c   |1 +
 5 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 8fc7ee4..b6e5ed6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -2625,6 +2625,7 @@ fs_visitor::nir_emit_texture(const fs_builder , 
nir_tex_instr *instr)
  switch (instr->op) {
  case nir_texop_txf:
  case nir_texop_txf_ms:
+ case nir_texop_samples_identical:
 coordinate = retype(src, BRW_REGISTER_TYPE_D);
 break;
  default:
@@ -2687,7 +2688,8 @@ fs_visitor::nir_emit_texture(const fs_builder , 
nir_tex_instr *instr)
   }
}
 
-   if (instr->op == nir_texop_txf_ms) {
+   if (instr->op == nir_texop_txf_ms ||
+   instr->op == nir_texop_samples_identical) {
   if (devinfo->gen >= 7 &&
   key_tex->compressed_multisample_layout_mask & (1 << sampler)) {
  mcs = emit_mcs_fetch(coordinate, instr->coord_components, 
sampler_reg);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index d97fcf3..2e04134 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -259,6 +259,26 @@ fs_visitor::emit_texture(ir_texture_opcode op,
   lod = brw_imm_ud(0u);
}
 
+   if (op == ir_samples_identical) {
+  fs_reg dst = vgrf(glsl_type::get_instance(dest_type->base_type, 1, 1));
+
+  /* If mcs is an immediate value, it means there is no MCS.  In that case
+   * just return false.
+   */
+  if (mcs.file == BRW_IMMEDIATE_VALUE) {
+ bld.MOV(dst, brw_imm_ud(0u));
+  } else if ((key_tex->msaa_16 & (1 << sampler))) {
+ fs_reg tmp = vgrf(glsl_type::uint_type);
+ bld.OR(tmp, mcs, offset(mcs, bld, 1));
+ bld.CMP(dst, tmp, brw_imm_ud(0u), BRW_CONDITIONAL_EQ);
+  } else {
+ bld.CMP(dst, mcs, brw_imm_ud(0u), BRW_CONDITIONAL_EQ);
+  }
+
+  this->result = dst;
+  return;
+   }
+
if (coordinate.file != BAD_FILE) {
   /* FINISHME: Texture coordinate rescaling doesn't work with non-constant
* samplers.  This should only be a problem with GL_CLAMP on Gen7.
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 63696a7..28656d4 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -1615,6 +1615,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
  switch (instr->op) {
  case nir_texop_txf:
  case nir_texop_txf_ms:
+ case nir_texop_samples_identical:
 coordinate = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_D,
  src_size);
 coord_type = glsl_type::ivec(src_size);
@@ -1695,7 +1696,8 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
   }
}
 
-   if (instr->op == nir_texop_txf_ms) {
+   if (instr->op == nir_texop_txf_ms ||
+   instr->op == nir_texop_samples_identical) {
   assert(coord_type != NULL);
   if (devinfo->gen >= 7 &&
   key_tex->compressed_multisample_layout_mask & (1 << sampler)) {
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 08a1f8b..2e4695a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -909,6 +909,13 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
   unreachable("TXB is not valid for vertex shaders.");
case ir_lod:
  

Mesa (master): glsl: Add textureSamplesIdenticalEXT built-in functions

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 06c56f443aa1850b2651df3636c42a8740cff847
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=06c56f443aa1850b2651df3636c42a8740cff847

Author: Ian Romanick 
Date:   Tue Nov 17 16:59:40 2015 -0800

glsl: Add textureSamplesIdenticalEXT built-in functions

Signed-off-by: Ian Romanick 
Reviewed-by: Kenneth Graunke 
Reviewed-by: Chris Forbes 

---

 src/glsl/builtin_functions.cpp |   44 
 1 file changed, 44 insertions(+)

diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index 1824b83..881ee2b 100644
--- a/src/glsl/builtin_functions.cpp
+++ b/src/glsl/builtin_functions.cpp
@@ -290,6 +290,20 @@ texture_multisample_array(const _mesa_glsl_parse_state 
*state)
 }
 
 static bool
+texture_samples_identical(const _mesa_glsl_parse_state *state)
+{
+   return texture_multisample(state) &&
+  state->EXT_shader_samples_identical_enable;
+}
+
+static bool
+texture_samples_identical_array(const _mesa_glsl_parse_state *state)
+{
+   return texture_multisample_array(state) &&
+  state->EXT_shader_samples_identical_enable;
+}
+
+static bool
 fs_texture_cube_map_array(const _mesa_glsl_parse_state *state)
 {
return state->stage == MESA_SHADER_FRAGMENT &&
@@ -724,6 +738,7 @@ private:
 
BA2(textureQueryLod);
B1(textureQueryLevels);
+   BA2(textureSamplesIdentical);
B1(dFdx);
B1(dFdy);
B1(fwidth);
@@ -2210,6 +2225,16 @@ builtin_builder::create_builtins()
 
 NULL);
 
+   add_function("textureSamplesIdenticalEXT",
+_textureSamplesIdentical(texture_samples_identical, 
glsl_type::sampler2DMS_type,  glsl_type::ivec2_type),
+_textureSamplesIdentical(texture_samples_identical, 
glsl_type::isampler2DMS_type, glsl_type::ivec2_type),
+_textureSamplesIdentical(texture_samples_identical, 
glsl_type::usampler2DMS_type, glsl_type::ivec2_type),
+
+_textureSamplesIdentical(texture_samples_identical_array, 
glsl_type::sampler2DMSArray_type,  glsl_type::ivec3_type),
+_textureSamplesIdentical(texture_samples_identical_array, 
glsl_type::isampler2DMSArray_type, glsl_type::ivec3_type),
+_textureSamplesIdentical(texture_samples_identical_array, 
glsl_type::usampler2DMSArray_type, glsl_type::ivec3_type),
+NULL);
+
add_function("texture1D",
 _texture(ir_tex, v110, glsl_type::vec4_type,  
glsl_type::sampler1D_type, glsl_type::float_type),
 _texture(ir_txb, v110_fs_only, glsl_type::vec4_type,  
glsl_type::sampler1D_type, glsl_type::float_type),
@@ -4684,6 +4709,25 @@ builtin_builder::_textureQueryLevels(const glsl_type 
*sampler_type)
return sig;
 }
 
+ir_function_signature *
+builtin_builder::_textureSamplesIdentical(builtin_available_predicate avail,
+  const glsl_type *sampler_type,
+  const glsl_type *coord_type)
+{
+   ir_variable *s = in_var(sampler_type, "sampler");
+   ir_variable *P = in_var(coord_type, "P");
+   const glsl_type *return_type = glsl_type::bool_type;
+   MAKE_SIG(return_type, avail, 2, s, P);
+
+   ir_texture *tex = new(mem_ctx) ir_texture(ir_samples_identical);
+   tex->coordinate = var_ref(P);
+   tex->set_sampler(var_ref(s), return_type);
+
+   body.emit(ret(tex));
+
+   return sig;
+}
+
 UNOP(dFdx, ir_unop_dFdx, fs_oes_derivatives)
 UNOP(dFdxCoarse, ir_unop_dFdx_coarse, fs_derivative_control)
 UNOP(dFdxFine, ir_unop_dFdx_fine, fs_derivative_control)

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Mesa (master): i965/vec4: Handle nir_tex_src_ms_index more like the scalar

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 84b6c64efc52948da8db89b8d92d5e744e6cfc95
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=84b6c64efc52948da8db89b8d92d5e744e6cfc95

Author: Ian Romanick 
Date:   Tue Nov 17 19:31:39 2015 -0800

i965/vec4: Handle nir_tex_src_ms_index more like the scalar

v2: Rebase on top of f9a9ba5e.

Signed-off-by: Ian Romanick 
Reviewed-by: Jason Ekstrand 
Reviewed-by: Chris Forbes 

---

 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp |   18 ++
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 8088767..63696a7 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -1654,14 +1654,6 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
 
   case nir_tex_src_ms_index: {
  sample_index = get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_D, 1);
- assert(coord_type != NULL);
- if (devinfo->gen >= 7 &&
- key_tex->compressed_multisample_layout_mask & (1 << sampler)) {
-mcs = emit_mcs_fetch(coord_type, coordinate, sampler_reg);
- } else {
-mcs = brw_imm_ud(0u);
- }
- mcs = retype(mcs, BRW_REGISTER_TYPE_UD);
  break;
   }
 
@@ -1703,6 +1695,16 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
   }
}
 
+   if (instr->op == nir_texop_txf_ms) {
+  assert(coord_type != NULL);
+  if (devinfo->gen >= 7 &&
+  key_tex->compressed_multisample_layout_mask & (1 << sampler)) {
+ mcs = emit_mcs_fetch(coord_type, coordinate, sampler_reg);
+  } else {
+ mcs = brw_imm_ud(0u);
+  }
+   }
+
uint32_t constant_offset = 0;
for (unsigned i = 0; i < 3; i++) {
   if (instr->const_offset[i] != 0) {

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Mesa (master): nir: Add nir_texop_samples_identical opcode

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 457bb290efc162ea3c7c51a820ab7cf88a4efb8d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=457bb290efc162ea3c7c51a820ab7cf88a4efb8d

Author: Ian Romanick 
Date:   Tue Nov 17 17:09:09 2015 -0800

nir: Add nir_texop_samples_identical opcode

This is the NIR analog to GLSL IR ir_samples_identical.

v2: Don't add the second nir_tex_src_ms_index parameter.  Suggested by
Ken and Jason.

Signed-off-by: Ian Romanick 
Reviewed-by: Jason Ekstrand 
Reviewed-by: Chris Forbes 

---

 src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c |3 +++
 src/glsl/nir/glsl_to_nir.cpp |6 ++
 src/glsl/nir/nir.h   |4 
 src/glsl/nir/nir_print.c |4 +++-
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp |1 +
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp   |1 +
 6 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c 
b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index 157dc73..0f5c7e9 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
@@ -1624,6 +1624,7 @@ emit_tex(struct ir3_compile *ctx, nir_tex_instr *tex)
case nir_texop_tg4:
case nir_texop_query_levels:
case nir_texop_texture_samples:
+   case nir_texop_samples_identical:
compile_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
return;
}
@@ -1889,6 +1890,8 @@ emit_instr(struct ir3_compile *ctx, nir_instr *instr)
case nir_texop_query_levels:
emit_tex_query_levels(ctx, tex);
break;
+   case nir_texop_samples_identical:
+   unreachable("nir_texop_samples_identical");
default:
emit_tex(ctx, tex);
break;
diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp
index e149d73..18ef490 100644
--- a/src/glsl/nir/glsl_to_nir.cpp
+++ b/src/glsl/nir/glsl_to_nir.cpp
@@ -1798,6 +1798,11 @@ nir_visitor::visit(ir_texture *ir)
   num_srcs = 0;
   break;
 
+   case ir_samples_identical:
+  op = nir_texop_samples_identical;
+  num_srcs = 1; /* coordinate */
+  break;
+
default:
   unreachable("not reached");
}
@@ -1825,6 +1830,7 @@ nir_visitor::visit(ir_texture *ir)
case GLSL_TYPE_INT:
   instr->dest_type = nir_type_int;
   break;
+   case GLSL_TYPE_BOOL:
case GLSL_TYPE_UINT:
   instr->dest_type = nir_type_unsigned;
   break;
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 09eb712..087b453 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -956,6 +956,9 @@ typedef enum {
nir_texop_tg4,/**< Texture gather */
nir_texop_query_levels,   /**< Texture levels query */
nir_texop_texture_samples,/**< Texture samples query */
+   nir_texop_samples_identical,  /**< Query whether all samples are definitely
+  * identical.
+  */
 } nir_texop;
 
 typedef struct {
@@ -1029,6 +1032,7 @@ nir_tex_instr_dest_size(nir_tex_instr *instr)
 
case nir_texop_texture_samples:
case nir_texop_query_levels:
+   case nir_texop_samples_identical:
   return 1;
 
default:
diff --git a/src/glsl/nir/nir_print.c b/src/glsl/nir/nir_print.c
index 54b8cc6..c98a047 100644
--- a/src/glsl/nir/nir_print.c
+++ b/src/glsl/nir/nir_print.c
@@ -512,7 +512,9 @@ print_tex_instr(nir_tex_instr *instr, print_state *state)
case nir_texop_texture_samples:
   fprintf(fp, "texture_samples ");
   break;
-
+   case nir_texop_samples_identical:
+  fprintf(fp, "samples_identical ");
+  break;
default:
   unreachable("Invalid texture operation");
   break;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 3394e4a..8fc7ee4 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -2733,6 +2733,7 @@ fs_visitor::nir_emit_texture(const fs_builder , 
nir_tex_instr *instr)
   inst->base_mrf = -1;
   return;
}
+   case nir_texop_samples_identical: op = ir_samples_identical; break;
default:
   unreachable("unknown texture opcode");
}
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 3d186b4..8088767 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -1545,6 +1545,7 @@ ir_texture_opcode_for_nir_texop(nir_texop texop)
case nir_texop_txf_ms: op = ir_txf_ms; break;
case nir_texop_txl: op = ir_txl; break;
case nir_texop_txs: op = ir_txs; break;
+   case 

Mesa (master): mesa: Extension tracking for EXT_shader_samples_indentical

[Ian Romanick]

Module: Mesa
Branch: master
Commit: ff59700d29bb5db0010c3f7508336bf66a03d11f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff59700d29bb5db0010c3f7508336bf66a03d11f

Author: Ian Romanick 
Date:   Tue Nov 17 15:32:10 2015 -0800

mesa: Extension tracking for EXT_shader_samples_indentical

Signed-off-by: Ian Romanick 
Reviewed-by: Kenneth Graunke 
Reviewed-by: Chris Forbes 

---

 src/mesa/main/extensions_table.h |1 +
 src/mesa/main/mtypes.h   |1 +
 2 files changed, 2 insertions(+)

diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index 2075168..7facc7f 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -212,6 +212,7 @@ EXT(EXT_secondary_color , dummy_true
 EXT(EXT_separate_shader_objects , dummy_true   
  ,  x ,  x ,  x , ES2, 2013)
 EXT(EXT_separate_specular_color , dummy_true   
  , GLL,  x ,  x ,  x , 1997)
 EXT(EXT_shader_integer_mix  , EXT_shader_integer_mix   
  , GLL, GLC,  x ,  30, 2013)
+EXT(EXT_shader_samples_identical, EXT_shader_samples_identical 
  , GLL, GLC,  x ,  31, 2015)
 EXT(EXT_shadow_funcs, ARB_shadow   
  , GLL,  x ,  x ,  x , 2002)
 EXT(EXT_stencil_two_side, EXT_stencil_two_side 
  , GLL,  x ,  x ,  x , 2001)
 EXT(EXT_stencil_wrap, dummy_true   
  , GLL,  x ,  x ,  x , 2002)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 4efdf1e..65276f9 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -3761,6 +3761,7 @@ struct gl_extensions
GLboolean EXT_polygon_offset_clamp;
GLboolean EXT_provoking_vertex;
GLboolean EXT_shader_integer_mix;
+   GLboolean EXT_shader_samples_identical;
GLboolean EXT_stencil_two_side;
GLboolean EXT_texture_array;
GLboolean EXT_texture_compression_latc;

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Mesa (master): glsl: Extension tracking for EXT_shader_samples_indentical

[Ian Romanick]

Module: Mesa
Branch: master
Commit: ef54434c52385bea59d47dbfcedc6845f33fb231
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef54434c52385bea59d47dbfcedc6845f33fb231

Author: Ian Romanick 
Date:   Tue Nov 17 15:36:15 2015 -0800

glsl: Extension tracking for EXT_shader_samples_indentical

Signed-off-by: Ian Romanick 
Reviewed-by: Kenneth Graunke 
Reviewed-by: Chris Forbes 

---

 src/glsl/glcpp/glcpp-parse.y|3 +++
 src/glsl/glsl_parser_extras.cpp |1 +
 src/glsl/glsl_parser_extras.h   |2 ++
 3 files changed, 6 insertions(+)

diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
index ab5ec84..2fd4cf0 100644
--- a/src/glsl/glcpp/glcpp-parse.y
+++ b/src/glsl/glcpp/glcpp-parse.y
@@ -2512,6 +2512,9 @@ _glcpp_parser_handle_version_declaration(glcpp_parser_t 
*parser, intmax_t versio
if (extensions != NULL) {
   if (extensions->EXT_shader_integer_mix)
  add_builtin_define(parser, "GL_EXT_shader_integer_mix", 1);
+
+  if (extensions->EXT_shader_samples_identical)
+ add_builtin_define(parser, "GL_EXT_shader_samples_identical", 1);
}
 
if (version >= 150)
diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp
index 8fb05fa..c54dcfd 100644
--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -650,6 +650,7 @@ static const _mesa_glsl_extension 
_mesa_glsl_supported_extensions[] = {
EXT(EXT_draw_buffers,   false,  true, dummy_true),
EXT(EXT_separate_shader_objects,false, true,  dummy_true),
EXT(EXT_shader_integer_mix, true,  true,  
EXT_shader_integer_mix),
+   EXT(EXT_shader_samples_identical,   true,  true,  
EXT_shader_samples_identical),
EXT(EXT_texture_array,  true,  false, EXT_texture_array),
 };
 
diff --git a/src/glsl/glsl_parser_extras.h b/src/glsl/glsl_parser_extras.h
index 17f8490..17ff0b5 100644
--- a/src/glsl/glsl_parser_extras.h
+++ b/src/glsl/glsl_parser_extras.h
@@ -606,6 +606,8 @@ struct _mesa_glsl_parse_state {
bool EXT_separate_shader_objects_warn;
bool EXT_shader_integer_mix_enable;
bool EXT_shader_integer_mix_warn;
+   bool EXT_shader_samples_identical_enable;
+   bool EXT_shader_samples_identical_warn;
bool EXT_texture_array_enable;
bool EXT_texture_array_warn;
/*@}*/

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Mesa (master): os: check for GALLIUM_PROCESS_NAME to override os_get_process_name()

[Brian Paul]

Module: Mesa
Branch: master
Commit: 15f8dc7b234fa79c9dca69b0b49afead463293e3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=15f8dc7b234fa79c9dca69b0b49afead463293e3

Author: Brian Paul 
Date:   Wed Nov 18 09:25:48 2015 -0700

os: check for GALLIUM_PROCESS_NAME to override os_get_process_name()

Useful for debugging and for glretrace.

Reviewed-by: Charmaine Lee 
Reviewed-by: José Fonseca 

---

 src/gallium/auxiliary/os/os_process.c |   47 -
 1 file changed, 29 insertions(+), 18 deletions(-)

diff --git a/src/gallium/auxiliary/os/os_process.c 
b/src/gallium/auxiliary/os/os_process.c
index a626228..d2dcd0d 100644
--- a/src/gallium/auxiliary/os/os_process.c
+++ b/src/gallium/auxiliary/os/os_process.c
@@ -54,37 +54,48 @@ boolean
 os_get_process_name(char *procname, size_t size)
 {
const char *name;
+
+   /* First, check if the GALLIUM_PROCESS_NAME env var is set to
+* override the normal process name query.
+*/
+   name = os_get_option("GALLIUM_PROCESS_NAME");
+
+   if (!name) {
+  /* do normal query */
+
 #if defined(PIPE_SUBSYSTEM_WINDOWS_USER)
-   char szProcessPath[MAX_PATH];
-   char *lpProcessName;
-   char *lpProcessExt;
+  char szProcessPath[MAX_PATH];
+  char *lpProcessName;
+  char *lpProcessExt;
 
-   GetModuleFileNameA(NULL, szProcessPath, Elements(szProcessPath));
+  GetModuleFileNameA(NULL, szProcessPath, Elements(szProcessPath));
 
-   lpProcessName = strrchr(szProcessPath, '\\');
-   lpProcessName = lpProcessName ? lpProcessName + 1 : szProcessPath;
+  lpProcessName = strrchr(szProcessPath, '\\');
+  lpProcessName = lpProcessName ? lpProcessName + 1 : szProcessPath;
 
-   lpProcessExt = strrchr(lpProcessName, '.');
-   if (lpProcessExt) {
-  *lpProcessExt = '\0';
-   }
+  lpProcessExt = strrchr(lpProcessName, '.');
+  if (lpProcessExt) {
+ *lpProcessExt = '\0';
+  }
 
-   name = lpProcessName;
+  name = lpProcessName;
 
 #elif defined(__GLIBC__) || defined(__CYGWIN__)
-   name = program_invocation_short_name;
+  name = program_invocation_short_name;
 #elif defined(PIPE_OS_BSD) || defined(PIPE_OS_APPLE)
-   /* *BSD and OS X */
-   name = getprogname();
+  /* *BSD and OS X */
+  name = getprogname();
 #elif defined(PIPE_OS_HAIKU)
-   image_info info;
-   get_image_info(B_CURRENT_TEAM, );
-   name = info.name;
+  image_info info;
+  get_image_info(B_CURRENT_TEAM, );
+  name = info.name;
 #else
 #warning unexpected platform in os_process.c
-   return FALSE;
+  return FALSE;
 #endif
 
+   }
+
assert(size > 0);
assert(procname);
 

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Mesa (master): glsl: add EXT_blend_func_extended parser enables

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: ceecb0876f1479661e561520c7e3561fd051720a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ceecb0876f1479661e561520c7e3561fd051720a

Author: Ryan Houdek 
Date:   Thu Nov  5 10:53:40 2015 -0600

glsl: add EXT_blend_func_extended parser enables

This adds a state for the maximum dual source draw variables available
and the variable for determining if the extension has been enabled
in the program shaders.

Reviewed-by: Ian Romanick 
Reviewed-by: Ilia Mirkin 

---

 src/glsl/glsl_parser_extras.cpp |3 +++
 src/glsl/glsl_parser_extras.h   |5 +
 2 files changed, 8 insertions(+)

diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp
index 3ed1168..8fb05fa 100644
--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -102,6 +102,8 @@ _mesa_glsl_parse_state::_mesa_glsl_parse_state(struct 
gl_context *_ctx,
 
this->Const.MaxDrawBuffers = ctx->Const.MaxDrawBuffers;
 
+   this->Const.MaxDualSourceDrawBuffers = ctx->Const.MaxDualSourceDrawBuffers;
+
/* 1.50 constants */
this->Const.MaxVertexOutputComponents = 
ctx->Const.Program[MESA_SHADER_VERTEX].MaxOutputComponents;
this->Const.MaxGeometryInputComponents = 
ctx->Const.Program[MESA_SHADER_GEOMETRY].MaxInputComponents;
@@ -644,6 +646,7 @@ static const _mesa_glsl_extension 
_mesa_glsl_supported_extensions[] = {
EXT(AMD_shader_trinary_minmax,  true,  false, dummy_true),
EXT(AMD_vertex_shader_layer,true,  false, 
AMD_vertex_shader_layer),
EXT(AMD_vertex_shader_viewport_index, true,  false,   
AMD_vertex_shader_viewport_index),
+   EXT(EXT_blend_func_extended,false,  true, 
ARB_blend_func_extended),
EXT(EXT_draw_buffers,   false,  true, dummy_true),
EXT(EXT_separate_shader_objects,false, true,  dummy_true),
EXT(EXT_shader_integer_mix, true,  true,  
EXT_shader_integer_mix),
diff --git a/src/glsl/glsl_parser_extras.h b/src/glsl/glsl_parser_extras.h
index 1d8c1b8..17f8490 100644
--- a/src/glsl/glsl_parser_extras.h
+++ b/src/glsl/glsl_parser_extras.h
@@ -380,6 +380,9 @@ struct _mesa_glsl_parse_state {
   /* ARB_draw_buffers */
   unsigned MaxDrawBuffers;
 
+  /* ARB_blend_func_extended */
+  unsigned MaxDualSourceDrawBuffers;
+
   /* 3.00 ES */
   int MinProgramTexelOffset;
   int MaxProgramTexelOffset;
@@ -595,6 +598,8 @@ struct _mesa_glsl_parse_state {
bool AMD_vertex_shader_layer_warn;
bool AMD_vertex_shader_viewport_index_enable;
bool AMD_vertex_shader_viewport_index_warn;
+   bool EXT_blend_func_extended_enable;
+   bool EXT_blend_func_extended_warn;
bool EXT_draw_buffers_enable;
bool EXT_draw_buffers_warn;
bool EXT_separate_shader_objects_enable;

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Mesa (master): mesa: enable EXT_blend_func_extended if the driver supports the ARB version

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 0ec218d167a2e5cef993ba7863608c7b40f4d649
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ec218d167a2e5cef993ba7863608c7b40f4d649

Author: Ryan Houdek 
Date:   Thu Nov  5 11:07:08 2015 -0600

mesa: enable EXT_blend_func_extended if the driver supports the ARB version

Reviewed-by: Ian Romanick 
Reviewed-by: Ilia Mirkin 

---

 docs/relnotes/11.1.0.html|1 +
 src/mesa/main/extensions_table.h |1 +
 2 files changed, 2 insertions(+)

diff --git a/docs/relnotes/11.1.0.html b/docs/relnotes/11.1.0.html
index f4563ea..c0c9a6a 100644
--- a/docs/relnotes/11.1.0.html
+++ b/docs/relnotes/11.1.0.html
@@ -58,6 +58,7 @@ Note: some of the new features are only available with 
certain drivers.
 GL_ARB_texture_query_lod on softpipe
 GL_ARB_texture_view on radeonsi and r600 (for evergeen and newer)
 GL_ARB_vertex_type_2_10_10_10_rev on freedreno (a3xx)
+GL_EXT_blend_func_extended on all drivers that support the ARB version
 GL_EXT_buffer_storage implemented for when ES 3.1 support is gained
 GL_EXT_draw_elements_base_vertex on all drivers
 GL_EXT_texture_compression_rgtc / latc on freedreno (a3xx & a4xx)
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index 8685a89..7b5cc7b 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -141,6 +141,7 @@ EXT(EXT_abgr, dummy_true
 EXT(EXT_bgra, dummy_true   
  , GLL,  x ,  x ,  x , 1995)
 EXT(EXT_blend_color , EXT_blend_color  
  , GLL,  x ,  x ,  x , 1995)
 EXT(EXT_blend_equation_separate , EXT_blend_equation_separate  
  , GLL, GLC,  x ,  x , 2003)
+EXT(EXT_blend_func_extended , ARB_blend_func_extended  
  ,  x ,  x ,  x , ES2, 2015)
 EXT(EXT_blend_func_separate , EXT_blend_func_separate  
  , GLL,  x ,  x ,  x , 1999)
 EXT(EXT_buffer_storage  , ARB_buffer_storage   
  ,  x ,  x ,  x ,  31, 2015)
 EXT(EXT_discard_framebuffer , dummy_true   
  ,  x ,  x , ES1, ES2, 2009)

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Mesa (master): glsl: add support for EXT_blend_func_extended builtins

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 1d1d02f2ac69475da112a6aadfa7c161b13ff4da
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d1d02f2ac69475da112a6aadfa7c161b13ff4da

Author: Ryan Houdek 
Date:   Thu Nov  5 10:59:32 2015 -0600

glsl: add support for EXT_blend_func_extended builtins

gl_MaxDualSourceDrawBuffersEXT - Maximum dual-source draw buffers supported

For ESSL 1.0, it provides two builtins since you can't have user-defined
color output variables:
  gl_SecondaryFragColorEXT
  gl_SecondaryFragDataEXT[MaxDSDrawBuffers]

Reviewed-by: Ilia Mirkin 

---

 src/glsl/ast_to_hir.cpp|   24 ++
 src/glsl/builtin_variables.cpp |   68 
 2 files changed, 92 insertions(+)

diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 41d05c0..a9b1c0e 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -7194,6 +7194,8 @@ detect_conflicting_assignments(struct 
_mesa_glsl_parse_state *state,
 {
bool gl_FragColor_assigned = false;
bool gl_FragData_assigned = false;
+   bool gl_FragSecondaryColor_assigned = false;
+   bool gl_FragSecondaryData_assigned = false;
bool user_defined_fs_output_assigned = false;
ir_variable *user_defined_fs_output = NULL;
 
@@ -7211,6 +7213,10 @@ detect_conflicting_assignments(struct 
_mesa_glsl_parse_state *state,
  gl_FragColor_assigned = true;
   else if (strcmp(var->name, "gl_FragData") == 0)
  gl_FragData_assigned = true;
+   else if (strcmp(var->name, "gl_SecondaryFragColorEXT") == 0)
+ gl_FragSecondaryColor_assigned = true;
+   else if (strcmp(var->name, "gl_SecondaryFragDataEXT") == 0)
+ gl_FragSecondaryData_assigned = true;
   else if (!is_gl_identifier(var->name)) {
  if (state->stage == MESA_SHADER_FRAGMENT &&
  var->data.mode == ir_var_shader_out) {
@@ -7242,11 +7248,29 @@ detect_conflicting_assignments(struct 
_mesa_glsl_parse_state *state,
   _mesa_glsl_error(, state, "fragment shader writes to both "
"`gl_FragColor' and `%s'",
user_defined_fs_output->name);
+   } else if (gl_FragSecondaryColor_assigned && gl_FragSecondaryData_assigned) 
{
+  _mesa_glsl_error(, state, "fragment shader writes to both "
+   "`gl_FragSecondaryColorEXT' and"
+   " `gl_FragSecondaryDataEXT'");
+   } else if (gl_FragColor_assigned && gl_FragSecondaryData_assigned) {
+  _mesa_glsl_error(, state, "fragment shader writes to both "
+   "`gl_FragColor' and"
+   " `gl_FragSecondaryDataEXT'");
+   } else if (gl_FragData_assigned && gl_FragSecondaryColor_assigned) {
+  _mesa_glsl_error(, state, "fragment shader writes to both "
+   "`gl_FragData' and"
+   " `gl_FragSecondaryColorEXT'");
} else if (gl_FragData_assigned && user_defined_fs_output_assigned) {
   _mesa_glsl_error(, state, "fragment shader writes to both "
"`gl_FragData' and `%s'",
user_defined_fs_output->name);
}
+
+   if ((gl_FragSecondaryColor_assigned || gl_FragSecondaryData_assigned) &&
+   !state->EXT_blend_func_extended_enable) {
+  _mesa_glsl_error(, state,
+   "Dual source blending requires 
EXT_blend_func_extended");
+   }
 }
 
 
diff --git a/src/glsl/builtin_variables.cpp b/src/glsl/builtin_variables.cpp
index fc7a3c3..e8eab80 100644
--- a/src/glsl/builtin_variables.cpp
+++ b/src/glsl/builtin_variables.cpp
@@ -377,6 +377,11 @@ private:
   return add_variable(name, type, ir_var_shader_out, slot);
}
 
+   ir_variable *add_index_output(int slot, int index, const glsl_type *type, 
const char *name)
+   {
+  return add_index_variable(name, type, ir_var_shader_out, slot, index);
+   }
+
ir_variable *add_system_value(int slot, const glsl_type *type,
  const char *name)
{
@@ -385,6 +390,8 @@ private:
 
ir_variable *add_variable(const char *name, const glsl_type *type,
  enum ir_variable_mode mode, int slot);
+   ir_variable *add_index_variable(const char *name, const glsl_type *type,
+ enum ir_variable_mode mode, int slot, int index);
ir_variable *add_uniform(const glsl_type *type, const char *name);
ir_variable *add_const(const char *name, int value);
ir_variable *add_const_ivec3(const char *name, int x, int y, int z);
@@ -430,6 +437,46 @@ builtin_variable_generator::builtin_variable_generator(
 {
 }
 
+ir_variable *
+builtin_variable_generator::add_index_variable(const char *name,
+ const glsl_type *type,
+ enum ir_variable_mode mode, int slot, 
int index)
+{
+   ir_variable *var = new(symtab) ir_variable(type, name, mode);
+   var->data.how_declared = 

Mesa (master): glsl: add a parse check to check for the index layout qualifier

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 33ddc8e865e67f3dabcd1b598f4e978be6c7be6f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=33ddc8e865e67f3dabcd1b598f4e978be6c7be6f

Author: Ryan Houdek 
Date:   Thu Nov  5 11:03:44 2015 -0600

glsl: add a parse check to check for the index layout qualifier

This can only be used if EXT_blend_func_extended is enabled

Reviewed-by: Ian Romanick 
Reviewed-by: Ilia Mirkin 

---

 src/glsl/glsl_parser.yy |5 +
 1 file changed, 5 insertions(+)

diff --git a/src/glsl/glsl_parser.yy b/src/glsl/glsl_parser.yy
index adf6a05..403cbd1 100644
--- a/src/glsl/glsl_parser.yy
+++ b/src/glsl/glsl_parser.yy
@@ -1476,6 +1476,11 @@ layout_qualifier_id:
   }
 
   if (match_layout_qualifier("index", $1, state) == 0) {
+ if (state->es_shader && !state->EXT_blend_func_extended_enable) {
+_mesa_glsl_error(& @3, state, "index layout qualifier requires 
EXT_blend_func_extended");
+YYERROR;
+ }
+
  $$.flags.q.explicit_index = 1;
 
  if ($3 >= 0) {

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Mesa (master): mesa: enable usage of blend_func_extended blend factors in GLES2

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 4b549f0d8ce425e96f57f4014edcfe7bac36920c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4b549f0d8ce425e96f57f4014edcfe7bac36920c

Author: Ryan Houdek 
Date:   Thu Nov  5 11:05:17 2015 -0600

mesa: enable usage of blend_func_extended blend factors in GLES2

Reviewed-by: Ilia Mirkin 

---

 src/mesa/main/blend.c |6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mesa/main/blend.c b/src/mesa/main/blend.c
index ddf7f49..f07552b 100644
--- a/src/mesa/main/blend.c
+++ b/src/mesa/main/blend.c
@@ -67,7 +67,7 @@ legal_src_factor(const struct gl_context *ctx, GLenum factor)
case GL_SRC1_ALPHA:
case GL_ONE_MINUS_SRC1_COLOR:
case GL_ONE_MINUS_SRC1_ALPHA:
-  return _mesa_is_desktop_gl(ctx)
+  return ctx->API != API_OPENGLES
  && ctx->Extensions.ARB_blend_func_extended;
default:
   return GL_FALSE;
@@ -100,14 +100,14 @@ legal_dst_factor(const struct gl_context *ctx, GLenum 
factor)
case GL_ONE_MINUS_CONSTANT_ALPHA:
   return _mesa_is_desktop_gl(ctx) || ctx->API == API_OPENGLES2;
case GL_SRC_ALPHA_SATURATE:
-  return (_mesa_is_desktop_gl(ctx)
+  return (ctx->API != API_OPENGLES
   && ctx->Extensions.ARB_blend_func_extended)
  || _mesa_is_gles3(ctx);
case GL_SRC1_COLOR:
case GL_SRC1_ALPHA:
case GL_ONE_MINUS_SRC1_COLOR:
case GL_ONE_MINUS_SRC1_ALPHA:
-  return _mesa_is_desktop_gl(ctx)
+  return ctx->API != API_OPENGLES
  && ctx->Extensions.ARB_blend_func_extended;
default:
   return GL_FALSE;

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Mesa (master): glsl: add GL_EXT_blend_func_extended preprocessor define

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: ef9e6d1ec8389f800d22c0dd091efb30f189fa45
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef9e6d1ec8389f800d22c0dd091efb30f189fa45

Author: Ryan Houdek 
Date:   Thu Nov  5 20:44:03 2015 -0600

glsl: add GL_EXT_blend_func_extended preprocessor define

Reviewed-by: Ian Romanick 
Reviewed-by: Ilia Mirkin 

---

 src/glsl/glcpp/glcpp-parse.y |2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
index 6aa7abe..ab5ec84 100644
--- a/src/glsl/glcpp/glcpp-parse.y
+++ b/src/glsl/glcpp/glcpp-parse.y
@@ -2384,6 +2384,8 @@ _glcpp_parser_handle_version_declaration(glcpp_parser_t 
*parser, intmax_t versio
  add_builtin_define(parser, "GL_OES_standard_derivatives", 1);
   if (extensions->ARB_texture_multisample)
  add_builtin_define(parser, 
"GL_OES_texture_storage_multisample_2d_array", 1);
+  if (extensions->ARB_blend_func_extended)
+ add_builtin_define(parser, "GL_EXT_blend_func_extended", 1);
   }
} else {
   add_builtin_define(parser, "GL_ARB_draw_buffers", 1);

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Mesa (master): docs: GL3.1 for a3xx and a4xx

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: bcda79676a7a51e433f0f044f43b61405ebcc9e5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bcda79676a7a51e433f0f044f43b61405ebcc9e5

Author: Ilia Mirkin 
Date:   Thu Nov 19 12:25:53 2015 -0500

docs: GL3.1 for a3xx and a4xx

Signed-off-by: Ilia Mirkin 

---

 docs/relnotes/11.1.0.html |1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/relnotes/11.1.0.html b/docs/relnotes/11.1.0.html
index c0c9a6a..2e20bb3 100644
--- a/docs/relnotes/11.1.0.html
+++ b/docs/relnotes/11.1.0.html
@@ -44,6 +44,7 @@ Note: some of the new features are only available with 
certain drivers.
 
 
 
+OpenGL 3.1 support on freedreno (a3xx, a4xx)
 GL_ARB_arrays_of_arrays on i965
 GL_ARB_blend_func_extended on freedreno (a3xx)
 GL_ARB_clear_texture on nv50, nvc0

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