Mesa (master): nv50/ir: fix (un)spilling of 3-wide results

2015-11-22 Thread Ilia Mirkin 
Module: Mesa
Branch: master
Commit: 4deb118d06e96731f3481daa72c201d7258bfbbb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4deb118d06e96731f3481daa72c201d7258bfbbb

Author: Ilia Mirkin 
Date:   Sat Apr 18 15:00:45 2015 -0400

nv50/ir: fix (un)spilling of 3-wide results

There is no 96-bit load/store operations, so we have to split it up
into a 32-bit parts, with a split/merge around it.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90348
Signed-off-by: Ilia Mirkin 
Cc: "11.0 11.1" 

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp |   46 ++--
 1 file changed, 42 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index 7859c8e..41d2cc9 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
@@ -1573,10 +1573,28 @@ SpillCodeInserter::spill(Instruction *defi, Value 
*slot, LValue *lval)
 
Instruction *st;
if (slot->reg.file == FILE_MEMORY_LOCAL) {
-  st = new_Instruction(func, OP_STORE, ty);
-  st->setSrc(0, slot);
-  st->setSrc(1, lval);
   lval->noSpill = 1;
+  if (ty != TYPE_B96) {
+ st = new_Instruction(func, OP_STORE, ty);
+ st->setSrc(0, slot);
+ st->setSrc(1, lval);
+  } else {
+ st = new_Instruction(func, OP_SPLIT, ty);
+ st->setSrc(0, lval);
+ for (int d = 0; d < lval->reg.size / 4; ++d)
+st->setDef(d, new_LValue(func, FILE_GPR));
+
+ for (int d = lval->reg.size / 4 - 1; d >= 0; --d) {
+Value *tmp = cloneShallow(func, slot);
+tmp->reg.size = 4;
+tmp->reg.data.offset += 4 * d;
+
+Instruction *s = new_Instruction(func, OP_STORE, TYPE_U32);
+s->setSrc(0, tmp);
+s->setSrc(1, st->getDef(d));
+defi->bb->insertAfter(defi, s);
+ }
+  }
} else {
   st = new_Instruction(func, OP_CVT, ty);
   st->setDef(0, slot);
@@ -1596,7 +1614,27 @@ SpillCodeInserter::unspill(Instruction *usei, LValue 
*lval, Value *slot)
Instruction *ld;
if (slot->reg.file == FILE_MEMORY_LOCAL) {
   lval->noSpill = 1;
-  ld = new_Instruction(func, OP_LOAD, ty);
+  if (ty != TYPE_B96) {
+ ld = new_Instruction(func, OP_LOAD, ty);
+  } else {
+ ld = new_Instruction(func, OP_MERGE, ty);
+ for (int d = 0; d < lval->reg.size / 4; ++d) {
+Value *tmp = cloneShallow(func, slot);
+LValue *val;
+tmp->reg.size = 4;
+tmp->reg.data.offset += 4 * d;
+
+Instruction *l = new_Instruction(func, OP_LOAD, TYPE_U32);
+l->setDef(0, (val = new_LValue(func, FILE_GPR)));
+l->setSrc(0, tmp);
+usei->bb->insertBefore(usei, l);
+ld->setSrc(d, val);
+val->noSpill = 1;
+ }
+ ld->setDef(0, lval);
+ usei->bb->insertBefore(usei, ld);
+ return lval;
+  }
} else {
   ld = new_Instruction(func, OP_CVT, ty);
}

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Mesa (master): nir: s/nir_type_unsigned/nir_type_uint

2015-11-22 Thread Iago Toral Quiroga 
Module: Mesa
Branch: master
Commit: f58813842bcece3498f55ec5d582466ccff92a5e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f58813842bcece3498f55ec5d582466ccff92a5e

Author: Jason Ekstrand 
Date:   Fri May 15 09:14:47 2015 -0700

nir: s/nir_type_unsigned/nir_type_uint

v2: do the same in tgsi_to_nir (Samuel)

v3: added missing cases after rebase (Iago)

v4: Add a blank space after '#' in one of the comments (Matt)

Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Matt Turner 

---

 src/gallium/auxiliary/nir/tgsi_to_nir.c|2 +-
 .../drivers/freedreno/ir3/ir3_compiler_nir.c   |2 +-
 src/glsl/nir/glsl_to_nir.cpp   |2 +-
 src/glsl/nir/nir.h |2 +-
 src/glsl/nir/nir_constant_expressions.py   |2 +-
 src/glsl/nir/nir_opcodes.py|   78 ++--
 src/glsl/nir/nir_search.c  |4 +-
 src/mesa/drivers/dri/i965/brw_nir.c|4 +-
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp |2 +-
 9 files changed, 49 insertions(+), 49 deletions(-)

diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c 
b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index 1da00b2..ce1da10 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -295,7 +295,7 @@ ttn_emit_declaration(struct ttn_compile *c)
  type = nir_type_int;
  break;
   case TGSI_RETURN_TYPE_UINT:
- type = nir_type_unsigned;
+ type = nir_type_uint;
  break;
   case TGSI_RETURN_TYPE_FLOAT:
   default:
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c 
b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index 0f5c7e9..25e8412 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
@@ -1718,7 +1718,7 @@ emit_tex(struct ir3_compile *ctx, nir_tex_instr *tex)
case nir_type_int:
type = TYPE_S32;
break;
-   case nir_type_unsigned:
+   case nir_type_uint:
case nir_type_bool:
type = TYPE_U32;
break;
diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp
index 18ef490..45d045c 100644
--- a/src/glsl/nir/glsl_to_nir.cpp
+++ b/src/glsl/nir/glsl_to_nir.cpp
@@ -1832,7 +1832,7 @@ nir_visitor::visit(ir_texture *ir)
   break;
case GLSL_TYPE_BOOL:
case GLSL_TYPE_UINT:
-  instr->dest_type = nir_type_unsigned;
+  instr->dest_type = nir_type_uint;
   break;
default:
   unreachable("not reached");
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 087b453..b4be145 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -634,7 +634,7 @@ typedef enum {
nir_type_invalid = 0, /* Not a valid type */
nir_type_float,
nir_type_int,
-   nir_type_unsigned,
+   nir_type_uint,
nir_type_bool
 } nir_alu_type;
 
diff --git a/src/glsl/nir/nir_constant_expressions.py 
b/src/glsl/nir/nir_constant_expressions.py
index 2ba8554..b16ef50 100644
--- a/src/glsl/nir/nir_constant_expressions.py
+++ b/src/glsl/nir/nir_constant_expressions.py
@@ -213,7 +213,7 @@ unpack_half_1x16(uint16_t u)
 }
 
 /* Some typed vector structures to make things like src0.y work */
-% for type in ["float", "int", "unsigned", "bool"]:
+% for type in ["float", "int", "uint", "bool"]:
 struct ${type}_vec {
${type} x;
${type} y;
diff --git a/src/glsl/nir/nir_opcodes.py b/src/glsl/nir/nir_opcodes.py
index 729f695..37d3dfc 100644
--- a/src/glsl/nir/nir_opcodes.py
+++ b/src/glsl/nir/nir_opcodes.py
@@ -91,7 +91,7 @@ class Opcode(object):
 tfloat = "float"
 tint = "int"
 tbool = "bool"
-tunsigned = "unsigned"
+tuint = "uint"
 
 commutative = "commutative "
 associative = "associative "
@@ -156,7 +156,7 @@ unop("fsqrt", tfloat, "sqrtf(src0)")
 unop("fexp2", tfloat, "exp2f(src0)")
 unop("flog2", tfloat, "log2f(src0)")
 unop_convert("f2i", tfloat, tint, "src0") # Float-to-integer conversion.
-unop_convert("f2u", tfloat, tunsigned, "src0") # Float-to-unsigned conversion
+unop_convert("f2u", tfloat, tuint, "src0") # Float-to-unsigned conversion
 unop_convert("i2f", tint, tfloat, "src0") # Integer-to-float conversion.
 # Float-to-boolean conversion
 unop_convert("f2b", tfloat, tbool, "src0 != 0.0f")
@@ -165,7 +165,7 @@ unop_convert("b2f", tbool, tfloat, "src0 ? 1.0f : 0.0f")
 # Int-to-boolean conversion
 unop_convert("i2b", tint, tbool, "src0 != 0")
 unop_convert("b2i", tbool, tint, "src0 ? 1 : 0") # Boolean-to-int conversion
-unop_convert("u2f", tunsigned, tfloat, "src0") #Unsigned-to-float conversion.
+unop_convert("u2f", tuint, tfloat, "src0") # Unsigned-to-float conversion.
 
 unop_reduce("bany", 1, tbool, tbool, "{src}", "{src0} || {src1}", "{src}")
 unop_reduce("ball", 1, tbool, tbool, "{src}", "{src0} && {src1}", "{src}")
@@ -205,13 +205,13 @@ unop("fddy_coarse",

Mesa (master): i965/fs: respect force_sechalf/force_writemask_all in CSE

2015-11-22 Thread Iago Toral Quiroga 
Module: Mesa
Branch: master
Commit: 70171a9c89ebd885f30bd432452ee35099b6874a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=70171a9c89ebd885f30bd432452ee35099b6874a

Author: Connor Abbott 
Date:   Tue Aug 11 14:25:36 2015 -0700

i965/fs: respect force_sechalf/force_writemask_all in CSE

Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Matt Turner 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_fs_cse.cpp |2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
index 3c40fcd..3b65a38 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
@@ -210,6 +210,8 @@ create_copy_instr(const fs_builder , fs_inst *inst, 
fs_reg src, bool negate)
   copy = bld.LOAD_PAYLOAD(inst->dst, payload, sources, header_size);
} else {
   copy = bld.MOV(inst->dst, src);
+  copy->force_sechalf = inst->force_sechalf;
+  copy->force_writemask_all = inst->force_writemask_all;
   copy->src[0].negate = negate;
}
assert(copy->regs_written == written);

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Mesa (master): i965/fs: add stride restrictions for copy propagation

2015-11-22 Thread Iago Toral Quiroga 
Module: Mesa
Branch: master
Commit: d982922b184930a4ceed1d97b772cce5c371865d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d982922b184930a4ceed1d97b772cce5c371865d

Author: Connor Abbott 
Date:   Fri Aug 14 12:00:13 2015 -0700

i965/fs: add stride restrictions for copy propagation

There are various restrictions on what the hstride can be that depend on
the Gen, and now that we're using hstride == 2 for packing/unpacking
doubles, we're going to run into these restrictions a lot more often.
Pull them out into a separate function, and move the one restriction we
checked previously into it.

Reviewed-by: Matt Turner 

---

 .../drivers/dri/i965/brw_fs_copy_propagation.cpp   |   56 +++-
 1 file changed, 55 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
index 426ea57..62ae9ab 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
@@ -275,6 +275,59 @@ is_logic_op(enum opcode opcode)
opcode == BRW_OPCODE_NOT);
 }
 
+static bool
+can_take_stride(fs_inst *inst, unsigned arg, unsigned stride,
+const brw_device_info *devinfo)
+{
+   if (stride > 4)
+  return false;
+
+   /* 3-source instructions can only be Align16, which restricts what strides
+* they can take. They can only take a stride of 1 (the usual case), or 0
+* with a special "repctrl" bit. But the repctrl bit doesn't work for
+* 64-bit datatypes, so if the source type is 64-bit then only a stride of
+* 1 is allowed. From the Broadwell PRM, Volume 7 "3D Media GPGPU", page
+* 944:
+*
+*This is applicable to 32b datatypes and 16b datatype. 64b datatypes
+*cannot use the replicate control.
+*/
+   if (inst->is_3src()) {
+  if (type_sz(inst->src[arg].type) > 4)
+ return stride == 1;
+  else
+ return stride == 1 || stride == 0;
+   }
+
+   /* From the Broadwell PRM, Volume 2a "Command Reference - Instructions",
+* page 391 ("Extended Math Function"):
+*
+* The following restrictions apply for align1 mode: Scalar source is
+* supported. Source and destination horizontal stride must be the
+* same.
+*
+* From the Haswell PRM Volume 2b "Command Reference - Instructions", page
+* 134 ("Extended Math Function"):
+*
+*Scalar source is supported. Source and destination horizontal stride
+*must be 1.
+*
+* and similar language exists for IVB and SNB. Pre-SNB, math instructions
+* are sends, so the sources are moved to MRF's and there are no
+* restrictions.
+*/
+   if (inst->is_math()) {
+  if (devinfo->gen == 6 || devinfo->gen == 7) {
+ assert(inst->dst.stride == 1);
+ return stride == 1 || stride == 0;
+  } else if (devinfo->gen >= 8) {
+ return stride == inst->dst.stride || stride == 0;
+  }
+   }
+
+   return true;
+}
+
 bool
 fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
 {
@@ -326,7 +379,8 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, 
acp_entry *entry)
/* Bail if the result of composing both strides would exceed the
 * hardware limit.
 */
-   if (entry->src.stride * inst->src[arg].stride > 4)
+   if (!can_take_stride(inst, arg, entry->src.stride * inst->src[arg].stride,
+devinfo))
   return false;
 
/* Bail if the instruction type is larger than the execution type of the

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Mesa (master): i965/fs: print non-1 strides when dumping instructions

2015-11-22 Thread Iago Toral Quiroga 
Module: Mesa
Branch: master
Commit: 718b9f52dd9ba780decf5bb59f5100cf590393a0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=718b9f52dd9ba780decf5bb59f5100cf590393a0

Author: Connor Abbott 
Date:   Wed Aug  5 09:41:18 2015 -0700

i965/fs: print non-1 strides when dumping instructions

v2:
  - Simplify code (Iago)

Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Matt Turner 

---

 src/mesa/drivers/dri/i965/brw_fs.cpp |   12 
 1 file changed, 12 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index e9c990d..7376f95 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -4621,6 +4621,8 @@ fs_visitor::dump_instruction(backend_instruction 
*be_inst, FILE *file)
case IMM:
   unreachable("not reached");
}
+   if (inst->dst.stride != 1)
+  fprintf(file, "<%u>", inst->dst.stride);
fprintf(file, ":%s, ", brw_reg_type_letters(inst->dst.type));
 
for (int i = 0; i < inst->sources; i++) {
@@ -4708,6 +4710,16 @@ fs_visitor::dump_instruction(backend_instruction 
*be_inst, FILE *file)
  fprintf(file, "|");
 
   if (inst->src[i].file != IMM) {
+ unsigned stride;
+ if (inst->src[i].file == ARF || inst->src[i].file == FIXED_GRF) {
+unsigned hstride = inst->src[i].hstride;
+stride = (hstride == 0 ? 0 : (1 << (hstride - 1)));
+ } else {
+stride = inst->src[i].stride;
+ }
+ if (stride != 1)
+fprintf(file, "<%u>", stride);
+
  fprintf(file, ":%s", brw_reg_type_letters(inst->src[i].type));
   }
 

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Mesa (master): nir/builder: only read meaningful channels in nir_swizzle()

2015-11-22 Thread Iago Toral Quiroga 
Module: Mesa
Branch: master
Commit: fb93dd7aa8f2cac520bbbd3fc2af807bd2573480
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb93dd7aa8f2cac520bbbd3fc2af807bd2573480

Author: Connor Abbott 
Date:   Mon Aug  3 15:04:13 2015 -0700

nir/builder: only read meaningful channels in nir_swizzle()

This way the caller doesn't have to initialize all 4 channels when they
aren't using them.

v2: Fix signed/unsigned comparison warning (Iago)

Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Matt Turner 

---

 src/glsl/nir/nir_builder.h |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/glsl/nir/nir_builder.h b/src/glsl/nir/nir_builder.h
index d09f929..b909f483 100644
--- a/src/glsl/nir/nir_builder.h
+++ b/src/glsl/nir/nir_builder.h
@@ -242,7 +242,7 @@ nir_swizzle(nir_builder *build, nir_ssa_def *src, unsigned 
swiz[4],
 {
nir_alu_src alu_src = { NIR_SRC_INIT };
alu_src.src = nir_src_for_ssa(src);
-   for (int i = 0; i < 4; i++)
+   for (unsigned i = 0; i < num_components; i++)
   alu_src.swizzle[i] = swiz[i];
 
return use_fmov ? nir_fmov_alu(build, alu_src, num_components) :

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Mesa (master): i965/fs: don't propagate cmod when the exec sizes differ

2015-11-22 Thread Iago Toral Quiroga 
Module: Mesa
Branch: master
Commit: 95ac3b1daeaa7d40d49fa2e0bdef46346c2996d5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=95ac3b1daeaa7d40d49fa2e0bdef46346c2996d5

Author: Connor Abbott 
Date:   Tue Aug 11 16:16:42 2015 -0700

i965/fs: don't propagate cmod when the exec sizes differ

This can happen when the source of the compare was split by the SIMD
lowering pass. Potentially, we could allow the case where the exec size
of scan_inst is larger, and scan_inst has the right quarter selected,
but doing that seems a little more risky.

v2: Merge the bail condition into the the previous if/break block (Matt)

Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Matt Turner 

---

 src/mesa/drivers/dri/i965/brw_fs_cmod_propagation.cpp |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_cmod_propagation.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_cmod_propagation.cpp
index 8fdc959..7c01f1e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_cmod_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_cmod_propagation.cpp
@@ -90,7 +90,8 @@ opt_cmod_propagation_local(bblock_t *block)
   foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
  if (scan_inst->overwrites_reg(inst->src[0])) {
 if (scan_inst->is_partial_write() ||
-scan_inst->dst.reg_offset != inst->src[0].reg_offset)
+scan_inst->dst.reg_offset != inst->src[0].reg_offset ||
+scan_inst->exec_size != inst->exec_size)
break;
 
 /* CMP's result is the same regardless of dest type. */

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Mesa (master): i965: fix 64-bit immediates in brw_inst(_set)_bits

2015-11-22 Thread Iago Toral Quiroga 
Module: Mesa
Branch: master
Commit: b1a83b5d1b677faf650a41cd2c152b4d1cd18f84
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1a83b5d1b677faf650a41cd2c152b4d1cd18f84

Author: Connor Abbott 
Date:   Mon Aug  3 14:38:12 2015 -0700

i965: fix 64-bit immediates in brw_inst(_set)_bits

If we tried to get/set something that was exactly 64 bits, we would
try to do (1 << 64) - 1 to calculate the mask which doesn't give us all
1's like we want.

v2 (Iago)
 - Replace ~0 by ~0ull
 - Removed unnecessary parenthesis

v3 (Kristian)
 - Avoid the conditional

Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Matt Turner 
Reviewed-by: Kristian Høgsberg 

---

 src/mesa/drivers/dri/i965/brw_inst.h |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_inst.h 
b/src/mesa/drivers/dri/i965/brw_inst.h
index 4ed95c4..b2afe17 100644
--- a/src/mesa/drivers/dri/i965/brw_inst.h
+++ b/src/mesa/drivers/dri/i965/brw_inst.h
@@ -694,7 +694,7 @@ brw_inst_bits(const brw_inst *inst, unsigned high, unsigned 
low)
high %= 64;
low %= 64;
 
-   const uint64_t mask = (1ull << (high - low + 1)) - 1;
+   const uint64_t mask = (~0ul >> (64 - (high - low + 1)));
 
return (inst->data[word] >> low) & mask;
 }
@@ -713,7 +713,7 @@ brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned 
low, uint64_t value)
high %= 64;
low %= 64;
 
-   const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
+   const uint64_t mask = (~0ul >> (64 - (high - low + 1))) << low;
 
/* Make sure the supplied value actually fits in the given bitfield. */
assert((value & (mask >> low)) == value);

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Mesa (master): glsl: fix max binding validation for uniform blocks

2015-11-22 Thread Timothy Arceri 
Module: Mesa
Branch: master
Commit: 6463d36394bf95f73cfe3ba6bdf900da431e4e55
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6463d36394bf95f73cfe3ba6bdf900da431e4e55

Author: Timothy Arceri 
Date:   Mon Nov 23 10:07:30 2015 +1100

glsl: fix max binding validation for uniform blocks

Regression as of 64710db66461e

We can't use the type returned by get_interface_type() as
the interface type has arrays removed.

Reviewed-by: Emil Velikov 

---

 src/glsl/ast_to_hir.cpp |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index df6dd9b..81cde73 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -6962,8 +6962,8 @@ ast_interface_block::hir(exec_list *instructions,
  delete var;
   } else {
  if (this->layout.flags.q.explicit_binding) {
-apply_explicit_binding(state, , var,
-   var->get_interface_type(), >layout);
+apply_explicit_binding(state, , var, var->type,
+   >layout);
  }
 
  var->data.stream = qual_stream;

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Mesa (master): nouveau: use the buffer usage to determine placement when no binding

2015-11-22 Thread Ilia Mirkin 
Module: Mesa
Branch: master
Commit: 079f713754a9e5d7802b655d54320bd37f24fbfa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=079f713754a9e5d7802b655d54320bd37f24fbfa

Author: Ilia Mirkin 
Date:   Sun Nov 22 20:58:56 2015 -0500

nouveau: use the buffer usage to determine placement when no binding

With ARB_direct_state_access, buffers can be created without any binding
hints at all. We still need to allocate these buffers to VRAM or GART,
as we don't have logic down the line to place them into GPU-mappable
space. Ideally we'd be able to shift these things around based on usage.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92438
Signed-off-by: Ilia Mirkin 
Cc: "11.0 11.1" 

---

 src/gallium/drivers/nouveau/nouveau_buffer.c |8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nouveau_buffer.c 
b/src/gallium/drivers/nouveau/nouveau_buffer.c
index 68e69be..1695553 100644
--- a/src/gallium/drivers/nouveau/nouveau_buffer.c
+++ b/src/gallium/drivers/nouveau/nouveau_buffer.c
@@ -657,8 +657,8 @@ nouveau_buffer_create(struct pipe_screen *pscreen,
if (buffer->base.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
  PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
   buffer->domain = NOUVEAU_BO_GART;
-   } else if (buffer->base.bind &
-  (screen->vidmem_bindings & screen->sysmem_bindings)) {
+   } else if (buffer->base.bind == 0 || (buffer->base.bind &
+  (screen->vidmem_bindings & screen->sysmem_bindings))) {
   switch (buffer->base.usage) {
   case PIPE_USAGE_DEFAULT:
   case PIPE_USAGE_IMMUTABLE:
@@ -685,6 +685,10 @@ nouveau_buffer_create(struct pipe_screen *pscreen,
   if (buffer->base.bind & screen->sysmem_bindings)
  buffer->domain = NOUVEAU_BO_GART;
}
+   /* There can be very special situations where we want non-gpu-mapped
+* buffers, but never through this interface.
+*/
+   assert(buffer->domain);
ret = nouveau_buffer_allocate(screen, buffer, buffer->domain);
 
if (ret == false)

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Mesa (master): nv50,nvc0: properly handle buffer storage invalidation on dsa buffer

2015-11-22 Thread Ilia Mirkin 
Module: Mesa
Branch: master
Commit: ad5f6b03e793b9390e3b9f3eca68bd43f9d809eb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad5f6b03e793b9390e3b9f3eca68bd43f9d809eb

Author: Ilia Mirkin 
Date:   Sun Nov 22 21:08:16 2015 -0500

nv50,nvc0: properly handle buffer storage invalidation on dsa buffer

In case that the buffer has no bind at all, assume it can be a regular
buffer. This can happen on buffers created through the ARB_dsa
interfaces.

Signed-off-by: Ilia Mirkin 
Cc: "11.0 11.1" 

---

 src/gallium/drivers/nouveau/nv50/nv50_context.c |   15 ---
 src/gallium/drivers/nouveau/nvc0/nvc0_context.c |   17 +
 2 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_context.c 
b/src/gallium/drivers/nouveau/nv50/nv50_context.c
index f645a4d..4874b77 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_context.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_context.c
@@ -168,9 +168,10 @@ nv50_invalidate_resource_storage(struct nouveau_context 
*ctx,
  int ref)
 {
struct nv50_context *nv50 = nv50_context(>pipe);
+   unsigned bind = res->bind ? res->bind : PIPE_BIND_VERTEX_BUFFER;
unsigned s, i;
 
-   if (res->bind & PIPE_BIND_RENDER_TARGET) {
+   if (bind & PIPE_BIND_RENDER_TARGET) {
   assert(nv50->framebuffer.nr_cbufs <= PIPE_MAX_COLOR_BUFS);
   for (i = 0; i < nv50->framebuffer.nr_cbufs; ++i) {
  if (nv50->framebuffer.cbufs[i] &&
@@ -182,7 +183,7 @@ nv50_invalidate_resource_storage(struct nouveau_context 
*ctx,
  }
   }
}
-   if (res->bind & PIPE_BIND_DEPTH_STENCIL) {
+   if (bind & PIPE_BIND_DEPTH_STENCIL) {
   if (nv50->framebuffer.zsbuf &&
   nv50->framebuffer.zsbuf->texture == res) {
  nv50->dirty |= NV50_NEW_FRAMEBUFFER;
@@ -192,11 +193,11 @@ nv50_invalidate_resource_storage(struct nouveau_context 
*ctx,
   }
}
 
-   if (res->bind & (PIPE_BIND_VERTEX_BUFFER |
-PIPE_BIND_INDEX_BUFFER |
-PIPE_BIND_CONSTANT_BUFFER |
-PIPE_BIND_STREAM_OUTPUT |
-PIPE_BIND_SAMPLER_VIEW)) {
+   if (bind & (PIPE_BIND_VERTEX_BUFFER |
+   PIPE_BIND_INDEX_BUFFER |
+   PIPE_BIND_CONSTANT_BUFFER |
+   PIPE_BIND_STREAM_OUTPUT |
+   PIPE_BIND_SAMPLER_VIEW)) {
 
   assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
   for (i = 0; i < nv50->num_vtxbufs; ++i) {
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
index 82ed5a1..162661f 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
@@ -180,9 +180,10 @@ nvc0_invalidate_resource_storage(struct nouveau_context 
*ctx,
  int ref)
 {
struct nvc0_context *nvc0 = nvc0_context(>pipe);
+   unsigned bind = res->bind ? res->bind : PIPE_BIND_VERTEX_BUFFER;
unsigned s, i;
 
-   if (res->bind & PIPE_BIND_RENDER_TARGET) {
+   if (bind & PIPE_BIND_RENDER_TARGET) {
   for (i = 0; i < nvc0->framebuffer.nr_cbufs; ++i) {
  if (nvc0->framebuffer.cbufs[i] &&
  nvc0->framebuffer.cbufs[i]->texture == res) {
@@ -193,7 +194,7 @@ nvc0_invalidate_resource_storage(struct nouveau_context 
*ctx,
  }
   }
}
-   if (res->bind & PIPE_BIND_DEPTH_STENCIL) {
+   if (bind & PIPE_BIND_DEPTH_STENCIL) {
   if (nvc0->framebuffer.zsbuf &&
   nvc0->framebuffer.zsbuf->texture == res) {
  nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
@@ -203,12 +204,12 @@ nvc0_invalidate_resource_storage(struct nouveau_context 
*ctx,
   }
}
 
-   if (res->bind & (PIPE_BIND_VERTEX_BUFFER |
-PIPE_BIND_INDEX_BUFFER |
-PIPE_BIND_CONSTANT_BUFFER |
-PIPE_BIND_STREAM_OUTPUT |
-PIPE_BIND_COMMAND_ARGS_BUFFER |
-PIPE_BIND_SAMPLER_VIEW)) {
+   if (bind & (PIPE_BIND_VERTEX_BUFFER |
+   PIPE_BIND_INDEX_BUFFER |
+   PIPE_BIND_CONSTANT_BUFFER |
+   PIPE_BIND_STREAM_OUTPUT |
+   PIPE_BIND_COMMAND_ARGS_BUFFER |
+   PIPE_BIND_SAMPLER_VIEW)) {
   for (i = 0; i < nvc0->num_vtxbufs; ++i) {
  if (nvc0->vtxbuf[i].buffer == res) {
 nvc0->dirty |= NVC0_NEW_ARRAYS;

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Mesa (master): i965: Fix num_uniforms count for scalar GS.

2015-11-22 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: 86fc97da0627cd4a81c2e190d2e157571eead111
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=86fc97da0627cd4a81c2e190d2e157571eead111

Author: Kenneth Graunke 
Date:   Fri Nov 13 13:29:16 2015 -0800

i965: Fix num_uniforms count for scalar GS.

I noticed that brw_vs.c does this.

I believe the point is that nir->num_uniforms is either counted in
scalar components (in scalar mode), or vec4 slots (in vector mode).
But we want param_count to be in scalar components regardless, so
we have to scale up in vector mode.

We don't have to scale up in scalar mode, though.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_gs.c |4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_gs.c 
b/src/mesa/drivers/dri/i965/brw_gs.c
index ad5b242..149b43b 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -75,7 +75,9 @@ brw_codegen_gs_prog(struct brw_context *brw,
 * every uniform is a float which gets padded to the size of a vec4.
 */
struct gl_shader *gs = prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
-   int param_count = gp->program.Base.nir->num_uniforms * 4;
+   int param_count = gp->program.Base.nir->num_uniforms;
+   if (!compiler->scalar_stage[MESA_SHADER_GEOMETRY])
+  param_count *= 4;
 
prog_data.base.base.param =
   rzalloc_array(NULL, const gl_constant_value *, param_count);

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Mesa (master): virgl: pipe_virgl_create_screen is not static

2015-11-22 Thread Emil Velikov 
Module: Mesa
Branch: master
Commit: 05eed0eca71f8c35f315b3b0d7de30f3ff1878b4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=05eed0eca71f8c35f315b3b0d7de30f3ff1878b4

Author: Igor Gnatenko 
Date:   Sun Nov 22 10:12:09 2015 +0100

virgl: pipe_virgl_create_screen is not static

Cc: mesa-sta...@lists.freedesktop.org
Fixes: 17d3a5f8579 "target-helpers: add a non-inline drm_helper.h"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93063
Signed-off-by: Igor Gnatenko 
Reviewed-by: Emil Velikov 

---

 src/gallium/auxiliary/target-helpers/drm_helper.h |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/target-helpers/drm_helper.h 
b/src/gallium/auxiliary/target-helpers/drm_helper.h
index 73a80b6..332b1cb 100644
--- a/src/gallium/auxiliary/target-helpers/drm_helper.h
+++ b/src/gallium/auxiliary/target-helpers/drm_helper.h
@@ -223,7 +223,7 @@ pipe_freedreno_create_screen(int fd)
 #include "virgl/drm/virgl_drm_public.h"
 #include "virgl/virgl_public.h"
 
-static struct pipe_screen *
+struct pipe_screen *
 pipe_virgl_create_screen(int fd)
 {
struct virgl_winsys *vws;

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Mesa (master): mesa/extensions: Enable overriding permanently enabled extensions

2015-11-22 Thread Nanley Chery 
Module: Mesa
Branch: master
Commit: 21d43fe51ab5bcbc89ad5c61a51d3517c4243298
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=21d43fe51ab5bcbc89ad5c61a51d3517c4243298

Author: Nanley Chery 
Date:   Fri Nov 20 16:15:04 2015 -0800

mesa/extensions: Enable overriding permanently enabled extensions

Provide the ability to prevent any permanently enabled extension
from appearing in the string returned by glGetString[i]().

Signed-off-by: Nanley Chery 
Reviewed-by: Brian Paul 
Tested-by: Brian Paul 

---

 src/mesa/main/extensions.c |   64 +---
 1 file changed, 24 insertions(+), 40 deletions(-)

diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index 01cfdf1..fa50cb6 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
@@ -40,7 +40,6 @@
 struct gl_extensions _mesa_extension_override_enables;
 struct gl_extensions _mesa_extension_override_disables;
 static char *extra_extensions = NULL;
-static char *cant_disable_extensions = NULL;
 
 
 /**
@@ -68,29 +67,30 @@ const struct mesa_extension _mesa_extension_table[] = {
 #undef EXT
 };
 
+static bool disabled_extensions[ARRAY_SIZE(_mesa_extension_table)];
 
 /**
  * Given an extension name, lookup up the corresponding member of struct
- * gl_extensions and return that member's offset (in bytes).  If the name is
- * not found in the \c _mesa_extension_table, return 0.
+ * gl_extensions and return that member's index.  If the name is
+ * not found in the \c _mesa_extension_table, return -1.
  *
  * \param name Name of extension.
- * \return Offset of member in struct gl_extensions.
+ * \return Index of member in struct gl_extensions.
  */
-static size_t
-name_to_offset(const char* name)
+static int
+name_to_index(const char* name)
 {
unsigned i;
 
if (name == 0)
-  return 0;
+  return -1;
 
for (i = 0; i < ARRAY_SIZE(_mesa_extension_table); ++i) {
   if (strcmp(name, _mesa_extension_table[i].name) == 0)
-return _mesa_extension_table[i].offset;
+return i;
}
 
-   return 0;
+   return -1;
 }
 
 /**
@@ -206,11 +206,11 @@ _mesa_enable_sw_extensions(struct gl_context *ctx)
  * \return offset of extensions withint `ext' or 0 if extension is not known
  */
 static size_t
-set_extension(struct gl_extensions *ext, const char *name, GLboolean state)
+set_extension(struct gl_extensions *ext, int i, GLboolean state)
 {
size_t offset;
 
-   offset = name_to_offset(name);
+   offset = i < 0 ? 0 : _mesa_extension_table[i].offset;
if (offset != 0 && (offset != o(dummy_true) || state != GL_FALSE)) {
   ((GLboolean *) ext)[offset] = state;
}
@@ -240,12 +240,6 @@ get_extension_override( struct gl_context *ctx )
 {
override_extensions_in_context(ctx);
 
-   if (cant_disable_extensions != NULL) {
-  _mesa_problem(ctx,
-"Trying to disable permanently enabled extensions: %s",
-   cant_disable_extensions);
-   }
-
if (extra_extensions == NULL) {
   return calloc(1, sizeof(char));
} else {
@@ -257,7 +251,7 @@ get_extension_override( struct gl_context *ctx )
 
 
 /**
- * \brief Free extra_extensions and cant_disable_extensions strings
+ * \brief Free extra_extensions string
  *
  * These strings are allocated early during the first context creation by
  * _mesa_one_time_init_extension_overrides.
@@ -266,7 +260,6 @@ static void
 free_unknown_extensions_strings(void)
 {
free(extra_extensions);
-   free(cant_disable_extensions);
 }
 
 
@@ -295,22 +288,20 @@ _mesa_one_time_init_extension_overrides(void)
 
/* extra_exts: List of unrecognized extensions. */
extra_extensions = calloc(ALIGN(strlen(env_const) + 2, 4), sizeof(char));
-   cant_disable_extensions = calloc(ALIGN(strlen(env_const) + 2, 4), 
sizeof(char));
 
/* Copy env_const because strtok() is destructive. */
env = strdup(env_const);
 
if (env == NULL ||
-   extra_extensions == NULL ||
-   cant_disable_extensions == NULL) {
+   extra_extensions == NULL) {
   free(env);
   free(extra_extensions);
-  free(cant_disable_extensions);
   return;
}
 
for (ext = strtok(env, " "); ext != NULL; ext = strtok(NULL, " ")) {
   int enable;
+  int i;
   bool recognized;
   switch (ext[0]) {
   case '+':
@@ -326,7 +317,8 @@ _mesa_one_time_init_extension_overrides(void)
  break;
   }
 
-  offset = set_extension(&_mesa_extension_override_enables, ext, enable);
+  i = name_to_index(ext);
+  offset = set_extension(&_mesa_extension_override_enables, i, enable);
   if (offset != 0 && (offset != o(dummy_true) || enable != GL_FALSE)) {
  ((GLboolean *) &_mesa_extension_override_disables)[offset] = !enable;
  recognized = true;
@@ -334,14 +326,12 @@ _mesa_one_time_init_extension_overrides(void)
  recognized = false;
   }
 
-  if

Mesa (master): mesa/teximage: Fix S3TC regression due to ASTC interaction

2015-11-22 Thread Nanley Chery 
Module: Mesa
Branch: master
Commit: d1212abf505a468c9947a66dbf2d59acb4616e42
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1212abf505a468c9947a66dbf2d59acb4616e42

Author: Nanley Chery 
Date:   Wed Oct 28 14:50:58 2015 -0700

mesa/teximage: Fix S3TC regression due to ASTC interaction

A prior, literal reading of the ASTC spec led to the prohibition
of some compressed formats being used against the targets:
TEXTURE_CUBE_MAP_ARRAY and TEXTURE_3D. Since the spec does not specify
interactions with other extensions for specific compressed textures,
remove such interactions.

Fixes the following Piglit tests on Gen9:
piglit.spec.arb_direct_state_access.getcompressedtextureimage
piglit.spec.arb_get_texture_sub_image.arb_get_texture_sub_image-getcompressed
piglit.spec.arb_texture_cube_map_array.fbo-generatemipmap-cubemap array 
s3tc_dxt1
piglit.spec.ext_texture_compression_s3tc.getteximage-targets cube_array s3tc

v2. Don't interact with other specific compressed formats (Ian).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91927
Suggested-by: Neil Roberts 
Signed-off-by: Nanley Chery 
Reviewed-by: Ilia Mirkin 

---

 src/mesa/main/teximage.c |   43 +++
 1 file changed, 15 insertions(+), 28 deletions(-)

diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index d9453e3..ac7599f 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -1333,21 +1333,6 @@ _mesa_target_can_be_compressed(const struct gl_context 
*ctx, GLenum target,
   break;
case GL_PROXY_TEXTURE_CUBE_MAP_ARRAY:
case GL_TEXTURE_CUBE_MAP_ARRAY:
-  /* From section 3.8.6, page 146 of OpenGL ES 3.0 spec:
-   *
-   *"The ETC2/EAC texture compression algorithm supports only
-   * two-dimensional images. If internalformat is an ETC2/EAC format,
-   * glCompressedTexImage3D will generate an INVALID_OPERATION error if
-   * target is not TEXTURE_2D_ARRAY."
-   *
-   * This should also be applicable for glTexStorage3D(). Other available
-   * targets for these functions are: TEXTURE_3D and 
TEXTURE_CUBE_MAP_ARRAY.
-   */
-  if (layout == MESA_FORMAT_LAYOUT_ETC2 && _mesa_is_gles3(ctx))
-return write_error(error, GL_INVALID_OPERATION);
-
-  target_can_be_compresed = ctx->Extensions.ARB_texture_cube_map_array;
-
   /* From the KHR_texture_compression_astc_hdr spec:
*
* Add a second new column "3D Tex." which is empty for all non-ASTC
@@ -1368,16 +1353,24 @@ _mesa_target_can_be_compressed(const struct gl_context 
*ctx, GLenum target,
*  8.19 is *not* checked'
*
* The instances of  above should say .
+   *
+   * ETC2/EAC formats are the only alternative in GLES and thus such errors
+   * have already been handled by normal ETC2/EAC behavior.
*/
 
-  /* Throw an INVALID_OPERATION error if the target is
-   * TEXTURE_CUBE_MAP_ARRAY and the format is not ASTC.
+  /* From section 3.8.6, page 146 of OpenGL ES 3.0 spec:
+   *
+   *"The ETC2/EAC texture compression algorithm supports only
+   * two-dimensional images. If internalformat is an ETC2/EAC format,
+   * glCompressedTexImage3D will generate an INVALID_OPERATION error if
+   * target is not TEXTURE_2D_ARRAY."
+   *
+   * This should also be applicable for glTexStorage3D(). Other available
+   * targets for these functions are: TEXTURE_3D and 
TEXTURE_CUBE_MAP_ARRAY.
*/
-  if (target_can_be_compresed &&
-  ctx->Extensions.KHR_texture_compression_astc_ldr &&
-  layout != MESA_FORMAT_LAYOUT_ASTC)
- return write_error(error, GL_INVALID_OPERATION);
-
+  if (layout == MESA_FORMAT_LAYOUT_ETC2 && _mesa_is_gles3(ctx))
+return write_error(error, GL_INVALID_OPERATION);
+  target_can_be_compresed = ctx->Extensions.ARB_texture_cube_map_array;
   break;
case GL_TEXTURE_3D:
   switch (layout) {
@@ -1401,12 +1394,6 @@ _mesa_target_can_be_compressed(const struct gl_context 
*ctx, GLenum target,
 return write_error(error, GL_INVALID_OPERATION);
  break;
   default:
- /* Throw an INVALID_OPERATION error if the target is TEXTURE_3D and
-  * the format is not ASTC.
-  * See comment in switch case GL_TEXTURE_CUBE_MAP_ARRAY for more info.
-  */
- if (ctx->Extensions.KHR_texture_compression_astc_ldr)
-return write_error(error, GL_INVALID_OPERATION);
  break;
   }
default:

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Mesa (master): vc4: Take precedence over ilo when in simulator mode.

2015-11-22 Thread Eric Anholt 
Module: Mesa
Branch: master
Commit: 1b62a4e885267c374dbbe5d5bb2c36515eee6a95
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b62a4e885267c374dbbe5d5bb2c36515eee6a95

Author: Eric Anholt 
Date:   Sat Nov 21 12:52:48 2015 -0800

vc4: Take precedence over ilo when in simulator mode.

They're exclusive at build time, but the ilo entry is always present, so
we'd try to use it and fail out.

v2: Add comment in the code, from Emil.

Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Emil Velikov 

---

 .../auxiliary/pipe-loader/pipe_loader_drm.c|   20 
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c 
b/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
index b5dfc56..994a284 100644
--- a/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
+++ b/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
@@ -94,6 +94,18 @@ static const struct drm_driver_descriptor 
driver_descriptors[] = {
 .create_screen = pipe_i915_create_screen,
 .configuration = configuration_query,
 },
+#ifdef USE_VC4_SIMULATOR
+/* VC4 simulator and ILO (i965) are mutually exclusive (error at
+ * configure). As the latter is unconditionally added, keep this one above
+ * it.
+ */
+{
+.name = "i965",
+.driver_name = "vc4",
+.create_screen = pipe_vc4_create_screen,
+.configuration = configuration_query,
+},
+#endif
 {
 .name = "i965",
 .driver_name = "i915",
@@ -154,14 +166,6 @@ static const struct drm_driver_descriptor 
driver_descriptors[] = {
 .create_screen = pipe_vc4_create_screen,
 .configuration = configuration_query,
 },
-#ifdef USE_VC4_SIMULATOR
-{
-.name = "i965",
-.driver_name = "vc4",
-.create_screen = pipe_vc4_create_screen,
-.configuration = configuration_query,
-},
-#endif
 };
 #endif
 

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Mesa (master): vc4: Just put USE_VC4_SIMULATOR in DEFINES.

2015-11-22 Thread Eric Anholt 
Module: Mesa
Branch: master
Commit: a39eac80fd491abb990b0b77dd5e4adc5b9c53e1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a39eac80fd491abb990b0b77dd5e4adc5b9c53e1

Author: Eric Anholt 
Date:   Sat Nov 21 13:07:42 2015 -0800

vc4: Just put USE_VC4_SIMULATOR in DEFINES.

In the pipe-loader reworks, it was missed in one of the new directories it
was used.

Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Emil Velikov 

---

 configure.ac |4 +++-
 src/gallium/drivers/vc4/Automake.inc |4 
 src/gallium/drivers/vc4/Makefile.am  |1 -
 3 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/configure.ac b/configure.ac
index 91fdfe5..120c93e 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2173,7 +2173,9 @@ if test -n "$with_gallium_drivers"; then
 gallium_require_drm_loader
 
 PKG_CHECK_MODULES([SIMPENROSE], [simpenrose],
-  [USE_VC4_SIMULATOR=yes], [USE_VC4_SIMULATOR=no])
+  [USE_VC4_SIMULATOR=yes;
+   DEFINES="$DEFINES -DUSE_VC4_SIMULATOR"],
+  [USE_VC4_SIMULATOR=no])
 ;;
 xvirgl)
 HAVE_GALLIUM_VIRGL=yes
diff --git a/src/gallium/drivers/vc4/Automake.inc 
b/src/gallium/drivers/vc4/Automake.inc
index 6fa3e19..5664c2a 100644
--- a/src/gallium/drivers/vc4/Automake.inc
+++ b/src/gallium/drivers/vc4/Automake.inc
@@ -6,8 +6,4 @@ TARGET_LIB_DEPS += \
$(top_builddir)/src/gallium/winsys/vc4/drm/libvc4drm.la \
$(top_builddir)/src/gallium/drivers/vc4/libvc4.la
 
-if USE_VC4_SIMULATOR
-TARGET_CPPFLAGS += -DUSE_VC4_SIMULATOR
-endif
-
 endif
diff --git a/src/gallium/drivers/vc4/Makefile.am 
b/src/gallium/drivers/vc4/Makefile.am
index f4a57ba..a3bf72f 100644
--- a/src/gallium/drivers/vc4/Makefile.am
+++ b/src/gallium/drivers/vc4/Makefile.am
@@ -23,7 +23,6 @@ include Makefile.sources
 include $(top_srcdir)/src/gallium/Automake.inc
 
 if USE_VC4_SIMULATOR
-SIM_CFLAGS = -DUSE_VC4_SIMULATOR=1
 SIM_LDFLAGS = -lsimpenrose
 endif
 

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