date:20160412

Mesa (master): scons: Allow building with Address Sanitizer.

2016-04-12 Thread Jose Fonseca

Module: Mesa
Branch: master
Commit: fa46848e51a619aba5a748316fe8fe4c2e17d243
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa46848e51a619aba5a748316fe8fe4c2e17d243

Author: Jose Fonseca 
Date:   Sat Apr  9 20:26:42 2016 +0100

scons: Allow building with Address Sanitizer.

libasan is never linked to shared objects (which doesn't go well with
-z,defs).  It must either be linked to the main executable, or (more
practically for OpenGL drivers) be pre-loaded via LD_PRELOAD.

Otherwise works.

I didn't find anything with llvmpipe.  I suspect the fact that the
JIT compiled code isn't instrumented means there are lots of errors it
can't catch.

But for non-JIT drivers, the Address/Leak Sanitizers seem like a faster
alternative to Valgrind.

Usage (Ubuntu 15.10):

   scons asan=1 libgl-xlib
   export 
LD_LIBRARY_PATH=$PWD/build/linux-x86_64-debug/gallium/targets/libgl-xlib
   LD_PRELOAD=libasan.so.2 any-opengl-application

Acked-by: Roland Scheidegger 

---

 common.py |  1 +
 scons/gallium.py  | 12 +++-
 src/gallium/targets/libgl-xlib/SConscript | 12 
 src/mesa/drivers/x11/SConscript   |  8 ++--
 4 files changed, 26 insertions(+), 7 deletions(-)

diff --git a/common.py b/common.py
index 7a93941..70e6708 100644
--- a/common.py
+++ b/common.py
@@ -97,6 +97,7 @@ def AddOptions(opts):
 opts.Add(BoolOption('embedded', 'embedded build', 'no'))
 opts.Add(BoolOption('analyze',
 'enable static code analysis where available', 'no'))
+opts.Add(BoolOption('asan', 'enable Address Sanitizer', 'no'))
 opts.Add('toolchain', 'compiler toolchain', default_toolchain)
 opts.Add(BoolOption('gles', 'EXPERIMENTAL: enable OpenGL ES support',
 'no'))
diff --git a/scons/gallium.py b/scons/gallium.py
index 4652016..f37042d 100755
--- a/scons/gallium.py
+++ b/scons/gallium.py
@@ -410,7 +410,7 @@ def generate(env):
 # Work around aliasing bugs - developers should comment this out
 ccflags += ['-fno-strict-aliasing']
 ccflags += ['-g']
-if env['build'] in ('checked', 'profile'):
+if env['build'] in ('checked', 'profile') or env['asan']:
 # See 
http://code.google.com/p/jrfonseca/wiki/Gprof2Dot#Which_options_should_I_pass_to_gcc_when_compiling_for_profiling?
 ccflags += [
 '-fno-omit-frame-pointer',
@@ -540,6 +540,16 @@ def generate(env):
 # scan-build will produce more comprehensive output
 env.Append(CCFLAGS = ['--analyze'])
 
+# https://github.com/google/sanitizers/wiki/AddressSanitizer
+if env['asan']:
+if gcc_compat:
+env.Append(CCFLAGS = [
+'-fsanitize=address',
+])
+env.Append(LINKFLAGS = [
+'-fsanitize=address',
+])
+
 # Assembler options
 if gcc_compat:
 if env['machine'] == 'x86':
diff --git a/src/gallium/targets/libgl-xlib/SConscript 
b/src/gallium/targets/libgl-xlib/SConscript
index e1c78dd..1c816ff 100644
--- a/src/gallium/targets/libgl-xlib/SConscript
+++ b/src/gallium/targets/libgl-xlib/SConscript
@@ -48,11 +48,15 @@ if env['llvm']:
 env.Prepend(LIBS = [llvmpipe])
 
 if env['platform'] != 'darwin':
+# Disallow undefined symbols, except with Address Sanitizer, since libasan
+# is not linked on shared libs, as it should be LD_PRELOAD'ed instead
+if not env['asan']:
+env.Append(SHLINKFLAGS = [
+'-Wl,-z,defs',
+])
 env.Append(SHLINKFLAGS = [
-   # Disallow undefined symbols
-   '-Wl,-z,defs',
-   # Restrict exported symbols
-   '-Wl,--version-script=%s' % File("libgl-xlib.sym").srcnode().path,
+# Restrict exported symbols
+'-Wl,--version-script=%s' % File("libgl-xlib.sym").srcnode().path,
 ])
 
 # libGL.so.1.5
diff --git a/src/mesa/drivers/x11/SConscript b/src/mesa/drivers/x11/SConscript
index 4541997..59c8df4 100644
--- a/src/mesa/drivers/x11/SConscript
+++ b/src/mesa/drivers/x11/SConscript
@@ -34,9 +34,13 @@ sources = [
'xm_tri.c',
 ]
 
-# Disallow undefined symbols
 if env['platform'] != 'darwin':
-env.Append(SHLINKFLAGS = ['-Wl,-z,defs'])
+# Disallow undefined symbols, except with Address Sanitizer, since libasan
+# is not linked on shared libs, as it should be LD_PRELOAD'ed instead
+if not env['asan']:
+env.Append(SHLINKFLAGS = [
+'-Wl,-z,defs',
+])
 
 # libGL.so.1.6
 libgl_1_6 = env.SharedLibrary(

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Mesa (master): mesa: Change an error code in glSamplerParameterI[iu]v().

2016-04-12 Thread Kenneth Graunke

Module: Mesa
Branch: master
Commit: d1c89f60050fa5acd0bd1faa993de902631482a0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1c89f60050fa5acd0bd1faa993de902631482a0

Author: Kenneth Graunke 
Date:   Tue Apr 12 15:23:47 2016 -0700

mesa: Change an error code in glSamplerParameterI[iu]v().

This is supposed to be INVALID_OPERATION in ES.  We already did this
for the fv/iv variants, but not Iiv/Iuv, which are new in ES 3.2 (or
extensions).

Fixes:
ES31-CTS.texture_border_clamp.samplerparameteri_non_gen_sampler_error

Signed-off-by: Kenneth Graunke 
Reviewed-by: Ilia Mirkin 

---

 src/mesa/main/samplerobj.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/mesa/main/samplerobj.c b/src/mesa/main/samplerobj.c
index ca366d9..7476195 100644
--- a/src/mesa/main/samplerobj.c
+++ b/src/mesa/main/samplerobj.c
@@ -1171,8 +1171,9 @@ _mesa_SamplerParameterIiv(GLuint sampler, GLenum pname, 
const GLint *params)
 
sampObj = _mesa_lookup_samplerobj(ctx, sampler);
if (!sampObj) {
-  _mesa_error(ctx, GL_INVALID_VALUE, "glSamplerParameterIiv(sampler %u)",
-  sampler);
+  _mesa_error(ctx, (_mesa_is_gles(ctx) ?
+GL_INVALID_OPERATION : GL_INVALID_VALUE),
+  "glSamplerParameterIiv(sampler %u)", sampler);
   return;
}
 
@@ -1257,8 +1258,9 @@ _mesa_SamplerParameterIuiv(GLuint sampler, GLenum pname, 
const GLuint *params)
 
sampObj = _mesa_lookup_samplerobj(ctx, sampler);
if (!sampObj) {
-  _mesa_error(ctx, GL_INVALID_VALUE, "glSamplerParameterIuiv(sampler %u)",
-  sampler);
+  _mesa_error(ctx, (_mesa_is_gles(ctx) ?
+GL_INVALID_OPERATION : GL_INVALID_VALUE),
+  "glSamplerParameterIuiv(sampler %u)", sampler);
   return;
}
 

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Mesa (master): softpipe: Enable ARB_framebuffer_no_attachments

2016-04-12 Thread Dave Airlie

Module: Mesa
Branch: master
Commit: 5a3d928e2cd8eeb4776c732cab5c0fce9d593ea2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a3d928e2cd8eeb4776c732cab5c0fce9d593ea2

Author: Edward O'Callaghan 
Date:   Sun Apr 10 17:41:30 2016 +1000

softpipe: Enable ARB_framebuffer_no_attachments

Signed-off-by: Edward O'Callaghan 
Signed-off-by: Dave Airlie 

---

 docs/GL3.txt | 4 ++--
 docs/relnotes/11.3.0.html| 2 +-
 src/gallium/drivers/softpipe/sp_screen.c | 3 ++-
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index 39f5122..dc75cf8 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -172,7 +172,7 @@ GL 4.3, GLSL 4.30:
   GL_KHR_debug  DONE (all drivers)
   GL_ARB_explicit_uniform_location  DONE (all drivers that 
support GLSL)
   GL_ARB_fragment_layer_viewportDONE (i965, nv50, 
nvc0, r600, radeonsi, llvmpipe)
-  GL_ARB_framebuffer_no_attachments DONE (i965, nvc0, 
r600, radeonsi)
+  GL_ARB_framebuffer_no_attachments DONE (i965, nvc0, 
r600, radeonsi, softpipe)
   GL_ARB_internalformat_query2  DONE (all drivers)
   GL_ARB_invalidate_subdata DONE (all drivers)
   GL_ARB_multi_draw_indirectDONE (i965, nvc0, 
r600, radeonsi, llvmpipe, softpipe)
@@ -228,7 +228,7 @@ GLES3.1, GLSL ES 3.1
   GL_ARB_compute_shader DONE (i965)
   GL_ARB_draw_indirect  DONE (i965, nvc0, 
r600, radeonsi, llvmpipe, softpipe)
   GL_ARB_explicit_uniform_location  DONE (all drivers that 
support GLSL)
-  GL_ARB_framebuffer_no_attachments DONE (i965, nvc0, 
r600, radeonsi)
+  GL_ARB_framebuffer_no_attachments DONE (i965, nvc0, 
r600, radeonsi, softpipe)
   GL_ARB_program_interface_queryDONE (all drivers)
   GL_ARB_shader_atomic_counters DONE (i965, nvc0, 
radeonsi, softpipe)
   GL_ARB_shader_image_load_storeDONE (i965, softpipe, 
radeonsi)
diff --git a/docs/relnotes/11.3.0.html b/docs/relnotes/11.3.0.html
index 1815cfc..0f9aed8 100644
--- a/docs/relnotes/11.3.0.html
+++ b/docs/relnotes/11.3.0.html
@@ -45,7 +45,7 @@ Note: some of the new features are only available with 
certain drivers.
 
 
 OpenGL 4.2 on radeonsi
-GL_ARB_framebuffer_no_attachments on nvc0, r600, radeonsi
+GL_ARB_framebuffer_no_attachments on nvc0, r600, radeonsi, softpipe
 GL_ARB_internalformat_query2 on all drivers
 GL_ARB_robust_buffer_access_behavior on radeonsi
 GL_ARB_shader_atomic_counters on radeonsi, softpipe
diff --git a/src/gallium/drivers/softpipe/sp_screen.c 
b/src/gallium/drivers/softpipe/sp_screen.c
index 9f87e03..d89d95c 100644
--- a/src/gallium/drivers/softpipe/sp_screen.c
+++ b/src/gallium/drivers/softpipe/sp_screen.c
@@ -239,6 +239,8 @@ softpipe_get_param(struct pipe_screen *screen, enum 
pipe_cap param)
case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
   return 1;
+   case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
+  return 1;
case PIPE_CAP_VERTEXID_NOBASE:
   return 0;
case PIPE_CAP_POLYGON_OFFSET_CLAMP:
@@ -269,7 +271,6 @@ softpipe_get_param(struct pipe_screen *screen, enum 
pipe_cap param)
case PIPE_CAP_PCI_BUS:
case PIPE_CAP_PCI_DEVICE:
case PIPE_CAP_PCI_FUNCTION:
-   case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
   return 0;
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:

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Mesa (master): softpipe: Free tgsi.image elements on context destruction.

2016-04-12 Thread Dave Airlie

Module: Mesa
Branch: master
Commit: 46bfcd61f5ca81fc7e19f0d74ee9fa70f16e9df7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=46bfcd61f5ca81fc7e19f0d74ee9fa70f16e9df7

Author: Jose Fonseca 
Date:   Tue Apr 12 17:03:52 2016 +0100

softpipe: Free tgsi.image elements on context destruction.

Courtesy of address sanitizer.

[airlied: free buffers as well]
Reviewed-by: Roland Scheidegger 
Signed-off-by: Dave Airlie 

---

 src/gallium/drivers/softpipe/sp_context.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/drivers/softpipe/sp_context.c 
b/src/gallium/drivers/softpipe/sp_context.c
index f66fea2..0342fc6 100644
--- a/src/gallium/drivers/softpipe/sp_context.c
+++ b/src/gallium/drivers/softpipe/sp_context.c
@@ -117,6 +117,8 @@ softpipe_destroy( struct pipe_context *pipe )
 
for (i = 0; i < PIPE_SHADER_TYPES; i++) {
   FREE(softpipe->tgsi.sampler[i]);
+  FREE(softpipe->tgsi.image[i]);
+  FREE(softpipe->tgsi.buffer[i]);
}
 
FREE( softpipe );

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Mesa (master): vc4: Work around hardware limits on the number of verts in a single draw.

2016-04-12 Thread Eric Anholt

Module: Mesa
Branch: master
Commit: 3b63301d9fff43119359eaeb34f80426919f0b4a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b63301d9fff43119359eaeb34f80426919f0b4a

Author: Eric Anholt 
Date:   Fri Dec 12 15:17:53 2014 -0800

vc4: Work around hardware limits on the number of verts in a single draw.

Fixes rendering failures in glmark2's refract and
bump:render-mode=high-poly demos, and partially in its terrain demo.

---

 src/gallium/drivers/vc4/vc4_draw.c | 110 +++--
 1 file changed, 92 insertions(+), 18 deletions(-)

diff --git a/src/gallium/drivers/vc4/vc4_draw.c 
b/src/gallium/drivers/vc4/vc4_draw.c
index 9b0b540..68b8573 100644
--- a/src/gallium/drivers/vc4/vc4_draw.c
+++ b/src/gallium/drivers/vc4/vc4_draw.c
@@ -32,12 +32,19 @@
 #include "vc4_resource.h"
 
 static void
-vc4_get_draw_cl_space(struct vc4_context *vc4)
+vc4_get_draw_cl_space(struct vc4_context *vc4, int vert_count)
 {
+/* The SW-5891 workaround may cause us to emit multiple shader recs
+ * and draw packets.
+ */
+int num_draws = DIV_ROUND_UP(vert_count, 65535) + 1;
+
 /* Binner gets our packet state -- vc4_emit.c contents,
  * and the primitive itself.
  */
-cl_ensure_space(>bcl, 256);
+cl_ensure_space(>bcl,
+256 + (VC4_PACKET_GL_ARRAY_PRIMITIVE_SIZE +
+   VC4_PACKET_GL_SHADER_STATE_SIZE) * num_draws);
 
 /* Nothing for rcl -- that's covered by vc4_context.c */
 
@@ -45,7 +52,8 @@ vc4_get_draw_cl_space(struct vc4_context *vc4)
  * sized shader_rec (104 bytes base for 8 vattrs plus 32 bytes of
  * vattr stride).
  */
-cl_ensure_space(>shader_rec, 12 * sizeof(uint32_t) + 104 + 8 * 
32);
+cl_ensure_space(>shader_rec,
+(12 * sizeof(uint32_t) + 104 + 8 * 32) * num_draws);
 
 /* Uniforms are covered by vc4_write_uniforms(). */
 
@@ -61,12 +69,12 @@ vc4_get_draw_cl_space(struct vc4_context *vc4)
  * Does the initial bining command list setup for drawing to a given FBO.
  */
 static void
-vc4_start_draw(struct vc4_context *vc4)
+vc4_start_draw(struct vc4_context *vc4, int vert_count)
 {
 if (vc4->needs_flush)
 return;
 
-vc4_get_draw_cl_space(vc4);
+vc4_get_draw_cl_space(vc4, 0);
 
 struct vc4_cl_out *bcl = cl_start(>bcl);
 //   Tile state data is 48 bytes per tile, I think it can be thrown 
away
@@ -119,7 +127,8 @@ vc4_update_shadow_textures(struct pipe_context *pctx,
 }
 
 static void
-vc4_emit_gl_shader_state(struct vc4_context *vc4, const struct pipe_draw_info 
*info)
+vc4_emit_gl_shader_state(struct vc4_context *vc4, const struct pipe_draw_info 
*info,
+ uint32_t extra_index_bias)
 {
 /* VC4_DIRTY_VTXSTATE */
 struct vc4_vertex_stateobj *vtx = vc4->vtx;
@@ -170,7 +179,8 @@ vc4_emit_gl_shader_state(struct vc4_context *vc4, const 
struct pipe_draw_info *i
 /* not vc4->dirty tracked: vc4->last_index_bias */
 uint32_t offset = (vb->buffer_offset +
elem->src_offset +
-   vb->stride * info->index_bias);
+   vb->stride * (info->index_bias +
+ extra_index_bias));
 uint32_t vb_size = rsc->bo->size - offset;
 uint32_t elem_size =
 util_format_get_blocksize(elem->src_format);
@@ -219,8 +229,9 @@ vc4_emit_gl_shader_state(struct vc4_context *vc4, const 
struct pipe_draw_info *i
>constbuf[PIPE_SHADER_VERTEX],
>verttex);
 
-vc4->last_index_bias = info->index_bias;
+vc4->last_index_bias = info->index_bias + extra_index_bias;
 vc4->max_index = max_index;
+vc4->shader_rec_count++;
 }
 
 /**
@@ -275,14 +286,14 @@ vc4_draw_vbo(struct pipe_context *pctx, const struct 
pipe_draw_info *info)
 
 vc4_hw_2116_workaround(pctx);
 
-vc4_get_draw_cl_space(vc4);
+vc4_get_draw_cl_space(vc4, info->count);
 
 if (vc4->prim_mode != info->mode) {
 vc4->prim_mode = info->mode;
 vc4->dirty |= VC4_DIRTY_PRIM_MODE;
 }
 
-vc4_start_draw(vc4);
+vc4_start_draw(vc4, info->count);
 vc4_update_compiled_shaders(vc4, info->mode);
 
 vc4_emit_state(pctx);
@@ -298,7 +309,7 @@ vc4_draw_vbo(struct pipe_context *pctx, const struct 
pipe_draw_info *info)
vc4->prog.vs->uniform_dirty_bits |
vc4->prog.fs->uniform_dirty_bits)) ||
 vc4->last_index_bias != info->index_bias) {
-vc4_emit_gl_shader_state(vc4, info);
+vc4_emit_gl_shader_state(vc4, info, 0);
 }
 
 vc4->dirty = 0;
@@ -342,10 +353,75 @@

Mesa (master): tgsi: fix buffer overflow

2016-04-12 Thread Dave Airlie

Module: Mesa
Branch: master
Commit: b89708f95fafc458cc79bc210407b723a0f0f78c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b89708f95fafc458cc79bc210407b723a0f0f78c

Author: Thomas Hindoe Paaboel Andersen 
Date:   Wed Apr 13 03:06:05 2016 +0200

tgsi: fix buffer overflow

Increase r to four channels as rgba is written to it
Reviewed-by: Edward O'Callaghan 

Signed-off-by: Dave Airlie 

---

 src/gallium/auxiliary/tgsi/tgsi_exec.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c 
b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index fb51051..41dd0f0 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -4011,7 +4011,7 @@ static void
 exec_atomop_buf(struct tgsi_exec_machine *mach,
 const struct tgsi_full_instruction *inst)
 {
-   union tgsi_exec_channel r[3];
+   union tgsi_exec_channel r[4];
union tgsi_exec_channel value[4], value2[4];
float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];

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Mesa (master): softpipe: avoid buffer overflow

2016-04-12 Thread Dave Airlie

Module: Mesa
Branch: master
Commit: 6d6525a377250865cc6baa2c9cd5c6c0b6cd3f9c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d6525a377250865cc6baa2c9cd5c6c0b6cd3f9c

Author: Thomas Hindoe Paaboel Andersen 
Date:   Wed Apr 13 03:06:06 2016 +0200

softpipe: avoid buffer overflow

Signed-off-by: Dave Airlie 

---

 src/gallium/drivers/softpipe/sp_buffer.c | 8 
 src/gallium/drivers/softpipe/sp_image.c  | 8 
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/softpipe/sp_buffer.c 
b/src/gallium/drivers/softpipe/sp_buffer.c
index 69717ba..69a6bd1 100644
--- a/src/gallium/drivers/softpipe/sp_buffer.c
+++ b/src/gallium/drivers/softpipe/sp_buffer.c
@@ -59,7 +59,7 @@ sp_tgsi_load(const struct tgsi_buffer *buffer,
unsigned char *data_ptr;
const struct util_format_description *format_desc = 
util_format_description(PIPE_FORMAT_R32_UINT);
 
-   if (params->unit > PIPE_MAX_SHADER_BUFFERS)
+   if (params->unit >= PIPE_MAX_SHADER_BUFFERS)
   goto fail_write_all_zero;
 
bview = _buf->sp_bview[params->unit];
@@ -117,7 +117,7 @@ sp_tgsi_store(const struct tgsi_buffer *buffer,
int j, c;
const struct util_format_description *format_desc = 
util_format_description(PIPE_FORMAT_R32_UINT);
 
-   if (params->unit > PIPE_MAX_SHADER_BUFFERS)
+   if (params->unit >= PIPE_MAX_SHADER_BUFFERS)
   return;
 
bview = _buf->sp_bview[params->unit];
@@ -293,7 +293,7 @@ sp_tgsi_op(const struct tgsi_buffer *buffer,
int j, c;
unsigned char *data_ptr;
 
-   if (params->unit > PIPE_MAX_SHADER_BUFFERS)
+   if (params->unit >= PIPE_MAX_SHADER_BUFFERS)
   return;
 
bview = _buf->sp_bview[params->unit];
@@ -345,7 +345,7 @@ sp_tgsi_get_dims(const struct tgsi_buffer *buffer,
struct pipe_shader_buffer *bview;
struct softpipe_resource *spr;
 
-   if (params->unit > PIPE_MAX_SHADER_BUFFERS)
+   if (params->unit >= PIPE_MAX_SHADER_BUFFERS)
   return;
 
bview = _buf->sp_bview[params->unit];
diff --git a/src/gallium/drivers/softpipe/sp_image.c 
b/src/gallium/drivers/softpipe/sp_image.c
index 3488fa8..a7c7328 100644
--- a/src/gallium/drivers/softpipe/sp_image.c
+++ b/src/gallium/drivers/softpipe/sp_image.c
@@ -217,7 +217,7 @@ sp_tgsi_load(const struct tgsi_image *image,
char *data_ptr;
unsigned offset = 0;
 
-   if (params->unit > PIPE_MAX_SHADER_IMAGES)
+   if (params->unit >= PIPE_MAX_SHADER_IMAGES)
   goto fail_write_all_zero;
iview = _img->sp_iview[params->unit];
spr = (struct softpipe_resource *)iview->resource;
@@ -320,7 +320,7 @@ sp_tgsi_store(const struct tgsi_image *image,
unsigned offset = 0;
unsigned pformat = params->format;
 
-   if (params->unit > PIPE_MAX_SHADER_IMAGES)
+   if (params->unit >= PIPE_MAX_SHADER_IMAGES)
   return;
iview = _img->sp_iview[params->unit];
spr = (struct softpipe_resource *)iview->resource;
@@ -630,7 +630,7 @@ sp_tgsi_op(const struct tgsi_image *image,
unsigned offset;
char *data_ptr;
 
-   if (params->unit > PIPE_MAX_SHADER_IMAGES)
+   if (params->unit >= PIPE_MAX_SHADER_IMAGES)
   return;
iview = _img->sp_iview[params->unit];
spr = (struct softpipe_resource *)iview->resource;
@@ -704,7 +704,7 @@ sp_tgsi_get_dims(const struct tgsi_image *image,
struct softpipe_resource *spr;
int level;
 
-   if (params->unit > PIPE_MAX_SHADER_IMAGES)
+   if (params->unit >= PIPE_MAX_SHADER_IMAGES)
   return;
iview = _img->sp_iview[params->unit];
spr = (struct softpipe_resource *)iview->resource;

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Mesa (master): swr: support samplers in vertex shaders

2016-04-12 Thread Tim Rowley

Module: Mesa
Branch: master
Commit: b19d214b238228bfebfe3869b6aee540993fe706
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b19d214b238228bfebfe3869b6aee540993fe706

Author: Tim Rowley 
Date:   Wed Mar 30 22:40:25 2016 -0500

swr: support samplers in vertex shaders

Reviewed-by: George Kyriazis 

---

 src/gallium/drivers/swr/swr_shader.cpp |  98 +++---
 src/gallium/drivers/swr/swr_shader.h   |  41 +---
 src/gallium/drivers/swr/swr_state.cpp  | 153 +++--
 src/gallium/drivers/swr/swr_state.h|   6 +-
 src/gallium/drivers/swr/swr_tex_sample.cpp |  33 ++-
 src/gallium/drivers/swr/swr_tex_sample.h   |   2 +-
 6 files changed, 228 insertions(+), 105 deletions(-)

diff --git a/src/gallium/drivers/swr/swr_shader.cpp 
b/src/gallium/drivers/swr/swr_shader.cpp
index ff16d0f..90f0f22 100644
--- a/src/gallium/drivers/swr/swr_shader.cpp
+++ b/src/gallium/drivers/swr/swr_shader.cpp
@@ -40,32 +40,29 @@
 #include "swr_state.h"
 #include "swr_screen.h"
 
-bool operator==(const swr_jit_key , const swr_jit_key )
+bool operator==(const swr_jit_fs_key , const swr_jit_fs_key )
 {
return !memcmp(, , sizeof(lhs));
 }
 
-void
-swr_generate_fs_key(struct swr_jit_key ,
-struct swr_context *ctx,
-swr_fragment_shader *swr_fs)
+bool operator==(const swr_jit_vs_key , const swr_jit_vs_key )
 {
-   key.nr_cbufs = ctx->framebuffer.nr_cbufs;
-   key.light_twoside = ctx->rasterizer->light_twoside;
-   memcpy(_output_semantic_name,
-  >vs->info.base.output_semantic_name,
-  sizeof(key.vs_output_semantic_name));
-   memcpy(_output_semantic_idx,
-  >vs->info.base.output_semantic_index,
-  sizeof(key.vs_output_semantic_idx));
+   return !memcmp(, , sizeof(lhs));
+}
 
-   key.nr_samplers = swr_fs->info.base.file_max[TGSI_FILE_SAMPLER] + 1;
+static void
+swr_generate_sampler_key(const struct lp_tgsi_info ,
+ struct swr_context *ctx,
+ unsigned shader_type,
+ struct swr_jit_sampler_key )
+{
+   key.nr_samplers = info.base.file_max[TGSI_FILE_SAMPLER] + 1;
 
for (unsigned i = 0; i < key.nr_samplers; i++) {
-  if (swr_fs->info.base.file_mask[TGSI_FILE_SAMPLER] & (1 << i)) {
+  if (info.base.file_mask[TGSI_FILE_SAMPLER] & (1 << i)) {
  lp_sampler_static_sampler_state(
 [i].sampler_state,
-ctx->samplers[PIPE_SHADER_FRAGMENT][i]);
+ctx->samplers[shader_type][i]);
   }
}
 
@@ -74,28 +71,57 @@ swr_generate_fs_key(struct swr_jit_key ,
 * are dx10-style? Can't really have mixed opcodes, at least not
 * if we want to skip the holes here (without rescanning tgsi).
 */
-   if (swr_fs->info.base.file_max[TGSI_FILE_SAMPLER_VIEW] != -1) {
+   if (info.base.file_max[TGSI_FILE_SAMPLER_VIEW] != -1) {
   key.nr_sampler_views =
- swr_fs->info.base.file_max[TGSI_FILE_SAMPLER_VIEW] + 1;
+ info.base.file_max[TGSI_FILE_SAMPLER_VIEW] + 1;
   for (unsigned i = 0; i < key.nr_sampler_views; i++) {
- if (swr_fs->info.base.file_mask[TGSI_FILE_SAMPLER_VIEW] & (1 << i)) {
+ if (info.base.file_mask[TGSI_FILE_SAMPLER_VIEW] & (1 << i)) {
 lp_sampler_static_texture_state(
[i].texture_state,
-   ctx->sampler_views[PIPE_SHADER_FRAGMENT][i]);
+   ctx->sampler_views[shader_type][i]);
  }
   }
} else {
   key.nr_sampler_views = key.nr_samplers;
   for (unsigned i = 0; i < key.nr_sampler_views; i++) {
- if (swr_fs->info.base.file_mask[TGSI_FILE_SAMPLER] & (1 << i)) {
+ if (info.base.file_mask[TGSI_FILE_SAMPLER] & (1 << i)) {
 lp_sampler_static_texture_state(
[i].texture_state,
-   ctx->sampler_views[PIPE_SHADER_FRAGMENT][i]);
+   ctx->sampler_views[shader_type][i]);
  }
   }
}
 }
 
+void
+swr_generate_fs_key(struct swr_jit_fs_key ,
+struct swr_context *ctx,
+swr_fragment_shader *swr_fs)
+{
+   memset(, 0, sizeof(key));
+
+   key.nr_cbufs = ctx->framebuffer.nr_cbufs;
+   key.light_twoside = ctx->rasterizer->light_twoside;
+   memcpy(_output_semantic_name,
+  >vs->info.base.output_semantic_name,
+  sizeof(key.vs_output_semantic_name));
+   memcpy(_output_semantic_idx,
+  >vs->info.base.output_semantic_index,
+  sizeof(key.vs_output_semantic_idx));
+
+   swr_generate_sampler_key(swr_fs->info, ctx, PIPE_SHADER_FRAGMENT, key);
+}
+
+void
+swr_generate_vs_key(struct swr_jit_vs_key ,
+struct swr_context *ctx,
+swr_vertex_shader *swr_vs)
+{
+   memset(, 0, sizeof(key));
+
+   swr_generate_sampler_key(swr_vs->info, ctx, PIPE_SHADER_VERTEX, key);
+}
+
 struct BuilderSWR : public Builder {
BuilderSWR(JitManager *pJitMgr)
   :

Mesa (master): swr: handle pci cap requests

2016-04-12 Thread Tim Rowley

Module: Mesa
Branch: master
Commit: b9294bc3452737914e2528775b3ae2099ab74110
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9294bc3452737914e2528775b3ae2099ab74110

Author: Tim Rowley 
Date:   Fri Apr  1 19:58:29 2016 -0500

swr: handle pci cap requests

Reviewed-by: George Kyriazis 

---

 src/gallium/drivers/swr/swr_screen.cpp | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/drivers/swr/swr_screen.cpp 
b/src/gallium/drivers/swr/swr_screen.cpp
index dcf896e..a0a6324 100644
--- a/src/gallium/drivers/swr/swr_screen.cpp
+++ b/src/gallium/drivers/swr/swr_screen.cpp
@@ -338,6 +338,10 @@ swr_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
case PIPE_CAP_QUERY_BUFFER_OBJECT:
case PIPE_CAP_QUERY_MEMORY_INFO:
case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
+   case PIPE_CAP_PCI_GROUP:
+   case PIPE_CAP_PCI_BUS:
+   case PIPE_CAP_PCI_DEVICE:
+   case PIPE_CAP_PCI_FUNCTION:
   return 0;
}
 

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Mesa (master): radeonsi: enable GLSL 4.20 and therefore OpenGL 4.2

2016-04-12 Thread Nicolai Hähnle

Module: Mesa
Branch: master
Commit: 10cfd7a6045ffbfd0debf66d2dfd2caeeb559951
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=10cfd7a6045ffbfd0debf66d2dfd2caeeb559951

Author: Nicolai Hähnle 
Date:   Thu Mar 17 19:53:36 2016 -0500

radeonsi: enable GLSL 4.20 and therefore OpenGL 4.2

This is the last necessary bit for OpenGL 4.2 support. All driver-specific
functionality has already been implemented as part of extensions.

Reviewed-by: Edward O'Callaghan 

---

 docs/GL3.txt   | 2 +-
 docs/relnotes/11.3.0.html  | 7 ---
 src/gallium/drivers/radeonsi/si_pipe.c | 3 ++-
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index 7535dc5..39f5122 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -146,7 +146,7 @@ GL 4.1, GLSL 4.10 --- all DONE: nvc0, r600, radeonsi
   GL_ARB_viewport_array DONE (i965, nv50, 
llvmpipe, softpipe)
 
 
-GL 4.2, GLSL 4.20:
+GL 4.2, GLSL 4.20 -- all DONE: radeonsi
 
   GL_ARB_texture_compression_bptc   DONE (i965, nvc0, 
r600, radeonsi)
   GL_ARB_compressed_texture_pixel_storage   DONE (all drivers)
diff --git a/docs/relnotes/11.3.0.html b/docs/relnotes/11.3.0.html
index 9860ab0..1815cfc 100644
--- a/docs/relnotes/11.3.0.html
+++ b/docs/relnotes/11.3.0.html
@@ -22,11 +22,11 @@ People who are concerned with stability and reliability 
should stick
 with a previous release or wait for Mesa 11.3.1.
 
 
-Mesa 11.3.0 implements the OpenGL 4.1 API, but the version reported by
+Mesa 11.3.0 implements the OpenGL 4.2 API, but the version reported by
 glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
 glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.1.  OpenGL
-4.1 is only available if requested at context creation
+Some drivers don't support all the features required in OpenGL 4.2.  OpenGL
+4.2 is only available if requested at context creation
 because compatibility contexts are not supported.
 
 
@@ -44,6 +44,7 @@ Note: some of the new features are only available with 
certain drivers.
 
 
 
+OpenGL 4.2 on radeonsi
 GL_ARB_framebuffer_no_attachments on nvc0, r600, radeonsi
 GL_ARB_internalformat_query2 on all drivers
 GL_ARB_robust_buffer_access_behavior on radeonsi
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 6b4b3d2..1dd7338 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -336,7 +336,8 @@ static int si_get_param(struct pipe_screen* pscreen, enum 
pipe_cap param)
return 4;
 
case PIPE_CAP_GLSL_FEATURE_LEVEL:
-   return HAVE_LLVM >= 0x0307 ? 410 : 330;
+   return HAVE_LLVM >= 0x0309 ? 420 :
+  HAVE_LLVM >= 0x0307 ? 410 : 330;
 
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
return MIN2(sscreen->b.info.vram_size, 0x);

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Mesa (master): va: check null context in vlVaDestroyContext

2016-04-12 Thread Julien Isorce

Module: Mesa
Branch: master
Commit: 047e3264f67bc54365be7b0e163b6910a9e9de3a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=047e3264f67bc54365be7b0e163b6910a9e9de3a

Author: Iurie Salomov 
Date:   Tue Apr 12 23:24:30 2016 +0100

va: check null context in vlVaDestroyContext

Signed-off-by: Iurie Salomov 
Reviewed-by: Julien Isorce 

---

 src/gallium/state_trackers/va/context.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/state_trackers/va/context.c 
b/src/gallium/state_trackers/va/context.c
index b25c381..25d587a 100644
--- a/src/gallium/state_trackers/va/context.c
+++ b/src/gallium/state_trackers/va/context.c
@@ -283,6 +283,10 @@ vlVaDestroyContext(VADriverContextP ctx, VAContextID 
context_id)
drv = VL_VA_DRIVER(ctx);
pipe_mutex_lock(drv->mutex);
context = handle_table_get(drv->htab, context_id);
+   if (!context) {
+  pipe_mutex_unlock(drv->mutex);
+  return VA_STATUS_ERROR_INVALID_CONTEXT;
+   }
 
if (context->decoder) {
   if (u_reduce_video_profile(context->decoder->profile) ==

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Mesa (master): nir/clone: Copy bit size when cloning registers

2016-04-12 Thread Jason Ekstrand

Module: Mesa
Branch: master
Commit: 8f3b516f2e9e3066792fe244351427f8775ce214
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f3b516f2e9e3066792fe244351427f8775ce214

Author: Jason Ekstrand 
Date:   Mon Apr 11 14:46:14 2016 -0700

nir/clone: Copy bit size when cloning registers

Reported-by: Mark Janes 
Reviewed-by: Eduardo Lima Mitev 

---

 src/compiler/nir/nir_clone.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/compiler/nir/nir_clone.c b/src/compiler/nir/nir_clone.c
index e889f19..e231387 100644
--- a/src/compiler/nir/nir_clone.c
+++ b/src/compiler/nir/nir_clone.c
@@ -179,6 +179,7 @@ clone_register(clone_state *state, const nir_register *reg)
add_remap(state, nreg, reg);
 
nreg->num_components = reg->num_components;
+   nreg->bit_size = reg->bit_size;
nreg->num_array_elems = reg->num_array_elems;
nreg->index = reg->index;
nreg->name = ralloc_strdup(nreg, reg->name);

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Mesa (master): radeonsi: fix a critical SI hang since PIPELINESTAT_START/ STOP was added

2016-04-12 Thread Marek Olšák

Module: Mesa
Branch: master
Commit: 8e70a58af394a8699aecdaad6e406a9183ce2090
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e70a58af394a8699aecdaad6e406a9183ce2090

Author: Marek Olšák 
Date:   Tue Apr 12 23:39:42 2016 +0200

radeonsi: fix a critical SI hang since PIPELINESTAT_START/STOP was added

For some reason unknown to me, SI hangs if the event is written after
CONTEXT_CONTROL.

---

 src/gallium/drivers/radeonsi/si_hw_context.c | 3 ++-
 src/gallium/drivers/radeonsi/si_state.c  | 8 
 2 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c 
b/src/gallium/drivers/radeonsi/si_hw_context.c
index 242c22c..b621b55 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -155,7 +155,8 @@ void si_begin_new_cs(struct si_context *ctx)
SI_CONTEXT_INV_VMEM_L1 |
SI_CONTEXT_INV_GLOBAL_L2 |
SI_CONTEXT_INV_SMEM_L1 |
-   SI_CONTEXT_INV_ICACHE;
+   SI_CONTEXT_INV_ICACHE |
+   R600_CONTEXT_START_PIPELINE_STATS;
 
/* set all valid group as dirty so they get reemited on
 * next draw command
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 664506e..4d24fa3 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3817,14 +3817,6 @@ static void si_init_config(struct si_context *sctx)
si_pm4_cmd_add(pm4, 0x8000);
si_pm4_cmd_end(pm4, false);
 
-   /* This enables pipeline stat & streamout queries.
-* They are only disabled by blits.
-*/
-   si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
-   si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
-   EVENT_INDEX(0));
-   si_pm4_cmd_end(pm4, false);
-
si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
 

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Mesa (master): glsl: Don't copy propagate or tree graft precise values.

2016-04-12 Thread Kenneth Graunke

Module: Mesa
Branch: master
Commit: 95d622e16df0ddbf52e43a34bd6ed6dd15e3bdee
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=95d622e16df0ddbf52e43a34bd6ed6dd15e3bdee

Author: Kenneth Graunke 
Date:   Sun Apr  3 02:02:12 2016 -0700

glsl: Don't copy propagate or tree graft precise values.

This is kind of a hack.  We currently track precise requirements
by decorating ir_variables.  Propagating or grafting the RHS of an
assignment to a precise value into some other expression tree can
lose those decorations.

In the long run, it might be better to replace these ir_variable
decorations with an "exact" decoration on ir_expression nodes,
similar to what NIR does.

In the short run, this is probably good enough.  It preserves
enough information for glsl_to_nir to generate "exact" decorations,
and NIR will then handle optimizing these expressions reasonably.

Fixes ES31-CTS.gpu_shader5.precise_qualifier.

v2: Drop invariant handling, as it shouldn't be necessary (caught
by Jason Ekstrand).

Signed-off-by: Kenneth Graunke 
Reviewed-by: Jason Ekstrand 

---

 src/compiler/glsl/opt_copy_propagation.cpp  | 3 ++-
 src/compiler/glsl/opt_copy_propagation_elements.cpp | 3 +++
 src/compiler/glsl/opt_tree_grafting.cpp | 3 +++
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/compiler/glsl/opt_copy_propagation.cpp 
b/src/compiler/glsl/opt_copy_propagation.cpp
index 310708d..ae62921 100644
--- a/src/compiler/glsl/opt_copy_propagation.cpp
+++ b/src/compiler/glsl/opt_copy_propagation.cpp
@@ -331,7 +331,8 @@ ir_copy_propagation_visitor::add_copy(ir_assignment *ir)
 ir->condition = new(ralloc_parent(ir)) ir_constant(false);
 this->progress = true;
   } else if (lhs_var->data.mode != ir_var_shader_storage &&
- lhs_var->data.mode != ir_var_shader_shared) {
+ lhs_var->data.mode != ir_var_shader_shared &&
+ lhs_var->data.precise == rhs_var->data.precise) {
 entry = new(this->acp) acp_entry(lhs_var, rhs_var);
 this->acp->push_tail(entry);
   }
diff --git a/src/compiler/glsl/opt_copy_propagation_elements.cpp 
b/src/compiler/glsl/opt_copy_propagation_elements.cpp
index a679180..e9e7c53 100644
--- a/src/compiler/glsl/opt_copy_propagation_elements.cpp
+++ b/src/compiler/glsl/opt_copy_propagation_elements.cpp
@@ -493,6 +493,9 @@ 
ir_copy_propagation_elements_visitor::add_copy(ir_assignment *ir)
   }
}
 
+   if (lhs->var->data.precise != rhs->var->data.precise)
+  return;
+
entry = new(this->mem_ctx) acp_entry(lhs->var, rhs->var, write_mask,
swizzle);
this->acp->push_tail(entry);
diff --git a/src/compiler/glsl/opt_tree_grafting.cpp 
b/src/compiler/glsl/opt_tree_grafting.cpp
index 812f996..a40e5f7 100644
--- a/src/compiler/glsl/opt_tree_grafting.cpp
+++ b/src/compiler/glsl/opt_tree_grafting.cpp
@@ -368,6 +368,9 @@ tree_grafting_basic_block(ir_instruction *bb_first,
   lhs_var->data.mode == ir_var_shader_shared)
  continue;
 
+  if (lhs_var->data.precise)
+ continue;
+
   ir_variable_refcount_entry *entry = 
info->refs->get_variable_entry(lhs_var);
 
   if (!entry->declaration ||

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Mesa (vulkan): util: Fix race condition on libgcrypt initialization

2016-04-12 Thread Mark Janes

Module: Mesa
Branch: vulkan
Commit: 9e351e077befbdc179f7926edd8b5dde02f20494
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e351e077befbdc179f7926edd8b5dde02f20494

Author: Mark Janes 
Date:   Tue Apr 12 11:52:53 2016 -0700

util: Fix race condition on libgcrypt initialization

Fixes intermittent Vulkan CTS failures within the test groups:
dEQP-VK.api.object_management.multithreaded_per_thread_device
dEQP-VK.api.object_management.multithreaded_per_thread_resources
dEQP-VK.api.object_management.multithreaded_shared_resources

Signed-off-by: Mark Janes 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94904

Reviewed-by: Edward O'Callaghan 
Reviewed-by: Jason Ekstrand 

---

 src/util/mesa-sha1.c | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/src/util/mesa-sha1.c b/src/util/mesa-sha1.c
index faa1c87..ca6b89b 100644
--- a/src/util/mesa-sha1.c
+++ b/src/util/mesa-sha1.c
@@ -175,21 +175,24 @@ _mesa_sha1_final(struct mesa_sha1 *ctx, unsigned char 
result[20])
 #elif defined(HAVE_SHA1_IN_LIBGCRYPT)   /* Use libgcrypt for SHA1 */
 
 #include 
+#include "c11/threads.h"
+
+static void _mesa_libgcrypt_init(void)
+{
+   if (!gcry_check_version(NULL))
+  return NULL;
+   gcry_control(GCRYCTL_DISABLE_SECMEM, 0);
+   gcry_control(GCRYCTL_INITIALIZATION_FINISHED, 0);
+}
 
 struct mesa_sha1 *
 _mesa_sha1_init(void)
 {
-   static int init;
+   static once_flag flag = ONCE_FLAG_INIT;
gcry_md_hd_t h;
gcry_error_t err;
 
-   if (!init) {
-  if (!gcry_check_version(NULL))
- return NULL;
-  gcry_control(GCRYCTL_DISABLE_SECMEM, 0);
-  gcry_control(GCRYCTL_INITIALIZATION_FINISHED, 0);
-  init = 1;
-   }
+   call_once(, _mesa_libgcrypt_init);
 
err = gcry_md_open(, GCRY_MD_SHA1, 0);
if (err)

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Mesa (master): glsl/linker: Add add_shader_variable() helper

2016-04-12 Thread Kristian Høgsberg

Module: Mesa
Branch: master
Commit: 8ab6aae4dcecba4e77f6777606e92cf2c2f1f83e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ab6aae4dcecba4e77f6777606e92cf2c2f1f83e

Author: Kristian Høgsberg Kristensen 
Date:   Mon Apr 11 12:57:41 2016 -0700

glsl/linker: Add add_shader_variable() helper

This consolidates the combination of create_shader_variable() and
add_program_resource() into a new helper function. No functional
difference, but we'll expand add_shader_variable() in the next few
commits.

Signed-off-by: Kristian Høgsberg Kristensen 
Reviewed-by: Kenneth Graunke 

---

 src/compiler/glsl/linker.cpp | 42 +++---
 1 file changed, 23 insertions(+), 19 deletions(-)

diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index 10b5a8f..63b3fdf 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -3569,6 +3569,19 @@ create_shader_variable(struct gl_shader_program *shProg,
 }
 
 static bool
+add_shader_variable(struct gl_shader_program *shProg, unsigned stage_mask,
+GLenum programInterface, ir_variable *var,
+bool use_implicit_location, int location_bias)
+{
+   gl_shader_variable *sha_v =
+  create_shader_variable(shProg, var, use_implicit_location, 
location_bias);
+   if (!sha_v)
+  return false;
+
+   return add_program_resource(shProg, programInterface, sha_v, stage_mask);
+}
+
+static bool
 add_interface_variables(struct gl_shader_program *shProg,
 unsigned stage, GLenum programInterface)
 {
@@ -3616,12 +3629,8 @@ add_interface_variables(struct gl_shader_program *shProg,
  (stage == MESA_SHADER_VERTEX && var->data.mode == ir_var_shader_in) ||
  (stage == MESA_SHADER_FRAGMENT && var->data.mode == 
ir_var_shader_out);
 
-  gl_shader_variable *sha_v =
- create_shader_variable(shProg, var, vs_input_or_fs_output, loc_bias);
-  if (!sha_v)
- return false;
-
-  if (!add_program_resource(shProg, programInterface, sha_v, 1 << stage))
+  if (!add_shader_variable(shProg, 1 << stage, programInterface,
+   var, vs_input_or_fs_output, loc_bias))
  return false;
}
return true;
@@ -3651,13 +3660,10 @@ add_packed_varyings(struct gl_shader_program *shProg, 
int stage, GLenum type)
  }
 
  if (type == iface) {
-gl_shader_variable *sha_v =
-   create_shader_variable(shProg, var, false, VARYING_SLOT_VAR0);
-if (!sha_v)
-   return false;
-if (!add_program_resource(shProg, iface, sha_v,
-  build_stageref(shProg, sha_v->name,
- sha_v->mode)))
+const int stage_mask =
+   build_stageref(shProg, var->name, var->data.mode);
+if (!add_shader_variable(shProg, stage_mask,
+ iface, var, false, VARYING_SLOT_VAR0))
return false;
  }
   }
@@ -3677,12 +3683,10 @@ add_fragdata_arrays(struct gl_shader_program *shProg)
   ir_variable *var = node->as_variable();
   if (var) {
  assert(var->data.mode == ir_var_shader_out);
- gl_shader_variable *sha_v =
-create_shader_variable(shProg, var, true, FRAG_RESULT_DATA0);
- if (!sha_v)
-return false;
- if (!add_program_resource(shProg, GL_PROGRAM_OUTPUT, sha_v,
-   1 << MESA_SHADER_FRAGMENT))
+
+ if (!add_shader_variable(shProg,
+  1 << MESA_SHADER_FRAGMENT,
+  GL_PROGRAM_OUTPUT, var, true, 
FRAG_RESULT_DATA0))
 return false;
   }
}

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Mesa (master): glsl/linker: Recurse on struct fields when adding shader variables

2016-04-12 Thread Kristian Høgsberg

Module: Mesa
Branch: master
Commit: 1af0f0151c6ae7d8634a642ad7a13713f395ca4d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1af0f0151c6ae7d8634a642ad7a13713f395ca4d

Author: Kristian Høgsberg Kristensen 
Date:   Mon Apr 11 14:28:18 2016 -0700

glsl/linker: Recurse on struct fields when adding shader variables

ARB_program_interface_query requires that we add struct fields
recursively down to basic types.

Fixes 52 struct test cases in dEQP-GLES31.functional.program_interface_query.*

Signed-off-by: Kristian Høgsberg Kristensen 
Reviewed-by: Kenneth Graunke 

---

 src/compiler/glsl/linker.cpp | 51 ++--
 1 file changed, 45 insertions(+), 6 deletions(-)

diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index c1bc699..0773d42 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -3575,13 +3575,52 @@ add_shader_variable(struct gl_shader_program *shProg, 
unsigned stage_mask,
 const char *name, const glsl_type *type,
 bool use_implicit_location, int location)
 {
-   gl_shader_variable *sha_v =
-  create_shader_variable(shProg, var, name, type,
- use_implicit_location, location);
-   if (!sha_v)
-  return false;
+   const bool vertex_input_slots =
+  programInterface == GL_PROGRAM_INPUT &&
+  stage_mask == MESA_SHADER_VERTEX;
+
+   switch (type->base_type) {
+   case GLSL_TYPE_STRUCT: {
+  /* From the ARB_program_interface_query specification:
+   *
+   *  "For an active variable declared as a structure, a separate entry
+   *   will be generated for each active structure member.  The name of
+   *   each entry is formed by concatenating the name of the structure,
+   *   the "."  character, and the name of the structure member.  If a
+   *   structure member to enumerate is itself a structure or array, these
+   *   enumeration rules are applied recursively."
+   */
+  unsigned field_location = location;
+  for (unsigned i = 0; i < type->length; i++) {
+ const struct glsl_struct_field *field = >fields.structure[i];
+ char *field_name = ralloc_asprintf(shProg, "%s.%s", name, 
field->name);
+ if (!add_shader_variable(shProg, stage_mask, programInterface,
+  var, field_name, field->type,
+  use_implicit_location, field_location))
+return false;
+
+ field_location +=
+field->type->count_attribute_slots(vertex_input_slots);
+  }
+  return true;
+   }
+
+   default: {
+  /* From the ARB_program_interface_query specification:
+   *
+   *  "For an active variable declared as a single instance of a basic
+   *   type, a single entry will be generated, using the variable name
+   *   from the shader source."
+   */
+  gl_shader_variable *sha_v =
+ create_shader_variable(shProg, var, name, type,
+use_implicit_location, location);
+  if (!sha_v)
+ return false;
 
-   return add_program_resource(shProg, programInterface, sha_v, stage_mask);
+  return add_program_resource(shProg, programInterface, sha_v, stage_mask);
+   }
+   }
 }
 
 static bool

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Mesa (master): glsl/linker: Pass name and type through to create_shader_variable()

2016-04-12 Thread Kristian Høgsberg

Module: Mesa
Branch: master
Commit: 778fd46aa4df08f2dd5d5a9162e6dce062cc1cb6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=778fd46aa4df08f2dd5d5a9162e6dce062cc1cb6

Author: Kristian Høgsberg Kristensen 
Date:   Mon Apr 11 13:06:07 2016 -0700

glsl/linker: Pass name and type through to create_shader_variable()

No functional change here, but this now lets us recurse throught structs
in add_shader_variable().

Signed-off-by: Kristian Høgsberg Kristensen 
Reviewed-by: Kenneth Graunke 

---

 src/compiler/glsl/linker.cpp | 21 -
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index 1ea5c1f..c1bc699 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -3518,8 +3518,9 @@ build_stageref(struct gl_shader_program *shProg, const 
char *name,
  */
 static gl_shader_variable *
 create_shader_variable(struct gl_shader_program *shProg,
-   const ir_variable *in, bool use_implicit_location,
-   int location)
+   const ir_variable *in,
+   const char *name, const glsl_type *type,
+   bool use_implicit_location, int location)
 {
gl_shader_variable *out = ralloc(shProg, struct gl_shader_variable);
if (!out)
@@ -3532,7 +3533,7 @@ create_shader_variable(struct gl_shader_program *shProg,
in->data.location == SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) {
   out->name = ralloc_strdup(shProg, "gl_VertexID");
} else {
-  out->name = ralloc_strdup(shProg, in->name);
+  out->name = ralloc_strdup(shProg, name);
}
 
if (!out->name)
@@ -3560,7 +3561,7 @@ create_shader_variable(struct gl_shader_program *shProg,
   out->location = location;
}
 
-   out->type = in->type;
+   out->type = type;
out->index = in->data.index;
out->patch = in->data.patch;
out->mode = in->data.mode;
@@ -3571,10 +3572,12 @@ create_shader_variable(struct gl_shader_program *shProg,
 static bool
 add_shader_variable(struct gl_shader_program *shProg, unsigned stage_mask,
 GLenum programInterface, ir_variable *var,
+const char *name, const glsl_type *type,
 bool use_implicit_location, int location)
 {
gl_shader_variable *sha_v =
-  create_shader_variable(shProg, var, use_implicit_location, location);
+  create_shader_variable(shProg, var, name, type,
+ use_implicit_location, location);
if (!sha_v)
   return false;
 
@@ -3630,7 +3633,7 @@ add_interface_variables(struct gl_shader_program *shProg,
  (stage == MESA_SHADER_FRAGMENT && var->data.mode == 
ir_var_shader_out);
 
   if (!add_shader_variable(shProg, 1 << stage, programInterface,
-   var, vs_input_or_fs_output,
+   var, var->name, var->type, 
vs_input_or_fs_output,
var->data.location - loc_bias))
  return false;
}
@@ -3664,7 +3667,7 @@ add_packed_varyings(struct gl_shader_program *shProg, int 
stage, GLenum type)
 const int stage_mask =
build_stageref(shProg, var->name, var->data.mode);
 if (!add_shader_variable(shProg, stage_mask,
- iface, var, false,
+ iface, var, var->name, var->type, false,
  var->data.location - VARYING_SLOT_VAR0))
return false;
  }
@@ -3688,8 +3691,8 @@ add_fragdata_arrays(struct gl_shader_program *shProg)
 
  if (!add_shader_variable(shProg,
   1 << MESA_SHADER_FRAGMENT,
-  GL_PROGRAM_OUTPUT, var, true,
-  var->data.location - FRAG_RESULT_DATA0))
+  GL_PROGRAM_OUTPUT, var, var->name, var->type,
+  true, var->data.location - 
FRAG_RESULT_DATA0))
 return false;
   }
}

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Mesa (master): glsl/linker: Pass absolute location to add_shader_variable( )

2016-04-12 Thread Kristian Høgsberg

Module: Mesa
Branch: master
Commit: 09f01215933f8f7f8d3d4cda9ff94605164df9a9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=09f01215933f8f7f8d3d4cda9ff94605164df9a9

Author: Kristian Høgsberg Kristensen 
Date:   Mon Apr 11 13:03:12 2016 -0700

glsl/linker: Pass absolute location to add_shader_variable()

This lets us pass in the absolution location of a variable instead of
computing it in add_shader_variable() based on variable location and
bias. This is in preparation for recursing into struct variables.

Signed-off-by: Kristian Høgsberg Kristensen 
Reviewed-by: Kenneth Graunke 

---

 src/compiler/glsl/linker.cpp | 17 ++---
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index 63b3fdf..1ea5c1f 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -3519,7 +3519,7 @@ build_stageref(struct gl_shader_program *shProg, const 
char *name,
 static gl_shader_variable *
 create_shader_variable(struct gl_shader_program *shProg,
const ir_variable *in, bool use_implicit_location,
-   int location_bias)
+   int location)
 {
gl_shader_variable *out = ralloc(shProg, struct gl_shader_variable);
if (!out)
@@ -3557,7 +3557,7 @@ create_shader_variable(struct gl_shader_program *shProg,
!(in->data.explicit_location || use_implicit_location)) {
   out->location = -1;
} else {
-  out->location = in->data.location - location_bias;
+  out->location = location;
}
 
out->type = in->type;
@@ -3571,10 +3571,10 @@ create_shader_variable(struct gl_shader_program *shProg,
 static bool
 add_shader_variable(struct gl_shader_program *shProg, unsigned stage_mask,
 GLenum programInterface, ir_variable *var,
-bool use_implicit_location, int location_bias)
+bool use_implicit_location, int location)
 {
gl_shader_variable *sha_v =
-  create_shader_variable(shProg, var, use_implicit_location, 
location_bias);
+  create_shader_variable(shProg, var, use_implicit_location, location);
if (!sha_v)
   return false;
 
@@ -3630,7 +3630,8 @@ add_interface_variables(struct gl_shader_program *shProg,
  (stage == MESA_SHADER_FRAGMENT && var->data.mode == 
ir_var_shader_out);
 
   if (!add_shader_variable(shProg, 1 << stage, programInterface,
-   var, vs_input_or_fs_output, loc_bias))
+   var, vs_input_or_fs_output,
+   var->data.location - loc_bias))
  return false;
}
return true;
@@ -3663,7 +3664,8 @@ add_packed_varyings(struct gl_shader_program *shProg, int 
stage, GLenum type)
 const int stage_mask =
build_stageref(shProg, var->name, var->data.mode);
 if (!add_shader_variable(shProg, stage_mask,
- iface, var, false, VARYING_SLOT_VAR0))
+ iface, var, false,
+ var->data.location - VARYING_SLOT_VAR0))
return false;
  }
   }
@@ -3686,7 +3688,8 @@ add_fragdata_arrays(struct gl_shader_program *shProg)
 
  if (!add_shader_variable(shProg,
   1 << MESA_SHADER_FRAGMENT,
-  GL_PROGRAM_OUTPUT, var, true, 
FRAG_RESULT_DATA0))
+  GL_PROGRAM_OUTPUT, var, true,
+  var->data.location - FRAG_RESULT_DATA0))
 return false;
   }
}

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Mesa (master): i965/tiled_memcpy: Move SSSE3 code back into inline functions.

2016-04-12 Thread Matt Turner

Module: Mesa
Branch: master
Commit: fc88b4babf86e93421e7a9da29ae125712891390
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc88b4babf86e93421e7a9da29ae125712891390

Author: Matt Turner 
Date:   Mon Apr 11 11:47:21 2016 -0700

i965/tiled_memcpy: Move SSSE3 code back into inline functions.

This will make adding SSE2 code a lot cleaner.

Reviewed-by: Roland Scheidegger 

---

 src/mesa/drivers/dri/i965/intel_tiled_memcpy.c | 42 +++---
 1 file changed, 24 insertions(+), 18 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c 
b/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
index fa5ec75..5d58530 100644
--- a/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
+++ b/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
@@ -85,6 +85,22 @@ rgba8_copy(void *dst, const void *src, size_t bytes)
 #ifdef __SSSE3__
 static const uint8_t rgba8_permutation[16] =
{ 2,1,0,3, 6,5,4,7, 10,9,8,11, 14,13,12,15 };
+
+static inline void
+rgba8_copy_16_aligned_dst(void *dst, const void *src)
+{
+   _mm_store_si128(dst,
+   _mm_shuffle_epi8(_mm_loadu_si128(src),
+*(__m128i *)rgba8_permutation));
+}
+
+static inline void
+rgba8_copy_16_aligned_src(void *dst, const void *src)
+{
+   _mm_storeu_si128(dst,
+_mm_shuffle_epi8(_mm_load_si128(src),
+ *(__m128i *)rgba8_permutation));
+}
 #endif
 
 /**
@@ -93,23 +109,18 @@ static const uint8_t rgba8_permutation[16] =
 static inline void *
 rgba8_copy_aligned_dst(void *dst, const void *src, size_t bytes)
 {
-   uint8_t *d = dst;
-   uint8_t const *s = src;
-
assert(bytes == 0 || !(((uintptr_t)dst) & 0xf));
 
 #ifdef __SSSE3__
while (bytes >= 16) {
-  _mm_store_si128((__m128i *)d,
-  _mm_shuffle_epi8(_mm_loadu_si128((__m128i *)s),
-   *(__m128i *) rgba8_permutation));
-  s += 16;
-  d += 16;
+  rgba8_copy_16_aligned_dst(dst, src);
+  src += 16;
+  dst += 16;
   bytes -= 16;
}
 #endif
 
-   rgba8_copy(d, s, bytes);
+   rgba8_copy(dst, src, bytes);
 
return dst;
 }
@@ -120,23 +131,18 @@ rgba8_copy_aligned_dst(void *dst, const void *src, size_t 
bytes)
 static inline void *
 rgba8_copy_aligned_src(void *dst, const void *src, size_t bytes)
 {
-   uint8_t *d = dst;
-   uint8_t const *s = src;
-
assert(bytes == 0 || !(((uintptr_t)src) & 0xf));
 
 #ifdef __SSSE3__
while (bytes >= 16) {
-  _mm_storeu_si128((__m128i *)d,
-   _mm_shuffle_epi8(_mm_load_si128((__m128i *)s),
-*(__m128i *) rgba8_permutation));
-  s += 16;
-  d += 16;
+  rgba8_copy_16_aligned_src(dst, src);
+  src += 16;
+  dst += 16;
   bytes -= 16;
}
 #endif
 
-   rgba8_copy(d, s, bytes);
+   rgba8_copy(dst, src, bytes);
 
return dst;
 }

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Mesa (master): i965/tiled_memcpy: Optimize RGBA -> BGRA swizzle.

2016-04-12 Thread Matt Turner

Module: Mesa
Branch: master
Commit: 0a5d8d9af42fd77fce1492d55f958da97816961a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a5d8d9af42fd77fce1492d55f958da97816961a

Author: Matt Turner 
Date:   Fri Apr  8 15:30:30 2016 -0700

i965/tiled_memcpy: Optimize RGBA -> BGRA swizzle.

Replaces four byte loads and four byte stores with a load, bswap,
rotate, store; or a movbe, rotate, store.

Reviewed-by: Roland Scheidegger 

---

 src/mesa/drivers/dri/i965/intel_tiled_memcpy.c | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c 
b/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
index 0a68751..fa5ec75 100644
--- a/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
+++ b/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
@@ -56,24 +56,27 @@ static const uint32_t ytile_width = 128;
 static const uint32_t ytile_height = 32;
 static const uint32_t ytile_span = 16;
 
+static inline uint32_t
+ror(uint32_t n, uint32_t d)
+{
+   return (n >> d) | (n << (32 - d));
+}
+
 /**
  * Copy RGBA to BGRA - swap R and B.
  */
 static inline void *
 rgba8_copy(void *dst, const void *src, size_t bytes)
 {
-   uint8_t *d = dst;
-   uint8_t const *s = src;
+   uint32_t *d = dst;
+   uint32_t const *s = src;
 
assert(bytes % 4 == 0);
 
while (bytes >= 4) {
-  d[0] = s[2];
-  d[1] = s[1];
-  d[2] = s[0];
-  d[3] = s[3];
-  d += 4;
-  s += 4;
+  *d = ror(__builtin_bswap32(*s), 8);
+  d += 1;
+  s += 1;
   bytes -= 4;
}
return dst;

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Mesa (master): i965/tiled_memcpy: Unroll bytes==64 case.

2016-04-12 Thread Matt Turner

Module: Mesa
Branch: master
Commit: eafeb8db66dae7619ff3cb039706b990d718cba7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eafeb8db66dae7619ff3cb039706b990d718cba7

Author: Matt Turner 
Date:   Mon Apr 11 11:59:59 2016 -0700

i965/tiled_memcpy: Unroll bytes==64 case.

Reviewed-by: Roland Scheidegger 

---

 src/mesa/drivers/dri/i965/intel_tiled_memcpy.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c 
b/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
index 04a348a..b61a842 100644
--- a/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
+++ b/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
@@ -149,6 +149,14 @@ rgba8_copy_aligned_dst(void *dst, const void *src, size_t 
bytes)
assert(bytes == 0 || !(((uintptr_t)dst) & 0xf));
 
 #if defined(__SSSE3__) || defined(__SSE2__)
+   if (bytes == 64) {
+  rgba8_copy_16_aligned_dst(dst +  0, src +  0);
+  rgba8_copy_16_aligned_dst(dst + 16, src + 16);
+  rgba8_copy_16_aligned_dst(dst + 32, src + 32);
+  rgba8_copy_16_aligned_dst(dst + 48, src + 48);
+  return dst;
+   }
+
while (bytes >= 16) {
   rgba8_copy_16_aligned_dst(dst, src);
   src += 16;
@@ -171,6 +179,14 @@ rgba8_copy_aligned_src(void *dst, const void *src, size_t 
bytes)
assert(bytes == 0 || !(((uintptr_t)src) & 0xf));
 
 #if defined(__SSSE3__) || defined(__SSE2__)
+   if (bytes == 64) {
+  rgba8_copy_16_aligned_dst(dst +  0, src +  0);
+  rgba8_copy_16_aligned_dst(dst + 16, src + 16);
+  rgba8_copy_16_aligned_dst(dst + 32, src + 32);
+  rgba8_copy_16_aligned_dst(dst + 48, src + 48);
+  return dst;
+   }
+
while (bytes >= 16) {
   rgba8_copy_16_aligned_src(dst, src);
   src += 16;

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Mesa (master): i965/tiled_memcpy: Provide SSE2 for RGBA8 <-> BGRA8 swizzle.

2016-04-12 Thread Matt Turner

Module: Mesa
Branch: master
Commit: 0e605d9b3af68b67dceb8eeaeabebe91bc9cf31c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e605d9b3af68b67dceb8eeaeabebe91bc9cf31c

Author: Roland Scheidegger 
Date:   Fri Jan 29 03:18:36 2016 +0100

i965/tiled_memcpy: Provide SSE2 for RGBA8 <-> BGRA8 swizzle.

The existing code uses SSSE3, and because it isn't compiled in a
separate file compiled with that, it is usually not used (that, of
course, could be fixed...), whereas SSE2 is always present with 64-bit
builds.  This should be pretty much as fast as the pshufb version,
albeit those code paths aren't really used on chips without llc in any
case.

v2: fix andnot argument order, add comments
v3: use pshuflw/hw instead of shifts (suggested by Matt Turner), cut comments
v4: [mattst88] Rebase

Reviewed-by: Matt Turner 

---

 src/mesa/drivers/dri/i965/intel_tiled_memcpy.c | 43 --
 1 file changed, 40 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c 
b/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
index 5d58530..04a348a 100644
--- a/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
+++ b/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
@@ -36,8 +36,10 @@
 #include "brw_context.h"
 #include "intel_tiled_memcpy.h"
 
-#ifdef __SSSE3__
+#if defined(__SSSE3__)
 #include 
+#elif defined(__SSE2__)
+#include 
 #endif
 
 #define FILE_DEBUG_FLAG DEBUG_TEXTURE
@@ -101,6 +103,41 @@ rgba8_copy_16_aligned_src(void *dst, const void *src)
 _mm_shuffle_epi8(_mm_load_si128(src),
  *(__m128i *)rgba8_permutation));
 }
+
+#elif defined(__SSE2__)
+static inline void
+rgba8_copy_16_aligned_dst(void *dst, const void *src)
+{
+   __m128i srcreg, dstreg, agmask, ag, rb, br;
+
+   agmask = _mm_set1_epi32(0xFF00FF00);
+   srcreg = _mm_loadu_si128((__m128i *)src);
+
+   rb = _mm_andnot_si128(agmask, srcreg);
+   ag = _mm_and_si128(agmask, srcreg);
+   br = _mm_shufflehi_epi16(_mm_shufflelo_epi16(rb, _MM_SHUFFLE(2, 3, 0, 1)),
+_MM_SHUFFLE(2, 3, 0, 1));
+   dstreg = _mm_or_si128(ag, br);
+
+   _mm_store_si128((__m128i *)dst, dstreg);
+}
+
+static inline void
+rgba8_copy_16_aligned_src(void *dst, const void *src)
+{
+   __m128i srcreg, dstreg, agmask, ag, rb, br;
+
+   agmask = _mm_set1_epi32(0xFF00FF00);
+   srcreg = _mm_load_si128((__m128i *)src);
+
+   rb = _mm_andnot_si128(agmask, srcreg);
+   ag = _mm_and_si128(agmask, srcreg);
+   br = _mm_shufflehi_epi16(_mm_shufflelo_epi16(rb, _MM_SHUFFLE(2, 3, 0, 1)),
+_MM_SHUFFLE(2, 3, 0, 1));
+   dstreg = _mm_or_si128(ag, br);
+
+   _mm_storeu_si128((__m128i *)dst, dstreg);
+}
 #endif
 
 /**
@@ -111,7 +148,7 @@ rgba8_copy_aligned_dst(void *dst, const void *src, size_t 
bytes)
 {
assert(bytes == 0 || !(((uintptr_t)dst) & 0xf));
 
-#ifdef __SSSE3__
+#if defined(__SSSE3__) || defined(__SSE2__)
while (bytes >= 16) {
   rgba8_copy_16_aligned_dst(dst, src);
   src += 16;
@@ -133,7 +170,7 @@ rgba8_copy_aligned_src(void *dst, const void *src, size_t 
bytes)
 {
assert(bytes == 0 || !(((uintptr_t)src) & 0xf));
 
-#ifdef __SSSE3__
+#if defined(__SSSE3__) || defined(__SSE2__)
while (bytes >= 16) {
   rgba8_copy_16_aligned_src(dst, src);
   src += 16;

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Mesa (master): radeonsi: fix bounds check in si_create_vertex_elements

2016-04-12 Thread Nicolai Hähnle

Module: Mesa
Branch: master
Commit: a191e6b719848a17963f185954f1696fa5a2bcb1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a191e6b719848a17963f185954f1696fa5a2bcb1

Author: Nicolai Hähnle 
Date:   Tue Apr 12 12:23:31 2016 -0500

radeonsi: fix bounds check in si_create_vertex_elements

This was triggered by
dEQP-GLES3.functional.vertex_array_objects.all_attributes

Cc: "11.1 11.2" 
Reviewed-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_state.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 85ee1c4..664506e 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3278,7 +3278,7 @@ static void *si_create_vertex_elements(struct 
pipe_context *ctx,
struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
int i;
 
-   assert(count < SI_MAX_ATTRIBS);
+   assert(count <= SI_MAX_ATTRIBS);
if (!v)
return NULL;
 

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Mesa (master): radeonsi: add shader buffer support to TGSI_OPCODE_RESQ

2016-04-12 Thread Nicolai Hähnle

Module: Mesa
Branch: master
Commit: 4e81843b135827ad7e4c6771dee574a695c3b64d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e81843b135827ad7e4c6771dee574a695c3b64d

Author: Nicolai Hähnle 
Date:   Wed Mar 16 18:03:19 2016 -0500

radeonsi: add shader buffer support to TGSI_OPCODE_RESQ

Reviewed-by: Marek Olšák 
Reviewed-by: Edward O'Callaghan 

---

 src/gallium/drivers/radeonsi/si_shader.c | 17 +++--
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 18f75da..c58467d 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -3374,14 +3374,17 @@ static void resq_fetch_args(
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
 {
+   struct si_shader_context *ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
const struct tgsi_full_instruction *inst = emit_data->inst;
const struct tgsi_full_src_register *reg = >Src[0];
-   unsigned tex_target = inst->Memory.Texture;
 
emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
 
-   if (tex_target == TGSI_TEXTURE_BUFFER) {
+   if (reg->Register.File == TGSI_FILE_BUFFER) {
+   emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
+   emit_data->arg_count = 1;
+   } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
image_fetch_rsrc(bld_base, reg, false, _data->args[0]);
emit_data->arg_count = 1;
} else {
@@ -3390,7 +3393,7 @@ static void resq_fetch_args(
emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* 
dmask */
emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
-   emit_data->args[5] = tgsi_is_array_image(tex_target) ?
+   emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da 
*/
emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
@@ -3408,10 +3411,12 @@ static void resq_emit(
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
const struct tgsi_full_instruction *inst = emit_data->inst;
-   unsigned target = inst->Memory.Texture;
LLVMValueRef out;
 
-   if (target == TGSI_TEXTURE_BUFFER) {
+   if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
+   out = LLVMBuildExtractElement(builder, emit_data->args[0],
+ lp_build_const_int32(gallivm, 2), 
"");
+   } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
out = get_buffer_size(bld_base, emit_data->args[0]);
} else {
out = lp_build_intrinsic(
@@ -3420,7 +3425,7 @@ static void resq_emit(
LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
 
/* Divide the number of layers by 6 to get the number of cubes. 
*/
-   if (target == TGSI_TEXTURE_CUBE_ARRAY) {
+   if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
 

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Mesa (master): docs: mark atomic counters and SSBOs as done for radeonsi

2016-04-12 Thread Nicolai Hähnle

Module: Mesa
Branch: master
Commit: 4285a97ceae4f5e49dc9da4be6b066c520052954
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4285a97ceae4f5e49dc9da4be6b066c520052954

Author: Nicolai Hähnle 
Date:   Mon Mar 21 17:31:15 2016 -0500

docs: mark atomic counters and SSBOs as done for radeonsi

Reviewed-by: Marek Olšák 
Reviewed-by: Edward O'Callaghan 

---

 docs/GL3.txt  | 8 
 docs/relnotes/11.3.0.html | 6 +++---
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index 423cafa..7535dc5 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -150,7 +150,7 @@ GL 4.2, GLSL 4.20:
 
   GL_ARB_texture_compression_bptc   DONE (i965, nvc0, 
r600, radeonsi)
   GL_ARB_compressed_texture_pixel_storage   DONE (all drivers)
-  GL_ARB_shader_atomic_counters DONE (i965, nvc0, 
softpipe)
+  GL_ARB_shader_atomic_counters DONE (i965, nvc0, 
radeonsi, softpipe)
   GL_ARB_texture_storageDONE (all drivers)
   GL_ARB_transform_feedback_instanced   DONE (i965, nv50, 
nvc0, r600, radeonsi, llvmpipe, softpipe)
   GL_ARB_base_instance  DONE (i965, nv50, 
nvc0, r600, radeonsi, llvmpipe, softpipe)
@@ -179,7 +179,7 @@ GL 4.3, GLSL 4.30:
   GL_ARB_program_interface_queryDONE (all drivers)
   GL_ARB_robust_buffer_access_behavior  DONE (radeonsi)
   GL_ARB_shader_image_size  DONE (i965, radeonsi, 
softpipe)
-  GL_ARB_shader_storage_buffer_object   DONE (i965, nvc0, 
softpipe)
+  GL_ARB_shader_storage_buffer_object   DONE (i965, nvc0, 
radeonsi, softpipe)
   GL_ARB_stencil_texturing  DONE (i965/gen8+, 
nv50, nvc0, r600, radeonsi, llvmpipe, softpipe)
   GL_ARB_texture_buffer_range   DONE (nv50, nvc0, 
i965, r600, radeonsi, llvmpipe)
   GL_ARB_texture_query_levels   DONE (all drivers that 
support GLSL 1.30)
@@ -230,10 +230,10 @@ GLES3.1, GLSL ES 3.1
   GL_ARB_explicit_uniform_location  DONE (all drivers that 
support GLSL)
   GL_ARB_framebuffer_no_attachments DONE (i965, nvc0, 
r600, radeonsi)
   GL_ARB_program_interface_queryDONE (all drivers)
-  GL_ARB_shader_atomic_counters DONE (i965, nvc0, 
softpipe)
+  GL_ARB_shader_atomic_counters DONE (i965, nvc0, 
radeonsi, softpipe)
   GL_ARB_shader_image_load_storeDONE (i965, softpipe, 
radeonsi)
   GL_ARB_shader_image_size  DONE (i965, softpipe, 
radeonsi)
-  GL_ARB_shader_storage_buffer_object   DONE (i965, nvc0, 
softpipe)
+  GL_ARB_shader_storage_buffer_object   DONE (i965, nvc0, 
radeonsi, softpipe)
   GL_ARB_shading_language_packing   DONE (all drivers)
   GL_ARB_separate_shader_objectsDONE (all drivers)
   GL_ARB_stencil_texturing  DONE (i965/gen8+, 
nv50, nvc0, r600, radeonsi, llvmpipe, softpipe)
diff --git a/docs/relnotes/11.3.0.html b/docs/relnotes/11.3.0.html
index f46616d..9860ab0 100644
--- a/docs/relnotes/11.3.0.html
+++ b/docs/relnotes/11.3.0.html
@@ -47,11 +47,11 @@ Note: some of the new features are only available with 
certain drivers.
 GL_ARB_framebuffer_no_attachments on nvc0, r600, radeonsi
 GL_ARB_internalformat_query2 on all drivers
 GL_ARB_robust_buffer_access_behavior on radeonsi
-GL_ARB_shader_atomic_counters on softpipe
-GL_ARB_shader_atomic_counter_ops on nvc0, softpipe
+GL_ARB_shader_atomic_counters on radeonsi, softpipe
+GL_ARB_shader_atomic_counter_ops on nvc0, radeonsi, softpipe
 GL_ARB_shader_image_load_store on radeonsi, softpipe
 GL_ARB_shader_image_size on radeonsi, softpipe
-GL_ARB_shader_storage_buffer_objects on softpipe
+GL_ARB_shader_storage_buffer_objects on radeonsi, softpipe
 GL_ATI_fragment_shader on all Gallium drivers
 GL_EXT_base_instance on all drivers that support GL_ARB_base_instance
 GL_OES_draw_buffers_indexed and GL_EXT_draw_buffers_indexed on all drivers 
that support GL_ARB_draw_buffers_blend

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Mesa (master): radeonsi: add shader buffer support to TGSI_OPCODE_ATOM*

2016-04-12 Thread Nicolai Hähnle

Module: Mesa
Branch: master
Commit: 68bc25c931ab76fc9794cb10f515e81b28e2703d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=68bc25c931ab76fc9794cb10f515e81b28e2703d

Author: Nicolai Hähnle 
Date:   Tue Mar 15 19:02:38 2016 -0500

radeonsi: add shader buffer support to TGSI_OPCODE_ATOM*

Reviewed-by: Marek Olšák 
Reviewed-by: Edward O'Callaghan 

---

 src/gallium/drivers/radeonsi/si_shader.c | 61 
 1 file changed, 46 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 2c7a6fa..f7e3c8c 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2776,6 +2776,24 @@ static void membar_emit(
emit_optimization_barrier(ctx);
 }
 
+static LLVMValueRef
+shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
+const struct tgsi_full_src_register *reg)
+{
+   LLVMValueRef ind_index;
+   LLVMValueRef rsrc_ptr;
+
+   if (!reg->Register.Indirect)
+   return ctx->shader_buffers[reg->Register.Index];
+
+   ind_index = get_bounded_indirect_index(ctx, >Indirect,
+  reg->Register.Index,
+  SI_NUM_SHADER_BUFFERS);
+
+   rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, 
SI_PARAM_SHADER_BUFFERS);
+   return build_indexed_load_const(ctx, rsrc_ptr, ind_index);
+}
+
 static bool tgsi_is_array_sampler(unsigned target)
 {
return target == TGSI_TEXTURE_1D_ARRAY ||
@@ -3123,18 +3141,12 @@ static void atomic_fetch_args(
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
const struct tgsi_full_instruction * inst = emit_data->inst;
-   unsigned target = inst->Memory.Texture;
LLVMValueRef data1, data2;
-   LLVMValueRef coords;
LLVMValueRef rsrc;
LLVMValueRef tmp;
 
emit_data->dst_type = bld_base->base.elem_type;
 
-   image_fetch_rsrc(bld_base, >Src[0], target != TGSI_TEXTURE_BUFFER,
-);
-   coords = image_fetch_coords(bld_base, inst, 1);
-
tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, 
"");
 
@@ -3150,15 +3162,34 @@ static void atomic_fetch_args(
emit_data->args[emit_data->arg_count++] = data2;
emit_data->args[emit_data->arg_count++] = data1;
 
-   if (target == TGSI_TEXTURE_BUFFER) {
-   rsrc = extract_rsrc_top_half(ctx, rsrc);
-   buffer_append_args(ctx, emit_data, rsrc, coords,
-  bld_base->uint_bld.zero, true);
+   if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
+   LLVMValueRef offset;
+
+   rsrc = shader_buffer_fetch_rsrc(ctx, >Src[0]);
+
+   tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
+   offset = LLVMBuildBitCast(builder, tmp, 
bld_base->uint_bld.elem_type, "");
+
+   buffer_append_args(ctx, emit_data, rsrc, 
bld_base->uint_bld.zero,
+  offset, true);
} else {
-   emit_data->args[emit_data->arg_count++] = coords;
-   emit_data->args[emit_data->arg_count++] = rsrc;
+   unsigned target = inst->Memory.Texture;
+   LLVMValueRef coords;
+
+   image_fetch_rsrc(bld_base, >Src[0],
+target != TGSI_TEXTURE_BUFFER, );
+   coords = image_fetch_coords(bld_base, inst, 1);
 
-   image_append_args(ctx, emit_data, target, true);
+   if (target == TGSI_TEXTURE_BUFFER) {
+   rsrc = extract_rsrc_top_half(ctx, rsrc);
+   buffer_append_args(ctx, emit_data, rsrc, coords,
+  bld_base->uint_bld.zero, true);
+   } else {
+   emit_data->args[emit_data->arg_count++] = coords;
+   emit_data->args[emit_data->arg_count++] = rsrc;
+
+   image_append_args(ctx, emit_data, target, true);
+   }
}
 }
 
@@ -3170,11 +3201,11 @@ static void atomic_emit(
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
const struct tgsi_full_instruction * inst = emit_data->inst;
-   unsigned target = inst->Memory.Texture;
char intrinsic_name[40];
LLVMValueRef tmp;
 
-   if (target == TGSI_TEXTURE_BUFFER) {
+   if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
+   inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
snprintf(intrinsic_name, sizeof(intrinsic_name),
 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);

Mesa (master): radeonsi: move resetting of constant buffers into a separate function

2016-04-12 Thread Nicolai Hähnle

Module: Mesa
Branch: master
Commit: 73c8b85b6456775ab19b08b4d1f335e4f3c88dd0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=73c8b85b6456775ab19b08b4d1f335e4f3c88dd0

Author: Nicolai Hähnle 
Date:   Wed Mar 16 17:42:57 2016 -0500

radeonsi: move resetting of constant buffers into a separate function

This will be re-used for shader buffers.

Reviewed-by: Marek Olšák 
Reviewed-by: Edward O'Callaghan 

---

 src/gallium/drivers/radeonsi/si_descriptors.c | 41 +--
 1 file changed, 26 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index b3792c2..9cdf5e0 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -983,6 +983,30 @@ void si_update_compressed_colortex_masks(struct si_context 
*sctx)
 
 /* BUFFER DISCARD/INVALIDATION */
 
+/** Reset descriptors of buffer resources after \p buf has been invalidated. */
+static void si_reset_buffer_resources(struct si_context *sctx,
+ struct si_buffer_resources *buffers,
+ struct pipe_resource *buf,
+ uint64_t old_va)
+{
+   uint64_t mask = buffers->desc.enabled_mask;
+
+   while (mask) {
+   unsigned i = u_bit_scan64();
+   if (buffers->buffers[i] == buf) {
+   si_desc_reset_buffer_offset(>b.b,
+   buffers->desc.list + i*4,
+   old_va, buf);
+   buffers->desc.list_dirty = true;
+
+   radeon_add_to_buffer_list(>b, >b.gfx,
+   (struct r600_resource *)buf,
+   buffers->shader_usage,
+   buffers->priority);
+   }
+   }
+}
+
 /* Reallocate a buffer a update all resource bindings where the buffer is
  * bound.
  *
@@ -1056,21 +1080,8 @@ static void si_invalidate_buffer(struct pipe_context 
*ctx, struct pipe_resource
 
/* Constant buffers. */
for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
-   struct si_buffer_resources *buffers = 
>const_buffers[shader];
-   uint64_t mask = buffers->desc.enabled_mask;
-
-   while (mask) {
-   unsigned i = u_bit_scan64();
-   if (buffers->buffers[i] == buf) {
-   si_desc_reset_buffer_offset(ctx, 
buffers->desc.list + i*4,
-   old_va, buf);
-   buffers->desc.list_dirty = true;
-
-   radeon_add_to_buffer_list(>b, 
>b.gfx,
- rbuffer, 
buffers->shader_usage,
- buffers->priority);
-   }
-   }
+   si_reset_buffer_resources(sctx, >const_buffers[shader],
+ buf, old_va);
}
 
/* Texture buffers - update virtual addresses in sampler view 
descriptors. */

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Mesa (master): radeonsi: add offset parameter to buffer_append_args

2016-04-12 Thread Nicolai Hähnle

Module: Mesa
Branch: master
Commit: c6f5d000db1963eac6fb89d18008e5375720af93
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c6f5d000db1963eac6fb89d18008e5375720af93

Author: Nicolai Hähnle 
Date:   Tue Mar 15 19:00:11 2016 -0500

radeonsi: add offset parameter to buffer_append_args

Reviewed-by: Marek Olšák 
Reviewed-by: Edward O'Callaghan 

---

 src/gallium/drivers/radeonsi/si_shader.c | 15 ++-
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 027cef3..2c7a6fa 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2947,13 +2947,15 @@ static LLVMValueRef extract_rsrc_top_half(
  * Append the resource and indexing arguments for buffer intrinsics.
  *
  * \param rsrc the v4i32 buffer resource
- * \param index index into the buffer
+ * \param index index into the buffer (stride-based)
+ * \param offset byte offset into the buffer
  */
 static void buffer_append_args(
struct si_shader_context *ctx,
struct lp_build_emit_data *emit_data,
LLVMValueRef rsrc,
LLVMValueRef index,
+   LLVMValueRef offset,
bool atomic)
 {
struct lp_build_tgsi_context *bld_base = >radeon_bld.soa.bld_base;
@@ -2963,7 +2965,7 @@ static void buffer_append_args(
 
emit_data->args[emit_data->arg_count++] = rsrc;
emit_data->args[emit_data->arg_count++] = index; /* vindex */
-   emit_data->args[emit_data->arg_count++] = bld_base->uint_bld.zero; /* 
voffset */
+   emit_data->args[emit_data->arg_count++] = offset; /* voffset */
if (!atomic) {
emit_data->args[emit_data->arg_count++] =
inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | 
TGSI_MEMORY_VOLATILE) ?
@@ -2990,7 +2992,8 @@ static void load_fetch_args(
 
if (target == TGSI_TEXTURE_BUFFER) {
rsrc = extract_rsrc_top_half(ctx, rsrc);
-   buffer_append_args(ctx, emit_data, rsrc, coords, false);
+   buffer_append_args(ctx, emit_data, rsrc, coords,
+  bld_base->uint_bld.zero, false);
} else {
emit_data->args[0] = coords;
emit_data->args[1] = rsrc;
@@ -3068,7 +3071,8 @@ static void store_fetch_args(
emit_data->arg_count = 1;
 
rsrc = extract_rsrc_top_half(ctx, rsrc);
-   buffer_append_args(ctx, emit_data, rsrc, coords, false);
+   buffer_append_args(ctx, emit_data, rsrc, coords,
+  bld_base->uint_bld.zero, false);
} else {
emit_data->args[0] = data;
emit_data->args[1] = coords;
@@ -3148,7 +3152,8 @@ static void atomic_fetch_args(
 
if (target == TGSI_TEXTURE_BUFFER) {
rsrc = extract_rsrc_top_half(ctx, rsrc);
-   buffer_append_args(ctx, emit_data, rsrc, coords, true);
+   buffer_append_args(ctx, emit_data, rsrc, coords,
+  bld_base->uint_bld.zero, true);
} else {
emit_data->args[emit_data->arg_count++] = coords;
emit_data->args[emit_data->arg_count++] = rsrc;

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Mesa (master): radeonsi: preload shader buffers in shaders

2016-04-12 Thread Nicolai Hähnle

Module: Mesa
Branch: master
Commit: e88018ffe5dd57e368d6c15946f014c5457bb74c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e88018ffe5dd57e368d6c15946f014c5457bb74c

Author: Nicolai Hähnle 
Date:   Tue Mar 15 18:34:52 2016 -0500

radeonsi: preload shader buffers in shaders

Reviewed-by: Marek Olšák 
Reviewed-by: Edward O'Callaghan 

---

 src/gallium/drivers/radeonsi/si_shader.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 8f9a621..9d74c2a 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -98,6 +98,7 @@ struct si_shader_context
LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
LLVMValueRef lds;
LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
+   LLVMValueRef shader_buffers[SI_NUM_SHADER_BUFFERS];
LLVMValueRef sampler_views[SI_NUM_SAMPLERS];
LLVMValueRef sampler_states[SI_NUM_SAMPLERS];
LLVMValueRef fmasks[SI_NUM_USER_SAMPLERS];
@@ -4710,6 +4711,21 @@ static void preload_constants(struct si_shader_context 
*ctx)
}
 }
 
+static void preload_shader_buffers(struct si_shader_context *ctx)
+{
+   struct gallivm_state *gallivm = >radeon_bld.gallivm;
+   LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, 
SI_PARAM_SHADER_BUFFERS);
+   int buf, maxbuf;
+
+   maxbuf = MIN2(ctx->shader->selector->info.file_max[TGSI_FILE_BUFFER],
+ SI_NUM_SHADER_BUFFERS - 1);
+   for (buf = 0; buf <= maxbuf; ++buf) {
+   ctx->shader_buffers[buf] =
+   build_indexed_load_const(
+   ctx, ptr, lp_build_const_int32(gallivm, buf));
+   }
+}
+
 static void preload_samplers(struct si_shader_context *ctx)
 {
struct lp_build_tgsi_context *bld_base = >radeon_bld.soa.bld_base;
@@ -5575,6 +5591,7 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
create_meta_data();
create_function();
preload_constants();
+   preload_shader_buffers();
preload_samplers();
preload_images();
preload_streamout_buffers();

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Mesa (master): radeonsi: implement set_shader_buffers

2016-04-12 Thread Nicolai Hähnle

Module: Mesa
Branch: master
Commit: c495c0ad37dc6a4505a726e3ac0e3d83adc46d30
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c495c0ad37dc6a4505a726e3ac0e3d83adc46d30

Author: Nicolai Hähnle 
Date:   Tue Mar 15 16:30:56 2016 -0500

radeonsi: implement set_shader_buffers

Reviewed-by: Marek Olšák 
Reviewed-by: Edward O'Callaghan 

---

 src/gallium/drivers/radeonsi/si_descriptors.c |  61 +-
 src/gallium/drivers/radeonsi/si_pipe.h|   1 +
 src/gallium/drivers/radeonsi/si_shader.c  |   5 +-
 src/gallium/drivers/radeonsi/si_shader.h  | 114 +-
 src/gallium/drivers/radeonsi/si_state.h   |   2 +
 5 files changed, 125 insertions(+), 58 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 9cdf5e0..b5557d8 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -746,6 +746,55 @@ static void si_set_constant_buffer(struct pipe_context 
*ctx, uint shader, uint s
buffers->desc.list_dirty = true;
 }
 
+/* SHADER BUFFERS */
+
+static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
+ unsigned start_slot, unsigned count,
+ struct pipe_shader_buffer *sbuffers)
+{
+   struct si_context *sctx = (struct si_context *)ctx;
+   struct si_buffer_resources *buffers = >shader_buffers[shader];
+   unsigned i;
+
+   assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
+
+   for (i = 0; i < count; ++i) {
+   struct pipe_shader_buffer *sbuffer = sbuffers ? [i] : 
NULL;
+   struct r600_resource *buf;
+   unsigned slot = start_slot + i;
+   uint32_t *desc = buffers->desc.list + slot * 4;
+   uint64_t va;
+
+   if (!sbuffer || !sbuffer->buffer) {
+   pipe_resource_reference(>buffers[slot], NULL);
+   memset(desc, 0, sizeof(uint32_t) * 4);
+   buffers->desc.enabled_mask &= ~(1llu << slot);
+   continue;
+   }
+
+   buf = (struct r600_resource *)sbuffer->buffer;
+   va = buf->gpu_address + sbuffer->buffer_offset;
+
+   desc[0] = va;
+   desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
+ S_008F04_STRIDE(0);
+   desc[2] = sbuffer->buffer_size;
+   desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
+ S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
+ S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
+ S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
+ S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+ S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+
+   pipe_resource_reference(>buffers[slot], >b.b);
+   radeon_add_to_buffer_list(>b, >b.gfx, buf,
+ buffers->shader_usage, buffers->priority);
+   buffers->desc.enabled_mask |= 1llu << slot;
+   }
+
+   buffers->desc.list_dirty = true;
+}
+
 /* RING BUFFERS */
 
 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
@@ -1078,10 +1127,12 @@ static void si_invalidate_buffer(struct pipe_context 
*ctx, struct pipe_resource
}
}
 
-   /* Constant buffers. */
+   /* Constant and shader buffers. */
for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
si_reset_buffer_resources(sctx, >const_buffers[shader],
  buf, old_va);
+   si_reset_buffer_resources(sctx, >shader_buffers[shader],
+ buf, old_va);
}
 
/* Texture buffers - update virtual addresses in sampler view 
descriptors. */
@@ -1261,6 +1312,7 @@ void si_emit_shader_userdata(struct si_context *sctx, 
struct r600_atom *atom)
si_emit_shader_pointer(sctx, >rw_buffers[i].desc, 
base, false);
 
si_emit_shader_pointer(sctx, >const_buffers[i].desc, 
base, false);
+   si_emit_shader_pointer(sctx, >shader_buffers[i].desc, 
base, false);
si_emit_shader_pointer(sctx, >samplers[i].views.desc, 
base, false);
si_emit_shader_pointer(sctx, >images[i].desc, base, 
false);
}
@@ -1280,6 +1332,9 @@ void si_init_all_descriptors(struct si_context *sctx)
si_init_buffer_resources(>rw_buffers[i],
 SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
 RADEON_USAGE_READWRITE, 
RADEON_PRIO_RINGS_STREAMOUT);
+   si_init_buffer_resources(>shader_buffers[i],
+

Mesa (master): radeonsi: enable shader buffer pipe caps

2016-04-12 Thread Nicolai Hähnle

Module: Mesa
Branch: master
Commit: bfd11c599600960f966d5d217b8dc20442108ef1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfd11c599600960f966d5d217b8dc20442108ef1

Author: Nicolai Hähnle 
Date:   Tue Mar 15 16:25:42 2016 -0500

radeonsi: enable shader buffer pipe caps

Reviewed-by: Marek Olšák 
Reviewed-by: Edward O'Callaghan 

---

 src/gallium/drivers/radeonsi/si_pipe.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 971359c..6b4b3d2 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -331,6 +331,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum 
pipe_cap param)
 
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
+   case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
return 4;
 
@@ -354,7 +355,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum 
pipe_cap param)
case PIPE_CAP_DRAW_PARAMETERS:
case PIPE_CAP_MULTI_DRAW_INDIRECT:
case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
-   case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_GENERATE_MIPMAP:
case PIPE_CAP_STRING_MARKER:
case PIPE_CAP_QUERY_BUFFER_OBJECT:
@@ -540,7 +540,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen, 
unsigned shader, enu
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
-   return 0;
+   return HAVE_LLVM >= 0x0309 ? SI_NUM_SHADER_BUFFERS : 0;
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
return HAVE_LLVM >= 0x0309 ? SI_NUM_IMAGES : 0;
}

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Mesa (master): radeonsi: add shader buffer support to TGSI_OPCODE_LOAD

2016-04-12 Thread Nicolai Hähnle

Module: Mesa
Branch: master
Commit: 745014c502bae7509828436eeade6b88c2e76834
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=745014c502bae7509828436eeade6b88c2e76834

Author: Nicolai Hähnle 
Date:   Tue Mar 15 19:11:38 2016 -0500

radeonsi: add shader buffer support to TGSI_OPCODE_LOAD

Reviewed-by: Marek Olšák 
Reviewed-by: Edward O'Callaghan 

---

 src/gallium/drivers/radeonsi/si_shader.c | 89 +---
 1 file changed, 70 insertions(+), 19 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index f7e3c8c..2b4c684 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2976,7 +2976,6 @@ static void buffer_append_args(
LLVMValueRef offset,
bool atomic)
 {
-   struct lp_build_tgsi_context *bld_base = >radeon_bld.soa.bld_base;
const struct tgsi_full_instruction *inst = emit_data->inst;
LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
@@ -3000,28 +2999,75 @@ static void load_fetch_args(
struct gallivm_state *gallivm = bld_base->base.gallivm;
const struct tgsi_full_instruction * inst = emit_data->inst;
unsigned target = inst->Memory.Texture;
-   LLVMValueRef coords;
LLVMValueRef rsrc;
 
emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
 
-   image_fetch_rsrc(bld_base, >Src[0], false, );
-   coords = image_fetch_coords(bld_base, inst, 1);
+   if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
+   LLVMBuilderRef builder = gallivm->builder;
+   LLVMValueRef offset;
+   LLVMValueRef tmp;
 
-   if (target == TGSI_TEXTURE_BUFFER) {
-   rsrc = extract_rsrc_top_half(ctx, rsrc);
-   buffer_append_args(ctx, emit_data, rsrc, coords,
-  bld_base->uint_bld.zero, false);
+   rsrc = shader_buffer_fetch_rsrc(ctx, >Src[0]);
+
+   tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
+   offset = LLVMBuildBitCast(builder, tmp, 
bld_base->uint_bld.elem_type, "");
+
+   buffer_append_args(ctx, emit_data, rsrc, 
bld_base->uint_bld.zero,
+  offset, false);
} else {
-   emit_data->args[0] = coords;
-   emit_data->args[1] = rsrc;
-   emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* 
dmask */
-   emit_data->arg_count = 3;
+   LLVMValueRef coords;
 
-   image_append_args(ctx, emit_data, target, false);
+   image_fetch_rsrc(bld_base, >Src[0], false, );
+   coords = image_fetch_coords(bld_base, inst, 1);
+
+   if (target == TGSI_TEXTURE_BUFFER) {
+   rsrc = extract_rsrc_top_half(ctx, rsrc);
+   buffer_append_args(ctx, emit_data, rsrc, coords,
+   bld_base->uint_bld.zero, false);
+   } else {
+   emit_data->args[0] = coords;
+   emit_data->args[1] = rsrc;
+   emit_data->args[2] = lp_build_const_int32(gallivm, 15); 
/* dmask */
+   emit_data->arg_count = 3;
+
+   image_append_args(ctx, emit_data, target, false);
+   }
}
 }
 
+static void load_emit_buffer(struct si_shader_context *ctx,
+struct lp_build_emit_data *emit_data)
+{
+   const struct tgsi_full_instruction *inst = emit_data->inst;
+   struct gallivm_state *gallivm = >radeon_bld.gallivm;
+   LLVMBuilderRef builder = gallivm->builder;
+   uint writemask = inst->Dst[0].Register.WriteMask;
+   uint count = util_last_bit(writemask);
+   const char *intrinsic_name;
+   LLVMTypeRef dst_type;
+
+   switch (count) {
+   case 1:
+   intrinsic_name = "llvm.amdgcn.buffer.load.f32";
+   dst_type = ctx->f32;
+   break;
+   case 2:
+   intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
+   dst_type = LLVMVectorType(ctx->f32, 2);
+   break;
+   default: // 3 & 4
+   intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
+   dst_type = ctx->v4f32;
+   count = 4;
+   }
+
+   emit_data->output[emit_data->chan] = lp_build_intrinsic(
+   builder, intrinsic_name, dst_type,
+   emit_data->args, emit_data->arg_count,
+   LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
+}
+
 static void load_emit(
const struct lp_build_tgsi_action *action,
struct lp_build_tgsi_context *bld_base,
@@ -3031,18 +3077,23 @@ static void load_emit(
struct

Mesa (master): radeonsi: adjust buffer_append_args to take a 128 bit resource

2016-04-12 Thread Nicolai Hähnle

Module: Mesa
Branch: master
Commit: c565466eeaea344e379af95967999e180d29a600
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c565466eeaea344e379af95967999e180d29a600

Author: Nicolai Hähnle 
Date:   Tue Mar 15 18:47:14 2016 -0500

radeonsi: adjust buffer_append_args to take a 128 bit resource

Move the buffer resource extraction code out into its own function.

Reviewed-by: Marek Olšák 
Reviewed-by: Edward O'Callaghan 

---

 src/gallium/drivers/radeonsi/si_shader.c | 30 +++---
 1 file changed, 23 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 9d74c2a..027cef3 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2925,9 +2925,28 @@ static void image_append_args(
 }
 
 /**
+ * Given a 256 bit resource, extract the top half (which stores the buffer
+ * resource in the case of textures and images).
+ */
+static LLVMValueRef extract_rsrc_top_half(
+   struct si_shader_context *ctx,
+   LLVMValueRef rsrc)
+{
+   struct gallivm_state *gallivm = >radeon_bld.gallivm;
+   struct lp_build_tgsi_context *bld_base = >radeon_bld.soa.bld_base;
+   LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
+
+   rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, "");
+   rsrc = LLVMBuildExtractElement(gallivm->builder, rsrc, 
bld_base->uint_bld.one, "");
+   rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, "");
+
+   return rsrc;
+}
+
+/**
  * Append the resource and indexing arguments for buffer intrinsics.
  *
- * \param rsrc the 256 bit resource
+ * \param rsrc the v4i32 buffer resource
  * \param index index into the buffer
  */
 static void buffer_append_args(
@@ -2937,17 +2956,11 @@ static void buffer_append_args(
LLVMValueRef index,
bool atomic)
 {
-   struct gallivm_state *gallivm = >radeon_bld.gallivm;
struct lp_build_tgsi_context *bld_base = >radeon_bld.soa.bld_base;
const struct tgsi_full_instruction *inst = emit_data->inst;
-   LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
 
-   rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, "");
-   rsrc = LLVMBuildExtractElement(gallivm->builder, rsrc, 
bld_base->uint_bld.one, "");
-   rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, "");
-
emit_data->args[emit_data->arg_count++] = rsrc;
emit_data->args[emit_data->arg_count++] = index; /* vindex */
emit_data->args[emit_data->arg_count++] = bld_base->uint_bld.zero; /* 
voffset */
@@ -2976,6 +2989,7 @@ static void load_fetch_args(
coords = image_fetch_coords(bld_base, inst, 1);
 
if (target == TGSI_TEXTURE_BUFFER) {
+   rsrc = extract_rsrc_top_half(ctx, rsrc);
buffer_append_args(ctx, emit_data, rsrc, coords, false);
} else {
emit_data->args[0] = coords;
@@ -3053,6 +3067,7 @@ static void store_fetch_args(
emit_data->args[0] = data;
emit_data->arg_count = 1;
 
+   rsrc = extract_rsrc_top_half(ctx, rsrc);
buffer_append_args(ctx, emit_data, rsrc, coords, false);
} else {
emit_data->args[0] = data;
@@ -3132,6 +3147,7 @@ static void atomic_fetch_args(
emit_data->args[emit_data->arg_count++] = data1;
 
if (target == TGSI_TEXTURE_BUFFER) {
+   rsrc = extract_rsrc_top_half(ctx, rsrc);
buffer_append_args(ctx, emit_data, rsrc, coords, true);
} else {
emit_data->args[emit_data->arg_count++] = coords;

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Mesa (master): radeonsi: add shader buffer support to TGSI_OPCODE_STORE

2016-04-12 Thread Nicolai Hähnle

Module: Mesa
Branch: master
Commit: 01109282ce47094f19495b9928845d4b47d9629f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=01109282ce47094f19495b9928845d4b47d9629f

Author: Nicolai Hähnle 
Date:   Wed Mar 16 17:03:02 2016 -0500

radeonsi: add shader buffer support to TGSI_OPCODE_STORE

Reviewed-by: Marek Olšák 
Reviewed-by: Edward O'Callaghan 

---

 src/gallium/drivers/radeonsi/si_shader.c | 129 ++-
 1 file changed, 111 insertions(+), 18 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 2b4c684..18f75da 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -3115,41 +3115,129 @@ static void store_fetch_args(
 {
struct si_shader_context *ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
+   LLVMBuilderRef builder = gallivm->builder;
const struct tgsi_full_instruction * inst = emit_data->inst;
-   struct tgsi_full_src_register image;
-   unsigned target = inst->Memory.Texture;
+   struct tgsi_full_src_register memory;
LLVMValueRef chans[4];
LLVMValueRef data;
-   LLVMValueRef coords;
LLVMValueRef rsrc;
unsigned chan;
 
emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
 
-   image = tgsi_full_src_register_from_dst(>Dst[0]);
-   coords = image_fetch_coords(bld_base, inst, 0);
-
for (chan = 0; chan < 4; ++chan) {
chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
}
data = lp_build_gather_values(gallivm, chans, 4);
 
-   if (target == TGSI_TEXTURE_BUFFER) {
-   image_fetch_rsrc(bld_base, , false, );
-   emit_data->args[0] = data;
-   emit_data->arg_count = 1;
+   emit_data->args[emit_data->arg_count++] = data;
+
+   memory = tgsi_full_src_register_from_dst(>Dst[0]);
 
-   rsrc = extract_rsrc_top_half(ctx, rsrc);
-   buffer_append_args(ctx, emit_data, rsrc, coords,
-  bld_base->uint_bld.zero, false);
+   if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
+   LLVMValueRef offset;
+   LLVMValueRef tmp;
+
+   rsrc = shader_buffer_fetch_rsrc(ctx, );
+
+   tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
+   offset = LLVMBuildBitCast(builder, tmp, 
bld_base->uint_bld.elem_type, "");
+
+   buffer_append_args(ctx, emit_data, rsrc, 
bld_base->uint_bld.zero,
+  offset, false);
} else {
+   unsigned target = inst->Memory.Texture;
+   LLVMValueRef coords;
+
+   coords = image_fetch_coords(bld_base, inst, 0);
+
+   if (target == TGSI_TEXTURE_BUFFER) {
+   image_fetch_rsrc(bld_base, , false, );
+
+   rsrc = extract_rsrc_top_half(ctx, rsrc);
+   buffer_append_args(ctx, emit_data, rsrc, coords,
+   bld_base->uint_bld.zero, false);
+   } else {
+   emit_data->args[1] = coords;
+   image_fetch_rsrc(bld_base, , true, 
_data->args[2]);
+   emit_data->args[3] = lp_build_const_int32(gallivm, 15); 
/* dmask */
+   emit_data->arg_count = 4;
+
+   image_append_args(ctx, emit_data, target, false);
+   }
+   }
+}
+
+static void store_emit_buffer(
+   struct si_shader_context *ctx,
+   struct lp_build_emit_data *emit_data)
+{
+   const struct tgsi_full_instruction *inst = emit_data->inst;
+   struct gallivm_state *gallivm = >radeon_bld.gallivm;
+   LLVMBuilderRef builder = gallivm->builder;
+   struct lp_build_context *uint_bld = 
>radeon_bld.soa.bld_base.uint_bld;
+   LLVMValueRef base_data = emit_data->args[0];
+   LLVMValueRef base_offset = emit_data->args[3];
+   unsigned writemask = inst->Dst[0].Register.WriteMask;
+
+   while (writemask) {
+   int start, count;
+   const char *intrinsic_name;
+   LLVMValueRef data;
+   LLVMValueRef offset;
+   LLVMValueRef tmp;
+
+   u_bit_scan_consecutive_range(, , );
+
+   /* Due to an LLVM limitation, split 3-element writes
+* into a 2-element and a 1-element write. */
+   if (count == 3) {
+   writemask |= 1 << (start + 2);
+   count = 2;
+   }
+
+   if (count == 4) {
+   data = base_data;
+   intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
+   } else if (count == 2) {
+   LLVMTypeRef

Mesa (master): glsl: Add a method to print error messages for illegal qualifiers.

2016-04-12 Thread Kenneth Graunke

Module: Mesa
Branch: master
Commit: 929e44099f83acee74d07eb3e33a3c0d22f8bc6b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=929e44099f83acee74d07eb3e33a3c0d22f8bc6b

Author: Kenneth Graunke 
Date:   Sun Apr 10 22:41:46 2016 -0700

glsl: Add a method to print error messages for illegal qualifiers.

Suggested by Timothy Arceri a while back on mesa-dev:
https://lists.freedesktop.org/archives/mesa-dev/2016-February/107735.html

Signed-off-by: Kenneth Graunke 
Reviewed-by: Timothy Arceri 
Acked-by: Matt Turner 

---

 src/compiler/glsl/ast.h|  5 +++
 src/compiler/glsl/ast_type.cpp | 85 ++
 2 files changed, 90 insertions(+)

diff --git a/src/compiler/glsl/ast.h b/src/compiler/glsl/ast.h
index 7436edc..92aa39e 100644
--- a/src/compiler/glsl/ast.h
+++ b/src/compiler/glsl/ast.h
@@ -736,6 +736,11 @@ struct ast_type_qualifier {
const ast_type_qualifier ,
ast_node* , bool create_node);
 
+   bool validate_flags(YYLTYPE *loc,
+   _mesa_glsl_parse_state *state,
+   const char *message,
+   const ast_type_qualifier _flags);
+
ast_subroutine_list *subroutine_list;
 };
 
diff --git a/src/compiler/glsl/ast_type.cpp b/src/compiler/glsl/ast_type.cpp
index c3d38cb..7a0014b 100644
--- a/src/compiler/glsl/ast_type.cpp
+++ b/src/compiler/glsl/ast_type.cpp
@@ -581,6 +581,91 @@ ast_type_qualifier::merge_in_qualifier(YYLTYPE *loc,
return true;
 }
 
+/**
+ * Check if the current type qualifier has any illegal flags.
+ *
+ * If so, print an error message, followed by a list of illegal flags.
+ *
+ * \param messageThe error message to print.
+ * \param allowed_flags  A list of valid flags.
+ */
+bool
+ast_type_qualifier::validate_flags(YYLTYPE *loc,
+   _mesa_glsl_parse_state *state,
+   const char *message,
+   const ast_type_qualifier _flags)
+{
+   ast_type_qualifier bad;
+   bad.flags.i = this->flags.i & ~allowed_flags.flags.i;
+   if (bad.flags.i == 0)
+  return true;
+
+   _mesa_glsl_error(loc, state,
+"%s:"
+"%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
+"%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
+"%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+message,
+bad.flags.q.invariant ? " invariant" : "",
+bad.flags.q.precise ? " precise" : "",
+bad.flags.q.constant ? " constant" : "",
+bad.flags.q.attribute ? " attribute" : "",
+bad.flags.q.varying ? " varying" : "",
+bad.flags.q.in ? " in" : "",
+bad.flags.q.out ? " out" : "",
+bad.flags.q.centroid ? " centroid" : "",
+bad.flags.q.sample ? " sample" : "",
+bad.flags.q.patch ? " patch" : "",
+bad.flags.q.uniform ? " uniform" : "",
+bad.flags.q.buffer ? " buffer" : "",
+bad.flags.q.shared_storage ? " shared_storage" : "",
+bad.flags.q.smooth ? " smooth" : "",
+bad.flags.q.flat ? " flat" : "",
+bad.flags.q.noperspective ? " noperspective" : "",
+bad.flags.q.origin_upper_left ? " origin_upper_left" : "",
+bad.flags.q.pixel_center_integer ? " pixel_center_integer" 
: "",
+bad.flags.q.explicit_align ? " align" : "",
+bad.flags.q.explicit_location ? " location" : "",
+bad.flags.q.explicit_index ? " index" : "",
+bad.flags.q.explicit_binding ? " binding" : "",
+bad.flags.q.explicit_offset ? " offset" : "",
+bad.flags.q.depth_any ? " depth_any" : "",
+bad.flags.q.depth_greater ? " depth_greater" : "",
+bad.flags.q.depth_less ? " depth_less" : "",
+bad.flags.q.depth_unchanged ? " depth_unchanged" : "",
+bad.flags.q.std140 ? " std140" : "",
+bad.flags.q.std430 ? " std430" : "",
+bad.flags.q.shared ? " shared" : "",
+bad.flags.q.packed ? " packed" : "",
+bad.flags.q.column_major ? " column_major" : "",
+bad.flags.q.row_major ? " row_major" : "",
+bad.flags.q.prim_type ? " prim_type" : "",
+bad.flags.q.max_vertices ? " max_vertices" : "",
+bad.flags.q.local_size ? " local_size" : "",
+bad.flags.q.early_fragment_tests ? " early_fragment_tests" 
: "",
+bad.flags.q.explicit_image_format ? "

Mesa (master): glsl: Reject illegal qualifiers on atomic counter uniforms.

2016-04-12 Thread Kenneth Graunke

Module: Mesa
Branch: master
Commit: e303e88a9c86ce9b08c34919982729bf234fe995
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e303e88a9c86ce9b08c34919982729bf234fe995

Author: Kenneth Graunke 
Date:   Sun Apr 10 22:50:05 2016 -0700

glsl: Reject illegal qualifiers on atomic counter uniforms.

This fixes

dEQP-GLES31.functional.uniform_location.negative.atomic_fragment
dEQP-GLES31.functional.uniform_location.negative.atomic_vertex

Both of which have lines like

layout(location = 3, binding = 0, offset = 0) uniform atomic_uint uni0;

The ARB_explicit_uniform_location spec makes a very tangential mention
regarding atomic counters, but location isn't something that makes sense
with them.

Signed-off-by: Ilia Mirkin 
Signed-off-by: Kenneth Graunke 
Reviewed-by: Timothy Arceri 

---

 src/compiler/glsl/ast_to_hir.cpp | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index 7c9be81..82eb22a 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -4300,6 +4300,17 @@ ast_declarator_list::hir(exec_list *instructions,
 state->atomic_counter_offsets[qual_binding] = qual_offset;
  }
   }
+
+  ast_type_qualifier allowed_atomic_qual_mask;
+  allowed_atomic_qual_mask.flags.i = 0;
+  allowed_atomic_qual_mask.flags.q.explicit_binding = 1;
+  allowed_atomic_qual_mask.flags.q.explicit_offset = 1;
+  allowed_atomic_qual_mask.flags.q.uniform = 1;
+
+  type->qualifier.validate_flags(, state,
+ "invalid layout qualifier for "
+ "atomic_uint",
+ allowed_atomic_qual_mask);
}
 
if (this->declarations.is_empty()) {

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Mesa (master): dri/i965: fix incorrect rgbFormat in intelCreateBuffer().

2016-04-12 Thread Kenneth Graunke

Module: Mesa
Branch: master
Commit: 35ade36c88e5aaa0b18c3cc911d9a4de3a60a80b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=35ade36c88e5aaa0b18c3cc911d9a4de3a60a80b

Author: Haixia Shi 
Date:   Thu Apr  7 11:05:09 2016 -0700

dri/i965: fix incorrect rgbFormat in intelCreateBuffer().

It is incorrect to assume that pixel format is always in BGR byte order.
We need to check bitmask parameters (such as |redMask|) to determine whether
the RGB or BGR byte order is requested.

v2: reformat code to stay within 80 character per line limit.
v3: just fix the byte order problem first and investigate SRGB later.
v4: rebased on top of the GLES3 sRGB workaround fix.
v5: rebased on top of the GLES3 sRGB workaround fix v2.

Signed-off-by: Haixia Shi 
Reviewed-by: Stéphane Marchesin 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/intel_screen.c | 20 
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 03e6852..dbec82f 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1000,14 +1000,18 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
   fb->Visual.samples = num_samples;
}
 
-   if (mesaVis->redBits == 5)
-  rgbFormat = MESA_FORMAT_B5G6R5_UNORM;
-   else if (mesaVis->sRGBCapable)
-  rgbFormat = MESA_FORMAT_B8G8R8A8_SRGB;
-   else if (mesaVis->alphaBits == 0)
-  rgbFormat = MESA_FORMAT_B8G8R8X8_UNORM;
-   else {
-  rgbFormat = MESA_FORMAT_B8G8R8A8_SRGB;
+   if (mesaVis->redBits == 5) {
+  rgbFormat = mesaVis->redMask == 0x1f ? MESA_FORMAT_R5G6B5_UNORM
+   : MESA_FORMAT_B5G6R5_UNORM;
+   } else if (mesaVis->sRGBCapable) {
+  rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
+   : MESA_FORMAT_B8G8R8A8_SRGB;
+   } else if (mesaVis->alphaBits == 0) {
+  rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
+   : MESA_FORMAT_B8G8R8X8_UNORM;
+   } else {
+  rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
+   : MESA_FORMAT_B8G8R8A8_SRGB;
   fb->Visual.sRGBCapable = true;
}
 

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Mesa (master): xlib: fix memory leak on Display close

2016-04-12 Thread Brian Paul

Module: Mesa
Branch: master
Commit: 7f0854724827bd34b9e64ab0c9cabc328e404c62
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f0854724827bd34b9e64ab0c9cabc328e404c62

Author: John Sheu 
Date:   Tue Apr 12 12:53:00 2016 -0600

xlib: fix memory leak on Display close

The XMesaVisual instances freed in the visuals table on display close
are being freed with a free() call, instead of XMesaDestroyVisual(),
causing a memory leak.

Signed-off-by: John Sheu 
Reviewed-by: Brian Paul 

---

 src/mesa/drivers/x11/fakeglx.c | 2 +-
 src/mesa/drivers/x11/xm_api.c  | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/x11/fakeglx.c b/src/mesa/drivers/x11/fakeglx.c
index 80b7176..2f4d966 100644
--- a/src/mesa/drivers/x11/fakeglx.c
+++ b/src/mesa/drivers/x11/fakeglx.c
@@ -794,7 +794,7 @@ destroy_visuals_on_display(Display *dpy)
   if (VisualTable[i]->display == dpy) {
  /* remove this visual */
  int j;
- free(VisualTable[i]);
+ XMesaDestroyVisual(VisualTable[i]);
  for (j = i; j < NumVisuals - 1; j++)
 VisualTable[j] = VisualTable[j + 1];
  NumVisuals--;
diff --git a/src/mesa/drivers/x11/xm_api.c b/src/mesa/drivers/x11/xm_api.c
index 65e7ca8..82c4d18 100644
--- a/src/mesa/drivers/x11/xm_api.c
+++ b/src/mesa/drivers/x11/xm_api.c
@@ -856,6 +856,7 @@ XMesaVisual XMesaCreateVisual( XMesaDisplay *display,
 accum_red_size, accum_green_size,
 accum_blue_size, accum_alpha_size,
 0)) {
+  free(v->visinfo);
   free(v);
   return NULL;
}

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Mesa (master): st/mesa: Replace GLvoid with void

2016-04-12 Thread Brian Paul

Module: Mesa
Branch: master
Commit: d04bb14d04d2f2f03cdaa3d78121d338a81de2e4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d04bb14d04d2f2f03cdaa3d78121d338a81de2e4

Author: Jakob Sinclair 
Date:   Tue Apr 12 20:48:18 2016 +0200

st/mesa: Replace GLvoid with void

GLvoid was used before in OpenGL but it has changed to just using void.
All GLvoids in mesa's state tracker has been changed to void in this patch.

Tested this with piglit and no problems were found. No compiler warnings.

Signed-off-by: Jakob Sinclair 
Reviewed-by: Brian Paul 

---

 src/mesa/state_tracker/st_cb_bufferobjects.c |  8 
 src/mesa/state_tracker/st_cb_drawpixels.c|  8 
 src/mesa/state_tracker/st_cb_readpixels.c|  4 ++--
 src/mesa/state_tracker/st_cb_texture.c   | 20 ++--
 src/mesa/state_tracker/st_vdpau.c| 12 ++--
 5 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/src/mesa/state_tracker/st_cb_bufferobjects.c 
b/src/mesa/state_tracker/st_cb_bufferobjects.c
index 202b4ee..8bbc2f0 100644
--- a/src/mesa/state_tracker/st_cb_bufferobjects.c
+++ b/src/mesa/state_tracker/st_cb_bufferobjects.c
@@ -98,7 +98,7 @@ static void
 st_bufferobj_subdata(struct gl_context *ctx,
 GLintptrARB offset,
 GLsizeiptrARB size,
-const GLvoid * data, struct gl_buffer_object *obj)
+const void * data, struct gl_buffer_object *obj)
 {
struct st_buffer_object *st_obj = st_buffer_object(obj);
 
@@ -142,7 +142,7 @@ static void
 st_bufferobj_get_subdata(struct gl_context *ctx,
  GLintptrARB offset,
  GLsizeiptrARB size,
- GLvoid * data, struct gl_buffer_object *obj)
+ void * data, struct gl_buffer_object *obj)
 {
struct st_buffer_object *st_obj = st_buffer_object(obj);
 
@@ -175,7 +175,7 @@ static GLboolean
 st_bufferobj_data(struct gl_context *ctx,
  GLenum target,
  GLsizeiptrARB size,
- const GLvoid * data,
+ const void * data,
  GLenum usage,
   GLbitfield storageFlags,
  struct gl_buffer_object *obj)
@@ -513,7 +513,7 @@ st_copy_buffer_subdata(struct gl_context *ctx,
 static void
 st_clear_buffer_subdata(struct gl_context *ctx,
 GLintptr offset, GLsizeiptr size,
-const GLvoid *clearValue,
+const void *clearValue,
 GLsizeiptr clearValueSize,
 struct gl_buffer_object *bufObj)
 {
diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c 
b/src/mesa/state_tracker/st_cb_drawpixels.c
index 3c7bc0c..c3e05bb 100644
--- a/src/mesa/state_tracker/st_cb_drawpixels.c
+++ b/src/mesa/state_tracker/st_cb_drawpixels.c
@@ -379,7 +379,7 @@ static struct pipe_resource *
 make_texture(struct st_context *st,
 GLsizei width, GLsizei height, GLenum format, GLenum type,
 const struct gl_pixelstore_attrib *unpack,
-const GLvoid *pixels)
+const void *pixels)
 {
struct gl_context *ctx = st->ctx;
struct pipe_context *pipe = st->pipe;
@@ -758,7 +758,7 @@ static void
 draw_stencil_pixels(struct gl_context *ctx, GLint x, GLint y,
 GLsizei width, GLsizei height, GLenum format, GLenum type,
 const struct gl_pixelstore_attrib *unpack,
-const GLvoid *pixels)
+const void *pixels)
 {
struct st_context *st = st_context(ctx);
struct pipe_context *pipe = st->pipe;
@@ -812,7 +812,7 @@ draw_stencil_pixels(struct gl_context *ctx, GLint x, GLint 
y,
   for (row = 0; row < height; row++) {
  GLfloat *zValuesFloat = (GLfloat*)zValues;
  GLenum destType = GL_UNSIGNED_BYTE;
- const GLvoid *source = _mesa_image_address2d(, pixels,
+ const void *source = _mesa_image_address2d(, pixels,
   width, height,
   format, type,
   row, 0);
@@ -1055,7 +1055,7 @@ static void
 st_DrawPixels(struct gl_context *ctx, GLint x, GLint y,
   GLsizei width, GLsizei height,
   GLenum format, GLenum type,
-  const struct gl_pixelstore_attrib *unpack, const GLvoid *pixels)
+  const struct gl_pixelstore_attrib *unpack, const void *pixels)
 {
void *driver_vp, *driver_fp;
struct st_context *st = st_context(ctx);
diff --git a/src/mesa/state_tracker/st_cb_readpixels.c 
b/src/mesa/state_tracker/st_cb_readpixels.c
index 5153c4b..393b881 100644
--- a/src/mesa/state_tracker/st_cb_readpixels.c
+++ b/src/mesa/state_tracker/st_cb_readpixels.c
@@ -85,7 +85,7 @@ st_ReadPixels(struct

Mesa (master): gallium: Add capability for ARB_robust_buffer_access_behavior.

2016-04-12 Thread Bas Nieuwenhuizen

Module: Mesa
Branch: master
Commit: 70dcd841f7d94a7b44b294d5264324fc5905aae8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=70dcd841f7d94a7b44b294d5264324fc5905aae8

Author: Bas Nieuwenhuizen 
Date:   Tue Apr 12 15:00:31 2016 +0200

gallium: Add capability for ARB_robust_buffer_access_behavior.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 
Reviewed-by: Roland Scheidegger 

---

 src/gallium/docs/source/screen.rst   | 5 +
 src/gallium/drivers/freedreno/freedreno_screen.c | 1 +
 src/gallium/drivers/i915/i915_screen.c   | 1 +
 src/gallium/drivers/ilo/ilo_screen.c | 1 +
 src/gallium/drivers/llvmpipe/lp_screen.c | 1 +
 src/gallium/drivers/nouveau/nv30/nv30_screen.c   | 1 +
 src/gallium/drivers/nouveau/nv50/nv50_screen.c   | 1 +
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c   | 1 +
 src/gallium/drivers/r300/r300_screen.c   | 1 +
 src/gallium/drivers/r600/r600_pipe.c | 1 +
 src/gallium/drivers/radeonsi/si_pipe.c   | 1 +
 src/gallium/drivers/softpipe/sp_screen.c | 1 +
 src/gallium/drivers/svga/svga_screen.c   | 1 +
 src/gallium/drivers/swr/swr_screen.cpp   | 1 +
 src/gallium/drivers/vc4/vc4_screen.c | 1 +
 src/gallium/drivers/virgl/virgl_screen.c | 1 +
 src/gallium/include/pipe/p_defines.h | 1 +
 src/mesa/state_tracker/st_extensions.c   | 1 +
 18 files changed, 22 insertions(+)

diff --git a/src/gallium/docs/source/screen.rst 
b/src/gallium/docs/source/screen.rst
index 824f580..9451075 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -331,6 +331,11 @@ The integer capabilities:
   primitive on a layer is obtained from ``PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS``
   even though it can be larger than the number of layers supported by either
   rendering or textures.
+* ``PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR``: Implementation uses bounds
+  checking on resource accesses by shader if the context is created with
+  PIPE_CONTEXT_ROBUST_BUFFER_ACCESS. See the ARB_robust_buffer_access_behavior
+  extension for information on the required behavior for out of bounds accesses
+  and accesses to unbound resources.
 
 
 .. _pipe_capf:
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c 
b/src/gallium/drivers/freedreno/freedreno_screen.c
index 707be17..37a72f2 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -256,6 +256,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
case PIPE_CAP_GENERATE_MIPMAP:
case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
+   case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
return 0;
 
case PIPE_CAP_MAX_VIEWPORTS:
diff --git a/src/gallium/drivers/i915/i915_screen.c 
b/src/gallium/drivers/i915/i915_screen.c
index 68e32e5..9b6a660 100644
--- a/src/gallium/drivers/i915/i915_screen.c
+++ b/src/gallium/drivers/i915/i915_screen.c
@@ -270,6 +270,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap 
cap)
case PIPE_CAP_PCI_DEVICE:
case PIPE_CAP_PCI_FUNCTION:
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
+   case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
   return 0;
 
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
diff --git a/src/gallium/drivers/ilo/ilo_screen.c 
b/src/gallium/drivers/ilo/ilo_screen.c
index 142d6f1..538f817 100644
--- a/src/gallium/drivers/ilo/ilo_screen.c
+++ b/src/gallium/drivers/ilo/ilo_screen.c
@@ -499,6 +499,7 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
case PIPE_CAP_PCI_DEVICE:
case PIPE_CAP_PCI_FUNCTION:
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
+   case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
   return 0;
 
case PIPE_CAP_VENDOR_ID:
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c 
b/src/gallium/drivers/llvmpipe/lp_screen.c
index 6a5f906..cb681ba 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -320,6 +320,7 @@ llvmpipe_get_param(struct pipe_screen *screen, enum 
pipe_cap param)
case PIPE_CAP_PCI_DEVICE:
case PIPE_CAP_PCI_FUNCTION:
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
+   case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
   return 0;
}
/* should only get here on unhandled cases */
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c 
b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
index ece8af7..400e9f5 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
@@ -193,6 +193,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
case PIPE_CAP_PCI_DEVICE:
case PIPE_CAP_PCI_FUNCTION:
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
+   case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:

Mesa (master): radeonsi: Mark ARB_robust_buffer_access_behavior as supported.

2016-04-12 Thread Bas Nieuwenhuizen

Module: Mesa
Branch: master
Commit: 126da23d70dccd9eb5ebe7bf26cb113193f882a4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=126da23d70dccd9eb5ebe7bf26cb113193f882a4

Author: Bas Nieuwenhuizen 
Date:   Sun Apr  3 21:49:44 2016 +0200

radeonsi: Mark ARB_robust_buffer_access_behavior as supported.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 docs/GL3.txt   | 2 +-
 docs/relnotes/11.3.0.html  | 1 +
 src/gallium/drivers/radeonsi/si_pipe.c | 2 +-
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index 066889a..423cafa 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -177,7 +177,7 @@ GL 4.3, GLSL 4.30:
   GL_ARB_invalidate_subdata DONE (all drivers)
   GL_ARB_multi_draw_indirectDONE (i965, nvc0, 
r600, radeonsi, llvmpipe, softpipe)
   GL_ARB_program_interface_queryDONE (all drivers)
-  GL_ARB_robust_buffer_access_behavior  not started
+  GL_ARB_robust_buffer_access_behavior  DONE (radeonsi)
   GL_ARB_shader_image_size  DONE (i965, radeonsi, 
softpipe)
   GL_ARB_shader_storage_buffer_object   DONE (i965, nvc0, 
softpipe)
   GL_ARB_stencil_texturing  DONE (i965/gen8+, 
nv50, nvc0, r600, radeonsi, llvmpipe, softpipe)
diff --git a/docs/relnotes/11.3.0.html b/docs/relnotes/11.3.0.html
index f1d958d..f46616d 100644
--- a/docs/relnotes/11.3.0.html
+++ b/docs/relnotes/11.3.0.html
@@ -46,6 +46,7 @@ Note: some of the new features are only available with 
certain drivers.
 
 GL_ARB_framebuffer_no_attachments on nvc0, r600, radeonsi
 GL_ARB_internalformat_query2 on all drivers
+GL_ARB_robust_buffer_access_behavior on radeonsi
 GL_ARB_shader_atomic_counters on softpipe
 GL_ARB_shader_atomic_counter_ops on nvc0, softpipe
 GL_ARB_shader_image_load_store on radeonsi, softpipe
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 9cfb11c..971359c 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -308,6 +308,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum 
pipe_cap param)
case PIPE_CAP_QUERY_MEMORY_INFO:
case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
+   case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
return 1;
 
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
@@ -357,7 +358,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum 
pipe_cap param)
case PIPE_CAP_GENERATE_MIPMAP:
case PIPE_CAP_STRING_MARKER:
case PIPE_CAP_QUERY_BUFFER_OBJECT:
-   case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
return 0;
 
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:

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Mesa (master): mesa: Expose the ARB_robust_buffer_access_behavior extension.

2016-04-12 Thread Bas Nieuwenhuizen

Module: Mesa
Branch: master
Commit: 285dc05055f2f98137188692d4c924605e5a942d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=285dc05055f2f98137188692d4c924605e5a942d

Author: Bas Nieuwenhuizen 
Date:   Tue Apr 12 14:57:07 2016 +0200

mesa: Expose the ARB_robust_buffer_access_behavior extension.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 src/mesa/main/extensions_table.h | 1 +
 src/mesa/main/mtypes.h   | 1 +
 src/mesa/main/version.c  | 2 +-
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index ddc25d8..78899ec 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -91,6 +91,7 @@ EXT(ARB_point_sprite, ARB_point_sprite
 EXT(ARB_program_interface_query , dummy_true   
  , GLL, GLC,  x ,  x , 2012)
 EXT(ARB_provoking_vertex, EXT_provoking_vertex 
  , GLL, GLC,  x ,  x , 2009)
 EXT(ARB_query_buffer_object , ARB_query_buffer_object  
  , GLL, GLC,  x ,  x , 2013)
+EXT(ARB_robust_buffer_access_behavior   , 
ARB_robust_buffer_access_behavior  , GLL, GLC,  x ,  x , 2012)
 EXT(ARB_robustness  , dummy_true   
  , GLL, GLC,  x ,  x , 2010)
 EXT(ARB_sample_shading  , ARB_sample_shading   
  , GLL, GLC,  x ,  x , 2009)
 EXT(ARB_sampler_objects , dummy_true   
  , GLL, GLC,  x ,  x , 2009)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 36c6e20..e4a3036 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -3766,6 +3766,7 @@ struct gl_extensions
GLboolean ARB_pipeline_statistics_query;
GLboolean ARB_point_sprite;
GLboolean ARB_query_buffer_object;
+   GLboolean ARB_robust_buffer_access_behavior;
GLboolean ARB_sample_shading;
GLboolean ARB_seamless_cube_map;
GLboolean ARB_shader_atomic_counter_ops;
diff --git a/src/mesa/main/version.c b/src/mesa/main/version.c
index 2af3653..b9c1bcb 100644
--- a/src/mesa/main/version.c
+++ b/src/mesa/main/version.c
@@ -361,7 +361,7 @@ compute_version(const struct gl_extensions *extensions,
  extensions->ARB_fragment_layer_viewport &&
  extensions->ARB_framebuffer_no_attachments &&
  extensions->ARB_internalformat_query2 &&
- /* extensions->ARB_robust_buffer_access_behavior */ 0 
&&
+ extensions->ARB_robust_buffer_access_behavior &&
  extensions->ARB_shader_image_size &&
  extensions->ARB_shader_storage_buffer_object &&
  extensions->ARB_stencil_texturing &&

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Mesa (master): main: rework the compatibility check of visuals in glXMakeCurrent

2016-04-12 Thread Marek Olšák

Module: Mesa
Branch: master
Commit: aad8707b288b03b26c1afde8b6280674e327115d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aad8707b288b03b26c1afde8b6280674e327115d

Author: Miklós Máté 
Date:   Thu Mar 24 01:12:59 2016 +0100

main: rework the compatibility check of visuals in glXMakeCurrent

Now it follows the compatibility criteria listed in section 2.1 of
the GLX 1.4 specification.
This is needed for post-process effects in SW:KotOR.

Signed-off-by: Miklós Máté 
Signed-off-by: Marek Olšák 

---

 src/mesa/main/context.c | 42 --
 1 file changed, 12 insertions(+), 30 deletions(-)

diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index dbba136..6af02d1 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -1525,10 +1525,6 @@ _mesa_copy_context( const struct gl_context *src, struct 
gl_context *dst,
  * Check if the given context can render into the given framebuffer
  * by checking visual attributes.
  *
- * Most of these tests could go away because Mesa is now pretty flexible
- * in terms of mixing rendering contexts with framebuffers.  As long
- * as RGB vs. CI mode agree, we're probably good.
- *
  * \return GL_TRUE if compatible, GL_FALSE otherwise.
  */
 static GLboolean 
@@ -1541,32 +1537,18 @@ check_compatible(const struct gl_context *ctx,
if (buffer == _mesa_get_incomplete_framebuffer())
   return GL_TRUE;
 
-#if 0
-   /* disabling this fixes the fgl_glxgears pbuffer demo */
-   if (ctxvis->doubleBufferMode && !bufvis->doubleBufferMode)
-  return GL_FALSE;
-#endif
-   if (ctxvis->stereoMode && !bufvis->stereoMode)
-  return GL_FALSE;
-   if (ctxvis->haveAccumBuffer && !bufvis->haveAccumBuffer)
-  return GL_FALSE;
-   if (ctxvis->haveDepthBuffer && !bufvis->haveDepthBuffer)
-  return GL_FALSE;
-   if (ctxvis->haveStencilBuffer && !bufvis->haveStencilBuffer)
-  return GL_FALSE;
-   if (ctxvis->redMask && ctxvis->redMask != bufvis->redMask)
-  return GL_FALSE;
-   if (ctxvis->greenMask && ctxvis->greenMask != bufvis->greenMask)
-  return GL_FALSE;
-   if (ctxvis->blueMask && ctxvis->blueMask != bufvis->blueMask)
-  return GL_FALSE;
-#if 0
-   /* disabled (see bug 11161) */
-   if (ctxvis->depthBits && ctxvis->depthBits != bufvis->depthBits)
-  return GL_FALSE;
-#endif
-   if (ctxvis->stencilBits && ctxvis->stencilBits != bufvis->stencilBits)
-  return GL_FALSE;
+#define check_component(foo)   \
+   if (ctxvis->foo && bufvis->foo &&   \
+   ctxvis->foo != bufvis->foo) \
+  return GL_FALSE
+
+   check_component(redMask);
+   check_component(greenMask);
+   check_component(blueMask);
+   check_component(depthBits);
+   check_component(stencilBits);
+
+#undef check_component
 
return GL_TRUE;
 }

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Mesa (master): swr: [rasterizer core] Affinitize thread scratch space to numa node of worker

2016-04-12 Thread Tim Rowley

Module: Mesa
Branch: master
Commit: c25244f2f7f61ebb368a9651aef4de93bd8306ac
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c25244f2f7f61ebb368a9651aef4de93bd8306ac

Author: Tim Rowley 
Date:   Thu Mar 24 16:20:02 2016 -0600

swr: [rasterizer core] Affinitize thread scratch space to numa node of worker

Acked-by: Brian Paul 

---

 src/gallium/drivers/swr/rasterizer/core/api.cpp | 16 ++--
 src/gallium/drivers/swr/rasterizer/core/arena.h |  2 +-
 src/gallium/drivers/swr/rasterizer/core/backend.cpp |  2 +-
 3 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/core/api.cpp 
b/src/gallium/drivers/swr/rasterizer/core/api.cpp
index f0f7956..442cdd4 100644
--- a/src/gallium/drivers/swr/rasterizer/core/api.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/api.cpp
@@ -93,8 +93,16 @@ HANDLE SwrCreateContext(
 ///@note We could lazily allocate this but its rather small amount of 
memory.
 for (uint32_t i = 0; i < pContext->NumWorkerThreads; ++i)
 {
-///@todo Use numa API for allocations using numa information from 
thread data (if exists).
-pContext->pScratch[i] = (uint8_t*)_aligned_malloc((32 * 1024), 
KNOB_SIMD_WIDTH * 4);
+#if defined(_WIN32)
+uint32_t numaNode = pContext->threadPool.pThreadData ?
+pContext->threadPool.pThreadData[i].numaId : 0;
+pContext->pScratch[i] = (uint8_t*)VirtualAllocExNuma(
+GetCurrentProcess(), nullptr, 32 * sizeof(KILOBYTE),
+MEM_RESERVE | MEM_COMMIT, PAGE_READWRITE,
+numaNode);
+#else
+pContext->pScratch[i] = (uint8_t*)_aligned_malloc(32 * 
sizeof(KILOBYTE), KNOB_SIMD_WIDTH * 4);
+#endif
 }
 
 // State setup AFTER context is fully initialized
@@ -138,7 +146,11 @@ void SwrDestroyContext(HANDLE hContext)
 // Free scratch space.
 for (uint32_t i = 0; i < pContext->NumWorkerThreads; ++i)
 {
+#if defined(_WIN32)
+VirtualFree(pContext->pScratch[i], 0, MEM_RELEASE);
+#else
 _aligned_free(pContext->pScratch[i]);
+#endif
 }
 
 delete(pContext->pHotTileMgr);
diff --git a/src/gallium/drivers/swr/rasterizer/core/arena.h 
b/src/gallium/drivers/swr/rasterizer/core/arena.h
index 67d81a4..0241f5b 100644
--- a/src/gallium/drivers/swr/rasterizer/core/arena.h
+++ b/src/gallium/drivers/swr/rasterizer/core/arena.h
@@ -209,7 +209,7 @@ struct CachingAllocatorT : DefaultAllocator
 };
 typedef CachingAllocatorT<> CachingAllocator;
 
-template
+template
 class TArena
 {
 public:
diff --git a/src/gallium/drivers/swr/rasterizer/core/backend.cpp 
b/src/gallium/drivers/swr/rasterizer/core/backend.cpp
index 7fb83ed..ad0a5a0 100644
--- a/src/gallium/drivers/swr/rasterizer/core/backend.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/backend.cpp
@@ -83,7 +83,7 @@ void ProcessComputeBE(DRAW_CONTEXT* pDC, uint32_t workerId, 
uint32_t threadGroup
 if (pDC->pSpillFill[workerId] == nullptr)
 {
 ///@todo Add state which indicates the spill fill size.
-pDC->pSpillFill[workerId] = 
(uint8_t*)pDC->pArena->AllocAlignedSync(4096 * 1024, sizeof(float) * 8);
+pDC->pSpillFill[workerId] = (uint8_t*)pDC->pArena->AllocAlignedSync(4 
* sizeof(MEGABYTE), sizeof(float) * 8);
 }
 
 const API_STATE& state = GetApiState(pDC);

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Mesa (master): swr: [rasterizer core] Replace all naked OSALIGN macro uses with OSALIGNSIMD / OSALIGNLINE

2016-04-12 Thread Tim Rowley

Module: Mesa
Branch: master
Commit: 2c71fd4bf81b82c7c3f57fc2c97aa83e814b6883
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c71fd4bf81b82c7c3f57fc2c97aa83e814b6883

Author: Tim Rowley 
Date:   Tue Mar 29 11:56:04 2016 -0600

swr: [rasterizer core] Replace all naked OSALIGN macro uses with OSALIGNSIMD / 
OSALIGNLINE

Future proofing

Acked-by: Brian Paul 

---

 src/gallium/drivers/swr/rasterizer/core/clip.cpp   |  4 ++--
 src/gallium/drivers/swr/rasterizer/core/clip.h |  4 ++--
 src/gallium/drivers/swr/rasterizer/core/pa.h   |  4 ++--
 src/gallium/drivers/swr/rasterizer/core/rasterizer.cpp | 16 
 4 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/core/clip.cpp 
b/src/gallium/drivers/swr/rasterizer/core/clip.cpp
index 3a2a8b3..e624fd8 100644
--- a/src/gallium/drivers/swr/rasterizer/core/clip.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/clip.cpp
@@ -162,8 +162,8 @@ int ClipTriToPlane( const float *pInPts, int numInPts,
 void Clip(const float *pTriangle, const float *pAttribs, int numAttribs, float 
*pOutTriangles, int *numVerts, float *pOutAttribs)
 {
 // temp storage to hold at least 6 sets of vertices, the max number that 
can be created during clipping
-OSALIGN(float, 16) tempPts[6 * 4];
-OSALIGN(float, 16) tempAttribs[6 * KNOB_NUM_ATTRIBUTES * 4];
+OSALIGNSIMD(float) tempPts[6 * 4];
+OSALIGNSIMD(float) tempAttribs[6 * KNOB_NUM_ATTRIBUTES * 4];
 
 // we opt to clip to viewport frustum to produce smaller triangles for 
rasterization precision
 int NumOutPts = ClipTriToPlane(pTriangle, 3, pAttribs, 
numAttribs, tempPts, tempAttribs);
diff --git a/src/gallium/drivers/swr/rasterizer/core/clip.h 
b/src/gallium/drivers/swr/rasterizer/core/clip.h
index ba5870a..67a4c4f 100644
--- a/src/gallium/drivers/swr/rasterizer/core/clip.h
+++ b/src/gallium/drivers/swr/rasterizer/core/clip.h
@@ -265,8 +265,8 @@ public:
 // clip a single primitive
 int ClipScalar(PA_STATE& pa, uint32_t primIndex, float* pOutPos, float* 
pOutAttribs)
 {
-OSALIGN(float, 16) inVerts[3 * 4];
-OSALIGN(float, 16) inAttribs[3 * KNOB_NUM_ATTRIBUTES * 4];
+OSALIGNSIMD(float) inVerts[3 * 4];
+OSALIGNSIMD(float) inAttribs[3 * KNOB_NUM_ATTRIBUTES * 4];
 
 // transpose primitive position
 __m128 verts[3];
diff --git a/src/gallium/drivers/swr/rasterizer/core/pa.h 
b/src/gallium/drivers/swr/rasterizer/core/pa.h
index 4fd6dd0..17f4885 100644
--- a/src/gallium/drivers/swr/rasterizer/core/pa.h
+++ b/src/gallium/drivers/swr/rasterizer/core/pa.h
@@ -1017,13 +1017,13 @@ struct PA_TESS : PA_STATE
 {
 SWR_ASSERT(numPrims <= KNOB_SIMD_WIDTH);
 #if KNOB_SIMD_WIDTH == 8
-static const OSALIGN(int32_t, 64) maskGen[KNOB_SIMD_WIDTH * 2] =
+static const OSALIGNLINE(int32_t) maskGen[KNOB_SIMD_WIDTH * 2] =
 {
 -1, -1, -1, -1, -1, -1, -1, -1,
  0,  0,  0,  0,  0,  0,  0,  0
 };
 #elif KNOB_SIMD_WIDTH == 16
-static const OSALIGN(int32_t, 128) maskGen[KNOB_SIMD_WIDTH * 2] =
+static const OSALIGNLINE(int32_t) maskGen[KNOB_SIMD_WIDTH * 2] =
 {
 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0
diff --git a/src/gallium/drivers/swr/rasterizer/core/rasterizer.cpp 
b/src/gallium/drivers/swr/rasterizer/core/rasterizer.cpp
index 52fb7c8..3144a90 100644
--- a/src/gallium/drivers/swr/rasterizer/core/rasterizer.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/rasterizer.cpp
@@ -383,7 +383,7 @@ __declspec(thread) volatile uint64_t gToss;
 
 static const uint32_t vertsPerTri = 3, componentsPerAttrib = 4;
 // try to avoid _chkstk insertions; make this thread local
-static THREAD OSALIGN(float, 16) perspAttribsTLS[vertsPerTri * 
KNOB_NUM_ATTRIBUTES * componentsPerAttrib];
+static THREAD OSALIGNLINE(float) perspAttribsTLS[vertsPerTri * 
KNOB_NUM_ATTRIBUTES * componentsPerAttrib];
 
 INLINE
 void ComputeEdgeData(int32_t a, int32_t b, EDGE& edge)
@@ -439,7 +439,7 @@ void RasterizeTriangle(DRAW_CONTEXT* pDC, uint32_t 
workerId, uint32_t macroTile,
 const SWR_RASTSTATE  = state.rastState;
 const BACKEND_FUNCS& backendFuncs = pDC->pState->backendFuncs;
 
-OSALIGN(SWR_TRIANGLE_DESC, 16) triDesc;
+OSALIGNSIMD(SWR_TRIANGLE_DESC) triDesc;
 triDesc.pUserClipBuffer = workDesc.pUserClipBuffer;
 
 __m128 vX, vY, vZ, vRecipW;
@@ -502,7 +502,7 @@ void RasterizeTriangle(DRAW_CONTEXT* pDC, uint32_t 
workerId, uint32_t macroTile,
 _MM_EXTRACT_FLOAT(triDesc.J[1], vB, 2);
 _MM_EXTRACT_FLOAT(triDesc.J[2], vC, 2);
 
-OSALIGN(float, 16) oneOverW[4];
+OSALIGNSIMD(float) oneOverW[4];
 _mm_store_ps(oneOverW, vRecipW);
 triDesc.OneOverW[0] = oneOverW[0] - oneOverW[2];
 triDesc.OneOverW[1] = oneOverW[1] - oneOverW[2];
@@ -537,7 +537,7 @@ void

Mesa (master): swr: [rasterizer core] Quantize depth to depth buffer precision prior to depth test/write.

2016-04-12 Thread Tim Rowley

Module: Mesa
Branch: master
Commit: e1871c4459bbd291e6356e971c6aa2becf4ecb96
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e1871c4459bbd291e6356e971c6aa2becf4ecb96

Author: Tim Rowley 
Date:   Fri Mar 25 17:24:45 2016 -0600

swr: [rasterizer core] Quantize depth to depth buffer precision prior to depth 
test/write.

Fixes z-fighting issues.

Acked-by: Brian Paul 

---

 src/gallium/drivers/swr/rasterizer/core/api.cpp| 20 +++
 .../drivers/swr/rasterizer/core/backend.cpp| 31 ++---
 src/gallium/drivers/swr/rasterizer/core/context.h  |  2 ++
 .../drivers/swr/rasterizer/core/depthstencil.h | 40 +-
 src/gallium/drivers/swr/rasterizer/core/state.h|  1 +
 5 files changed, 81 insertions(+), 13 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/core/api.cpp 
b/src/gallium/drivers/swr/rasterizer/core/api.cpp
index 442cdd4..9e13ee1 100644
--- a/src/gallium/drivers/swr/rasterizer/core/api.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/api.cpp
@@ -33,6 +33,7 @@
 #include "core/api.h"
 #include "core/backend.h"
 #include "core/context.h"
+#include "core/depthstencil.h"
 #include "core/frontend.h"
 #include "core/rasterizer.h"
 #include "core/rdtsc_core.h"
@@ -884,6 +885,25 @@ void SetupPipeline(DRAW_CONTEXT *pDC)
  !pState->state.blendState.renderTarget[rt].writeDisableBlue) 
? (1 << rt) : 0;
 }
 }
+
+// Setup depth quantization function
+if (pState->state.depthHottileEnable)
+{
+switch (pState->state.rastState.depthFormat)
+{
+case R32_FLOAT_X8X24_TYPELESS: pState->state.pfnQuantizeDepth = 
QuantizeDepth < R32_FLOAT_X8X24_TYPELESS > ; break;
+case R32_FLOAT: pState->state.pfnQuantizeDepth = QuantizeDepth < 
R32_FLOAT > ; break;
+case R24_UNORM_X8_TYPELESS: pState->state.pfnQuantizeDepth = 
QuantizeDepth < R24_UNORM_X8_TYPELESS > ; break;
+case R16_UNORM: pState->state.pfnQuantizeDepth = QuantizeDepth < 
R16_UNORM > ; break;
+default: SWR_ASSERT(false, "Unsupported depth format for depth 
quantiztion.");
+pState->state.pfnQuantizeDepth = QuantizeDepth < R32_FLOAT > ;
+}
+}
+else
+{
+// set up pass-through quantize if depth isn't enabled
+pState->state.pfnQuantizeDepth = QuantizeDepth < R32_FLOAT > ;
+}
 }
 
 //
diff --git a/src/gallium/drivers/swr/rasterizer/core/backend.cpp 
b/src/gallium/drivers/swr/rasterizer/core/backend.cpp
index ad0a5a0..842ea32 100644
--- a/src/gallium/drivers/swr/rasterizer/core/backend.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/backend.cpp
@@ -772,8 +772,10 @@ void BackendSingleSample(DRAW_CONTEXT *pDC, uint32_t 
workerId, uint32_t x, uint3
 psContext.vOneOverW.centroid = psContext.vOneOverW.center;
 }
 
-// interpolate z
+// interpolate and quantize z
 psContext.vZ = vplaneps(coeffs.vZa, coeffs.vZb, coeffs.vZc, 
psContext.vI.center, psContext.vJ.center);
+psContext.vZ = state.pfnQuantizeDepth(psContext.vZ);
+
 RDTSC_STOP(BEBarycentric, 0, 0);
 
 simdmask clipCoverageMask = coverageMask & MASK;
@@ -793,7 +795,7 @@ void BackendSingleSample(DRAW_CONTEXT *pDC, uint32_t 
workerId, uint32_t x, uint3
 if(CanEarlyZ(pPSState))
 {
 RDTSC_START(BEEarlyDepthTest);
-depthPassMask = DepthStencilTest([0], 
, work.triFlags.frontFacing,
+depthPassMask = DepthStencilTest(, 
work.triFlags.frontFacing,
 psContext.vZ, 
pDepthBase, vCoverageMask, pStencilBase, );
 RDTSC_STOP(BEEarlyDepthTest, 0, 0);
 
@@ -825,7 +827,7 @@ void BackendSingleSample(DRAW_CONTEXT *pDC, uint32_t 
workerId, uint32_t x, uint3
 if(!CanEarlyZ(pPSState))
 {
 RDTSC_START(BELateDepthTest);
-depthPassMask = DepthStencilTest([0], 
, work.triFlags.frontFacing,
+depthPassMask = DepthStencilTest(, 
work.triFlags.frontFacing,
 psContext.vZ, 
pDepthBase, vCoverageMask, pStencilBase, );
 RDTSC_STOP(BELateDepthTest, 0, 0);
 
@@ -977,8 +979,9 @@ void BackendSampleRate(DRAW_CONTEXT *pDC, uint32_t 
workerId, uint32_t x, uint32_
 
 backendFuncs.pfnCalcSampleBarycentrics(coeffs, psContext);
 
-// interpolate z
+// interpolate and quantize z
 psContext.vZ = vplaneps(coeffs.vZa, coeffs.vZb, 
coeffs.vZc, psContext.vI.sample, psContext.vJ.sample);
+psContext.vZ = state.pfnQuantizeDepth(psContext.vZ);
 
 RDTSC_STOP(BEBarycentric, 0,

Mesa (master): swr: [rasterizer common] win32 build fixups

2016-04-12 Thread Tim Rowley

Module: Mesa
Branch: master
Commit: 2a19aca05fab2b7904b7187f85b2e421254a37e6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a19aca05fab2b7904b7187f85b2e421254a37e6

Author: Tim Rowley 
Date:   Thu Mar 24 17:48:57 2016 -0600

swr: [rasterizer common] win32 build fixups

Acked-by: Brian Paul 

---

 src/gallium/drivers/swr/rasterizer/common/os.h | 6 --
 1 file changed, 6 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/common/os.h 
b/src/gallium/drivers/swr/rasterizer/common/os.h
index 5794f3f..427ebc1 100644
--- a/src/gallium/drivers/swr/rasterizer/common/os.h
+++ b/src/gallium/drivers/swr/rasterizer/common/os.h
@@ -30,10 +30,6 @@
 
 #define SWR_API __cdecl
 
-#ifndef _CRT_SECURE_NO_WARNINGS
-#define _CRT_SECURE_NO_WARNINGS
-#endif
-
 #ifndef NOMINMAX
 #define NOMINMAX
 #endif
@@ -52,7 +48,6 @@
 
 #define PRAGMA_WARNING_POP() __pragma(warning(pop))
 
-#if defined(_WIN32)
 #if defined(_WIN64)
 #define BitScanReverseSizeT BitScanReverse64
 #define BitScanForwardSizeT BitScanForward64
@@ -62,7 +57,6 @@
 #define BitScanForwardSizeT BitScanForward
 #define _mm_popcount_sizeT _mm_popcnt_u32
 #endif
-#endif
 
 #elif defined(FORCE_LINUX) || defined(__linux__) || defined(__gnu_linux__)
 

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Mesa (master): swr: [rasterizer] Put in rudimentary garbage collection for the global arena allocator

2016-04-12 Thread Tim Rowley

Module: Mesa
Branch: master
Commit: 06c59dc417661cda41b50aa57656a848434acbb4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=06c59dc417661cda41b50aa57656a848434acbb4

Author: Tim Rowley 
Date:   Wed Mar 30 19:24:32 2016 -0600

swr: [rasterizer] Put in rudimentary garbage collection for the global arena 
allocator

- Check for unused blocks every few frames or every 64K draws
- Delete data unused since the last check if total unused data is > 20MB

Doesn't seem to cause a perf degridation

Acked-by: Brian Paul 

---

 src/gallium/drivers/swr/rasterizer/core/api.cpp   |  17 +-
 src/gallium/drivers/swr/rasterizer/core/arena.h   | 230 --
 src/gallium/drivers/swr/rasterizer/core/context.h |   1 +
 3 files changed, 187 insertions(+), 61 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/core/api.cpp 
b/src/gallium/drivers/swr/rasterizer/core/api.cpp
index d0738a7..c742ada 100644
--- a/src/gallium/drivers/swr/rasterizer/core/api.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/api.cpp
@@ -263,7 +263,20 @@ DRAW_CONTEXT* GetDrawContext(SWR_CONTEXT *pContext, bool 
isSplitDraw = false)
 _mm_pause();
 }
 
-uint32_t dcIndex = pContext->dcRing.GetHead() % 
KNOB_MAX_DRAWS_IN_FLIGHT;
+uint64_t curDraw = pContext->dcRing.GetHead();
+uint32_t dcIndex = curDraw % KNOB_MAX_DRAWS_IN_FLIGHT;
+
+static uint64_t lastDrawChecked;
+static uint32_t lastFrameChecked;
+if ((pContext->frameCount - lastFrameChecked) > 2 ||
+(curDraw - lastDrawChecked) > 0x1)
+{
+// Take this opportunity to clean-up old arena allocations
+pContext->cachingArenaAllocator.FreeOldBlocks();
+
+lastFrameChecked = pContext->frameCount;
+lastDrawChecked = curDraw;
+}
 
 DRAW_CONTEXT* pCurDrawContext = >dcRing[dcIndex];
 pContext->pCurDrawContext = pCurDrawContext;
@@ -1544,4 +1557,6 @@ void SWR_API SwrEndFrame(
 HANDLE hContext)
 {
 RDTSC_ENDFRAME();
+SWR_CONTEXT *pContext = GetContext(hContext);
+pContext->frameCount++;
 }
diff --git a/src/gallium/drivers/swr/rasterizer/core/arena.h 
b/src/gallium/drivers/swr/rasterizer/core/arena.h
index 0241f5b..64184e1 100644
--- a/src/gallium/drivers/swr/rasterizer/core/arena.h
+++ b/src/gallium/drivers/swr/rasterizer/core/arena.h
@@ -65,69 +65,41 @@ static_assert(sizeof(ArenaBlock) <= ARENA_BLOCK_ALIGN,
 template
 struct CachingAllocatorT : DefaultAllocator
 {
-static uint32_t GetBucketId(size_t blockSize)
-{
-uint32_t bucketId = 0;
-
-#if defined(BitScanReverseSizeT)
-BitScanReverseSizeT((unsigned long*), blockSize >> 
CACHE_START_BUCKET_BIT);
-bucketId = std::min(bucketId, CACHE_NUM_BUCKETS - 1);
-#endif
-
-return bucketId;
-}
-
 void* AllocateAligned(size_t size, size_t align)
 {
 SWR_ASSERT(size >= sizeof(ArenaBlock));
 SWR_ASSERT(size <= uint32_t(-1));
 
 size_t blockSize = size - ARENA_BLOCK_ALIGN;
+uint32_t bucket = GetBucketId(blockSize);
 
 {
 // search cached blocks
 std::lock_guard l(m_mutex);
-ArenaBlock* pPrevBlock = _cachedBlocks[GetBucketId(blockSize)];
-ArenaBlock* pBlock = pPrevBlock->pNext;
-ArenaBlock* pPotentialBlock = nullptr;
-ArenaBlock* pPotentialPrev = nullptr;
+ArenaBlock* pPrevBlock = _cachedBlocks[bucket];
+ArenaBlock* pBlock = SearchBlocks(pPrevBlock, blockSize, align);
 
-while (pBlock)
+if (pBlock)
 {
-if (pBlock->blockSize >= blockSize)
-{
-if (pBlock == AlignUp(pBlock, align))
-{
-if (pBlock->blockSize == blockSize)
-{
-// Won't find a better match
-break;
-}
-
-// We could use this as it is larger than we wanted, 
but
-// continue to search for a better match
-pPotentialBlock = pBlock;
-pPotentialPrev = pPrevBlock;
-}
-}
-else
+m_cachedSize -= pBlock->blockSize;
+if (pBlock == m_pLastCachedBlocks[bucket])
 {
-// Blocks are sorted by size (biggest first)
-// So, if we get here, there are no blocks 
-// large enough, fall through to allocation.
-pBlock = nullptr;
-break;
+m_pLastCachedBlocks[bucket] = pPrevBlock;
 }
-
-pPrevBlock = pBlock;
-pBlock = pBlock->pNext;
 }
-
-if (!pBlock)
+else
 {
-

Mesa (master): swr: [rasterizer core] Put DRAW_CONTEXT on a diet

2016-04-12 Thread Tim Rowley

Module: Mesa
Branch: master
Commit: b990483de21cd99a94a098bb0eb397ba86b7b2a6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b990483de21cd99a94a098bb0eb397ba86b7b2a6

Author: Tim Rowley 
Date:   Wed Mar 30 15:54:48 2016 -0600

swr: [rasterizer core] Put DRAW_CONTEXT on a diet

No need for 256 pointers per DC.

Acked-by: Brian Paul 

---

 src/gallium/drivers/swr/rasterizer/core/api.cpp| 31 +++---
 .../drivers/swr/rasterizer/core/backend.cpp|  8 +++---
 src/gallium/drivers/swr/rasterizer/core/backend.h  |  2 +-
 src/gallium/drivers/swr/rasterizer/core/context.h  | 16 ++-
 .../drivers/swr/rasterizer/core/threads.cpp|  8 --
 .../drivers/swr/rasterizer/core/tilemgr.cpp| 21 ---
 src/gallium/drivers/swr/rasterizer/core/tilemgr.h  |  6 -
 7 files changed, 43 insertions(+), 49 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/core/api.cpp 
b/src/gallium/drivers/swr/rasterizer/core/api.cpp
index 665b6c0..d0738a7 100644
--- a/src/gallium/drivers/swr/rasterizer/core/api.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/api.cpp
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "core/api.h"
 #include "core/backend.h"
@@ -65,11 +66,14 @@ HANDLE SwrCreateContext(
 pContext->dcRing.Init(KNOB_MAX_DRAWS_IN_FLIGHT);
 pContext->dsRing.Init(KNOB_MAX_DRAWS_IN_FLIGHT);
 
+pContext->pMacroTileManagerArray = 
(MacroTileMgr*)_aligned_malloc(sizeof(MacroTileMgr) * KNOB_MAX_DRAWS_IN_FLIGHT, 
64);
+pContext->pDispatchQueueArray = 
(DispatchQueue*)_aligned_malloc(sizeof(DispatchQueue) * 
KNOB_MAX_DRAWS_IN_FLIGHT, 64);
+
 for (uint32_t dc = 0; dc < KNOB_MAX_DRAWS_IN_FLIGHT; ++dc)
 {
 pContext->dcRing[dc].pArena = new 
CachingArena(pContext->cachingArenaAllocator);
-pContext->dcRing[dc].pTileMgr = new 
MacroTileMgr(*(pContext->dcRing[dc].pArena));
-pContext->dcRing[dc].pDispatch = new DispatchQueue(); /// @todo Could 
lazily allocate this if Dispatch seen.
+new (>pMacroTileManagerArray[dc]) 
MacroTileMgr(*pContext->dcRing[dc].pArena);
+new (>pDispatchQueueArray[dc]) DispatchQueue();
 
 pContext->dsRing[dc].pArena = new 
CachingArena(pContext->cachingArenaAllocator);
 }
@@ -143,10 +147,13 @@ void SwrDestroyContext(HANDLE hContext)
 {
 delete pContext->dcRing[i].pArena;
 delete pContext->dsRing[i].pArena;
-delete(pContext->dcRing[i].pTileMgr);
-delete(pContext->dcRing[i].pDispatch);
+pContext->pMacroTileManagerArray[i].~MacroTileMgr();
+pContext->pDispatchQueueArray[i].~DispatchQueue();
 }
 
+_aligned_free(pContext->pDispatchQueueArray);
+_aligned_free(pContext->pMacroTileManagerArray);
+
 // Free scratch space.
 for (uint32_t i = 0; i < pContext->NumWorkerThreads; ++i)
 {
@@ -176,6 +183,15 @@ void WakeAllThreads(SWR_CONTEXT *pContext)
 template
 void QueueWork(SWR_CONTEXT *pContext)
 {
+DRAW_CONTEXT* pDC = pContext->pCurDrawContext;
+uint32_t dcIndex = pDC->drawId % KNOB_MAX_DRAWS_IN_FLIGHT;
+
+if (IsDraw)
+{
+pDC->pTileMgr = >pMacroTileManagerArray[dcIndex];
+pDC->pTileMgr->initialize();
+}
+
 // Each worker thread looks at a DC for both FE and BE work at different 
times and so we
 // multiply threadDone by 2.  When the threadDone counter has reached 0 
then all workers
 // have moved past this DC. (i.e. Each worker has checked this DC for both 
FE and BE work and
@@ -299,8 +315,6 @@ DRAW_CONTEXT* GetDrawContext(SWR_CONTEXT *pContext, bool 
isSplitDraw = false)
 pCurDrawContext->FeLock = 0;
 pCurDrawContext->threadsDone = 0;
 
-pCurDrawContext->pTileMgr->initialize();
-
 // Assign unique drawId for this DC
 pCurDrawContext->drawId = pContext->dcRing.GetHead();
 
@@ -1368,9 +1382,6 @@ void SwrDispatch(
 
 pDC->isCompute = true;  // This is a compute context.
 
-// Ensure spill fill pointers are initialized to nullptr.
-memset(pDC->pSpillFill, 0, sizeof(pDC->pSpillFill));
-
 COMPUTE_DESC* pTaskData = 
(COMPUTE_DESC*)pDC->pArena->AllocAligned(sizeof(COMPUTE_DESC), 64);
 
 pTaskData->threadGroupCountX = threadGroupCountX;
@@ -1378,6 +1389,8 @@ void SwrDispatch(
 pTaskData->threadGroupCountZ = threadGroupCountZ;
 
 uint32_t totalThreadGroups = threadGroupCountX * threadGroupCountY * 
threadGroupCountZ;
+uint32_t dcIndex = pDC->drawId % KNOB_MAX_DRAWS_IN_FLIGHT;
+pDC->pDispatch = >pDispatchQueueArray[dcIndex];
 pDC->pDispatch->initialize(totalThreadGroups, pTaskData);
 
 QueueDispatch(pContext);
diff --git a/src/gallium/drivers/swr/rasterizer/core/backend.cpp 
b/src/gallium/drivers/swr/rasterizer/core/backend.cpp
index 842ea32..b2d3d9e 100644
--- a/src/gallium/drivers/swr/rasterizer/core/backend.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/backend.cpp
@@ -70,7 +70,7 @@ static PFN_CLEAR_TILES

Mesa (master): swr: [rasterizer] Misc fixes identified by static code analysis

2016-04-12 Thread Tim Rowley

Module: Mesa
Branch: master
Commit: f89f6d562aaa7d85fb5c6e9d8d98a9f20deab462
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f89f6d562aaa7d85fb5c6e9d8d98a9f20deab462

Author: Tim Rowley 
Date:   Thu Mar 24 15:52:11 2016 -0600

swr: [rasterizer] Misc fixes identified by static code analysis

No perf loss detected

Acked-by: Brian Paul 

---

 src/gallium/drivers/swr/rasterizer/core/frontend.cpp | 10 --
 src/gallium/drivers/swr/rasterizer/core/pa.h | 10 --
 src/gallium/drivers/swr/rasterizer/core/threads.cpp  |  5 -
 src/gallium/drivers/swr/rasterizer/core/tilemgr.h|  2 +-
 4 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp 
b/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
index 36721e0..9386961 100644
--- a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
@@ -793,8 +793,14 @@ static void GeometryShaderStage(
 uint8_t* pCutBase = pCutBufferBase + instance * cutInstanceStride;
 
 DWORD numAttribs;
-_BitScanReverse(, state.feAttribMask);
-numAttribs++;
+if (_BitScanReverse(, state.feAttribMask))
+{
+numAttribs++;
+}
+else
+{
+numAttribs = 0;
+}
 
 for (uint32_t stream = 0; stream < MAX_SO_STREAMS; ++stream)
 {
diff --git a/src/gallium/drivers/swr/rasterizer/core/pa.h 
b/src/gallium/drivers/swr/rasterizer/core/pa.h
index f8f1a33..4fd6dd0 100644
--- a/src/gallium/drivers/swr/rasterizer/core/pa.h
+++ b/src/gallium/drivers/swr/rasterizer/core/pa.h
@@ -1167,8 +1167,14 @@ struct PA_FACTORY
 {
 memset(, 0, sizeof(indexStore));
 DWORD numAttribs;
-_BitScanReverse(, state.feAttribMask);
-numAttribs++;
+if (_BitScanReverse(, state.feAttribMask))
+{
+numAttribs++;
+}
+else
+{
+numAttribs = 0;
+}
 new (>paCut) PA_STATE_CUT(pDC, 
(uint8_t*)>vertexStore[0], MAX_NUM_VERTS_PER_PRIM * KNOB_SIMD_WIDTH, 
 >indexStore[0], numVerts, numAttribs, state.topology, 
false);
 cutPA = true;
diff --git a/src/gallium/drivers/swr/rasterizer/core/threads.cpp 
b/src/gallium/drivers/swr/rasterizer/core/threads.cpp
index 07bc94a..1a11175 100644
--- a/src/gallium/drivers/swr/rasterizer/core/threads.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/threads.cpp
@@ -68,7 +68,10 @@ void CalculateProcessorTopology(CPUNumaNodes& out_nodes, 
uint32_t& out_numThread
 
 #if defined(_WIN32)
 
-SYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX buffer[KNOB_MAX_NUM_THREADS];
+static std::mutex m;
+std::lock_guard l(m);
+
+static SYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX 
buffer[KNOB_MAX_NUM_THREADS];
 DWORD bufSize = sizeof(buffer);
 
 BOOL ret = GetLogicalProcessorInformationEx(RelationProcessorCore, buffer, 
);
diff --git a/src/gallium/drivers/swr/rasterizer/core/tilemgr.h 
b/src/gallium/drivers/swr/rasterizer/core/tilemgr.h
index aa561ba..34992aa 100644
--- a/src/gallium/drivers/swr/rasterizer/core/tilemgr.h
+++ b/src/gallium/drivers/swr/rasterizer/core/tilemgr.h
@@ -272,7 +272,7 @@ class HotTileMgr
 public:
 HotTileMgr()
 {
-memset([0][0], 0, sizeof(mHotTiles));
+memset(mHotTiles, 0, sizeof(mHotTiles));
 
 // cache hottile size
 for (uint32_t i = SWR_ATTACHMENT_COLOR0; i <= SWR_ATTACHMENT_COLOR7; 
++i)

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Mesa (master): swr: [rasterizer core] warning cleanup

2016-04-12 Thread Tim Rowley

Module: Mesa
Branch: master
Commit: df37b06276a7298d3785e95fbe2ec9dc1ebd6c4c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=df37b06276a7298d3785e95fbe2ec9dc1ebd6c4c

Author: Tim Rowley 
Date:   Fri Apr  1 15:52:34 2016 -0600

swr: [rasterizer core] warning cleanup

Acked-by: Brian Paul 

---

 src/gallium/drivers/swr/rasterizer/core/api.cpp | 8 
 src/gallium/drivers/swr/rasterizer/core/tilemgr.cpp | 1 -
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/core/api.cpp 
b/src/gallium/drivers/swr/rasterizer/core/api.cpp
index c742ada..ca9cfdb 100644
--- a/src/gallium/drivers/swr/rasterizer/core/api.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/api.cpp
@@ -1090,9 +1090,9 @@ void DrawInstanced(
 SWR_CONTEXT *pContext = GetContext(hContext);
 DRAW_CONTEXT* pDC = GetDrawContext(pContext);
 
-int32_t maxVertsPerDraw = MaxVertsPerDraw(pDC, numVertices, topology);
+uint32_t maxVertsPerDraw = MaxVertsPerDraw(pDC, numVertices, topology);
 uint32_t primsPerDraw = GetNumPrims(topology, maxVertsPerDraw);
-int32_t remainingVerts = numVertices;
+uint32_t remainingVerts = numVertices;
 
 API_STATE*pState = >pState->state;
 pState->topology = topology;
@@ -1210,9 +1210,9 @@ void DrawIndexedInstance(
 DRAW_CONTEXT* pDC = GetDrawContext(pContext);
 API_STATE* pState = >pState->state;
 
-int32_t maxIndicesPerDraw = MaxVertsPerDraw(pDC, numIndices, topology);
+uint32_t maxIndicesPerDraw = MaxVertsPerDraw(pDC, numIndices, topology);
 uint32_t primsPerDraw = GetNumPrims(topology, maxIndicesPerDraw);
-int32_t remainingIndices = numIndices;
+uint32_t remainingIndices = numIndices;
 
 uint32_t indexSize = 0;
 switch (pState->indexBuffer.format)
diff --git a/src/gallium/drivers/swr/rasterizer/core/tilemgr.cpp 
b/src/gallium/drivers/swr/rasterizer/core/tilemgr.cpp
index c053e27..87d9f42 100644
--- a/src/gallium/drivers/swr/rasterizer/core/tilemgr.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/tilemgr.cpp
@@ -283,7 +283,6 @@ void HotTileMgr::ClearStencilHotTile(const HOTTILE* 
pHotTile)
 void HotTileMgr::InitializeHotTiles(SWR_CONTEXT* pContext, DRAW_CONTEXT* pDC, 
uint32_t macroID)
 {
 const API_STATE& state = GetApiState(pDC);
-HotTileMgr *pHotTileMgr = pContext->pHotTileMgr;
 
 uint32_t x, y;
 MacroTileMgr::getTileIndices(macroID, x, y);

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Mesa (master): swr: [rasterizer core] Add experimental support for hyper-threaded front-end

2016-04-12 Thread Tim Rowley

Module: Mesa
Branch: master
Commit: a939a58881063c092a95bd7f1426b8fae1d8a44d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a939a58881063c092a95bd7f1426b8fae1d8a44d

Author: Tim Rowley 
Date:   Wed Mar 30 14:59:40 2016 -0600

swr: [rasterizer core] Add experimental support for hyper-threaded front-end

Acked-by: Brian Paul 

---

 src/gallium/drivers/swr/rasterizer/core/api.cpp|   8 +-
 src/gallium/drivers/swr/rasterizer/core/context.h  |  38 +++
 .../drivers/swr/rasterizer/core/threads.cpp| 126 +++--
 src/gallium/drivers/swr/rasterizer/core/threads.h  |   4 +-
 .../drivers/swr/rasterizer/scripts/knob_defs.py|  19 
 5 files changed, 139 insertions(+), 56 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/core/api.cpp 
b/src/gallium/drivers/swr/rasterizer/core/api.cpp
index 9e13ee1..665b6c0 100644
--- a/src/gallium/drivers/swr/rasterizer/core/api.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/api.cpp
@@ -87,7 +87,10 @@ HANDLE SwrCreateContext(
 // Calling createThreadPool() above can set SINGLE_THREADED
 if (KNOB_SINGLE_THREADED)
 {
+SET_KNOB(HYPERTHREADED_FE, false);
 pContext->NumWorkerThreads = 1;
+pContext->NumFEThreads = 1;
+pContext->NumBEThreads = 1;
 }
 
 // Allocate scratch space for workers.
@@ -177,8 +180,7 @@ void QueueWork(SWR_CONTEXT *pContext)
 // multiply threadDone by 2.  When the threadDone counter has reached 0 
then all workers
 // have moved past this DC. (i.e. Each worker has checked this DC for both 
FE and BE work and
 // then moved on if all work is done.)
-pContext->pCurDrawContext->threadsDone =
-pContext->NumWorkerThreads ? pContext->NumWorkerThreads * 2 : 2;
+pContext->pCurDrawContext->threadsDone = pContext->NumFEThreads + 
pContext->NumBEThreads;
 
 _ReadWriteBarrier();
 {
@@ -196,7 +198,7 @@ void QueueWork(SWR_CONTEXT *pContext)
 {
 static TileSet lockedTiles;
 uint64_t curDraw[2] = { pContext->pCurDrawContext->drawId, 
pContext->pCurDrawContext->drawId };
-WorkOnFifoFE(pContext, 0, curDraw[0], 0);
+WorkOnFifoFE(pContext, 0, curDraw[0]);
 WorkOnFifoBE(pContext, 0, curDraw[1], lockedTiles, 0, 0);
 }
 else
diff --git a/src/gallium/drivers/swr/rasterizer/core/context.h 
b/src/gallium/drivers/swr/rasterizer/core/context.h
index 27abe43..2c28286 100644
--- a/src/gallium/drivers/swr/rasterizer/core/context.h
+++ b/src/gallium/drivers/swr/rasterizer/core/context.h
@@ -382,32 +382,28 @@ struct DRAW_STATE
 //This draw context maintains all of the state needed for the draw 
operation.
 struct DRAW_CONTEXT
 {
-SWR_CONTEXT *pContext;
+SWR_CONTEXT*pContext;
+uint64_tdrawId;
+MacroTileMgr*   pTileMgr;
+DispatchQueue*  pDispatch;  // Queue for thread groups. (isCompute)
+uint64_tdependency;
+DRAW_STATE* pState;
+CachingArena*   pArena;
 
-uint64_t drawId;
+boolisCompute;  // Is this DC a compute context?
+boolcleanupState;   // True if this is the last draw using an 
entry in the state ring.
+volatile bool   doneFE; // Is FE work done for this draw?
 
-bool isCompute;// Is this DC a compute context?
+volatile OSALIGNLINE(uint32_t)   FeLock;
+volatile int64_tthreadsDone;
 
-FE_WORK FeWork;
-volatile OSALIGNLINE(uint32_t) FeLock;
-volatile OSALIGNLINE(bool) doneFE;// Is FE work done for this draw?
-volatile OSALIGNLINE(int64_t) threadsDone;
+OSALIGNLINE(FE_WORK) FeWork;
+uint8_t*pSpillFill[KNOB_MAX_NUM_THREADS];  // Scratch space used 
for spill fills.
 
-uint64_t dependency;
-
-MacroTileMgr* pTileMgr;
-
-// The following fields are valid if isCompute is true.
-DispatchQueue* pDispatch;   // Queue for thread groups. 
(isCompute)
-
-DRAW_STATE* pState;
-CachingArena* pArena;
-
-uint8_t* pSpillFill[KNOB_MAX_NUM_THREADS];  // Scratch space used for 
spill fills.
-
-bool  cleanupState; // True if this is the last draw using an entry in the 
state ring.
 };
 
+static_assert((sizeof(DRAW_CONTEXT) & 63) == 0, "Invalid size for 
DRAW_CONTEXT");
+
 INLINE const API_STATE& GetApiState(const DRAW_CONTEXT* pDC)
 {
 SWR_ASSERT(pDC != nullptr);
@@ -459,6 +455,8 @@ struct SWR_CONTEXT
 uint32_t curStateId;   // Current index to the next available 
entry in the DS ring.
 
 uint32_t NumWorkerThreads;
+uint32_t NumFEThreads;
+uint32_t NumBEThreads;
 
 THREAD_POOL threadPool; // Thread pool associated with this context
 
diff --git a/src/gallium/drivers/swr/rasterizer/core/threads.cpp 
b/src/gallium/drivers/swr/rasterizer/core/threads.cpp
index 056003e..bee1e13 100644
--- a/src/gallium/drivers/swr/rasterizer/core/threads.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/threads.cpp
@@

Mesa (master): swr: [rasterizer] Avoid segv in thread creation on machines with non-consecutive NUMA topology.

2016-04-12 Thread Tim Rowley

Module: Mesa
Branch: master
Commit: 9a8146d0ff623ee26f17b9292176ab0a79ead374
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a8146d0ff623ee26f17b9292176ab0a79ead374

Author: Tim Rowley 
Date:   Wed Mar 30 12:32:41 2016 -0600

swr: [rasterizer] Avoid segv in thread creation on machines with 
non-consecutive NUMA topology.

Acked-by: Brian Paul 

---

 src/gallium/drivers/swr/rasterizer/core/threads.cpp | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/drivers/swr/rasterizer/core/threads.cpp 
b/src/gallium/drivers/swr/rasterizer/core/threads.cpp
index 1a11175..056003e 100644
--- a/src/gallium/drivers/swr/rasterizer/core/threads.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/threads.cpp
@@ -783,6 +783,10 @@ void CreateThreadPool(SWR_CONTEXT *pContext, THREAD_POOL 
*pPool)
 for (uint32_t n = 0; n < numNodes; ++n)
 {
 auto& node = nodes[n];
+if (node.cores.size() == 0)
+{
+   continue;
+}
 
 uint32_t numCores = numCoresPerNode;
 for (uint32_t c = 0; c < numCores; ++c)

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Mesa (master): swr: [rasterizer] Ensure correct alignment of stack variables used as vectors

2016-04-12 Thread Tim Rowley

Module: Mesa
Branch: master
Commit: 32a8653ad2cef2fba70b33ee62adc6f5d9d427d8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=32a8653ad2cef2fba70b33ee62adc6f5d9d427d8

Author: Tim Rowley 
Date:   Tue Mar 29 10:58:43 2016 -0600

swr: [rasterizer] Ensure correct alignment of stack variables used as vectors

Acked-by: Brian Paul 

---

 src/gallium/drivers/swr/rasterizer/common/os.h  | 4 +---
 src/gallium/drivers/swr/rasterizer/core/knobs.h | 3 +++
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/common/os.h 
b/src/gallium/drivers/swr/rasterizer/common/os.h
index 427ebc1..180a056 100644
--- a/src/gallium/drivers/swr/rasterizer/common/os.h
+++ b/src/gallium/drivers/swr/rasterizer/common/os.h
@@ -193,9 +193,7 @@ typedef KILOBYTEMEGABYTE[1024];
 typedef MEGABYTEGIGABYTE[1024];
 
 #define OSALIGNLINE(RWORD) OSALIGN(RWORD, 64)
-#if KNOB_SIMD_WIDTH == 8
-#define OSALIGNSIMD(RWORD) OSALIGN(RWORD, 32)
-#endif
+#define OSALIGNSIMD(RWORD) OSALIGN(RWORD, KNOB_SIMD_BYTES)
 
 #include "common/swr_assert.h"
 
diff --git a/src/gallium/drivers/swr/rasterizer/core/knobs.h 
b/src/gallium/drivers/swr/rasterizer/core/knobs.h
index d7feb86..55a22a6 100644
--- a/src/gallium/drivers/swr/rasterizer/core/knobs.h
+++ b/src/gallium/drivers/swr/rasterizer/core/knobs.h
@@ -45,14 +45,17 @@
 #define KNOB_ARCH_ISA AVX
 #define KNOB_ARCH_STR "AVX"
 #define KNOB_SIMD_WIDTH 8
+#define KNOB_SIMD_BYTES 32
 #elif (KNOB_ARCH == KNOB_ARCH_AVX2)
 #define KNOB_ARCH_ISA AVX2
 #define KNOB_ARCH_STR "AVX2"
 #define KNOB_SIMD_WIDTH 8
+#define KNOB_SIMD_BYTES 32
 #elif (KNOB_ARCH == KNOB_ARCH_AVX512)
 #define KNOB_ARCH_ISA AVX512F
 #define KNOB_ARCH_STR "AVX512"
 #define KNOB_SIMD_WIDTH 16
+#define KNOB_SIMD_BYTES 64
 #error "AVX512 not yet supported"
 #else
 #error "Unknown architecture"

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Mesa (master): st/mesa: fix memleak in glDrawPixels cache code

2016-04-12 Thread Brian Paul

Module: Mesa
Branch: master
Commit: 6c014782138634d5d36e1484bf498cef2b2d888f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c014782138634d5d36e1484bf498cef2b2d888f

Author: Brian Paul 
Date:   Mon Apr 11 18:54:28 2016 -0600

st/mesa: fix memleak in glDrawPixels cache code

If the glDrawPixels size changed, we leaked the previously cached
texture, if there was one.  This patch fixes the reference counting,
adds a refcount assertion check, and better handles potential malloc()
failures.

Tested with a modified version of the drawpix Mesa demo which changed
the image size for each glDrawPixels call.

Cc: "11.2" 
Reviewed-by: José Fonseca 
Reviewed-by: Charmaine Lee 

---

 src/mesa/state_tracker/st_cb_drawpixels.c | 23 ++-
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c 
b/src/mesa/state_tracker/st_cb_drawpixels.c
index 01ed544..3c7bc0c 100644
--- a/src/mesa/state_tracker/st_cb_drawpixels.c
+++ b/src/mesa/state_tracker/st_cb_drawpixels.c
@@ -384,7 +384,7 @@ make_texture(struct st_context *st,
struct gl_context *ctx = st->ctx;
struct pipe_context *pipe = st->pipe;
mesa_format mformat;
-   struct pipe_resource *pt;
+   struct pipe_resource *pt = NULL;
enum pipe_format pipeFormat;
GLenum baseInternalFormat;
 
@@ -403,10 +403,18 @@ make_texture(struct st_context *st,
unpack->SkipRows == 0 &&
unpack->SwapBytes == GL_FALSE &&
st->drawpix_cache.image) {
+  assert(st->drawpix_cache.texture);
+
   /* check if the pixel data is the same */
   if (memcmp(pixels, st->drawpix_cache.image, width * height * bpp) == 0) {
  /* OK, re-use the cached texture */
- return st->drawpix_cache.texture;
+ pipe_resource_reference(, st->drawpix_cache.texture);
+ /* refcount of returned texture should be at least two here.  One
+  * reference for the cache to hold on to, one for the caller (which
+  * it will release), and possibly more held by the driver.
+  */
+ assert(pt->reference.count >= 2);
+ return pt;
   }
}
 
@@ -525,8 +533,14 @@ make_texture(struct st_context *st,
   st->drawpix_cache.image = malloc(width * height * bpp);
   if (st->drawpix_cache.image) {
  memcpy(st->drawpix_cache.image, pixels, width * height * bpp);
+ pipe_resource_reference(>drawpix_cache.texture, pt);
+  }
+  else {
+ /* out of memory, free/disable cached texture */
+ st->drawpix_cache.width = 0;
+ st->drawpix_cache.height = 0;
+ pipe_resource_reference(>drawpix_cache.texture, NULL);
   }
-  st->drawpix_cache.texture = pt;
}
 #endif
 
@@ -1160,9 +1174,8 @@ st_DrawPixels(struct gl_context *ctx, GLint x, GLint y,
if (num_sampler_view > 1)
   pipe_sampler_view_reference([1], NULL);
 
-#if !USE_DRAWPIXELS_CACHE
+   /* free the texture (but may persist in the cache) */
pipe_resource_reference(, NULL);
-#endif
 }
 
 

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Mesa (master): mesa: Use STATIC_ASSERT whenever possible.

2016-04-12 Thread Jose Fonseca

Module: Mesa
Branch: master
Commit: 7279098dc58d2d9d533900f1607aee76fcbbdab0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7279098dc58d2d9d533900f1607aee76fcbbdab0

Author: Jose Fonseca 
Date:   Tue Apr 12 07:35:08 2016 +0100

mesa: Use STATIC_ASSERT whenever possible.

Reviewed-by: Eric Engestrom 
Reviewed-by: Roland Scheidegger 

---

 src/mesa/main/imports.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/main/imports.c b/src/mesa/main/imports.c
index 14cd588..fe54109 100644
--- a/src/mesa/main/imports.c
+++ b/src/mesa/main/imports.c
@@ -262,7 +262,7 @@ ffsll(long long int val)
 {
int bit;
 
-   assert(sizeof(val) == 8);
+   STATIC_ASSERT(sizeof(val) == 8);
 
bit = ffs((int) val);
if (bit != 0)

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Mesa (master): gallium: Use STATIC_ASSERT whenever possible.

2016-04-12 Thread Jose Fonseca

Module: Mesa
Branch: master
Commit: b5105e67a860c6c3271ad7d48e2d80e84c3e8ade
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5105e67a860c6c3271ad7d48e2d80e84c3e8ade

Author: Jose Fonseca 
Date:   Tue Apr 12 07:36:06 2016 +0100

gallium: Use STATIC_ASSERT whenever possible.

Reviewed-by: Eric Engestrom 
Reviewed-by: Roland Scheidegger 

---

 src/gallium/auxiliary/rtasm/rtasm_x86sse.c | 2 +-
 src/gallium/auxiliary/tgsi/tgsi_lowering.c | 2 +-
 src/gallium/auxiliary/tgsi/tgsi_parse.c| 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/auxiliary/rtasm/rtasm_x86sse.c 
b/src/gallium/auxiliary/rtasm/rtasm_x86sse.c
index 27ee8f1..3e7d699 100644
--- a/src/gallium/auxiliary/rtasm/rtasm_x86sse.c
+++ b/src/gallium/auxiliary/rtasm/rtasm_x86sse.c
@@ -2203,7 +2203,7 @@ voidptr_to_x86_func(void *v)
   void *v;
   x86_func f;
} u;
-   assert(sizeof(u.v) == sizeof(u.f));
+   STATIC_ASSERT(sizeof(u.v) == sizeof(u.f));
u.v = v;
return u.f;
 }
diff --git a/src/gallium/auxiliary/tgsi/tgsi_lowering.c 
b/src/gallium/auxiliary/tgsi/tgsi_lowering.c
index a3b90bd..0ffd855 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_lowering.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_lowering.c
@@ -1430,7 +1430,7 @@ tgsi_transform_lowering(const struct tgsi_lowering_config 
*config,
int newlen, numtmp;
 
/* sanity check in case limit is ever increased: */
-   assert((sizeof(config->saturate_s) * 8) >= PIPE_MAX_SAMPLERS);
+   STATIC_ASSERT((sizeof(config->saturate_s) * 8) >= PIPE_MAX_SAMPLERS);
 
memset(, 0, sizeof(ctx));
ctx.base.transform_instruction = transform_instr;
diff --git a/src/gallium/auxiliary/tgsi/tgsi_parse.c 
b/src/gallium/auxiliary/tgsi/tgsi_parse.c
index ae95ebd..16564dd 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_parse.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_parse.c
@@ -313,7 +313,7 @@ tgsi_dump_tokens(const struct tgsi_token *tokens)
int nr = tgsi_num_tokens(tokens);
int i;

-   assert(sizeof(*tokens) == sizeof(unsigned));
+   STATIC_ASSERT(sizeof(*tokens) == sizeof(unsigned));
 
debug_printf("const unsigned tokens[%d] = {\n", nr);
for (i = 0; i < nr; i++)

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Mesa (master): softpipe: Use STATIC_ASSERT whenever possible.

2016-04-12 Thread Jose Fonseca

Module: Mesa
Branch: master
Commit: b025c23cfe6069829601df46670366a2b625f245
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b025c23cfe6069829601df46670366a2b625f245

Author: Jose Fonseca 
Date:   Tue Apr 12 07:35:38 2016 +0100

softpipe: Use STATIC_ASSERT whenever possible.

Reviewed-by: Eric Engestrom 
Reviewed-by: Roland Scheidegger 

---

 src/gallium/drivers/softpipe/sp_tile_cache.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/softpipe/sp_tile_cache.c 
b/src/gallium/drivers/softpipe/sp_tile_cache.c
index 9cc8ac1..c623326 100644
--- a/src/gallium/drivers/softpipe/sp_tile_cache.c
+++ b/src/gallium/drivers/softpipe/sp_tile_cache.c
@@ -99,9 +99,9 @@ sp_create_tile_cache( struct pipe_context *pipe )
maxTexSize = 1 << (maxLevels - 1);
assert(MAX_WIDTH >= maxTexSize);
 
-   assert(sizeof(union tile_address) == 4);
+   STATIC_ASSERT(sizeof(union tile_address) == 4);
 
-   assert((TILE_SIZE << TILE_ADDR_BITS) >= MAX_WIDTH);
+   STATIC_ASSERT((TILE_SIZE << TILE_ADDR_BITS) >= MAX_WIDTH);
 
tc = CALLOC_STRUCT( softpipe_tile_cache );
if (tc) {

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Mesa (master): svga: Use STATIC_ASSERT whenever possible.

2016-04-12 Thread Jose Fonseca

Module: Mesa
Branch: master
Commit: 2f13d7543fd272b4dd49d1389854ebcd6302694e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f13d7543fd272b4dd49d1389854ebcd6302694e

Author: Jose Fonseca 
Date:   Tue Apr 12 07:35:23 2016 +0100

svga: Use STATIC_ASSERT whenever possible.

Reviewed-by: Eric Engestrom 
Reviewed-by: Roland Scheidegger 

---

 src/gallium/drivers/svga/svga_pipe_depthstencil.c | 6 +++---
 src/gallium/drivers/svga/svga_state_rss.c | 4 ++--
 src/gallium/drivers/svga/svga_state_tss.c | 4 ++--
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_pipe_depthstencil.c 
b/src/gallium/drivers/svga/svga_pipe_depthstencil.c
index 83fcdc3..c5d83c3 100644
--- a/src/gallium/drivers/svga/svga_pipe_depthstencil.c
+++ b/src/gallium/drivers/svga/svga_pipe_depthstencil.c
@@ -86,9 +86,9 @@ define_depth_stencil_state_object(struct svga_context *svga,
ds->id = util_bitmask_add(svga->ds_object_id_bm);
 
/* spot check that these comparision tokens are the same */
-   assert(SVGA3D_COMPARISON_NEVER == SVGA3D_CMP_NEVER);
-   assert(SVGA3D_COMPARISON_LESS == SVGA3D_CMP_LESS);
-   assert(SVGA3D_COMPARISON_NOT_EQUAL == SVGA3D_CMP_NOTEQUAL);
+   STATIC_ASSERT(SVGA3D_COMPARISON_NEVER == SVGA3D_CMP_NEVER);
+   STATIC_ASSERT(SVGA3D_COMPARISON_LESS == SVGA3D_CMP_LESS);
+   STATIC_ASSERT(SVGA3D_COMPARISON_NOT_EQUAL == SVGA3D_CMP_NOTEQUAL);
 
/* Loop in case command buffer is full and we need to flush and retry */
for (try = 0; try < 2; try++) {
diff --git a/src/gallium/drivers/svga/svga_state_rss.c 
b/src/gallium/drivers/svga/svga_state_rss.c
index d43894d..317b44e 100644
--- a/src/gallium/drivers/svga/svga_state_rss.c
+++ b/src/gallium/drivers/svga/svga_state_rss.c
@@ -47,7 +47,7 @@ struct rs_queue {
 
 #define EMIT_RS(svga, value, token, fail)   \
 do {\
-   assert(SVGA3D_RS_##token < Elements(svga->state.hw_draw.rs)); \
+   STATIC_ASSERT(SVGA3D_RS_##token < Elements(svga->state.hw_draw.rs)); \
if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) {\
   svga_queue_rs( , SVGA3D_RS_##token, value );\
   svga->state.hw_draw.rs[SVGA3D_RS_##token] = value;\
@@ -57,7 +57,7 @@ do {  
  \
 #define EMIT_RS_FLOAT(svga, fvalue, token, fail)\
 do {\
unsigned value = fui(fvalue);\
-   assert(SVGA3D_RS_##token < Elements(svga->state.hw_draw.rs)); \
+   STATIC_ASSERT(SVGA3D_RS_##token < Elements(svga->state.hw_draw.rs)); \
if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) {\
   svga_queue_rs( , SVGA3D_RS_##token, value );\
   svga->state.hw_draw.rs[SVGA3D_RS_##token] = value;\
diff --git a/src/gallium/drivers/svga/svga_state_tss.c 
b/src/gallium/drivers/svga/svga_state_tss.c
index 4debbf1..fd6d1ce 100644
--- a/src/gallium/drivers/svga/svga_state_tss.c
+++ b/src/gallium/drivers/svga/svga_state_tss.c
@@ -327,7 +327,7 @@ svga_queue_tss( struct ts_queue *q,
 #define EMIT_TS(svga, unit, val, token) \
 do {\
assert(unit < Elements(svga->state.hw_draw.ts)); \
-   assert(SVGA3D_TS_##token < Elements(svga->state.hw_draw.ts[unit]));  \
+   STATIC_ASSERT(SVGA3D_TS_##token < Elements(svga->state.hw_draw.ts[unit])); \
if (svga->state.hw_draw.ts[unit][SVGA3D_TS_##token] != val) {\
   svga_queue_tss( queue, unit, SVGA3D_TS_##token, val );\
   svga->state.hw_draw.ts[unit][SVGA3D_TS_##token] = val;\
@@ -338,7 +338,7 @@ do {
\
 do {\
unsigned val = fui(fvalue);  \
assert(unit < Elements(svga->state.hw_draw.ts)); \
-   assert(SVGA3D_TS_##token < Elements(svga->state.hw_draw.ts[unit]));  \
+   STATIC_ASSERT(SVGA3D_TS_##token < Elements(svga->state.hw_draw.ts[unit])); \
if (svga->state.hw_draw.ts[unit][SVGA3D_TS_##token] != val) {\
   svga_queue_tss( queue, unit, SVGA3D_TS_##token, val );\
   svga->state.hw_draw.ts[unit][SVGA3D_TS_##token] = val;\

___
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Mesa (master): r600g: use common scissor and viewport code

2016-04-12 Thread Marek Olšák

Module: Mesa
Branch: master
Commit: 686b018ab313e3a95931676995be0e65dc7a9b75
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=686b018ab313e3a95931676995be0e65dc7a9b75

Author: Marek Olšák 
Date:   Sun Apr 10 04:56:46 2016 +0200

r600g: use common scissor and viewport code

It's the same as radeonsi. This adds guard band support to r600g.

Reviewed-by: Edward O'Callaghan 
Reviewed-by: Grigori Goronzy 
Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/r600/evergreen_state.c   | 76 +++-
 src/gallium/drivers/r600/r600_blit.c |  4 +-
 src/gallium/drivers/r600/r600_hw_context.c   | 10 ++--
 src/gallium/drivers/r600/r600_pipe.h | 17 ---
 src/gallium/drivers/r600/r600_state.c| 70 ++---
 src/gallium/drivers/r600/r600_state_common.c | 66 ++--
 6 files changed, 34 insertions(+), 209 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 0e05587..6b6e816 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -472,6 +472,7 @@ static void *evergreen_create_rs_state(struct pipe_context 
*ctx,
 
r600_init_command_buffer(>buffer, 30);
 
+   rs->scissor_enable = state->scissor;
rs->flatshade = state->flatshade;
rs->sprite_coord_enable = state->sprite_coord_enable;
rs->two_side = state->light_twoside;
@@ -528,7 +529,7 @@ static void *evergreen_create_rs_state(struct pipe_context 
*ctx,
r600_store_context_reg(>buffer, R_0286D4_SPI_INTERP_CONTROL_0, 
spi_interp);
r600_store_context_reg(>buffer, R_028A48_PA_SC_MODE_CNTL_0,
   S_028A48_MSAA_ENABLE(state->multisample) |
-  S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
+  S_028A48_VPORT_SCISSOR_ENABLE(1) |
   
S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
 
if (rctx->b.chip_class == CAYMAN) {
@@ -920,60 +921,12 @@ static void evergreen_get_scissor_rect(struct 
r600_context *rctx,
   unsigned tl_x, unsigned tl_y, unsigned 
br_x, unsigned br_y,
   uint32_t *tl, uint32_t *br)
 {
-   /* EG hw workaround */
-   if (br_x == 0)
-   tl_x = 1;
-   if (br_y == 0)
-   tl_y = 1;
+   struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y};
 
-   /* cayman hw workaround */
-   if (rctx->b.chip_class == CAYMAN) {
-   if (br_x == 1 && br_y == 1)
-   br_x = 2;
-   }
+   evergreen_apply_scissor_bug_workaround(>b, );
 
-   *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
-   *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
-}
-
-static void evergreen_set_scissor_states(struct pipe_context *ctx,
- unsigned start_slot,
- unsigned num_scissors,
-   const struct pipe_scissor_state *state)
-{
-   struct r600_context *rctx = (struct r600_context *)ctx;
-   struct r600_scissor_state *rstate = >scissor;
-   int i;
-
-   for (i = start_slot; i < start_slot + num_scissors; i++)
-   rstate->scissor[i] = state[i - start_slot];
-   rstate->dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
-   rstate->atom.num_dw = util_bitcount(rstate->dirty_mask) * 4;
-   r600_mark_atom_dirty(rctx, >atom);
-}
-
-static void evergreen_emit_scissor_state(struct r600_context *rctx, struct 
r600_atom *atom)
-{
-   struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
-   struct r600_scissor_state *rstate = >scissor;
-   struct pipe_scissor_state *state;
-   uint32_t dirty_mask;
-   unsigned i, offset;
-   uint32_t tl, br;
-
-   dirty_mask = rstate->dirty_mask;
-   while (dirty_mask != 0) {
-   i = u_bit_scan(_mask);
-   state = >scissor[i];
-   evergreen_get_scissor_rect(rctx, state->minx, state->miny, 
state->maxx, state->maxy, , );
-
-   offset = i * 4 * 2;
-   radeon_set_context_reg_seq(cs, 
R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2);
-   radeon_emit(cs, tl);
-   radeon_emit(cs, br);
-   }
-   rstate->dirty_mask = 0;
-   rstate->atom.num_dw = 0;
+   *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny);
+   *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy);
 }
 
 /**
@@ -2484,12 +2437,6 @@ static void cayman_init_atom_start_cs(struct 
r600_context *rctx)
r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0x);
r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
 
-   r600_store_context_reg_seq(cb,

Mesa (master): radeonsi: use guard band clipping

2016-04-12 Thread Marek Olšák

Module: Mesa
Branch: master
Commit: db00f6cc9cdef551e1069a6d5cf6171565cc0ace
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=db00f6cc9cdef551e1069a6d5cf6171565cc0ace

Author: Marek Olšák 
Date:   Sun Apr 10 03:38:09 2016 +0200

radeonsi: use guard band clipping

Guard band clipping speeds up rasterization for primitives that are
partially off-screen.  This change in particular results in small
framerate improvements in a wide range of games.

Started by Grigori Goronzy .

Reviewed-by: Edward O'Callaghan 
Reviewed-by: Grigori Goronzy 
Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_state.c | 73 +++--
 1 file changed, 69 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index fb7a070..14a58b3 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -887,6 +887,15 @@ static void si_clip_scissor(struct pipe_scissor_state *out,
out->maxy = MIN2(out->maxy, clip->maxy);
 }
 
+static void si_scissor_make_union(struct si_signed_scissor *out,
+ struct si_signed_scissor *in)
+{
+   out->minx = MIN2(out->minx, in->minx);
+   out->miny = MIN2(out->miny, in->miny);
+   out->maxx = MAX2(out->maxx, in->maxx);
+   out->maxy = MAX2(out->maxy, in->maxy);
+}
+
 static void si_emit_one_scissor(struct radeon_winsys_cs *cs,
struct si_signed_scissor *vp_scissor,
struct pipe_scissor_state *scissor)
@@ -908,12 +917,64 @@ static void si_emit_one_scissor(struct radeon_winsys_cs 
*cs,
S_028254_BR_Y(final.maxy));
 }
 
+/* the range is [-MAX, MAX] */
+#define SI_MAX_VIEWPORT_RANGE 32768
+
+static void si_emit_guardband(struct si_context *sctx,
+ struct si_signed_scissor *vp_as_scissor)
+{
+   struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+   struct pipe_viewport_state vp;
+   float left, top, right, bottom, max_range, guardband_x, guardband_y;
+
+   /* Reconstruct the viewport transformation from the scissor. */
+   vp.translate[0] = (vp_as_scissor->minx + vp_as_scissor->maxx) / 2.0;
+   vp.translate[1] = (vp_as_scissor->miny + vp_as_scissor->maxy) / 2.0;
+   vp.scale[0] = vp_as_scissor->maxx - vp.translate[0];
+   vp.scale[1] = vp_as_scissor->maxy - vp.translate[1];
+
+   /* Treat a 0x0 viewport as 1x1 to prevent division by zero. */
+   if (vp_as_scissor->minx == vp_as_scissor->maxx)
+   vp.scale[0] = 0.5;
+   if (vp_as_scissor->miny == vp_as_scissor->maxy)
+   vp.scale[1] = 0.5;
+
+   /* Find the biggest guard band that is inside the supported viewport
+* range. The guard band is specified as a horizontal and vertical
+* distance from (0,0) in clip space.
+*
+* This is done by applying the inverse viewport transformation
+* on the viewport limits to get those limits in clip space.
+*
+* Use a limit one pixel smaller to allow for some precision error.
+*/
+   max_range = SI_MAX_VIEWPORT_RANGE - 1;
+   left   = (-max_range - vp.translate[0]) / vp.scale[0];
+   right  = ( max_range - vp.translate[0]) / vp.scale[0];
+   top= (-max_range - vp.translate[1]) / vp.scale[1];
+   bottom = ( max_range - vp.translate[1]) / vp.scale[1];
+
+   assert(left <= -1 && top <= -1 && right >= 1 && bottom >= 1);
+
+   guardband_x = MIN2(-left, right);
+   guardband_y = MIN2(-top, bottom);
+
+   /* If any of the GB registers is updated, all of them must be updated. 
*/
+   radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
+   radeon_emit(cs, fui(guardband_y)); /* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
+   radeon_emit(cs, fui(1.0)); /* R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
+   radeon_emit(cs, fui(guardband_x)); /* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
+   radeon_emit(cs, fui(1.0)); /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
+}
+
 static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom)
 {
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
struct pipe_scissor_state *states = sctx->scissors.states;
unsigned mask = sctx->scissors.dirty_mask;
bool scissor_enable = sctx->queued.named.rasterizer->scissor_enable;
+   struct si_signed_scissor max_vp_scissor;
+   int i;
 
/* The simple case: Only 1 viewport is active. */
if (!si_get_vs_info(sctx)->writes_viewport_index) {
@@ -924,10 +985,17 @@ static void si_emit_scissors(struct si_context *sctx, 
struct r600_atom *atom)
 
radeon_set_context_reg_seq(cs, 
R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
si_emit_one_scissor(cs, vp, scissor_enable ? [0] :

Mesa (master): radeonsi: compute scissor from viewport in set_viewport_states

2016-04-12 Thread Marek Olšák

Module: Mesa
Branch: master
Commit: cb21f8a97cdd5ae240aecdfa417b60b2c0dd6789
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb21f8a97cdd5ae240aecdfa417b60b2c0dd6789

Author: Marek Olšák 
Date:   Sun Apr 10 03:29:57 2016 +0200

radeonsi: compute scissor from viewport in set_viewport_states

and clamp it right before emitting. This is a prerequisite for computing
the guard band.

Reviewed-by: Edward O'Callaghan 
Reviewed-by: Grigori Goronzy 
Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_pipe.h  |  8 
 src/gallium/drivers/radeonsi/si_state.c | 70 +++--
 2 files changed, 48 insertions(+), 30 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h 
b/src/gallium/drivers/radeonsi/si_pipe.h
index f665c81..b600b86 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -179,10 +179,18 @@ struct si_scissors {
struct pipe_scissor_state   states[SI_MAX_VIEWPORTS];
 };
 
+struct si_signed_scissor {
+   int minx;
+   int miny;
+   int maxx;
+   int maxy;
+};
+
 struct si_viewports {
struct r600_atomatom;
unsigneddirty_mask;
struct pipe_viewport_state  states[SI_MAX_VIEWPORTS];
+   struct si_signed_scissoras_scissor[SI_MAX_VIEWPORTS];
 };
 
 /* A shader state consists of the shader selector, which is a constant state
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index d75565a..fb7a070 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -838,40 +838,44 @@ static void si_set_scissor_states(struct pipe_context 
*ctx,
si_mark_atom_dirty(sctx, >scissors.atom);
 }
 
-static void si_get_scissor_from_viewport(struct pipe_viewport_state *vp,
-struct pipe_scissor_state *scissor)
+static void si_get_scissor_from_viewport(const struct pipe_viewport_state *vp,
+struct si_signed_scissor *scissor)
 {
-   /* These must be signed, unlike pipe_scissor_state. */
-   int minx, miny, maxx, maxy, tmp;
+   int tmp;
 
/* Convert (-1, -1) and (1, 1) from clip space into window space. */
-   minx = -vp->scale[0] + vp->translate[0];
-   miny = -vp->scale[1] + vp->translate[1];
-   maxx = vp->scale[0] + vp->translate[0];
-   maxy = vp->scale[1] + vp->translate[1];
+   scissor->minx = -vp->scale[0] + vp->translate[0];
+   scissor->miny = -vp->scale[1] + vp->translate[1];
+   scissor->maxx = vp->scale[0] + vp->translate[0];
+   scissor->maxy = vp->scale[1] + vp->translate[1];
 
/* r600_draw_rectangle sets this. Disable the scissor. */
-   if (minx == -1 && miny == -1 && maxx == 1 && maxy == 1) {
-   minx = miny = 0;
-   maxx = maxy = 16384;
+   if (scissor->minx == -1 && scissor->miny == -1 &&
+   scissor->maxx == 1 && scissor->maxy == 1) {
+   scissor->minx = scissor->miny = 0;
+   scissor->maxx = scissor->maxy = 16384;
}
 
/* Handle inverted viewports. */
-   if (minx > maxx) {
-   tmp = minx;
-   minx = maxx;
-   maxx = tmp;
+   if (scissor->minx > scissor->maxx) {
+   tmp = scissor->minx;
+   scissor->minx = scissor->maxx;
+   scissor->maxx = tmp;
}
-   if (miny > maxy) {
-   tmp = miny;
-   miny = maxy;
-   maxy = tmp;
+   if (scissor->miny > scissor->maxy) {
+   tmp = scissor->miny;
+   scissor->miny = scissor->maxy;
+   scissor->maxy = tmp;
}
+}
 
-   scissor->minx = CLAMP(minx, 0, 16384);
-   scissor->miny = CLAMP(miny, 0, 16384);
-   scissor->maxx = CLAMP(maxx, 0, 16384);
-   scissor->maxy = CLAMP(maxy, 0, 16384);
+static void si_clamp_scissor(struct pipe_scissor_state *out,
+struct si_signed_scissor *scissor)
+{
+   out->minx = CLAMP(scissor->minx, 0, 16384);
+   out->miny = CLAMP(scissor->miny, 0, 16384);
+   out->maxx = CLAMP(scissor->maxx, 0, 16384);
+   out->maxy = CLAMP(scissor->maxy, 0, 16384);
 }
 
 static void si_clip_scissor(struct pipe_scissor_state *out,
@@ -884,7 +888,7 @@ static void si_clip_scissor(struct pipe_scissor_state *out,
 }
 
 static void si_emit_one_scissor(struct radeon_winsys_cs *cs,
-   struct pipe_viewport_state *vp,
+   struct si_signed_scissor *vp_scissor,
struct pipe_scissor_state *scissor)
 {
struct pipe_scissor_state final;
@@ -892,7 +896,7 @@ static void si_emit_one_scissor(struct radeon_winsys_cs *cs,
/* Since the guard band disables

Mesa (master): radeonsi: move scissor and viewport states into gallium/ radeon

2016-04-12 Thread Marek Olšák

Module: Mesa
Branch: master
Commit: 2ca5566ed7847f5a56d055fd6530382c55012663
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ca5566ed7847f5a56d055fd6530382c55012663

Author: Marek Olšák 
Date:   Sun Apr 10 04:26:50 2016 +0200

radeonsi: move scissor and viewport states into gallium/radeon

Reviewed-by: Edward O'Callaghan 
Reviewed-by: Grigori Goronzy 
Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/r600/r600_pipe.h|   2 -
 src/gallium/drivers/radeon/Makefile.sources |   1 +
 src/gallium/drivers/radeon/r600_pipe_common.c   |   1 +
 src/gallium/drivers/radeon/r600_pipe_common.h   |  32 +++
 src/gallium/drivers/radeon/r600_viewport.c  | 320 
 src/gallium/drivers/radeon/r600d_common.h   |  20 ++
 src/gallium/drivers/radeonsi/si_blit.c  |   4 +-
 src/gallium/drivers/radeonsi/si_hw_context.c|   8 +-
 src/gallium/drivers/radeonsi/si_pipe.c  |   2 +-
 src/gallium/drivers/radeonsi/si_pipe.h  |  23 --
 src/gallium/drivers/radeonsi/si_state.c | 269 +---
 src/gallium/drivers/radeonsi/si_state_shaders.c |  25 +-
 12 files changed, 388 insertions(+), 319 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_pipe.h 
b/src/gallium/drivers/r600/r600_pipe.h
index 52f04b2..3af8607 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -38,8 +38,6 @@
 
 #define R600_NUM_ATOMS 52
 
-#define R600_MAX_VIEWPORTS 16
-
 /* read caches */
 #define R600_CONTEXT_INV_VERTEX_CACHE  (R600_CONTEXT_PRIVATE_FLAG << 0)
 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
diff --git a/src/gallium/drivers/radeon/Makefile.sources 
b/src/gallium/drivers/radeon/Makefile.sources
index eb171f7..f993d75 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -11,6 +11,7 @@ C_SOURCES := \
r600_query.h \
r600_streamout.c \
r600_texture.c \
+   r600_viewport.c \
radeon_uvd.c \
radeon_uvd.h \
radeon_vce_40_2_2.c \
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index a64a091..490cf8b 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -286,6 +286,7 @@ bool r600_common_context_init(struct r600_common_context 
*rctx,
LIST_INITHEAD(>texture_buffers);
 
r600_init_context_texture_functions(rctx);
+   r600_init_viewport_functions(rctx);
r600_streamout_init(rctx);
r600_query_init(rctx);
cayman_init_msaa(>b);
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index e227e48..ad41028 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -97,9 +97,11 @@
 #define DBG_MONOLITHIC_SHADERS (1llu << 47)
 
 #define R600_MAP_BUFFER_ALIGNMENT 64
+#define R600_MAX_VIEWPORTS16
 
 struct r600_common_context;
 struct r600_perfcounters;
+struct tgsi_shader_info;
 
 struct radeon_shader_reloc {
char name[32];
@@ -394,6 +396,26 @@ struct r600_streamout {
int num_prims_gen_queries;
 };
 
+struct r600_signed_scissor {
+   int minx;
+   int miny;
+   int maxx;
+   int maxy;
+};
+
+struct r600_scissors {
+   struct r600_atomatom;
+   unsigneddirty_mask;
+   struct pipe_scissor_state   states[R600_MAX_VIEWPORTS];
+};
+
+struct r600_viewports {
+   struct r600_atomatom;
+   unsigneddirty_mask;
+   struct pipe_viewport_state  states[R600_MAX_VIEWPORTS];
+   struct r600_signed_scissor  as_scissor[R600_MAX_VIEWPORTS];
+};
+
 struct r600_ring {
struct radeon_winsys_cs *cs;
void (*flush)(void *ctx, unsigned flags,
@@ -426,6 +448,10 @@ struct r600_common_context {
 
/* States. */
struct r600_streamout   streamout;
+   struct r600_scissorsscissors;
+   struct r600_viewports   viewports;
+   boolscissor_enabled;
+   boolvs_writes_viewport_index;
 
/* Additional context states. */
unsigned flags; /* flush flags */
@@ -609,6 +635,12 @@ void r600_texture_disable_dcc(struct r600_common_screen 
*rscreen,
 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 
+/* r600_viewport.c */
+void r600_set_scissor_enable(struct r600_common_context *rctx, bool enable);
+void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
+ struct

Mesa (master): 29 new commits

2016-04-12 Thread Marek Olšák

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b6a0b7fc02c27c334cf932cfdfd7bedef5a5198
Author: Marek Olšák 
Date:   Mon Apr 11 20:24:34 2016 +0200

gallium/radeon: set GTT WC on tiled textures

Just for consistency. This should have no effect, because OpenGL textures
always go to VRAM.

Reviewed-by: Alex Deucher 
Reviewed-by: Edward O'Callaghan 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a4b74d1ba2c156766a7a5dbfef099c7db5d6694
Author: Marek Olšák 
Date:   Mon Apr 11 19:56:07 2016 +0200

gallium/radeon: relax requirements on VRAM placements on APUs

This makes Tonga with vramlimit=128 2x faster in Heaven.

Reviewed-by: Alex Deucher 
Reviewed-by: Edward O'Callaghan 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a57309f807dc1e4450cd8c5ac132de0de4e17f89
Author: Marek Olšák 
Date:   Mon Apr 11 19:26:03 2016 +0200

winsys/amdgpu: remove hack for low VRAM configuration

A better solution will be used.

Reviewed-by: Alex Deucher 
Reviewed-by: Edward O'Callaghan 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b36f19bf98e206264b4de6ce5ca510c2d305ffe4
Author: Marek Olšák 
Date:   Thu Apr 7 21:18:14 2016 +0200

r600g: disable aniso filtering for non-mipmap textures on EG

this is the default behavior of the closed driver when running on VI

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3bc2d967c4c626f0efadfca8771a90797a12c22b
Author: Marek Olšák 
Date:   Fri Apr 8 02:09:59 2016 +0200

r600g: clean up aniso state translation

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0d4469519bf07c4051af8eb86ab71647fb1eb61
Author: Marek Olšák 
Date:   Thu Apr 7 21:37:43 2016 +0200

radeonsi: disable aniso filtering for non-mipmap textures on SI-CI

The closed driver does this, but it looks at base_level and last_level
and uses a conditional assignment, which LLVM can't generate on SGPRs.

That led me to invent this solution that abuses the image descriptor.

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ddd33431c54379ecf0dce71078e34a07be82e2fc
Author: Marek Olšák 
Date:   Fri Apr 8 02:08:23 2016 +0200

radeonsi: clean up aniso state translation

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7420ef5b4640a92a5aaa57341c59e0d4185a4a0
Author: Marek Olšák 
Date:   Thu Apr 7 17:02:51 2016 +0200

radeonsi: enable some sampler fields to match the closed driver

copied from the Vulkan driver

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a98be001f06ae2d50d444d1103cc15b67502a14
Author: Marek Olšák 
Date:   Thu Apr 7 15:34:45 2016 +0200

gallium/radeon: fix maximum texture anisotropy setup

We were overdoing it for non-power-of-two values.

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d7be5d37e70d19df88be53222bf02def40e93e6
Author: Marek Olšák 
Date:   Sun Apr 10 22:48:48 2016 +0200

gallium/radeon: never choose a linear tiling for DB surfaces

Just for consistency. This is actually not a problem, because both addrlib
and radeon check and fix this.

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7878146c444628e8f579d57f4c3af03ad1fc201
Author: Marek Olšák 
Date:   Sun Apr 10 22:39:54 2016 +0200

gallium/radeon: removing dead code for sharing stencil buffers

This is a remnant of the times when the DDX was allocating depth-stencil
buffers for windows. Now, st/dri allocates them and doesn't share them.

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=73aeebd772cfb840dee05d5815239b365d68f09e
Author: Marek Olšák 
Date:   Sun Apr 10 17:21:19 2016 +0200

radeonsi: allow clearing buffers >= 4 GB

Only CMASK and DCC clears can use this, because only textures can be so
large.

Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1dd8832e046ddef6d9ee69210127bebc9ddb35eb
Author: Marek Olšák 
Date:   Sun Apr 10 17:14:49

Mesa (master): radeonsi: Synchronize a streamout write after read hazard.

2016-04-12 Thread Bas Nieuwenhuizen

Module: Mesa
Branch: master
Commit: fc67375379ec26eef63f8e530724cd53c97bc3d0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc67375379ec26eef63f8e530724cd53c97bc3d0

Author: Bas Nieuwenhuizen 
Date:   Mon Apr 11 15:53:43 2016 +0200

radeonsi: Synchronize a streamout write after read hazard.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_descriptors.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 6dd2e4f..b3792c2 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -883,6 +883,12 @@ static void si_set_streamout_targets(struct pipe_context 
*ctx,
 SI_CONTEXT_VS_PARTIAL_FLUSH;
}
 
+   /* All readers of the streamout targets need to be finished before we 
can
+* start writing to the targets.
+*/
+   if (num_targets)
+   sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
+
/* Streamout buffers must be bound in 2 places:
 * 1) in VGT by setting the VGT_STRMOUT registers
 * 2) as shader resources

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Mesa (master): nv30: Add missing PIPE_SHADER_CAP_INTEGERS to get_shader_param()

2016-04-12 Thread Hans de Goede

Module: Mesa
Branch: master
Commit: dccdb655a169a43de4427580e230f9d3706436cd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dccdb655a169a43de4427580e230f9d3706436cd

Author: Hans de Goede 
Date:   Mon Apr 11 14:07:20 2016 +0200

nv30: Add missing PIPE_SHADER_CAP_INTEGERS to get_shader_param()

Add missing PIPE_SHADER_CAP_INTEGERS for frag shaders to
nv30_screen_get_shader_param().

Signed-off-by: Hans de Goede 
Reviewed-by: Samuel Pitoiset 

---

 src/gallium/drivers/nouveau/nv30/nv30_screen.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c 
b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
index db7c2d1..ece8af7 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
@@ -324,6 +324,7 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen, 
unsigned shader,
   case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
   case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
   case PIPE_SHADER_CAP_SUBROUTINES:
+  case PIPE_SHADER_CAP_INTEGERS:
   case PIPE_SHADER_CAP_DOUBLES:
   case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
   case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:

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Mesa (master): dri/i965: extend GLES3 sRGB workaround to cover all formats

2016-04-12 Thread Kenneth Graunke

Module: Mesa
Branch: master
Commit: b0e3ba61b5f8bb285472d5acda5ff233b05aeef4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0e3ba61b5f8bb285472d5acda5ff233b05aeef4

Author: Haixia Shi 
Date:   Thu Apr  7 11:05:08 2016 -0700

dri/i965: extend GLES3 sRGB workaround to cover all formats

It is incorrect to assume BGRA byte order for the GLES3 sRGB workaround.

v2: use _mesa_get_srgb_format_linear to handle all formats

Signed-off-by: Haixia Shi 
Reviewed-by: Stéphane Marchesin 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_context.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 2d480d0..63ac3bc 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1151,10 +1151,9 @@ intel_gles3_srgb_workaround(struct brw_context *brw,
 */
fb->Visual.sRGBCapable = false;
for (int i = 0; i < BUFFER_COUNT; i++) {
-  if (fb->Attachment[i].Renderbuffer &&
-  fb->Attachment[i].Renderbuffer->Format == MESA_FORMAT_B8G8R8A8_SRGB) 
{
- fb->Attachment[i].Renderbuffer->Format = MESA_FORMAT_B8G8R8A8_UNORM;
-  }
+  struct gl_renderbuffer *rb = fb->Attachment[i].Renderbuffer;
+  if (rb)
+ rb->Format = _mesa_get_srgb_format_linear(rb->Format);
}
 }
 

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Mesa (master): i965: Add autogenerated 'brw_nir_trig_workarounds.c' to gitignore

2016-04-12 Thread Eduardo Lima Mitev

Module: Mesa
Branch: master
Commit: ea8a65f503f05404d923a2a076064c3ffe6660aa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea8a65f503f05404d923a2a076064c3ffe6660aa

Author: Eduardo Lima Mitev 
Date:   Tue Apr 12 10:11:35 2016 +0200

i965: Add autogenerated 'brw_nir_trig_workarounds.c' to gitignore

Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/.gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/.gitignore 
b/src/mesa/drivers/dri/i965/.gitignore
index 8eb9f4e..70aae3f 100644
--- a/src/mesa/drivers/dri/i965/.gitignore
+++ b/src/mesa/drivers/dri/i965/.gitignore
@@ -1,3 +1,4 @@
+brw_nir_trig_workarounds.c
 i965_symbols_test
 test_eu_compact
 test_vec4_copy_propagation

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Mesa (master): glsl: Update hash table comments in constant propagation

2016-04-12 Thread Kenneth Graunke

Module: Mesa
Branch: master
Commit: 703c1e69d89df303e5fb4c1873f9b3954bdeda9c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=703c1e69d89df303e5fb4c1873f9b3954bdeda9c

Author: Rhys Kidd 
Date:   Sun Apr 10 20:43:25 2016 -0400

glsl: Update hash table comments in constant propagation

Signed-off-by: Rhys Kidd 
Reviewed-by: Kenneth Graunke 

---

 src/compiler/glsl/opt_constant_propagation.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/compiler/glsl/opt_constant_propagation.cpp 
b/src/compiler/glsl/opt_constant_propagation.cpp
index 416ba16..4764d16 100644
--- a/src/compiler/glsl/opt_constant_propagation.cpp
+++ b/src/compiler/glsl/opt_constant_propagation.cpp
@@ -122,7 +122,7 @@ public:
exec_list *acp;
 
/**
-* List of kill_entry: The masks of variables whose values were
+* Hash table of kill_entry: The masks of variables whose values were
 * killed in this block.
 */
hash_table *kills;
@@ -454,7 +454,7 @@ ir_constant_propagation_visitor::kill(ir_variable *var, 
unsigned write_mask)
   }
}
 
-   /* Add this writemask of the variable to the list of killed
+   /* Add this writemask of the variable to the hash table of killed
 * variables in this block.
 */
hash_entry *kill_hash_entry = _mesa_hash_table_search(this->kills, var);
@@ -463,7 +463,7 @@ ir_constant_propagation_visitor::kill(ir_variable *var, 
unsigned write_mask)
   entry->write_mask |= write_mask;
   return;
}
-   /* Not already in the list.  Make new entry. */
+   /* Not already in the hash table.  Make new entry. */
_mesa_hash_table_insert(this->kills, var,
new(this->mem_ctx) kill_entry(var, write_mask));
 }

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