Mesa (master): isl: Fix some tautological-compare warnings

[Ben Widawsky]

Module: Mesa
Branch: master
Commit: 8314dd7ff2c4719ffb64b202cf5fdd0e38ad276e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8314dd7ff2c4719ffb64b202cf5fdd0e38ad276e

Author: Ben Widawsky 
Date:   Thu May 26 21:59:17 2016 -0700

isl: Fix some tautological-compare warnings

Fixes:
isl.c:62:22: warning: self-comparison always evaluates to true 
[-Wtautological-compare]
assert(ISL_DEV_GEN(dev) == dev->info->gen);
  ^~
isl.c:63:33: warning: self-comparison always evaluates to true 
[-Wtautological-compare]
assert(ISL_DEV_USE_SEPARATE_STENCIL(dev) == dev->use_separate_stencil);

Signed-off-by: Ben Widawsky 
Reviewed-by: Anuj Phogat 

---

 src/intel/isl/isl.c | 4 ++--
 src/intel/isl/isl.h | 8 
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index e4bca16..77b570d 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -59,8 +59,8 @@ isl_device_init(struct isl_device *dev,
 * device properties at buildtime. Verify that the macros with the device
 * properties chosen during runtime.
 */
-   assert(ISL_DEV_GEN(dev) == dev->info->gen);
-   assert(ISL_DEV_USE_SEPARATE_STENCIL(dev) == dev->use_separate_stencil);
+   ISL_DEV_GEN_SANITIZE(dev);
+   ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev);
 
/* Did we break hiz or stencil? */
if (ISL_DEV_USE_SEPARATE_STENCIL(dev))
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index daa5428..ef86228 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -59,6 +59,10 @@ struct brw_image_param;
  * `gcc -DISL_DEV_GEN(dev)=9 ...`.
  */
 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
+#define ISL_DEV_GEN_SANITIZE(__dev)
+#else
+#define ISL_DEV_GEN_SANITIZE(__dev) \
+   (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
 #endif
 
 #ifndef ISL_DEV_IS_HASWELL
@@ -77,6 +81,10 @@ struct brw_image_param;
  * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
  */
 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
+#define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
+#else
+#define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
+   (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == 
(__dev)->use_separate_stencil))
 #endif
 
 /**

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Mesa (master): mapi: expose new functions in GL ES 3.2

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: faae9ab2eeed28037f645fd66e68e4b9ff08b8e8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=faae9ab2eeed28037f645fd66e68e4b9ff08b8e8

Author: Ilia Mirkin 
Date:   Thu May 26 13:58:41 2016 -0400

mapi: expose new functions in GL ES 3.2

Signed-off-by: Ilia Mirkin 
Reviewed-by: Anuj Phogat 

---

 src/mapi/glapi/gen/ARB_copy_image.xml|  2 +-
 src/mapi/glapi/gen/ARB_sampler_objects.xml   |  8 
 src/mapi/glapi/gen/ARB_tessellation_shader.xml   |  2 +-
 src/mapi/glapi/gen/ARB_texture_buffer_range.xml  |  2 +-
 .../glapi/gen/ARB_texture_storage_multisample.xml|  2 +-
 src/mapi/glapi/gen/GL3x.xml  | 20 ++--
 src/mapi/glapi/gen/GL4x.xml  | 10 +-
 src/mapi/glapi/gen/KHR_debug.xml | 20 ++--
 src/mapi/glapi/gen/KHR_robustness.xml| 10 +-
 9 files changed, 38 insertions(+), 38 deletions(-)

diff --git a/src/mapi/glapi/gen/ARB_copy_image.xml 
b/src/mapi/glapi/gen/ARB_copy_image.xml
index af672cd..9ee2ba3 100644
--- a/src/mapi/glapi/gen/ARB_copy_image.xml
+++ b/src/mapi/glapi/gen/ARB_copy_image.xml
@@ -5,7 +5,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/mapi/glapi/gen/ARB_sampler_objects.xml 
b/src/mapi/glapi/gen/ARB_sampler_objects.xml
index bc69e97..20363f7 100644
--- a/src/mapi/glapi/gen/ARB_sampler_objects.xml
+++ b/src/mapi/glapi/gen/ARB_sampler_objects.xml
@@ -51,13 +51,13 @@
   
 
 
-
+
   
   
   
 
 
-
+
   
   
   
@@ -75,13 +75,13 @@
   
 
 
-
+
   
   
   
 
 
-
+
   
   
   
diff --git a/src/mapi/glapi/gen/ARB_tessellation_shader.xml 
b/src/mapi/glapi/gen/ARB_tessellation_shader.xml
index 5ffc2ba..cc55f9b 100644
--- a/src/mapi/glapi/gen/ARB_tessellation_shader.xml
+++ b/src/mapi/glapi/gen/ARB_tessellation_shader.xml
@@ -50,7 +50,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/mapi/glapi/gen/ARB_texture_buffer_range.xml 
b/src/mapi/glapi/gen/ARB_texture_buffer_range.xml
index 36bcc49..93ed534 100644
--- a/src/mapi/glapi/gen/ARB_texture_buffer_range.xml
+++ b/src/mapi/glapi/gen/ARB_texture_buffer_range.xml
@@ -9,7 +9,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/mapi/glapi/gen/ARB_texture_storage_multisample.xml 
b/src/mapi/glapi/gen/ARB_texture_storage_multisample.xml
index 6ed8f1a..d1dd2f9 100644
--- a/src/mapi/glapi/gen/ARB_texture_storage_multisample.xml
+++ b/src/mapi/glapi/gen/ARB_texture_storage_multisample.xml
@@ -16,7 +16,7 @@
   

 
-   
+   
   
   
   
diff --git a/src/mapi/glapi/gen/GL3x.xml b/src/mapi/glapi/gen/GL3x.xml
index 7241c66..6b91945 100644
--- a/src/mapi/glapi/gen/GL3x.xml
+++ b/src/mapi/glapi/gen/GL3x.xml
@@ -156,7 +156,7 @@
 
   
 
-  
+  
 
 
 
@@ -176,17 +176,17 @@
 
   
 
-  
+  
 
 
   
 
-  
+  
 
 
   
 
-  
+  
 
 
   
@@ -446,25 +446,25 @@
 
   
 
-  
+  
 
 
 
   
 
-  
+  
 
 
 
   
 
-  
+  
 
 
 
   
 
-  
+  
 
 
 
@@ -555,7 +555,7 @@
 
   
 
-  
+  
 
 
 
@@ -605,7 +605,7 @@
 
   
 
-  
+  
 
 
 
diff --git a/src/mapi/glapi/gen/GL4x.xml b/src/mapi/glapi/gen/GL4x.xml
index dd48c83..53b7789 100644
--- a/src/mapi/glapi/gen/GL4x.xml
+++ b/src/mapi/glapi/gen/GL4x.xml
@@ -9,17 +9,17 @@
   
   
 
-  
+  
 
   
 
-  
+  
 
 
 
   
 
-  
+  
 
 
 
@@ -27,12 +27,12 @@
 
   
 
-  
+  
 
 
   
 
-  
+  
 
 
 
diff --git a/src/mapi/glapi/gen/KHR_debug.xml b/src/mapi/glapi/gen/KHR_debug.xml
index 50daba3..21b7e58 100644
--- a/src/mapi/glapi/gen/KHR_debug.xml
+++ b/src/mapi/glapi/gen/KHR_debug.xml
@@ -73,7 +73,7 @@
   
   
 
-  
+  
 
 
 
@@ -82,7 +82,7 @@
 
   
 
-  
+  
 
 
 
@@ -91,12 +91,12 @@
 
   
 
-  
+  
 
 
   
 
-  
+  
 
 
 
@@ -108,23 +108,23 @@
 
   
 
-  
+  
 
 
 
 
   
 
-  
+  
 
-  
+  
 
 
 
 
   
 
-  
+  
 
 
 
@@ -132,13 +132,13 @@
 
   
 
-  
+  
 
 
 
   
 
-  
+  
 
 
 
diff --git a/src/mapi/glapi/gen/KHR_robustness.xml 
b/src/mapi/glapi/gen/KHR_robustness.xml
index 56bcfcc..e773501 100644
--- a/src/mapi/glapi/gen/KHR_robustness.xml
+++ b/src/mapi/glapi/gen/KHR_robustness.xml
@@ -25,11 +25,11 @@
  defines entry points for GL. -->
 
 
-
+
 
 
 
-
+
 
 
 
@@ -40,21 +40,21 @@
 
 
 
-
+
 
 
 
 
 
 
-
+
 
 
 
 
 
 
-
+
 
 
 

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Mesa (master): mesa: add support for GLSL ES 3.20 version string

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 4ccf8c952abb471f94d6f40786d896723f94c0ea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4ccf8c952abb471f94d6f40786d896723f94c0ea

Author: Ilia Mirkin 
Date:   Thu May 26 13:58:42 2016 -0400

mesa: add support for GLSL ES 3.20 version string

Signed-off-by: Ilia Mirkin 
Reviewed-by: Anuj Phogat 

---

 src/mesa/main/getstring.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/main/getstring.c b/src/mesa/main/getstring.c
index c39a076..6e90511 100644
--- a/src/mesa/main/getstring.c
+++ b/src/mesa/main/getstring.c
@@ -80,6 +80,8 @@ shading_language_version(struct gl_context *ctx)
  return (const GLubyte *) "OpenGL ES GLSL ES 3.00";
   case 31:
  return (const GLubyte *) "OpenGL ES GLSL ES 3.10";
+  case 32:
+ return (const GLubyte *) "OpenGL ES GLSL ES 3.20";
   default:
  _mesa_problem(ctx,
"Invalid OpenGL ES version in 
shading_language_version()");

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Mesa (master): nvc0/ir: handle a load' s reg result not being used for locked variants

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: df2881381ac67c42aa8ec9e0ed28f21a1d253785
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=df2881381ac67c42aa8ec9e0ed28f21a1d253785

Author: Ilia Mirkin 
Date:   Wed May 25 22:41:06 2016 -0400

nvc0/ir: handle a load's reg result not being used for locked variants

For a load locked, we might not use the first result but the second
result is the predicate result of the locking. In that case the load
splitting logic doesn't apply (which is designed for splitting 128-bit
loads). Instead we take the predicate and move it into the first
position (as having a dead result in first def's position upsets all
sorts of things including RA). Update the emitters to deal with this as
well.

Signed-off-by: Ilia Mirkin 
Tested-by: Dave Airlie 
Reviewed-by: Samuel Pitoiset 

---

 .../drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 20 ++---
 .../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp  | 26 +-
 .../drivers/nouveau/codegen/nv50_ir_peephole.cpp   | 10 +++--
 3 files changed, 45 insertions(+), 11 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
index 6a5981d..27d9b8e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
@@ -2080,15 +2080,29 @@ CodeEmitterGK110::emitLOAD(const Instruction *i)
code[1] |= offset >> 9;
 
// Locked store on shared memory can fail.
+   int r = 0, p = -1;
if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
-  assert(i->defExists(1));
-  defId(i->def(1), 32 + 16);
+  if (i->def(0).getFile() == FILE_PREDICATE) { // p, #
+ r = -1;
+ p = 0;
+  } else if (i->defExists(1)) { // r, p
+ p = 1;
+  } else {
+ assert(!"Expected predicate dest for load locked");
+  }
}
 
emitPredicate(i);
 
-   defId(i->def(0), 2);
+   if (r >= 0)
+  defId(i->def(r), 2);
+   else
+  code[0] |= 255 << 2;
+
+   if (p >= 0)
+  defId(i->def(p), 32 + 16);
+
if (i->getIndirect(0, 0)) {
   srcId(i->src(0).getIndirect(0), 10);
   if (i->getIndirect(0, 0)->reg.size == 8)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index 596293e..1bb962f 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -1874,17 +1874,31 @@ CodeEmitterNVC0::emitLOAD(const Instruction *i)
}
code[1] = opc;
 
+   int r = 0, p = -1;
if (i->src(0).getFile() == FILE_MEMORY_SHARED) {
   if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
- assert(i->defExists(1));
- if (targ->getChipset() >= NVISA_GK104_CHIPSET)
-defId(i->def(1), 8);
- else
-defId(i->def(1), 32 + 18);
+ if (i->def(0).getFile() == FILE_PREDICATE) { // p, #
+r = -1;
+p = 0;
+ } else if (i->defExists(1)) { // r, p
+p = 1;
+ } else {
+assert(!"Expected predicate dest for load locked");
+ }
   }
}
 
-   defId(i->def(0), 14);
+   if (r >= 0)
+  defId(i->def(r), 14);
+   else
+  code[0] |= 63 << 14;
+
+   if (p >= 0) {
+  if (targ->getChipset() >= NVISA_GK104_CHIPSET)
+ defId(i->def(p), 8);
+  else
+ defId(i->def(p), 32 + 18);
+   }
 
setAddressByFile(i->src(0));
srcId(i->src(0).getIndirect(0), 20);
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index cd801f3..3213188 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -3265,14 +3265,20 @@ DeadCodeElim::visit(BasicBlock *bb)
  ++deadCount;
  delete_Instruction(prog, i);
   } else
-  if (i->defExists(1) && (i->op == OP_VFETCH || i->op == OP_LOAD)) {
+  if (i->defExists(1) &&
+  i->subOp == 0 &&
+  (i->op == OP_VFETCH || i->op == OP_LOAD)) {
  checkSplitLoad(i);
   } else
   if (i->defExists(0) && !i->getDef(0)->refCount()) {
  if (i->op == OP_ATOM ||
  i->op == OP_SUREDP ||
- i->op == OP_SUREDB)
+ i->op == OP_SUREDB) {
 i->setDef(0, NULL);
+ } else if (i->op == OP_LOAD && i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) 
{
+i->setDef(0, i->getDef(1));
+i->setDef(1, NULL);
+ }
   }
}
return true;

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Mesa (master): nvc0/ir: avoid generating illegal instructions for compute constbuf loads

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 04ecad97ff7b44bd9afd1bff9108dea199723829
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=04ecad97ff7b44bd9afd1bff9108dea199723829

Author: Ilia Mirkin 
Date:   Wed May 25 21:54:39 2016 -0400

nvc0/ir: avoid generating illegal instructions for compute constbuf loads

For user-supplied constbufs, fileIndex is 0. In that case, when we
subtract 1, we'll end up loading from constbuf offset -16. This is
illegal, and there are asserts to avoid it. Normally we'd just DCE it,
but no point in generating the instructions if they're not going to be
used.

Signed-off-by: Ilia Mirkin 
Acked-by: Hans de Goede 
Reviewed-by: Samuel Pitoiset 

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 869040c..da2fa4b 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -2180,11 +2180,11 @@ NVC0LoweringPass::handleLDST(Instruction *i)
  // memory.
  int8_t fileIndex = i->getSrc(0)->reg.fileIndex - 1;
  Value *ind = i->getIndirect(0, 1);
- Value *ptr = loadUboInfo64(ind, fileIndex * 16);
 
  // TODO: clamp the offset to the maximum number of const buf.
  if (i->src(0).isIndirect(1)) {
 Value *offset = bld.loadImm(NULL, i->getSrc(0)->reg.data.offset + 
typeSizeof(i->sType));
+Value *ptr = loadUboInfo64(ind, fileIndex * 16);
 Value *length = loadUboLength32(ind, fileIndex * 16);
 Value *pred = new_LValue(func, FILE_PREDICATE);
 if (i->src(0).isIndirect(0)) {
@@ -2200,6 +2200,7 @@ NVC0LoweringPass::handleLDST(Instruction *i)
bld.mkMov(i->getDef(0), bld.mkImm(0));
 }
  } else if (fileIndex >= 0) {
+Value *ptr = loadUboInfo64(ind, fileIndex * 16);
 if (i->src(0).isIndirect(0)) {
bld.mkOp2(OP_ADD, TYPE_U64, ptr, ptr, i->getIndirect(0, 0));
 }

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Mesa (master): gallium/util: fix build break

[Rob Clark]

Module: Mesa
Branch: master
Commit: 4f98c94be7e56a535a6b84a5561ae071e052c1e2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f98c94be7e56a535a6b84a5561ae071e052c1e2

Author: Rob Clark 
Date:   Thu May 26 20:59:08 2016 -0400

gallium/util: fix build break

Missing #include caused build breaks after 21a3fb9cd.

Signed-off-by: Rob Clark 

---

 src/gallium/auxiliary/util/u_upload_mgr.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/auxiliary/util/u_upload_mgr.h 
b/src/gallium/auxiliary/util/u_upload_mgr.h
index 6c70723..b36e9e5 100644
--- a/src/gallium/auxiliary/util/u_upload_mgr.h
+++ b/src/gallium/auxiliary/util/u_upload_mgr.h
@@ -33,6 +33,7 @@
 #define U_UPLOAD_MGR_H
 
 #include "pipe/p_compiler.h"
+#include "pipe/p_defines.h"
 
 struct pipe_context;
 struct pipe_resource;

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Mesa (master): nir/spirv: Allow pointless variable decorations on inputs

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 9f9f229359a7c850bd5a24945f3445e611267789
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f9f229359a7c850bd5a24945f3445e611267789

Author: Jason Ekstrand 
Date:   Thu May 26 17:06:17 2016 -0700

nir/spirv: Allow pointless variable decorations on inputs

SPIR-V specifies that a bunch of stuff gets applied to types.  This means
taht a local variable could get, for instance, an array stride.  Just
because it's pointless doesn't mean you'll never see it.

---

 src/compiler/spirv/vtn_variables.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index 8abd8ee..812ac62 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1050,6 +1050,8 @@ var_decoration_cb(struct vtn_builder *b, struct vtn_value 
*val, int member,
case SpvDecorationArrayStride:
case SpvDecorationGLSLShared:
case SpvDecorationGLSLPacked:
+  break; /* These can apply to a type but we don't care about them */
+
case SpvDecorationBinding:
case SpvDecorationDescriptorSet:
case SpvDecorationNoContraction:

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Mesa (master): svga: clean up and improve comments in svga_draw_private.h

[Brian Paul]

Module: Mesa
Branch: master
Commit: 2c07c40d2f65e3c7ac25db21b247e647c846edcf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c07c40d2f65e3c7ac25db21b247e647c846edcf

Author: Brian Paul 
Date:   Wed May 25 09:46:17 2016 -0600

svga: clean up and improve comments in svga_draw_private.h

Reviewed-by: Charmaine Lee 

---

 src/gallium/drivers/svga/svga_draw_private.h | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_draw_private.h 
b/src/gallium/drivers/svga/svga_draw_private.h
index c821742..48e0b60 100644
--- a/src/gallium/drivers/svga/svga_draw_private.h
+++ b/src/gallium/drivers/svga/svga_draw_private.h
@@ -157,13 +157,17 @@ struct svga_hwtnl {
 * This is compensated for in the offset associated with all
 * vertex buffers.
 */
-
int index_bias;

-   /* Flatshade information:
+   /* Provoking vertex information (for flat shading). */
+   unsigned api_pv;  /**< app-requested PV mode (PV_FIRST or PV_LAST) */
+   unsigned hw_pv;   /**< device-supported PV mode (PV_FIRST or PV_LAST) */
+
+   /* The triangle fillmode for the device (one of PIPE_POLYGON_MODE_{FILL,
+* LINE,POINT}).  If the polygon front mode matches the back mode,
+* api_fillmode will be that mode.  Otherwise, api_fillmode will be
+* PIPE_POLYGON_MODE_FILL.
 */
-   unsigned api_pv;
-   unsigned hw_pv;
unsigned api_fillmode;
 
/* Cache the results of running a particular generate func on each

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Mesa (master): gallium/util: use enum pipe_prim_type in u_prim.h functions

[Brian Paul]

Module: Mesa
Branch: master
Commit: 1ec45a1948548ee26d55b6e5dfab1559f7f0a8ce
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1ec45a1948548ee26d55b6e5dfab1559f7f0a8ce

Author: Brian Paul 
Date:   Thu May 26 14:50:13 2016 -0600

gallium/util: use enum pipe_prim_type in u_prim.h functions

Reviewed-by: Roland Scheidegger 

---

 src/gallium/auxiliary/util/u_prim.h | 30 --
 1 file changed, 16 insertions(+), 14 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_prim.h 
b/src/gallium/auxiliary/util/u_prim.h
index a09c315..fb9290d 100644
--- a/src/gallium/auxiliary/util/u_prim.h
+++ b/src/gallium/auxiliary/util/u_prim.h
@@ -46,8 +46,8 @@ struct u_prim_vertex_count {
  * Decompose a primitive that is a loop, a strip, or a fan.  Return the
  * original primitive if it is already decomposed.
  */
-static inline unsigned
-u_decomposed_prim(unsigned prim)
+static inline enum pipe_prim_type
+u_decomposed_prim(enum pipe_prim_type prim)
 {
switch (prim) {
case PIPE_PRIM_LINE_LOOP:
@@ -71,8 +71,8 @@ u_decomposed_prim(unsigned prim)
  * Reduce a primitive to one of PIPE_PRIM_POINTS, PIPE_PRIM_LINES, and
  * PIPE_PRIM_TRIANGLES.
  */
-static inline unsigned
-u_reduced_prim(unsigned prim)
+static inline enum pipe_prim_type
+u_reduced_prim(enum pipe_prim_type prim)
 {
switch (prim) {
case PIPE_PRIM_POINTS:
@@ -91,8 +91,8 @@ u_reduced_prim(unsigned prim)
 /**
  * Re-assemble a primitive to remove its adjacency.
  */
-static inline unsigned
-u_assembled_prim(unsigned prim)
+static inline enum pipe_prim_type
+u_assembled_prim(enum pipe_prim_type prim)
 {
switch (prim) {
case PIPE_PRIM_LINES_ADJACENCY:
@@ -114,7 +114,7 @@ u_assembled_prim(unsigned prim)
  * expected because of the use of a table.
  */
 static inline const struct u_prim_vertex_count *
-u_prim_vertex_count(unsigned prim)
+u_prim_vertex_count(enum pipe_prim_type prim)
 {
static const struct u_prim_vertex_count prim_table[PIPE_PRIM_MAX] = {
   { 1, 1 }, /* PIPE_PRIM_POINTS */
@@ -141,7 +141,7 @@ u_prim_vertex_count(unsigned prim)
  * For polygons, return the number of triangles.
  */
 static inline unsigned
-u_prims_for_vertices(unsigned prim, unsigned num)
+u_prims_for_vertices(enum pipe_prim_type prim, unsigned num)
 {
const struct u_prim_vertex_count *info = u_prim_vertex_count(prim);
 
@@ -154,7 +154,8 @@ u_prims_for_vertices(unsigned prim, unsigned num)
return 1 + ((num - info->min) / info->incr);
 }
 
-static inline boolean u_validate_pipe_prim( unsigned pipe_prim, unsigned nr )
+static inline boolean
+u_validate_pipe_prim(enum pipe_prim_type pipe_prim, unsigned nr)
 {
const struct u_prim_vertex_count *count = u_prim_vertex_count(pipe_prim);
 
@@ -162,7 +163,8 @@ static inline boolean u_validate_pipe_prim( unsigned 
pipe_prim, unsigned nr )
 }
 
 
-static inline boolean u_trim_pipe_prim( unsigned pipe_prim, unsigned *nr )
+static inline boolean
+u_trim_pipe_prim(enum pipe_prim_type pipe_prim, unsigned *nr)
 {
const struct u_prim_vertex_count *count = u_prim_vertex_count(pipe_prim);
 
@@ -178,7 +180,7 @@ static inline boolean u_trim_pipe_prim( unsigned pipe_prim, 
unsigned *nr )
 }
 
 static inline unsigned
-u_vertices_per_prim(int primitive)
+u_vertices_per_prim(enum pipe_prim_type primitive)
 {
switch(primitive) {
case PIPE_PRIM_POINTS:
@@ -220,7 +222,7 @@ u_vertices_per_prim(int primitive)
  * primitives for a set of vertices.
  */
 static inline unsigned
-u_decomposed_prims_for_vertices(int primitive, int vertices)
+u_decomposed_prims_for_vertices(enum pipe_prim_type primitive, int vertices)
 {
switch (primitive) {
case PIPE_PRIM_POINTS:
@@ -267,7 +269,7 @@ u_decomposed_prims_for_vertices(int primitive, int vertices)
  * triangle fans.
  */
 static inline unsigned
-u_reduced_prims_for_vertices(int primitive, int vertices)
+u_reduced_prims_for_vertices(enum pipe_prim_type primitive, int vertices)
 {
switch (primitive) {
case PIPE_PRIM_QUADS:
@@ -281,7 +283,7 @@ u_reduced_prims_for_vertices(int primitive, int vertices)
}
 }
 
-const char *u_prim_name( unsigned pipe_prim );
+const char *u_prim_name(enum pipe_prim_type pipe_prim);
 
 
 #ifdef __cplusplus

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Mesa (master): util/indices: improve comments in u_indices.h

[Brian Paul]

Module: Mesa
Branch: master
Commit: 24eadb4810be963e0a4473e071548313686ad5cb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=24eadb4810be963e0a4473e071548313686ad5cb

Author: Brian Paul 
Date:   Fri May 13 16:45:25 2016 -0600

util/indices: improve comments in u_indices.h

Reviewed-by: Roland Scheidegger 

---

 src/gallium/auxiliary/indices/u_indices.h | 32 ---
 1 file changed, 29 insertions(+), 3 deletions(-)

diff --git a/src/gallium/auxiliary/indices/u_indices.h 
b/src/gallium/auxiliary/indices/u_indices.h
index 4483eb8..7f696ab 100644
--- a/src/gallium/auxiliary/indices/u_indices.h
+++ b/src/gallium/auxiliary/indices/u_indices.h
@@ -27,6 +27,7 @@
 
 #include "pipe/p_compiler.h"
 
+/* First/last provoking vertex */
 #define PV_FIRST  0
 #define PV_LAST   1
 #define PV_COUNT  2
@@ -35,13 +36,15 @@
 #define PR_DISABLE 0
 #define PR_ENABLE 1
 #define PR_COUNT 2
+
+
 /**
  * Index translator function (for glDrawElements() case)
  *
  * \param in the input index buffer
  * \param start  the index of the first vertex (pipe_draw_info::start)
  * \param nr the number of vertices (pipe_draw_info::count)
- * \param outoutput buffer big enough or nr vertices (of
+ * \param outoutput buffer big enough for nr vertices (of
  *@out_index_size bytes each)
  */
 typedef void (*u_translate_func)( const void *in,
@@ -56,7 +59,7 @@ typedef void (*u_translate_func)( const void *in,
  *
  * \param start  the index of the first vertex (pipe_draw_info::start)
  * \param nr the number of vertices (pipe_draw_info::count)
- * \param outoutput buffer big enough or nr vertices (of
+ * \param outoutput buffer big enough for nr vertices (of
  *@out_index_size bytes each)
  */
 typedef void (*u_generate_func)( unsigned start,
@@ -78,6 +81,15 @@ enum indices_mode {
 
 void u_index_init( void );
 
+
+/**
+ * For indexed drawing, this function determines what kind of primitive
+ * transformation is needed (if any) for handling:
+ * - unsupported primitive types (such as PIPE_PRIM_POLYGON)
+ * - changing the provoking vertex
+ * - primitive restart
+ * - index size (1 byte, 2 byte or 4 byte indexes)
+ */
 enum indices_mode
 u_index_translator(unsigned hw_mask,
unsigned prim,
@@ -91,7 +103,12 @@ u_index_translator(unsigned hw_mask,
unsigned *out_nr,
u_translate_func *out_translate);
 
-/* Note that even when generating it is necessary to know what the
+
+/**
+ * For non-indexed drawing, this function determines what kind of primitive
+ * transformation is needed (see above).
+ *
+ * Note that even when generating it is necessary to know what the
  * API's PV is, as the indices generated will depend on whether it is
  * the same as hardware or not, and in the case of triangle strips,
  * whether it is first or last.
@@ -111,6 +128,12 @@ u_index_generator(unsigned hw_mask,
 
 void u_unfilled_init( void );
 
+/**
+ * If the driver can't handle "unfilled" primitives (i.e. drawing triangle
+ * primitives as 3 lines or 3 points) this function can be used to translate
+ * an indexed primitive into a new indexed primitive to draw as lines or
+ * points.
+ */
 enum indices_mode
 u_unfilled_translator(unsigned prim,
   unsigned in_index_size,
@@ -121,6 +144,9 @@ u_unfilled_translator(unsigned prim,
   unsigned *out_nr,
   u_translate_func *out_translate);
 
+/**
+ * As above, but for non-indexed (array) primitives.
+ */
 enum indices_mode
 u_unfilled_generator(unsigned prim,
  unsigned start,

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Mesa (master): svga: s/unsigned/enum pipe_prim_type/ for primitive type variables

[Brian Paul]

Module: Mesa
Branch: master
Commit: d21a309c6c00122b0562284d78fce5138fa2ad30
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d21a309c6c00122b0562284d78fce5138fa2ad30

Author: Brian Paul 
Date:   Wed May 25 16:52:34 2016 -0600

svga: s/unsigned/enum pipe_prim_type/ for primitive type variables

Proper enum types were only added recently.

Reviewed-by: Roland Scheidegger 

---

 src/gallium/drivers/svga/svga_draw.h  | 4 ++--
 src/gallium/drivers/svga/svga_draw_arrays.c   | 6 +++---
 src/gallium/drivers/svga/svga_draw_elements.c | 6 +++---
 src/gallium/drivers/svga/svga_draw_private.h  | 5 +++--
 src/gallium/drivers/svga/svga_pipe_draw.c | 4 ++--
 src/gallium/drivers/svga/svga_swtnl_backend.c | 2 +-
 src/gallium/drivers/svga/svga_swtnl_private.h | 2 +-
 7 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_draw.h 
b/src/gallium/drivers/svga/svga_draw.h
index af8ecab..baefcd9 100644
--- a/src/gallium/drivers/svga/svga_draw.h
+++ b/src/gallium/drivers/svga/svga_draw.h
@@ -59,7 +59,7 @@ svga_hwtnl_vertex_buffers(struct svga_hwtnl *hwtnl,
 
 enum pipe_error
 svga_hwtnl_draw_arrays(struct svga_hwtnl *hwtnl,
-   unsigned prim, unsigned start, unsigned count,
+   enum pipe_prim_type prim, unsigned start, unsigned 
count,
unsigned start_instance, unsigned instance_count);
 
 enum pipe_error
@@ -69,7 +69,7 @@ svga_hwtnl_draw_range_elements(struct svga_hwtnl *hwtnl,
int index_bias,
unsigned min_index,
unsigned max_index,
-   unsigned prim, unsigned start, unsigned count,
+   enum pipe_prim_type prim, unsigned start, 
unsigned count,
unsigned start_instance, unsigned 
instance_count);
 
 boolean
diff --git a/src/gallium/drivers/svga/svga_draw_arrays.c 
b/src/gallium/drivers/svga/svga_draw_arrays.c
index 43d7a97..4bd1a33 100644
--- a/src/gallium/drivers/svga/svga_draw_arrays.c
+++ b/src/gallium/drivers/svga/svga_draw_arrays.c
@@ -90,7 +90,7 @@ compare(unsigned cached_nr, unsigned nr, unsigned type)
 
 static enum pipe_error
 retrieve_or_generate_indices(struct svga_hwtnl *hwtnl,
- unsigned prim,
+ enum pipe_prim_type prim,
  unsigned gen_type,
  unsigned gen_nr,
  unsigned gen_size,
@@ -170,7 +170,7 @@ retrieve_or_generate_indices(struct svga_hwtnl *hwtnl,
 
 static enum pipe_error
 simple_draw_arrays(struct svga_hwtnl *hwtnl,
-   unsigned prim, unsigned start, unsigned count,
+   enum pipe_prim_type prim, unsigned start, unsigned count,
unsigned start_instance, unsigned instance_count)
 {
SVGA3dPrimitiveRange range;
@@ -202,7 +202,7 @@ simple_draw_arrays(struct svga_hwtnl *hwtnl,
 
 enum pipe_error
 svga_hwtnl_draw_arrays(struct svga_hwtnl *hwtnl,
-   unsigned prim, unsigned start, unsigned count,
+   enum pipe_prim_type prim, unsigned start, unsigned 
count,
unsigned start_instance, unsigned instance_count)
 {
unsigned gen_prim, gen_size, gen_nr;
diff --git a/src/gallium/drivers/svga/svga_draw_elements.c 
b/src/gallium/drivers/svga/svga_draw_elements.c
index b74c745..6eb5067 100644
--- a/src/gallium/drivers/svga/svga_draw_elements.c
+++ b/src/gallium/drivers/svga/svga_draw_elements.c
@@ -39,7 +39,7 @@
 
 static enum pipe_error
 translate_indices(struct svga_hwtnl *hwtnl, struct pipe_resource *src,
-  unsigned offset, unsigned prim, unsigned nr,
+  unsigned offset, enum pipe_prim_type prim, unsigned nr,
   unsigned index_size,
   u_translate_func translate, struct pipe_resource **out_buf)
 {
@@ -98,7 +98,7 @@ svga_hwtnl_simple_draw_range_elements(struct svga_hwtnl 
*hwtnl,
   struct pipe_resource *index_buffer,
   unsigned index_size, int index_bias,
   unsigned min_index, unsigned max_index,
-  unsigned prim, unsigned start,
+  enum pipe_prim_type prim, unsigned start,
   unsigned count,
   unsigned start_instance,
   unsigned instance_count)
@@ -130,7 +130,7 @@ svga_hwtnl_draw_range_elements(struct svga_hwtnl *hwtnl,
struct pipe_resource *index_buffer,
unsigned index_size, int index_bias,
unsigned min_index, unsigned max_index,
-   unsigned prim, 

Mesa (master): util/indices,svga: s/unsigned/enum pipe_prim_type/

[Brian Paul]

Module: Mesa
Branch: master
Commit: a25ae485a6ae17fa78ffa51c3e4c08823cfffd88
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a25ae485a6ae17fa78ffa51c3e4c08823cfffd88

Author: Brian Paul 
Date:   Thu May 26 07:12:59 2016 -0600

util/indices,svga: s/unsigned/enum pipe_prim_type/

Reviewed-by: Roland Scheidegger 

---

 src/gallium/auxiliary/indices/u_indices.c  |  6 +++---
 src/gallium/auxiliary/indices/u_indices.h  | 17 +
 src/gallium/auxiliary/indices/u_unfilled_indices.c | 10 +-
 src/gallium/drivers/svga/svga_draw_arrays.c|  3 ++-
 src/gallium/drivers/svga/svga_draw_elements.c  |  3 ++-
 5 files changed, 21 insertions(+), 18 deletions(-)

diff --git a/src/gallium/auxiliary/indices/u_indices.c 
b/src/gallium/auxiliary/indices/u_indices.c
index 2b2d10c..91f00f2 100644
--- a/src/gallium/auxiliary/indices/u_indices.c
+++ b/src/gallium/auxiliary/indices/u_indices.c
@@ -72,7 +72,7 @@ static void translate_memcpy_uint( const void *in,
  */
 enum indices_mode
 u_index_translator(unsigned hw_mask,
-   unsigned prim,
+   enum pipe_prim_type prim,
unsigned in_index_size,
unsigned nr,
unsigned in_pv,
@@ -235,12 +235,12 @@ u_index_translator(unsigned hw_mask,
  */
 enum indices_mode
 u_index_generator(unsigned hw_mask,
-  unsigned prim,
+  enum pipe_prim_type prim,
   unsigned start,
   unsigned nr,
   unsigned in_pv,
   unsigned out_pv,
-  unsigned *out_prim,
+  enum pipe_prim_type *out_prim,
   unsigned *out_index_size,
   unsigned *out_nr,
   u_generate_func *out_generate)
diff --git a/src/gallium/auxiliary/indices/u_indices.h 
b/src/gallium/auxiliary/indices/u_indices.h
index 7f696ab..f160fcb 100644
--- a/src/gallium/auxiliary/indices/u_indices.h
+++ b/src/gallium/auxiliary/indices/u_indices.h
@@ -26,6 +26,7 @@
 #define U_INDICES_H
 
 #include "pipe/p_compiler.h"
+#include "pipe/p_defines.h"
 
 /* First/last provoking vertex */
 #define PV_FIRST  0
@@ -92,13 +93,13 @@ void u_index_init( void );
  */
 enum indices_mode
 u_index_translator(unsigned hw_mask,
-   unsigned prim,
+   enum pipe_prim_type prim,
unsigned in_index_size,
unsigned nr,
unsigned in_pv,   /* API */
unsigned out_pv,  /* hardware */
unsigned prim_restart,
-   unsigned *out_prim,
+   enum pipe_prim_type *out_prim,
unsigned *out_index_size,
unsigned *out_nr,
u_translate_func *out_translate);
@@ -115,12 +116,12 @@ u_index_translator(unsigned hw_mask,
  */
 enum indices_mode
 u_index_generator(unsigned hw_mask,
-  unsigned prim,
+  enum pipe_prim_type prim,
   unsigned start,
   unsigned nr,
   unsigned in_pv,   /* API */
   unsigned out_pv,  /* hardware */
-  unsigned *out_prim,
+  enum pipe_prim_type *out_prim,
   unsigned *out_index_size,
   unsigned *out_nr,
   u_generate_func *out_generate);
@@ -135,11 +136,11 @@ void u_unfilled_init( void );
  * points.
  */
 enum indices_mode
-u_unfilled_translator(unsigned prim,
+u_unfilled_translator(enum pipe_prim_type prim,
   unsigned in_index_size,
   unsigned nr,
   unsigned unfilled_mode,
-  unsigned *out_prim,
+  enum pipe_prim_type *out_prim,
   unsigned *out_index_size,
   unsigned *out_nr,
   u_translate_func *out_translate);
@@ -148,11 +149,11 @@ u_unfilled_translator(unsigned prim,
  * As above, but for non-indexed (array) primitives.
  */
 enum indices_mode
-u_unfilled_generator(unsigned prim,
+u_unfilled_generator(enum pipe_prim_type prim,
  unsigned start,
  unsigned nr,
  unsigned unfilled_mode,
- unsigned *out_prim,
+ enum pipe_prim_type *out_prim,
  unsigned *out_index_size,
  unsigned *out_nr,
  u_generate_func *out_generate);
diff --git a/src/gallium/auxiliary/indices/u_unfilled_indices.c 
b/src/gallium/auxiliary/indices/u_unfilled_indices.c
index 8cb5192..0ca1d04 100644
--- a/src/gallium/auxiliary/indices/u_unfilled_indices.c
+++ b/src/gallium/auxiliary/indices/u_unfilled_indices.c
@@ -95,7 +95,7 @@ static void generate_linear_uint( unsigned start,
  * separate lines (PIPE_PRIM_LINES).
  */
 static unsigned

Mesa (master): svga: s/unsigned/enum pipe_resource_usage/ for buffer usage variables

[Brian Paul]

Module: Mesa
Branch: master
Commit: 45078e8890a6709390007d0fce8d6ed1be5ad5c0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=45078e8890a6709390007d0fce8d6ed1be5ad5c0

Author: Brian Paul 
Date:   Wed May 25 17:13:23 2016 -0600

svga: s/unsigned/enum pipe_resource_usage/ for buffer usage variables

Reviewed-by: Roland Scheidegger 

---

 src/gallium/drivers/svga/svga_resource_buffer.c | 2 +-
 src/gallium/drivers/svga/svga_screen_cache.c| 2 +-
 src/gallium/drivers/svga/svga_screen_cache.h| 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_resource_buffer.c 
b/src/gallium/drivers/svga/svga_resource_buffer.c
index 9ecb975..d91497c 100644
--- a/src/gallium/drivers/svga/svga_resource_buffer.c
+++ b/src/gallium/drivers/svga/svga_resource_buffer.c
@@ -69,7 +69,7 @@ static void *
 svga_buffer_transfer_map(struct pipe_context *pipe,
  struct pipe_resource *resource,
  unsigned level,
- unsigned usage,
+ enum pipe_resource_usage usage,
  const struct pipe_box *box,
  struct pipe_transfer **ptransfer)
 {
diff --git a/src/gallium/drivers/svga/svga_screen_cache.c 
b/src/gallium/drivers/svga/svga_screen_cache.c
index 321c564..eaa589c 100644
--- a/src/gallium/drivers/svga/svga_screen_cache.c
+++ b/src/gallium/drivers/svga/svga_screen_cache.c
@@ -413,7 +413,7 @@ svga_screen_cache_init(struct svga_screen *svgascreen)
  */
 struct svga_winsys_surface *
 svga_screen_surface_create(struct svga_screen *svgascreen,
-   unsigned bind_flags, unsigned usage,
+   unsigned bind_flags, enum pipe_resource_usage usage,
struct svga_host_surface_cache_key *key)
 {
struct svga_winsys_screen *sws = svgascreen->sws;
diff --git a/src/gallium/drivers/svga/svga_screen_cache.h 
b/src/gallium/drivers/svga/svga_screen_cache.h
index 424eb2c..05d8c56 100644
--- a/src/gallium/drivers/svga/svga_screen_cache.h
+++ b/src/gallium/drivers/svga/svga_screen_cache.h
@@ -140,7 +140,7 @@ svga_screen_cache_init(struct svga_screen *svgascreen);
 
 struct svga_winsys_surface *
 svga_screen_surface_create(struct svga_screen *svgascreen,
-   unsigned bind_flags, unsigned usage,
+   unsigned bind_flags, enum pipe_resource_usage usage,
struct svga_host_surface_cache_key *key);
 
 void

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Mesa (master): util/indices: implement unfilled (tri->line) conversion for adjacency prims

[Brian Paul]

Module: Mesa
Branch: master
Commit: 0f983e1793360d98eb8e254755d95d33e2ea8ea2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f983e1793360d98eb8e254755d95d33e2ea8ea2

Author: Brian Paul 
Date:   Wed May 25 11:58:29 2016 -0600

util/indices: implement unfilled (tri->line) conversion for adjacency prims

Tested with new piglit gl-3.2-adj-prims test.

v2: re-order trisadj and tristripadj code, per Roland.

Reviewed-by: Roland Scheidegger 

---

 src/gallium/auxiliary/indices/u_unfilled_gen.py| 26 --
 src/gallium/auxiliary/indices/u_unfilled_indices.c | 14 
 2 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/indices/u_unfilled_gen.py 
b/src/gallium/auxiliary/indices/u_unfilled_gen.py
index 873e781..6b02627 100644
--- a/src/gallium/auxiliary/indices/u_unfilled_gen.py
+++ b/src/gallium/auxiliary/indices/u_unfilled_gen.py
@@ -35,14 +35,18 @@ PRIMS=('tris',
'tristrip', 
'quads', 
'quadstrip', 
-   'polygon')
+   'polygon',
+   'trisadj',
+   'tristripadj')
 
 LONGPRIMS=('PIPE_PRIM_TRIANGLES', 
'PIPE_PRIM_TRIANGLE_FAN', 
'PIPE_PRIM_TRIANGLE_STRIP', 
'PIPE_PRIM_QUADS', 
'PIPE_PRIM_QUAD_STRIP', 
-   'PIPE_PRIM_POLYGON')
+   'PIPE_PRIM_POLYGON',
+   'PIPE_PRIM_TRIANGLES_ADJACENCY',
+   'PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY')
 
 longprim = dict(zip(PRIMS, LONGPRIMS))
 intype_idx = dict(ubyte='IN_UBYTE', ushort='IN_USHORT', uint='IN_UINT')
@@ -194,6 +198,22 @@ def quadstrip(intype, outtype):
 postamble()
 
 
+def trisadj(intype, outtype):
+preamble(intype, outtype, prim='trisadj')
+print '  for (i = start, j = 0; j < out_nr; j+=6, i+=6) { '
+do_tri( intype, outtype, 'out+j',  'i', 'i+2', 'i+4' );
+print '   }'
+postamble()
+
+
+def tristripadj(intype, outtype):
+preamble(intype, outtype, prim='tristripadj')
+print '  for (i = start, j = 0; j < out_nr; j+=6, i+=2) { '
+do_tri( intype, outtype, 'out+j',  'i', 'i+2', 'i+4' );
+print '   }'
+postamble()
+
+
 def emit_funcs():
 for intype in INTYPES:
 for outtype in OUTTYPES:
@@ -203,6 +223,8 @@ def emit_funcs():
 quads(intype, outtype)
 quadstrip(intype, outtype)
 polygon(intype, outtype)
+trisadj(intype, outtype)
+tristripadj(intype, outtype)
 
 def init(intype, outtype, prim):
 if intype == GENERATE:
diff --git a/src/gallium/auxiliary/indices/u_unfilled_indices.c 
b/src/gallium/auxiliary/indices/u_unfilled_indices.c
index 49fff6b..8cb5192 100644
--- a/src/gallium/auxiliary/indices/u_unfilled_indices.c
+++ b/src/gallium/auxiliary/indices/u_unfilled_indices.c
@@ -22,6 +22,12 @@
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 
+
+/*
+ * NOTE: This file is not compiled by itself.  It's actually #included
+ * by the generated u_unfilled_gen.c file!
+ */
+
 #include "u_indices.h"
 #include "u_indices_priv.h"
 #include "util/u_prim.h"
@@ -104,6 +110,14 @@ nr_lines(unsigned prim, unsigned nr)
   return (nr - 2) / 2 * 8;
case PIPE_PRIM_POLYGON:
   return 2 * nr; /* a line (two verts) for each polygon edge */
+   /* Note: these cases can't really be handled since drawing lines instead
+* of triangles would also require changing the GS.  But if there's no GS,
+* this should work.
+*/
+   case PIPE_PRIM_TRIANGLES_ADJACENCY:
+  return (nr / 6) * 6;
+   case PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY:
+  return ((nr - 4) / 2) * 6;
default:
   assert(0);
   return 0;

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Mesa (master): util/indices: assert that the incoming primitive is a triangle type

[Brian Paul]

Module: Mesa
Branch: master
Commit: 479d364c39e06dfcbe2e1d995bd82f748b1a172d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=479d364c39e06dfcbe2e1d995bd82f748b1a172d

Author: Brian Paul 
Date:   Fri May 13 16:49:22 2016 -0600

util/indices: assert that the incoming primitive is a triangle type

The unfilled index translator/generator functions should only be
called when the primitive mode is one of the triangle types.

Reviewed-by: Roland Scheidegger 

---

 src/gallium/auxiliary/indices/u_unfilled_indices.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/gallium/auxiliary/indices/u_unfilled_indices.c 
b/src/gallium/auxiliary/indices/u_unfilled_indices.c
index fe57fd7..49fff6b 100644
--- a/src/gallium/auxiliary/indices/u_unfilled_indices.c
+++ b/src/gallium/auxiliary/indices/u_unfilled_indices.c
@@ -24,6 +24,7 @@
 
 #include "u_indices.h"
 #include "u_indices_priv.h"
+#include "util/u_prim.h"
 
 
 static void translate_ubyte_ushort( const void *in,
@@ -123,6 +124,8 @@ u_unfilled_translator(unsigned prim,
unsigned in_idx;
unsigned out_idx;
 
+   assert(u_reduced_prim(prim) == PIPE_PRIM_TRIANGLES);
+
u_unfilled_init();
 
in_idx = in_size_idx(in_index_size);
@@ -180,6 +183,8 @@ u_unfilled_generator(unsigned prim,
 {
unsigned out_idx;
 
+   assert(u_reduced_prim(prim) == PIPE_PRIM_TRIANGLES);
+
u_unfilled_init();
 
*out_index_size = ((start + nr) > 0xfffe) ? 4 : 2;

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Mesa (master): util/indices: implement provoking vertex conversion for adjacency primitives

[Brian Paul]

Module: Mesa
Branch: master
Commit: d6c2c7d7109785935086551ac3d82c4ad819483a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6c2c7d7109785935086551ac3d82c4ad819483a

Author: Brian Paul 
Date:   Wed May 25 15:53:25 2016 -0600

util/indices: implement provoking vertex conversion for adjacency primitives

Tested with new piglit gl-3.2-adj-prims test.

Reviewed-by: Roland Scheidegger 

---

 src/gallium/auxiliary/indices/u_indices.c  | 52 
 src/gallium/auxiliary/indices/u_indices_gen.py | 83 +-
 src/gallium/auxiliary/indices/u_indices_priv.h |  2 +-
 3 files changed, 134 insertions(+), 3 deletions(-)

diff --git a/src/gallium/auxiliary/indices/u_indices.c 
b/src/gallium/auxiliary/indices/u_indices.c
index 436f8f0..2b2d10c 100644
--- a/src/gallium/auxiliary/indices/u_indices.c
+++ b/src/gallium/auxiliary/indices/u_indices.c
@@ -55,6 +55,8 @@ static void translate_memcpy_uint( const void *in,
  * - Translate from first provoking vertex to last provoking vertex and
  *   vice versa.
  *
+ * Note that this function is used for indexed primitives.
+ *
  * \param hw_mask  mask of (1 << PIPE_PRIM_x) flags indicating which types
  * of primitives are supported by the hardware.
  * \param prim  incoming PIPE_PRIM_x
@@ -172,6 +174,30 @@ u_index_translator(unsigned hw_mask,
  *out_nr = (nr - 2) * 3;
  break;
 
+  case PIPE_PRIM_LINES_ADJACENCY:
+ *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
+ *out_prim = PIPE_PRIM_LINES_ADJACENCY;
+ *out_nr = nr;
+ break;
+
+  case PIPE_PRIM_LINE_STRIP_ADJACENCY:
+ *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
+ *out_prim = PIPE_PRIM_LINES_ADJACENCY;
+ *out_nr = (nr - 3) * 4;
+ break;
+
+  case PIPE_PRIM_TRIANGLES_ADJACENCY:
+ *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
+ *out_prim = PIPE_PRIM_TRIANGLES_ADJACENCY;
+ *out_nr = nr;
+ break;
+
+  case PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY:
+ *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
+ *out_prim = PIPE_PRIM_TRIANGLES_ADJACENCY;
+ *out_nr = ((nr - 4) / 2) * 6;
+ break;
+
   default:
  assert(0);
  *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
@@ -193,6 +219,8 @@ u_index_translator(unsigned hw_mask,
  * The generator functions generates a number of ushort or uint indexes
  * for drawing the new type of primitive.
  *
+ * Note that this function is used for non-indexed primitives.
+ *
  * \param hw_mask  a bitmask of (1 << PIPE_PRIM_x) values that indicates
  * kind of primitives are supported by the driver.
  * \param prim  the PIPE_PRIM_x that the user wants to draw
@@ -294,6 +322,30 @@ u_index_generator(unsigned hw_mask,
  *out_nr = (nr - 2) * 3;
  return U_GENERATE_REUSABLE;
 
+  case PIPE_PRIM_LINES_ADJACENCY:
+ *out_generate = generate[out_idx][in_pv][out_pv][prim];
+ *out_prim = PIPE_PRIM_LINES_ADJACENCY;
+ *out_nr = nr;
+ return U_GENERATE_REUSABLE;
+
+  case PIPE_PRIM_LINE_STRIP_ADJACENCY:
+ *out_generate = generate[out_idx][in_pv][out_pv][prim];
+ *out_prim = PIPE_PRIM_LINES_ADJACENCY;
+ *out_nr = (nr - 3) * 4;
+ return U_GENERATE_REUSABLE;
+
+  case PIPE_PRIM_TRIANGLES_ADJACENCY:
+ *out_generate = generate[out_idx][in_pv][out_pv][prim];
+ *out_prim = PIPE_PRIM_TRIANGLES_ADJACENCY;
+ *out_nr = nr;
+ return U_GENERATE_REUSABLE;
+
+  case PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY:
+ *out_generate = generate[out_idx][in_pv][out_pv][prim];
+ *out_prim = PIPE_PRIM_TRIANGLES_ADJACENCY;
+ *out_nr = ((nr - 4) / 2) * 6;
+ return U_GENERATE_REUSABLE;
+
   default:
  assert(0);
  *out_generate = generate[out_idx][in_pv][out_pv][PIPE_PRIM_POINTS];
diff --git a/src/gallium/auxiliary/indices/u_indices_gen.py 
b/src/gallium/auxiliary/indices/u_indices_gen.py
index 97c8e0d..fb6b310 100644
--- a/src/gallium/auxiliary/indices/u_indices_gen.py
+++ b/src/gallium/auxiliary/indices/u_indices_gen.py
@@ -42,7 +42,11 @@ PRIMS=('points',
'tristrip', 
'quads', 
'quadstrip', 
-   'polygon')
+   'polygon',
+   'linesadj',
+   'linestripadj',
+   'trisadj',
+   'tristripadj')
 
 LONGPRIMS=('PIPE_PRIM_POINTS', 
'PIPE_PRIM_LINES', 
@@ -53,7 +57,11 @@ LONGPRIMS=('PIPE_PRIM_POINTS',
'PIPE_PRIM_TRIANGLE_STRIP', 
'PIPE_PRIM_QUADS', 
'PIPE_PRIM_QUAD_STRIP', 
-   'PIPE_PRIM_POLYGON')
+   'PIPE_PRIM_POLYGON',
+   'PIPE_PRIM_LINES_ADJACENCY',
+   'PIPE_PRIM_LINE_STRIP_ADJACENCY',
+   

Mesa (master): util/indices: move duplicated assignments out of switch cases

[Brian Paul]

Module: Mesa
Branch: master
Commit: 7a49b41436e540e7dfa3d34d119a6aef72f228a5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a49b41436e540e7dfa3d34d119a6aef72f228a5

Author: Brian Paul 
Date:   Thu May 26 09:50:24 2016 -0600

util/indices: move duplicated assignments out of switch cases

Spotted by Roland.

Reviewed-by: Roland Scheidegger 

---

 src/gallium/auxiliary/indices/u_indices.c | 33 ---
 1 file changed, 4 insertions(+), 29 deletions(-)

diff --git a/src/gallium/auxiliary/indices/u_indices.c 
b/src/gallium/auxiliary/indices/u_indices.c
index 91f00f2..323c971 100644
--- a/src/gallium/auxiliary/indices/u_indices.c
+++ b/src/gallium/auxiliary/indices/u_indices.c
@@ -113,94 +113,81 @@ u_index_translator(unsigned hw_mask,
   return U_TRANSLATE_MEMCPY;
}
else {
+  *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
+
   switch (prim) {
   case PIPE_PRIM_POINTS:
- *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
  *out_prim = PIPE_PRIM_POINTS;
  *out_nr = nr;
  break;
 
   case PIPE_PRIM_LINES:
- *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
  *out_prim = PIPE_PRIM_LINES;
  *out_nr = nr;
  break;
 
   case PIPE_PRIM_LINE_STRIP:
- *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
  *out_prim = PIPE_PRIM_LINES;
  *out_nr = (nr - 1) * 2;
  break;
 
   case PIPE_PRIM_LINE_LOOP:
- *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
  *out_prim = PIPE_PRIM_LINES;
  *out_nr = nr * 2;
  break;
 
   case PIPE_PRIM_TRIANGLES:
- *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
  *out_prim = PIPE_PRIM_TRIANGLES;
  *out_nr = nr;
  break;
 
   case PIPE_PRIM_TRIANGLE_STRIP:
- *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
  *out_prim = PIPE_PRIM_TRIANGLES;
  *out_nr = (nr - 2) * 3;
  break;
 
   case PIPE_PRIM_TRIANGLE_FAN:
- *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
  *out_prim = PIPE_PRIM_TRIANGLES;
  *out_nr = (nr - 2) * 3;
  break;
 
   case PIPE_PRIM_QUADS:
- *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
  *out_prim = PIPE_PRIM_TRIANGLES;
  *out_nr = (nr / 4) * 6;
  break;
 
   case PIPE_PRIM_QUAD_STRIP:
- *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
  *out_prim = PIPE_PRIM_TRIANGLES;
  *out_nr = (nr - 2) * 3;
  break;
 
   case PIPE_PRIM_POLYGON:
- *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
  *out_prim = PIPE_PRIM_TRIANGLES;
  *out_nr = (nr - 2) * 3;
  break;
 
   case PIPE_PRIM_LINES_ADJACENCY:
- *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
  *out_prim = PIPE_PRIM_LINES_ADJACENCY;
  *out_nr = nr;
  break;
 
   case PIPE_PRIM_LINE_STRIP_ADJACENCY:
- *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
  *out_prim = PIPE_PRIM_LINES_ADJACENCY;
  *out_nr = (nr - 3) * 4;
  break;
 
   case PIPE_PRIM_TRIANGLES_ADJACENCY:
- *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
  *out_prim = PIPE_PRIM_TRIANGLES_ADJACENCY;
  *out_nr = nr;
  break;
 
   case PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY:
- *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
  *out_prim = PIPE_PRIM_TRIANGLES_ADJACENCY;
  *out_nr = ((nr - 4) / 2) * 6;
  break;
 
   default:
  assert(0);
- *out_translate = 
translate[in_idx][out_idx][in_pv][out_pv][prim_restart][prim];
  *out_prim = PIPE_PRIM_POINTS;
  *out_nr = nr;
  return U_TRANSLATE_ERROR;
@@ -261,87 +248,75 @@ u_index_generator(unsigned hw_mask,
   return U_GENERATE_LINEAR;
}
else {
+  *out_generate = generate[out_idx][in_pv][out_pv][prim];
+
   switch (prim) {
   case PIPE_PRIM_POINTS:
- *out_generate = generate[out_idx][in_pv][out_pv][prim];
  *out_prim = PIPE_PRIM_POINTS;
  *out_nr = nr;
  return U_GENERATE_REUSABLE;
 
   case PIPE_PRIM_LINES:
- *out_generate = generate[out_idx][in_pv][out_pv][prim];
  *out_prim = PIPE_PRIM_LINES;
  *out_nr = nr;
  return U_GENERATE_REUSABLE;
 
   case PIPE_PRIM_LINE_STRIP:
- *out_generate = generate[out_idx][in_pv][out_pv][prim];
  

Mesa (master): svga: fix test for unfilled triangles fallback

[Brian Paul]

Module: Mesa
Branch: master
Commit: 90afd7b7ef897f7ba126006d866d1e726235b974
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=90afd7b7ef897f7ba126006d866d1e726235b974

Author: Brian Paul 
Date:   Wed May 25 12:42:55 2016 -0600

svga: fix test for unfilled triangles fallback

VGPU10 actually supports line-mode triangles.  We failed to make use of
that before.

Reviewed-by: Charmaine Lee 

---

 src/gallium/drivers/svga/svga_draw_arrays.c   |  8 --
 src/gallium/drivers/svga/svga_draw_elements.c |  3 +--
 src/gallium/drivers/svga/svga_draw_private.h  | 38 +--
 3 files changed, 43 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_draw_arrays.c 
b/src/gallium/drivers/svga/svga_draw_arrays.c
index c056772..43d7a97 100644
--- a/src/gallium/drivers/svga/svga_draw_arrays.c
+++ b/src/gallium/drivers/svga/svga_draw_arrays.c
@@ -212,6 +212,11 @@ svga_hwtnl_draw_arrays(struct svga_hwtnl *hwtnl,
unsigned api_pv = hwtnl->api_pv;
struct svga_context *svga = hwtnl->svga;
 
+   if (svga->curr.rast->templ.fill_front !=
+   svga->curr.rast->templ.fill_back) {
+  assert(hwtnl->api_fillmode == PIPE_POLYGON_MODE_FILL);
+   }
+
if (svga->curr.rast->templ.flatshade &&
svga->state.hw_draw.fs->constant_color_output) {
   /* The fragment color is a constant, not per-vertex so the whole
@@ -236,8 +241,7 @@ svga_hwtnl_draw_arrays(struct svga_hwtnl *hwtnl,
   }
}
 
-   if (hwtnl->api_fillmode != PIPE_POLYGON_MODE_FILL &&
-   u_reduced_prim(prim) == PIPE_PRIM_TRIANGLES) {
+   if (svga_need_unfilled_fallback(hwtnl, prim)) {
   /* Convert unfilled polygons into points, lines, triangles */
   gen_type = u_unfilled_generator(prim,
   start,
diff --git a/src/gallium/drivers/svga/svga_draw_elements.c 
b/src/gallium/drivers/svga/svga_draw_elements.c
index a987b92..b74c745 100644
--- a/src/gallium/drivers/svga/svga_draw_elements.c
+++ b/src/gallium/drivers/svga/svga_draw_elements.c
@@ -138,8 +138,7 @@ svga_hwtnl_draw_range_elements(struct svga_hwtnl *hwtnl,
u_translate_func gen_func;
enum pipe_error ret = PIPE_OK;
 
-   if (hwtnl->api_fillmode != PIPE_POLYGON_MODE_FILL &&
-   u_reduced_prim(prim) == PIPE_PRIM_TRIANGLES) {
+   if (svga_need_unfilled_fallback(hwtnl, prim)) {
   gen_type = u_unfilled_translator(prim,
index_size,
count,
diff --git a/src/gallium/drivers/svga/svga_draw_private.h 
b/src/gallium/drivers/svga/svga_draw_private.h
index 48e0b60..da5d60e 100644
--- a/src/gallium/drivers/svga/svga_draw_private.h
+++ b/src/gallium/drivers/svga/svga_draw_private.h
@@ -29,6 +29,8 @@
 #include "pipe/p_compiler.h"
 #include "pipe/p_defines.h"
 #include "indices/u_indices.h"
+#include "util/u_prim.h"
+#include "svga_context.h"
 #include "svga_hw_reg.h"
 #include "svga3d_shaderdefs.h"
 
@@ -182,9 +184,41 @@ struct svga_hwtnl {
 
 
 
-/***
- * Internal functions
+/**
+ * Do we need to use the gallium 'indices' helper to render unfilled
+ * triangles?
  */
+static inline boolean
+svga_need_unfilled_fallback(const struct svga_hwtnl *hwtnl, unsigned prim)
+{
+   const struct svga_context *svga = hwtnl->svga;
+
+   if (u_reduced_prim(prim) != PIPE_PRIM_TRIANGLES) {
+  /* if we're drawing points or lines, no fallback needed */
+  return FALSE;
+   }
+
+   if (svga_have_vgpu10(svga)) {
+  /* vgpu10 supports polygon fill and line modes */
+  if ((prim == PIPE_PRIM_QUADS ||
+   prim == PIPE_PRIM_QUAD_STRIP ||
+   prim == PIPE_PRIM_POLYGON) &&
+  hwtnl->api_fillmode == PIPE_POLYGON_MODE_LINE) {
+ /* VGPU10 doesn't directly render quads or polygons.  They're
+  * converted to triangles.  If we let the device draw the triangle
+  * outlines we'll get an extra, stray lines in the interiors.
+  * So, to draw unfilled quads correctly, we need the fallback.
+  */
+ return true;
+  }
+  return hwtnl->api_fillmode == PIPE_POLYGON_MODE_POINT;
+   } else {
+  /* vgpu9 doesn't support line or point fill modes */
+  return hwtnl->api_fillmode != PIPE_POLYGON_MODE_FILL;
+   }
+}
+
+
 enum pipe_error 
 svga_hwtnl_prim( struct svga_hwtnl *hwtnl,
  const SVGA3dPrimitiveRange *range,

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Mesa (master): util/indices: formatting, whitespace fixes in u_unfilled_indices.c

[Brian Paul]

Module: Mesa
Branch: master
Commit: 26de558072509ca9a6d399d6c597f1da30e28ab6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=26de558072509ca9a6d399d6c597f1da30e28ab6

Author: Brian Paul 
Date:   Fri May 13 16:46:26 2016 -0600

util/indices: formatting, whitespace fixes in u_unfilled_indices.c

Reviewed-by: Roland Scheidegger 

---

 src/gallium/auxiliary/indices/u_unfilled_indices.c | 19 +++
 1 file changed, 7 insertions(+), 12 deletions(-)

diff --git a/src/gallium/auxiliary/indices/u_unfilled_indices.c 
b/src/gallium/auxiliary/indices/u_unfilled_indices.c
index fc974f8..fe57fd7 100644
--- a/src/gallium/auxiliary/indices/u_unfilled_indices.c
+++ b/src/gallium/auxiliary/indices/u_unfilled_indices.c
@@ -49,7 +49,7 @@ static void translate_memcpy_ushort( const void *in,
 {
memcpy(out, &((short *)in)[start], out_nr*sizeof(short));
 }
-  
+
 static void translate_memcpy_uint( const void *in,
unsigned start,
unsigned in_nr,
@@ -70,7 +70,7 @@ static void generate_linear_ushort( unsigned start,
for (i = 0; i < nr; i++)
   out_us[i] = (ushort)(i + start);
 }
-  
+
 static void generate_linear_uint( unsigned start,
   unsigned nr,
   void *out )
@@ -87,12 +87,12 @@ static void generate_linear_uint( unsigned start,
  * needed to draw the primitive with fill mode = PIPE_POLYGON_MODE_LINE using
  * separate lines (PIPE_PRIM_LINES).
  */
-static unsigned nr_lines( unsigned prim,
-  unsigned nr )
+static unsigned
+nr_lines(unsigned prim, unsigned nr)
 {
switch (prim) {
case PIPE_PRIM_TRIANGLES:
-  return (nr / 3) * 6; 
+  return (nr / 3) * 6;
case PIPE_PRIM_TRIANGLE_STRIP:
   return (nr - 2) * 6;
case PIPE_PRIM_TRIANGLE_FAN:
@@ -108,7 +108,6 @@ static unsigned nr_lines( unsigned prim,
   return 0;
}
 }
-  
 
 
 enum indices_mode
@@ -130,13 +129,11 @@ u_unfilled_translator(unsigned prim,
*out_index_size = (in_index_size == 4) ? 4 : 2;
out_idx = out_size_idx(*out_index_size);
 
-   if (unfilled_mode == PIPE_POLYGON_MODE_POINT) 
-   {
+   if (unfilled_mode == PIPE_POLYGON_MODE_POINT) {
   *out_prim = PIPE_PRIM_POINTS;
   *out_nr = nr;
 
-  switch (in_index_size)
-  {
+  switch (in_index_size) {
   case 1:
  *out_translate = translate_ubyte_ushort;
  return U_TRANSLATE_NORMAL;
@@ -189,7 +186,6 @@ u_unfilled_generator(unsigned prim,
out_idx = out_size_idx(*out_index_size);
 
if (unfilled_mode == PIPE_POLYGON_MODE_POINT) {
-
   if (*out_index_size == 4)
  *out_generate = generate_linear_uint;
   else
@@ -208,4 +204,3 @@ u_unfilled_generator(unsigned prim,
   return U_GENERATE_REUSABLE;
}
 }
-

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Mesa (master): util: s/unsigned/enum pipe_resource_usage/ for buffer usage variables

[Brian Paul]

Module: Mesa
Branch: master
Commit: 21a3fb9cd838cdcbdf1be97453878abf74dd3f6f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=21a3fb9cd838cdcbdf1be97453878abf74dd3f6f

Author: Brian Paul 
Date:   Wed May 25 17:13:56 2016 -0600

util: s/unsigned/enum pipe_resource_usage/ for buffer usage variables

Reviewed-by: Marek Olšák 

Reviewed-by: Roland Scheidegger 

---

 src/gallium/auxiliary/util/u_debug.c  | 2 +-
 src/gallium/auxiliary/util/u_debug.h  | 2 +-
 src/gallium/auxiliary/util/u_inlines.h| 6 +++---
 src/gallium/auxiliary/util/u_staging.c| 2 +-
 src/gallium/auxiliary/util/u_staging.h| 2 +-
 src/gallium/auxiliary/util/u_suballoc.c   | 5 +++--
 src/gallium/auxiliary/util/u_suballoc.h   | 3 ++-
 src/gallium/auxiliary/util/u_upload_mgr.c | 4 ++--
 src/gallium/auxiliary/util/u_upload_mgr.h | 2 +-
 9 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_debug.c 
b/src/gallium/auxiliary/util/u_debug.c
index db66357..0d63cfe 100644
--- a/src/gallium/auxiliary/util/u_debug.c
+++ b/src/gallium/auxiliary/util/u_debug.c
@@ -550,7 +550,7 @@ debug_print_bind_flags(const char *msg, unsigned usage)
  * Print PIPE_USAGE_x enum values with a message.
  */
 void
-debug_print_usage_enum(const char *msg, unsigned usage)
+debug_print_usage_enum(const char *msg, enum pipe_resource_usage usage)
 {
static const struct debug_named_value names[] = {
   DEBUG_NAMED_VALUE(PIPE_USAGE_DEFAULT),
diff --git a/src/gallium/auxiliary/util/u_debug.h 
b/src/gallium/auxiliary/util/u_debug.h
index 85d0cb6..7da7f53 100644
--- a/src/gallium/auxiliary/util/u_debug.h
+++ b/src/gallium/auxiliary/util/u_debug.h
@@ -473,7 +473,7 @@ void
 debug_print_bind_flags(const char *msg, unsigned usage);
 
 void
-debug_print_usage_enum(const char *msg, unsigned usage);
+debug_print_usage_enum(const char *msg, enum pipe_resource_usage usage);
 
 
 #ifdef __cplusplus
diff --git a/src/gallium/auxiliary/util/u_inlines.h 
b/src/gallium/auxiliary/util/u_inlines.h
index 07c058a..a38223c 100644
--- a/src/gallium/auxiliary/util/u_inlines.h
+++ b/src/gallium/auxiliary/util/u_inlines.h
@@ -230,12 +230,12 @@ pipe_surface_equal(struct pipe_surface *s1, struct 
pipe_surface *s2)
 /**
  * Create a new resource.
  * \param bind  bitmask of PIPE_BIND_x flags
- * \param usage  bitmask of PIPE_USAGE_x flags
+ * \param usage  a PIPE_USAGE_x value
  */
 static inline struct pipe_resource *
 pipe_buffer_create( struct pipe_screen *screen,
unsigned bind,
-   unsigned usage,
+   enum pipe_resource_usage usage,
unsigned size )
 {
struct pipe_resource buffer;
@@ -395,7 +395,7 @@ pipe_buffer_write_nooverlap(struct pipe_context *pipe,
 static inline struct pipe_resource *
 pipe_buffer_create_with_data(struct pipe_context *pipe,
  unsigned bind,
- unsigned usage,
+ enum pipe_resource_usage usage,
  unsigned size,
  const void *ptr)
 {
diff --git a/src/gallium/auxiliary/util/u_staging.c 
b/src/gallium/auxiliary/util/u_staging.c
index caef2a8..5b61f5e 100644
--- a/src/gallium/auxiliary/util/u_staging.c
+++ b/src/gallium/auxiliary/util/u_staging.c
@@ -56,7 +56,7 @@ util_staging_resource_template(struct pipe_resource *pt, 
unsigned width,
 struct util_staging_transfer *
 util_staging_transfer_init(struct pipe_context *pipe,
struct pipe_resource *pt,
-   unsigned level, unsigned usage,
+   unsigned level, enum pipe_resource_usage usage,
const struct pipe_box *box,
boolean direct, struct util_staging_transfer *tx)
 {
diff --git a/src/gallium/auxiliary/util/u_staging.h 
b/src/gallium/auxiliary/util/u_staging.h
index 6c468aa..eed5584 100644
--- a/src/gallium/auxiliary/util/u_staging.h
+++ b/src/gallium/auxiliary/util/u_staging.h
@@ -56,7 +56,7 @@ struct util_staging_transfer {
 struct util_staging_transfer *
 util_staging_transfer_init(struct pipe_context *pipe,
struct pipe_resource *pt,
-   unsigned level, unsigned usage,
+   unsigned level, enum pipe_resource_usage usage,
const struct pipe_box *box,
boolean direct, struct util_staging_transfer *tx);
 
diff --git a/src/gallium/auxiliary/util/u_suballoc.c 
b/src/gallium/auxiliary/util/u_suballoc.c
index efa9a0c..3f9ede0 100644
--- a/src/gallium/auxiliary/util/u_suballoc.c
+++ b/src/gallium/auxiliary/util/u_suballoc.c
@@ -43,7 +43,7 @@ struct u_suballocator {
unsigned size;  /* Size of the whole buffer, in bytes. */
unsigned alignment; /* Alignment of each sub-allocation. */
unsigned bind;  /* Bitmask of 

Mesa (master): gallium: change pipe_draw_info::mode to be pipe_prim_type

[Brian Paul]

Module: Mesa
Branch: master
Commit: 46be65c681b251beced67abfabbb86117b589d44
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=46be65c681b251beced67abfabbb86117b589d44

Author: Brian Paul 
Date:   Thu May 26 07:17:50 2016 -0600

gallium: change pipe_draw_info::mode to be pipe_prim_type

Makes debugging with gdb a little nicer.

Reviewed-by: Marek Olšák 
Reviewed-by: Roland Scheidegger 

---

 src/gallium/include/pipe/p_state.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/include/pipe/p_state.h 
b/src/gallium/include/pipe/p_state.h
index eacf9bb..396f563 100644
--- a/src/gallium/include/pipe/p_state.h
+++ b/src/gallium/include/pipe/p_state.h
@@ -617,7 +617,7 @@ struct pipe_draw_info
 {
boolean indexed;  /**< use index buffer */
 
-   unsigned mode;  /**< the mode of the primitive */
+   enum pipe_prim_type mode;  /**< the mode of the primitive */
unsigned start;  /**< the index of the first vertex */
unsigned count;  /**< number of vertices */
 

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Mesa (master): svga: fix primitive mode (point/line/tri) test for unfilled primitives

[Brian Paul]

Module: Mesa
Branch: master
Commit: 5393238765b478f77616936047e78512fe91b66f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5393238765b478f77616936047e78512fe91b66f

Author: Brian Paul 
Date:   Mon May  9 13:42:58 2016 -0600

svga: fix primitive mode (point/line/tri) test for unfilled primitives

The original mode test was valid before we had GS support.

Regression tested with full piglit run.  Though, I don't think we have
any piglit tests that exercise drawing unfilled adjacency primitives.

Reviewed-by: Charmaine Lee 

---

 src/gallium/drivers/svga/svga_draw_arrays.c   | 2 +-
 src/gallium/drivers/svga/svga_draw_elements.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_draw_arrays.c 
b/src/gallium/drivers/svga/svga_draw_arrays.c
index 7d82930..c056772 100644
--- a/src/gallium/drivers/svga/svga_draw_arrays.c
+++ b/src/gallium/drivers/svga/svga_draw_arrays.c
@@ -237,7 +237,7 @@ svga_hwtnl_draw_arrays(struct svga_hwtnl *hwtnl,
}
 
if (hwtnl->api_fillmode != PIPE_POLYGON_MODE_FILL &&
-   prim >= PIPE_PRIM_TRIANGLES) {
+   u_reduced_prim(prim) == PIPE_PRIM_TRIANGLES) {
   /* Convert unfilled polygons into points, lines, triangles */
   gen_type = u_unfilled_generator(prim,
   start,
diff --git a/src/gallium/drivers/svga/svga_draw_elements.c 
b/src/gallium/drivers/svga/svga_draw_elements.c
index 74bfebd..a987b92 100644
--- a/src/gallium/drivers/svga/svga_draw_elements.c
+++ b/src/gallium/drivers/svga/svga_draw_elements.c
@@ -139,7 +139,7 @@ svga_hwtnl_draw_range_elements(struct svga_hwtnl *hwtnl,
enum pipe_error ret = PIPE_OK;
 
if (hwtnl->api_fillmode != PIPE_POLYGON_MODE_FILL &&
-   prim >= PIPE_PRIM_TRIANGLES) {
+   u_reduced_prim(prim) == PIPE_PRIM_TRIANGLES) {
   gen_type = u_unfilled_translator(prim,
index_size,
count,

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Mesa (master): mesa: Add extension tracking for GL_OES_shader_io_blocks

[Ian Romanick]

Module: Mesa
Branch: master
Commit: f0902ee813c7939e114d3adca3baa9ca13eed6ce
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0902ee813c7939e114d3adca3baa9ca13eed6ce

Author: Ian Romanick 
Date:   Wed May 11 13:05:22 2016 -0700

mesa: Add extension tracking for GL_OES_shader_io_blocks

v2: Also support GL_EXT_shader_io_blocks.  It's pretty much identical to
the OES extension.  Suggested by Ilia.

Signed-off-by: Ian Romanick 
Reviewed-by: Timothy Arceri 
Reviewed-by: Alejandro Piñeiro 

---

 src/compiler/glsl/glcpp/glcpp-parse.y| 5 +
 src/compiler/glsl/glsl_parser_extras.cpp | 2 ++
 src/compiler/glsl/glsl_parser_extras.h   | 4 
 src/mesa/main/extensions_table.h | 2 ++
 src/mesa/main/mtypes.h   | 1 +
 5 files changed, 14 insertions(+)

diff --git a/src/compiler/glsl/glcpp/glcpp-parse.y 
b/src/compiler/glsl/glcpp/glcpp-parse.y
index ee0d8f1..4022727 100644
--- a/src/compiler/glsl/glcpp/glcpp-parse.y
+++ b/src/compiler/glsl/glcpp/glcpp-parse.y
@@ -2329,6 +2329,11 @@ _glcpp_parser_handle_version_declaration(glcpp_parser_t 
*parser, intmax_t versio
add_builtin_define(parser, "GL_EXT_texture_buffer", 1);
add_builtin_define(parser, "GL_OES_texture_buffer", 1);
 }
+
+if (extensions->OES_shader_io_blocks) {
+   add_builtin_define(parser, "GL_EXT_shader_io_blocks", 1);
+   add_builtin_define(parser, "GL_OES_shader_io_blocks", 1);
+}
  }
   }
} else {
diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
b/src/compiler/glsl/glsl_parser_extras.cpp
index 1d9b4c5..916fca8 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -626,6 +626,7 @@ static const _mesa_glsl_extension 
_mesa_glsl_supported_extensions[] = {
EXT(OES_gpu_shader5,false, true,  ARB_gpu_shader5),
EXT(OES_sample_variables,   false, true,  OES_sample_variables),
EXT(OES_shader_image_atomic,false, true,  
ARB_shader_image_load_store),
+   EXT(OES_shader_io_blocks,   false, true,  OES_shader_io_blocks),
EXT(OES_shader_multisample_interpolation, false, true, 
OES_sample_variables),
EXT(OES_standard_derivatives,   false, true,  
OES_standard_derivatives),
EXT(OES_texture_3D, false, true,  dummy_true),
@@ -645,6 +646,7 @@ static const _mesa_glsl_extension 
_mesa_glsl_supported_extensions[] = {
EXT(EXT_gpu_shader5,false, true,  ARB_gpu_shader5),
EXT(EXT_separate_shader_objects,false, true,  dummy_true),
EXT(EXT_shader_integer_mix, true,  true,  
EXT_shader_integer_mix),
+   EXT(EXT_shader_io_blocks,   false, true,  OES_shader_io_blocks),
EXT(EXT_shader_samples_identical,   true,  true,  
EXT_shader_samples_identical),
EXT(EXT_texture_array,  true,  false, EXT_texture_array),
EXT(EXT_texture_buffer, false, true,  OES_texture_buffer),
diff --git a/src/compiler/glsl/glsl_parser_extras.h 
b/src/compiler/glsl/glsl_parser_extras.h
index 0c8405d..d70a31b 100644
--- a/src/compiler/glsl/glsl_parser_extras.h
+++ b/src/compiler/glsl/glsl_parser_extras.h
@@ -626,6 +626,8 @@ struct _mesa_glsl_parse_state {
bool OES_sample_variables_warn;
bool OES_shader_image_atomic_enable;
bool OES_shader_image_atomic_warn;
+   bool OES_shader_io_blocks_enable;
+   bool OES_shader_io_blocks_warn;
bool OES_shader_multisample_interpolation_enable;
bool OES_shader_multisample_interpolation_warn;
bool OES_standard_derivatives_enable;
@@ -661,6 +663,8 @@ struct _mesa_glsl_parse_state {
bool EXT_separate_shader_objects_warn;
bool EXT_shader_integer_mix_enable;
bool EXT_shader_integer_mix_warn;
+   bool EXT_shader_io_blocks_enable;
+   bool EXT_shader_io_blocks_warn;
bool EXT_shader_samples_identical_enable;
bool EXT_shader_samples_identical_warn;
bool EXT_texture_array_enable;
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index e3c91ef..b715f7c 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -227,6 +227,7 @@ EXT(EXT_secondary_color , dummy_true
 EXT(EXT_separate_shader_objects , dummy_true   
  ,  x ,  x ,  x , ES2, 2013)
 EXT(EXT_separate_specular_color , dummy_true   
  , GLL,  x ,  x ,  x , 1997)
 EXT(EXT_shader_integer_mix  , EXT_shader_integer_mix   
  , GLL, GLC,  x ,  30, 2013)
+EXT(EXT_shader_io_blocks, OES_shader_io_blocks 
  ,  x ,  x ,  x ,  31, 2014)
 EXT(EXT_shader_samples_identical, EXT_shader_samples_identical 
  , GLL, GLC,  x ,  31, 2015)
 EXT(EXT_shadow_funcs  

Mesa (master): glsl: Allow shader interface blocks in GLSL ES

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 660240da9e801c5e62ecce373464290ae1048c70
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=660240da9e801c5e62ecce373464290ae1048c70

Author: Ian Romanick 
Date:   Wed May 11 18:24:32 2016 -0700

glsl: Allow shader interface blocks in GLSL ES

Signed-off-by: Ian Romanick 
Reviewed-by: Timothy Arceri 
Reviewed-by: Alejandro Piñeiro 

---

 src/compiler/glsl/glsl_parser_extras.cpp | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
b/src/compiler/glsl/glsl_parser_extras.cpp
index 916fca8..843998d 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -895,10 +895,16 @@ _mesa_ast_process_interface_block(YYLTYPE *locp,
 "required for defining uniform blocks");
   }
} else {
-  if (state->es_shader || state->language_version < 150) {
- _mesa_glsl_error(locp, state,
-  "#version 150 required for using "
-  "interface blocks");
+  if (!state->has_shader_io_blocks()) {
+ if (state->es_shader) {
+_mesa_glsl_error(locp, state,
+ "GL_OES_shader_io_blocks or #version 320 "
+ "required for using interface blocks");
+ } else {
+_mesa_glsl_error(locp, state,
+ "#version 150 required for using "
+ "interface blocks");
+ }
   }
}
 

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Mesa (master): i965: Enable GL_OES_shader_io_blocks

[Ian Romanick]

Module: Mesa
Branch: master
Commit: b7af108d3edd156836824dbad23f97d6acf75dc9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7af108d3edd156836824dbad23f97d6acf75dc9

Author: Ian Romanick 
Date:   Wed May 11 13:11:00 2016 -0700

i965: Enable GL_OES_shader_io_blocks

Only one dEQP io_blocks test fails.  This test fails for the same reason
as the match_different_member_struct_names test in a previous commit.

dEQP-GLES31.functional.separate_shader.validation.io_blocks.match_different_member_struct_names

v2: Add to release notes.

Signed-off-by: Ian Romanick 
Reviewed-by: Timothy Arceri 
Reviewed-by: Alejandro Piñeiro 

---

 docs/GL3.txt | 2 +-
 docs/relnotes/11.3.0.html| 1 +
 src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index 9258fdf..9a686fd 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -264,7 +264,7 @@ GLES3.2, GLSL ES 3.2
   GL_OES_sample_shading DONE (i965, nvc0, 
r600, radeonsi)
   GL_OES_sample_variables   DONE (i965, nvc0, 
r600, radeonsi)
   GL_OES_shader_image_atomicDONE (all drivers that 
support GL_ARB_shader_image_load_store)
-  GL_OES_shader_io_blocks   started (idr)
+  GL_OES_shader_io_blocks   DONE (i965/gen8+)
   GL_OES_shader_multisample_interpolation   DONE (i965, nvc0, 
r600, radeonsi)
   GL_OES_tessellation_shaderstarted (Ken)
   GL_OES_texture_border_clamp   DONE (all drivers)
diff --git a/docs/relnotes/11.3.0.html b/docs/relnotes/11.3.0.html
index 6838e1c..0ae1a72 100644
--- a/docs/relnotes/11.3.0.html
+++ b/docs/relnotes/11.3.0.html
@@ -67,6 +67,7 @@ Note: some of the new features are only available with 
certain drivers.
 GL_OES_sample_shading on i965, nvc0, r600, radeonsi
 GL_OES_sample_variables on i965, nvc0, r600, radeonsi
 GL_OES_shader_image_atomic on all drivers that support 
GL_ARB_shader_image_load_store
+GL_OES_shader_io_blocks on all i965
 GL_OES_shader_multisample_interpolation on i965, nvc0, r600, radeonsi
 GL_OES_texture_border_clamp and GL_EXT_texture_border_clamp on all drivers 
that support GL_ARB_texture_border_clamp
 GL_OES_texture_buffer and GL_EXT_texture_buffer on i965, nvc0, 
radeonsi
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
b/src/mesa/drivers/dri/i965/intel_extensions.c
index c392674..b49e060 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -393,6 +393,7 @@ intelInitExtensions(struct gl_context *ctx)
   ctx->Extensions.ARB_texture_stencil8 = true;
   ctx->Extensions.ARB_gpu_shader_fp64 = true;
   ctx->Extensions.ARB_vertex_attrib_64bit = true;
+  ctx->Extensions.OES_shader_io_blocks = true;
}
 
if (brw->gen >= 9) {

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Mesa (master): glsl: Add a has_shader_io_blocks helper

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 7a3093efcceb22a1d190a4c72a6f3280b2cad5ca
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a3093efcceb22a1d190a4c72a6f3280b2cad5ca

Author: Ian Romanick 
Date:   Wed May 11 14:03:40 2016 -0700

glsl: Add a has_shader_io_blocks helper

Signed-off-by: Ian Romanick 
Reviewed-by: Timothy Arceri 
Reviewed-by: Alejandro Piñeiro 

---

 src/compiler/glsl/glsl_parser_extras.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/src/compiler/glsl/glsl_parser_extras.h 
b/src/compiler/glsl/glsl_parser_extras.h
index d70a31b..a0c1903 100644
--- a/src/compiler/glsl/glsl_parser_extras.h
+++ b/src/compiler/glsl/glsl_parser_extras.h
@@ -265,6 +265,13 @@ struct _mesa_glsl_parse_state {
   return ARB_compute_shader_enable || is_version(430, 310);
}
 
+   bool has_shader_io_blocks() const
+   {
+  return OES_shader_io_blocks_enable ||
+ EXT_shader_io_blocks_enable ||
+ is_version(150, 320);
+   }
+
bool has_geometry_shader() const
{
   return OES_geometry_shader_enable || is_version(150, 320);

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Mesa (master): mesa: Only validate SSO shader IO in OpenGL ES or debug context

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 326a269c7778e2921d48e5d1d2a3683331a1173d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=326a269c7778e2921d48e5d1d2a3683331a1173d

Author: Ian Romanick 
Date:   Thu May 19 10:27:12 2016 -0700

mesa: Only validate SSO shader IO in OpenGL ES or debug context

v2: Move later in series to avoid issues with Gallium drivers and debug
contexts.  Suggested by Ilia.

Signed-off-by: Ian Romanick 
Suggested-by: Timothy Arceri 
Reviewed-by: Timothy Arceri 

---

 src/mesa/main/pipelineobj.c| 18 --
 src/mesa/main/shader_query.cpp |  3 ---
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/src/mesa/main/pipelineobj.c b/src/mesa/main/pipelineobj.c
index b150198..5a46cfe 100644
--- a/src/mesa/main/pipelineobj.c
+++ b/src/mesa/main/pipelineobj.c
@@ -906,7 +906,8 @@ _mesa_validate_program_pipeline(struct gl_context* ctx,
/* Validate inputs against outputs, this cannot be done during linking
 * since programs have been linked separately from each other.
 *
-* From OpenGL 4.5 Core spec:
+* Section 11.1.3.11 (Validation) of the OpenGL 4.5 Core Profile spec says:
+*
 * "Separable program objects may have validation failures that cannot 
be
 * detected without the complete program pipeline. Mismatched 
interfaces,
 * improper usage of program objects together, and the same
@@ -914,8 +915,21 @@ _mesa_validate_program_pipeline(struct gl_context* ctx,
 * program objects."
 *
 * OpenGL ES 3.1 specification has the same text.
+*
+* Section 11.1.3.11 (Validation) of the OpenGL ES spec also says:
+*
+*An INVALID_OPERATION error is generated by any command that transfers
+*vertices to the GL or launches compute work if the current set of
+*active program objects cannot be executed, for reasons including:
+*
+** The current program pipeline object contains a shader interface
+*  that doesn't have an exact match (see section 7.4.1)
+*
+* Based on this, only perform the most-strict checking on ES or when the
+* application has created a debug context.
 */
-   if (!_mesa_validate_pipeline_io(pipe))
+   if ((_mesa_is_gles(ctx) || (ctx->Const.ContextFlags & 
GL_CONTEXT_FLAG_DEBUG_BIT)) &&
+   !_mesa_validate_pipeline_io(pipe))
   return GL_FALSE;
 
pipe->Validated = GL_TRUE;
diff --git a/src/mesa/main/shader_query.cpp b/src/mesa/main/shader_query.cpp
index 81277b6..31c0a4e 100644
--- a/src/mesa/main/shader_query.cpp
+++ b/src/mesa/main/shader_query.cpp
@@ -1377,9 +1377,6 @@ validate_io(struct gl_shader_program *producer,
if (producer == consumer)
   return true;
 
-   if (!producer->IsES && !consumer->IsES)
-  return true;
-
bool valid = true;
 
gl_shader_variable const **outputs =

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Mesa (master): mesa: Remove old validate_io function

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 3722c76001ae3190ce7a813e02b5f1eefa5d07eb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3722c76001ae3190ce7a813e02b5f1eefa5d07eb

Author: Ian Romanick 
Date:   Thu May 19 18:09:00 2016 -0700

mesa: Remove old validate_io function

The new validate_io catches all of the cases (and many more) that the
old function caught.

Signed-off-by: Ian Romanick 
Reviewed-by: Timothy Arceri 
Reviewed-by: Alejandro Piñeiro 

---

 src/mesa/main/shader_query.cpp | 109 -
 1 file changed, 109 deletions(-)

diff --git a/src/mesa/main/shader_query.cpp b/src/mesa/main/shader_query.cpp
index 80e9274..81277b6 100644
--- a/src/mesa/main/shader_query.cpp
+++ b/src/mesa/main/shader_query.cpp
@@ -1371,110 +1371,6 @@ _mesa_get_program_resourceiv(struct gl_shader_program 
*shProg,
 }
 
 static bool
-validate_io(const struct gl_shader *producer,
-const struct gl_shader *consumer, bool isES)
-{
-   assert(producer && consumer);
-   unsigned inputs = 0, outputs = 0;
-
-   /* From OpenGL ES 3.1 spec (Interface matching):
-*
-*"An output variable is considered to match an input variable in the
-*subsequent shader if:
-*
-*- the two variables match in name, type, and qualification; or
-*- the two variables are declared with the same location qualifier and
-*  match in type and qualification.
-*
-*...
-*
-*At an interface between program objects, the set of inputs and outputs
-*are considered to match exactly if and only if:
-*
-*- Every declared input variable has a matching output, as described
-*above.
-*
-*- There are no user-defined output variables declared without a
-*matching input variable declaration.
-*
-*- All matched input and output variables have identical precision
-*qualification.
-*
-*When the set of inputs and outputs on an interface between programs
-*matches exactly, all inputs are well-defined except when the
-*corresponding outputs were not written in the previous shader. 
However,
-*any mismatch between inputs and outputs will result in a validation
-*failure."
-*
-* OpenGL Core 4.5 spec includes same paragraph as above but without check
-* for precision and the last 'validation failure' clause. Therefore
-* behaviour is more relaxed, input and output amount is not required by the
-* spec to be validated.
-*
-* FIXME: Update once Khronos spec bug #15331 is resolved.
-* FIXME: Add validation by type, currently information loss during varying
-* packing makes this challenging.
-*/
-
-   /* Currently no matching done for desktop. */
-   if (!isES)
-  return true;
-
-   /* For each output in a, find input in b and do any required checks. */
-   foreach_in_list(ir_instruction, out, producer->ir) {
-  ir_variable *out_var = out->as_variable();
-  if (!out_var || out_var->data.mode != ir_var_shader_out ||
-  is_gl_identifier(out_var->name))
- continue;
-
-  outputs++;
-
-  inputs = 0;
-  foreach_in_list(ir_instruction, in, consumer->ir) {
- ir_variable *in_var = in->as_variable();
- if (!in_var || in_var->data.mode != ir_var_shader_in ||
- is_gl_identifier(in_var->name))
-continue;
-
- inputs++;
-
- /* Match by location qualifier and precision.
-  *
-  * FIXME: Add explicit location matching validation here. Be careful
-  * not to match varyings with explicit locations to varyings without
-  * explicit locations.
-  */
- if ((in_var->data.explicit_location &&
- out_var->data.explicit_location) &&
- in_var->data.location == out_var->data.location &&
- in_var->data.precision == out_var->data.precision)
-continue;
-
- unsigned len = strlen(in_var->name);
-
- /* Handle input swizzle in variable name. */
- const char *dot = strchr(in_var->name, '.');
- if (dot)
-len = dot - in_var->name;
-
- /* Match by name and precision. */
- if (strncmp(in_var->name, out_var->name, len) == 0) {
-/* From OpenGL ES 3.1 spec:
- * "When both shaders are in separate programs, mismatched
- * precision qualifiers will result in a program interface
- * mismatch that will result in program pipeline validation
- * failures, as described in section 7.4.1 (“Shader Interface
- * Matching”) of the OpenGL ES 3.1 Specification."
- */
-if (in_var->data.precision != out_var->data.precision)
-   return false;
- }
-  }
-   }
-   return inputs == outputs;
-}
-

Mesa (master): mesa: Track the additional data in gl_shader_variable

[Ian Romanick]

Module: Mesa
Branch: master
Commit: cfff74629765d1d06313705f5ca80138c2182ef0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cfff74629765d1d06313705f5ca80138c2182ef0

Author: Ian Romanick 
Date:   Thu May 19 10:25:47 2016 -0700

mesa: Track the additional data in gl_shader_variable

The interface type, interpolation mode, precision, the type of the
outermost structure, and whether or not the variable has an explicit
location will be used for SSO validation on OpenGL ES.

Signed-off-by: Ian Romanick 
Reviewed-by: Timothy Arceri 
Reviewed-by: Alejandro Piñeiro 

---

 src/compiler/glsl/linker.cpp | 20 
 src/mesa/main/mtypes.h   | 32 
 2 files changed, 48 insertions(+), 4 deletions(-)

diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index 8e64553..1d55529 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -3660,7 +3660,8 @@ static gl_shader_variable *
 create_shader_variable(struct gl_shader_program *shProg,
const ir_variable *in,
const char *name, const glsl_type *type,
-   bool use_implicit_location, int location)
+   bool use_implicit_location, int location,
+   const glsl_type *outermost_struct_type)
 {
gl_shader_variable *out = ralloc(shProg, struct gl_shader_variable);
if (!out)
@@ -3703,10 +3704,15 @@ create_shader_variable(struct gl_shader_program *shProg,
}
 
out->type = type;
+   out->outermost_struct_type = outermost_struct_type;
+   out->interface_type = in->get_interface_type();
out->component = in->data.location_frac;
out->index = in->data.index;
out->patch = in->data.patch;
out->mode = in->data.mode;
+   out->interpolation = in->data.interpolation;
+   out->explicit_location = in->data.explicit_location;
+   out->precision = in->data.precision;
 
return out;
 }
@@ -3715,7 +3721,8 @@ static bool
 add_shader_variable(struct gl_shader_program *shProg, unsigned stage_mask,
 GLenum programInterface, ir_variable *var,
 const char *name, const glsl_type *type,
-bool use_implicit_location, int location)
+bool use_implicit_location, int location,
+const glsl_type *outermost_struct_type = NULL)
 {
const bool is_vertex_input =
   programInterface == GL_PROGRAM_INPUT &&
@@ -3732,13 +3739,17 @@ add_shader_variable(struct gl_shader_program *shProg, 
unsigned stage_mask,
* structure member to enumerate is itself a structure or array,
* these enumeration rules are applied recursively."
*/
+  if (outermost_struct_type == NULL)
+ outermost_struct_type = type;
+
   unsigned field_location = location;
   for (unsigned i = 0; i < type->length; i++) {
  const struct glsl_struct_field *field = >fields.structure[i];
  char *field_name = ralloc_asprintf(shProg, "%s.%s", name, 
field->name);
  if (!add_shader_variable(shProg, stage_mask, programInterface,
   var, field_name, field->type,
-  use_implicit_location, field_location))
+  use_implicit_location, field_location,
+  outermost_struct_type))
 return false;
 
  field_location +=
@@ -3772,7 +3783,8 @@ add_shader_variable(struct gl_shader_program *shProg, 
unsigned stage_mask,
*/
   gl_shader_variable *sha_v =
  create_shader_variable(shProg, var, prefixed_name, type,
-use_implicit_location, location);
+use_implicit_location, location,
+outermost_struct_type);
   if (!sha_v)
  return false;
 
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index e16663d..e8ab195 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2547,6 +2547,17 @@ struct gl_shader_variable
const struct glsl_type *type;
 
/**
+* If the variable is in an interface block, this is the type of the block.
+*/
+   const struct glsl_type *interface_type;
+
+   /**
+* For variables inside structs (possibly recursively), this is the
+* outermost struct type.
+*/
+   const struct glsl_type *outermost_struct_type;
+
+   /**
 * Declared name of the variable
 */
char *name;
@@ -2600,6 +2611,27 @@ struct gl_shader_variable
 * \sa (n)ir_variable_mode
 */
unsigned mode:4;
+
+   /**
+* Interpolation mode for shader inputs / outputs
+*
+* \sa ir_variable_interpolation
+*/
+   unsigned interpolation:2;
+
+   /**
+* Was the location explicitly set in the shader?
+*
+* If the location is explicitly 

Mesa (master): mesa: Additional SSO validation using program_interface_query data

[Ian Romanick]

Module: Mesa
Branch: master
Commit: bd3f15cffdbbec6d1ea5b7db2fcddaf8b7ae4524
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd3f15cffdbbec6d1ea5b7db2fcddaf8b7ae4524

Author: Ian Romanick 
Date:   Thu May 19 10:28:25 2016 -0700

mesa: Additional SSO validation using program_interface_query data

Fixes the following dEQP tests on SKL:

dEQP-GLES31.functional.separate_shader.validation.varying.mismatch_qualifier_vertex_smooth_fragment_flat
dEQP-GLES31.functional.separate_shader.validation.varying.mismatch_implicit_explicit_location_1
dEQP-GLES31.functional.separate_shader.validation.varying.mismatch_array_element_type
dEQP-GLES31.functional.separate_shader.validation.varying.mismatch_qualifier_vertex_flat_fragment_none
dEQP-GLES31.functional.separate_shader.validation.varying.mismatch_struct_member_order
dEQP-GLES31.functional.separate_shader.validation.varying.mismatch_struct_member_type
dEQP-GLES31.functional.separate_shader.validation.varying.mismatch_qualifier_vertex_centroid_fragment_flat
dEQP-GLES31.functional.separate_shader.validation.varying.mismatch_array_length
dEQP-GLES31.functional.separate_shader.validation.varying.mismatch_type
dEQP-GLES31.functional.separate_shader.validation.varying.mismatch_struct_member_precision
dEQP-GLES31.functional.separate_shader.validation.varying.mismatch_explicit_location_type
dEQP-GLES31.functional.separate_shader.validation.varying.mismatch_qualifier_vertex_flat_fragment_centroid
dEQP-GLES31.functional.separate_shader.validation.varying.mismatch_explicit_location
dEQP-GLES31.functional.separate_shader.validation.varying.mismatch_qualifier_vertex_flat_fragment_smooth
dEQP-GLES31.functional.separate_shader.validation.varying.mismatch_struct_member_name

It regresses one test:

dEQP-GLES31.functional.separate_shader.validation.varying.match_different_struct_names

Hoever, this test is based on language in the OpenGL ES 3.1 spec that I
believe is incorrect.  I have already submitted a spec bug:

https://www.khronos.org/bugzilla/show_bug.cgi?id=1500

v2: Move spec quote about built-in variables to the first place where
it's relevant.  Suggested by Alejandro.

v3: Move patch earlier in series, fix rebase issues.

Signed-off-by: Ian Romanick 
Reviewed-by: Alejandro Piñeiro  [v2]
Reviewed-by: Timothy Arceri  [v2]

---

 src/mesa/main/shader_query.cpp | 176 +
 1 file changed, 176 insertions(+)

diff --git a/src/mesa/main/shader_query.cpp b/src/mesa/main/shader_query.cpp
index 9e18a1c..80e9274 100644
--- a/src/mesa/main/shader_query.cpp
+++ b/src/mesa/main/shader_query.cpp
@@ -1474,6 +1474,178 @@ validate_io(const struct gl_shader *producer,
return inputs == outputs;
 }
 
+static bool
+validate_io(struct gl_shader_program *producer,
+struct gl_shader_program *consumer)
+{
+   if (producer == consumer)
+  return true;
+
+   if (!producer->IsES && !consumer->IsES)
+  return true;
+
+   bool valid = true;
+
+   gl_shader_variable const **outputs =
+  (gl_shader_variable const **) calloc(producer->NumProgramResourceList,
+   sizeof(gl_shader_variable *));
+   if (outputs == NULL)
+  return false;
+
+   /* Section 7.4.1 (Shader Interface Matching) of the OpenGL ES 3.1 spec
+* says:
+*
+*At an interface between program objects, the set of inputs and
+*outputs are considered to match exactly if and only if:
+*
+*- Every declared input variable has a matching output, as described
+*  above.
+*- There are no user-defined output variables declared without a
+*  matching input variable declaration.
+*
+* Every input has an output, and every output has an input.  Scan the list
+* of producer resources once, and generate the list of outputs.  As inputs
+* and outputs are matched, remove the matched outputs from the set.  At
+* the end, the set must be empty.  If the set is not empty, then there is
+* some output that did not have an input.
+*/
+   unsigned num_outputs = 0;
+   for (unsigned i = 0; i < producer->NumProgramResourceList; i++) {
+  struct gl_program_resource *res = >ProgramResourceList[i];
+
+  if (res->Type != GL_PROGRAM_OUTPUT)
+ continue;
+
+  gl_shader_variable const *const var = RESOURCE_VAR(res);
+
+  /* Section 7.4.1 (Shader Interface Matching) of the OpenGL ES 3.1 spec
+   * says:
+   *
+   *Built-in inputs or outputs do not affect interface matching.
+   */
+  if (is_gl_identifier(var->name))
+ continue;
+
+  outputs[num_outputs++] = var;
+   }
+
+   unsigned match_index = 0;
+   for (unsigned i = 0; i < consumer->NumProgramResourceList; i++) {
+  struct gl_program_resource *res = >ProgramResourceList[i];
+
+  if (res->Type != GL_PROGRAM_INPUT)
+ continue;
+
+  

Mesa (master): nir: Make nir_const_value a union

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 15e553daf0cd5fe70994b6ac5377ff11002357a3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=15e553daf0cd5fe70994b6ac5377ff11002357a3

Author: Jason Ekstrand 
Date:   Thu May 26 15:38:45 2016 -0700

nir: Make nir_const_value a union

There's no good reason for it to be a struct of an anonymous union.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96221
Tested-by: Vinson Lee 
Reviewed-by: Matt Turner 

---

 src/compiler/nir/nir.h   | 16 +++-
 src/compiler/nir/nir_constant_expressions.py |  2 +-
 2 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 96246f6..2e1bdfb 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1266,15 +1266,13 @@ nir_tex_instr_src_index(nir_tex_instr *instr, 
nir_tex_src_type type)
return -1;
 }
 
-typedef struct {
-   union {
-  float f32[4];
-  double f64[4];
-  int32_t i32[4];
-  uint32_t u32[4];
-  int64_t i64[4];
-  uint64_t u64[4];
-   };
+typedef union {
+   float f32[4];
+   double f64[4];
+   int32_t i32[4];
+   uint32_t u32[4];
+   int64_t i64[4];
+   uint64_t u64[4];
 } nir_const_value;
 
 typedef struct {
diff --git a/src/compiler/nir/nir_constant_expressions.py 
b/src/compiler/nir/nir_constant_expressions.py
index e36dc48..96d5255 100644
--- a/src/compiler/nir/nir_constant_expressions.py
+++ b/src/compiler/nir/nir_constant_expressions.py
@@ -270,7 +270,7 @@ static nir_const_value
 evaluate_${name}(unsigned num_components, unsigned bit_size,
  nir_const_value *_src)
 {
-   nir_const_value _dst_val = { { {0, 0, 0, 0} } };
+   nir_const_value _dst_val = { {0, } };
 
switch (bit_size) {
% for bit_size in [32, 64]:

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Mesa (master): i965: Use the buffer object size for VERTEX_BUFFER_STATE' s size field.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: e7776fa9473af0fd1424f860323916077b991bf6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7776fa9473af0fd1424f860323916077b991bf6

Author: Kenneth Graunke 
Date:   Wed May 25 14:38:32 2016 -0700

i965: Use the buffer object size for VERTEX_BUFFER_STATE's size field.

commit 7c8dfa78b98a12c1c5 (i965/draw: Use the real size for vertex
buffers) changed how we programmed the VERTEX_BUFFER_STATE size field.

Previously, we programmed it to the size of the actual underlying BO,
which is page-aligned, and potentially much larger than the GL buffer
object.  This violated the ARB_robust_buffer_access spec.

With that change, we started programming it based on the range of data
we expect the draw call to actually access - which is based on the
min_index and max_index information provided to glDrawRangeElements().

Unfortunately, applications often provide inaccurate range information
to glDrawRangeElements().  For example, all the Unreal demos appear to
draw using a range of [0, 3] when the index buffer's actual index range
is [0, 5].  Such results are undefined, and we are absolutely allowed
to restrict access to the range they specified.  However, the failure
mode is usually that nothing draws, or misrendering with wild geometry,
which is kind of bad for a common mistake.  And people tend to assume
the range information isn't that important when data is in VBOs.

There's no real advantage, either.  ARB_robust_buffer_access only
requires us to restrict access to the GL buffer object size, not
the range of data we think they should access.  Doing that allows
buggy applications to still function.  (Note that we still use this
information for busy-tracking, so if they try to overwrite the data
with glBufferSubData, they'll still hit a bug.)  This seems to be
safer.

We may want to provide the more strict range as a debug option,
or scan the VBO and warn against bogus glDrawRangeElements in
debug contexts.  That can be done as a later patch, though.

Makes Unreal demos draw again.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_draw_upload.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c 
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index f4d1b2c..bfe20c5 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -543,6 +543,7 @@ brw_prepare_vertices(struct brw_context *brw)
buffer->offset = offset;
buffer->stride = glarray->StrideB;
buffer->step_rate = glarray->InstanceDivisor;
+buffer->size = glarray->BufferObj->Size - offset;
 
 enabled_buffer[j] = intel_buffer;
 buffer_range_start[j] = start;
@@ -610,8 +611,6 @@ brw_prepare_vertices(struct brw_context *brw)
 
   buffer->bo = intel_bufferobj_buffer(brw, enabled_buffer[i], start, 
range);
   drm_intel_bo_reference(buffer->bo);
-
-  buffer->size = start + range;
}
 
/* If we need to upload all the arrays, then we can trim those arrays to

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Mesa (master): nvc0: invalidate textures/ samplers between 3D and CP on Fermi

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: e01a48218205adc280d3da00720dfb3d1ca5bde5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e01a48218205adc280d3da00720dfb3d1ca5bde5

Author: Samuel Pitoiset 
Date:   Thu May 26 23:01:37 2016 +0200

nvc0: invalidate textures/samplers between 3D and CP on Fermi

Like constant buffers, samplers and textures are aliased on Fermi and
we need to invalidate the state when switching from 3D to CP and vice
versa.

This fixes rendering issues in the UE4 demos.

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Ilia Mirkin 

---

 src/gallium/drivers/nouveau/nvc0/nvc0_compute.c | 13 +
 src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 14 ++
 2 files changed, 27 insertions(+)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
index 80d6f38..832c085 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
@@ -124,6 +124,11 @@ nvc0_compute_validate_samplers(struct nvc0_context *nvc0)
   BEGIN_NVC0(nvc0->base.pushbuf, NVC0_CP(TSC_FLUSH), 1);
   PUSH_DATA (nvc0->base.pushbuf, 0);
}
+
+   /* Invalidate all 3D samplers because they are aliased. */
+   for (int s = 0; s < 5; s++)
+  nvc0->samplers_dirty[s] = ~0;
+   nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLERS;
 }
 
 static void
@@ -134,6 +139,14 @@ nvc0_compute_validate_textures(struct nvc0_context *nvc0)
   BEGIN_NVC0(nvc0->base.pushbuf, NVC0_CP(TIC_FLUSH), 1);
   PUSH_DATA (nvc0->base.pushbuf, 0);
}
+
+   /* Invalidate all 3D textures because they are aliased. */
+   for (int s = 0; s < 5; s++) {
+  for (int i = 0; i < nvc0->num_textures[s]; i++)
+ nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
+  nvc0->textures_dirty[s] = ~0;
+   }
+   nvc0->dirty_3d |= NVC0_NEW_3D_TEXTURES;
 }
 
 static void
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
index 2523c20..d36cea7 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
@@ -588,6 +588,14 @@ void nvc0_validate_textures(struct nvc0_context *nvc0)
   BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(TIC_FLUSH), 1);
   PUSH_DATA (nvc0->base.pushbuf, 0);
}
+
+   if (nvc0->screen->base.class_3d < NVE4_3D_CLASS) {
+  /* Invalidate all CP textures because they are aliased. */
+  for (int i = 0; i < nvc0->num_textures[5]; i++)
+ nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_CP_TEX(i));
+  nvc0->textures_dirty[5] = ~0;
+  nvc0->dirty_cp |= NVC0_NEW_CP_TEXTURES;
+   }
 }
 
 bool
@@ -700,6 +708,12 @@ void nvc0_validate_samplers(struct nvc0_context *nvc0)
   BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(TSC_FLUSH), 1);
   PUSH_DATA (nvc0->base.pushbuf, 0);
}
+
+   if (nvc0->screen->base.class_3d < NVE4_3D_CLASS) {
+  /* Invalidate all CP samplers because they are aliased. */
+  nvc0->samplers_dirty[5] = ~0;
+  nvc0->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
+   }
 }
 
 /* Upload the "diagonal" entries for the possible texture sources ($t == $s).

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Mesa (master): compiler: Move glsl_to_nir to libglsl.la

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 32210dea8e474f8e93f5df681fb6a8265a0cda4b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=32210dea8e474f8e93f5df681fb6a8265a0cda4b

Author: Jason Ekstrand 
Date:   Wed May 25 16:00:38 2016 -0700

compiler: Move glsl_to_nir to libglsl.la

Right now libglsl.la depends on libnir.la so putting it in libnir.la
adds a dependency on libglsl.la that goes the wrong direction.

Reviewed-by: Emil Velikov 
Reviewed-by: Kristian Høgsberg 

---

 src/compiler/Android.glsl.mk|  1 +
 src/compiler/Makefile.am|  2 ++
 src/compiler/Makefile.nir.am|  5 -
 src/compiler/Makefile.sources   |  4 ++--
 src/compiler/SConscript.glsl|  3 +++
 src/compiler/{nir => glsl}/glsl_to_nir.cpp  | 10 +-
 src/compiler/{nir => glsl}/glsl_to_nir.h|  2 +-
 src/gallium/drivers/freedreno/ir3/ir3_cmdline.c |  2 +-
 src/mesa/drivers/dri/i965/brw_nir.c |  2 +-
 src/mesa/state_tracker/st_glsl_to_nir.cpp   |  2 +-
 10 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/src/compiler/Android.glsl.mk b/src/compiler/Android.glsl.mk
index 8184d2d..5d2bc18 100644
--- a/src/compiler/Android.glsl.mk
+++ b/src/compiler/Android.glsl.mk
@@ -38,6 +38,7 @@ LOCAL_SRC_FILES := \
$(LIBGLSL_FILES) \
 
 LOCAL_C_INCLUDES := \
+   $(MESA_TOP)/src/compiler/nir \
$(MESA_TOP)/src/mapi \
$(MESA_TOP)/src/mesa \
$(MESA_TOP)/src/gallium/include \
diff --git a/src/compiler/Makefile.am b/src/compiler/Makefile.am
index dc30f90..50e87bb 100644
--- a/src/compiler/Makefile.am
+++ b/src/compiler/Makefile.am
@@ -31,6 +31,8 @@ AM_CPPFLAGS = \
-I$(top_builddir)/src/compiler/glsl\
-I$(top_srcdir)/src/compiler/glsl\
-I$(top_srcdir)/src/compiler/glsl/glcpp\
+   -I$(top_builddir)/src/compiler/nir \
+   -I$(top_srcdir)/src/compiler/nir \
-I$(top_srcdir)/src/gallium/include \
-I$(top_srcdir)/src/gallium/auxiliary \
-I$(top_srcdir)/src/gtest/include \
diff --git a/src/compiler/Makefile.nir.am b/src/compiler/Makefile.nir.am
index 45a9c80..08713a8 100644
--- a/src/compiler/Makefile.nir.am
+++ b/src/compiler/Makefile.nir.am
@@ -23,11 +23,6 @@
 
 noinst_LTLIBRARIES += nir/libnir.la
 
-nir_libnir_la_CPPFLAGS = \
-   $(AM_CPPFLAGS) \
-   -I$(top_builddir)/src/compiler/nir \
-   -I$(top_srcdir)/src/compiler/nir
-
 nir_libnir_la_LIBADD = \
libcompiler.la
 
diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index ebc5953..800e318 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -25,6 +25,8 @@ LIBGLSL_FILES = \
glsl/glsl_parser_extras.h \
glsl/glsl_symbol_table.cpp \
glsl/glsl_symbol_table.h \
+   glsl/glsl_to_nir.cpp \
+   glsl/glsl_to_nir.h \
glsl/hir_field_selection.cpp \
glsl/ir_basic_block.cpp \
glsl/ir_basic_block.h \
@@ -164,8 +166,6 @@ NIR_GENERATED_FILES = \
nir/nir_opt_algebraic.c
 
 NIR_FILES = \
-   nir/glsl_to_nir.cpp \
-   nir/glsl_to_nir.h \
nir/nir.c \
nir/nir.h \
nir/nir_array.h \
diff --git a/src/compiler/SConscript.glsl b/src/compiler/SConscript.glsl
index 474df11..4252ce1 100644
--- a/src/compiler/SConscript.glsl
+++ b/src/compiler/SConscript.glsl
@@ -17,12 +17,15 @@ env.Prepend(CPPPATH = [
 '#src/gallium/auxiliary',
 '#src/compiler/glsl',
 '#src/compiler/glsl/glcpp',
+'#src/compiler/nir',
 ])
 
 env.Prepend(LIBS = [mesautil])
 
 # Make glcpp-parse.h and glsl_parser.h reachable from the include path.
 env.Prepend(CPPPATH = [Dir('.').abspath, Dir('glsl').abspath])
+# Make NIR headers reachable from the include path.
+env.Prepend(CPPPATH = [Dir('.').abspath, Dir('nir').abspath])
 
 glcpp_env = env.Clone()
 glcpp_env.Append(YACCFLAGS = [
diff --git a/src/compiler/nir/glsl_to_nir.cpp 
b/src/compiler/glsl/glsl_to_nir.cpp
similarity index 99%
rename from src/compiler/nir/glsl_to_nir.cpp
rename to src/compiler/glsl/glsl_to_nir.cpp
index 00e3fd5..63a2cfd 100644
--- a/src/compiler/nir/glsl_to_nir.cpp
+++ b/src/compiler/glsl/glsl_to_nir.cpp
@@ -26,11 +26,11 @@
  */
 
 #include "glsl_to_nir.h"
-#include "nir_control_flow.h"
-#include "nir_builder.h"
-#include "compiler/glsl/ir_visitor.h"
-#include "compiler/glsl/ir_hierarchical_visitor.h"
-#include "compiler/glsl/ir.h"
+#include "ir_visitor.h"
+#include "ir_hierarchical_visitor.h"
+#include "ir.h"
+#include "compiler/nir/nir_control_flow.h"
+#include "compiler/nir/nir_builder.h"
 #include "main/imports.h"
 
 /*
diff --git a/src/compiler/nir/glsl_to_nir.h b/src/compiler/glsl/glsl_to_nir.h
similarity index 98%
rename from src/compiler/nir/glsl_to_nir.h
rename to src/compiler/glsl/glsl_to_nir.h
index 14641fc..c63382e 100644
--- a/src/compiler/nir/glsl_to_nir.h
+++ b/src/compiler/glsl/glsl_to_nir.h
@@ -25,7 

Mesa (master): i965/test: Remove the fragment/ vertex_program field from test visitors

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 327161a48dcff9ec082ba5365ffa41bf0cbec3e4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=327161a48dcff9ec082ba5365ffa41bf0cbec3e4

Author: Jason Ekstrand 
Date:   Wed May 25 17:41:59 2016 -0700

i965/test: Remove the fragment/vertex_program field from test visitors

None of them are actually using it.  It's a relic of an older compiler
interface that required a gl_program.

Reviewed-by: Emil Velikov 
Reviewed-by: Kristian Høgsberg 

---

 src/mesa/drivers/dri/i965/test_fs_cmod_propagation.cpp | 4 
 src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp | 4 
 src/mesa/drivers/dri/i965/test_vec4_cmod_propagation.cpp   | 5 -
 src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp   | 5 -
 src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp  | 5 -
 5 files changed, 23 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/test_fs_cmod_propagation.cpp 
b/src/mesa/drivers/dri/i965/test_fs_cmod_propagation.cpp
index 034d8a5..7cd7245 100644
--- a/src/mesa/drivers/dri/i965/test_fs_cmod_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/test_fs_cmod_propagation.cpp
@@ -37,7 +37,6 @@ public:
struct gl_context *ctx;
struct brw_wm_prog_data *prog_data;
struct gl_shader_program *shader_prog;
-   struct brw_fragment_program *fp;
fs_visitor *v;
 };
 
@@ -60,14 +59,11 @@ void cmod_propagation_test::SetUp()
devinfo = (struct brw_device_info *)calloc(1, sizeof(*devinfo));
compiler->devinfo = devinfo;
 
-   fp = ralloc(NULL, struct brw_fragment_program);
prog_data = ralloc(NULL, struct brw_wm_prog_data);
nir_shader *shader = nir_shader_create(NULL, MESA_SHADER_FRAGMENT, NULL);
 
v = new cmod_propagation_fs_visitor(compiler, prog_data, shader);
 
-   _mesa_init_gl_program(>program.Base, GL_FRAGMENT_SHADER, 0);
-
devinfo->gen = 4;
 }
 
diff --git a/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp 
b/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
index 7b3b9e5..06caaad 100644
--- a/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
@@ -37,7 +37,6 @@ public:
struct gl_context *ctx;
struct brw_wm_prog_data *prog_data;
struct gl_shader_program *shader_prog;
-   struct brw_fragment_program *fp;
fs_visitor *v;
 };
 
@@ -60,14 +59,11 @@ void saturate_propagation_test::SetUp()
devinfo = (struct brw_device_info *)calloc(1, sizeof(*devinfo));
compiler->devinfo = devinfo;
 
-   fp = ralloc(NULL, struct brw_fragment_program);
prog_data = ralloc(NULL, struct brw_wm_prog_data);
nir_shader *shader = nir_shader_create(NULL, MESA_SHADER_FRAGMENT, NULL);
 
v = new saturate_propagation_fs_visitor(compiler, prog_data, shader);
 
-   _mesa_init_gl_program(>program.Base, GL_FRAGMENT_SHADER, 0);
-
devinfo->gen = 4;
 }
 
diff --git a/src/mesa/drivers/dri/i965/test_vec4_cmod_propagation.cpp 
b/src/mesa/drivers/dri/i965/test_vec4_cmod_propagation.cpp
index 0b74165..1b6a9e7 100644
--- a/src/mesa/drivers/dri/i965/test_vec4_cmod_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/test_vec4_cmod_propagation.cpp
@@ -39,7 +39,6 @@ public:
struct brw_device_info *devinfo;
struct gl_context *ctx;
struct gl_shader_program *shader_prog;
-   struct brw_vertex_program *vp;
struct brw_vue_prog_data *prog_data;
vec4_visitor *v;
 };
@@ -103,14 +102,10 @@ void cmod_propagation_test::SetUp()
prog_data = (struct brw_vue_prog_data *)calloc(1, sizeof(*prog_data));
compiler->devinfo = devinfo;
 
-   vp = ralloc(NULL, struct brw_vertex_program);
-
nir_shader *shader = nir_shader_create(NULL, MESA_SHADER_VERTEX, NULL);
 
v = new cmod_propagation_vec4_visitor(compiler, shader, prog_data);
 
-   _mesa_init_gl_program(>program.Base, GL_VERTEX_SHADER, 0);
-
devinfo->gen = 4;
 }
 
diff --git a/src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp 
b/src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp
index 0638246..901f12a 100644
--- a/src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp
@@ -38,7 +38,6 @@ public:
struct brw_device_info *devinfo;
struct gl_context *ctx;
struct gl_shader_program *shader_prog;
-   struct brw_vertex_program *vp;
struct brw_vue_prog_data *prog_data;
vec4_visitor *v;
 };
@@ -96,14 +95,10 @@ void copy_propagation_test::SetUp()
prog_data = (struct brw_vue_prog_data *)calloc(1, sizeof(*prog_data));
compiler->devinfo = devinfo;
 
-   vp = ralloc(NULL, struct brw_vertex_program);
-
nir_shader *shader = nir_shader_create(NULL, MESA_SHADER_VERTEX, NULL);
 
v = new copy_propagation_vec4_visitor(compiler, shader, prog_data);
 
-   _mesa_init_gl_program(>program.Base, GL_VERTEX_SHADER, 0);
-
devinfo->gen = 4;
 }
 
diff --git a/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp 

Mesa (master): i965: Move compiler debug functions to intel_screen.c

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 870ff6cd3829b1f15f1aa636be17c1ffb371a290
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=870ff6cd3829b1f15f1aa636be17c1ffb371a290

Author: Jason Ekstrand 
Date:   Wed May 25 18:19:50 2016 -0700

i965: Move compiler debug functions to intel_screen.c

They reference the compiler so they shouldn't go in libi965_compiler.la.

Reviewed-by: Emil Velikov 
Reviewed-by: Kristian Høgsberg 

---

 src/mesa/drivers/dri/i965/brw_compiler.c | 42 
 src/mesa/drivers/dri/i965/intel_screen.c | 42 
 2 files changed, 42 insertions(+), 42 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_compiler.c 
b/src/mesa/drivers/dri/i965/brw_compiler.c
index 3f17589..a4855a0 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.c
+++ b/src/mesa/drivers/dri/i965/brw_compiler.c
@@ -27,46 +27,6 @@
 #include "main/errors.h"
 #include "util/debug.h"
 
-static void
-shader_debug_log_mesa(void *data, const char *fmt, ...)
-{
-   struct brw_context *brw = (struct brw_context *)data;
-   va_list args;
-
-   va_start(args, fmt);
-   GLuint msg_id = 0;
-   _mesa_gl_vdebug(>ctx, _id,
-   MESA_DEBUG_SOURCE_SHADER_COMPILER,
-   MESA_DEBUG_TYPE_OTHER,
-   MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
-   va_end(args);
-}
-
-static void
-shader_perf_log_mesa(void *data, const char *fmt, ...)
-{
-   struct brw_context *brw = (struct brw_context *)data;
-
-   va_list args;
-   va_start(args, fmt);
-
-   if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
-  va_list args_copy;
-  va_copy(args_copy, args);
-  vfprintf(stderr, fmt, args_copy);
-  va_end(args_copy);
-   }
-
-   if (brw->perf_debug) {
-  GLuint msg_id = 0;
-  _mesa_gl_vdebug(>ctx, _id,
-  MESA_DEBUG_SOURCE_SHADER_COMPILER,
-  MESA_DEBUG_TYPE_PERFORMANCE,
-  MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
-   }
-   va_end(args);
-}
-
 #define COMMON_OPTIONS\
.lower_sub = true, \
.lower_fdiv = true,\
@@ -139,8 +99,6 @@ brw_compiler_create(void *mem_ctx, const struct 
brw_device_info *devinfo)
struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
 
compiler->devinfo = devinfo;
-   compiler->shader_debug_log = shader_debug_log_mesa;
-   compiler->shader_perf_log = shader_perf_log_mesa;
 
brw_fs_alloc_reg_sets(compiler);
brw_vec4_alloc_reg_set(compiler);
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 4f14201..2f8fed5 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1467,6 +1467,46 @@ brw_get_revision(int fd)
 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
 #endif
 
+static void
+shader_debug_log_mesa(void *data, const char *fmt, ...)
+{
+   struct brw_context *brw = (struct brw_context *)data;
+   va_list args;
+
+   va_start(args, fmt);
+   GLuint msg_id = 0;
+   _mesa_gl_vdebug(>ctx, _id,
+   MESA_DEBUG_SOURCE_SHADER_COMPILER,
+   MESA_DEBUG_TYPE_OTHER,
+   MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
+   va_end(args);
+}
+
+static void
+shader_perf_log_mesa(void *data, const char *fmt, ...)
+{
+   struct brw_context *brw = (struct brw_context *)data;
+
+   va_list args;
+   va_start(args, fmt);
+
+   if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
+  va_list args_copy;
+  va_copy(args_copy, args);
+  vfprintf(stderr, fmt, args_copy);
+  va_end(args_copy);
+   }
+
+   if (brw->perf_debug) {
+  GLuint msg_id = 0;
+  _mesa_gl_vdebug(>ctx, _id,
+  MESA_DEBUG_SOURCE_SHADER_COMPILER,
+  MESA_DEBUG_TYPE_PERFORMANCE,
+  MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
+   }
+   va_end(args);
+}
+
 /**
  * This is the driver specific part of the createNewScreen entry point.
  * Called when using DRI2.
@@ -1579,6 +1619,8 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp)
 
intelScreen->compiler = brw_compiler_create(intelScreen,
intelScreen->devinfo);
+   intelScreen->compiler->shader_debug_log = shader_debug_log_mesa;
+   intelScreen->compiler->shader_perf_log = shader_perf_log_mesa;
intelScreen->program_id = 1;
 
if (intelScreen->devinfo->has_resource_streamer) {

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Mesa (master): i965: Move brw_new_shader to brw_link.cpp

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: e0ae10c49ae7c7c93ba076ee1088e3d829173f46
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e0ae10c49ae7c7c93ba076ee1088e3d829173f46

Author: Jason Ekstrand 
Date:   Wed May 25 17:46:07 2016 -0700

i965: Move brw_new_shader to brw_link.cpp

That's where brw_link_shader lives and they seem to go together.  Also,
this gets it out of libi965_compiler.

Reviewed-by: Emil Velikov 
Reviewed-by: Kristian Høgsberg 

---

 src/mesa/drivers/dri/i965/brw_link.cpp   | 17 +
 src/mesa/drivers/dri/i965/brw_shader.cpp | 17 -
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index c169658..16bfbaa 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -31,6 +31,7 @@
 #include "compiler/glsl/program.h"
 #include "program/program.h"
 #include "main/shaderapi.h"
+#include "main/shaderobj.h"
 #include "main/uniforms.h"
 
 /**
@@ -183,6 +184,22 @@ process_glsl_ir(gl_shader_stage stage,
}
 }
 
+extern "C" struct gl_shader *
+brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
+{
+   struct brw_shader *shader;
+
+   shader = rzalloc(NULL, struct brw_shader);
+   if (shader) {
+  shader->base.Type = type;
+  shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
+  shader->base.Name = name;
+  _mesa_init_shader(ctx, >base);
+   }
+
+   return >base;
+}
+
 extern "C" GLboolean
 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 {
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp 
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index fa8cf88..d24db58 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -27,25 +27,8 @@
 #include "brw_fs.h"
 #include "brw_nir.h"
 #include "brw_vec4_tes.h"
-#include "main/shaderobj.h"
 #include "main/uniforms.h"
 
-extern "C" struct gl_shader *
-brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
-{
-   struct brw_shader *shader;
-
-   shader = rzalloc(NULL, struct brw_shader);
-   if (shader) {
-  shader->base.Type = type;
-  shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
-  shader->base.Name = name;
-  _mesa_init_shader(ctx, >base);
-   }
-
-   return >base;
-}
-
 extern "C" void
 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
   unsigned surf_index)

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Mesa (master): i965: Don't link libmesa or libdri_test_stubs into tests

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 057259655e79f6adfa79b71b0ee181dcae5454de
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=057259655e79f6adfa79b71b0ee181dcae5454de

Author: Jason Ekstrand 
Date:   Wed May 25 17:51:59 2016 -0700

i965: Don't link libmesa or libdri_test_stubs into tests

Now that the compiler has been completely separated from libmesa, we no
longer need these.  We can make the tests much smaller by not linking them
in.  This also ensures that anyone who runs make check won't accidentally
put in any dependencies from the compiler to the rest of mesa core.

Reviewed-by: Emil Velikov 
Reviewed-by: Kristian Høgsberg 

---

 src/mesa/drivers/dri/i965/Makefile.am | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/Makefile.am 
b/src/mesa/drivers/dri/i965/Makefile.am
index 9a990d2..0a5222e 100644
--- a/src/mesa/drivers/dri/i965/Makefile.am
+++ b/src/mesa/drivers/dri/i965/Makefile.am
@@ -66,11 +66,11 @@ EXTRA_DIST = \
 
 TEST_LIBS = \
libi965_compiler.la \
-../../../libmesa.la \
+   $(top_builddir)/src/compiler/nir/libnir.la \
+   $(top_builddir)/src/util/libmesautil.la \
$(top_builddir)/src/intel/isl/libisl.la \
$(PTHREAD_LIBS) \
-   $(DLOPEN_LIBS) \
-   ../common/libdri_test_stubs.la
+   $(DLOPEN_LIBS)
 
 TESTS = \
test_fs_cmod_propagation \

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Mesa (master): i965: Move brw_nir_lower_uniforms.cpp to i965_FILES

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 5136b67915ffbafa1715e08be4bd714c6ff540b3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5136b67915ffbafa1715e08be4bd714c6ff540b3

Author: Jason Ekstrand 
Date:   Wed May 25 17:29:38 2016 -0700

i965: Move brw_nir_lower_uniforms.cpp to i965_FILES

This gets it out of i965_compiler.la

Reviewed-by: Emil Velikov 
Reviewed-by: Kristian Høgsberg 

---

 src/mesa/drivers/dri/i965/Makefile.sources | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 01f2ef6..d8711ed 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -47,7 +47,6 @@ i965_compiler_FILES = \
brw_nir_analyze_boolean_resolves.c \
brw_nir_attribute_workarounds.c \
brw_nir_opt_peephole_ffma.c \
-   brw_nir_uniforms.cpp \
brw_packed_float.c \
brw_predicated_break.cpp \
brw_reg.h \
@@ -138,6 +137,7 @@ i965_FILES = \
brw_meta_util.h \
brw_misc_state.c \
brw_multisample_state.h \
+   brw_nir_uniforms.cpp \
brw_object_purgeable.c \
brw_performance_monitor.c \
brw_pipe_control.c \

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Mesa (master): anv: Stop linking against libmesa.la and libdri_test_stubs.la

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 9f0bc0f2b311f719090701a345428bd42bf79488
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f0bc0f2b311f719090701a345428bd42bf79488

Author: Jason Ekstrand 
Date:   Wed May 25 18:20:40 2016 -0700

anv: Stop linking against libmesa.la and libdri_test_stubs.la

This brings the final size of an optimized non-debug build of the Vulkan
driver down to 2.9 MB as opposed to 8.7 MB for the dri driver.

Reviewed-by: Emil Velikov 
Reviewed-by: Kristian Høgsberg 

---

 src/intel/vulkan/Makefile.am | 6 +++---
 src/intel/vulkan/TODO| 1 -
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/intel/vulkan/Makefile.am b/src/intel/vulkan/Makefile.am
index 662d720..8c6ce18 100644
--- a/src/intel/vulkan/Makefile.am
+++ b/src/intel/vulkan/Makefile.am
@@ -112,10 +112,10 @@ libvulkan_common_la_SOURCES = $(VULKAN_SOURCES)
 
 VULKAN_LIB_DEPS += \
libvulkan_common.la \
-   $(top_builddir)/src/intel/isl/libisl.la \
$(top_builddir)/src/mesa/drivers/dri/i965/libi965_compiler.la \
-   $(top_builddir)/src/mesa/libmesa.la \
-   $(top_builddir)/src/mesa/drivers/dri/common/libdri_test_stubs.la \
+   $(top_builddir)/src/compiler/nir/libnir.la \
+   $(top_builddir)/src/util/libmesautil.la \
+   $(top_builddir)/src/intel/isl/libisl.la \
$(PER_GEN_LIBS) \
$(PTHREAD_LIBS) \
$(DLOPEN_LIBS) \
diff --git a/src/intel/vulkan/TODO b/src/intel/vulkan/TODO
index 197bf0c..8fac370 100644
--- a/src/intel/vulkan/TODO
+++ b/src/intel/vulkan/TODO
@@ -30,5 +30,4 @@ Performance:
  - Use soft-pin to avoid relocations
 
 Cleanups:
- - Drop libmesa.la
  - Deduplicate gen7 and gen8

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Mesa (master): ptn: Include nir.h

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 58d1e82d32ccdbcda4dbf96c8fdef827ad076c10
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=58d1e82d32ccdbcda4dbf96c8fdef827ad076c10

Author: Jason Ekstrand 
Date:   Wed May 25 17:27:57 2016 -0700

ptn: Include nir.h

Reviewed-by: Emil Velikov 
Reviewed-by: Kristian Høgsberg 

---

 src/mesa/program/prog_to_nir.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/program/prog_to_nir.h b/src/mesa/program/prog_to_nir.h
index 34e4cd1..09425b5 100644
--- a/src/mesa/program/prog_to_nir.h
+++ b/src/mesa/program/prog_to_nir.h
@@ -24,6 +24,9 @@
 #pragma once
 #ifndef PROG_TO_NIR_H
 #define PROG_TO_NIR_H
+
+#include "compiler/nir/nir.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif

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Mesa (master): i965/nir: Move the type_size_*_bytes functions to brw_nir.h

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 86a2447eec7e87e46e842ca7a3ad5cd9fadb1ca5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=86a2447eec7e87e46e842ca7a3ad5cd9fadb1ca5

Author: Jason Ekstrand 
Date:   Wed May 25 17:26:42 2016 -0700

i965/nir: Move the type_size_*_bytes functions to brw_nir.h

Reviewed-by: Emil Velikov 
Reviewed-by: Kristian Høgsberg 

---

 src/mesa/drivers/dri/i965/brw_nir.c | 12 
 src/mesa/drivers/dri/i965/brw_nir.h | 13 +
 2 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_nir.c 
b/src/mesa/drivers/dri/i965/brw_nir.c
index 45551a1..62ed0e8 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -337,18 +337,6 @@ brw_nir_lower_fs_outputs(nir_shader *nir)
nir_lower_io(nir, nir_var_shader_out, type_size_scalar);
 }
 
-static int
-type_size_scalar_bytes(const struct glsl_type *type)
-{
-   return type_size_scalar(type) * 4;
-}
-
-static int
-type_size_vec4_bytes(const struct glsl_type *type)
-{
-   return type_size_vec4(type) * 16;
-}
-
 static void
 brw_nir_lower_uniforms(nir_shader *nir, bool is_scalar)
 {
diff --git a/src/mesa/drivers/dri/i965/brw_nir.h 
b/src/mesa/drivers/dri/i965/brw_nir.h
index 2711606..041f337 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.h
+++ b/src/mesa/drivers/dri/i965/brw_nir.h
@@ -25,12 +25,25 @@
 
 #include "brw_context.h"
 #include "brw_reg.h"
+#include "brw_shader.h"
 #include "compiler/nir/nir.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+static inline int
+type_size_scalar_bytes(const struct glsl_type *type)
+{
+   return type_size_scalar(type) * 4;
+}
+
+static inline int
+type_size_vec4_bytes(const struct glsl_type *type)
+{
+   return type_size_vec4(type) * 16;
+}
+
 /* Flags set in the instr->pass_flags field by i965 analysis passes */
 enum {
BRW_NIR_NON_BOOLEAN   = 0x0,

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Mesa (master): i965: Move brw_create_nir to brw_program.c

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 5e43ba7e9e9bfce451f9caa3845136f8a5b6eda0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e43ba7e9e9bfce451f9caa3845136f8a5b6eda0

Author: Jason Ekstrand 
Date:   Wed May 25 17:27:23 2016 -0700

i965: Move brw_create_nir to brw_program.c

This way it's no longer part of libi965_compiler.la since it depends on
GLSL and ARB program stuff.

Reviewed-by: Emil Velikov 
Reviewed-by: Kristian Høgsberg 

---

 src/mesa/drivers/dri/i965/brw_nir.c | 70 -
 src/mesa/drivers/dri/i965/brw_nir.h |  6 ---
 src/mesa/drivers/dri/i965/brw_program.c | 68 
 src/mesa/drivers/dri/i965/brw_program.h |  6 +++
 4 files changed, 74 insertions(+), 76 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_nir.c 
b/src/mesa/drivers/dri/i965/brw_nir.c
index 62ed0e8..e01f160 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -24,10 +24,7 @@
 #include "brw_nir.h"
 #include "brw_shader.h"
 #include "compiler/glsl_types.h"
-#include "compiler/glsl/glsl_to_nir.h"
 #include "compiler/nir/nir_builder.h"
-#include "program/prog_to_nir.h"
-#include "program/prog_parameter.h"
 
 static bool
 is_input(nir_intrinsic_instr *intrin)
@@ -337,20 +334,6 @@ brw_nir_lower_fs_outputs(nir_shader *nir)
nir_lower_io(nir, nir_var_shader_out, type_size_scalar);
 }
 
-static void
-brw_nir_lower_uniforms(nir_shader *nir, bool is_scalar)
-{
-   if (is_scalar) {
-  nir_assign_var_locations(>uniforms, >num_uniforms,
-   type_size_scalar_bytes);
-  nir_lower_io(nir, nir_var_uniform, type_size_scalar_bytes);
-   } else {
-  nir_assign_var_locations(>uniforms, >num_uniforms,
-   type_size_vec4_bytes);
-  nir_lower_io(nir, nir_var_uniform, type_size_vec4_bytes);
-   }
-}
-
 void
 brw_nir_lower_cs_shared(nir_shader *nir)
 {
@@ -534,59 +517,6 @@ brw_postprocess_nir(nir_shader *nir,
 }
 
 nir_shader *
-brw_create_nir(struct brw_context *brw,
-   const struct gl_shader_program *shader_prog,
-   const struct gl_program *prog,
-   gl_shader_stage stage,
-   bool is_scalar)
-{
-   struct gl_context *ctx = >ctx;
-   const nir_shader_compiler_options *options =
-  ctx->Const.ShaderCompilerOptions[stage].NirOptions;
-   bool progress;
-   nir_shader *nir;
-
-   /* First, lower the GLSL IR or Mesa IR to NIR */
-   if (shader_prog) {
-  nir = glsl_to_nir(shader_prog, stage, options);
-  nir_remove_dead_variables(nir, nir_var_shader_in | nir_var_shader_out);
-  OPT_V(nir_lower_io_to_temporaries,
-nir_shader_get_entrypoint(nir),
-true, false);
-   } else {
-  nir = prog_to_nir(prog, options);
-  OPT_V(nir_convert_to_ssa); /* turn registers into SSA */
-   }
-   nir_validate_shader(nir);
-
-   (void)progress;
-
-   nir = brw_preprocess_nir(brw->intelScreen->compiler, nir);
-
-   if (stage == MESA_SHADER_FRAGMENT) {
-  static const struct nir_lower_wpos_ytransform_options wpos_options = {
- .state_tokens = {STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0},
- .fs_coord_pixel_center_integer = 1,
- .fs_coord_origin_upper_left = 1,
-  };
-  _mesa_add_state_reference(prog->Parameters,
-(gl_state_index *) wpos_options.state_tokens);
-
-  OPT(nir_lower_wpos_ytransform, _options);
-   }
-
-   OPT(nir_lower_system_values);
-   OPT_V(brw_nir_lower_uniforms, is_scalar);
-
-   if (shader_prog) {
-  OPT_V(nir_lower_samplers, shader_prog);
-  OPT_V(nir_lower_atomics, shader_prog);
-   }
-
-   return nir;
-}
-
-nir_shader *
 brw_nir_apply_sampler_key(nir_shader *nir,
   const struct brw_device_info *devinfo,
   const struct brw_sampler_prog_key_data *key_tex,
diff --git a/src/mesa/drivers/dri/i965/brw_nir.h 
b/src/mesa/drivers/dri/i965/brw_nir.h
index 041f337..409e49a 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.h
+++ b/src/mesa/drivers/dri/i965/brw_nir.h
@@ -88,12 +88,6 @@ enum {
 
 void brw_nir_analyze_boolean_resolves(nir_shader *nir);
 
-nir_shader *brw_create_nir(struct brw_context *brw,
-   const struct gl_shader_program *shader_prog,
-   const struct gl_program *prog,
-   gl_shader_stage stage,
-   bool is_scalar);
-
 nir_shader *brw_preprocess_nir(const struct brw_compiler *compiler,
nir_shader *nir);
 
diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index 3112c0c..792f81b 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -33,11 +33,13 @@
 #include "main/imports.h"
 #include "program/prog_parameter.h"
 #include "program/prog_print.h"

Mesa (master): i965/sklgt4: Implement depth/timestamp write w/a

[Ben Widawsky]

Module: Mesa
Branch: master
Commit: ddcfc35f62ed3ad83b100beacb5b30394dcd9960
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ddcfc35f62ed3ad83b100beacb5b30394dcd9960

Author: Ben Widawsky 
Date:   Thu May 26 11:04:07 2016 -0700

i965/sklgt4: Implement depth/timestamp write w/a

The stated bug describes a scenario in which a post sync write operation for
depth or timestamp can be ignored. There are two workarounds suggested, the
first and easier is to simply do a cs stall when we do these type of writes.
The second option is to do a PIPE_CONTROL flush after the post sync but before
the data is required.

Generally, I believe the data written out is consumed by the application on the
CPU side and so doing the easier of the two is ideal. Furthermore, these queries
aren't tremendously common in the perf sensitive apps I have looked at. However,
there could be cases where a shader stage might directly consume the data, and
as a result option 2 may be desirable.

This patch goes with the easier solution for now.

gen9lp bug_de_id=2137196

By itself, this does *not* fix any of the GT4 hangs we're currently
experiencing.

Cc: Mika Kuoppala 
Signed-off-by: Ben Widawsky 
Reviewed-by: Anuj Phogat 

---

 src/mesa/drivers/dri/i965/brw_queryobj.c | 16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c 
b/src/mesa/drivers/dri/i965/brw_queryobj.c
index f32721b..7baa213 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -56,7 +56,12 @@ brw_write_timestamp(struct brw_context *brw, drm_intel_bo 
*query_bo, int idx)
   PIPE_CONTROL_STALL_AT_SCOREBOARD);
}
 
-   brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_TIMESTAMP,
+   uint32_t flags = PIPE_CONTROL_WRITE_TIMESTAMP;
+
+   if (brw->gen == 9 && brw->gt == 4)
+  flags |= PIPE_CONTROL_CS_STALL;
+
+   brw_emit_pipe_control_write(brw, flags,
query_bo, idx * sizeof(uint64_t), 0, 0);
 }
 
@@ -66,9 +71,12 @@ brw_write_timestamp(struct brw_context *brw, drm_intel_bo 
*query_bo, int idx)
 void
 brw_write_depth_count(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
 {
-   brw_emit_pipe_control_write(brw,
-   PIPE_CONTROL_WRITE_DEPTH_COUNT |
-   PIPE_CONTROL_DEPTH_STALL,
+   uint32_t flags = PIPE_CONTROL_WRITE_DEPTH_COUNT | PIPE_CONTROL_DEPTH_STALL;
+
+   if (brw->gen == 9 && brw->gt == 4)
+  flags |= PIPE_CONTROL_CS_STALL;
+
+   brw_emit_pipe_control_write(brw, flags,
query_bo, idx * sizeof(uint64_t),
0, 0);
 }

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Mesa (master): i965/bxt: Add 2x6 variant

[Ben Widawsky]

Module: Mesa
Branch: master
Commit: f1fa8b4a1ca73fac4400e13b9aaca8c6b2955d2c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f1fa8b4a1ca73fac4400e13b9aaca8c6b2955d2c

Author: Ben Widawsky 
Date:   Thu May 26 08:08:29 2016 -0700

i965/bxt: Add 2x6 variant

Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Ben Widawsky 
Reviewed-by: Kristian Høgsberg 

---

 include/pci_ids/i965_pci_ids.h  |  2 ++
 src/mesa/drivers/dri/i965/brw_device_info.c | 22 ++
 2 files changed, 24 insertions(+)

diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index bd645fa..fce00da 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -162,4 +162,6 @@ CHIPSET(0x22B2, chv, "Intel(R) HD Graphics 
(Cherryview)")
 CHIPSET(0x22B3, chv, "Intel(R) HD Graphics (Cherryview)")
 CHIPSET(0x0A84, bxt, "Intel(R) HD Graphics (Broxton)")
 CHIPSET(0x1A84, bxt, "Intel(R) HD Graphics (Broxton)")
+CHIPSET(0x1A85, bxt_2x6, "Intel(R) HD Graphics (Broxton 2x6)")
 CHIPSET(0x5A84, bxt, "Intel(R) HD Graphics (Broxton)")
+CHIPSET(0x5A85, bxt_2x6, "Intel(R) HD Graphics (Broxton 2x6)")
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c 
b/src/mesa/drivers/dri/i965/brw_device_info.c
index 3666190..77bbe78 100644
--- a/src/mesa/drivers/dri/i965/brw_device_info.c
+++ b/src/mesa/drivers/dri/i965/brw_device_info.c
@@ -401,6 +401,28 @@ static const struct brw_device_info brw_device_info_bxt = {
}
 };
 
+static const struct brw_device_info brw_device_info_bxt_2x6 = {
+   GEN9_FEATURES,
+   .is_broxton = 1,
+   .gt = 1,
+   .has_llc = false,
+
+   .num_slices = 1,
+   .max_vs_threads = 56, /* XXX: guess */
+   .max_hs_threads = 56, /* XXX: guess */
+   .max_ds_threads = 56,
+   .max_gs_threads = 56,
+   .max_wm_threads = 64 * 2,
+   .max_cs_threads = 6 * 6,
+   .urb = {
+  .size = 128,
+  .min_vs_entries = 34,
+  .max_vs_entries = 352,
+  .max_hs_entries = 128,
+  .max_ds_entries = 208,
+  .max_gs_entries = 128,
+   }
+};
 /*
  * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
  * There's no KBL entry. Using the default SKL (GEN9) GS entries value.

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Mesa (master): radeonsi: Allow TES distribution between shader engines.

[Bas Nieuwenhuizen]

Module: Mesa
Branch: master
Commit: 43d7305a405c82e81c9b7b3cc4958169b13777bb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=43d7305a405c82e81c9b7b3cc4958169b13777bb

Author: Bas Nieuwenhuizen 
Date:   Tue Apr 12 20:28:46 2016 +0200

radeonsi: Allow TES distribution between shader engines.

The R_028B50_VGT_TESS_DISTRIBUTION value is copied from
amdgpu-pro. Smaller values in the ACCUM fields seem to
decrease the performance advantage from this patch, higher
values don't seem to matter.

v2: Add distribution mode field enums.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_state.c |  5 
 src/gallium/drivers/radeonsi/si_state_draw.c|  8 +
 src/gallium/drivers/radeonsi/si_state_shaders.c | 39 +++--
 src/gallium/drivers/radeonsi/sid.h  |  3 ++
 4 files changed, 40 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index aefa336..ab321ef 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3791,6 +3791,11 @@ static void si_init_config(struct si_context *sctx)
   S_028424_OVERWRITE_COMBINER_WATERMARK(4));
si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
+   si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION,
+  S_028B50_ACCUM_ISOLINE(32) |
+  S_028B50_ACCUM_TRI(11) |
+  S_028B50_ACCUM_QUAD(11) |
+  S_028B50_DONUT_SPLIT(16));
}
 
if (sctx->b.family == CHIP_STONEY)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c 
b/src/gallium/drivers/radeonsi/si_state_draw.c
index c8b87a9..788869e 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -279,6 +279,14 @@ static unsigned si_get_ia_multi_vgt_param(struct 
si_context *sctx,
 sctx->b.family == CHIP_BONAIRE) &&
sctx->gs_shader.cso)
partial_vs_wave = true;
+
+   /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
+   if (sctx->b.chip_class >= VI) {
+   if (sctx->gs_shader.cso)
+   partial_es_wave = true;
+   else
+   partial_vs_wave = true;
+   }
}
 
/* This is a hardware requirement. */
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c 
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 116bf27..c6f51ea 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -249,7 +249,8 @@ void si_destroy_shader_cache(struct si_screen *sscreen)
 
 /* SHADER STATES */
 
-static void si_set_tesseval_regs(struct si_shader *shader,
+static void si_set_tesseval_regs(struct si_screen *sscreen,
+struct si_shader *shader,
 struct si_pm4_state *pm4)
 {
struct tgsi_shader_info *info = >selector->info;
@@ -257,7 +258,7 @@ static void si_set_tesseval_regs(struct si_shader *shader,
unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
bool tes_vertex_order_cw = 
info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
-   unsigned type, partitioning, topology;
+   unsigned type, partitioning, topology, distribution_mode;
 
switch (tes_prim_mode) {
case PIPE_PRIM_LINES:
@@ -299,10 +300,16 @@ static void si_set_tesseval_regs(struct si_shader *shader,
else
topology = V_028B6C_OUTPUT_TRIANGLE_CW;
 
+   if (sscreen->b.chip_class >= VI)
+   distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
+   else
+   distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
+
si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
   S_028B6C_TYPE(type) |
   S_028B6C_PARTITIONING(partitioning) |
-  S_028B6C_TOPOLOGY(topology));
+  S_028B6C_TOPOLOGY(topology) |
+  S_028B6C_DISTRIBUTION_MODE(distribution_mode));
 }
 
 static void si_shader_ls(struct si_shader *shader)
@@ -359,7 +366,7 @@ static void si_shader_hs(struct si_shader *shader)
   
S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
 }
 
-static void si_shader_es(struct si_shader *shader)
+static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
 {
struct si_pm4_state *pm4;
   

Mesa (master): radeonsi: Use correct parameter index for LS_OUT_LAYOUT.

[Bas Nieuwenhuizen]

Module: Mesa
Branch: master
Commit: d9a0c54f6f9811cfe6411a0ed4af8a1086b01b9d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d9a0c54f6f9811cfe6411a0ed4af8a1086b01b9d

Author: Bas Nieuwenhuizen 
Date:   Sun May  1 20:35:40 2016 +0200

radeonsi: Use correct parameter index for LS_OUT_LAYOUT.

This happens to be in the right position, but that changes
when TCS/TES get new parameters.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_shader.h | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.h 
b/src/gallium/drivers/radeonsi/si_shader.h
index 61ddcd1..7b1cbf9 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -141,8 +141,10 @@ enum {
SI_PARAM_VERTEX_BUFFERS = SI_NUM_RESOURCE_PARAMS,
SI_PARAM_BASE_VERTEX,
SI_PARAM_START_INSTANCE,
-   /* [0] = clamp vertex color */
+   /* [0] = clamp vertex color, VS as VS only */
SI_PARAM_VS_STATE_BITS,
+   /* same value as TCS_IN_LAYOUT, VS as LS only */
+   SI_PARAM_LS_OUT_LAYOUT = SI_PARAM_START_INSTANCE + 1,
/* the other VS parameters are assigned dynamically */
 
/* Offsets where TCS outputs and TCS patch outputs live in LDS:
@@ -163,10 +165,9 @@ enum {
 *   [13:20] = stride between vertices in dwords = num_inputs * 4, max 
= 32*4
 */
SI_PARAM_TCS_IN_LAYOUT,  /* TCS only */
-   SI_PARAM_LS_OUT_LAYOUT,  /* same value as TCS_IN_LAYOUT, LS only */
 
/* TCS only parameters. */
-   SI_PARAM_TCS_OC_LDS = SI_PARAM_TCS_IN_LAYOUT + 1,
+   SI_PARAM_TCS_OC_LDS,
SI_PARAM_TESS_FACTOR_OFFSET,
SI_PARAM_PATCH_ID,
SI_PARAM_REL_IDS,

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Mesa (master): radeonsi: Add barrier before writing the tess factors.

[Bas Nieuwenhuizen]

Module: Mesa
Branch: master
Commit: fd0a7a382f2accea67396584826f5f8e40239ef3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fd0a7a382f2accea67396584826f5f8e40239ef3

Author: Bas Nieuwenhuizen 
Date:   Thu May 26 14:09:43 2016 +0200

radeonsi: Add barrier before writing the tess factors.

The factors may be stored to LDs by another invocation than
the invocation for vertex 0.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_shader.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 166b2e8..5e5bf68 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -144,6 +144,10 @@ static void si_init_shader_ctx(struct si_shader_context 
*ctx,
   struct si_shader *shader,
   LLVMTargetMachineRef tm);
 
+static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
+struct lp_build_tgsi_context *bld_base,
+struct lp_build_emit_data *emit_data);
+
 /* Ideally pass the sample mask input to the PS epilog as v13, which
  * is its usual location, so that the shader doesn't have to add v_mov.
  */
@@ -2534,6 +2538,8 @@ static void si_write_tess_factors(struct 
lp_build_tgsi_context *bld_base,
unsigned stride, outer_comps, inner_comps, i;
struct lp_build_if_state if_ctx, inner_if_ctx;
 
+   si_llvm_emit_barrier(NULL, bld_base, NULL);
+
/* Do this only for invocation 0, because the tess levels are per-patch,
 * not per-vertex.
 *

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Mesa (master): radeonsi: Add offchip tessellation parameters.

[Bas Nieuwenhuizen]

Module: Mesa
Branch: master
Commit: 5c34562d7ce5d278c2948b4f27d16fcb3e4fd22d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c34562d7ce5d278c2948b4f27d16fcb3e4fd22d

Author: Bas Nieuwenhuizen 
Date:   Mon May  2 13:20:43 2016 +0200

radeonsi: Add offchip tessellation parameters.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_shader.c| 28 -
 src/gallium/drivers/radeonsi/si_shader.h|  3 ++-
 src/gallium/drivers/radeonsi/si_state_shaders.c |  9 
 3 files changed, 34 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 3df7820..1f162b5 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -91,6 +91,12 @@ struct si_shader_context
int param_tes_rel_patch_id;
int param_tes_patch_id;
int param_es2gs_offset;
+   int param_oc_lds;
+
+   /* Sets a bit if the dynamic HS control word was 0x8000. The bit is
+* 0x80 for VS, 0x1 for ES.
+*/
+   int param_tess_offchip;
 
LLVMTargetMachineRef tm;
 
@@ -2326,14 +2332,14 @@ static void si_llvm_emit_tcs_epilogue(struct 
lp_build_tgsi_context *bld_base)
tf_soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
  SI_PARAM_TESS_FACTOR_OFFSET);
ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
-  SI_TCS_NUM_USER_SGPR, "");
+  SI_TCS_NUM_USER_SGPR + 1, "");
 
/* VGPRs */
rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, 
invocation_id);
tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, 
tf_lds_offset);
 
-   vgpr = SI_TCS_NUM_USER_SGPR + 1;
+   vgpr = SI_TCS_NUM_USER_SGPR + 2;
ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, 
"");
ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, 
"");
ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, 
"");
@@ -4945,7 +4951,11 @@ static void declare_streamout_params(struct 
si_shader_context *ctx,
 
/* Streamout SGPRs. */
if (so->num_outputs) {
-   params[ctx->param_streamout_config = (*num_params)++] = i32;
+   if (ctx->type != PIPE_SHADER_TESS_EVAL)
+   params[ctx->param_streamout_config = (*num_params)++] = 
i32;
+   else
+   ctx->param_streamout_config = ctx->param_tess_offchip;
+
params[ctx->param_streamout_write_index = (*num_params)++] = 
i32;
}
/* A streamout buffer offset is loaded if the stride is non-zero. */
@@ -5065,6 +5075,7 @@ static void create_function(struct si_shader_context *ctx)
params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
+   params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
 
@@ -5074,8 +5085,10 @@ static void create_function(struct si_shader_context 
*ctx)
num_params = SI_PARAM_REL_IDS+1;
 
if (!ctx->is_monolithic) {
-   /* PARAM_TESS_FACTOR_OFFSET is after user SGPRs. */
-   for (i = 0; i <= SI_TCS_NUM_USER_SGPR; i++)
+   /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
+* placed after the user SGPRs.
+*/
+   for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
returns[num_returns++] = ctx->i32; /* SGPRs */
 
for (i = 0; i < 3; i++)
@@ -5089,10 +5102,14 @@ static void create_function(struct si_shader_context 
*ctx)
num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
 
if (shader->key.tes.as_es) {
+   params[ctx->param_oc_lds = num_params++] = ctx->i32;
+   params[ctx->param_tess_offchip = num_params++] = 
ctx->i32;
params[ctx->param_es2gs_offset = num_params++] = 
ctx->i32;
} else {
+   params[ctx->param_tess_offchip = num_params++] = 
ctx->i32;
declare_streamout_params(ctx, >selector->so,
 params, ctx->i32, _params);
+   params[ctx->param_oc_lds = num_params++] = ctx->i32;
}
 

Mesa (master): radeonsi: Add offchip buffer address calculation.

[Bas Nieuwenhuizen]

Module: Mesa
Branch: master
Commit: 7846fa876820fde373b4402e5d1cf3d24f06d11f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7846fa876820fde373b4402e5d1cf3d24f06d11f

Author: Bas Nieuwenhuizen 
Date:   Tue May 10 00:49:39 2016 +0200

radeonsi: Add offchip buffer address calculation.

Instead of creating a memory area per patch and per vertex, we put
the same attribute of every vertex & patch together. Most loads
and stores access the same attribute across all lanes, only for
different patches and vertices.

For the TCS this results in tightly packed data for 4-component
stores.

For the TES this is not the case as within a patch the loads
often also access the same vertex. However if there are < 4
vertices/patch, this still results in a reduction of the number
of cache lines. In the LDS situation we only do better than worst
case if the data per patch < 64 bytes, which due to the
tessellation factors is pretty much never.

We do not use hardware swizzling for this. It would slightly reduce
the number of executed VALU instructions, but I had issues with
increased wait times that I haven't been able to solve yet.
Furthermore, the tbuffer_store intrinsic does not support both
VGPR offset and an index, so we have a problem storing
indirectly indexed outputs. This can be solved by temporarily
storing arrays in LDS and then copying them, but I don't think
that is worth the effort. The difference in VALU cycles
hardware swizzling gives is about 0.2% of total busy cycles.
That is without handling the array case.

I chose for attributes instead of components as they are often
accessed together, and the software swizzling takes VALU cycles
for calculating offsets.

v2: - Rename functions to get_tcs_tes_buffer_address.
- multiply by 16 as late as possible.
- Use  tgsi_full_src_register_from_dst.
- Remove some bad comments.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_shader.c | 124 +++
 1 file changed, 124 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index ac42721..83bcf5e 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -671,6 +671,130 @@ static LLVMValueRef get_dw_address(struct 
si_shader_context *ctx,
lp_build_const_int32(gallivm, param * 4), "");
 }
 
+/* The offchip buffer layout for TCS->TES is
+ *
+ * - attribute 0 of patch 0 vertex 0
+ * - attribute 0 of patch 0 vertex 1
+ * - attribute 0 of patch 0 vertex 2
+ *   ...
+ * - attribute 0 of patch 1 vertex 0
+ * - attribute 0 of patch 1 vertex 1
+ *   ...
+ * - attribute 1 of patch 0 vertex 0
+ * - attribute 1 of patch 0 vertex 1
+ *   ...
+ * - per patch attribute 0 of patch 0
+ * - per patch attribute 0 of patch 1
+ *   ...
+ *
+ * Note that every attribute has 4 components.
+ */
+static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
+   LLVMValueRef vertex_index,
+   LLVMValueRef param_index)
+{
+   struct gallivm_state *gallivm = 
ctx->radeon_bld.soa.bld_base.base.gallivm;
+   LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
+   LLVMValueRef param_stride, constant16;
+
+   vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 
6);
+   num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
+   total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
+ num_patches, "");
+
+   constant16 = lp_build_const_int32(gallivm, 16);
+   if (vertex_index) {
+   base_addr = LLVMBuildMul(gallivm->builder, 
get_rel_patch_id(ctx),
+vertices_per_patch, "");
+
+   base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
+vertex_index, "");
+
+   param_stride = total_vertices;
+   } else {
+   base_addr = get_rel_patch_id(ctx);
+   param_stride = num_patches;
+   }
+
+   base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
+LLVMBuildMul(gallivm->builder, param_index,
+ param_stride, ""), "");
+
+   base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
+
+   if (!vertex_index) {
+   LLVMValueRef patch_data_offset =
+  unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 
16);
+
+   base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
+patch_data_offset, "");
+   }
+   return base_addr;
+}
+
+static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
+   

Mesa (master): radeonsi: Enable dynamic HS.

[Bas Nieuwenhuizen]

Module: Mesa
Branch: master
Commit: fee3160af9c8c9594e7d452cf3035b03a8f4153a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fee3160af9c8c9594e7d452cf3035b03a8f4153a

Author: Bas Nieuwenhuizen 
Date:   Mon May  2 14:59:43 2016 +0200

radeonsi: Enable dynamic HS.

This allows running the TES on different CU's than the
TCS which results in performance improvements.

v2: Only write the control word from one invocation.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_shader.c| 19 +++
 src/gallium/drivers/radeonsi/si_state_shaders.c |  2 +-
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 11c7c38..166b2e8 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2532,7 +2532,7 @@ static void si_write_tess_factors(struct 
lp_build_tgsi_context *bld_base,
LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
unsigned stride, outer_comps, inner_comps, i;
-   struct lp_build_if_state if_ctx;
+   struct lp_build_if_state if_ctx, inner_if_ctx;
 
/* Do this only for invocation 0, because the tess levels are per-patch,
 * not per-vertex.
@@ -2604,12 +2604,23 @@ static void si_write_tess_factors(struct 
lp_build_tgsi_context *bld_base,
byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
  lp_build_const_int32(gallivm, 4 * stride), 
"");
 
-   /* Store the outputs. */
+   lp_build_if(_if_ctx, gallivm,
+   LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
+ rel_patch_id, bld_base->uint_bld.zero, ""));
+
+   /* Store the dynamic HS control word. */
+   build_tbuffer_store_dwords(ctx, buffer,
+  lp_build_const_int32(gallivm, 0x8000),
+  1, lp_build_const_int32(gallivm, 0), 
tf_base, 0);
+
+   lp_build_endif(_if_ctx);
+
+   /* Store the tessellation factors. */
build_tbuffer_store_dwords(ctx, buffer, vec0,
-  MIN2(stride, 4), byteoffset, tf_base, 0);
+  MIN2(stride, 4), byteoffset, tf_base, 4);
if (vec1)
build_tbuffer_store_dwords(ctx, buffer, vec1,
-  stride - 4, byteoffset, tf_base, 16);
+  stride - 4, byteoffset, tf_base, 20);
lp_build_endif(_ctx);
 }
 
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c 
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 2aecfa3..116bf27 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1882,7 +1882,7 @@ static void si_update_vgt_shader_config(struct si_context 
*sctx)
 
if (sctx->tes_shader.cso) {
stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
- S_028B54_HS_EN(1);
+ S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
 
if (sctx->gs_shader.cso)
stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |

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Mesa (master): radeonsi: Define build_tbuffer_store_dwords earlier to support new users.

[Bas Nieuwenhuizen]

Module: Mesa
Branch: master
Commit: 9fdb7787023e6032cf263d282669b31291ddb6ce
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9fdb7787023e6032cf263d282669b31291ddb6ce

Author: Bas Nieuwenhuizen 
Date:   Mon May  2 14:20:19 2016 +0200

radeonsi: Define build_tbuffer_store_dwords earlier to support new users.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_shader.c | 138 +++
 1 file changed, 69 insertions(+), 69 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 1f162b5..6690f05 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -671,6 +671,75 @@ static LLVMValueRef get_dw_address(struct 
si_shader_context *ctx,
lp_build_const_int32(gallivm, param * 4), "");
 }
 
+/* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by 
num_channels=1..4.
+ * The type of vdata must be one of i32 (num_channels=1), v2i32 
(num_channels=2),
+ * or v4i32 (num_channels=3,4). */
+static void build_tbuffer_store(struct si_shader_context *ctx,
+   LLVMValueRef rsrc,
+   LLVMValueRef vdata,
+   unsigned num_channels,
+   LLVMValueRef vaddr,
+   LLVMValueRef soffset,
+   unsigned inst_offset,
+   unsigned dfmt,
+   unsigned nfmt,
+   unsigned offen,
+   unsigned idxen,
+   unsigned glc,
+   unsigned slc,
+   unsigned tfe)
+{
+   struct gallivm_state *gallivm = >radeon_bld.gallivm;
+   LLVMValueRef args[] = {
+   rsrc,
+   vdata,
+   LLVMConstInt(ctx->i32, num_channels, 0),
+   vaddr,
+   soffset,
+   LLVMConstInt(ctx->i32, inst_offset, 0),
+   LLVMConstInt(ctx->i32, dfmt, 0),
+   LLVMConstInt(ctx->i32, nfmt, 0),
+   LLVMConstInt(ctx->i32, offen, 0),
+   LLVMConstInt(ctx->i32, idxen, 0),
+   LLVMConstInt(ctx->i32, glc, 0),
+   LLVMConstInt(ctx->i32, slc, 0),
+   LLVMConstInt(ctx->i32, tfe, 0)
+   };
+
+   /* The instruction offset field has 12 bits */
+   assert(offen || inst_offset < (1 << 12));
+
+   /* The intrinsic is overloaded, we need to add a type suffix for 
overloading to work. */
+   unsigned func = CLAMP(num_channels, 1, 3) - 1;
+   const char *types[] = {"i32", "v2i32", "v4i32"};
+   char name[256];
+   snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
+
+   lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
+  args, ARRAY_SIZE(args), 0);
+}
+
+static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
+LLVMValueRef rsrc,
+LLVMValueRef vdata,
+unsigned num_channels,
+LLVMValueRef vaddr,
+LLVMValueRef soffset,
+unsigned inst_offset)
+{
+   static unsigned dfmt[] = {
+   V_008F0C_BUF_DATA_FORMAT_32,
+   V_008F0C_BUF_DATA_FORMAT_32_32,
+   V_008F0C_BUF_DATA_FORMAT_32_32_32,
+   V_008F0C_BUF_DATA_FORMAT_32_32_32_32
+   };
+   assert(num_channels >= 1 && num_channels <= 4);
+
+   build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
+   inst_offset, dfmt[num_channels-1],
+   V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
+}
+
 /**
  * Load from LDS.
  *
@@ -1844,75 +1913,6 @@ static void si_dump_streamout(struct 
pipe_stream_output_info *so)
}
 }
 
-/* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by 
num_channels=1..4.
- * The type of vdata must be one of i32 (num_channels=1), v2i32 
(num_channels=2),
- * or v4i32 (num_channels=3,4). */
-static void build_tbuffer_store(struct si_shader_context *ctx,
-   LLVMValueRef rsrc,
-   LLVMValueRef vdata,
-   unsigned num_channels,
-   LLVMValueRef vaddr,
-   LLVMValueRef soffset,
-   unsigned inst_offset,
-   unsigned dfmt,
-   unsigned nfmt,
-   unsigned offen,
-   

Mesa (master): radeonsi: Add buffer load functions.

[Bas Nieuwenhuizen]

Module: Mesa
Branch: master
Commit: 3e7a7a9a65ebc4add06a3786d641a0eff7d5068f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e7a7a9a65ebc4add06a3786d641a0eff7d5068f

Author: Bas Nieuwenhuizen 
Date:   Mon May  2 14:39:56 2016 +0200

radeonsi: Add buffer load functions.

v2: - Use llvm.admgcn.buffer.load instrinsics for new LLVM.
- Code style fixes.

v3: - Code style fix.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_shader.c | 114 +++
 1 file changed, 114 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 6690f05..eb57345 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -740,6 +740,120 @@ static void build_tbuffer_store_dwords(struct 
si_shader_context *ctx,
V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
 }
 
+static LLVMValueRef build_buffer_load(struct si_shader_context *ctx,
+  LLVMValueRef rsrc,
+  int num_channels,
+  LLVMValueRef vindex,
+  LLVMValueRef voffset,
+  LLVMValueRef soffset,
+  unsigned inst_offset,
+  unsigned glc,
+  unsigned slc)
+{
+   struct gallivm_state *gallivm = >radeon_bld.gallivm;
+   unsigned func = CLAMP(num_channels, 1, 3) - 1;
+
+   if (HAVE_LLVM >= 0x309) {
+   LLVMValueRef args[] = {
+   LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, 
""),
+   vindex ? vindex : LLVMConstInt(ctx->i32, 0, 0),
+   LLVMConstInt(ctx->i32, inst_offset, 0),
+   LLVMConstInt(ctx->i1, glc, 0),
+   LLVMConstInt(ctx->i1, slc, 0)
+   };
+
+   LLVMTypeRef types[] = {ctx->f32, LLVMVectorType(ctx->f32, 2),
+  ctx->v4f32};
+   const char *type_names[] = {"f32", "v2f32", "v4f32"};
+   char name[256];
+
+   if (voffset) {
+   args[2] = LLVMBuildAdd(gallivm->builder, args[2], 
voffset,
+  "");
+   }
+
+   if (soffset) {
+   args[2] = LLVMBuildAdd(gallivm->builder, args[2], 
soffset,
+  "");
+   }
+
+   snprintf(name, sizeof(name), "llvm.amdgcn.buffer.load.%s",
+type_names[func]);
+
+   return lp_build_intrinsic(gallivm->builder, name, types[func], 
args,
+ ARRAY_SIZE(args), 
LLVMReadOnlyAttribute |
+ LLVMNoUnwindAttribute);
+   } else {
+   LLVMValueRef args[] = {
+   LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v16i8, 
""),
+   voffset ? voffset : vindex,
+   soffset,
+   LLVMConstInt(ctx->i32, inst_offset, 0),
+   LLVMConstInt(ctx->i32, voffset ? 1 : 0, 0), // offen
+   LLVMConstInt(ctx->i32, vindex ? 1 : 0, 0), //idxen
+   LLVMConstInt(ctx->i32, glc, 0),
+   LLVMConstInt(ctx->i32, slc, 0),
+   LLVMConstInt(ctx->i32, 0, 0), // TFE
+   };
+
+   LLVMTypeRef types[] = {ctx->i32, LLVMVectorType(ctx->i32, 2),
+  ctx->v4i32};
+   const char *type_names[] = {"i32", "v2i32", "v4i32"};
+   const char *arg_type = "i32";
+   char name[256];
+
+   if (voffset && vindex) {
+   LLVMValueRef vaddr[] = {vindex, voffset};
+
+   arg_type = "v2i32";
+   args[1] = lp_build_gather_values(gallivm, vaddr, 2);
+   }
+
+   snprintf(name, sizeof(name), "llvm.SI.buffer.load.dword.%s.%s",
+type_names[func], arg_type);
+
+   return lp_build_intrinsic(gallivm->builder, name, types[func], 
args,
+ ARRAY_SIZE(args), 
LLVMReadOnlyAttribute |
+ LLVMNoUnwindAttribute);
+   }
+}
+
+static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
+enum tgsi_opcode_type type, unsigned swizzle,
+LLVMValueRef buffer, LLVMValueRef offset,
+LLVMValueRef base)
+{
+   struct si_shader_context *ctx = si_shader_context(bld_base);
+   

Mesa (master): radeonsi: Remove LDS layout user SGPR's from TES.

[Bas Nieuwenhuizen]

Module: Mesa
Branch: master
Commit: 26f436132bbeebb7ec5efd56c1473a13719daccf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=26f436132bbeebb7ec5efd56c1473a13719daccf

Author: Bas Nieuwenhuizen 
Date:   Tue May 10 01:05:32 2016 +0200

radeonsi: Remove LDS layout user SGPR's from TES.

They are unused.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_shader.c |  4 +---
 src/gallium/drivers/radeonsi/si_shader.h | 15 ---
 src/gallium/drivers/radeonsi/si_state_draw.c |  4 +---
 3 files changed, 10 insertions(+), 13 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 6694f00..11c7c38 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -5414,9 +5414,7 @@ static void create_function(struct si_shader_context *ctx)
 
case PIPE_SHADER_TESS_EVAL:
params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
-   params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
-   params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
-   num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
+   num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
 
if (shader->key.tes.as_es) {
params[ctx->param_oc_lds = num_params++] = ctx->i32;
diff --git a/src/gallium/drivers/radeonsi/si_shader.h 
b/src/gallium/drivers/radeonsi/si_shader.h
index 67b457b..9425b1e 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -108,12 +108,12 @@ enum {
 
/* both TCS and TES */
SI_SGPR_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
-   SI_SGPR_TCS_OUT_OFFSETS,
-   SI_SGPR_TCS_OUT_LAYOUT,
SI_TES_NUM_USER_SGPR,
 
/* TCS only */
-   SI_SGPR_TCS_IN_LAYOUT = SI_TES_NUM_USER_SGPR,
+   SI_SGPR_TCS_OUT_OFFSETS = SI_TES_NUM_USER_SGPR,
+   SI_SGPR_TCS_OUT_LAYOUT,
+   SI_SGPR_TCS_IN_LAYOUT,
SI_TCS_NUM_USER_SGPR,
 
/* GS limits */
@@ -155,26 +155,27 @@ enum {
 */
SI_PARAM_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_PARAMS, /* for TCS & TES 
*/
 
+   /* TCS only parameters. */
+
/* Offsets where TCS outputs and TCS patch outputs live in LDS:
 *   [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
 *   [16:31] = TCS output patch0 offset for per-patch / 16, max = 
NUM_PATCHES*32*32* + 32*32
 */
-   SI_PARAM_TCS_OUT_OFFSETS, /* for TCS & TES */
+   SI_PARAM_TCS_OUT_OFFSETS,
 
/* Layout of TCS outputs / TES inputs:
 *   [0:12] = stride between output patches in dwords, num_outputs * 
num_vertices * 4, max = 32*32*4
 *   [13:20] = stride between output vertices in dwords = num_inputs * 
4, max = 32*4
 *   [26:31] = gl_PatchVerticesIn, max = 32
 */
-   SI_PARAM_TCS_OUT_LAYOUT, /* for TCS & TES */
+   SI_PARAM_TCS_OUT_LAYOUT,
 
/* Layout of LS outputs / TCS inputs
 *   [0:12] = stride between patches in dwords = num_inputs * 
num_vertices * 4, max = 32*32*4
 *   [13:20] = stride between vertices in dwords = num_inputs * 4, max 
= 32*4
 */
-   SI_PARAM_TCS_IN_LAYOUT,  /* TCS only */
+   SI_PARAM_TCS_IN_LAYOUT,
 
-   /* TCS only parameters. */
SI_PARAM_TCS_OC_LDS,
SI_PARAM_TESS_FACTOR_OFFSET,
SI_PARAM_PATCH_ID,
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c 
b/src/gallium/drivers/radeonsi/si_state_draw.c
index e14a1c9..6fe2619 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -201,10 +201,8 @@ static void si_emit_derived_tess_state(struct si_context 
*sctx,
radeon_emit(cs, tcs_in_layout);
 
/* Set them for TES. */
-   radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 
3);
+   radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 
1);
radeon_emit(cs, offchip_layout);
-   radeon_emit(cs, tcs_out_offsets);
-   radeon_emit(cs, tcs_out_layout | (num_tcs_output_cp << 26));
 }
 
 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)

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Mesa (master): radeonsi: Use buffer loads and stores for passing data from TCS to TES.

[Bas Nieuwenhuizen]

Module: Mesa
Branch: master
Commit: a4e2146a9d24592ed7e3bf778e3c21c6cfb89330
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4e2146a9d24592ed7e3bf778e3c21c6cfb89330

Author: Bas Nieuwenhuizen 
Date:   Mon May  2 14:55:52 2016 +0200

radeonsi: Use buffer loads and stores for passing data from TCS to TES.

We always try to use 4-component loads, as LLVM does not combine loads
and they bypass the L1 cache.

We can't use a similar strategy for stores and this is especially
notable with the tess factors, as they are often set with separate
MOV's per component in the TGSI.

We keep storing to LDS and the LDS space, so we can load the outputs
later, either due to the shader, of for wrting the tess factors.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_shader.c | 66 
 1 file changed, 50 insertions(+), 16 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index b04d0f7..6694f00 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1082,18 +1082,18 @@ static LLVMValueRef fetch_input_tes(
enum tgsi_opcode_type type, unsigned swizzle)
 {
struct si_shader_context *ctx = si_shader_context(bld_base);
-   LLVMValueRef dw_addr, stride;
+   struct gallivm_state *gallivm = bld_base->base.gallivm;
+   LLVMValueRef rw_buffers, buffer, base, addr;
 
-   if (reg->Register.Dimension) {
-   stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
-   dw_addr = get_tcs_out_current_patch_offset(ctx);
-   dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
-   } else {
-   dw_addr = get_tcs_out_current_patch_data_offset(ctx);
-   dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
-   }
+   rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
+ SI_PARAM_RW_BUFFERS);
+   buffer = build_indexed_load_const(ctx, rw_buffers,
+   lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
 
-   return lds_load(bld_base, type, swizzle, dw_addr);
+   base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
+   addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
+
+   return buffer_load(bld_base, type, swizzle, buffer, base, addr);
 }
 
 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
@@ -1102,9 +1102,12 @@ static void store_output_tcs(struct 
lp_build_tgsi_context *bld_base,
 LLVMValueRef dst[4])
 {
struct si_shader_context *ctx = si_shader_context(bld_base);
+   struct gallivm_state *gallivm = bld_base->base.gallivm;
const struct tgsi_full_dst_register *reg = >Dst[0];
unsigned chan_index;
LLVMValueRef dw_addr, stride;
+   LLVMValueRef rw_buffers, buffer, base, buf_addr;
+   LLVMValueRef values[4];
 
/* Only handle per-patch and per-vertex outputs here.
 * Vectors will be lowered to scalars and this function will be called 
again.
@@ -1124,6 +1127,15 @@ static void store_output_tcs(struct 
lp_build_tgsi_context *bld_base,
dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
}
 
+   rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
+ SI_PARAM_RW_BUFFERS);
+   buffer = build_indexed_load_const(ctx, rw_buffers,
+   lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
+
+   base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
+   buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
+
+
TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
LLVMValueRef value = dst[chan_index];
 
@@ -1131,6 +1143,22 @@ static void store_output_tcs(struct 
lp_build_tgsi_context *bld_base,
value = radeon_llvm_saturate(bld_base, value);
 
lds_store(bld_base, chan_index, dw_addr, value);
+
+   value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
+   values[chan_index] = value;
+
+   if (inst->Dst[0].Register.WriteMask != 0xF) {
+   build_tbuffer_store_dwords(ctx, buffer, value, 1,
+  buf_addr, base,
+  4 * chan_index);
+   }
+   }
+
+   if (inst->Dst[0].Register.WriteMask == 0xF) {
+   LLVMValueRef value = 
lp_build_gather_values(bld_base->base.gallivm,
+   values, 4);
+   build_tbuffer_store_dwords(ctx, buffer, value, 4, buf_addr,
+  base, 0);
 

Mesa (master): radeonsi: Store inputs to memory when not using a TCS.

[Bas Nieuwenhuizen]

Module: Mesa
Branch: master
Commit: 6217716e8f6091f7bbacbb9fa2f52997d3ac5d03
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6217716e8f6091f7bbacbb9fa2f52997d3ac5d03

Author: Bas Nieuwenhuizen 
Date:   Tue May  3 21:31:00 2016 +0200

radeonsi: Store inputs to memory when not using a TCS.

We need to copy the VS outputs to memory. I decided to do this
using a shader key, as the value depends on other shaders.

I also switch the fixed function TCS over to monolithic, as
otherwisze many of the user SGPR's need to be passed to the
epilog, which increases register pressure, or complexity to
avoid that. The main body of the fixed function TCS is not
that interesting to precompile anyway, since we do it on
demand and it is very small.

v2: Use u_bit_scan64.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_shader.c| 45 +
 src/gallium/drivers/radeonsi/si_shader.h|  1 +
 src/gallium/drivers/radeonsi/si_state_shaders.c |  3 ++
 3 files changed, 49 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 83bcf5e..b04d0f7 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2444,6 +2444,48 @@ handle_semantic:
}
 }
 
+static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
+{
+   struct si_shader_context *ctx = si_shader_context(bld_base);
+   struct gallivm_state *gallivm = bld_base->base.gallivm;
+   LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
+   LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
+   uint64_t inputs;
+
+   invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
+
+   rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
+   buffer = build_indexed_load_const(ctx, rw_buffers,
+   lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
+
+   buffer_offset = LLVMGetParam(ctx->radeon_bld.main_fn, 
ctx->param_oc_lds);
+
+   lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
+   lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
+lds_vertex_stride, "");
+   lds_base = get_tcs_in_current_patch_offset(ctx);
+   lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, 
"");
+
+   inputs = ctx->shader->key.tcs.epilog.inputs_to_copy;
+   while (inputs) {
+   unsigned i = u_bit_scan64();
+
+   LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
+   lp_build_const_int32(gallivm, 4 * 
i),
+"");
+
+   LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
+ invocation_id,
+ lp_build_const_int32(gallivm, i));
+
+   LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
+ lds_ptr);
+
+   build_tbuffer_store_dwords(ctx, buffer, value, 4, buffer_addr,
+  buffer_offset, 0);
+   }
+}
+
 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
  LLVMValueRef rel_patch_id,
  LLVMValueRef invocation_id,
@@ -2585,6 +2627,7 @@ static void si_llvm_emit_tcs_epilogue(struct 
lp_build_tgsi_context *bld_base)
return;
}
 
+   si_copy_tcs_inputs(bld_base);
si_write_tess_factors(bld_base, rel_patch_id, invocation_id, 
tf_lds_offset);
 }
 
@@ -7426,6 +7469,8 @@ int si_shader_create(struct si_screen *sscreen, 
LLVMTargetMachineRef tm,
  shader->key.vs.as_ls != mainp->key.vs.as_ls)) ||
(shader->selector->type == PIPE_SHADER_TESS_EVAL &&
 shader->key.tes.as_es != mainp->key.tes.as_es) ||
+   (shader->selector->type == PIPE_SHADER_TESS_CTRL &&
+shader->key.tcs.epilog.inputs_to_copy) ||
shader->selector->type == PIPE_SHADER_COMPUTE) {
/* Monolithic shader (compiled as a whole, has many variants,
 * may take a long time to compile).
diff --git a/src/gallium/drivers/radeonsi/si_shader.h 
b/src/gallium/drivers/radeonsi/si_shader.h
index 26be25e..67b457b 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -304,6 +304,7 @@ struct si_vs_epilog_bits {
 /* Common TCS bits between the shader key and the epilog key. */
 struct si_tcs_epilog_bits {
unsignedprim_mode:3;
+   uint64_tinputs_to_copy;
 };
 
 /* Common PS bits between the shader key and the prolog key. */
diff --git 

Mesa (master): radeonsi: Add buffer for offchip storage between TCS and TES.

[Bas Nieuwenhuizen]

Module: Mesa
Branch: master
Commit: d27ff7d6838fef2419ffb05798967e785e196afb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d27ff7d6838fef2419ffb05798967e785e196afb

Author: Bas Nieuwenhuizen 
Date:   Mon May  2 09:54:11 2016 +0200

radeonsi: Add buffer for offchip storage between TCS and TES.

The buffer is quite large, but should only be allocated if the
application uses tessellation. Most non-games don't.

v2: - Use the correct register for SI.
- Add define for block size.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_pipe.c  |  1 +
 src/gallium/drivers/radeonsi/si_pipe.h  |  1 +
 src/gallium/drivers/radeonsi/si_state.h |  3 +++
 src/gallium/drivers/radeonsi/si_state_shaders.c | 18 ++
 4 files changed, 23 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 6700590..eefc68a 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -48,6 +48,7 @@ static void si_destroy_context(struct pipe_context *context)
pipe_resource_reference(>esgs_ring, NULL);
pipe_resource_reference(>gsvs_ring, NULL);
pipe_resource_reference(>tf_ring, NULL);
+   pipe_resource_reference(>tess_offchip_ring, NULL);
pipe_resource_reference(>null_const_buf.buffer, NULL);
r600_resource_reference(>border_color_buffer, NULL);
free(sctx->border_color_table);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h 
b/src/gallium/drivers/radeonsi/si_pipe.h
index 33d3d25..e5b88c7 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -256,6 +256,7 @@ struct si_context {
struct pipe_resource*esgs_ring;
struct pipe_resource*gsvs_ring;
struct pipe_resource*tf_ring;
+   struct pipe_resource*tess_offchip_ring;
union pipe_color_union  *border_color_table; /* in CPU memory, 
any endian */
struct r600_resource*border_color_buffer;
union pipe_color_union  *border_color_map; /* in VRAM (slow 
access), little endian */
diff --git a/src/gallium/drivers/radeonsi/si_state.h 
b/src/gallium/drivers/radeonsi/si_state.h
index f2a3b03..a3589d4 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -40,6 +40,8 @@
 #define SI_NUM_IMAGES  16
 #define SI_NUM_SHADER_BUFFERS  16
 
+#define SI_TESS_OFFCHIP_BLOCK_SIZE (8192 * 4)
+
 struct si_screen;
 struct si_shader;
 
@@ -155,6 +157,7 @@ struct si_shader_data {
 /* Private read-write buffer slots. */
 enum {
SI_HS_RING_TESS_FACTOR,
+   SI_HS_RING_TESS_OFFCHIP,
 
SI_ES_RING_ESGS,
SI_GS_RING_ESGS,
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c 
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 13066ff..d8ae2b2 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1770,6 +1770,7 @@ static bool si_update_spi_tmpring_size(struct si_context 
*sctx)
 
 static void si_init_tess_factor_ring(struct si_context *sctx)
 {
+   unsigned offchip_blocks = sctx->b.chip_class >= CIK ? 256 : 64;
assert(!sctx->tf_ring);
 
sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
@@ -1780,6 +1781,14 @@ static void si_init_tess_factor_ring(struct si_context 
*sctx)
 
assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
 
+   sctx->tess_offchip_ring = pipe_buffer_create(sctx->b.b.screen,
+PIPE_BIND_CUSTOM,
+PIPE_USAGE_DEFAULT,
+offchip_blocks *
+
SI_TESS_OFFCHIP_BLOCK_SIZE);
+   if (!sctx->tess_offchip_ring)
+   return;
+
si_init_config_add_vgt_flush(sctx);
 
/* Append these registers to the init config state. */
@@ -1788,11 +1797,16 @@ static void si_init_tess_factor_ring(struct si_context 
*sctx)
   S_030938_SIZE(sctx->tf_ring->width0 / 4));
si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
   r600_resource(sctx->tf_ring)->gpu_address >> 8);
+   si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
+S_03093C_OFFCHIP_BUFFERING(offchip_blocks - 1) |
+
S_03093C_OFFCHIP_GRANULARITY(V_03093C_X_8K_DWORDS));
} else {
si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
   S_008988_SIZE(sctx->tf_ring->width0 / 4));

Mesa (master): radeonsi: Add user SGPR for the layout of the offchip buffer.

[Bas Nieuwenhuizen]

Module: Mesa
Branch: master
Commit: c49e68dc4bcc14cac529d1e3be5fe0090ed4d146
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c49e68dc4bcc14cac529d1e3be5fe0090ed4d146

Author: Bas Nieuwenhuizen 
Date:   Tue May 10 00:48:55 2016 +0200

radeonsi: Add user SGPR for the layout of the offchip buffer.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_shader.c |  3 +++
 src/gallium/drivers/radeonsi/si_shader.h | 12 ++--
 src/gallium/drivers/radeonsi/si_state_draw.c |  9 +++--
 3 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index eb57345..ac42721 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -5186,6 +5186,7 @@ static void create_function(struct si_shader_context *ctx)
break;
 
case PIPE_SHADER_TESS_CTRL:
+   params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
@@ -5211,6 +5212,7 @@ static void create_function(struct si_shader_context *ctx)
break;
 
case PIPE_SHADER_TESS_EVAL:
+   params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
@@ -6768,6 +6770,7 @@ static bool si_compile_tcs_epilog(struct si_screen 
*sscreen,
params[SI_PARAM_SAMPLERS] = ctx.i64;
params[SI_PARAM_IMAGES] = ctx.i64;
params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
+   params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx.i32;
params[SI_PARAM_TCS_OUT_OFFSETS] = ctx.i32;
params[SI_PARAM_TCS_OUT_LAYOUT] = ctx.i32;
params[SI_PARAM_TCS_IN_LAYOUT] = ctx.i32;
diff --git a/src/gallium/drivers/radeonsi/si_shader.h 
b/src/gallium/drivers/radeonsi/si_shader.h
index 7b1cbf9..26be25e 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -107,7 +107,8 @@ enum {
SI_LS_NUM_USER_SGPR,
 
/* both TCS and TES */
-   SI_SGPR_TCS_OUT_OFFSETS = SI_NUM_RESOURCE_SGPRS,
+   SI_SGPR_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
+   SI_SGPR_TCS_OUT_OFFSETS,
SI_SGPR_TCS_OUT_LAYOUT,
SI_TES_NUM_USER_SGPR,
 
@@ -147,11 +148,18 @@ enum {
SI_PARAM_LS_OUT_LAYOUT = SI_PARAM_START_INSTANCE + 1,
/* the other VS parameters are assigned dynamically */
 
+   /* Layout of TCS outputs in the offchip buffer
+*   [0:8] = the number of patches per threadgroup.
+*   [9:15] = the number of output vertices per patch.
+*   [16:31] = the offset of per patch attributes in the buffer in 
bytes.
+*/
+   SI_PARAM_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_PARAMS, /* for TCS & TES 
*/
+
/* Offsets where TCS outputs and TCS patch outputs live in LDS:
 *   [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
 *   [16:31] = TCS output patch0 offset for per-patch / 16, max = 
NUM_PATCHES*32*32* + 32*32
 */
-   SI_PARAM_TCS_OUT_OFFSETS = SI_NUM_RESOURCE_PARAMS, /* for TCS & TES */
+   SI_PARAM_TCS_OUT_OFFSETS, /* for TCS & TES */
 
/* Layout of TCS outputs / TES inputs:
 *   [0:12] = stride between output patches in dwords, num_outputs * 
num_vertices * 4, max = 32*32*4
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c 
b/src/gallium/drivers/radeonsi/si_state_draw.c
index dab0dcc..e14a1c9 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -108,6 +108,7 @@ static void si_emit_derived_tess_state(struct si_context 
*sctx,
unsigned input_patch_size, output_patch_size, output_patch0_offset;
unsigned perpatch_output_offset, lds_size, ls_rsrc2;
unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
+   unsigned offchip_layout;
 
*num_patches = 1; /* TODO: calculate this */
 
@@ -183,6 +184,8 @@ static void si_emit_derived_tess_state(struct si_context 
*sctx,
 ((output_vertex_size / 4) << 13);
tcs_out_offsets = (output_patch0_offset / 16) |
  ((perpatch_output_offset / 16) << 16);
+   offchip_layout = (pervertex_output_patch_size * *num_patches << 16) |
+(num_tcs_output_cp << 9) | *num_patches;
 
/* Set them for LS. */
radeon_set_sh_reg(cs,
@@ -191,13 +194,15 @@ static void si_emit_derived_tess_state(struct si_context 
*sctx,
 
/* Set them for TCS. */
radeon_set_sh_reg_seq(cs,
-

Mesa (si-offchip-tess-v3): radeonsi: Allow TES distribution between shader engines.

[Bas Nieuwenhuizen]

Module: Mesa
Branch: si-offchip-tess-v3
Commit: 9df32d1e509c7ce49ea9a89aaaff1488d4650395
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9df32d1e509c7ce49ea9a89aaaff1488d4650395

Author: Bas Nieuwenhuizen 
Date:   Tue Apr 12 20:28:46 2016 +0200

radeonsi: Allow TES distribution between shader engines.

The R_028B50_VGT_TESS_DISTRIBUTION value is copied from
amdgpu-pro. Smaller values in the ACCUM fields seem to
decrease the performance advantage from this patch, higher
values don't seem to matter.

v2: Add distribution mode field enums.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_state.c |  5 
 src/gallium/drivers/radeonsi/si_state_draw.c|  8 +
 src/gallium/drivers/radeonsi/si_state_shaders.c | 39 +++--
 src/gallium/drivers/radeonsi/sid.h  |  3 ++
 4 files changed, 40 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index aefa336..ab321ef 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3791,6 +3791,11 @@ static void si_init_config(struct si_context *sctx)
   S_028424_OVERWRITE_COMBINER_WATERMARK(4));
si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
+   si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION,
+  S_028B50_ACCUM_ISOLINE(32) |
+  S_028B50_ACCUM_TRI(11) |
+  S_028B50_ACCUM_QUAD(11) |
+  S_028B50_DONUT_SPLIT(16));
}
 
if (sctx->b.family == CHIP_STONEY)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c 
b/src/gallium/drivers/radeonsi/si_state_draw.c
index c8b87a9..788869e 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -279,6 +279,14 @@ static unsigned si_get_ia_multi_vgt_param(struct 
si_context *sctx,
 sctx->b.family == CHIP_BONAIRE) &&
sctx->gs_shader.cso)
partial_vs_wave = true;
+
+   /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
+   if (sctx->b.chip_class >= VI) {
+   if (sctx->gs_shader.cso)
+   partial_es_wave = true;
+   else
+   partial_vs_wave = true;
+   }
}
 
/* This is a hardware requirement. */
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c 
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 116bf27..c6f51ea 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -249,7 +249,8 @@ void si_destroy_shader_cache(struct si_screen *sscreen)
 
 /* SHADER STATES */
 
-static void si_set_tesseval_regs(struct si_shader *shader,
+static void si_set_tesseval_regs(struct si_screen *sscreen,
+struct si_shader *shader,
 struct si_pm4_state *pm4)
 {
struct tgsi_shader_info *info = >selector->info;
@@ -257,7 +258,7 @@ static void si_set_tesseval_regs(struct si_shader *shader,
unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
bool tes_vertex_order_cw = 
info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
-   unsigned type, partitioning, topology;
+   unsigned type, partitioning, topology, distribution_mode;
 
switch (tes_prim_mode) {
case PIPE_PRIM_LINES:
@@ -299,10 +300,16 @@ static void si_set_tesseval_regs(struct si_shader *shader,
else
topology = V_028B6C_OUTPUT_TRIANGLE_CW;
 
+   if (sscreen->b.chip_class >= VI)
+   distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
+   else
+   distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
+
si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
   S_028B6C_TYPE(type) |
   S_028B6C_PARTITIONING(partitioning) |
-  S_028B6C_TOPOLOGY(topology));
+  S_028B6C_TOPOLOGY(topology) |
+  S_028B6C_DISTRIBUTION_MODE(distribution_mode));
 }
 
 static void si_shader_ls(struct si_shader *shader)
@@ -359,7 +366,7 @@ static void si_shader_hs(struct si_shader *shader)
   
S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
 }
 
-static void si_shader_es(struct si_shader *shader)
+static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
 {
struct si_pm4_state 

Mesa (master): tgsi: fix out of bounds access

[Rob Clark]

Module: Mesa
Branch: master
Commit: 3d66ba971e984a1c58eda6a938a37f58ba6f8134
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d66ba971e984a1c58eda6a938a37f58ba6f8134

Author: Rob Clark 
Date:   Thu May 26 10:22:33 2016 -0400

tgsi: fix out of bounds access

Not sure why coverity calls this an out-of-bounds read vs out-of-bounds
write.

CID 1358920 (#1 of 1): Out-of-bounds read (OVERRUN)9. overrun-local:
Overrunning array r of 3 16-byte elements at element index 3 (byte
offset 48) using index chan (which evaluates to 3).

Signed-off-by: Rob Clark 
Reviewed-by: Brian Paul 

---

 src/gallium/auxiliary/tgsi/tgsi_exec.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c 
b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index baf4a89..289fe04 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -3851,7 +3851,7 @@ static void
 exec_load_mem(struct tgsi_exec_machine *mach,
   const struct tgsi_full_instruction *inst)
 {
-   union tgsi_exec_channel r[3];
+   union tgsi_exec_channel r[4];
uint chan;
char *ptr = mach->LocalMem;
uint32_t offset;

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Mesa (master): tgsi: fix coverity out-of-bounds warning

[Rob Clark]

Module: Mesa
Branch: master
Commit: 6e51fe75a4997328625753c9409b328f207d5e51
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e51fe75a4997328625753c9409b328f207d5e51

Author: Rob Clark 
Date:   Thu May 26 11:11:32 2016 -0400

tgsi: fix coverity out-of-bounds warning

CID 1271532 (#1 of 1): Out-of-bounds read (OVERRUN)34. overrun-local:
Overrunning array of 2 16-byte elements at element index 2 (byte offset
32) by dereferencing pointer [i].

Signed-off-by: Rob Clark 
Reviewed-by: Brian Paul 

---

 src/gallium/auxiliary/tgsi/tgsi_text.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_text.c 
b/src/gallium/auxiliary/tgsi/tgsi_text.c
index 955d042..8bdec06 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_text.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_text.c
@@ -1081,6 +1081,9 @@ parse_instruction(
   inst.Memory.Qualifier = 0;
}
 
+   assume(info->num_dst <= TGSI_FULL_MAX_DST_REGISTERS);
+   assume(info->num_src <= TGSI_FULL_MAX_SRC_REGISTERS);
+
/* Parse instruction operands.
 */
for (i = 0; i < info->num_dst + info->num_src + info->is_tex; i++) {

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Mesa (master): i965/gen9: Remove the halign/ valign field setup code in fast copy blit

[Anuj Phogat]

Module: Mesa
Branch: master
Commit: 97f0f91cc191d9d024588458f23a229b91acb84d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=97f0f91cc191d9d024588458f23a229b91acb84d

Author: Anuj Phogat 
Date:   Fri Dec 11 19:14:24 2015 -0800

i965/gen9: Remove the halign/valign field setup code in fast copy blit

Experimentation with different values of src/dst horizontal/vertical
alignment showed that these fileds are not used on gen9 hardware.

A recent update in graphics specs has removed these fields from
XY_FAST_COPY_BLT command.

Cc: Ben Widawsky 
Cc: Chad Versace 
Signed-off-by: Anuj Phogat 
Reviewed-by: Ben Widawsky 

---

 src/mesa/drivers/dri/i965/intel_blit.c | 65 --
 1 file changed, 65 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
b/src/mesa/drivers/dri/i965/intel_blit.c
index 72cf9af..4296222 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -104,64 +104,6 @@ br13_for_cpp(int cpp)
}
 }
 
-static uint32_t
-get_tr_horizontal_align(uint32_t tr_mode, uint32_t cpp, bool is_src) {
-   /* Alignment tables for YF/YS tiled surfaces. */
-   const uint32_t align_2d_yf[] = {64, 64, 32, 32, 16};
-   const uint32_t bpp = cpp * 8;
-   const uint32_t shift = is_src ? 17 : 10;
-   uint32_t align;
-   int i = 0;
-
-   if (tr_mode == INTEL_MIPTREE_TRMODE_NONE)
-  return 0;
-
-   /* Compute array index. */
-   assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp));
-   i = ffs(bpp / 8) - 1;
-
-   align = tr_mode == INTEL_MIPTREE_TRMODE_YF ?
-   align_2d_yf[i] :
-   4 * align_2d_yf[i];
-
-   assert(_mesa_is_pow_two(align));
-
-   /* XY_FAST_COPY_BLT doesn't support horizontal alignment of 16. */
-   if (align == 16)
-  align = 32;
-
-   return (ffs(align) - 6) << shift;
-}
-
-static uint32_t
-get_tr_vertical_align(uint32_t tr_mode, uint32_t cpp, bool is_src) {
-   /* Vertical alignment tables for YF/YS tiled surfaces. */
-   const unsigned align_2d_yf[] = {64, 32, 32, 16, 16};
-   const uint32_t bpp = cpp * 8;
-   const uint32_t shift = is_src ? 15 : 8;
-   uint32_t align;
-   int i = 0;
-
-   if (tr_mode == INTEL_MIPTREE_TRMODE_NONE)
-  return 0;
-
-   /* Compute array index. */
-   assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp));
-   i = ffs(bpp / 8) - 1;
-
-   align = tr_mode == INTEL_MIPTREE_TRMODE_YF ?
-   align_2d_yf[i] :
-   4 * align_2d_yf[i];
-
-   assert(_mesa_is_pow_two(align));
-
-   /* XY_FAST_COPY_BLT doesn't support vertical alignments of 16 and 32. */
-   if (align == 16 || align == 32)
-  align = 64;
-
-   return (ffs(align) - 7) << shift;
-}
-
 /**
  * Emits the packet for switching the blitter from X to Y tiled or back.
  *
@@ -457,13 +399,6 @@ xy_blit_cmd(uint32_t src_tiling, uint32_t src_tr_mode,
 
   if (src_tiling != I915_TILING_NONE)
  SET_TILING_XY_FAST_COPY_BLT(src_tiling, src_tr_mode, XY_FAST_SRC);
-
-  CMD |= get_tr_horizontal_align(src_tr_mode, cpp, true /* is_src */);
-  CMD |= get_tr_vertical_align(src_tr_mode, cpp, true /* is_src */);
-
-  CMD |= get_tr_horizontal_align(dst_tr_mode, cpp, false /* is_src */);
-  CMD |= get_tr_vertical_align(dst_tr_mode, cpp, false /* is_src */);
-
} else {
   assert(cpp <= 4);
   switch (cpp) {

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Mesa (master): i965: Don' t use fast copy blit in case of logical operations other than GL_COPY

[Anuj Phogat]

Module: Mesa
Branch: master
Commit: 0c02d7002d6c005b4c1fe997b5ef5916978dd183
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c02d7002d6c005b4c1fe997b5ef5916978dd183

Author: Anuj Phogat 
Date:   Wed May 25 11:33:51 2016 -0700

i965: Don't use fast copy blit in case of logical operations other than GL_COPY

XY_FAST_COPY_BLT command doesn't have a field for raster operation. So, fall
back to using XY_SRC_COPY_BLT to handle those cases.

Fixes piglit test gl-1.1-xor-copypixels when fast copy blit is enabled
for all tiling formats.

Signed-off-by: Anuj Phogat 
Reviewed-by: Matt Turner 

---

 src/mesa/drivers/dri/i965/intel_blit.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
b/src/mesa/drivers/dri/i965/intel_blit.c
index 4296222..5a48c20 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -340,7 +340,8 @@ can_fast_copy_blit(struct brw_context *brw,
int16_t dst_x, int16_t dst_y,
uintptr_t dst_offset, uint32_t dst_pitch,
uint32_t dst_tiling, uint32_t dst_tr_mode,
-   int16_t w, int16_t h, uint32_t cpp)
+   int16_t w, int16_t h, uint32_t cpp,
+   GLenum logic_op)
 {
const bool dst_tiling_none = dst_tiling == I915_TILING_NONE;
const bool src_tiling_none = src_tiling == I915_TILING_NONE;
@@ -354,6 +355,8 @@ can_fast_copy_blit(struct brw_context *brw,
 */
if (src_tr_mode == INTEL_MIPTREE_TRMODE_NONE &&
dst_tr_mode == INTEL_MIPTREE_TRMODE_NONE)
+
+   if (logic_op != GL_COPY)
   return false;
 
/* The start pixel for Fast Copy blit should be on an OWord boundary. */
@@ -498,13 +501,15 @@ intelEmitCopyBlit(struct brw_context *brw,
dst_x, dst_y,
dst_offset, dst_pitch,
dst_tiling, dst_tr_mode,
-   w, h, cpp);
+   w, h, cpp, logic_op);
if (!use_fast_copy_blit &&
(src_tr_mode != INTEL_MIPTREE_TRMODE_NONE ||
 dst_tr_mode != INTEL_MIPTREE_TRMODE_NONE))
   return false;
 
if (use_fast_copy_blit) {
+  assert(logic_op == GL_COPY);
+
   /* When two sequential fast copy blits have different source surfaces,
* but their destinations refer to the same destination surfaces and
* therefore destinations overlap it is imperative that a flush be

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Mesa (master): nvc0: allow to monitor MP perf counters with compute shaders

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: c52e92ec3a37c9ab3fb35132e62e1ddf6a770c27
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c52e92ec3a37c9ab3fb35132e62e1ddf6a770c27

Author: Samuel Pitoiset 
Date:   Wed May 25 23:36:48 2016 +0200

nvc0: allow to monitor MP perf counters with compute shaders

To read out MP perf counters we use a compute shader and need to upload
input data like a 64-bits addr used to store the values and a sequence
ID for synchronization. Currently, this input data is uploaded as user
uniforms which means that it's sticked to c0[], but if a compute shader
from a real application is used, monitoring those performance counters
will just overwrite some data and miserably crash.

Instead, sticking the 64-bits addr and the sequence into the driver
constant buffer seems like much better and will allow to monitor
counters with GL 4.3 apps.

Tested on GF119 and GK110, but should not hurt anything on GK104.

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Ilia Mirkin 

---

 src/gallium/drivers/nouveau/nvc0/nvc0_context.h|  3 +
 .../drivers/nouveau/nvc0/nvc0_query_hw_sm.c| 71 --
 2 files changed, 55 insertions(+), 19 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h 
b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
index 5be78aa..c099758 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
@@ -133,6 +133,9 @@
 /* 8 surfaces, at 16 32-bits integers each */
 #define NVC0_CB_AUX_SU_INFO(i)  0x400 + (i) * 16 * 4
 #define NVC0_CB_AUX_SU_SIZE (NVC0_MAX_IMAGES * 16 * 4)
+/* 1 64-bits address and 1 32-bits sequence */
+#define NVC0_CB_AUX_MP_INFO 0x600
+#define NVC0_CB_AUX_MP_SIZE 3 * 4
 /* 4 32-bits floats for the vertex runout, put at the end */
 #define NVC0_CB_AUX_RUNOUT_INFO NVC0_CB_USR_SIZE + NVC0_CB_AUX_SIZE
 
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
index 54e0140..27cbbc4 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
@@ -372,9 +372,9 @@ static const uint64_t nve4_read_hw_sm_counters_code[] =
 * mov b32 $r6 $pm6
 * mov b32 $r7 $pm7
 * set $p0 0x1 eq u32 $r8 0x0
-* mov b32 $r10 c0[0x0]
+* mov b32 $r10 c7[0x600]
 * ext u32 $r8 $r12 0x414
-* mov b32 $r11 c0[0x4]
+* mov b32 $r11 c7[0x604]
 * sched 0x04 0x2e 0x04 0x20 0x20 0x28 0x04
 * ext u32 $r9 $r12 0x208
 * (not $p0) exit
@@ -392,7 +392,7 @@ static const uint64_t nve4_read_hw_sm_counters_code[] =
 * add b32 $r12 $c $r12 $r9
 * st b128 wt g[$r10d] $r0q
 * sched 0x4 0x2c 0x20 0x04 0x2e 0x00 0x00
-* mov b32 $r0 c0[0x8]
+* mov b32 $r0 c7[0x608]
 * add b32 $r13 $r13 0x0 $c
 * $p1 st b128 wt g[$r12d+0x40] $r4q
 * st b32 wt g[$r12d+0x50] $r0
@@ -410,9 +410,9 @@ static const uint64_t nve4_read_hw_sm_counters_code[] =
0x2c0028019c04ULL,
0x2c002c01dc04ULL,
0x190efc81dc03ULL,
-   0x280040029de4ULL,
+   0x28005c1800029de4ULL,
0x7000c01050c21c03ULL,
-   0x280040001002dde4ULL,
+   0x28005c181002dde4ULL,
0x204282020042e047ULL,
0x7000c00820c25c03ULL,
0x800021e7ULL,
@@ -430,7 +430,7 @@ static const uint64_t nve4_read_hw_sm_counters_code[] =
0x480124c31c03ULL,
0x94a01fc5ULL,
0x22e04202c047ULL,
-   0x2800400020001de4ULL,
+   0x28005c1820001de4ULL,
0x08d35c42ULL,
0x940100c107c5ULL,
0x940140c01f85ULL,
@@ -453,9 +453,9 @@ static const uint64_t nvf0_read_hw_sm_counters_code[] =
0x8640051c001aULL,
0x8640059c001eULL,
0xdb201c007f9c201eULL,
-   0x64c03c1c002aULL,
+   0x64c03ce0c01c002aULL,
0xc0020a1c3021ULL,
-   0x64c03c9c002eULL,
+   0x64c03ce0c09c002eULL,
0x0810a0808010b810ULL,
0xc001041c3025ULL,
0x1820003cULL,
@@ -473,7 +473,7 @@ static const uint64_t nvf0_read_hw_sm_counters_code[] =
0xe084049c3032ULL,
0xfe80001c2800ULL,
0x08b81080b010ULL,
-   0x64c03c00011c0002ULL,
+   0x64c03ce0c11c0002ULL,
0xe08040007f9c3436ULL,
0xfe8020043010ULL,
0xfc80281c3000ULL,
@@ -1105,14 +1105,14 @@ static const uint64_t nvc0_read_hw_sm_counters_code[] =
 * mov b32 $r6 $pm6
 * mov b32 $r7 $pm7
 * set $p0 0x1 eq u32 $r8 0x0
-* mov b32 $r10 c0[0x0]
-* mov b32 $r11 c0[0x4]
+* mov b32 $r10 c15[0x600]
+* mov b32 $r11 c15[0x604]
 * ext u32 $r8 $r9 0x414
 * (not $p0) exit
 * mul $r8 u32 $r8 u32 48
 * add b32 $r10 $c $r10 $r8
 * add b32 $r11 $r11 0x0 $c
-* mov b32 $r8 c0[0x8]
+* mov b32 $r8 c15[0x608]
 * st b128 wt g[$r10d+0x00] $r0q
 * st b128 wt g[$r10d+0x10] $r4q
 * st b32 wt g[$r10d+0x20] $r8
@@ -1128,14 +1128,14 @@ static const uint64_t 

Mesa (master): mesa: Move robustness code to main/robustness.c

[Kristian Høgsberg]

Module: Mesa
Branch: master
Commit: 329d115ac68b40082540cf844c548e0656fbdbf9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=329d115ac68b40082540cf844c548e0656fbdbf9

Author: Kristian Høgsberg Kristensen 
Date:   Wed May 25 15:29:41 2016 -0700

mesa: Move robustness code to main/robustness.c

Signed-off-by: Kristian Høgsberg Kristensen 
Reviewed-by: Jason Ekstrand 
Reviewed-by: Brian Paul 

---

 src/mesa/Makefile.sources  |   1 +
 src/mesa/main/getstring.c  | 136 -
 src/mesa/main/robustness.c | 165 +
 3 files changed, 166 insertions(+), 136 deletions(-)

diff --git a/src/mesa/Makefile.sources b/src/mesa/Makefile.sources
index 840a68e..5f7f46d 100644
--- a/src/mesa/Makefile.sources
+++ b/src/mesa/Makefile.sources
@@ -171,6 +171,7 @@ MAIN_FILES = \
main/remap.h \
main/renderbuffer.c \
main/renderbuffer.h \
+   main/robustness.c \
main/samplerobj.c \
main/samplerobj.h \
main/scissor.c \
diff --git a/src/mesa/main/getstring.c b/src/mesa/main/getstring.c
index 1118a44..c39a076 100644
--- a/src/mesa/main/getstring.c
+++ b/src/mesa/main/getstring.c
@@ -32,7 +32,6 @@
 #include "extensions.h"
 #include "mtypes.h"
 #include "macros.h"
-#include "main/dispatch.h" /* for _gloffset_COUNT */
 
 /**
  * Return the string for a glGetString(GL_SHADING_LANGUAGE_VERSION) query.
@@ -310,138 +309,3 @@ _mesa_GetError( void )
ctx->ErrorDebugCount = 0;
return e;
 }
-
-static void GLAPIENTRY
-_context_lost_GetSynciv(GLsync sync, GLenum pname, GLsizei bufSize,
-GLsizei *length, GLint *values)
-{
-   GET_CURRENT_CONTEXT(ctx);
-   if (ctx)
-  _mesa_error(ctx, GL_CONTEXT_LOST, "GetSynciv(invalid call)");
-
-   if (pname == GL_SYNC_STATUS && bufSize >= 1)
-  *values = GL_SIGNALED;
-}
-
-static void GLAPIENTRY
-_context_lost_GetQueryObjectuiv(GLuint id, GLenum pname, GLuint *params)
-{
-   GET_CURRENT_CONTEXT(ctx);
-   if (ctx)
-  _mesa_error(ctx, GL_CONTEXT_LOST, "GetQueryObjectuiv(context lost)");
-
-   if (pname == GL_QUERY_RESULT_AVAILABLE)
-  *params = GL_TRUE;
-}
-
-static int
-context_lost_nop_handler(void)
-{
-   GET_CURRENT_CONTEXT(ctx);
-   if (ctx)
-  _mesa_error(ctx, GL_CONTEXT_LOST, "context lost");
-
-   return 0;
-}
-
-void
-_mesa_set_context_lost_dispatch(struct gl_context *ctx)
-{
-   if (ctx->ContextLost == NULL) {
-  int numEntries = MAX2(_glapi_get_dispatch_table_size(), _gloffset_COUNT);
-
-  ctx->ContextLost = malloc(numEntries * sizeof(_glapi_proc));
-  if (!ctx->ContextLost)
- return;
-
-  _glapi_proc *entry = (_glapi_proc *) ctx->ContextLost;
-  unsigned i;
-  for (i = 0; i < numEntries; i++)
- entry[i] = (_glapi_proc) context_lost_nop_handler;
-
-  /* The ARB_robustness specification says:
-   *
-   *"* GetError and GetGraphicsResetStatus behave normally following a
-   *   graphics reset, so that the application can determine a reset
-   *   has occurred, and when it is safe to destroy and recreate the
-   *   context.
-   *
-   * * Any commands which might cause a polling application to block
-   *   indefinitely will generate a CONTEXT_LOST error, but will also
-   *   return a value indicating completion to the application. Such
-   *   commands include:
-   *
-   *+ GetSynciv with  SYNC_STATUS ignores the other
-   *  parameters and returns SIGNALED in .
-   *
-   *+ GetQueryObjectuiv with  QUERY_RESULT_AVAILABLE
-   *  ignores the other parameters and returns TRUE in ."
-   */
-  SET_GetError(ctx->ContextLost, _mesa_GetError);
-  SET_GetGraphicsResetStatusARB(ctx->ContextLost, 
_mesa_GetGraphicsResetStatusARB);
-  SET_GetSynciv(ctx->ContextLost, _context_lost_GetSynciv);
-  SET_GetQueryObjectuiv(ctx->ContextLost, _context_lost_GetQueryObjectuiv);
-   }
-
-   ctx->CurrentDispatch = ctx->ContextLost;
-   _glapi_set_dispatch(ctx->CurrentDispatch);
-}
-
-/**
- * Returns an error code specified by GL_ARB_robustness, or GL_NO_ERROR.
- * \return current context status
- */
-GLenum GLAPIENTRY
-_mesa_GetGraphicsResetStatusARB( void )
-{
-   GET_CURRENT_CONTEXT(ctx);
-   GLenum status = GL_NO_ERROR;
-
-   /* The ARB_robustness specification says:
-*
-* "If the reset notification behavior is NO_RESET_NOTIFICATION_ARB,
-* then the implementation will never deliver notification of reset
-* events, and GetGraphicsResetStatusARB will always return NO_ERROR."
-*/
-   if (ctx->Const.ResetStrategy == GL_NO_RESET_NOTIFICATION_ARB) {
-  if (MESA_VERBOSE & VERBOSE_API)
- _mesa_debug(ctx,
- "glGetGraphicsResetStatusARB always returns GL_NO_ERROR "
- "because reset notifictation was 

Mesa (master): docs: Mark GL_KHR_robustness done for GLES3.2 as well

[Kristian Høgsberg]

Module: Mesa
Branch: master
Commit: d7d729b965e7b4e64f9b2ed5a9113a7be66baf29
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7d729b965e7b4e64f9b2ed5a9113a7be66baf29

Author: Kristian Høgsberg Kristensen 
Date:   Wed May 25 15:22:52 2016 -0700

docs: Mark GL_KHR_robustness done for GLES3.2 as well

Signed-off-by: Kristian Høgsberg Kristensen 
Reviewed-by: Jason Ekstrand 
Reviewed-by: Brian Paul 

---

 docs/GL3.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index 555a9be..9258fdf 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -253,7 +253,7 @@ GLES3.2, GLSL ES 3.2
   GL_EXT_color_buffer_float DONE (all drivers)
   GL_KHR_blend_equation_advancednot started
   GL_KHR_debug  DONE (all drivers)
-  GL_KHR_robustness not started (90% done 
with the ARB variant)
+  GL_KHR_robustness DONE (i965)
   GL_KHR_texture_compression_astc_ldr   DONE (i965/gen9+)
   GL_OES_copy_image DONE (i965)
   GL_OES_draw_buffers_indexed   DONE (all drivers that 
support GL_ARB_draw_buffers_blend)

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Mesa (master): egl: Additional attribute validation for eglCreatePbufferSurface

[Ben Widawsky]

Module: Mesa
Branch: master
Commit: a0674ce5c41903ccd161e89abb149621bfbc40d2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0674ce5c41903ccd161e89abb149621bfbc40d2

Author: Plamena Manolova 
Date:   Wed May 25 17:29:55 2016 +0100

egl: Additional attribute validation for eglCreatePbufferSurface

eglCreatePbufferSurface should generate an EGL_BAD_MATCH error if:
1: The EGL_TEXTURE_FORMAT attribute is EGL_NO_TEXTURE and EGL_TEXTURE_TARGET
is something other than EGL_NO_TEXTURE
2: EGL_TEXTURE_FORMAT is something other than EGL_NO_TEXTURE and
EGL_TEXTURE_TARGET is EGL_NO_TEXTURE.

This fixes the dEQP-EGL.functional.negative_api.create_pbuffer_surface test.

Signed-off-by: Plamena Manolova 
Reviewed-by: Ben Widawsky 

---

 src/egl/main/eglsurface.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/src/egl/main/eglsurface.c b/src/egl/main/eglsurface.c
index 2971bb0..17d7907 100644
--- a/src/egl/main/eglsurface.c
+++ b/src/egl/main/eglsurface.c
@@ -71,6 +71,8 @@ _eglParseSurfaceAttribList(_EGLSurface *surf, const EGLint 
*attrib_list)
EGLint type = surf->Type;
EGLint texture_type = EGL_PBUFFER_BIT;
EGLint i, err = EGL_SUCCESS;
+   EGLint tex_target = -1;
+   EGLint tex_format = -1;
 
if (!attrib_list)
   return EGL_SUCCESS;
@@ -186,6 +188,8 @@ _eglParseSurfaceAttribList(_EGLSurface *surf, const EGLint 
*attrib_list)
 err = EGL_BAD_ATTRIBUTE;
 break;
  }
+
+ tex_format = val;
  switch (val) {
  case EGL_TEXTURE_RGB:
  case EGL_TEXTURE_RGBA:
@@ -204,6 +208,8 @@ _eglParseSurfaceAttribList(_EGLSurface *surf, const EGLint 
*attrib_list)
 err = EGL_BAD_ATTRIBUTE;
 break;
  }
+
+ tex_target = val;
  switch (val) {
  case EGL_TEXTURE_2D:
  case EGL_NO_TEXTURE:
@@ -229,6 +235,13 @@ _eglParseSurfaceAttribList(_EGLSurface *surf, const EGLint 
*attrib_list)
  break;
   }
 
+  if (type == EGL_PBUFFER_BIT) {
+ if ((tex_target == EGL_NO_TEXTURE && tex_format != EGL_NO_TEXTURE) ||
+ (tex_format == EGL_NO_TEXTURE && tex_target != EGL_NO_TEXTURE)) {
+err = EGL_BAD_MATCH;
+ }
+  }
+
   if (err != EGL_SUCCESS) {
  _eglLog(_EGL_WARNING, "bad surface attribute 0x%04x", attr);
  break;

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Mesa (master): gallium/radeon: add the kernel version into the renderer string

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 8539c9bf3158416b22346dc49696872e631e969f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8539c9bf3158416b22346dc49696872e631e969f

Author: Marek Olšák 
Date:   Wed May 25 01:00:53 2016 +0200

gallium/radeon: add the kernel version into the renderer string

Example:
Gallium 0.4 on AMD TONGA (DRM 3.2.0 / 4.5.0, LLVM 3.9.0)

My kernel version is pretty long already (4.5.0-amd-01025-g32791c1)
and adding "kernel" into the string would make too it long for glxinfo
to display.

Reviewed-by: Michel Dänzer 

---

 src/gallium/drivers/radeon/r600_pipe_common.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 8d9c5a5..c00e584 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -37,6 +37,7 @@
 #include "vl/vl_video_buffer.h"
 #include "radeon/radeon_video.h"
 #include 
+#include 
 
 #ifndef HAVE_LLVM
 #define HAVE_LLVM 0
@@ -938,10 +939,15 @@ struct pipe_resource *r600_resource_create_common(struct 
pipe_screen *screen,
 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 struct radeon_winsys *ws)
 {
-   char llvm_string[32] = {};
+   char llvm_string[32] = {}, kernel_version[128] = {};
+   struct utsname uname_data;
 
ws->query_info(ws, >info);
 
+   if (uname(_data) == 0)
+   snprintf(kernel_version, sizeof(kernel_version),
+" / %s", uname_data.release);
+
 #if HAVE_LLVM
snprintf(llvm_string, sizeof(llvm_string),
 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
@@ -949,10 +955,10 @@ bool r600_common_screen_init(struct r600_common_screen 
*rscreen,
 #endif
 
snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
-"%s (DRM %i.%i.%i%s)",
+"%s (DRM %i.%i.%i%s%s)",
 r600_get_chip_name(rscreen), rscreen->info.drm_major,
 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
-llvm_string);
+kernel_version, llvm_string);
 
rscreen->b.get_name = r600_get_name;
rscreen->b.get_vendor = r600_get_vendor;

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Mesa (master): winsys/amdgpu: add back multithreaded command submission

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 53f33619a47b014b9ba7cc88310611081c5916db
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=53f33619a47b014b9ba7cc88310611081c5916db

Author: Marek Olšák 
Date:   Tue Mar  8 01:19:31 2016 +0100

winsys/amdgpu: add back multithreaded command submission

Ported from the initial amdgpu winsys from the private AMD branch.

The thread creates the buffer list, submits IBs, and cleans up
the submission context, which can also destroy buffers.

3-5% reduction in CPU overhead is expected for apps submitting a lot
of IBs per frame. This is most visible with DMA IBs.

v2: use a semaphore instead of a busy loop in amdgpu_ws_queue_cs
add another amdgpu_cs_sync_flush call into amdgpu_bo_map

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c |  30 ++-
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.h |   4 +
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 313 +-
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.h |  52 +++--
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c |  63 ++
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h |  10 +
 6 files changed, 341 insertions(+), 131 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index bd69790..2555d57 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -43,8 +43,21 @@ static bool amdgpu_bo_wait(struct pb_buffer *_buf, uint64_t 
timeout,
 {
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
struct amdgpu_winsys *ws = bo->ws;
+   int64_t abs_timeout;
int i;
 
+   if (timeout == 0) {
+  if (p_atomic_read(>num_active_ioctls))
+ return false;
+
+   } else {
+  abs_timeout = os_time_get_absolute_timeout(timeout);
+
+  /* Wait if any ioctl is being submitted with this buffer. */
+  if (!os_wait_until_zero_abs_timeout(>num_active_ioctls, abs_timeout))
+ return false;
+   }
+
if (bo->is_shared) {
   /* We can't use user fences for shared buffers, because user fences
* are local to this process only. If we want to wait for all buffer
@@ -61,7 +74,6 @@ static bool amdgpu_bo_wait(struct pb_buffer *_buf, uint64_t 
timeout,
}
 
if (timeout == 0) {
-  /* Timeout == 0 is quite simple. */
   pipe_mutex_lock(ws->bo_fence_lock);
   for (i = 0; i < RING_LAST; i++)
  if (bo->fence[i]) {
@@ -80,7 +92,6 @@ static bool amdgpu_bo_wait(struct pb_buffer *_buf, uint64_t 
timeout,
   struct pipe_fence_handle *fence[RING_LAST] = {};
   bool fence_idle[RING_LAST] = {};
   bool buffer_idle = true;
-  int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
 
   /* Take references to all fences, so that we can wait for them
* without the lock. */
@@ -209,13 +220,24 @@ static void *amdgpu_bo_map(struct pb_buffer *buf,
 if (cs && amdgpu_bo_is_referenced_by_cs_with_usage(cs, bo,

RADEON_USAGE_WRITE)) {
cs->flush_cs(cs->flush_data, 0, NULL);
+} else {
+   /* Try to avoid busy-waiting in amdgpu_bo_wait. */
+   if (p_atomic_read(>num_active_ioctls))
+  amdgpu_cs_sync_flush(rcs);
 }
 amdgpu_bo_wait((struct pb_buffer*)bo, PIPE_TIMEOUT_INFINITE,
RADEON_USAGE_WRITE);
  } else {
 /* Mapping for write. */
-if (cs && amdgpu_bo_is_referenced_by_cs(cs, bo))
-   cs->flush_cs(cs->flush_data, 0, NULL);
+if (cs) {
+   if (amdgpu_bo_is_referenced_by_cs(cs, bo)) {
+  cs->flush_cs(cs->flush_data, 0, NULL);
+   } else {
+  /* Try to avoid busy-waiting in amdgpu_bo_wait. */
+  if (p_atomic_read(>num_active_ioctls))
+ amdgpu_cs_sync_flush(rcs);
+   }
+}
 
 amdgpu_bo_wait((struct pb_buffer*)bo, PIPE_TIMEOUT_INFINITE,
RADEON_USAGE_READWRITE);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
index 69ada10..a768771 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
@@ -53,6 +53,10 @@ struct amdgpu_winsys_bo {
/* how many command streams is this bo referenced in? */
int num_cs_references;
 
+   /* how many command streams, which are being emitted in a separate
+* thread, is this bo referenced in? */
+   volatile int num_active_ioctls;
+
/* whether buffer_get_handle or buffer_from_handle was called,
 * it can only transition from false to true
 */
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index ffb0b7b..e949874 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ 

Mesa (master): gallium/tgsi: use _mesa_roundevenf in micro_rnd

[Brian Paul]

Module: Mesa
Branch: master
Commit: c626a86586f1cfc7c6423e74cd63c1da212365c9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c626a86586f1cfc7c6423e74cd63c1da212365c9

Author: Lars Hamre 
Date:   Thu May 19 15:34:00 2016 -0600

gallium/tgsi: use _mesa_roundevenf in micro_rnd

Fixes the following piglit tests (for softpipe):

/spec/glsl-1.30/execution/built-in-functions/...
fs-roundeven-float
fs-roundeven-vec2
fs-roundeven-vec3
fs-roundeven-vec4
vs-roundeven-float
vs-roundeven-vec2
vs-roundeven-vec3
vs-roundeven-vec4

/spec/glsl-1.50/execution/built-in-functions/...
gs-roundeven-float
gs-roundeven-vec2
gs-roundeven-vec3
gs-roundeven-vec4

Signed-off-by: Lars Hamre 
Reviewed-by: Matt Turner 
Reviewed-by: Brian Paul 

---

 src/gallium/auxiliary/tgsi/tgsi_exec.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c 
b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index d483429..baf4a89 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -61,6 +61,7 @@
 #include "util/u_half.h"
 #include "util/u_memory.h"
 #include "util/u_math.h"
+#include "util/rounding.h"
 
 
 #define DEBUG_EXECUTION 0
@@ -543,10 +544,10 @@ static void
 micro_rnd(union tgsi_exec_channel *dst,
   const union tgsi_exec_channel *src)
 {
-   dst->f[0] = floorf(src->f[0] + 0.5f);
-   dst->f[1] = floorf(src->f[1] + 0.5f);
-   dst->f[2] = floorf(src->f[2] + 0.5f);
-   dst->f[3] = floorf(src->f[3] + 0.5f);
+   dst->f[0] = _mesa_roundevenf(src->f[0]);
+   dst->f[1] = _mesa_roundevenf(src->f[1]);
+   dst->f[2] = _mesa_roundevenf(src->f[2]);
+   dst->f[3] = _mesa_roundevenf(src->f[3]);
 }
 
 static void

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Mesa (master): .mailmap: use Jakob Bornecrantz's personal email

[Emil Velikov]

Module: Mesa
Branch: master
Commit: d519f59a9f44354e433bb71b56934a18e43446f3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d519f59a9f44354e433bb71b56934a18e43446f3

Author: Emil Velikov 
Date:   Thu May 26 13:57:32 2016 +0100

.mailmap: use Jakob Bornecrantz's personal email

The VMware one is bouncing.

Signed-off-by: Emil Velikov 

---

 .mailmap | 11 +--
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/.mailmap b/.mailmap
index fb35e30..3c4add7 100644
--- a/.mailmap
+++ b/.mailmap
@@ -168,12 +168,11 @@ Hui Qi Tay  
 Ian Romanick  
 Ian Romanick  
 
-Jakob Bornecrantz  
-Jakob Bornecrantz  
-Jakob Bornecrantz  
-Jakob Bornecrantz  
-Jakob Bornecrantz  
-Jakob Bornecrantz  
+Jakob Bornecrantz  
+Jakob Bornecrantz  
+Jakob Bornecrantz  
+Jakob Bornecrantz  
+Jakob Bornecrantz  
 
 Jakub Bogusz  
 

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Mesa (master): nvc0: enable 32 textures on kepler+

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: b634936d3b05712ece5ddda4da3c161e293e6678
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b634936d3b05712ece5ddda4da3c161e293e6678

Author: Ilia Mirkin 
Date:   Sat May 21 19:09:32 2016 -0400

nvc0: enable 32 textures on kepler+

For fermi, this likely will require use of linked tsc mode. However on
bindless architectures, we can have as many as we want. As it stands,
the AUX_TEX_INFO has 32 teture handles reserved.

Signed-off-by: Ilia Mirkin 
Reviewed-by: Samuel Pitoiset 

---

 src/gallium/drivers/nouveau/nvc0/nvc0_context.h | 2 +-
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c  | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h 
b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
index 436e912..5be78aa 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
@@ -197,7 +197,7 @@ struct nvc0_context {
uint32_t textures_coherent[6];
struct nv50_tsc_entry *samplers[6][PIPE_MAX_SAMPLERS];
unsigned num_samplers[6];
-   uint16_t samplers_dirty[6];
+   uint32_t samplers_dirty[6];
bool seamless_cube_map;
 
uint32_t tex_handles[6][PIPE_MAX_SAMPLERS]; /* for nve4 */
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 7d692ea..4c47503 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -369,9 +369,9 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, 
unsigned shader,
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
   return NVC0_MAX_BUFFERS;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
-  return 16; /* would be 32 in linked (OpenGL-style) mode */
+  return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
-  return 16; /* XXX not sure if more are really safe */
+  return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
   return 32;
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:

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Mesa (master): nvc0: add note about where the viewport mask would go

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: f998e5dc6bc9f844cfb1b080a740771022a29aa9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f998e5dc6bc9f844cfb1b080a740771022a29aa9

Author: Ilia Mirkin 
Date:   Thu May 26 00:02:57 2016 -0400

nvc0: add note about where the viewport mask would go

Not piping this all the way through yet, but no better place to note
this down. This will can be used with NV_viewport_array2.

Signed-off-by: Ilia Mirkin 

---

 src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index 4177d8d..d73e0c4 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -80,6 +80,7 @@ nvc0_shader_output_address(unsigned sn, unsigned si)
case TGSI_SEMANTIC_CLIPDIST:  return 0x2c0 + si * 0x10;
case TGSI_SEMANTIC_CLIPVERTEX:return 0x270;
case TGSI_SEMANTIC_TEXCOORD:  return 0x300 + si * 0x10;
+   /* case TGSI_SEMANTIC_VIEWPORT_MASK: return 0x3a0; */
case TGSI_SEMANTIC_EDGEFLAG:  return ~0;
default:
   assert(!"invalid TGSI output semantic");

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Mesa (master): glsl: add unit tests data vertex/ expected outcome for uninitialized warning

[Alejandro Pinheiro]

Module: Mesa
Branch: master
Commit: 2ed9563e79670ba2430f0827050e9a851fc56e79
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ed9563e79670ba2430f0827050e9a851fc56e79

Author: Alejandro Piñeiro 
Date:   Wed Apr 20 10:02:45 2016 +0200

glsl: add unit tests data vertex/expected outcome for uninitialized warning

v2: fix 025 test. Add three more tests (Ian Romanick)

Reviewed-by: Ian Romanick 

---

 .../glsl/tests/warnings/000-basic-test.vert| 10 
 .../tests/warnings/000-basic-test.vert.expected|  1 +
 .../warnings/001-use-undefined-then-define.vert| 12 ++
 .../001-use-undefined-then-define.vert.expected|  1 +
 src/compiler/glsl/tests/warnings/002-loop.vert | 23 ++
 .../glsl/tests/warnings/002-loop.vert.expected |  3 +++
 src/compiler/glsl/tests/warnings/003-less.vert | 17 +
 .../glsl/tests/warnings/003-less.vert.expected |  1 +
 src/compiler/glsl/tests/warnings/004-greater.vert  | 17 +
 .../glsl/tests/warnings/004-greater.vert.expected  |  1 +
 src/compiler/glsl/tests/warnings/005-lequal.vert   | 17 +
 .../glsl/tests/warnings/005-lequal.vert.expected   |  1 +
 src/compiler/glsl/tests/warnings/006-gequal.vert   | 17 +
 .../glsl/tests/warnings/006-gequal.vert.expected   |  1 +
 src/compiler/glsl/tests/warnings/007-test-mod.vert | 25 +++
 .../glsl/tests/warnings/007-test-mod.vert.expected |  3 +++
 .../glsl/tests/warnings/008-mulassign.vert | 12 ++
 .../tests/warnings/008-mulassign.vert.expected |  1 +
 .../glsl/tests/warnings/009-div-assign.vert| 12 ++
 .../tests/warnings/009-div-assign.vert.expected|  1 +
 .../glsl/tests/warnings/010-add-assign.vert| 12 ++
 .../tests/warnings/010-add-assign.vert.expected|  1 +
 .../glsl/tests/warnings/011-sub-assign.vert| 12 ++
 .../tests/warnings/011-sub-assign.vert.expected|  1 +
 .../glsl/tests/warnings/012-modassign.vert | 12 ++
 .../tests/warnings/012-modassign.vert.expected |  1 +
 src/compiler/glsl/tests/warnings/013-lsassign.vert | 12 ++
 .../glsl/tests/warnings/013-lsassign.vert.expected |  1 +
 src/compiler/glsl/tests/warnings/014-rsassign.vert | 12 ++
 .../glsl/tests/warnings/014-rsassign.vert.expected |  1 +
 .../glsl/tests/warnings/015-andassign.vert | 12 ++
 .../tests/warnings/015-andassign.vert.expected |  1 +
 src/compiler/glsl/tests/warnings/016-orassign.vert | 12 ++
 .../glsl/tests/warnings/016-orassign.vert.expected |  1 +
 .../glsl/tests/warnings/017-xorassign.vert | 12 ++
 .../tests/warnings/017-xorassign.vert.expected |  1 +
 src/compiler/glsl/tests/warnings/018-bitand.vert   | 24 +++
 .../glsl/tests/warnings/018-bitand.vert.expected   |  3 +++
 src/compiler/glsl/tests/warnings/019-array.vert| 23 ++
 .../glsl/tests/warnings/019-array.vert.expected|  5 
 .../glsl/tests/warnings/020-array-length.vert  | 12 ++
 .../tests/warnings/020-array-length.vert.expected  |  0
 src/compiler/glsl/tests/warnings/021-lshift.vert   | 25 +++
 .../glsl/tests/warnings/021-lshift.vert.expected   |  3 +++
 src/compiler/glsl/tests/warnings/022-rshift.vert   | 25 +++
 .../glsl/tests/warnings/022-rshift.vert.expected   |  3 +++
 src/compiler/glsl/tests/warnings/023-switch.vert   | 28 ++
 .../glsl/tests/warnings/023-switch.vert.expected   |  3 +++
 .../glsl/tests/warnings/024-shaderout.vert | 19 +++
 .../tests/warnings/024-shaderout.vert.expected |  2 ++
 .../tests/warnings/025-function-parameters.vert| 16 +
 .../warnings/025-function-parameters.vert.expected |  2 ++
 .../026-out-function-parameter-shaderout.vert  | 14 +++
 ...-out-function-parameter-shaderout.vert.expected |  0
 .../027-inout-function-parameter-shaderout.vert| 14 +++
 ...nout-function-parameter-shaderout.vert.expected |  1 +
 .../glsl/tests/warnings/028-conditional.vert   | 17 +
 .../tests/warnings/028-conditional.vert.expected   |  6 +
 .../glsl/tests/warnings/029-fieldselection.vert| 23 ++
 .../warnings/029-fieldselection.vert.expected  |  1 +
 .../warnings/030-array-as-function-parameter.vert  | 17 +
 .../030-array-as-function-parameter.vert.expected  |  7 ++
 62 files changed, 573 insertions(+)

diff --git a/src/compiler/glsl/tests/warnings/000-basic-test.vert 
b/src/compiler/glsl/tests/warnings/000-basic-test.vert
new file mode 100644
index 000..266eed6
--- /dev/null
+++ b/src/compiler/glsl/tests/warnings/000-basic-test.vert
@@ -0,0 +1,10 @@
+#version 130
+
+void main()
+{
+  float foo;
+  float undefined;
+
+  foo = undefined;
+}
+
diff --git a/src/compiler/glsl/tests/warnings/000-basic-test.vert.expected 

Mesa (master): glsl: add a empty set_is_lhs on ast_node

[Alejandro Pinheiro]

Module: Mesa
Branch: master
Commit: b9f90ef652dae687a5aff97f9132b374320638a5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9f90ef652dae687a5aff97f9132b374320638a5

Author: Alejandro Piñeiro 
Date:   Tue Apr 19 11:15:54 2016 +0200

glsl: add a empty set_is_lhs on ast_node

Just to allow to call set_is_lhs on any ast_node without a casting. Useful
when processing a ast_node list that we know it contain ast_expression.

v2: comment out new_value to avoid unused parameter warning (Ian Romanick)

Reviewed-by: Ian Romanick 

---

 src/compiler/glsl/ast.h  | 2 ++
 src/compiler/glsl/ast_to_hir.cpp | 5 +
 2 files changed, 7 insertions(+)

diff --git a/src/compiler/glsl/ast.h b/src/compiler/glsl/ast.h
index fb25bb3..ca98ed2 100644
--- a/src/compiler/glsl/ast.h
+++ b/src/compiler/glsl/ast.h
@@ -126,6 +126,8 @@ public:
 
exec_node link;
 
+   virtual void set_is_lhs(bool);
+
 protected:
/**
 * The only constructor is protected so that only derived class objects can
diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index 22bc008..e1e26f8 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -1054,6 +1054,11 @@ ast_node::has_sequence_subexpression() const
 }
 
 void
+ast_node::set_is_lhs(bool /* new_value */)
+{
+}
+
+void
 ast_function_expression::hir_no_rvalue(exec_list *instructions,
struct _mesa_glsl_parse_state *state)
 {

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Mesa (master): glsl: add just-log option for the standalone compiler.

[Alejandro Pinheiro]

Module: Mesa
Branch: master
Commit: 68c23d2d046b6419c7b3bd273278235095e29dae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=68c23d2d046b6419c7b3bd273278235095e29dae

Author: Alejandro Piñeiro 
Date:   Tue Apr 19 20:26:32 2016 +0200

glsl: add just-log option for the standalone compiler.

Add an option in order to ask to just print the InfoLog, without any
header or separator. Useful if we want to use the standalone compiler
to track only the warning/error messages.

v2: all printfs goes on its own line (Ian Romanick)
v3: rebasing: move just_log to standalone.h/cpp

Reviewed-by: Ian Romanick 

---

 src/compiler/glsl/main.cpp   |  1 +
 src/compiler/glsl/standalone.cpp | 20 
 src/compiler/glsl/standalone.h   |  1 +
 3 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/src/compiler/glsl/main.cpp b/src/compiler/glsl/main.cpp
index f65b185..1e5e0fe 100644
--- a/src/compiler/glsl/main.cpp
+++ b/src/compiler/glsl/main.cpp
@@ -43,6 +43,7 @@ const struct option compiler_opts[] = {
{ "dump-hir", no_argument, _hir, 1 },
{ "dump-lir", no_argument, _lir, 1 },
{ "link", no_argument, _link,  1 },
+   { "just-log", no_argument, _log, 1 },
{ "version",  required_argument, NULL, 'v' },
{ NULL, 0, NULL, 0 }
 };
diff --git a/src/compiler/glsl/standalone.cpp b/src/compiler/glsl/standalone.cpp
index e5b9057..c9f20e4 100644
--- a/src/compiler/glsl/standalone.cpp
+++ b/src/compiler/glsl/standalone.cpp
@@ -381,8 +381,14 @@ standalone_compile_shader(const struct standalone_options 
*_options,
 
   compile_shader(ctx, shader);
 
-  if (strlen(shader->InfoLog) > 0)
- printf("Info log for %s:\n%s\n", files[i], shader->InfoLog);
+  if (strlen(shader->InfoLog) > 0) {
+ if (!options->just_log)
+printf("Info log for %s:\n", files[i]);
+
+ printf("%s", shader->InfoLog);
+ if (!options->just_log)
+printf("\n");
+  }
 
   if (!shader->CompileStatus) {
  status = EXIT_FAILURE;
@@ -396,8 +402,14 @@ standalone_compile_shader(const struct standalone_options 
*_options,
   link_shaders(ctx, whole_program);
   status = (whole_program->LinkStatus) ? EXIT_SUCCESS : EXIT_FAILURE;
 
-  if (strlen(whole_program->InfoLog) > 0)
- printf("Info log for linking:\n%s\n", whole_program->InfoLog);
+  if (strlen(whole_program->InfoLog) > 0) {
+ printf("\n");
+ if (!options->just_log)
+printf("Info log for linking:\n");
+ printf("%s", whole_program->InfoLog);
+ if (!options->just_log)
+printf("\n");
+  }
 
   for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
  struct gl_shader *shader = whole_program->_LinkedShaders[i];
diff --git a/src/compiler/glsl/standalone.h b/src/compiler/glsl/standalone.h
index 5b387c5..648cedb 100644
--- a/src/compiler/glsl/standalone.h
+++ b/src/compiler/glsl/standalone.h
@@ -34,6 +34,7 @@ struct standalone_options {
int dump_hir;
int dump_lir;
int do_link;
+   int just_log;
 };
 
 struct gl_shader_program;

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Mesa (master): glsl: add warning-test

[Alejandro Pinheiro]

Module: Mesa
Branch: master
Commit: eee00274fa330edfa536da039ba9116bdceb9990
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eee00274fa330edfa536da039ba9116bdceb9990

Author: Alejandro Piñeiro 
Date:   Tue Apr 19 21:03:07 2016 +0200

glsl: add warning-test

It executes compiler-glsl on all the available shaders, and it checks
that the outcome is the expected.

Bash code based on the already existing optimization-test

v2: rebasing: use --version option

Reviewed-by: Ian Romanick 

---

 src/compiler/Makefile.glsl.am |  3 ++-
 src/compiler/glsl/tests/warnings-test | 31 +++
 2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/src/compiler/Makefile.glsl.am b/src/compiler/Makefile.glsl.am
index 23c2a6b..4e90f16 100644
--- a/src/compiler/Makefile.glsl.am
+++ b/src/compiler/Makefile.glsl.am
@@ -35,7 +35,8 @@ TESTS += glsl/glcpp/tests/glcpp-test  \
glsl/tests/general-ir-test  \
glsl/tests/optimization-test\
glsl/tests/sampler-types-test   \
-   glsl/tests/uniform-initializer-test
+   glsl/tests/uniform-initializer-test \
+   glsl/tests/warnings-test
 
 TESTS_ENVIRONMENT= \
export PYTHON2=$(PYTHON2); \
diff --git a/src/compiler/glsl/tests/warnings-test 
b/src/compiler/glsl/tests/warnings-test
new file mode 100755
index 000..1bea466
--- /dev/null
+++ b/src/compiler/glsl/tests/warnings-test
@@ -0,0 +1,31 @@
+#!/usr/bin/env bash
+
+# Execute several shaders, and check that the InfoLog outcome is the expected.
+
+compiler=./glsl_compiler
+total=0
+pass=0
+
+echo "== Testing compilation output =="
+for test in `find . -iname '*.vert'`; do
+echo -n "Testing $test..."
+$compiler --just-log --version 150 "$test" > "$test.out" 2>&1
+total=$((total+1))
+if diff "$test.expected" "$test.out" >/dev/null 2>&1; then
+echo "PASS"
+pass=$((pass+1))
+else
+echo "FAIL"
+diff "$test.expected" "$test.out"
+fi
+done
+
+echo ""
+echo "$pass/$total tests returned correct results"
+echo ""
+
+if [[ $pass == $total ]]; then
+exit 0
+else
+exit 1
+fi

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Mesa (master): glsl: do not raise uninitialized warning with out function parameters

[Alejandro Pinheiro]

Module: Mesa
Branch: master
Commit: 66ff04322e80d14d9b1c8a4d1ef8cf63440242af
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=66ff04322e80d14d9b1c8a4d1ef8cf63440242af

Author: Alejandro Piñeiro 
Date:   Tue Apr 19 11:17:27 2016 +0200

glsl: do not raise uninitialized warning with out function parameters

It silence by default warnings with function parameters, as the
parameters need to be processed in order to have the actual and the
formal parameter, and the function signature. Then it raises the
warning if needed at verify_parameter_modes where other in/out/inout modes
checks are done.

v2: fix comment style, multi-line condition style, simplify check,
remove extra blank (Ian Romanick)
v3: inout function parameters can raise the warning too (Ian
Romanick)

Reviewed-by: Ian Romanick 

---

 src/compiler/glsl/ast_function.cpp | 28 
 1 file changed, 28 insertions(+)

diff --git a/src/compiler/glsl/ast_function.cpp 
b/src/compiler/glsl/ast_function.cpp
index 4433fdd..a97e6c9 100644
--- a/src/compiler/glsl/ast_function.cpp
+++ b/src/compiler/glsl/ast_function.cpp
@@ -43,6 +43,12 @@ process_parameters(exec_list *instructions, exec_list 
*actual_parameters,
unsigned count = 0;
 
foreach_list_typed(ast_node, ast, link, parameters) {
+  /* We need to process the parameters first in order to know if we can
+   * raise or not a unitialized warning. Calling set_is_lhs silence the
+   * warning for now. Raising the warning or not will be checked at
+   * verify_parameter_modes.
+   */
+  ast->set_is_lhs(true);
   ir_rvalue *result = ast->hir(instructions, state);
 
   ir_constant *const constant = result->constant_expression_value();
@@ -257,6 +263,16 @@ verify_parameter_modes(_mesa_glsl_parse_state *state,
 }
 
 ir_variable *var = actual->variable_referenced();
+
+ if (var && formal->data.mode == ir_var_function_inout) {
+if ((var->data.mode == ir_var_auto || var->data.mode == 
ir_var_shader_out) &&
+!var->data.assigned &&
+!is_gl_identifier(var->name)) {
+   _mesa_glsl_warning(, state, "`%s' used uninitialized",
+  var->name);
+}
+ }
+
 if (var)
var->data.assigned = true;
 
@@ -273,6 +289,18 @@ verify_parameter_modes(_mesa_glsl_parse_state *state,
  mode, formal->name);
 return false;
 }
+  } else {
+ assert(formal->data.mode == ir_var_function_in ||
+formal->data.mode == ir_var_const_in);
+ ir_variable *var = actual->variable_referenced();
+ if (var) {
+if ((var->data.mode == ir_var_auto || var->data.mode == 
ir_var_shader_out) &&
+!var->data.assigned &&
+!is_gl_identifier(var->name)) {
+   _mesa_glsl_warning(, state, "`%s' used uninitialized",
+  var->name);
+}
+ }
   }
 
   if (formal->type->is_image() &&

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