Mesa (master): i965/xfb: skip components in correct buffer.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: ebb81cd6839c5b0f7094e86f846958f10791f9bd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ebb81cd6839c5b0f7094e86f846958f10791f9bd

Author: Dave Airlie 
Date:   Wed Jun  1 14:10:22 2016 +1000

i965/xfb: skip components in correct buffer.

The driver was adding the skip components but always for buffer 0.

This fixes:
GL45-CTS.gtf40.GL3Tests.transform_feedback3.transform_feedback3_skip_multiple_buffers

Reviewed-by: Kenneth Graunke 
Cc: "12.0 11.2" 
Signed-off-by: Dave Airlie 

---

 src/mesa/drivers/dri/i965/gen7_sol_state.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c 
b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index f7b1443..4749cc8 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -123,7 +123,7 @@ gen7_upload_3dstate_so_decl_list(struct brw_context *brw,
   const unsigned components = linked_xfb_info->Outputs[i].NumComponents;
   unsigned component_mask = (1 << components) - 1;
   unsigned stream_id = linked_xfb_info->Outputs[i].StreamId;
-
+  unsigned decl_buffer_slot = buffer << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT;
   assert(stream_id < MAX_VERTEX_STREAMS);
 
   /* gl_PointSize is stored in VARYING_SLOT_PSIZ.w
@@ -145,7 +145,7 @@ gen7_upload_3dstate_so_decl_list(struct brw_context *brw,
 
   buffer_mask[stream_id] |= 1 << buffer;
 
-  decl |= buffer << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT;
+  decl |= decl_buffer_slot;
   if (varying == VARYING_SLOT_LAYER || varying == VARYING_SLOT_VIEWPORT) {
  decl |= vue_map->varying_to_slot[VARYING_SLOT_PSIZ] <<
 SO_DECL_REGISTER_INDEX_SHIFT;
@@ -172,12 +172,14 @@ gen7_upload_3dstate_so_decl_list(struct brw_context *brw,
   next_offset[buffer] += skip_components;
 
   while (skip_components >= 4) {
- so_decl[stream_id][decls[stream_id]++] = SO_DECL_HOLE_FLAG | 0xf;
+ so_decl[stream_id][decls[stream_id]++] =
+SO_DECL_HOLE_FLAG | 0xf | decl_buffer_slot;
  skip_components -= 4;
   }
   if (skip_components > 0)
  so_decl[stream_id][decls[stream_id]++] =
-SO_DECL_HOLE_FLAG | ((1 << skip_components) - 1);
+SO_DECL_HOLE_FLAG | ((1 << skip_components) - 1) |
+decl_buffer_slot;
 
   assert(linked_xfb_info->Outputs[i].DstOffset == next_offset[buffer]);
 

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Mesa (master): mesa/bufferobj: use mapping range in BufferSubData.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: e891f7cf55f2f3e3d37ece12e5c64f4be70e3845
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e891f7cf55f2f3e3d37ece12e5c64f4be70e3845

Author: Dave Airlie 
Date:   Wed May 25 14:02:27 2016 +1000

mesa/bufferobj: use mapping range in BufferSubData.

According to GL4.5 spec:
An INVALID_OPERATION error is generated if any part of the speci-
fied buffer range is mapped with MapBufferRange or MapBuffer (see sec-
tion 6.3), unless it was mapped with MAP_PERSISTENT_BIT set in the Map-
BufferRange access flags.

So we should use the if range is mapped path.

This fixes:
GL45-CTS.buffer_storage.map_persistent_buffer_sub_data

Reviewed-by: Nicolai Hähnle 
Cc: "12.0, 11.2" 
Signed-off-by: Dave Airlie 

---

 src/mesa/main/bufferobj.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index 33bc574..795cb16 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -1765,7 +1765,7 @@ _mesa_buffer_sub_data(struct gl_context *ctx, struct 
gl_buffer_object *bufObj,
   const char *func)
 {
if (!buffer_object_subdata_range_good(ctx, bufObj, offset, size,
- false, func)) {
+ true, func)) {
   /* error already recorded */
   return;
}

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Mesa (master): glsl/linker: fix multiple streams transform feedback.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 1fe7bbb911ac708999685c942e971693b688a334
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1fe7bbb911ac708999685c942e971693b688a334

Author: Dave Airlie 
Date:   Tue May 31 12:51:47 2016 +1000

glsl/linker: fix multiple streams transform feedback.

e2791b38b42f83add5b07298c39741bf0a6d7d4b
mesa/program_interface_query: fix transform feedback varyings.

caused a regression in
GL45-CTS.gtf40.GL3Tests.transform_feedback3.transform_feedback3_multiple_streams
on radeonsi.

The problem was it was using the skip components varying to set
the stream id, when it should wait until a varying was written,
this just adds the varying checks in the right place.

Cc: "12.0" 
Reviewed-by: Timothy Arceri 
Signed-off-by: Dave Airlie 

---

 src/compiler/glsl/link_varyings.cpp | 32 +---
 1 file changed, 17 insertions(+), 15 deletions(-)

diff --git a/src/compiler/glsl/link_varyings.cpp 
b/src/compiler/glsl/link_varyings.cpp
index 7c3bedf..a286e77 100644
--- a/src/compiler/glsl/link_varyings.cpp
+++ b/src/compiler/glsl/link_varyings.cpp
@@ -1117,21 +1117,23 @@ store_tfeedback_info(struct gl_context *ctx, struct 
gl_shader_program *prog,
 num_buffers++;
 buffer_stream_id = -1;
 continue;
- } else if (buffer_stream_id == -1)  {
-/* First varying writing to this buffer: remember its stream */
-buffer_stream_id = (int) tfeedback_decls[i].get_stream_id();
- } else if (buffer_stream_id !=
-(int) tfeedback_decls[i].get_stream_id()) {
-/* Varying writes to the same buffer from a different stream */
-linker_error(prog,
- "Transform feedback can't capture varyings belonging "
- "to different vertex streams in a single buffer. "
- "Varying %s writes to buffer from stream %u, other "
- "varyings in the same buffer write from stream %u.",
- tfeedback_decls[i].name(),
- tfeedback_decls[i].get_stream_id(),
- buffer_stream_id);
-return false;
+ } else if (tfeedback_decls[i].is_varying()) {
+if (buffer_stream_id == -1)  {
+   /* First varying writing to this buffer: remember its stream */
+   buffer_stream_id = (int) tfeedback_decls[i].get_stream_id();
+} else if (buffer_stream_id !=
+   (int) tfeedback_decls[i].get_stream_id()) {
+   /* Varying writes to the same buffer from a different stream */
+   linker_error(prog,
+"Transform feedback can't capture varyings 
belonging "
+"to different vertex streams in a single buffer. "
+"Varying %s writes to buffer from stream %u, other 
"
+"varyings in the same buffer write from stream 
%u.",
+tfeedback_decls[i].name(),
+tfeedback_decls[i].get_stream_id(),
+buffer_stream_id);
+   return false;
+}
  }
 
  if (has_xfb_qualifiers) {

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Mesa (master): nv50/ir: fix error finding free element in bitset in some situations

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 18d11c998940d4228ce0f5057042a885f1aa65af
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=18d11c998940d4228ce0f5057042a885f1aa65af

Author: Ilia Mirkin 
Date:   Tue May 31 00:33:50 2016 -0400

nv50/ir: fix error finding free element in bitset in some situations

This really only hits for bitsets with a size of a multiple of 32. We
can end up with pos = -1 as a result of the ffs, which we in turn decide
is a valid position (since we fall through the loop and i == 1, we end
up adding 32 to it, so end up returning 31 again).

Up until recently this was largely unreachable, as the register file
sizes were all 63 or 255. However with the advent of compute shaders
which can restrict the number of registers, this can now happen.

Signed-off-by: Ilia Mirkin 
Cc: "12.0" 

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_util.cpp | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_util.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_util.cpp
index d26acb3..682c569 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_util.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_util.cpp
@@ -365,6 +365,12 @@ int BitSet::findFreeRange(unsigned int count) const
  }
   }
}
+
+   // If we couldn't find a position, we can have a left-over -1 in pos. Make
+   // sure to abort in such a case.
+   if (pos < 0)
+  return -1;
+
pos += i * 32;
 
return ((pos + count) <= size) ? pos : -1;

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Mesa (master): nv50/ir: print relevant file's bitset when showing RA info

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: d873608bcf97cddaaca396d29f065657c1f63039
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d873608bcf97cddaaca396d29f065657c1f63039

Author: Ilia Mirkin 
Date:   Tue May 31 00:33:19 2016 -0400

nv50/ir: print relevant file's bitset when showing RA info

Signed-off-by: Ilia Mirkin 

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index 6b52d7b..5bb6f78 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
@@ -101,7 +101,7 @@ public:
   return (size < 4) ? u : ((u << unit[f]) / 4);
}
 
-   void print() const;
+   void print(DataFile f) const;
 
const bool restrictedGPR16Range;
 
@@ -156,10 +156,10 @@ RegisterSet::intersect(DataFile f, const RegisterSet *set)
 }
 
 void
-RegisterSet::print() const
+RegisterSet::print(DataFile f) const
 {
INFO("GPR:");
-   bits[FILE_GPR].print();
+   bits[f].print();
INFO("\n");
 }
 
@@ -1424,7 +1424,7 @@ GCRA::selectRegisters()
  continue;
   LValue *lval = node->getValue();
   if (prog->dbgFlags & NV50_IR_DEBUG_REG_ALLOC)
- regs.print();
+ regs.print(node->f);
   bool ret = regs.assign(node->reg, node->f, node->colors);
   if (ret) {
  INFO_DBG(prog->dbgFlags, REG_ALLOC, "assigned reg %i\n", node->reg);

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Mesa (master): Revert "glsl: fix xfb_offset unsized array validation"

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 98d40b4d1195ebfaa2fd9ed43755ca6896422c1a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=98d40b4d1195ebfaa2fd9ed43755ca6896422c1a

Author: Timothy Arceri 
Date:   Wed Jun  1 09:21:01 2016 +1000

Revert "glsl: fix xfb_offset unsized array validation"

This reverts commit aac90ba2920cf5ceb4df6dba776dd3952780e456.

The commit caused a regression in:
piglit.spec.glsl-1_50.compiler.gs-input-nonarray-named-block.geom

Also the CTS test it was meant to fix seems like it may be bogus.

Cc: "12.0" 

---

 src/compiler/glsl/ast_to_hir.cpp| 23 ---
 src/compiler/glsl/ir.cpp| 23 ---
 src/compiler/glsl/ir.h  |  3 ---
 src/compiler/glsl/link_varyings.cpp | 23 +++
 4 files changed, 31 insertions(+), 41 deletions(-)

diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index c0cb3d6..400d3c4 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -3442,11 +3442,11 @@ apply_layout_qualifier_to_variable(const struct 
ast_type_qualifier *qual,
if (qual->flags.q.explicit_xfb_offset) {
   unsigned qual_xfb_offset;
   unsigned component_size = var->type->contains_double() ? 8 : 4;
-  const glsl_type *t = get_varying_type(var, state->stage);
+
   if (process_qualifier_constant(state, loc, "xfb_offset",
  qual->offset, _xfb_offset) &&
   validate_xfb_offset_qualifier(loc, state, (int) qual_xfb_offset,
-t, component_size)) {
+var->type, component_size)) {
  var->data.offset = qual_xfb_offset;
  var->data.explicit_xfb_offset = true;
   }
@@ -7336,6 +7336,12 @@ ast_interface_block::hir(exec_list *instructions,
 packing,
 this->block_name);
 
+   unsigned component_size = block_type->contains_double() ? 8 : 4;
+   int xfb_offset =
+  layout.flags.q.explicit_xfb_offset ? (int) qual_xfb_offset : -1;
+   validate_xfb_offset_qualifier(, state, xfb_offset, block_type,
+ component_size);
+
if (!state->symbols->add_interface(block_type->name, block_type, var_mode)) 
{
   YYLTYPE loc = this->get_location();
   _mesa_glsl_error(, state, "interface block `%s' with type `%s' "
@@ -7474,13 +7480,6 @@ ast_interface_block::hir(exec_list *instructions,
   var_mode);
   }
 
-  unsigned component_size = block_type->contains_double() ? 8 : 4;
-  int xfb_offset =
- layout.flags.q.explicit_xfb_offset ? (int) qual_xfb_offset : -1;
-  const glsl_type *t = get_varying_type(var, state->stage);
-  validate_xfb_offset_qualifier(, state, xfb_offset, t,
-component_size);
-
   var->data.matrix_layout = matrix_layout == GLSL_MATRIX_LAYOUT_INHERITED
  ? GLSL_MATRIX_LAYOUT_COLUMN_MAJOR : matrix_layout;
 
@@ -7531,12 +7530,6 @@ ast_interface_block::hir(exec_list *instructions,
*/
   assert(this->array_specifier == NULL);
 
-  unsigned component_size = block_type->contains_double() ? 8 : 4;
-  int xfb_offset =
- layout.flags.q.explicit_xfb_offset ? (int) qual_xfb_offset : -1;
-  validate_xfb_offset_qualifier(, state, xfb_offset, block_type,
-component_size);
-
   for (unsigned i = 0; i < num_variables; i++) {
  ir_variable *var =
 new(state) ir_variable(fields[i].type,
diff --git a/src/compiler/glsl/ir.cpp b/src/compiler/glsl/ir.cpp
index 70859a7..5bb3ac3 100644
--- a/src/compiler/glsl/ir.cpp
+++ b/src/compiler/glsl/ir.cpp
@@ -2021,26 +2021,3 @@ mode_string(const ir_variable *var)
assert(!"Should not get here.");
return "invalid variable";
 }
-
-/**
- * Get the varying type stripped of the outermost array if we're processing
- * a stage whose varyings are arrays indexed by a vertex number (such as
- * geometry shader inputs).
- */
-const glsl_type *
-get_varying_type(const ir_variable *var, gl_shader_stage stage)
-{
-   const glsl_type *type = var->type;
-
-   if (!var->data.patch &&
-   ((var->data.mode == ir_var_shader_out &&
- stage == MESA_SHADER_TESS_CTRL) ||
-(var->data.mode == ir_var_shader_in &&
- (stage == MESA_SHADER_TESS_CTRL || stage == MESA_SHADER_TESS_EVAL ||
-  stage == MESA_SHADER_GEOMETRY {
-  assert(type->is_array());
-  type = type->fields.array;
-   }
-
-   return type;
-}
diff --git a/src/compiler/glsl/ir.h b/src/compiler/glsl/ir.h
index b1cfd52..e8efd27 100644
--- a/src/compiler/glsl/ir.h
+++ b/src/compiler/glsl/ir.h
@@ -2621,9 +2621,6 @@ is_gl_identifier(const char *s)
return s && s[0] == 'g' && s[1] == 'l' && s[2] == '_';
 }
 
-const glsl_type 

Mesa (master): i965/fs: Teach compute_to_mrf() about the COMPR4 address transformation.

[Francisco Jerez]

Module: Mesa
Branch: master
Commit: 1898673f586b9110fb2a3125e2781cbb1d795c73
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1898673f586b9110fb2a3125e2781cbb1d795c73

Author: Francisco Jerez 
Date:   Fri May 27 14:17:28 2016 -0700

i965/fs: Teach compute_to_mrf() about the COMPR4 address transformation.

This will be required to correctly transform the destination of 8-wide
instructions that write a single GRF of a VGRF to MRF copy marked
COMPR4.

Cc: "12.0" 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_fs.cpp | 24 +++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index bb36a8e..c04d642 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2894,8 +2894,30 @@ fs_visitor::compute_to_mrf()
   foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
  if (regions_overlap(scan_inst->dst, scan_inst->regs_written * 
REG_SIZE,
  inst->src[0], inst->regs_read(0) * REG_SIZE)) {
+const unsigned rel_offset = (reg_offset(scan_inst->dst) -
+ reg_offset(inst->src[0])) / REG_SIZE;
+
+if (inst->dst.nr & BRW_MRF_COMPR4) {
+   /* Apply the same address transformation done by the hardware
+* for COMPR4 MRF writes.
+*/
+   assert(rel_offset < 2);
+   scan_inst->dst.nr = inst->dst.nr + rel_offset * 4;
+
+   /* Clear the COMPR4 bit if the generating instruction is not
+* compressed.
+*/
+   if (scan_inst->regs_written < 2)
+  scan_inst->dst.nr &= ~BRW_MRF_COMPR4;
+
+} else {
+   /* Calculate the MRF number the result of this instruction is
+* ultimately written to.
+*/
+   scan_inst->dst.nr = inst->dst.nr + rel_offset;
+}
+
 scan_inst->dst.file = MRF;
-scan_inst->dst.nr = inst->dst.nr;
 scan_inst->dst.reg_offset = 0;
 scan_inst->saturate |= inst->saturate;
 break;

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Mesa (master): i965/fs: Fix compute-to-mrf VGRF region coverage condition.

[Francisco Jerez]

Module: Mesa
Branch: master
Commit: 4b0ec9f4759bab68b51e2f410e9305e39c1e1e7f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4b0ec9f4759bab68b51e2f410e9305e39c1e1e7f

Author: Francisco Jerez 
Date:   Fri May 27 16:41:35 2016 -0700

i965/fs: Fix compute-to-mrf VGRF region coverage condition.

Compute-to-mrf was checking whether the destination of scan_inst is
more than one component (making assumptions about the instruction data
type) in order to find out whether the result is being fully copied
into the MRF destination, which is rather inaccurate in cases where a
single-component instruction is only partially contained in the source
region, or when the execution size of the copy and scan_inst
instructions differ.  Instead check whether the destination region of
the instruction is really contained within the bounds of the source
region of the copy.

Cc: "12.0" 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_fs.cpp | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 172182a..b521f90 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2816,10 +2816,13 @@ fs_visitor::compute_to_mrf()
if (scan_inst->is_partial_write())
   break;
 
-/* Things returning more than one register would need us to
- * understand coalescing out more than one MOV at a time.
+/* Handling things not fully contained in the source of the copy
+ * would need us to understand coalescing out more than one MOV at
+ * a time.
  */
-if (scan_inst->regs_written > scan_inst->exec_size / 8)
+if (scan_inst->dst.reg_offset < inst->src[0].reg_offset ||
+scan_inst->dst.reg_offset + scan_inst->regs_written >
+inst->src[0].reg_offset + inst->regs_read(0))
break;
 
/* SEND instructions can't have MRF as a destination. */

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Mesa (master): i965/fs: Fix constant combining for instructions that cannot accept source mods.

[Francisco Jerez]

Module: Mesa
Branch: master
Commit: 06d8765bc09ecd8ff73fff424c8cfec645cb0ded
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=06d8765bc09ecd8ff73fff424c8cfec645cb0ded

Author: Francisco Jerez 
Date:   Fri May 27 23:29:10 2016 -0700

i965/fs: Fix constant combining for instructions that cannot accept source mods.

This is the case for SNB math instructions so we need to be careful
and insert the literal value of the immediate into the table (rather
than its absolute value) if the instruction is unable to invert the
sign of the constant on the fly.

Cc: "12.0" 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp
index d7a1456..5bd5343 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp
@@ -147,8 +147,6 @@ struct table {
 static struct imm *
 find_imm(struct table *table, float val)
 {
-   assert(signbit(val) == 0);
-
for (int i = 0; i < table->len; i++) {
   if (table->imm[i].val == val) {
  return >imm[i];
@@ -220,7 +218,8 @@ fs_visitor::opt_combine_constants()
  inst->src[i].type != BRW_REGISTER_TYPE_F)
 continue;
 
- float val = fabsf(inst->src[i].f);
+ float val = !inst->can_do_source_mods(devinfo) ? inst->src[i].f :
+ fabs(inst->src[i].f);
  struct imm *imm = find_imm(, val);
 
  if (imm) {
@@ -301,7 +300,7 @@ fs_visitor::opt_combine_constants()
  reg->stride = 0;
  reg->negate = signbit(reg->f) != signbit(table.imm[i].val);
  assert((isnan(reg->f) && isnan(table.imm[i].val)) ||
-fabsf(reg->f) == table.imm[i].val);
+fabsf(reg->f) == fabs(table.imm[i].val));
   }
}
 

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Mesa (master): i965/fs: Refactor compute_to_mrf() to split search and rewrite into separate loops.

[Francisco Jerez]

Module: Mesa
Branch: master
Commit: 485fbaff03f7d281ff4f22bd6321548512783799
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=485fbaff03f7d281ff4f22bd6321548512783799

Author: Francisco Jerez 
Date:   Fri May 27 13:15:55 2016 -0700

i965/fs: Refactor compute_to_mrf() to split search and rewrite into separate 
loops.

This will allow compute_to_mrf to handle cases where the source of the
VGRF-to-MRF copy is initialized by more than one instruction.  In such
cases we cannot rewrite the destination of any of the generating
instructions until it's known whether the whole VGRF source region can
be coalesced into the destination MRF, which will imply continuing the
search until all generating instructions have been found or it has
been determined that the VGRF and MRF registers cannot be coalesced.

Cc: "12.0" 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_fs.cpp | 35 +--
 1 file changed, 25 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index b521f90..bb36a8e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2801,6 +2801,8 @@ fs_visitor::compute_to_mrf()
   /* Found a move of a GRF to a MRF.  Let's see if we can go
* rewrite the thing that made this GRF to write into the MRF.
*/
+  bool found = false;
+
   foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
  if (regions_overlap(scan_inst->dst, scan_inst->regs_written * 
REG_SIZE,
  inst->src[0], inst->regs_read(0) * REG_SIZE)) {
@@ -2811,7 +2813,7 @@ fs_visitor::compute_to_mrf()
/* If this one instruction didn't populate all the
 * channels, bail.  We might be able to rewrite everything
 * that writes that reg, but it would require smarter
-* tracking to delay the rewriting until complete success.
+* tracking.
 */
if (scan_inst->is_partial_write())
   break;
@@ -2838,15 +2840,9 @@ fs_visitor::compute_to_mrf()
   }
}
 
-   if (scan_inst->dst.reg_offset == inst->src[0].reg_offset) {
-  /* Found the creator of our MRF's source value. */
-  scan_inst->dst.file = MRF;
-   scan_inst->dst.nr = inst->dst.nr;
-   scan_inst->dst.reg_offset = 0;
-  scan_inst->saturate |= inst->saturate;
-  inst->remove(block);
-  progress = true;
-   }
+   if (scan_inst->dst.reg_offset == inst->src[0].reg_offset)
+   found = true;
+
break;
 }
 
@@ -2889,6 +2885,25 @@ fs_visitor::compute_to_mrf()
 break;
  }
   }
+
+  if (!found)
+ continue;
+
+  /* Found all generating instructions of our MRF's source value.
+   */
+  foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
+ if (regions_overlap(scan_inst->dst, scan_inst->regs_written * 
REG_SIZE,
+ inst->src[0], inst->regs_read(0) * REG_SIZE)) {
+scan_inst->dst.file = MRF;
+scan_inst->dst.nr = inst->dst.nr;
+scan_inst->dst.reg_offset = 0;
+scan_inst->saturate |= inst->saturate;
+break;
+ }
+  }
+
+  inst->remove(block);
+  progress = true;
}
 
if (progress)

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Mesa (master): i965/fs: Fix compute_to_mrf() to coalesce VGRFs initialized by multiple single-GRF writes.

[Francisco Jerez]

Module: Mesa
Branch: master
Commit: 4fe4f6e8a776acc60633809693e4135f5c894aa3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4fe4f6e8a776acc60633809693e4135f5c894aa3

Author: Francisco Jerez 
Date:   Fri May 27 16:03:34 2016 -0700

i965/fs: Fix compute_to_mrf() to coalesce VGRFs initialized by multiple 
single-GRF writes.

Which requires using a bitset instead of a boolean flag to keep track
of the GRFs we've seen a generating instruction for already.  The
search loop continues until all instructions initializing the value of
the source VGRF have been found, or it is determined that coalescing
is not possible.

Fixes a few piglit test cases on Gen4-6 which were regressed by
6956015aa514f2d06d0e4b33bfe6bca83142fbf0 due to the different (yet
perfectly valid) ordering in which copy instructions are emitted now
by the simd lowering pass, which had the side effect of causing this
optimization pass to start corrupting the program in cases where a
VGRF-to-MRF copy instruction would be eliminated but only the last
instruction writing to the source VGRF region would be rewritten to
point to the target MRF.

Cc: "12.0" 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_fs.cpp | 46 
 1 file changed, 36 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index c04d642..5d5b98a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2767,6 +2767,20 @@ fs_visitor::opt_redundant_discard_jumps()
return progress;
 }
 
+/**
+ * Compute a bitmask with GRF granularity with a bit set for each GRF starting
+ * from \p r which overlaps the region starting at \p r and spanning \p n GRF
+ * units.
+ */
+static inline unsigned
+mask_relative_to(const fs_reg , const fs_reg , unsigned n)
+{
+   const int rel_offset = (reg_offset(s) - reg_offset(r)) / REG_SIZE;
+   assert(reg_space(r) == reg_space(s) &&
+  rel_offset >= 0 && rel_offset < int(8 * sizeof(unsigned)));
+   return ((1 << n) - 1) << rel_offset;
+}
+
 bool
 fs_visitor::compute_to_mrf()
 {
@@ -2798,10 +2812,12 @@ fs_visitor::compute_to_mrf()
   if (this->virtual_grf_end[inst->src[0].nr] > ip)
 continue;
 
-  /* Found a move of a GRF to a MRF.  Let's see if we can go
-   * rewrite the thing that made this GRF to write into the MRF.
+  /* Found a move of a GRF to a MRF.  Let's see if we can go rewrite the
+   * things that computed the value of all GRFs of the source region.  The
+   * regs_left bitset keeps track of the registers we haven't yet found a
+   * generating instruction for.
*/
-  bool found = false;
+  unsigned regs_left = (1 << inst->regs_read(0)) - 1;
 
   foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
  if (regions_overlap(scan_inst->dst, scan_inst->regs_written * 
REG_SIZE,
@@ -2840,10 +2856,11 @@ fs_visitor::compute_to_mrf()
   }
}
 
-   if (scan_inst->dst.reg_offset == inst->src[0].reg_offset)
-   found = true;
-
-   break;
+/* Clear the bits for any registers this instruction overwrites. */
+regs_left &= ~mask_relative_to(
+   inst->src[0], scan_inst->dst, scan_inst->regs_written);
+if (!regs_left)
+   break;
 }
 
 /* We don't handle control flow here.  Most computation of
@@ -2886,14 +2903,21 @@ fs_visitor::compute_to_mrf()
  }
   }
 
-  if (!found)
+  if (regs_left)
  continue;
 
-  /* Found all generating instructions of our MRF's source value.
+  /* Found all generating instructions of our MRF's source value, so it
+   * should be safe to rewrite them to point to the MRF directly.
*/
+  regs_left = (1 << inst->regs_read(0)) - 1;
+
   foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
  if (regions_overlap(scan_inst->dst, scan_inst->regs_written * 
REG_SIZE,
  inst->src[0], inst->regs_read(0) * REG_SIZE)) {
+/* Clear the bits for any registers this instruction overwrites. */
+regs_left &= ~mask_relative_to(
+   inst->src[0], scan_inst->dst, scan_inst->regs_written);
+
 const unsigned rel_offset = (reg_offset(scan_inst->dst) -
  reg_offset(inst->src[0])) / REG_SIZE;
 
@@ -2920,10 +2944,12 @@ fs_visitor::compute_to_mrf()
 scan_inst->dst.file = MRF;
 scan_inst->dst.reg_offset = 0;
 scan_inst->saturate |= inst->saturate;
-break;
+if (!regs_left)
+   break;
  }
   }
 
+  assert(!regs_left);
   inst->remove(block);
   progress = true;
}

___

Mesa (master): i965/fs: Teach regions_overlap() about COMPR4 MRF regions.

[Francisco Jerez]

Module: Mesa
Branch: master
Commit: 88f380a2ddbdeda6e83725403b12ee0070f1f0f3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=88f380a2ddbdeda6e83725403b12ee0070f1f0f3

Author: Francisco Jerez 
Date:   Thu May 26 23:53:31 2016 -0700

i965/fs: Teach regions_overlap() about COMPR4 MRF regions.

Cc: "12.0" 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_ir_fs.h | 20 +---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h 
b/src/mesa/drivers/dri/i965/brw_ir_fs.h
index 7b1ec68..f214483 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h
@@ -204,9 +204,23 @@ reg_offset(const fs_reg )
 static inline bool
 regions_overlap(const fs_reg , unsigned dr, const fs_reg , unsigned ds)
 {
-   return reg_space(r) == reg_space(s) &&
-  !(reg_offset(r) + dr <= reg_offset(s) ||
-reg_offset(s) + ds <= reg_offset(r));
+   if (r.file == MRF && (r.nr & BRW_MRF_COMPR4)) {
+  fs_reg t = r;
+  t.nr &= ~BRW_MRF_COMPR4;
+  /* COMPR4 regions are translated by the hardware during decompression
+   * into two separate half-regions 4 MRFs apart from each other.
+   */
+  return regions_overlap(t, dr / 2, s, ds) ||
+ regions_overlap(byte_offset(t, 4 * REG_SIZE), dr / 2, s, ds);
+
+   } else if (s.file == MRF && (s.nr & BRW_MRF_COMPR4)) {
+  return regions_overlap(s, ds, r, dr);
+
+   } else {
+  return reg_space(r) == reg_space(s) &&
+ !(reg_offset(r) + dr <= reg_offset(s) ||
+   reg_offset(s) + ds <= reg_offset(r));
+   }
 }
 
 /**

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Mesa (master): i965/fs: Allow scalar source regions on SNB math instructions.

[Francisco Jerez]

Module: Mesa
Branch: master
Commit: c1107cec44ab030c7fcc97c67baa12df1cc9d7b5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c1107cec44ab030c7fcc97c67baa12df1cc9d7b5

Author: Francisco Jerez 
Date:   Fri May 27 23:29:14 2016 -0700

i965/fs: Allow scalar source regions on SNB math instructions.

I haven't found any evidence that this isn't supported by the
hardware, in fact according to the SNB hardware spec:

 "The supported regioning modes for math instructions are align16,
  align1 with the following restrictions:
   - Scalar source is supported.
  [...]
   - Source and destination offset must be the same, except the case of
 scalar source."

Cc: "12.0" 
Reviewed-by: Jason Ekstrand 
Reviewed-by: Matt Turner 

---

 src/mesa/drivers/dri/i965/brw_eu_emit.c   |  6 --
 src/mesa/drivers/dri/i965/brw_fs_builder.h| 10 ++
 src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp |  9 ++---
 3 files changed, 8 insertions(+), 17 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 1c2ccb4..2538f0d 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -2000,8 +2000,10 @@ void gen6_math(struct brw_codegen *p,
 
assert(dest.hstride == BRW_HORIZONTAL_STRIDE_1);
if (devinfo->gen == 6) {
-  assert(src0.hstride == BRW_HORIZONTAL_STRIDE_1);
-  assert(src1.hstride == BRW_HORIZONTAL_STRIDE_1);
+  assert(has_scalar_region(src0) ||
+ src0.hstride == BRW_HORIZONTAL_STRIDE_1);
+  assert(has_scalar_region(src1) ||
+ src1.hstride == BRW_HORIZONTAL_STRIDE_1);
}
 
if (function == BRW_MATH_FUNCTION_INT_DIV_QUOTIENT ||
diff --git a/src/mesa/drivers/dri/i965/brw_fs_builder.h 
b/src/mesa/drivers/dri/i965/brw_fs_builder.h
index f22903e..aef35f3 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_builder.h
+++ b/src/mesa/drivers/dri/i965/brw_fs_builder.h
@@ -621,20 +621,14 @@ namespace brw {
   src_reg
   fix_math_operand(const src_reg ) const
   {
- /* Can't do hstride == 0 args on gen6 math, so expand it out. We
-  * might be able to do better by doing execsize = 1 math and then
-  * expanding that result out, but we would need to be careful with
-  * masking.
-  *
-  * Gen6 hardware ignores source modifiers (negate and abs) on math
+ /* Gen6 hardware ignores source modifiers (negate and abs) on math
   * instructions, so we also move to a temp to set those up.
   *
   * Gen7 relaxes most of the above restrictions, but still can't use 
IMM
   * operands to math
   */
  if ((shader->devinfo->gen == 6 &&
-  (src.file == IMM || src.file == UNIFORM ||
-   src.abs || src.negate)) ||
+  (src.file == IMM || src.abs || src.negate)) ||
  (shader->devinfo->gen == 7 && src.file == IMM)) {
 const dst_reg tmp = vgrf(src.type);
 MOV(tmp, src);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
index d88d62b..2a83eb9 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
@@ -578,14 +578,9 @@ fs_visitor::try_constant_propagate(fs_inst *inst, 
acp_entry *entry)
 break;
  /* fallthrough */
   case SHADER_OPCODE_POW:
- /* Allow constant propagation into src1 (except on Gen 6), and let
-  * constant combining promote the constant on Gen < 8.
-  *
-  * While Gen 6 MATH can take a scalar source, its source and
-  * destination offsets must be equal and we cannot ensure that.
+ /* Allow constant propagation into src1, and let constant combining
+  * promote the constant on Gen < 8.
   */
- if (devinfo->gen == 6)
-break;
  /* fallthrough */
   case BRW_OPCODE_BFI1:
   case BRW_OPCODE_ASR:

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Mesa (master): i965/fs: Simplify and improve accuracy of compute_to_mrf() by using regions_overlap().

[Francisco Jerez]

Module: Mesa
Branch: master
Commit: bb61e24787952a4796a687a86200a05cf83af7e9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb61e24787952a4796a687a86200a05cf83af7e9

Author: Francisco Jerez 
Date:   Fri May 27 12:50:28 2016 -0700

i965/fs: Simplify and improve accuracy of compute_to_mrf() by using 
regions_overlap().

Compute-to-mrf was being rather heavy-handed about checking whether
instruction source or destination regions interfere with the copy
instruction, which could conceivably lead to program miscompilation.
Fix it by using regions_overlap() instead of the open-coded and
dubiously correct overlap checks.

Cc: "12.0" 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_fs.cpp | 60 
 1 file changed, 13 insertions(+), 47 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index d04eebc..172182a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2792,19 +2792,6 @@ fs_visitor::compute_to_mrf()
   inst->src[0].subreg_offset)
 continue;
 
-  /* Work out which hardware MRF registers are written by this
-   * instruction.
-   */
-  int mrf_low = inst->dst.nr & ~BRW_MRF_COMPR4;
-  int mrf_high;
-  if (inst->dst.nr & BRW_MRF_COMPR4) {
-mrf_high = mrf_low + 4;
-  } else if (inst->exec_size == 16) {
-mrf_high = mrf_low + 1;
-  } else {
-mrf_high = mrf_low;
-  }
-
   /* Can't compute-to-MRF this GRF if someone else was going to
* read it later.
*/
@@ -2815,8 +2802,8 @@ fs_visitor::compute_to_mrf()
* rewrite the thing that made this GRF to write into the MRF.
*/
   foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) {
-if (scan_inst->dst.file == VGRF &&
-scan_inst->dst.nr == inst->src[0].nr) {
+ if (regions_overlap(scan_inst->dst, scan_inst->regs_written * 
REG_SIZE,
+ inst->src[0], inst->regs_read(0) * REG_SIZE)) {
/* Found the last thing to write our reg we want to turn
 * into a compute-to-MRF.
 */
@@ -2872,53 +2859,32 @@ fs_visitor::compute_to_mrf()
  */
 bool interfered = false;
 for (int i = 0; i < scan_inst->sources; i++) {
-   if (scan_inst->src[i].file == VGRF &&
-scan_inst->src[i].nr == inst->src[0].nr &&
-   scan_inst->src[i].reg_offset == inst->src[0].reg_offset) {
+if (regions_overlap(scan_inst->src[i], scan_inst->regs_read(i) * 
REG_SIZE,
+inst->src[0], inst->regs_read(0) * REG_SIZE)) {
   interfered = true;
}
 }
 if (interfered)
break;
 
-if (scan_inst->dst.file == MRF) {
+ if (regions_overlap(scan_inst->dst, scan_inst->regs_written * 
REG_SIZE,
+ inst->dst, inst->regs_written * REG_SIZE)) {
/* If somebody else writes our MRF here, we can't
 * compute-to-MRF before that.
 */
-int scan_mrf_low = scan_inst->dst.nr & ~BRW_MRF_COMPR4;
-   int scan_mrf_high;
-
-if (scan_inst->dst.nr & BRW_MRF_COMPR4) {
-  scan_mrf_high = scan_mrf_low + 4;
-   } else if (scan_inst->exec_size == 16) {
-  scan_mrf_high = scan_mrf_low + 1;
-   } else {
-  scan_mrf_high = scan_mrf_low;
-   }
-
-   if (mrf_low == scan_mrf_low ||
-   mrf_low == scan_mrf_high ||
-   mrf_high == scan_mrf_low ||
-   mrf_high == scan_mrf_high) {
-  break;
-   }
-}
+break;
+ }
 
-if (scan_inst->mlen > 0 && scan_inst->base_mrf != -1) {
+ if (scan_inst->mlen > 0 && scan_inst->base_mrf != -1 &&
+ regions_overlap(fs_reg(MRF, scan_inst->base_mrf), scan_inst->mlen 
* REG_SIZE,
+ inst->dst, inst->regs_written * REG_SIZE)) {
/* Found a SEND instruction, which means that there are
 * live values in MRFs from base_mrf to base_mrf +
 * scan_inst->mlen - 1.  Don't go pushing our MRF write up
 * above it.
 */
-   if (mrf_low >= scan_inst->base_mrf &&
-   mrf_low < scan_inst->base_mrf + scan_inst->mlen) {
-  break;
-   }
-   if (mrf_high >= scan_inst->base_mrf &&
-   mrf_high < scan_inst->base_mrf + scan_inst->mlen) {
-  break;
-   }
-}
+break;
+ }
   }
}
 

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Mesa (master): genxml: require future imports for python2 compatibility.

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: a45a25418bd6310122d52f12a4640e8493246439
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a45a25418bd6310122d52f12a4640e8493246439

Author: Dylan Baker 
Date:   Tue May 31 11:36:26 2016 -0700

genxml: require future imports for python2 compatibility.

Signed-off-by: Dylan Baker 
Reviewed-by: Jason Ekstrand 
cc: 12.0 

---

 src/intel/genxml/gen_pack_header.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/intel/genxml/gen_pack_header.py 
b/src/intel/genxml/gen_pack_header.py
index 8cdb3e3..876d609 100644
--- a/src/intel/genxml/gen_pack_header.py
+++ b/src/intel/genxml/gen_pack_header.py
@@ -1,6 +1,9 @@
 #!/usr/bin/env python3
 #encoding=utf-8
 
+from __future__ import (
+absolute_import, division, print_function, unicode_literals
+)
 import xml.parsers.expat
 import re
 import sys

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Mesa (master): genxml: Make classes descendants of object

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: de2e9da2e9b0bfeca535f318c20df93b3a0fd08b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=de2e9da2e9b0bfeca535f318c20df93b3a0fd08b

Author: Dylan Baker 
Date:   Tue May 31 11:31:18 2016 -0700

genxml: Make classes descendants of object

This is the default in python3, but in python2 you get old style
classes. No one likes old-style classes.

Signed-off-by: Dylan Baker 
Reviewed-by: Jason Ekstrand 
cc: 12.0 

---

 src/intel/genxml/gen_pack_header.py | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/intel/genxml/gen_pack_header.py 
b/src/intel/genxml/gen_pack_header.py
index 2920ec9..2a7e265 100644
--- a/src/intel/genxml/gen_pack_header.py
+++ b/src/intel/genxml/gen_pack_header.py
@@ -210,7 +210,7 @@ def num_from_str(num_str):
 assert(not num_str.startswith('0') and 'octals numbers not allowed')
 return int(num_str)
 
-class Field:
+class Field(object):
 ufixed_pattern = re.compile("u(\d+)\.(\d+)")
 sfixed_pattern = re.compile("s(\d+)\.(\d+)")
 
@@ -279,7 +279,7 @@ class Field:
 for value in self.values:
 print("#define %-40s %d" % (prefix + value.name, value.value))
 
-class Group:
+class Group(object):
 def __init__(self, parser, parent, start, count, size):
 self.parser = parser
 self.parent = parent
@@ -467,12 +467,12 @@ class Group:
 print("   dw[%d] = %s;" % (index, v))
 print("   dw[%d] = %s >> 32;" % (index + 1, v))
 
-class Value:
+class Value(object):
 def __init__(self, attrs):
 self.name = safe_name(attrs["name"])
 self.value = int(attrs["value"])
 
-class Parser:
+class Parser(object):
 def __init__(self):
 self.parser = xml.parsers.expat.ParserCreate()
 self.parser.StartElementHandler = self.start_element

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Mesa (master): genxml: change chbang to python 2

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: ab31817fedff4634c7daeb3eb04fac49d4625c54
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ab31817fedff4634c7daeb3eb04fac49d4625c54

Author: Dylan Baker 
Date:   Tue May 31 11:40:22 2016 -0700

genxml: change chbang to python 2

Signed-off-by: Dylan Baker 
Reviewed-by: Jason Ekstrand 
cc: 12.0 

---

 src/intel/genxml/gen_pack_header.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/genxml/gen_pack_header.py 
b/src/intel/genxml/gen_pack_header.py
index 9945272..01f20ad 100644
--- a/src/intel/genxml/gen_pack_header.py
+++ b/src/intel/genxml/gen_pack_header.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python3
+#!/usr/bin/env python2
 #encoding=utf-8
 
 from __future__ import (

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Mesa (master): genxml: mark re strings as raw

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: e5681e4d7056dbe561127dedf76fb2cd9d16fc00
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5681e4d7056dbe561127dedf76fb2cd9d16fc00

Author: Dylan Baker 
Date:   Tue May 31 11:33:19 2016 -0700

genxml: mark re strings as raw

This is a correctness issue.

Signed-off-by: Dylan Baker 
Reviewed-by: Jason Ekstrand 
cc: 12.0 

---

 src/intel/genxml/gen_pack_header.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/genxml/gen_pack_header.py 
b/src/intel/genxml/gen_pack_header.py
index 2a7e265..8cdb3e3 100644
--- a/src/intel/genxml/gen_pack_header.py
+++ b/src/intel/genxml/gen_pack_header.py
@@ -211,8 +211,8 @@ def num_from_str(num_str):
 return int(num_str)
 
 class Field(object):
-ufixed_pattern = re.compile("u(\d+)\.(\d+)")
-sfixed_pattern = re.compile("s(\d+)\.(\d+)")
+ufixed_pattern = re.compile(r"u(\d+)\.(\d+)")
+sfixed_pattern = re.compile(r"s(\d+)\.(\d+)")
 
 def __init__(self, parser, attrs):
 self.parser = parser

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Mesa (master): genxml: use the isalpha method rather than str.isalpha.

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 12c1a01c720f4e9fa16345ee403ac061ed40601e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=12c1a01c720f4e9fa16345ee403ac061ed40601e

Author: Dylan Baker 
Date:   Tue May 31 13:33:50 2016 -0700

genxml: use the isalpha method rather than str.isalpha.

This fixes gen_pack_header to work on python 2, where name[0] is unicode
not str.

Signed-off-by: Dylan Bake 
Reviewed-by: Jason Ekstrand 
cc: 12.0 

---

 src/intel/genxml/gen_pack_header.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/genxml/gen_pack_header.py 
b/src/intel/genxml/gen_pack_header.py
index 876d609..9945272 100644
--- a/src/intel/genxml/gen_pack_header.py
+++ b/src/intel/genxml/gen_pack_header.py
@@ -201,7 +201,7 @@ def to_alphanum(name):
 
 def safe_name(name):
 name = to_alphanum(name)
-if not str.isalpha(name[0]):
+if not name[0].isalpha():
 name = '_' + name
 
 return name

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Mesa (master): Don't use python 3

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 604010a7edbe03ff65720cab8dddba1d0ca1571b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=604010a7edbe03ff65720cab8dddba1d0ca1571b

Author: Dylan Baker 
Date:   Tue May 31 13:31:44 2016 -0700

Don't use python 3

Now there are not files that require python 3, so for now just remove
the python 3 dependency and use python 2. I think the right plan is to
just get all of the python ready for python 3, and then use whatever
python is available.

Signed-off-by: Dylan Baker 
Reviewed-by: Jason Ekstrand 
cc: 12.0 

---

 configure.ac | 8 
 src/intel/genxml/Makefile.am | 4 ++--
 2 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/configure.ac b/configure.ac
index 173d6df..33d1fef 100644
--- a/configure.ac
+++ b/configure.ac
@@ -99,7 +99,6 @@ AM_PROG_CC_C_O
 AM_PROG_AS
 AX_CHECK_GNU_MAKE
 AC_CHECK_PROGS([PYTHON2], [python2.7 python2 python])
-AC_CHECK_PROGS([PYTHON3], [python3.5 python3.4 python3])
 AC_PROG_SED
 AC_PROG_MKDIR_P
 
@@ -142,12 +141,6 @@ else
 fi
 fi
 
-if test -z "$PYTHON3"; then
-if test ! -f "$srcdir/src/intel/genxml/gen9_pack.h"; then
-AC_MSG_ERROR([Python3 not found - unable to generate sources])
-fi
-fi
-
 AC_PROG_INSTALL
 
 dnl We need a POSIX shell for parts of the build. Assume we have one
@@ -2874,7 +2867,6 @@ if test "x$MESA_LLVM" = x1; then
 echo ""
 fi
 echo "PYTHON2: $PYTHON2"
-echo "PYTHON3: $PYTHON3"
 
 echo ""
 echo "Run '${MAKE-make}' to build Mesa"
diff --git a/src/intel/genxml/Makefile.am b/src/intel/genxml/Makefile.am
index c393ebe..d6c1c5b 100644
--- a/src/intel/genxml/Makefile.am
+++ b/src/intel/genxml/Makefile.am
@@ -23,14 +23,14 @@ include Makefile.sources
 
 BUILT_SOURCES = $(GENXML_GENERATED_FILES)
 
-PYTHON3_GEN = $(AM_V_GEN)$(PYTHON3) $(PYTHON_FLAGS)
+PYTHON_GEN = $(AM_V_GEN)$(PYTHON2) $(PYTHON_FLAGS)
 
 SUFFIXES = _pack.h .xml
 
 $(BUILT_SOURCES): gen_pack_header.py
 
 .xml_pack.h:
-   $(PYTHON3_GEN) $(srcdir)/gen_pack_header.py $< > $@
+   $(PYTHON_GEN) $(srcdir)/gen_pack_header.py $< > $@
 
 CLEANFILES = $(BUILT_SOURCES)
 

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Mesa (master): radeonsi: Decompress DCC textures in a render feedback loop.

[Bas Nieuwenhuizen]

Module: Mesa
Branch: master
Commit: 35818129a676502415a5f502ccd2759646066921
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=35818129a676502415a5f502ccd2759646066921

Author: Bas Nieuwenhuizen 
Date:   Tue May 31 14:11:49 2016 +0200

radeonsi: Decompress DCC textures in a render feedback loop.

By using a counter to quickly reject textures that are not
bound to a framebuffer, the performance impact when binding
sampler_views/images is not too large.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_blit.c| 100 ++
 src/gallium/drivers/radeonsi/si_descriptors.c |   8 +++
 src/gallium/drivers/radeonsi/si_pipe.h|   3 +
 src/gallium/drivers/radeonsi/si_state.c   |   2 +
 4 files changed, 113 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 6f3199c..3748a59 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -412,6 +412,104 @@ si_decompress_image_color_textures(struct si_context 
*sctx,
}
 }
 
+static void si_check_render_feedback_textures(struct si_context *sctx,
+  struct si_textures_info 
*textures)
+{
+   uint32_t mask = textures->views.desc.enabled_mask;
+
+   while (mask) {
+   const struct pipe_sampler_view *view;
+   struct r600_texture *tex;
+   bool render_feedback = false;
+
+   unsigned i = u_bit_scan();
+
+   view = textures->views.views[i];
+   if(view->texture->target == PIPE_BUFFER)
+   continue;
+
+   tex = (struct r600_texture *)view->texture;
+   if (!tex->dcc_offset)
+   continue;
+
+   for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) 
{
+   struct r600_surface * surf;
+
+   if (!sctx->framebuffer.state.cbufs[j])
+   continue;
+
+   surf = (struct 
r600_surface*)sctx->framebuffer.state.cbufs[j];
+
+   if (tex == (struct r600_texture*)surf->base.texture &&
+   surf->base.u.tex.level >= view->u.tex.first_level &&
+   surf->base.u.tex.level <= view->u.tex.last_level &&
+   surf->base.u.tex.first_layer <= 
view->u.tex.last_layer &&
+   surf->base.u.tex.last_layer >= 
view->u.tex.first_layer)
+   render_feedback = true;
+   }
+
+   if (render_feedback) {
+   struct si_screen *screen = sctx->screen;
+   r600_texture_disable_dcc(>b, tex);
+   }
+   }
+}
+
+static void si_check_render_feedback_images(struct si_context *sctx,
+struct si_images_info *images)
+{
+   uint32_t mask = images->desc.enabled_mask;
+
+   while (mask) {
+   const struct pipe_image_view *view;
+   struct r600_texture *tex;
+   bool render_feedback = false;
+
+   unsigned i = u_bit_scan();
+
+   view = >views[i];
+   if (view->resource->target == PIPE_BUFFER)
+   continue;
+
+   tex = (struct r600_texture *)view->resource;
+   if (!tex->dcc_offset)
+   continue;
+
+   for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) 
{
+   struct r600_surface * surf;
+
+   if (!sctx->framebuffer.state.cbufs[j])
+   continue;
+
+   surf = (struct 
r600_surface*)sctx->framebuffer.state.cbufs[j];
+
+   if (tex == (struct r600_texture*)surf->base.texture &&
+   surf->base.u.tex.level == view->u.tex.level &&
+   surf->base.u.tex.first_layer <= 
view->u.tex.last_layer &&
+   surf->base.u.tex.last_layer >= 
view->u.tex.first_layer)
+   render_feedback = true;
+   }
+
+   if (render_feedback) {
+   struct si_screen *screen = sctx->screen;
+   r600_texture_disable_dcc(>b, tex);
+   }
+   }
+}
+
+static void si_check_render_feedback(struct si_context *sctx)
+{
+
+   if (!sctx->need_check_render_feedback)
+   return;
+
+   for (int i = 0; i < SI_NUM_SHADERS; ++i) {
+   si_check_render_feedback_images(sctx, >images[i]);
+   si_check_render_feedback_textures(sctx, >samplers[i]);
+   }
+   sctx->need_check_render_feedback = false;
+}
+
 static void si_decompress_textures(struct si_context *sctx, int 

Mesa (master): radeonsi: Add counter to check if a texture is bound to a framebuffer.

[Bas Nieuwenhuizen]

Module: Mesa
Branch: master
Commit: cbe3421f05b1a99df6df0fc93d7ce7d5071af02f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cbe3421f05b1a99df6df0fc93d7ce7d5071af02f

Author: Bas Nieuwenhuizen 
Date:   Tue May 31 13:44:03 2016 +0200

radeonsi: Add counter to check if a texture is bound to a framebuffer.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeon/r600_pipe_common.h |  5 +
 src/gallium/drivers/radeonsi/si_pipe.c|  2 ++
 src/gallium/drivers/radeonsi/si_state.c   | 18 ++
 src/gallium/drivers/radeonsi/si_state.h   |  1 +
 4 files changed, 26 insertions(+)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 3e54534..084e3fb 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -260,6 +260,11 @@ struct r600_texture {
uint8_t stencil_clear_value;
 
boolnon_disp_tiling; /* R600-Cayman only */
+
+   /* Counter that should be non-zero if the texture is bound to a
+* framebuffer. Implemented in radeonsi only.
+*/
+   uint32_tframebuffers_bound;
 };
 
 struct r600_surface {
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 88f4f20..0987baf 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -40,6 +40,8 @@ static void si_destroy_context(struct pipe_context *context)
struct si_context *sctx = (struct si_context *)context;
int i;
 
+   si_dec_framebuffer_counters(>framebuffer.state);
+
si_release_all_descriptors(sctx);
 
if (sctx->ce_suballocator)
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index ab321ef..ed62710 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2268,6 +2268,21 @@ static void si_init_depth_surface(struct si_context 
*sctx,
surf->depth_initialized = true;
 }
 
+void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
+{
+   for (int i = 0; i < state->nr_cbufs; ++i) {
+   struct r600_surface *surf = NULL;
+   struct r600_texture *rtex;
+
+   if (!state->cbufs[i])
+   continue;
+   surf = (struct r600_surface*)state->cbufs[i];
+   rtex = (struct r600_texture*)surf->base.texture;
+
+   p_atomic_dec(>framebuffers_bound);
+   }
+}
+
 static void si_set_framebuffer_state(struct pipe_context *ctx,
 const struct pipe_framebuffer_state *state)
 {
@@ -2298,6 +2313,7 @@ static void si_set_framebuffer_state(struct pipe_context 
*ctx,
(1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) 
- 1;
sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != 
state->zsbuf;
 
+   si_dec_framebuffer_counters(>framebuffer.state);
util_copy_framebuffer_state(>framebuffer.state, state);
 
sctx->framebuffer.spi_shader_col_format = 0;
@@ -2342,6 +2358,8 @@ static void si_set_framebuffer_state(struct pipe_context 
*ctx,
sctx->framebuffer.compressed_cb_mask |= 1 << i;
}
r600_context_add_resource_size(ctx, surf->base.texture);
+
+   p_atomic_inc(>framebuffers_bound);
}
/* Set the second SPI format for possible dual-src blending. */
if (i == 1 && surf) {
diff --git a/src/gallium/drivers/radeonsi/si_state.h 
b/src/gallium/drivers/radeonsi/si_state.h
index a3589d4..01b73f6 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -308,6 +308,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
  const struct pipe_sampler_view *state,
  unsigned width0, unsigned height0,
  unsigned force_level);
+void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state);
 
 /* si_state_shader.c */
 bool si_update_shaders(struct si_context *sctx);

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Mesa (master): vc4: Fix compiler warnings in fail_instr path of QIR validate pass

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 8cb74dd4e6504f77b473aacd783218727e252909
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8cb74dd4e6504f77b473aacd783218727e252909

Author: Rhys Kidd 
Date:   Thu May 19 23:17:20 2016 -0400

vc4: Fix compiler warnings in fail_instr path of QIR validate pass

Introduced in 8e2d0843c02daf5280184f179ae8ed440ac90d7f.

Signed-off-by: Rhys Kidd 
Reviewed-by: Eric Anholt 

---

 src/gallium/drivers/vc4/vc4_qir_validate.c | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/gallium/drivers/vc4/vc4_qir_validate.c 
b/src/gallium/drivers/vc4/vc4_qir_validate.c
index af2e3ba..da6457c 100644
--- a/src/gallium/drivers/vc4/vc4_qir_validate.c
+++ b/src/gallium/drivers/vc4/vc4_qir_validate.c
@@ -25,10 +25,10 @@
 #include "vc4_qpu.h"
 
 static void
-fail_instr(struct qinst *inst, const char *msg)
+fail_instr(struct vc4_compile *c, struct qinst *inst, const char *msg)
 {
 fprintf(stderr, "qir_validate: %s: ", msg);
-qir_dump_inst(stderr, inst);
+qir_dump_inst(c, inst);
 fprintf(stderr, "\n");
 abort();
 }
@@ -50,18 +50,18 @@ void qir_validate(struct vc4_compile *c)
 struct qinst *def = c->defs[i];
 
 if (def && def->cond != QPU_COND_ALWAYS)
-fail_instr(def, "SSA def with condition");
+fail_instr(c, def, "SSA def with condition");
 }
 
 list_for_each_entry(struct qinst, inst, >instructions, link) {
 switch (inst->dst.file) {
 case QFILE_TEMP:
 if (inst->dst.index >= c->num_temps)
-fail_instr(inst, "bad temp index");
+fail_instr(c, inst, "bad temp index");
 
 if (c->defs[inst->dst.index] &&
 already_assigned[inst->dst.index]) {
-fail_instr(inst, "Re-assignment of SSA value");
+fail_instr(c, inst, "Re-assignment of SSA 
value");
 }
 already_assigned[inst->dst.index] = true;
 break;
@@ -81,7 +81,7 @@ void qir_validate(struct vc4_compile *c)
 case QFILE_FRAG_REV_FLAG:
 case QFILE_SMALL_IMM:
 case QFILE_LOAD_IMM:
-fail_instr(inst, "Bad dest file");
+fail_instr(c, inst, "Bad dest file");
 break;
 }
 
@@ -91,7 +91,7 @@ void qir_validate(struct vc4_compile *c)
 switch (src.file) {
 case QFILE_TEMP:
 if (src.index >= c->num_temps)
-fail_instr(inst, "bad temp index");
+fail_instr(c, inst, "bad temp index");
 break;
 
 case QFILE_VARY:
@@ -102,14 +102,14 @@ void qir_validate(struct vc4_compile *c)
 
 case QFILE_SMALL_IMM:
 if (qpu_encode_small_immediate(src.index) == 
~0)
-fail_instr(inst, "bad small 
immediate");
+fail_instr(c, inst, "bad small 
immediate");
 break;
 
 case QFILE_FRAG_X:
 case QFILE_FRAG_Y:
 case QFILE_FRAG_REV_FLAG:
 if (c->stage != QSTAGE_FRAG)
-fail_instr(inst, "frag access in 
VS/CS");
+fail_instr(c, inst, "frag access in 
VS/CS");
 break;
 
 case QFILE_NULL:
@@ -117,7 +117,7 @@ void qir_validate(struct vc4_compile *c)
 case QFILE_TLB_COLOR_WRITE_MS:
 case QFILE_TLB_Z_WRITE:
 case QFILE_TLB_STENCIL_SETUP:
-fail_instr(inst, "Bad src file");
+fail_instr(c, inst, "Bad src file");
 break;
 }
 }

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Mesa (master): anv: let anv_entrypoints_gen.py generate proper Wayland/ Xcb guards

[Emil Velikov]

Module: Mesa
Branch: master
Commit: b8e1f59d62bbe9b071c1012fd26a84928f3b0564
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b8e1f59d62bbe9b071c1012fd26a84928f3b0564

Author: Emil Velikov 
Date:   Tue May 31 14:55:04 2016 +0100

anv: let anv_entrypoints_gen.py generate proper Wayland/Xcb guards

The generated sources should follow the example set by the vulkan
headers and our non-generated code. Namely: the code for all supported
platforms should be available, each one guarded by its respective
VK_USE_PLATFORM_*_KHR macro.

v2: Reword commit message.

Cc: Mark Janes 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96285
Signed-off-by: Emil Velikov 
Reviewed-by: Jason Ekstrand  (v1 over IRC)

---

 src/intel/vulkan/anv_entrypoints_gen.py | 28 
 1 file changed, 28 insertions(+)

diff --git a/src/intel/vulkan/anv_entrypoints_gen.py 
b/src/intel/vulkan/anv_entrypoints_gen.py
index cedecfe..7a47372 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -51,6 +51,20 @@ def hash(name):
 
 return h
 
+def print_guard_start(name):
+if "Wayland" in name:
+print "#ifdef VK_USE_PLATFORM_WAYLAND_KHR"
+if "Xcb" in name:
+print "#ifdef VK_USE_PLATFORM_XCB_KHR"
+return
+
+def print_guard_end(name):
+if "Wayland" in name:
+print "#endif // VK_USE_PLATFORM_WAYLAND_KHR"
+if "Xcb" in name:
+print "#endif // VK_USE_PLATFORM_XCB_KHR"
+return
+
 opt_header = False
 opt_code = False
 
@@ -86,7 +100,9 @@ if opt_header:
 print "  struct {"
 
 for type, name, args, num, h in entrypoints:
+print_guard_start(name)
 print " %s (*%s)%s;" % (type, name, args)
+print_guard_end(name)
 print "  };\n"
 print "   };\n"
 print "};\n"
@@ -94,12 +110,14 @@ if opt_header:
 print "void anv_set_dispatch_devinfo(const struct brw_device_info 
*info);\n"
 
 for type, name, args, num, h in entrypoints:
+print_guard_start(name)
 print "%s anv_%s%s;" % (type, name, args)
 print "%s gen7_%s%s;" % (type, name, args)
 print "%s gen75_%s%s;" % (type, name, args)
 print "%s gen8_%s%s;" % (type, name, args)
 print "%s gen9_%s%s;" % (type, name, args)
 print "%s anv_validate_%s%s;" % (type, name, args)
+print_guard_end(name)
 exit()
 
 
@@ -146,9 +164,11 @@ static const char strings[] ="""
 offsets = []
 i = 0;
 for type, name, args, num, h in entrypoints:
+print_guard_start(name)
 print "   \"vk%s\\0\"" % name
 offsets.append(i)
 i += 2 + len(name) + 1
+print_guard_end(name)
 print """   ;
 
 /* Weak aliases for all potential validate functions. These will resolve to
@@ -162,15 +182,21 @@ print """   ;
 
 print "\nstatic const struct anv_entrypoint entrypoints[] = {"
 for type, name, args, num, h in entrypoints:
+print_guard_start(name)
 print "   { %5d, 0x%08x }," % (offsets[num], h)
+print_guard_end(name)
 print "};\n"
 
 for layer in [ "anv", "validate", "gen7", "gen75", "gen8", "gen9" ]:
 for type, name, args, num, h in entrypoints:
+print_guard_start(name)
 print "%s %s_%s%s __attribute__ ((weak));" % (type, layer, name, args)
+print_guard_end(name)
 print "\nconst struct anv_dispatch_table %s_layer = {" % layer
 for type, name, args, num, h in entrypoints:
+print_guard_start(name)
 print "   .%s = %s_%s," % (name, layer, name)
+print_guard_end(name)
 print "};\n"
 
 print """
@@ -242,8 +268,10 @@ anv_resolve_entrypoint(uint32_t index)
 # lets the resolver look it up in the table.
 
 for type, name, args, num, h in entrypoints:
+print_guard_start(name)
 print "static void *resolve_%s(void) { return anv_resolve_entrypoint(%d); 
}" % (name, num)
 print "%s vk%s%s\n   __attribute__ ((ifunc (\"resolve_%s\"), visibility 
(\"default\")));\n" % (type, name, args, name)
+print_guard_end(name)
 
 
 # Now generate the hash table used for entry point look up.  This is a

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Mesa (master): svga: change enum pipe_resource_usage back to unsigned

[Brian Paul]

Module: Mesa
Branch: master
Commit: 6bea33008e42040335d5a44359be291f0b5ac24f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6bea33008e42040335d5a44359be291f0b5ac24f

Author: Brian Paul 
Date:   Tue May 31 07:25:03 2016 -0600

svga: change enum pipe_resource_usage back to unsigned

This parameter is actually a bitmask of PIPE_TRANSFER_x flags.
Change it back to a simple unsigned type.  IIRC, some compilers
complain about masks of enum values.  Also, this make the function
signature match u_resource_vtbl::transfer_map() again.

Reviewed-by: Roland Scheidegger 

---

 src/gallium/drivers/svga/svga_resource_buffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/svga/svga_resource_buffer.c 
b/src/gallium/drivers/svga/svga_resource_buffer.c
index d91497c..9ecb975 100644
--- a/src/gallium/drivers/svga/svga_resource_buffer.c
+++ b/src/gallium/drivers/svga/svga_resource_buffer.c
@@ -69,7 +69,7 @@ static void *
 svga_buffer_transfer_map(struct pipe_context *pipe,
  struct pipe_resource *resource,
  unsigned level,
- enum pipe_resource_usage usage,
+ unsigned usage,
  const struct pipe_box *box,
  struct pipe_transfer **ptransfer)
 {

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Mesa (master): radeonsi: fix CP DMA hazard with index buffer fetches

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 7ca55d2da88edb45cd99ef42888de18a61e64b0a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ca55d2da88edb45cd99ef42888de18a61e64b0a

Author: Marek Olšák 
Date:   Thu May 26 22:00:03 2016 +0200

radeonsi: fix CP DMA hazard with index buffer fetches

Reviewed-by: Alex Deucher 

---

 src/gallium/drivers/radeonsi/si_cp_dma.c | 22 --
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c 
b/src/gallium/drivers/radeonsi/si_cp_dma.c
index cbb84b0..882458c 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -73,12 +73,23 @@ static void si_emit_cp_dma_copy_buffer(struct si_context 
*sctx,
radeon_emit(cs, (dst_va >> 32) & 0x);   /* DST_ADDR_HI 
[15:0] */
radeon_emit(cs, size | wr_confirm | raw_wait);  /* COMMAND 
[29:22] | BYTE_COUNT [20:0] */
}
+
+   /* CP DMA is executed in ME, but index buffers are read by PFP.
+* This ensures that ME (CP DMA) is idle before PFP starts fetching
+* indices. If we wanted to execute CP DMA in PFP, this packet
+* should precede it.
+*/
+   if (sync_flag) {
+   radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
+   radeon_emit(cs, 0);
+   }
 }
 
 /* Emit a CP DMA packet to clear a buffer. The size must fit in bits [20:0]. */
 static void si_emit_cp_dma_clear_buffer(struct si_context *sctx,
uint64_t dst_va, unsigned size,
-   uint32_t clear_value, unsigned flags)
+   uint32_t clear_value, unsigned flags,
+   enum r600_coherency coher)
 {
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
@@ -105,6 +116,12 @@ static void si_emit_cp_dma_clear_buffer(struct si_context 
*sctx,
radeon_emit(cs, (dst_va >> 32) & 0x);   /* DST_ADDR_HI 
[15:0] */
radeon_emit(cs, size | wr_confirm | raw_wait);  /* COMMAND 
[29:22] | BYTE_COUNT [20:0] */
}
+
+   /* See "copy_buffer" for explanation. */
+   if (coher == R600_COHERENCY_SHADER && sync_flag) {
+   radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
+   radeon_emit(cs, 0);
+   }
 }
 
 static unsigned get_flush_flags(struct si_context *sctx, enum r600_coherency 
coher)
@@ -207,7 +224,8 @@ static void si_clear_buffer(struct pipe_context *ctx, 
struct pipe_resource *dst,
si_cp_dma_prepare(sctx, dst, NULL, byte_count, size, 
_flags);
 
/* Emit the clear packet. */
-   si_emit_cp_dma_clear_buffer(sctx, va, byte_count, value, 
dma_flags);
+   si_emit_cp_dma_clear_buffer(sctx, va, byte_count, value,
+   dma_flags, coher);
 
size -= byte_count;
va += byte_count;

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Mesa (master): gallium/u_blitter: do GL-compliant integer resolves

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 921ab0028e7ed90c4eeef3a2f674291450f39874
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=921ab0028e7ed90c4eeef3a2f674291450f39874

Author: Marek Olšák 
Date:   Tue May 31 12:03:32 2016 +0200

gallium/u_blitter: do GL-compliant integer resolves

The GL spec has been clarified and the new rule says we should just
copy 1 sample.

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/auxiliary/util/u_blitter.c | 26 +++---
 1 file changed, 7 insertions(+), 19 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_blitter.c 
b/src/gallium/auxiliary/util/u_blitter.c
index 2a44d6b..ad645ad 100644
--- a/src/gallium/auxiliary/util/u_blitter.c
+++ b/src/gallium/auxiliary/util/u_blitter.c
@@ -100,8 +100,6 @@ struct blitter_context_priv
 
/* FS which outputs an average of all samples. */
void *fs_resolve[PIPE_MAX_TEXTURE_TYPES][NUM_RESOLVE_FRAG_SHADERS][2];
-   void *fs_resolve_sint[PIPE_MAX_TEXTURE_TYPES][NUM_RESOLVE_FRAG_SHADERS][2];
-   void *fs_resolve_uint[PIPE_MAX_TEXTURE_TYPES][NUM_RESOLVE_FRAG_SHADERS][2];
 
/* Blend state. */
void *blend[PIPE_MASK_RGBA+1][2]; /**< blend state with writemask */
@@ -487,16 +485,6 @@ void util_blitter_destroy(struct blitter_context *blitter)
  for (f = 0; f < 2; f++)
 if (ctx->fs_resolve[i][j][f])
ctx->delete_fs_state(pipe, ctx->fs_resolve[i][j][f]);
-
-  for (j = 0; j< ARRAY_SIZE(ctx->fs_resolve_sint[i]); j++)
- for (f = 0; f < 2; f++)
-if (ctx->fs_resolve_sint[i][j][f])
-   ctx->delete_fs_state(pipe, ctx->fs_resolve_sint[i][j][f]);
-
-  for (j = 0; j< ARRAY_SIZE(ctx->fs_resolve_uint[i]); j++)
- for (f = 0; f < 2; f++)
-if (ctx->fs_resolve_uint[i][j][f])
-   ctx->delete_fs_state(pipe, ctx->fs_resolve_uint[i][j][f]);
}
 
if (ctx->fs_empty)
@@ -891,18 +879,18 @@ static void *blitter_get_fs_texfetch_col(struct 
blitter_context_priv *ctx,
if (src_nr_samples > 1) {
   void **shader;
 
-  if (dst_nr_samples <= 1) {
+  /* OpenGL requires that integer textures just copy 1 sample instead
+   * of averaging.
+   */
+  if (dst_nr_samples <= 1 &&
+  stype != TGSI_RETURN_TYPE_UINT &&
+  stype != TGSI_RETURN_TYPE_SINT) {
  /* The destination has one sample, so we'll do color resolve. */
  unsigned index = GET_MSAA_RESOLVE_FS_IDX(src_nr_samples);
 
  assert(filter < 2);
 
- if (stype == TGSI_RETURN_TYPE_UINT)
-shader = >fs_resolve_uint[target][index][filter];
- else if (stype == TGSI_RETURN_TYPE_SINT)
-shader = >fs_resolve_sint[target][index][filter];
- else
-shader = >fs_resolve[target][index][filter];
+ shader = >fs_resolve[target][index][filter];
 
  if (!*shader) {
 assert(!ctx->cached_all_shaders);

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Mesa (master): r600g: do GL-compliant integer resolves

[Marek Olšák]

Module: Mesa
Branch: master
Commit: d4271108825e2d1590d62cdc3d99b1b6fb2c5fef
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4271108825e2d1590d62cdc3d99b1b6fb2c5fef

Author: Marek Olšák 
Date:   Tue May 31 12:03:32 2016 +0200

r600g: do GL-compliant integer resolves

The GL spec has been clarified and the new rule says we should just
copy 1 sample. u_blitter does the right thing.

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/r600/r600_blit.c | 38 +---
 1 file changed, 1 insertion(+), 37 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_blit.c 
b/src/gallium/drivers/r600/r600_blit.c
index 9230b40..282645f 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -756,42 +756,6 @@ void r600_resource_copy_region(struct pipe_context *ctx,
pipe_sampler_view_reference(_view, NULL);
 }
 
-/* For MSAA integer resolving to work, we change the format to NORM using this 
function. */
-static enum pipe_format int_to_norm_format(enum pipe_format format)
-{
-   switch (format) {
-#define REPLACE_FORMAT_SIGN(format,sign) \
-   case PIPE_FORMAT_##format##_##sign##INT: \
-   return PIPE_FORMAT_##format##_##sign##NORM
-#define REPLACE_FORMAT(format) \
-   REPLACE_FORMAT_SIGN(format, U); \
-   REPLACE_FORMAT_SIGN(format, S)
-
-   REPLACE_FORMAT_SIGN(B10G10R10A2, U);
-   REPLACE_FORMAT(R8);
-   REPLACE_FORMAT(R8G8);
-   REPLACE_FORMAT(R8G8B8X8);
-   REPLACE_FORMAT(R8G8B8A8);
-   REPLACE_FORMAT(A8);
-   REPLACE_FORMAT(I8);
-   REPLACE_FORMAT(L8);
-   REPLACE_FORMAT(L8A8);
-   REPLACE_FORMAT(R16);
-   REPLACE_FORMAT(R16G16);
-   REPLACE_FORMAT(R16G16B16X16);
-   REPLACE_FORMAT(R16G16B16A16);
-   REPLACE_FORMAT(A16);
-   REPLACE_FORMAT(I16);
-   REPLACE_FORMAT(L16);
-   REPLACE_FORMAT(L16A16);
-
-#undef REPLACE_FORMAT
-#undef REPLACE_FORMAT_SIGN
-   default:
-   return format;
-   }
-}
-
 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
 const struct pipe_blit_info *info)
 {
@@ -799,7 +763,7 @@ static bool do_hardware_msaa_resolve(struct pipe_context 
*ctx,
struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
unsigned dst_width = u_minify(info->dst.resource->width0, 
info->dst.level);
unsigned dst_height = u_minify(info->dst.resource->height0, 
info->dst.level);
-   enum pipe_format format = int_to_norm_format(info->dst.format);
+   enum pipe_format format = info->dst.format;
unsigned sample_mask =
rctx->b.chip_class == CAYMAN ? ~0 :
((1ull << MAX2(1, info->src.resource->nr_samples)) - 1);

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Mesa (master): radeonsi: do GL-compliant integer resolves

[Marek Olšák]

Module: Mesa
Branch: master
Commit: d5882bb0df87aeb94cddc9f00e4105907e35e81f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5882bb0df87aeb94cddc9f00e4105907e35e81f

Author: Marek Olšák 
Date:   Tue May 31 12:03:32 2016 +0200

radeonsi: do GL-compliant integer resolves

The GL spec has been clarified and the new rule says we should just
copy 1 sample. u_blitter does the right thing.

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_blit.c | 38 +-
 1 file changed, 1 insertion(+), 37 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 716a522..6f3199c 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -748,42 +748,6 @@ void si_resource_copy_region(struct pipe_context *ctx,
pipe_sampler_view_reference(_view, NULL);
 }
 
-/* For MSAA integer resolving to work, we change the format to NORM using this 
function. */
-static enum pipe_format int_to_norm_format(enum pipe_format format)
-{
-   switch (format) {
-#define REPLACE_FORMAT_SIGN(format,sign) \
-   case PIPE_FORMAT_##format##_##sign##INT: \
-   return PIPE_FORMAT_##format##_##sign##NORM
-#define REPLACE_FORMAT(format) \
-   REPLACE_FORMAT_SIGN(format, U); \
-   REPLACE_FORMAT_SIGN(format, S)
-
-   REPLACE_FORMAT_SIGN(B10G10R10A2, U);
-   REPLACE_FORMAT(R8);
-   REPLACE_FORMAT(R8G8);
-   REPLACE_FORMAT(R8G8B8X8);
-   REPLACE_FORMAT(R8G8B8A8);
-   REPLACE_FORMAT(A8);
-   REPLACE_FORMAT(I8);
-   REPLACE_FORMAT(L8);
-   REPLACE_FORMAT(L8A8);
-   REPLACE_FORMAT(R16);
-   REPLACE_FORMAT(R16G16);
-   REPLACE_FORMAT(R16G16B16X16);
-   REPLACE_FORMAT(R16G16B16A16);
-   REPLACE_FORMAT(A16);
-   REPLACE_FORMAT(I16);
-   REPLACE_FORMAT(L16);
-   REPLACE_FORMAT(L16A16);
-
-#undef REPLACE_FORMAT
-#undef REPLACE_FORMAT_SIGN
-   default:
-   return format;
-   }
-}
-
 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
 const struct pipe_blit_info *info)
 {
@@ -791,7 +755,7 @@ static bool do_hardware_msaa_resolve(struct pipe_context 
*ctx,
struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
unsigned dst_width = u_minify(info->dst.resource->width0, 
info->dst.level);
unsigned dst_height = u_minify(info->dst.resource->height0, 
info->dst.level);
-   enum pipe_format format = int_to_norm_format(info->dst.format);
+   enum pipe_format format = info->dst.format;
unsigned sample_mask = ~0;
 
/* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and

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Mesa (master): mesa: fix crash in driver_RenderTexture_is_safe

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 8a10192b4b2435577bde1227c06166029b581398
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a10192b4b2435577bde1227c06166029b581398

Author: Marek Olšák 
Date:   Mon May 30 16:29:18 2016 +0200

mesa: fix crash in driver_RenderTexture_is_safe

This just fixed the crash with the apitrace in bug report.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95246

Cc: 11.1 11.2 12.0 
Reviewed-by: Nicolai Hähnle 

---

 src/mesa/main/fbobject.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index fa5baa3..bf47c1c 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -389,7 +389,8 @@ driver_RenderTexture_is_safe(const struct 
gl_renderbuffer_attachment *att)
const struct gl_texture_image *const texImage =
   att->Texture->Image[att->CubeMapFace][att->TextureLevel];
 
-   if (texImage->Width == 0 || texImage->Height == 0 || texImage->Depth == 0)
+   if (!texImage ||
+   texImage->Width == 0 || texImage->Height == 0 || texImage->Depth == 0)
   return false;
 
if ((texImage->TexObject->Target == GL_TEXTURE_1D_ARRAY

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Mesa (master): radeonsi: don't flush TC at the end of IBs on DRM >= 3.2.0

[Marek Olšák]

Module: Mesa
Branch: master
Commit: fc4896e686f79893d6496c7a792a6c72cb3759c1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc4896e686f79893d6496c7a792a6c72cb3759c1

Author: Marek Olšák 
Date:   Thu May 26 20:39:51 2016 +0200

radeonsi: don't flush TC at the end of IBs on DRM >= 3.2.0

It's not needed since it was fixed in the kernel.

Reviewed-by: Alex Deucher 

---

 src/gallium/drivers/radeonsi/si_hw_context.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c 
b/src/gallium/drivers/radeonsi/si_hw_context.c
index dcf206d..6221f1c 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -116,8 +116,9 @@ void si_context_gfx_flush(void *context, unsigned flags,
 
ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
SI_CONTEXT_PS_PARTIAL_FLUSH;
-   /* The kernel doesn't flush TC for VI correctly (need 
TC_WB_ACTION_ENA). */
-   if (ctx->b.chip_class == VI)
+
+   /* DRM 3.1.0 doesn't flush TC for VI correctly. */
+   if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1)
ctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2 |
SI_CONTEXT_INV_VMEM_L1;
 

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Mesa (master): gallium/radeon: fixed division by zero

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 877c00c653ac782f8867a3fee24f16707b1d568c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=877c00c653ac782f8867a3fee24f16707b1d568c

Author: Jakob Sinclair 
Date:   Wed May 18 19:48:29 2016 +0200

gallium/radeon: fixed division by zero

Coverity is getting a false positive that a division by zero can occur
here. This change will silence the Coverity warnings as a division by zero
cannot occur in this case.

Signed-off-by: Jakob Sinclair 
Reviewed-by: Nicolai Hähnle 
Signed-off-by: Marek Olšák 

---

 src/gallium/drivers/radeon/r600_test_dma.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/drivers/radeon/r600_test_dma.c 
b/src/gallium/drivers/radeon/r600_test_dma.c
index c203b4d..1e60f6a 100644
--- a/src/gallium/drivers/radeon/r600_test_dma.c
+++ b/src/gallium/drivers/radeon/r600_test_dma.c
@@ -345,6 +345,9 @@ void r600_test_dma(struct r600_common_screen *rscreen)
dstx = rand() % (tdst.width0 - width + 
1) & ~0x7;
dsty = rand() % (tdst.height0 - height 
+ 1) & ~0x7;
} else {
+   /* just make sure that it doesn't 
divide by zero */
+   assert(max_width > 0 && max_height > 0);
+
width = (rand() % max_width) + 1;
height = (rand() % max_height) + 1;
 

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Mesa (master): st/glsl_to_tgsi: prevent infinite loop

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 35fd5282ea39a15fab4f7b9639ffe0853a19b415
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=35fd5282ea39a15fab4f7b9639ffe0853a19b415

Author: Eric Engestrom 
Date:   Tue May 31 02:20:12 2016 +0100

st/glsl_to_tgsi: prevent infinite loop

`unsigned j` would never fail `j >= 0`, leading to an infinite loop as
`j--` wraps around.

Signed-off-by: Eric Engestrom 
Signed-off-by: Marek Olšák 

---

 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index aa443a5..91a0a26 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -2447,7 +2447,8 @@ shrink_array_declarations(struct array_decl *arrays, 
unsigned count,
   GLbitfield64 double_usage_mask,
   GLbitfield patch_usage_mask)
 {
-   unsigned i, j;
+   unsigned i;
+   int j;
 
/* Fix array declarations by removing unused array elements at both ends
 * of the arrays. For example, mat4[3] where only mat[1] is used.
@@ -2456,7 +2457,7 @@ shrink_array_declarations(struct array_decl *arrays, 
unsigned count,
   struct array_decl *decl = [i];
 
   /* Shrink the beginning. */
-  for (j = 0; j < decl->array_size; j++) {
+  for (j = 0; j < (int)decl->array_size; j++) {
  if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
 if (patch_usage_mask &
 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))

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