Mesa (master): glsl: stop allocating memory for SSBOs and builtins

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 8c3ecde0e18977f49b804226d7c28483e025cbcd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c3ecde0e18977f49b804226d7c28483e025cbcd

Author: Timothy Arceri 
Date:   Thu Jun  2 15:32:14 2016 +1000

glsl: stop allocating memory for SSBOs and builtins

This just stops counting and assigning a storage location for
these uniforms, the count is only used to create the uniform storage.

These uniform types don't use this storage.

Reviewed-by: Dave Airlie 

---

 src/compiler/glsl/link_uniforms.cpp | 20 +---
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/src/compiler/glsl/link_uniforms.cpp 
b/src/compiler/glsl/link_uniforms.cpp
index 3a2ac4d..98ae3ad 100644
--- a/src/compiler/glsl/link_uniforms.cpp
+++ b/src/compiler/glsl/link_uniforms.cpp
@@ -402,7 +402,9 @@ private:
* uniforms.
*/
   this->num_active_uniforms++;
-  this->num_values += values;
+
+  if(!is_gl_identifier(name) && !is_shader_storage)
+ this->num_values += values;
}
 
struct string_to_uint_map *hidden_map;
@@ -762,13 +764,14 @@ private:
  current_var->data.how_declared == ir_var_hidden;
   this->uniforms[id].builtin = is_gl_identifier(name);
 
-  /* Do not assign storage if the uniform is builtin */
-  if (!this->uniforms[id].builtin)
- this->uniforms[id].storage = this->values;
-
   this->uniforms[id].is_shader_storage =
  current_var->is_in_shader_storage_block();
 
+  /* Do not assign storage if the uniform is builtin */
+  if (!this->uniforms[id].builtin &&
+  !this->uniforms[id].is_shader_storage)
+ this->uniforms[id].storage = this->values;
+
   if (this->buffer_block_index != -1) {
  this->uniforms[id].block_index = this->buffer_block_index;
 
@@ -819,7 +822,9 @@ private:
  this->uniforms[id].row_major = false;
   }
 
-  this->values += values_for_type(type);
+  if (!this->uniforms[id].builtin &&
+  !this->uniforms[id].is_shader_storage)
+ this->values += values_for_type(type);
}
 
/**
@@ -1251,7 +1256,8 @@ link_assign_uniform_locations(struct gl_shader_program 
*prog,
 
 #ifndef NDEBUG
for (unsigned i = 0; i < num_uniforms; i++) {
-  assert(uniforms[i].storage != NULL || uniforms[i].builtin);
+  assert(uniforms[i].storage != NULL || uniforms[i].builtin ||
+ uniforms[i].is_shader_storage);
}
 
assert(parcel.values == data_end);

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Mesa (master): st/mesa: use buffer usage history to set dirty flags for revalidation

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 6e6fd911da8a1d9cd62fe0a8a4cc0fb7bdccfe02
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e6fd911da8a1d9cd62fe0a8a4cc0fb7bdccfe02

Author: Ilia Mirkin 
Date:   Sat Jun  4 13:26:46 2016 -0400

st/mesa: use buffer usage history to set dirty flags for revalidation

We were previously unconditionally doing this for arrays and ubo's, and
ignoring texture/storage/atomic buffers. Instead use the usage history
to determine which atoms need to be revalidated.

Signed-off-by: Ilia Mirkin 
Reviewed-by: Nicolai Hähnle 
Cc: "12.0" 

---

 src/mesa/state_tracker/st_cb_bufferobjects.c | 15 +--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/src/mesa/state_tracker/st_cb_bufferobjects.c 
b/src/mesa/state_tracker/st_cb_bufferobjects.c
index 8bbc2f0..1a8aea3 100644
--- a/src/mesa/state_tracker/st_cb_bufferobjects.c
+++ b/src/mesa/state_tracker/st_cb_bufferobjects.c
@@ -332,8 +332,19 @@ st_bufferobj_data(struct gl_context *ctx,
   }
}
 
-   /* BufferData may change an array or uniform buffer, need to update it */
-   st->dirty.st |= ST_NEW_VERTEX_ARRAYS | ST_NEW_UNIFORM_BUFFER;
+   /* The current buffer may be bound, so we have to revalidate all atoms that
+* might be using it.
+*/
+   /* TODO: Add arrays to usage history */
+   st->dirty.st |= ST_NEW_VERTEX_ARRAYS;
+   if (st_obj->Base.UsageHistory & USAGE_UNIFORM_BUFFER)
+  st->dirty.st |= ST_NEW_UNIFORM_BUFFER;
+   if (st_obj->Base.UsageHistory & USAGE_SHADER_STORAGE_BUFFER)
+  st->dirty.st |= ST_NEW_STORAGE_BUFFER;
+   if (st_obj->Base.UsageHistory & USAGE_TEXTURE_BUFFER)
+  st->dirty.st |= ST_NEW_SAMPLER_VIEWS | ST_NEW_IMAGE_UNITS;
+   if (st_obj->Base.UsageHistory & USAGE_ATOMIC_COUNTER_BUFFER)
+  st->dirty.st |= ST_NEW_ATOMIC_BUFFER;
 
return GL_TRUE;
 }

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Mesa (master): i965: Integrate precise trig into configuration infrastructure

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: d9546b0c5d1a5136a92276cdd7c14883f0c62737
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d9546b0c5d1a5136a92276cdd7c14883f0c62737

Author: Gurchetan Singh 
Date:   Wed May 11 13:32:09 2016 -0700

i965: Integrate precise trig into configuration infrastructure

With this change, to enable precise SIN and COS instructions
on Intel hardware, one can put



in the proper drirc file.

V2: Make option name more generic

Reviewed-by: Kenneth Graunke 
Reviewed-by: Stephane Marchesin 

---

 src/mesa/drivers/dri/common/xmlpool/t_options.h | 5 +
 src/mesa/drivers/dri/i965/brw_compiler.c| 2 --
 src/mesa/drivers/dri/i965/brw_context.c | 3 +++
 src/mesa/drivers/dri/i965/intel_screen.c| 2 ++
 4 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/common/xmlpool/t_options.h 
b/src/mesa/drivers/dri/common/xmlpool/t_options.h
index e5cbc46..4b298a4 100644
--- a/src/mesa/drivers/dri/common/xmlpool/t_options.h
+++ b/src/mesa/drivers/dri/common/xmlpool/t_options.h
@@ -158,6 +158,11 @@ DRI_CONF_OPT_BEGIN_B(force_s3tc_enable, def) \
 DRI_CONF_DESC(en,gettext("Enable S3TC texture compression even if 
software support is not available")) \
 DRI_CONF_OPT_END
 
+#define DRI_CONF_PRECISE_TRIG(def) \
+DRI_CONF_OPT_BEGIN_B(precise_trig, def) \
+DRI_CONF_DESC(en,gettext("Prefer accuracy over performance in trig 
functions")) \
+DRI_CONF_OPT_END
+
 #define DRI_CONF_COLOR_REDUCTION_ROUND 0
 #define DRI_CONF_COLOR_REDUCTION_DITHER 1
 #define DRI_CONF_COLOR_REDUCTION(def) \
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.c 
b/src/mesa/drivers/dri/i965/brw_compiler.c
index a4855a0..9eda3fc 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.c
+++ b/src/mesa/drivers/dri/i965/brw_compiler.c
@@ -103,8 +103,6 @@ brw_compiler_create(void *mem_ctx, const struct 
brw_device_info *devinfo)
brw_fs_alloc_reg_sets(compiler);
brw_vec4_alloc_reg_set(compiler);
 
-   compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
-
compiler->scalar_stage[MESA_SHADER_VERTEX] =
   devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 97dc226..7bbc128 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -803,6 +803,9 @@ brw_process_driconf_options(struct brw_context *brw)
 
brw->precompile = driQueryOptionb(>optionCache, "shader_precompile");
 
+   brw->intelScreen->compiler->precise_trig =
+  driQueryOptionb(>optionCache, "precise_trig");
+
ctx->Const.ForceGLSLExtensionsWarn =
   driQueryOptionb(options, "force_glsl_extensions_warn");
 
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index fb06e25..aa072fa 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -65,6 +65,8 @@ DRI_CONF_BEGIN
DRI_CONF_SECTION_QUALITY
   DRI_CONF_FORCE_S3TC_ENABLE("false")
 
+  DRI_CONF_PRECISE_TRIG("false")
+
   DRI_CONF_OPT_BEGIN(clamp_max_samples, int, -1)
   DRI_CONF_DESC(en, "Clamp the value of GL_MAX_SAMPLES to the "
 "given integer. If negative, then do not clamp.")

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Mesa (master): winsys/amdgpu: enable DCC for mipmapped textures

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 00389100b63d03adf70892b721d1b2e8b8d5e48a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=00389100b63d03adf70892b721d1b2e8b8d5e48a

Author: Marek Olšák 
Date:   Fri Jun  3 20:48:01 2016 +0200

winsys/amdgpu: enable DCC for mipmapped textures

Also add dcc_fast_clear_size for clearing only the necessary subset
of DCC. For no AA, it's equal to the size of the whole DCC level.

Reviewed-by: Nicolai Hähnle 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/gallium/drivers/radeon/r600_texture.c  | 10 ++---
 src/gallium/drivers/radeon/radeon_winsys.h |  1 +
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 29 --
 3 files changed, 31 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 27b464f..9daad65 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -931,8 +931,11 @@ void r600_print_texture_info(struct r600_texture *rtex, 
FILE *f)
rtex->dcc_offset, rtex->surface.dcc_size,
rtex->surface.dcc_alignment);
for (i = 0; i <= rtex->surface.last_level; i++)
-   fprintf(f, "  DCCLevel[%i]: offset=%"PRIu64"\n",
-   i, rtex->surface.level[i].dcc_offset);
+   fprintf(f, "  DCCLevel[%i]: enabled=%u, 
offset=%"PRIu64", "
+   "fast_clear_size=%"PRIu64"\n",
+   i, rtex->surface.level[i].dcc_enabled,
+   rtex->surface.level[i].dcc_offset,
+   rtex->surface.level[i].dcc_fast_clear_size);
}
 
for (i = 0; i <= rtex->surface.last_level; i++)
@@ -1865,7 +1868,8 @@ void evergreen_do_fast_color_clear(struct 
r600_common_context *rctx,
vi_get_fast_clear_parameters(fb->cbufs[i]->format, 
color, _value, _words_needed);
 
rctx->clear_buffer(>b, >resource.b.b,
-  tex->dcc_offset, 
tex->surface.dcc_size,
+  tex->dcc_offset,
+  
tex->surface.level[0].dcc_fast_clear_size,
   reset_value, R600_COHERENCY_CB_META);
 
if (clear_words_needed)
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index d7bb165..c2d1f9e 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -360,6 +360,7 @@ struct radeon_surf_level {
 uint32_tpitch_bytes;
 uint32_tmode;
 uint64_tdcc_offset;
+uint64_tdcc_fast_clear_size;
 booldcc_enabled;
 };
 
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 52b3fa8..9f52588 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -230,7 +230,9 @@ static int compute_level(struct amdgpu_winsys *ws,
surf_level->dcc_offset = 0;
surf_level->dcc_enabled = false;
 
-   if (AddrSurfInfoIn->flags.dccCompatible) {
+   /* The previous level's flag tells us if we can use DCC for this level. */
+   if (AddrSurfInfoIn->flags.dccCompatible &&
+   (level == 0 || AddrDccOut->subLvlCompressible)) {
   AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
   AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
   AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
@@ -243,14 +245,11 @@ static int compute_level(struct amdgpu_winsys *ws,
 
   if (ret == ADDR_OK) {
  surf_level->dcc_offset = surf->dcc_size;
+ surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
  surf_level->dcc_enabled = true;
  surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
  surf->dcc_alignment = MAX2(surf->dcc_alignment, 
AddrDccOut->dccRamBaseAlign);
-  } else {
- surf->dcc_size = 0;
   }
-   } else {
-  surf->dcc_size = 0;
}
 
return 0;
@@ -344,11 +343,19 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
AddrSurfInfoIn.flags.pow2Pad = surf->last_level > 0;
AddrSurfInfoIn.flags.degrade4Space = 1;
+
+   /* DCC notes:
+* - If we add MSAA support, keep in mind that CB can't decompress 8bpp
+*   with samples >= 4.
+* - Mipmapped array textures have low performance (discovered by a closed
+*   driver team).
+*/
AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & 
RADEON_SURF_Z_OR_SBUFFER) &&
 

Mesa (master): radeonsi: allow MSAA resolving into a texture that has DCC enabled

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 7c6e88b6430b3a805f982c7f8b34d1f79a8fc09c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c6e88b6430b3a805f982c7f8b34d1f79a8fc09c

Author: Marek Olšák 
Date:   Mon Jun  6 02:01:36 2016 +0200

radeonsi: allow MSAA resolving into a texture that has DCC enabled

Since DCC is enabled almost everywhere now, it's important not to disable
this fast path.

Reviewed-by: Nicolai Hähnle 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/gallium/drivers/radeonsi/si_blit.c  | 15 +--
 src/gallium/drivers/radeonsi/si_state.c | 12 ++--
 2 files changed, 23 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index c28533e..23ae382 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -902,8 +902,19 @@ static bool do_hardware_msaa_resolve(struct pipe_context 
*ctx,
info->src.box.height == dst_height &&
info->src.box.depth == 1 &&
dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
-   (!dst->cmask.size || !dst->dirty_level_mask) && /* dst cannot be 
fast-cleared */
-   !dst->dcc_offset) {
+   (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be 
fast-cleared */
+   /* Resolving into a surface with DCC is unsupported. Since
+* it's being overwritten anyway, clear it to uncompressed.
+* This is still the fastest codepath even with this clear.
+*/
+   if (dst->dcc_offset &&
+   dst->surface.level[info->dst.level].dcc_enabled) {
+   vi_dcc_clear_level(>b, dst, info->dst.level,
+  0x);
+   dst->dirty_level_mask &= ~(1 << info->dst.level);
+   }
+
+   /* Resolve directly from src to dst. */
si_blitter_begin(ctx, SI_COLOR_RESOLVE |
 (info->render_condition_enable ? 0 : 
SI_DISABLE_RENDER_COND));
util_blitter_custom_resolve_color(sctx->blitter,
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 270b9fd..92448a4 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2443,8 +2443,16 @@ static void si_emit_framebuffer_state(struct si_context 
*sctx, struct r600_atom
}
 
cb_color_info = cb->cb_color_info | tex->cb_color_info;
-   if (tex->dcc_offset && cb->level_info->dcc_enabled)
-   cb_color_info |= S_028C70_DCC_ENABLE(1);
+
+   if (tex->dcc_offset && cb->level_info->dcc_enabled) {
+   bool is_msaa_resolve_dst = state->cbufs[0] &&
+  
state->cbufs[0]->texture->nr_samples > 1 &&
+  state->cbufs[1] == >base 
&&
+  
state->cbufs[1]->texture->nr_samples <= 1;
+
+   if (!is_msaa_resolve_dst)
+   cb_color_info |= S_028C70_DCC_ENABLE(1);
+   }
 
radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 
0x3C,
   sctx->b.chip_class >= VI ? 14 : 13);

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Mesa (master): radeonsi: don' t enable DCC in the sampler if first_level doesn't have it

[Marek Olšák]

Module: Mesa
Branch: master
Commit: c06246501ed9c095a3fa9f8fe2a5dadd1df55271
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c06246501ed9c095a3fa9f8fe2a5dadd1df55271

Author: Marek Olšák 
Date:   Mon Jun  6 17:33:42 2016 +0200

radeonsi: don't enable DCC in the sampler if first_level doesn't have it

If first_level > 0 and DCC is disabled for that level, let's skip DCC
reads entirely.

Reviewed-by: Nicolai Hähnle 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/gallium/drivers/radeonsi/si_descriptors.c | 21 +
 src/gallium/drivers/radeonsi/si_state.c   |  2 +-
 src/gallium/drivers/radeonsi/si_state.h   |  5 +++--
 3 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index e0c9666..e80db39 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -312,10 +312,21 @@ static void si_sampler_views_begin_new_cs(struct 
si_context *sctx,
}
 }
 
+/* Set texture descriptor fields that can be changed by reallocations.
+ *
+ * \param tex  texture
+ * \param base_level_info  information of the level of BASE_ADDRESS
+ * \param base_level   the level of BASE_ADDRESS
+ * \param first_level  pipe_sampler_view.u.tex.first_level
+ * \param block_width  util_format_get_blockwidth()
+ * \param is_stencil   select between separate Z & Stencil
+ * \param statedescriptor to update
+ */
 void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
const struct radeon_surf_level 
*base_level_info,
-   unsigned base_level, unsigned block_width,
-   bool is_stencil, uint32_t *state)
+   unsigned base_level, unsigned first_level,
+   unsigned block_width, bool is_stencil,
+   uint32_t *state)
 {
uint64_t va = tex->resource.gpu_address + base_level_info->offset;
unsigned pitch = base_level_info->nblk_x * block_width;
@@ -331,7 +342,7 @@ void si_set_mutable_tex_desc_fields(struct r600_texture 
*tex,
 is_stencil));
state[4] |= S_008F20_PITCH(pitch - 1);
 
-   if (tex->dcc_offset && base_level_info->dcc_enabled) {
+   if (tex->dcc_offset && tex->surface.level[first_level].dcc_enabled) {
state[6] |= S_008F28_COMPRESSION_EN(1);
state[7] = (tex->resource.gpu_address +
tex->dcc_offset +
@@ -369,6 +380,7 @@ static void si_set_sampler_view(struct si_context *sctx,
si_set_mutable_tex_desc_fields(rtex,
   rview->base_level_info,
   rview->base_level,
+  
rview->base.u.tex.first_level,
   rview->block_width,
   is_separate_stencil,
   desc);
@@ -640,7 +652,8 @@ static void si_set_shader_image(struct si_context *ctx,
   view->u.tex.last_layer,
   width, height, depth,
   desc, NULL);
-   si_set_mutable_tex_desc_fields(tex, >surface.level[level], 
level,
+   si_set_mutable_tex_desc_fields(tex, >surface.level[level],
+  level, level,
   
util_format_get_blockwidth(view->format),
   false, desc);
}
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index fc28fc9..270b9fd 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3446,7 +3446,7 @@ static void si_query_opaque_metadata(struct 
r600_common_screen *rscreen,
   res->width0, res->height0, res->depth0,
   desc, NULL);
 
-   si_set_mutable_tex_desc_fields(rtex, >surface.level[0], 0,
+   si_set_mutable_tex_desc_fields(rtex, >surface.level[0], 0, 0,
   rtex->surface.blk_w, false, desc);
 
/* Clear the base address and set the relative DCC offset. */
diff --git a/src/gallium/drivers/radeonsi/si_state.h 
b/src/gallium/drivers/radeonsi/si_state.h
index 811a02f..a4a58bb 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -279,8 +279,9 @@ struct 

Mesa (master): radeonsi: re-enable PBO ReadPixels acceleration

[Marek Olšák]

Module: Mesa
Branch: master
Commit: f39439d1666481bd1316e865eb3507a2a397f346
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f39439d1666481bd1316e865eb3507a2a397f346

Author: Marek Olšák 
Date:   Tue Jun  7 21:34:31 2016 +0200

radeonsi: re-enable PBO ReadPixels acceleration

disabled by 4f1cccf570112f93265a4cace504eb763fa8f73e

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_state.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 92448a4..0c52eee 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1784,13 +1784,16 @@ boolean si_is_format_supported(struct pipe_screen 
*screen,
}
}
 
-   if (usage & PIPE_BIND_SAMPLER_VIEW) {
+   if (usage & (PIPE_BIND_SAMPLER_VIEW |
+PIPE_BIND_SHADER_IMAGE)) {
if (target == PIPE_BUFFER) {
if (si_is_vertex_format_supported(screen, format))
-   retval |= PIPE_BIND_SAMPLER_VIEW;
+   retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
+  PIPE_BIND_SHADER_IMAGE);
} else {
if (si_is_sampler_format_supported(screen, format))
-   retval |= PIPE_BIND_SAMPLER_VIEW;
+   retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
+  PIPE_BIND_SHADER_IMAGE);
}
}
 

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Mesa (master): radeonsi: add per-level dcc_enabled flags

[Marek Olšák]

Module: Mesa
Branch: master
Commit: aa7fe7044328039903993dde6edb32b7953ae9b0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa7fe7044328039903993dde6edb32b7953ae9b0

Author: Marek Olšák 
Date:   Fri Jun  3 20:40:30 2016 +0200

radeonsi: add per-level dcc_enabled flags

Reviewed-by: Nicolai Hähnle 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/gallium/drivers/radeon/r600_texture.c  |  6 +++---
 src/gallium/drivers/radeon/radeon_winsys.h |  1 +
 src/gallium/drivers/radeonsi/si_blit.c |  7 +++
 src/gallium/drivers/radeonsi/si_descriptors.c  |  9 +
 src/gallium/drivers/radeonsi/si_state.c|  2 +-
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 10 +++---
 6 files changed, 24 insertions(+), 11 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 37f8e02..b276417 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -72,10 +72,10 @@ bool r600_prepare_for_dma_blit(struct r600_common_context 
*rctx,
 *   dst: If overwriting the whole texture, discard DCC and use SDMA.
 *Otherwise, use the 3D path.
 */
-   if (rsrc->dcc_offset)
+   if (rsrc->dcc_offset && rsrc->surface.level[src_level].dcc_enabled)
return false;
 
-   if (rdst->dcc_offset) {
+   if (rdst->dcc_offset && rdst->surface.level[dst_level].dcc_enabled) {
/* We can't discard DCC if the texture has been exported.
 * We can only discard DCC for the entire texture.
 */
@@ -1872,7 +1872,7 @@ void evergreen_do_fast_color_clear(struct 
r600_common_context *rctx,
continue;
}
 
-   if (tex->dcc_offset) {
+   if (tex->dcc_offset && tex->surface.level[0].dcc_enabled) {
uint32_t reset_value;
bool clear_words_needed;
 
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index a0c7abf..d7bb165 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -360,6 +360,7 @@ struct radeon_surf_level {
 uint32_tpitch_bytes;
 uint32_tmode;
 uint64_tdcc_offset;
+booldcc_enabled;
 };
 
 struct radeon_surf {
diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 34481c1..2059d9d 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -321,6 +321,13 @@ static void si_blit_decompress_color(struct pipe_context 
*ctx,
 
if (rtex->dcc_offset && need_dcc_decompress) {
custom_blend = sctx->custom_blend_dcc_decompress;
+
+   /* disable levels without DCC */
+   for (int i = first_level; i <= last_level; i++) {
+   if (!rtex->dcc_offset ||
+   !rtex->surface.level[i].dcc_enabled)
+   level_mask &= ~(1 << i);
+   }
} else if (rtex->fmask.size) {
custom_blend = sctx->custom_blend_decompress;
} else {
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index bb81eb8..b2c3713 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -331,7 +331,7 @@ void si_set_mutable_tex_desc_fields(struct r600_texture 
*tex,
 is_stencil));
state[4] |= S_008F20_PITCH(pitch - 1);
 
-   if (tex->dcc_offset) {
+   if (tex->dcc_offset && base_level_info->dcc_enabled) {
state[6] |= S_008F28_COMPRESSION_EN(1);
state[7] = (tex->resource.gpu_address +
tex->dcc_offset +
@@ -591,14 +591,16 @@ static void si_set_shader_image(struct si_context *ctx,
} else {
static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
struct r600_texture *tex = (struct r600_texture *)res;
-   unsigned level;
+   unsigned level = view->u.tex.level;
unsigned width, height, depth;
uint32_t *desc = descs->list + slot * 8;
+   bool uses_dcc = tex->dcc_offset &&
+   tex->surface.level[level].dcc_enabled;
 
assert(!tex->is_depth);
assert(tex->fmask.size == 0);
 
-   if (tex->dcc_offset &&
+   if (uses_dcc &&
view->access & PIPE_IMAGE_ACCESS_WRITE) {
/* If DCC can't be disabled, at least decompress it.
 * The decompression is relatively cheap if the 

Mesa (master): radeonsi: don' t allocate DCC for the temporary MSAA resolve surface

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 4be46c7d9dbeaff9dede941ee6518f68ad0c5f75
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4be46c7d9dbeaff9dede941ee6518f68ad0c5f75

Author: Marek Olšák 
Date:   Mon Jun  6 01:42:46 2016 +0200

radeonsi: don't allocate DCC for the temporary MSAA resolve surface

Allocating it has no effect, but it adds overhead (useless DCC clear).

Reviewed-by: Nicolai Hähnle 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
 src/gallium/drivers/radeon/r600_texture.c | 3 ++-
 src/gallium/drivers/radeonsi/si_blit.c| 3 ++-
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index a917549..bb090d6 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -48,6 +48,7 @@
 #define R600_RESOURCE_FLAG_TRANSFER(PIPE_RESOURCE_FLAG_DRV_PRIV << 
0)
 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH   (PIPE_RESOURCE_FLAG_DRV_PRIV << 
1)
 #define R600_RESOURCE_FLAG_FORCE_TILING
(PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
+#define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 
3)
 
 #define R600_CONTEXT_STREAMOUT_FLUSH   (1u << 0)
 /* Pipeline & streamout query controls. */
diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 9daad65..b0f375e 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -263,7 +263,8 @@ static int r600_init_surface(struct r600_common_screen 
*rscreen,
}
 
if (rscreen->chip_class >= VI &&
-   ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT)
+   (ptex->flags & R600_RESOURCE_FLAG_DISABLE_DCC ||
+ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT))
surface->flags |= RADEON_SURF_DISABLE_DCC;
 
if (ptex->bind & PIPE_BIND_SCANOUT) {
diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 2059d9d..dee3c2f 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -928,7 +928,8 @@ static bool do_hardware_msaa_resolve(struct pipe_context 
*ctx,
templ.depth0 = 1;
templ.array_size = 1;
templ.usage = PIPE_USAGE_DEFAULT;
-   templ.flags = R600_RESOURCE_FLAG_FORCE_TILING;
+   templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
+ R600_RESOURCE_FLAG_DISABLE_DCC;
 
tmp = ctx->screen->resource_create(ctx->screen, );
if (!tmp)

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Mesa (master): gallium/radeon: add an assertion checking the validity of PIPE_BIND_SCANOUT

[Marek Olšák]

Module: Mesa
Branch: master
Commit: a01536a29fdebfcdf7781e28a66b3b2abba943c8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a01536a29fdebfcdf7781e28a66b3b2abba943c8

Author: Marek Olšák 
Date:   Mon Jun  6 11:28:16 2016 +0200

gallium/radeon: add an assertion checking the validity of PIPE_BIND_SCANOUT

Reviewed-by: Nicolai Hähnle 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/gallium/drivers/radeon/r600_texture.c | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 0f72a6d..ca91c37 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -266,9 +266,6 @@ static int r600_init_surface(struct r600_common_screen 
*rscreen,
default:
return -EINVAL;
}
-   if (ptex->bind & PIPE_BIND_SCANOUT) {
-   surface->flags |= RADEON_SURF_SCANOUT;
-   }
 
if (!is_flushed_depth && is_depth) {
surface->flags |= RADEON_SURF_ZBUFFER;
@@ -286,6 +283,16 @@ static int r600_init_surface(struct r600_common_screen 
*rscreen,
ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT)
surface->flags |= RADEON_SURF_DISABLE_DCC;
 
+   if (ptex->bind & PIPE_BIND_SCANOUT) {
+   /* This should catch bugs in gallium users setting incorrect 
flags. */
+   assert(surface->nsamples == 1 &&
+  surface->array_size == 1 &&
+  surface->npix_z == 1 &&
+  surface->last_level == 0 &&
+  !(surface->flags & RADEON_SURF_Z_OR_SBUFFER));
+
+   surface->flags |= RADEON_SURF_SCANOUT;
+   }
return 0;
 }
 

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Mesa (master): radeonsi: allow direct hw MSAA resolve for scanout surfaces

[Marek Olšák]

Module: Mesa
Branch: master
Commit: ffd54d1936fcd07424265b780e1d049222a01e94
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ffd54d1936fcd07424265b780e1d049222a01e94

Author: Marek Olšák 
Date:   Sun Jun  5 17:43:43 2016 +0200

radeonsi: allow direct hw MSAA resolve for scanout surfaces

No idea why this was disabled, but it works fine.

Reviewed-by: Nicolai Hähnle 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/gallium/drivers/radeonsi/si_blit.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index dee3c2f..c28533e 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -902,7 +902,6 @@ static bool do_hardware_msaa_resolve(struct pipe_context 
*ctx,
info->src.box.height == dst_height &&
info->src.box.depth == 1 &&
dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
-   !(dst->surface.flags & RADEON_SURF_SCANOUT) &&
(!dst->cmask.size || !dst->dirty_level_mask) && /* dst cannot be 
fast-cleared */
!dst->dcc_offset) {
si_blitter_begin(ctx, SI_COLOR_RESOLVE |

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Mesa (master): gallium/radeon: move DCC clearing into a separate function

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 9a472a3e0b20923e9a42d362c6fad546c591f3d1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a472a3e0b20923e9a42d362c6fad546c591f3d1

Author: Marek Olšák 
Date:   Mon Jun  6 01:54:20 2016 +0200

gallium/radeon: move DCC clearing into a separate function

Reviewed-by: Nicolai Hähnle 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/gallium/drivers/radeon/r600_pipe_common.h |  3 +++
 src/gallium/drivers/radeon/r600_texture.c | 21 -
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index bb090d6..edfae95 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -675,6 +675,9 @@ struct pipe_surface *r600_create_surface_custom(struct 
pipe_context *pipe,
const struct pipe_surface 
*templ,
unsigned width, unsigned 
height);
 unsigned r600_translate_colorswap(enum pipe_format format, bool 
do_endian_swap);
+void vi_dcc_clear_level(struct r600_common_context *rctx,
+   struct r600_texture *rtex,
+   unsigned level, unsigned clear_value);
 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
   struct pipe_framebuffer_state *fb,
   struct r600_atom *fb_state,
diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index b0f375e..a1c314e 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1793,6 +1793,21 @@ static void vi_get_fast_clear_parameters(enum 
pipe_format surface_format,
*reset_value |= 0x40404040U;
 }
 
+void vi_dcc_clear_level(struct r600_common_context *rctx,
+   struct r600_texture *rtex,
+   unsigned level, unsigned clear_value)
+{
+   struct pipe_resource *dcc_buffer = >resource.b.b;
+   uint64_t dcc_offset = rtex->dcc_offset +
+ rtex->surface.level[level].dcc_offset;
+
+   assert(rtex->dcc_offset && rtex->surface.level[level].dcc_enabled);
+
+   rctx->clear_buffer(>b, dcc_buffer, dcc_offset,
+  rtex->surface.level[level].dcc_fast_clear_size,
+  clear_value, R600_COHERENCY_CB_META);
+}
+
 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
   struct pipe_framebuffer_state *fb,
   struct r600_atom *fb_state,
@@ -1867,11 +1882,7 @@ void evergreen_do_fast_color_clear(struct 
r600_common_context *rctx,
continue;
 
vi_get_fast_clear_parameters(fb->cbufs[i]->format, 
color, _value, _words_needed);
-
-   rctx->clear_buffer(>b, >resource.b.b,
-  tex->dcc_offset,
-  
tex->surface.level[0].dcc_fast_clear_size,
-  reset_value, R600_COHERENCY_CB_META);
+   vi_dcc_clear_level(rctx, tex, 0, reset_value);
 
if (clear_words_needed)
tex->dirty_level_mask |= 1 << 
fb->cbufs[i]->u.tex.level;

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Mesa (master): gallium/radeon: don' t allocate DCC for non-renderable texture formats

[Marek Olšák]

Module: Mesa
Branch: master
Commit: d4d733e39de2fc75aaa17d95998abdf19219cb38
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4d733e39de2fc75aaa17d95998abdf19219cb38

Author: Marek Olšák 
Date:   Mon Jun  6 01:29:14 2016 +0200

gallium/radeon: don't allocate DCC for non-renderable texture formats

R9G9B9E5 is the only uncompressed one hopefully.

This fixes incorrect rendering not discovered (due to a lack of tests)
until DCC mipmapping was enabled.

Cc: 11.1 11.2 12.0 
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/gallium/drivers/radeon/r600_texture.c  | 5 +
 src/gallium/drivers/radeon/radeon_winsys.h | 1 +
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 1 +
 3 files changed, 7 insertions(+)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 920cc21..0f72a6d 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -281,6 +281,11 @@ static int r600_init_surface(struct r600_common_screen 
*rscreen,
if (rscreen->chip_class >= SI) {
surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
}
+
+   if (rscreen->chip_class >= VI &&
+   ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT)
+   surface->flags |= RADEON_SURF_DISABLE_DCC;
+
return 0;
 }
 
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index 806ea63..a0c7abf 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -342,6 +342,7 @@ enum radeon_feature_id {
 #define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
 #define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
 #define RADEON_SURF_FMASK   (1 << 21)
+#define RADEON_SURF_DISABLE_DCC (1 << 22)
 
 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) 
& RADEON_SURF_ ## field ## _MASK)
 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << 
RADEON_SURF_ ## field ## _SHIFT)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index d68c688..f609bf4 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -343,6 +343,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
AddrSurfInfoIn.flags.degrade4Space = 1;
AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & 
RADEON_SURF_Z_OR_SBUFFER) &&
 !(surf->flags & RADEON_SURF_SCANOUT) &&
+!(surf->flags & 
RADEON_SURF_DISABLE_DCC) &&
 !compressed && AddrDccIn.numSamples <= 
1;
 
AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;

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Mesa (master): gallium/radeon: don't disable DCC because of SDMA

[Marek Olšák]

Module: Mesa
Branch: master
Commit: c65361763cca709a28534aa354b6dffe1cbadf99
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c65361763cca709a28534aa354b6dffe1cbadf99

Author: Marek Olšák 
Date:   Sun Jun  5 15:45:30 2016 +0200

gallium/radeon: don't disable DCC because of SDMA

We want to keep DCC enabled to save bandwidth. It was a bad idea to disable
it here.

Reviewed-by: Nicolai Hähnle 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/gallium/drivers/radeon/r600_texture.c | 23 +++
 1 file changed, 3 insertions(+), 20 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index b276417..27b464f 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -32,8 +32,6 @@
 #include 
 #include 
 
-static bool r600_texture_discard_dcc(struct r600_common_screen *rscreen,
-struct r600_texture *rtex);
 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
   struct r600_texture *rtex);
 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
@@ -69,27 +67,12 @@ bool r600_prepare_for_dma_blit(struct r600_common_context 
*rctx,
 
/* DCC as:
 *   src: Use the 3D path. DCC decompression is expensive.
-*   dst: If overwriting the whole texture, discard DCC and use SDMA.
-*Otherwise, use the 3D path.
+*   dst: Use the 3D path to compress the pixels with DCC.
 */
-   if (rsrc->dcc_offset && rsrc->surface.level[src_level].dcc_enabled)
+   if ((rsrc->dcc_offset && rsrc->surface.level[src_level].dcc_enabled) ||
+   (rdst->dcc_offset && rdst->surface.level[dst_level].dcc_enabled))
return false;
 
-   if (rdst->dcc_offset && rdst->surface.level[dst_level].dcc_enabled) {
-   /* We can't discard DCC if the texture has been exported.
-* We can only discard DCC for the entire texture.
-*/
-   if (rdst->resource.is_shared ||
-   rdst->resource.b.b.last_level > 0 ||
-   !util_texrange_covers_whole_level(>resource.b.b, 
dst_level,
- dstx, dsty, dstz, 
src_box->width,
- src_box->height, 
src_box->depth))
-   return false;
-
-   if (!r600_texture_discard_dcc(rctx->screen, rdst))
-   return false;
-   }
-
/* CMASK as:
 *   src: Both texture and SDMA paths need decompression. Use SDMA.
 *   dst: If overwriting the whole texture, discard CMASK and use

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Mesa (master): radeonsi: compute DCC register parameters in si_emit_framebuffer_state

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 60e93ddd0675e525333ae928e94be31b973409de
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=60e93ddd0675e525333ae928e94be31b973409de

Author: Marek Olšák 
Date:   Fri Jun  3 19:56:38 2016 +0200

radeonsi: compute DCC register parameters in si_emit_framebuffer_state

This will get more complicated with mipmapped DCC or when DCC is enabled
after allocation.

Reviewed-by: Nicolai Hähnle 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/gallium/drivers/radeon/r600_pipe_common.h |  1 -
 src/gallium/drivers/radeon/r600_texture.c |  2 --
 src/gallium/drivers/radeon/r600d_common.h |  1 -
 src/gallium/drivers/radeonsi/si_state.c   | 22 --
 4 files changed, 12 insertions(+), 14 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index fd658b6..a917549 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -288,7 +288,6 @@ struct r600_surface {
unsigned cb_color_dim;  /* EG only */
unsigned cb_color_pitch;/* EG and later */
unsigned cb_color_slice;/* EG and later */
-   unsigned cb_dcc_base;   /* VI and later */
unsigned cb_color_attrib;   /* EG and later */
unsigned cb_dcc_control;/* VI and later */
unsigned cb_color_fmask;/* CB_COLORn_FMASK (EG and later) or 
CB_COLORn_FRAG (r600) */
diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index ca91c37..37f8e02 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -405,7 +405,6 @@ static bool r600_texture_discard_dcc(struct 
r600_common_screen *rscreen,
 
/* Disable DCC. */
rtex->dcc_offset = 0;
-   rtex->cb_color_info &= ~VI_S_028C70_DCC_ENABLE(1);
 
/* Notify all contexts about the change. */
r600_dirty_all_framebuffer_states(rscreen);
@@ -1056,7 +1055,6 @@ r600_texture_create_object(struct pipe_screen *screen,
/* Reserve space for the DCC buffer. */
rtex->dcc_offset = align64(rtex->size, 
rtex->surface.dcc_alignment);
rtex->size = rtex->dcc_offset + rtex->surface.dcc_size;
-   rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
}
}
 
diff --git a/src/gallium/drivers/radeon/r600d_common.h 
b/src/gallium/drivers/radeon/r600d_common.h
index fd9d79e..e50de96 100644
--- a/src/gallium/drivers/radeon/r600d_common.h
+++ b/src/gallium/drivers/radeon/r600d_common.h
@@ -216,7 +216,6 @@
 
 #define   EG_S_028C70_FAST_CLEAR(x)   (((unsigned)(x) & 
0x1) << 17)
 #define   SI_S_028C70_FAST_CLEAR(x)   (((unsigned)(x) & 
0x1) << 13)
-#define   VI_S_028C70_DCC_ENABLE(x)   (((unsigned)(x) & 
0x1) << 28)
 
 /*CIK+*/
 #define R_0300FC_CP_STRMOUT_CNTL0x0300FC
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 6c879f3..9433a2b 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1958,7 +1958,6 @@ static void si_initialize_color_surface(struct si_context 
*sctx,
struct r600_surface *surf)
 {
struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
-   unsigned level = surf->base.u.tex.level;
unsigned color_info, color_attrib, color_view;
unsigned format, swap, ntype, endian;
const struct util_format_description *desc;
@@ -2058,7 +2057,7 @@ static void si_initialize_color_surface(struct si_context 
*sctx,
surf->cb_color_info = color_info;
surf->cb_color_attrib = color_attrib;
 
-   if (sctx->b.chip_class >= VI && rtex->dcc_offset) {
+   if (sctx->b.chip_class >= VI) {
unsigned max_uncompressed_block_size = 2;
 
if (rtex->surface.nsamples > 1) {
@@ -2070,9 +2069,6 @@ static void si_initialize_color_surface(struct si_context 
*sctx,
 
surf->cb_dcc_control = 
S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
   S_028C78_INDEPENDENT_64B_BLOCKS(1);
-   surf->cb_dcc_base = (rtex->resource.gpu_address +
-rtex->dcc_offset +
-rtex->surface.level[level].dcc_offset) >> 
8;
}
 
/* This must be set for fast clear to work without FMASK. */
@@ -2388,6 +2384,7 @@ static void si_emit_framebuffer_state(struct si_context 
*sctx, struct r600_atom
unsigned i, nr_cbufs = state->nr_cbufs;
struct r600_texture *tex = NULL;
struct r600_surface *cb = NULL;
+   unsigned cb_color_info = 0;
 
   

Mesa (master): radeonsi: don' t flag renderbuffer feedback loop if DCC has just been disabled

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 2fd74a05bb1a53f2edbc2df3f7e77f84c630ac5f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2fd74a05bb1a53f2edbc2df3f7e77f84c630ac5f

Author: Marek Olšák 
Date:   Fri Jun  3 20:51:47 2016 +0200

radeonsi: don't flag renderbuffer feedback loop if DCC has just been disabled

Reviewed-by: Nicolai Hähnle 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/gallium/drivers/radeonsi/si_descriptors.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index b2c3713..e0c9666 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -606,7 +606,9 @@ static void si_set_shader_image(struct si_context *ctx,
 * The decompression is relatively cheap if the surface
 * has been decompressed already.
 */
-   if (!r600_texture_disable_dcc(>b, tex))
+   if (r600_texture_disable_dcc(>b, tex))
+   uses_dcc = false;
+   else
ctx->b.decompress_dcc(>b.b, tex);
}
 
@@ -616,7 +618,7 @@ static void si_set_shader_image(struct si_context *ctx,
images->compressed_colortex_mask &= ~(1 << slot);
}
 
-   if (tex->dcc_offset &&
+   if (uses_dcc &&
p_atomic_read(>framebuffers_bound))
ctx->need_check_render_feedback = true;
 

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Mesa (master): tgsi/scan: add uses_derivatives (v2)

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: d3a584defec988faa09960adea90545399440827
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d3a584defec988faa09960adea90545399440827

Author: Nicolai Hähnle 
Date:   Wed Jun  1 13:17:29 2016 +0200

tgsi/scan: add uses_derivatives (v2)

v2:
- TG4 does not calculate derivatives (Ilia)
- also handle SAMPLE* instructions (Roland)

Cc: 12.0 
Reviewed-by: Marek Olšák  (v1)
Reviewed-by: Brian Paul  (v1)
Reviewed-by: Ilia Mirkin 
Reviewed-by: Roland Scheidegger 

---

 src/gallium/auxiliary/tgsi/tgsi_scan.c | 30 ++
 src/gallium/auxiliary/tgsi/tgsi_scan.h |  1 +
 2 files changed, 31 insertions(+)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c 
b/src/gallium/auxiliary/tgsi/tgsi_scan.c
index 1baf031..98d86fc 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
@@ -68,6 +68,33 @@ is_texture_inst(unsigned opcode)
tgsi_get_opcode_info(opcode)->is_tex);
 }
 
+
+/**
+ * Is the opcode an instruction which computes a derivative explicitly or
+ * implicitly?
+ */
+static bool
+computes_derivative(unsigned opcode)
+{
+   if (tgsi_get_opcode_info(opcode)->is_tex) {
+  return opcode != TGSI_OPCODE_TG4 &&
+ opcode != TGSI_OPCODE_TXD &&
+ opcode != TGSI_OPCODE_TXF &&
+ opcode != TGSI_OPCODE_TXL &&
+ opcode != TGSI_OPCODE_TXL2 &&
+ opcode != TGSI_OPCODE_TXQ &&
+ opcode != TGSI_OPCODE_TXQ_LZ &&
+ opcode != TGSI_OPCODE_TXQS;
+   }
+
+   return opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE ||
+  opcode == TGSI_OPCODE_DDY || opcode == TGSI_OPCODE_DDY_FINE ||
+  opcode == TGSI_OPCODE_SAMPLE ||
+  opcode == TGSI_OPCODE_SAMPLE_B ||
+  opcode == TGSI_OPCODE_SAMPLE_C;
+}
+
+
 static void
 scan_instruction(struct tgsi_shader_info *info,
  const struct tgsi_full_instruction *fullinst,
@@ -263,6 +290,9 @@ scan_instruction(struct tgsi_shader_info *info,
if (is_mem_inst)
   info->num_memory_instructions++;
 
+   if (computes_derivative(fullinst->Instruction.Opcode))
+  info->uses_derivatives = true;
+
info->num_instructions++;
 }
  
diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.h 
b/src/gallium/auxiliary/tgsi/tgsi_scan.h
index 31adce7..f7eefa4 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.h
@@ -115,6 +115,7 @@ struct tgsi_shader_info
boolean writes_memory; /**< contains stores or atomics to buffers or images 
*/
boolean is_msaa_sampler[PIPE_MAX_SAMPLERS];
boolean uses_doubles; /**< uses any of the double instructions */
+   boolean uses_derivatives;
unsigned clipdist_writemask;
unsigned culldist_writemask;
unsigned num_written_culldistance;

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Mesa (master): radeonsi: enable WQM in PS prolog when needed

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: b42bc90b6add0d0f81d915d49712761d32329afa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b42bc90b6add0d0f81d915d49712761d32329afa

Author: Nicolai Hähnle 
Date:   Wed Jun  1 13:24:19 2016 +0200

radeonsi: enable WQM in PS prolog when needed

WQM is needed when the PS prolog computes a VGPR that is consumed by a shader
with (implicit or explicit) derivatives.

Depends on http://reviews.llvm.org/D20839 / LLVM r272063 for this to be
effective (otherwise it's just a no-op).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95130
Cc: 12.0 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_shader.c | 9 +
 src/gallium/drivers/radeonsi/si_shader.h | 1 +
 2 files changed, 10 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 5e5bf68..6e8eefb 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -7197,6 +7197,12 @@ static bool si_compile_ps_prolog(struct si_screen 
*sscreen,
   linear_sample[i], base + 10 
+ i, "");
}
 
+   /* Tell LLVM to insert WQM instruction sequence when needed. */
+   if (key->ps_prolog.wqm) {
+   LLVMAddTargetDependentFunctionAttr(func,
+  "amdgpu-ps-wqm-outputs", "");
+   }
+
/* Compile. */
LLVMBuildRet(gallivm->builder, ret);
radeon_llvm_finalize_module(_bld);
@@ -7347,6 +7353,9 @@ static bool si_shader_select_ps_parts(struct si_screen 
*sscreen,
prolog_key.ps_prolog.colors_read = info->colors_read;
prolog_key.ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
prolog_key.ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
+   prolog_key.ps_prolog.wqm = info->uses_derivatives &&
+   (prolog_key.ps_prolog.colors_read ||
+prolog_key.ps_prolog.states.force_persample_interp);
 
if (info->colors_read) {
unsigned *color = shader->selector->color_attr_index;
diff --git a/src/gallium/drivers/radeonsi/si_shader.h 
b/src/gallium/drivers/radeonsi/si_shader.h
index 9425b1e..e16bc9c 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -355,6 +355,7 @@ union si_shader_part_key {
unsignedcolors_read:8; /* color input components read */
unsignednum_interp_inputs:5; /* BCOLOR is at this 
location */
unsignedface_vgpr_index:5;
+   unsignedwqm:1;
charcolor_attr_index[2];
charcolor_interp_vgpr_index[2]; /* -1 == constant */
} ps_prolog;

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Mesa (master): docs/devinfo: Add closing paragraph tag

[Nanley Chery]

Module: Mesa
Branch: master
Commit: 26b0f023d749e92800804f650fe065d5a32d4edd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=26b0f023d749e92800804f650fe065d5a32d4edd

Author: Nanley Chery 
Date:   Fri Jun  3 10:56:46 2016 -0700

docs/devinfo: Add closing paragraph tag

Signed-off-by: Nanley Chery 
Reviewed-by: Ian Romanick 

---

 docs/devinfo.html | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/devinfo.html b/docs/devinfo.html
index 8ebf80f..70141ae 100644
--- a/docs/devinfo.html
+++ b/docs/devinfo.html
@@ -703,6 +703,7 @@ To add a new GL extension to Mesa you have to do at least 
the following.
tests are run using 'make check'
 
 
+
 
 
 

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Mesa (master): docs/devinfo: Update bullet in stale extension guide

[Nanley Chery]

Module: Mesa
Branch: master
Commit: 9e7de50cab78d1144f49688506353c78e1349ae3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e7de50cab78d1144f49688506353c78e1349ae3

Author: Nanley Chery 
Date:   Fri Jun  3 10:58:05 2016 -0700

docs/devinfo: Update bullet in stale extension guide

Signed-off-by: Nanley Chery 
Reviewed-by: Ian Romanick 

---

 docs/devinfo.html | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/devinfo.html b/docs/devinfo.html
index 70141ae..f5d23ab 100644
--- a/docs/devinfo.html
+++ b/docs/devinfo.html
@@ -686,7 +686,7 @@ To add a new GL extension to Mesa you have to do at least 
the following.
Add a new entry to the gl_extensions struct in mtypes.h
 
 
-   Update the extensions.c file.
+   Add a new entry to the src/mesa/main/extensions_table.h file.
 
 
From this point, the best way to proceed is to find another extension,

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Mesa (master): docs/devinfo: Expound on helpful extension tips

[Nanley Chery]

Module: Mesa
Branch: master
Commit: b7a0c0ec7f5626bbec4904e6754f27087120ec54
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7a0c0ec7f5626bbec4904e6754f27087120ec54

Author: Nanley Chery 
Date:   Fri Jun  3 10:59:18 2016 -0700

docs/devinfo: Expound on helpful extension tips

Signed-off-by: Nanley Chery 
Reviewed-by: Ian Romanick 

---

 docs/devinfo.html | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/docs/devinfo.html b/docs/devinfo.html
index f5d23ab..489d263 100644
--- a/docs/devinfo.html
+++ b/docs/devinfo.html
@@ -684,6 +684,8 @@ To add a new GL extension to Mesa you have to do at least 
the following.
 
 
Add a new entry to the gl_extensions struct in mtypes.h
+   if the extension requires driver capabilities not already exposed by
+   another extension.
 
 
Add a new entry to the src/mesa/main/extensions_table.h file.
@@ -698,6 +700,11 @@ To add a new GL extension to Mesa you have to do at least 
the following.
and attrib.c will most likely require new code.
 
 
+   To determine if the new extension is active in the current context,
+   use the auto-generated _mesa_has_##name_str() function defined in
+   src/mesa/main/extensions.h.
+
+
The dispatch tests check_table.cpp and dispatch_sanity.cpp
should be updated with details about the new extensions functions. These
tests are run using 'make check'

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Mesa (master): swr: fix provoking vertex

[Tim Rowley]

Module: Mesa
Branch: master
Commit: 87f0a0448fba898a7ab2a36eed9682ff8c1c6d5c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=87f0a0448fba898a7ab2a36eed9682ff8c1c6d5c

Author: Tim Rowley 
Date:   Wed Jun  1 09:56:26 2016 -0500

swr: fix provoking vertex

Use rasterizer provoking vertex API.

Fix rasterizer provoking vertex for tristrips and quad list/strips.

v2: make provoking vertex tables static const

Reviewed-by: Bruce Cherniak 

---

 .../drivers/swr/rasterizer/core/frontend.cpp   | 38 --
 src/gallium/drivers/swr/swr_draw.cpp   | 30 +
 src/gallium/drivers/swr/swr_screen.cpp |  2 +-
 src/gallium/drivers/swr/swr_shader.cpp | 12 +++
 src/gallium/drivers/swr/swr_shader.h   |  1 -
 src/gallium/drivers/swr/swr_state.cpp  |  5 ++-
 src/gallium/drivers/swr/swr_state.h|  1 +
 7 files changed, 77 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp 
b/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
index ef90a24..6e1bc0e 100644
--- a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
@@ -1467,6 +1467,7 @@ INLINE void ProcessAttributes(
 uint32_t mapIdx = 0;
 LONG constantInterpMask = 
pDC->pState->state.backendState.constantInterpolationMask;
 const uint32_t provokingVertex = 
pDC->pState->state.frontendState.topologyProvokingVertex;
+const PRIMITIVE_TOPOLOGY topo = pDC->pState->state.topology;
 
 while (_BitScanForward(, linkageMask))
 {
@@ -1476,18 +1477,51 @@ INLINE void ProcessAttributes(
 uint32_t inputSlot = VERTEX_ATTRIB_START_SLOT + pLinkageMap[mapIdx];
 
 __m128 attrib[3];// triangle attribs (always 4 wide)
-pa.AssembleSingle(inputSlot, triIndex, attrib);
 
 if (_bittest(, mapIdx))
 {
+uint32_t vid;
+static const uint32_t tristripProvokingVertex[] = {0, 2, 1};
+static const int32_t quadProvokingTri[2][4] = {{0, 0, 0, 1}, {0, 
-1, 0, 0}};
+static const uint32_t quadProvokingVertex[2][4] = {{0, 1, 2, 2}, 
{0, 1, 1, 2}};
+static const int32_t qstripProvokingTri[2][4] = {{0, 0, 0, 1}, 
{-1, 0, 0, 0}};
+static const uint32_t qstripProvokingVertex[2][4] = {{0, 1, 2, 1}, 
{0, 0, 2, 1}};
+
+switch (topo) {
+case TOP_QUAD_LIST:
+pa.AssembleSingle(inputSlot,
+  triIndex + quadProvokingTri[triIndex & 
1][provokingVertex],
+  attrib);
+vid = quadProvokingVertex[triIndex & 1][provokingVertex];
+break;
+case TOP_QUAD_STRIP:
+pa.AssembleSingle(inputSlot,
+  triIndex + qstripProvokingTri[triIndex & 
1][provokingVertex],
+  attrib);
+vid = qstripProvokingVertex[triIndex & 1][provokingVertex];
+break;
+case TOP_TRIANGLE_STRIP:
+   pa.AssembleSingle(inputSlot, triIndex, attrib);
+   vid = (triIndex & 1)
+   ? tristripProvokingVertex[provokingVertex]
+   : provokingVertex;
+   break;
+default:
+pa.AssembleSingle(inputSlot, triIndex, attrib);
+vid = provokingVertex;
+break;
+}
+
 for (uint32_t i = 0; i < NumVerts; ++i)
 {
-_mm_store_ps(pBuffer, attrib[provokingVertex]);
+_mm_store_ps(pBuffer, attrib[vid]);
 pBuffer += 4;
 }
 }
 else
 {
+pa.AssembleSingle(inputSlot, triIndex, attrib);
+
 for (uint32_t i = 0; i < NumVerts; ++i)
 {
 _mm_store_ps(pBuffer, attrib[i]);
diff --git a/src/gallium/drivers/swr/swr_draw.cpp 
b/src/gallium/drivers/swr/swr_draw.cpp
index 7a4c896..ab8d275 100644
--- a/src/gallium/drivers/swr/swr_draw.cpp
+++ b/src/gallium/drivers/swr/swr_draw.cpp
@@ -162,6 +162,36 @@ swr_draw_vbo(struct pipe_context *pipe, const struct 
pipe_draw_info *info)
/* Set up frontend state
 * XXX setup provokingVertex & topologyProvokingVertex */
SWR_FRONTEND_STATE feState = {0};
+   if (ctx->rasterizer->flatshade_first) {
+  feState.provokingVertex = {1, 0, 0};
+   } else {
+  feState.provokingVertex = {2, 1, 2};
+   }
+
+   switch (info->mode) {
+   case PIPE_PRIM_TRIANGLE_FAN:
+  feState.topologyProvokingVertex = feState.provokingVertex.triFan;
+  break;
+   case PIPE_PRIM_TRIANGLE_STRIP:
+   case PIPE_PRIM_TRIANGLES:
+  feState.topologyProvokingVertex = feState.provokingVertex.triStripList;
+  break;
+   case PIPE_PRIM_QUAD_STRIP:
+   case PIPE_PRIM_QUADS:
+  if (ctx->rasterizer->flatshade_first)

Mesa (master): gk104/ir: fix conditions for adding a texbar

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 71ad8a173f5c64d6384c13f04361455571c42ffe
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=71ad8a173f5c64d6384c13f04361455571c42ffe

Author: Ilia Mirkin 
Date:   Mon Jun  6 21:25:05 2016 -0400

gk104/ir: fix conditions for adding a texbar

Sometimes a register source can actually be double- or even quad-wide.
We must make sure that the inserted texbars take that width into
account.

Based on an earlier patch by Samuel Pitoiset.

Signed-off-by: Ilia Mirkin 
Reviewed-by: Samuel Pitoiset 
Cc: "12.0 11.2" 

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 689fecf..cb82216 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -227,18 +227,20 @@ NVC0LegalizePostRA::findFirstUsesBB(
  continue;
 
   for (int d = 0; insn->defExists(d); ++d) {
+ const Value *def = insn->def(d).rep();
  if (insn->def(d).getFile() != FILE_GPR ||
- insn->def(d).rep()->reg.data.id < minGPR ||
- insn->def(d).rep()->reg.data.id > maxGPR)
+ def->reg.data.id + def->reg.size / 4 - 1 < minGPR ||
+ def->reg.data.id > maxGPR)
 continue;
  addTexUse(uses, insn, texi);
  return;
   }
 
   for (int s = 0; insn->srcExists(s); ++s) {
+ const Value *src = insn->src(s).rep();
  if (insn->src(s).getFile() != FILE_GPR ||
- insn->src(s).rep()->reg.data.id < minGPR ||
- insn->src(s).rep()->reg.data.id > maxGPR)
+ src->reg.data.id + src->reg.size / 4 - 1 < minGPR ||
+ src->reg.data.id > maxGPR)
 continue;
  addTexUse(uses, insn, texi);
  return;

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Mesa (master): st/mesa: revalidate image atoms when a texture is updated

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: c81b090c920f90bf86a34c978e10ff336d1edbc0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c81b090c920f90bf86a34c978e10ff336d1edbc0

Author: Ilia Mirkin 
Date:   Sat Jun  4 13:25:35 2016 -0400

st/mesa: revalidate image atoms when a texture is updated

A texture may be redefined with _NEW_TEXTURE, which might have been
bound to a shader image slot. We have to revalidate the image atoms to
pick up on the new resource.

Signed-off-by: Ilia Mirkin 
Reviewed-by: Nicolai Hähnle 
Cc: "12.0" 

---

 src/mesa/state_tracker/st_atom_image.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mesa/state_tracker/st_atom_image.c 
b/src/mesa/state_tracker/st_atom_image.c
index 9b8f505..f8a0044 100644
--- a/src/mesa/state_tracker/st_atom_image.c
+++ b/src/mesa/state_tracker/st_atom_image.c
@@ -148,7 +148,7 @@ static void bind_vs_images(struct st_context *st)
 const struct st_tracked_state st_bind_vs_images = {
"st_bind_vs_images",
{
-  0,
+  _NEW_TEXTURE,
   ST_NEW_VERTEX_PROGRAM | ST_NEW_IMAGE_UNITS,
},
bind_vs_images
@@ -168,7 +168,7 @@ static void bind_fs_images(struct st_context *st)
 const struct st_tracked_state st_bind_fs_images = {
"st_bind_fs_images",
{
-  0,
+  _NEW_TEXTURE,
   ST_NEW_FRAGMENT_PROGRAM | ST_NEW_IMAGE_UNITS,
},
bind_fs_images
@@ -188,7 +188,7 @@ static void bind_gs_images(struct st_context *st)
 const struct st_tracked_state st_bind_gs_images = {
"st_bind_gs_images",
{
-  0,
+  _NEW_TEXTURE,
   ST_NEW_GEOMETRY_PROGRAM | ST_NEW_IMAGE_UNITS,
},
bind_gs_images
@@ -208,7 +208,7 @@ static void bind_tcs_images(struct st_context *st)
 const struct st_tracked_state st_bind_tcs_images = {
"st_bind_tcs_images",
{
-  0,
+  _NEW_TEXTURE,
   ST_NEW_TESSCTRL_PROGRAM | ST_NEW_IMAGE_UNITS,
},
bind_tcs_images
@@ -228,7 +228,7 @@ static void bind_tes_images(struct st_context *st)
 const struct st_tracked_state st_bind_tes_images = {
"st_bind_tes_images",
{
-  0,
+  _NEW_TEXTURE,
   ST_NEW_TESSEVAL_PROGRAM | ST_NEW_IMAGE_UNITS,
},
bind_tes_images
@@ -248,7 +248,7 @@ static void bind_cs_images(struct st_context *st)
 const struct st_tracked_state st_bind_cs_images = {
"st_bind_cs_images",
{
-  0,
+  _NEW_TEXTURE,
   ST_NEW_COMPUTE_PROGRAM | ST_NEW_IMAGE_UNITS,
},
bind_cs_images

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Mesa (master): radeonsi: add si_set_rw_buffer to be used for internal descriptors

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: ba4a2840c7fb52169400420fd94c655b2b229f7e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba4a2840c7fb52169400420fd94c655b2b229f7e

Author: Nicolai Hähnle 
Date:   Fri Jun  3 15:27:09 2016 +0200

radeonsi: add si_set_rw_buffer to be used for internal descriptors

So that callers outside of si_descriptors.c need to worry less about the
details of descriptor handling.

Reviewed-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_descriptors.c | 15 ++-
 src/gallium/drivers/radeonsi/si_state.c   |  9 +++--
 src/gallium/drivers/radeonsi/si_state.h   |  5 ++---
 3 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index bea7515..24fccbf 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -872,9 +872,9 @@ void si_upload_const_buffer(struct si_context *sctx, struct 
r600_resource **rbuf
util_memcpy_cpu_to_le32(tmp, ptr, size);
 }
 
-void si_set_constant_buffer(struct si_context *sctx,
-   struct si_buffer_resources *buffers,
-   uint slot, struct pipe_constant_buffer *input)
+static void si_set_constant_buffer(struct si_context *sctx,
+  struct si_buffer_resources *buffers,
+  uint slot, struct pipe_constant_buffer 
*input)
 {
assert(slot < buffers->desc.num_elements);
pipe_resource_reference(>buffers[slot], NULL);
@@ -934,6 +934,12 @@ void si_set_constant_buffer(struct si_context *sctx,
buffers->desc.dirty_mask |= 1u << slot;
 }
 
+void si_set_rw_buffer(struct si_context *sctx,
+ uint slot, struct pipe_constant_buffer *input)
+{
+   si_set_constant_buffer(sctx, >rw_buffers, slot, input);
+}
+
 static void si_pipe_set_constant_buffer(struct pipe_context *ctx,
uint shader, uint slot,
struct pipe_constant_buffer *input)
@@ -1230,8 +1236,7 @@ static void si_set_polygon_stipple(struct pipe_context 
*ctx,
cb.user_buffer = stipple;
cb.buffer_size = sizeof(stipple);
 
-   si_set_constant_buffer(sctx, >rw_buffers,
-  SI_PS_CONST_POLY_STIPPLE, );
+   si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, );
 }
 
 /* TEXTURE METADATA ENABLE/DISABLE */
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index e506ec9..6c879f3 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -620,8 +620,7 @@ static void si_set_clip_state(struct pipe_context *ctx,
cb.user_buffer = state->ucp;
cb.buffer_offset = 0;
cb.buffer_size = 4*4*8;
-   si_set_constant_buffer(sctx, >rw_buffers,
-  SI_VS_CONST_CLIP_PLANES, );
+   si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, );
pipe_resource_reference(, NULL);
 }
 
@@ -2363,8 +2362,7 @@ static void si_set_framebuffer_state(struct pipe_context 
*ctx,
assert(0);
}
constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
-   si_set_constant_buffer(sctx, >rw_buffers,
-  SI_PS_CONST_SAMPLE_POSITIONS, );
+   si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, );
 
/* Smoothing (only possible with nr_samples == 1) uses the same
 * sample locations as the MSAA it simulates.
@@ -3244,8 +3242,7 @@ static void si_set_tess_state(struct pipe_context *ctx,
   (void*)array, sizeof(array),
   _offset);
 
-   si_set_constant_buffer(sctx, >rw_buffers,
-  SI_HS_CONST_DEFAULT_TESS_LEVELS, );
+   si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, );
pipe_resource_reference(, NULL);
 }
 
diff --git a/src/gallium/drivers/radeonsi/si_state.h 
b/src/gallium/drivers/radeonsi/si_state.h
index d12d383..52ca593 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -276,9 +276,8 @@ void si_update_compressed_colortex_masks(struct si_context 
*sctx);
 void si_emit_graphics_shader_userdata(struct si_context *sctx,
   struct r600_atom *atom);
 void si_emit_compute_shader_userdata(struct si_context *sctx);
-void si_set_constant_buffer(struct si_context *sctx,
-   struct si_buffer_resources *buffers,
-   uint slot, struct pipe_constant_buffer *input);
+void si_set_rw_buffer(struct si_context *sctx,
+ uint slot, struct pipe_constant_buffer 

Mesa (master): radeonsi: move descriptor set begin_new_cs handling into a separate function

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: c32cd4b78dba16abae5e4cb9ed96d58a2578401c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c32cd4b78dba16abae5e4cb9ed96d58a2578401c

Author: Nicolai Hähnle 
Date:   Fri Jun  3 14:50:42 2016 +0200

radeonsi: move descriptor set begin_new_cs handling into a separate function

Reviewed-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_descriptors.c | 36 +++
 1 file changed, 15 insertions(+), 21 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index f51ebd2..0065ac5 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -249,6 +249,18 @@ static bool si_upload_descriptors(struct si_context *sctx,
return true;
 }
 
+static void
+si_descriptors_begin_new_cs(struct si_context *sctx, struct si_descriptors 
*desc)
+{
+   desc->ce_ram_dirty = true;
+
+   if (!desc->buffer)
+   return;
+
+   radeon_add_to_buffer_list(>b, >b.gfx, desc->buffer,
+ RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
+}
+
 /* SAMPLER VIEWS */
 
 static void si_release_sampler_views(struct si_sampler_views *views)
@@ -287,12 +299,7 @@ static void si_sampler_views_begin_new_cs(struct 
si_context *sctx,
   RADEON_USAGE_READ);
}
 
-   views->desc.ce_ram_dirty = true;
-
-   if (!views->desc.buffer)
-   return;
-   radeon_add_to_buffer_list(>b, >b.gfx, views->desc.buffer,
- RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS);
+   si_descriptors_begin_new_cs(sctx, >desc);
 }
 
 void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
@@ -489,14 +496,7 @@ si_image_views_begin_new_cs(struct si_context *sctx, 
struct si_images_info *imag
   RADEON_USAGE_READWRITE);
}
 
-   images->desc.ce_ram_dirty = true;
-
-   if (images->desc.buffer) {
-   radeon_add_to_buffer_list(>b, >b.gfx,
- images->desc.buffer,
- RADEON_USAGE_READ,
- RADEON_PRIO_DESCRIPTORS);
-   }
+   si_descriptors_begin_new_cs(sctx, >desc);
 }
 
 static void
@@ -743,13 +743,7 @@ static void si_buffer_resources_begin_new_cs(struct 
si_context *sctx,
  buffers->shader_usage, buffers->priority);
}
 
-   buffers->desc.ce_ram_dirty = true;
-
-   if (!buffers->desc.buffer)
-   return;
-   radeon_add_to_buffer_list(>b, >b.gfx,
- buffers->desc.buffer, RADEON_USAGE_READWRITE,
- RADEON_PRIO_DESCRIPTORS);
+   si_descriptors_begin_new_cs(sctx, >desc);
 }
 
 /* VERTEX BUFFERS */

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Mesa (master): radeonsi: access descriptor sets via local variables

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 4e0fb727868103ef875d6bff40269192388d82f0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e0fb727868103ef875d6bff40269192388d82f0

Author: Nicolai Hähnle 
Date:   Fri Jun  3 15:14:39 2016 +0200

radeonsi: access descriptor sets via local variables

This will simplify moving them to a per-context array.

Reviewed-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_descriptors.c | 72 +++
 1 file changed, 41 insertions(+), 31 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 24fccbf..23e98f7 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -336,13 +336,14 @@ static void si_set_sampler_view(struct si_context *sctx,
 {
struct si_sampler_views *views = >samplers[shader].views;
struct si_sampler_view *rview = (struct si_sampler_view*)view;
+   struct si_descriptors *descs = >desc;
 
if (views->views[slot] == view && !disallow_early_out)
return;
 
if (view) {
struct r600_texture *rtex = (struct r600_texture 
*)view->texture;
-   uint32_t *desc = views->desc.list + slot * 16;
+   uint32_t *desc = descs->list + slot * 16;
 
si_sampler_view_add_buffer(sctx, view->texture,
   RADEON_USAGE_READ);
@@ -380,13 +381,13 @@ static void si_set_sampler_view(struct si_context *sctx,
views->enabled_mask |= 1u << slot;
} else {
pipe_sampler_view_reference(>views[slot], NULL);
-   memcpy(views->desc.list + slot*16, null_texture_descriptor, 
8*4);
+   memcpy(descs->list + slot*16, null_texture_descriptor, 8*4);
/* Only clear the lower dwords of FMASK. */
-   memcpy(views->desc.list + slot*16 + 8, null_texture_descriptor, 
4*4);
+   memcpy(descs->list + slot*16 + 8, null_texture_descriptor, 4*4);
views->enabled_mask &= ~(1u << slot);
}
 
-   views->desc.dirty_mask |= 1u << slot;
+   descs->dirty_mask |= 1u << slot;
 }
 
 static bool is_compressed_colortex(struct r600_texture *rtex)
@@ -536,6 +537,7 @@ static void si_set_shader_image(struct si_context *ctx,
 {
struct si_screen *screen = ctx->screen;
struct si_images_info *images = >images[shader];
+   struct si_descriptors *descs = >desc;
struct r600_resource *res;
 
if (!view || !view->resource) {
@@ -559,14 +561,14 @@ static void si_set_shader_image(struct si_context *ctx,
  view->format,
  view->u.buf.first_element,
  view->u.buf.last_element,
- images->desc.list + slot * 8);
+ descs->list + slot * 8);
images->compressed_colortex_mask &= ~(1 << slot);
} else {
static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
struct r600_texture *tex = (struct r600_texture *)res;
unsigned level;
unsigned width, height, depth;
-   uint32_t *desc = images->desc.list + slot * 8;
+   uint32_t *desc = descs->list + slot * 8;
 
assert(!tex->is_depth);
assert(tex->fmask.size == 0);
@@ -616,7 +618,7 @@ static void si_set_shader_image(struct si_context *ctx,
}
 
images->enabled_mask |= 1u << slot;
-   images->desc.dirty_mask |= 1u << slot;
+   descs->dirty_mask |= 1u << slot;
 }
 
 static void
@@ -876,7 +878,8 @@ static void si_set_constant_buffer(struct si_context *sctx,
   struct si_buffer_resources *buffers,
   uint slot, struct pipe_constant_buffer 
*input)
 {
-   assert(slot < buffers->desc.num_elements);
+   struct si_descriptors *descs = >desc;
+   assert(slot < descs->num_elements);
pipe_resource_reference(>buffers[slot], NULL);
 
/* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
@@ -908,7 +911,7 @@ static void si_set_constant_buffer(struct si_context *sctx,
}
 
/* Set the descriptor. */
-   uint32_t *desc = buffers->desc.list + slot*4;
+   uint32_t *desc = descs->list + slot*4;
desc[0] = va;
desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
  S_008F04_STRIDE(0);
@@ -927,11 +930,11 @@ static void si_set_constant_buffer(struct si_context 
*sctx,
buffers->enabled_mask |= 1u << slot;
} else {
/* Clear the descriptor. */
-   

Mesa (master): radeonsi: pass shader stage to si_set_sampler_view

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: e6612a3e685b57714c3acde66b88bfee8aeb107f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6612a3e685b57714c3acde66b88bfee8aeb107f

Author: Nicolai Hähnle 
Date:   Fri Jun  3 15:03:59 2016 +0200

radeonsi: pass shader stage to si_set_sampler_view

Reviewed-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_descriptors.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 0065ac5..b1abdd2 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -330,10 +330,11 @@ void si_set_mutable_tex_desc_fields(struct r600_texture 
*tex,
 }
 
 static void si_set_sampler_view(struct si_context *sctx,
-   struct si_sampler_views *views,
+   unsigned shader,
unsigned slot, struct pipe_sampler_view *view,
bool disallow_early_out)
 {
+   struct si_sampler_views *views = >samplers[shader].views;
struct si_sampler_view *rview = (struct si_sampler_view*)view;
 
if (views->views[slot] == view && !disallow_early_out)
@@ -412,11 +413,11 @@ static void si_set_sampler_views(struct pipe_context *ctx,
if (!views || !views[i]) {
samplers->depth_texture_mask &= ~(1u << slot);
samplers->compressed_colortex_mask &= ~(1u << slot);
-   si_set_sampler_view(sctx, >views, slot, NULL, 
false);
+   si_set_sampler_view(sctx, shader, slot, NULL, false);
continue;
}
 
-   si_set_sampler_view(sctx, >views, slot, views[i], 
false);
+   si_set_sampler_view(sctx, shader, slot, views[i], false);
 
if (views[i]->texture && views[i]->texture->target != 
PIPE_BUFFER) {
struct r600_texture *rtex =
@@ -1433,7 +1434,7 @@ void si_update_all_texture_descriptors(struct si_context 
*sctx)
view->texture->target == PIPE_BUFFER)
continue;
 
-   si_set_sampler_view(sctx, samplers, i,
+   si_set_sampler_view(sctx, shader, i,
samplers->views[i], true);
}
}

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Mesa (master): radeonsi: pass shader stage to si_disable_shader_image

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: a29c4f9ebd83a815ed83c9fdcd19952ff8580132
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a29c4f9ebd83a815ed83c9fdcd19952ff8580132

Author: Nicolai Hähnle 
Date:   Fri Jun  3 15:36:45 2016 +0200

radeonsi: pass shader stage to si_disable_shader_image

Reviewed-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_descriptors.c | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 23e98f7..f8748d6 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -502,15 +502,19 @@ si_image_views_begin_new_cs(struct si_context *sctx, 
struct si_images_info *imag
 }
 
 static void
-si_disable_shader_image(struct si_images_info *images, unsigned slot)
+si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot)
 {
+   struct si_images_info *images = >images[shader];
+
if (images->enabled_mask & (1u << slot)) {
+   struct si_descriptors *descs = >desc;
+
pipe_resource_reference(>views[slot].resource, NULL);
images->compressed_colortex_mask &= ~(1 << slot);
 
-   memcpy(images->desc.list + slot*8, null_image_descriptor, 8*4);
+   memcpy(descs->list + slot*8, null_image_descriptor, 8*4);
images->enabled_mask &= ~(1u << slot);
-   images->desc.dirty_mask |= 1u << slot;
+   descs->dirty_mask |= 1u << slot;
}
 }
 
@@ -541,7 +545,7 @@ static void si_set_shader_image(struct si_context *ctx,
struct r600_resource *res;
 
if (!view || !view->resource) {
-   si_disable_shader_image(images, slot);
+   si_disable_shader_image(ctx, shader, slot);
return;
}
 

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Mesa (master): radeonsi: move si_descriptors into a per-context array

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: d152c737123d34c9b650e274607a2406ed4db535
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d152c737123d34c9b650e274607a2406ed4db535

Author: Nicolai Hähnle 
Date:   Fri Jun  3 15:56:39 2016 +0200

radeonsi: move si_descriptors into a per-context array

Reviewed-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_descriptors.c | 220 --
 src/gallium/drivers/radeonsi/si_pipe.h|   2 +-
 src/gallium/drivers/radeonsi/si_state.h   |  27 +++-
 3 files changed, 166 insertions(+), 83 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index f8748d6..4814618 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -263,6 +263,19 @@ si_descriptors_begin_new_cs(struct si_context *sctx, 
struct si_descriptors *desc
 
 /* SAMPLER VIEWS */
 
+static unsigned
+si_sampler_descriptors_idx(unsigned shader)
+{
+   return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
+  SI_SHADER_DESCS_SAMPLERS;
+}
+
+static struct si_descriptors *
+si_sampler_descriptors(struct si_context *sctx, unsigned shader)
+{
+   return >descriptors[si_sampler_descriptors_idx(shader)];
+}
+
 static void si_release_sampler_views(struct si_sampler_views *views)
 {
int i;
@@ -270,7 +283,6 @@ static void si_release_sampler_views(struct 
si_sampler_views *views)
for (i = 0; i < ARRAY_SIZE(views->views); i++) {
pipe_sampler_view_reference(>views[i], NULL);
}
-   si_release_descriptors(>desc);
 }
 
 static void si_sampler_view_add_buffer(struct si_context *sctx,
@@ -298,8 +310,6 @@ static void si_sampler_views_begin_new_cs(struct si_context 
*sctx,
si_sampler_view_add_buffer(sctx, views->views[i]->texture,
   RADEON_USAGE_READ);
}
-
-   si_descriptors_begin_new_cs(sctx, >desc);
 }
 
 void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
@@ -336,7 +346,7 @@ static void si_set_sampler_view(struct si_context *sctx,
 {
struct si_sampler_views *views = >samplers[shader].views;
struct si_sampler_view *rview = (struct si_sampler_view*)view;
-   struct si_descriptors *descs = >desc;
+   struct si_descriptors *descs = si_sampler_descriptors(sctx, shader);
 
if (views->views[slot] == view && !disallow_early_out)
return;
@@ -468,6 +478,19 @@ si_samplers_update_compressed_colortex_mask(struct 
si_textures_info *samplers)
 
 /* IMAGE VIEWS */
 
+static unsigned
+si_image_descriptors_idx(unsigned shader)
+{
+   return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
+  SI_SHADER_DESCS_IMAGES;
+}
+
+static struct si_descriptors*
+si_image_descriptors(struct si_context *sctx, unsigned shader)
+{
+   return >descriptors[si_image_descriptors_idx(shader)];
+}
+
 static void
 si_release_image_views(struct si_images_info *images)
 {
@@ -478,8 +501,6 @@ si_release_image_views(struct si_images_info *images)
 
pipe_resource_reference(>resource, NULL);
}
-
-   si_release_descriptors(>desc);
 }
 
 static void
@@ -497,8 +518,6 @@ si_image_views_begin_new_cs(struct si_context *sctx, struct 
si_images_info *imag
si_sampler_view_add_buffer(sctx, view->resource,
   RADEON_USAGE_READWRITE);
}
-
-   si_descriptors_begin_new_cs(sctx, >desc);
 }
 
 static void
@@ -507,7 +526,7 @@ si_disable_shader_image(struct si_context *ctx, unsigned 
shader, unsigned slot)
struct si_images_info *images = >images[shader];
 
if (images->enabled_mask & (1u << slot)) {
-   struct si_descriptors *descs = >desc;
+   struct si_descriptors *descs = si_image_descriptors(ctx, 
shader);
 
pipe_resource_reference(>views[slot].resource, NULL);
images->compressed_colortex_mask &= ~(1 << slot);
@@ -541,7 +560,7 @@ static void si_set_shader_image(struct si_context *ctx,
 {
struct si_screen *screen = ctx->screen;
struct si_images_info *images = >images[shader];
-   struct si_descriptors *descs = >desc;
+   struct si_descriptors *descs = si_image_descriptors(ctx, shader);
struct r600_resource *res;
 
if (!view || !view->resource) {
@@ -677,7 +696,7 @@ static void si_bind_sampler_states(struct pipe_context 
*ctx, unsigned shader,
 {
struct si_context *sctx = (struct si_context *)ctx;
struct si_textures_info *samplers = >samplers[shader];
-   struct si_descriptors *desc = >views.desc;
+   struct si_descriptors *desc = si_sampler_descriptors(sctx, shader);
struct si_sampler_state **sstates = (struct si_sampler_state**)states;
int i;
 
@@ -710,6 +729,7 @@ 

Mesa (master): radeonsi: keep track of dirty descriptor sets

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 8239da28e8b31b4727ecf59681aeebc65e17bf2f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8239da28e8b31b4727ecf59681aeebc65e17bf2f

Author: Nicolai Hähnle 
Date:   Fri Jun  3 17:40:12 2016 +0200

radeonsi: keep track of dirty descriptor sets

Reduces CPU load for draw calls that change none or few of the descriptors.

Reviewed-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_descriptors.c | 39 ---
 src/gallium/drivers/radeonsi/si_pipe.h|  1 +
 2 files changed, 36 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 4814618..bb81eb8 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -398,6 +398,7 @@ static void si_set_sampler_view(struct si_context *sctx,
}
 
descs->dirty_mask |= 1u << slot;
+   sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
 }
 
 static bool is_compressed_colortex(struct r600_texture *rtex)
@@ -534,6 +535,7 @@ si_disable_shader_image(struct si_context *ctx, unsigned 
shader, unsigned slot)
memcpy(descs->list + slot*8, null_image_descriptor, 8*4);
images->enabled_mask &= ~(1u << slot);
descs->dirty_mask |= 1u << slot;
+   ctx->descriptors_dirty |= 1u << 
si_image_descriptors_idx(shader);
}
 }
 
@@ -642,6 +644,7 @@ static void si_set_shader_image(struct si_context *ctx,
 
images->enabled_mask |= 1u << slot;
descs->dirty_mask |= 1u << slot;
+   ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
 }
 
 static void
@@ -723,6 +726,7 @@ static void si_bind_sampler_states(struct pipe_context 
*ctx, unsigned shader,
 
memcpy(desc->list + slot * 16 + 12, sstates[i]->val, 4*4);
desc->dirty_mask |= 1u << slot;
+   sctx->descriptors_dirty |= 1u << 
si_sampler_descriptors_idx(shader);
}
 }
 
@@ -971,6 +975,7 @@ static void si_set_constant_buffer(struct si_context *sctx,
}
 
descs->dirty_mask |= 1u << slot;
+   sctx->descriptors_dirty |= 1u << descriptors_idx;
 }
 
 void si_set_rw_buffer(struct si_context *sctx,
@@ -1032,6 +1037,8 @@ static void si_set_shader_buffers(struct pipe_context 
*ctx, unsigned shader,
memset(desc, 0, sizeof(uint32_t) * 4);
buffers->enabled_mask &= ~(1u << slot);
descs->dirty_mask |= 1u << slot;
+   sctx->descriptors_dirty |=
+   1u << si_shader_buffer_descriptors_idx(shader);
continue;
}
 
@@ -1054,6 +1061,8 @@ static void si_set_shader_buffers(struct pipe_context 
*ctx, unsigned shader,
  buffers->shader_usage, buffers->priority);
buffers->enabled_mask |= 1u << slot;
descs->dirty_mask |= 1u << slot;
+   sctx->descriptors_dirty |=
+   1u << si_shader_buffer_descriptors_idx(shader);
}
 }
 
@@ -1148,6 +1157,7 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint 
slot,
}
 
descs->dirty_mask |= 1u << slot;
+   sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
 }
 
 /* STREAMOUT BUFFERS */
@@ -1257,6 +1267,8 @@ static void si_set_streamout_targets(struct pipe_context 
*ctx,
buffers->enabled_mask &= ~(1u << bufidx);
descs->dirty_mask |= 1u << bufidx;
}
+
+   sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
 }
 
 static void si_desc_reset_buffer_offset(struct pipe_context *ctx,
@@ -1330,6 +1342,7 @@ static void si_reset_buffer_resources(struct si_context 
*sctx,
descs->list + i*4,
old_va, buf);
descs->dirty_mask |= 1u << i;
+   sctx->descriptors_dirty |= 1u << descriptors_idx;
 
radeon_add_to_buffer_list(>b, >b.gfx,
(struct r600_resource *)buf,
@@ -1393,6 +1406,7 @@ static void si_invalidate_buffer(struct pipe_context 
*ctx, struct pipe_resource
si_desc_reset_buffer_offset(ctx, descs->list + i*4,
old_va, buf);
descs->dirty_mask |= 1u << i;
+   sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
 
radeon_add_to_buffer_list(>b, >b.gfx,
  rbuffer, buffers->shader_usage,
@@ -1437,6 +1451,8 @@ static void si_invalidate_buffer(struct pipe_context 
*ctx, struct pipe_resource
i * 16 + 4,

Mesa (master): radeonsi: pass shader stage to si_set_shader_image

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: c615a055f4e6e6fcd6d53d8dadfac48f27358699
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c615a055f4e6e6fcd6d53d8dadfac48f27358699

Author: Nicolai Hähnle 
Date:   Fri Jun  3 15:04:40 2016 +0200

radeonsi: pass shader stage to si_set_shader_image

Reviewed-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_descriptors.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index b1abdd2..bea7515 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -531,10 +531,11 @@ si_mark_image_range_valid(struct pipe_image_view *view)
 }
 
 static void si_set_shader_image(struct si_context *ctx,
-   struct si_images_info *images,
+   unsigned shader,
unsigned slot, struct pipe_image_view *view)
 {
struct si_screen *screen = ctx->screen;
+   struct si_images_info *images = >images[shader];
struct r600_resource *res;
 
if (!view || !view->resource) {
@@ -624,7 +625,6 @@ si_set_shader_images(struct pipe_context *pipe, unsigned 
shader,
 struct pipe_image_view *views)
 {
struct si_context *ctx = (struct si_context *)pipe;
-   struct si_images_info *images = >images[shader];
unsigned i, slot;
 
assert(shader < SI_NUM_SHADERS);
@@ -636,10 +636,10 @@ si_set_shader_images(struct pipe_context *pipe, unsigned 
shader,
 
if (views) {
for (i = 0, slot = start_slot; i < count; ++i, ++slot)
-   si_set_shader_image(ctx, images, slot, [i]);
+   si_set_shader_image(ctx, shader, slot, [i]);
} else {
for (i = 0, slot = start_slot; i < count; ++i, ++slot)
-   si_set_shader_image(ctx, images, slot, NULL);
+   si_set_shader_image(ctx, shader, slot, NULL);
}
 }
 
@@ -1420,7 +1420,7 @@ void si_update_all_texture_descriptors(struct si_context 
*sctx)
view->resource->target == PIPE_BUFFER)
continue;
 
-   si_set_shader_image(sctx, images, i, view);
+   si_set_shader_image(sctx, shader, i, view);
}
 
/* Sampler views. */

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Mesa (master): radeonsi: move enabled_mask out of si_descriptors

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 031b57bc2f4065ed86973900c611dfdad721e41f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=031b57bc2f4065ed86973900c611dfdad721e41f

Author: Nicolai Hähnle 
Date:   Fri Jun  3 14:47:10 2016 +0200

radeonsi: move enabled_mask out of si_descriptors

This mask is irrelevant for the generic descriptor set handling, and having it
outside simplifies subsequent changes slightly.

Reviewed-by: Bas Nieuwenhuizen 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_blit.c|  4 +--
 src/gallium/drivers/radeonsi/si_descriptors.c | 50 +--
 src/gallium/drivers/radeonsi/si_pipe.h|  1 +
 src/gallium/drivers/radeonsi/si_state.h   |  9 +++--
 4 files changed, 34 insertions(+), 30 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 0d18730..34481c1 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -415,7 +415,7 @@ si_decompress_image_color_textures(struct si_context *sctx,
 static void si_check_render_feedback_textures(struct si_context *sctx,
   struct si_textures_info 
*textures)
 {
-   uint32_t mask = textures->views.desc.enabled_mask;
+   uint32_t mask = textures->views.enabled_mask;
 
while (mask) {
const struct pipe_sampler_view *view;
@@ -458,7 +458,7 @@ static void si_check_render_feedback_textures(struct 
si_context *sctx,
 static void si_check_render_feedback_images(struct si_context *sctx,
 struct si_images_info *images)
 {
-   uint32_t mask = images->desc.enabled_mask;
+   uint32_t mask = images->enabled_mask;
 
while (mask) {
const struct pipe_image_view *view;
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 9ddb142..f51ebd2 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -106,7 +106,7 @@ static void si_init_descriptors(struct si_descriptors *desc,
 {
int i;
 
-   assert(num_elements <= sizeof(desc->enabled_mask)*8);
+   assert(num_elements <= sizeof(desc->dirty_mask)*8);
 
desc->list = CALLOC(num_elements, element_dw_size * 4);
desc->element_dw_size = element_dw_size;
@@ -277,7 +277,7 @@ static void si_sampler_view_add_buffer(struct si_context 
*sctx,
 static void si_sampler_views_begin_new_cs(struct si_context *sctx,
  struct si_sampler_views *views)
 {
-   unsigned mask = views->desc.enabled_mask;
+   unsigned mask = views->enabled_mask;
 
/* Add buffers to the CS. */
while (mask) {
@@ -369,13 +369,13 @@ static void si_set_sampler_view(struct si_context *sctx,
   views->sampler_states[slot], 4*4);
}
 
-   views->desc.enabled_mask |= 1u << slot;
+   views->enabled_mask |= 1u << slot;
} else {
pipe_sampler_view_reference(>views[slot], NULL);
memcpy(views->desc.list + slot*16, null_texture_descriptor, 
8*4);
/* Only clear the lower dwords of FMASK. */
memcpy(views->desc.list + slot*16 + 8, null_texture_descriptor, 
4*4);
-   views->desc.enabled_mask &= ~(1u << slot);
+   views->enabled_mask &= ~(1u << slot);
}
 
views->desc.dirty_mask |= 1u << slot;
@@ -439,7 +439,7 @@ static void si_set_sampler_views(struct pipe_context *ctx,
 static void
 si_samplers_update_compressed_colortex_mask(struct si_textures_info *samplers)
 {
-   unsigned mask = samplers->views.desc.enabled_mask;
+   unsigned mask = samplers->views.enabled_mask;
 
while (mask) {
int i = u_bit_scan();
@@ -476,7 +476,7 @@ si_release_image_views(struct si_images_info *images)
 static void
 si_image_views_begin_new_cs(struct si_context *sctx, struct si_images_info 
*images)
 {
-   uint mask = images->desc.enabled_mask;
+   uint mask = images->enabled_mask;
 
/* Add buffers to the CS. */
while (mask) {
@@ -502,12 +502,12 @@ si_image_views_begin_new_cs(struct si_context *sctx, 
struct si_images_info *imag
 static void
 si_disable_shader_image(struct si_images_info *images, unsigned slot)
 {
-   if (images->desc.enabled_mask & (1u << slot)) {
+   if (images->enabled_mask & (1u << slot)) {
pipe_resource_reference(>views[slot].resource, NULL);
images->compressed_colortex_mask &= ~(1 << slot);
 
memcpy(images->desc.list + slot*8, null_image_descriptor, 8*4);
-   images->desc.enabled_mask &= ~(1u << slot);
+   images->enabled_mask &= ~(1u << slot);
images->desc.dirty_mask |= 

Mesa (12.0): mesa: automake: distclean git_sha1.h when building OOT

[Emil Velikov]

Module: Mesa
Branch: 12.0
Commit: bcfda0a1fe10bbe35a8c798a3e05b9fdc8802c70
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bcfda0a1fe10bbe35a8c798a3e05b9fdc8802c70

Author: Emil Velikov 
Date:   Mon Jun  6 19:39:40 2016 +0100

mesa: automake: distclean git_sha1.h when building OOT

In the case of out-of-tree (OOT) builds, in particular when building
from tarball, we'll end up with the file in both srcdir and builddir.

We want the former to remain intact (since we need it on rebuild) while
the latter should be removed otherwise `make distclean' gets angry at
us.

Ideally there'll be a solution that feels a bit less of a hack. Until
then this does the job exactly as expected.

Cc: 
Signed-off-by: Emil Velikov 
(cherry picked from commit b7f7ec78435771ab02f7d9a61bb1d4a11df720b8)

---

 src/Makefile.am | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/Makefile.am b/src/Makefile.am
index a5c54ff..0527a31 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -46,6 +46,12 @@ git_sha1.h: git_sha1.h.tmp
 
 BUILT_SOURCES = git_sha1.h
 
+# We want to keep the srcdir file since we need it on rebuild from tarball.
+# At the same time `make distclean' gets angry at us if we don't cleanup the
+# builddir one.
+distclean-local:
+   test $(top_srcdir) != $(top_builddir) && rm $(builddir)/git_sha1.h
+
 SUBDIRS = . gtest util mapi/glapi/gen mapi
 
 # include only conditionally ?

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Mesa (12.0): Update version to 12.0.0-rc2

[Emil Velikov]

Module: Mesa
Branch: 12.0
Commit: a7649abe9fc19671493957a8ffbbf6053c77cab4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7649abe9fc19671493957a8ffbbf6053c77cab4

Author: Emil Velikov 
Date:   Mon Jun  6 16:42:59 2016 +0100

Update version to 12.0.0-rc2

Signed-off-by: Emil Velikov 

---

 VERSION | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/VERSION b/VERSION
index cbc76f5..76ea38e 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-12.0.0-rc1
+12.0.0-rc2

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Mesa: tag mesa-12.0.0-rc2: Mesa 12.0.0-rc2 release candidate

[Emil Velikov]

Module: Mesa
Branch: refs/tags/mesa-12.0.0-rc2
Tag:d6a34effca74a4c3ed64a3d98fd6048952ce2cec
URL:
http://cgit.freedesktop.org/mesa/mesa/tag/?id=d6a34effca74a4c3ed64a3d98fd6048952ce2cec

Tagger: Emil Velikov 
Date:   Tue Jun  7 12:56:38 2016 +0100

Mesa 12.0.0-rc2 release candidate
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Mesa (12.0): mesa: automake: ensure that git_sha1.h.tmp has the right attributes

[Emil Velikov]

Module: Mesa
Branch: 12.0
Commit: 998e503592d13f1268df4e7ca1dd4da57e2d738f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=998e503592d13f1268df4e7ca1dd4da57e2d738f

Author: Emil Velikov 
Date:   Mon Jun  6 17:31:05 2016 +0100

mesa: automake: ensure that git_sha1.h.tmp has the right attributes

... when copied from git_sha1.h.

As the latter file can we lacking the write attribute, one should set it
explicitly. Otherwise we'll get a warning/failure at cleanup stage.

Cc: 
Signed-off-by: Emil Velikov 
(cherry picked from commit 2c424e00c3995a6a88f4db0c5dc9fd03ea749ebd)

---

 src/Makefile.am | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/Makefile.am b/src/Makefile.am
index 08446a8..a5c54ff 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -33,6 +33,7 @@ git_sha1.h.tmp:
fi \
else \
cp $(srcdir)/git_sha1.h git_sha1.h.tmp ;\
+   chmod u+w git_sha1.h.tmp; \
fi
 
 git_sha1.h: git_sha1.h.tmp

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Mesa (12.0): mesa: automake: add directory prefix for git_sha1.h

[Emil Velikov]

Module: Mesa
Branch: 12.0
Commit: 5e3e292502d48faa648d8267d35eb09cf2bd74ea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e3e292502d48faa648d8267d35eb09cf2bd74ea

Author: Emil Velikov 
Date:   Mon Jun  6 16:50:14 2016 +0100

mesa: automake: add directory prefix for git_sha1.h

Otherwise the build will assume that we've talking about builddir, which
is not the case in the else statement.

Here the file is already generated and is part of the tarball.

Cc: 
Signed-off-by: Emil Velikov 
(cherry picked from commit 359d9dfec3381284b044d6c9bcf7a648ea8c651a)

---

 src/Makefile.am | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/Makefile.am b/src/Makefile.am
index 45590c0..08446a8 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -32,7 +32,7 @@ git_sha1.h.tmp:
> git_sha1.h.tmp ; \
fi \
else \
-   cp git_sha1.h git_sha1.h.tmp ;\
+   cp $(srcdir)/git_sha1.h git_sha1.h.tmp ;\
fi
 
 git_sha1.h: git_sha1.h.tmp

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Mesa (12.0): egl: android: don' t add the image loader extension for !render_node

[Emil Velikov]

Module: Mesa
Branch: 12.0
Commit: 3be5c6a9ecc65ede2a112cfc6f548a3af860471d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3be5c6a9ecc65ede2a112cfc6f548a3af860471d

Author: Emil Velikov 
Date:   Sat Jun  4 01:09:14 2016 +0100

egl: android: don't add the image loader extension for !render_node

With earlier commit we introduced support for render_node devices, which
was couples with the use of the image loader extension.

As the work was inspired by egl/wayland we (erroneously) added the
extension for the !render_node path as well.

That works for wayland, as the implementations of the DRI2 and IMAGE
loader extensions converge behind the scenes. As that is not yet
the case for Android we shouldn't expose the extension.

Fixes: 34ddef39cef ("egl: android: add dma-buf fd support")

Cc: 
Reported-by: Mauro Rossi 
Tested-by: Mauro Rossi 
Acked-by: Rob Herring 
Signed-off-by: Emil Velikov 
(cherry picked from commit 1816c837c1906382c370d65afe65a691738fd03b)

---

 src/egl/drivers/dri2/platform_android.c | 15 +++
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index 25d02f5..70bbdff 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -814,10 +814,6 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *dpy)
 
dri2_dpy->is_render_node = drmGetNodeTypeFromFd(dri2_dpy->fd) == 
DRM_NODE_RENDER;
 
-   dri2_dpy->extensions[0] = _image_loader_extension.base;
-   dri2_dpy->extensions[1] = _invalidate.base;
-   dri2_dpy->extensions[2] = _lookup_extension.base;
-
/* render nodes cannot use Gem names, and thus do not support
 * the __DRI_DRI2_LOADER extension */
if (!dri2_dpy->is_render_node) {
@@ -827,10 +823,13 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *dpy)
   dri2_dpy->dri2_loader_extension.flushFrontBuffer = 
droid_flush_front_buffer;
   dri2_dpy->dri2_loader_extension.getBuffersWithFormat =
 droid_get_buffers_with_format;
-  dri2_dpy->extensions[3] = _dpy->dri2_loader_extension.base;
-  dri2_dpy->extensions[4] = NULL;
-   } else
-  dri2_dpy->extensions[3] = NULL;
+  dri2_dpy->extensions[0] = _dpy->dri2_loader_extension.base;
+   } else {
+  dri2_dpy->extensions[0] = _image_loader_extension.base;
+   }
+   dri2_dpy->extensions[1] = _invalidate.base;
+   dri2_dpy->extensions[2] = _lookup_extension.base;
+   dri2_dpy->extensions[3] = NULL;
 
 
if (!dri2_create_screen(dpy)) {

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Mesa (master): anv/entrypoints: Emit #if guards for all platforms

[Emil Velikov]

Module: Mesa
Branch: master
Commit: d1a53f91ee950720b54c35b7d61f0213659533de
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1a53f91ee950720b54c35b7d61f0213659533de

Author: Jason Ekstrand 
Date:   Mon Jun  6 14:29:18 2016 -0700

anv/entrypoints: Emit #if guards for all platforms

Reviewed-by: Emil Velikov 

---

 src/intel/vulkan/anv_entrypoints_gen.py | 32 ++--
 1 file changed, 22 insertions(+), 10 deletions(-)

diff --git a/src/intel/vulkan/anv_entrypoints_gen.py 
b/src/intel/vulkan/anv_entrypoints_gen.py
index 7a47372..546829f 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -51,19 +51,31 @@ def hash(name):
 
 return h
 
+def get_platform_guard_macro(name):
+if "Xlib" in name:
+return "VK_USE_PLATFORM_XLIB_KHR"
+elif "Xcb" in name:
+return "VK_USE_PLATFORM_XCB_KHR"
+elif "Wayland" in name:
+return "VK_USE_PLATFORM_WAYLAND_KHR"
+elif "Mir" in name:
+return "VK_USE_PLATFORM_MIR_KHR"
+elif "Android" in name:
+return "VK_USE_PLATFORM_ANDROID_KHR"
+elif "Win32" in name:
+return "VK_USE_PLATFORM_WIN32_KHR"
+else:
+return None
+
 def print_guard_start(name):
-if "Wayland" in name:
-print "#ifdef VK_USE_PLATFORM_WAYLAND_KHR"
-if "Xcb" in name:
-print "#ifdef VK_USE_PLATFORM_XCB_KHR"
-return
+guard = get_platform_guard_macro(name)
+if guard is not None:
+print "#ifdef {0}".format(guard)
 
 def print_guard_end(name):
-if "Wayland" in name:
-print "#endif // VK_USE_PLATFORM_WAYLAND_KHR"
-if "Xcb" in name:
-print "#endif // VK_USE_PLATFORM_XCB_KHR"
-return
+guard = get_platform_guard_macro(name)
+if guard is not None:
+print "#endif // {0}".format(guard)
 
 opt_header = False
 opt_code = False

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Mesa (master): mesa: automake: distclean git_sha1.h when building OOT

[Emil Velikov]

Module: Mesa
Branch: master
Commit: b7f7ec78435771ab02f7d9a61bb1d4a11df720b8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7f7ec78435771ab02f7d9a61bb1d4a11df720b8

Author: Emil Velikov 
Date:   Mon Jun  6 19:39:40 2016 +0100

mesa: automake: distclean git_sha1.h when building OOT

In the case of out-of-tree (OOT) builds, in particular when building
from tarball, we'll end up with the file in both srcdir and builddir.

We want the former to remain intact (since we need it on rebuild) while
the latter should be removed otherwise `make distclean' gets angry at
us.

Ideally there'll be a solution that feels a bit less of a hack. Until
then this does the job exactly as expected.

Cc: 
Signed-off-by: Emil Velikov 

---

 src/Makefile.am | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/Makefile.am b/src/Makefile.am
index a5c54ff..0527a31 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -46,6 +46,12 @@ git_sha1.h: git_sha1.h.tmp
 
 BUILT_SOURCES = git_sha1.h
 
+# We want to keep the srcdir file since we need it on rebuild from tarball.
+# At the same time `make distclean' gets angry at us if we don't cleanup the
+# builddir one.
+distclean-local:
+   test $(top_srcdir) != $(top_builddir) && rm $(builddir)/git_sha1.h
+
 SUBDIRS = . gtest util mapi/glapi/gen mapi
 
 # include only conditionally ?

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Mesa (master): platform_android: prevent deadlock in droid_swap_buffers

[Emil Velikov]

Module: Mesa
Branch: master
Commit: 1ea233c6f30a74e6ff5456c3521328237b01eed8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1ea233c6f30a74e6ff5456c3521328237b01eed8

Author: Haixia Shi 
Date:   Thu Jun  2 12:48:23 2016 -0700

platform_android: prevent deadlock in droid_swap_buffers

To avoid blocking other EGL calls, release the display mutex before
we enqueue buffer to android frameworks and re-acquire the mutex
upon return.

v2: moved lock/unlock inside droid_window_enqueue_buffer().

TEST=verify pinch zoom in Photos app no longer causes hangs

Signed-off-by: Haixia Shi 
Reviewed-by: Emil Velikov 

---

 src/egl/drivers/dri2/platform_android.c | 17 -
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index 70bbdff..b1d7272 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -160,8 +160,14 @@ droid_window_dequeue_buffer(struct dri2_egl_surface 
*dri2_surf)
 }
 
 static EGLBoolean
-droid_window_enqueue_buffer(struct dri2_egl_surface *dri2_surf)
+droid_window_enqueue_buffer(_EGLDisplay *disp, struct dri2_egl_surface 
*dri2_surf)
 {
+   /* To avoid blocking other EGL calls, release the display mutex before
+* we enter droid_window_enqueue_buffer() and re-acquire the mutex upon
+* return.
+*/
+   mtx_unlock(>Mutex);
+
 #if ANDROID_VERSION >= 0x0402
/* Queue the buffer without a sync fence. This informs the ANativeWindow
 * that it may access the buffer immediately.
@@ -185,14 +191,15 @@ droid_window_enqueue_buffer(struct dri2_egl_surface 
*dri2_surf)
dri2_surf->buffer->common.decRef(_surf->buffer->common);
dri2_surf->buffer = NULL;
 
+   mtx_lock(>Mutex);
return EGL_TRUE;
 }
 
 static void
-droid_window_cancel_buffer(struct dri2_egl_surface *dri2_surf)
+droid_window_cancel_buffer(_EGLDisplay *disp, struct dri2_egl_surface 
*dri2_surf)
 {
/* no cancel buffer? */
-   droid_window_enqueue_buffer(dri2_surf);
+   droid_window_enqueue_buffer(disp, dri2_surf);
 }
 
 static __DRIbuffer *
@@ -325,7 +332,7 @@ droid_destroy_surface(_EGLDriver *drv, _EGLDisplay *disp, 
_EGLSurface *surf)
 
if (dri2_surf->base.Type == EGL_WINDOW_BIT) {
   if (dri2_surf->buffer)
- droid_window_cancel_buffer(dri2_surf);
+ droid_window_cancel_buffer(disp, dri2_surf);
 
   dri2_surf->window->common.decRef(_surf->window->common);
}
@@ -435,7 +442,7 @@ droid_swap_buffers(_EGLDriver *drv, _EGLDisplay *disp, 
_EGLSurface *draw)
dri2_flush_drawable_for_swapbuffers(disp, draw);
 
if (dri2_surf->buffer)
-  droid_window_enqueue_buffer(dri2_surf);
+  droid_window_enqueue_buffer(disp, dri2_surf);
 
(*dri2_dpy->flush->invalidate)(dri2_surf->dri_drawable);
 

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Mesa (master): anv/entrypoints: Stop using the C preprocessor

[Emil Velikov]

Module: Mesa
Branch: master
Commit: d1e141a661b4ba7ffb0eac61d3288de76b4a8af1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1e141a661b4ba7ffb0eac61d3288de76b4a8af1

Author: Jason Ekstrand 
Date:   Mon Jun  6 14:29:19 2016 -0700

anv/entrypoints: Stop using the C preprocessor

Now that we emit guards for everything, we can just generate the files and
trust build flags to keep us safe.  This should also fix the tarball
problems.

Reviewed-by: Emil Velikov 

---

 src/intel/vulkan/Makefile.am | 14 ++
 1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/src/intel/vulkan/Makefile.am b/src/intel/vulkan/Makefile.am
index db81838..4d9ff90 100644
--- a/src/intel/vulkan/Makefile.am
+++ b/src/intel/vulkan/Makefile.am
@@ -82,17 +82,11 @@ VULKAN_SOURCES = \
 
 VULKAN_LIB_DEPS =
 
-VULKAN_ENTRYPOINT_CPPFLAGS =
-
 if HAVE_PLATFORM_X11
 AM_CPPFLAGS += \
$(XCB_DRI3_CFLAGS) \
-DVK_USE_PLATFORM_XCB_KHR
 
-VULKAN_ENTRYPOINT_CPPFLAGS += \
-   $(XCB_DRI3_CFLAGS) \
-   -DVK_USE_PLATFORM_XCB_KHR
-
 VULKAN_SOURCES += $(VULKAN_WSI_X11_FILES)
 VULKAN_LIB_DEPS += $(XCB_DRI3_LIBS)
 endif
@@ -105,10 +99,6 @@ AM_CPPFLAGS += \
$(WAYLAND_CFLAGS) \
-DVK_USE_PLATFORM_WAYLAND_KHR
 
-VULKAN_ENTRYPOINT_CPPFLAGS += \
-   $(WAYLAND_CFLAGS) \
-   -DVK_USE_PLATFORM_WAYLAND_KHR
-
 VULKAN_SOURCES += $(VULKAN_WSI_WAYLAND_FILES)
 
 VULKAN_LIB_DEPS += \
@@ -134,11 +124,11 @@ nodist_EXTRA_libvulkan_intel_la_SOURCES = dummy.cpp
 libvulkan_intel_la_SOURCES = $(VULKAN_GEM_FILES)
 
 anv_entrypoints.h : anv_entrypoints_gen.py $(vulkan_include_HEADERS)
-   $(AM_V_GEN)$(CPP) $(VULKAN_ENTRYPOINT_CPPFLAGS) 
$(top_srcdir)/include/vulkan/vulkan_intel.h |\
+   $(AM_V_GEN) cat $(vulkan_include_HEADERS) |\
$(PYTHON2) $(srcdir)/anv_entrypoints_gen.py header > $@
 
 anv_entrypoints.c : anv_entrypoints_gen.py $(vulkan_include_HEADERS)
-   $(AM_V_GEN)$(CPP) $(VULKAN_ENTRYPOINT_CPPFLAGS) 
$(top_srcdir)/include/vulkan/vulkan_intel.h |\
+   $(AM_V_GEN) cat $(vulkan_include_HEADERS) |\
$(PYTHON2) $(srcdir)/anv_entrypoints_gen.py code > $@
 
 BUILT_SOURCES = $(VULKAN_GENERATED_FILES)

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Mesa (master): mesa: automake: ensure that git_sha1.h.tmp has the right attributes

[Emil Velikov]

Module: Mesa
Branch: master
Commit: 2c424e00c3995a6a88f4db0c5dc9fd03ea749ebd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c424e00c3995a6a88f4db0c5dc9fd03ea749ebd

Author: Emil Velikov 
Date:   Mon Jun  6 17:31:05 2016 +0100

mesa: automake: ensure that git_sha1.h.tmp has the right attributes

... when copied from git_sha1.h.

As the latter file can we lacking the write attribute, one should set it
explicitly. Otherwise we'll get a warning/failure at cleanup stage.

Cc: 
Signed-off-by: Emil Velikov 

---

 src/Makefile.am | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/Makefile.am b/src/Makefile.am
index 08446a8..a5c54ff 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -33,6 +33,7 @@ git_sha1.h.tmp:
fi \
else \
cp $(srcdir)/git_sha1.h git_sha1.h.tmp ;\
+   chmod u+w git_sha1.h.tmp; \
fi
 
 git_sha1.h: git_sha1.h.tmp

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Mesa (master): mesa: automake: add directory prefix for git_sha1.h

[Emil Velikov]

Module: Mesa
Branch: master
Commit: 359d9dfec3381284b044d6c9bcf7a648ea8c651a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=359d9dfec3381284b044d6c9bcf7a648ea8c651a

Author: Emil Velikov 
Date:   Mon Jun  6 16:50:14 2016 +0100

mesa: automake: add directory prefix for git_sha1.h

Otherwise the build will assume that we've talking about builddir, which
is not the case in the else statement.

Here the file is already generated and is part of the tarball.

Cc: 
Signed-off-by: Emil Velikov 

---

 src/Makefile.am | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/Makefile.am b/src/Makefile.am
index 45590c0..08446a8 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -32,7 +32,7 @@ git_sha1.h.tmp:
> git_sha1.h.tmp ; \
fi \
else \
-   cp git_sha1.h git_sha1.h.tmp ;\
+   cp $(srcdir)/git_sha1.h git_sha1.h.tmp ;\
fi
 
 git_sha1.h: git_sha1.h.tmp

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Mesa (master): egl: android: don' t add the image loader extension for !render_node

[Emil Velikov]

Module: Mesa
Branch: master
Commit: 1816c837c1906382c370d65afe65a691738fd03b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1816c837c1906382c370d65afe65a691738fd03b

Author: Emil Velikov 
Date:   Sat Jun  4 01:09:14 2016 +0100

egl: android: don't add the image loader extension for !render_node

With earlier commit we introduced support for render_node devices, which
was couples with the use of the image loader extension.

As the work was inspired by egl/wayland we (erroneously) added the
extension for the !render_node path as well.

That works for wayland, as the implementations of the DRI2 and IMAGE
loader extensions converge behind the scenes. As that is not yet
the case for Android we shouldn't expose the extension.

Fixes: 34ddef39cef ("egl: android: add dma-buf fd support")

Cc: 
Reported-by: Mauro Rossi 
Tested-by: Mauro Rossi 
Acked-by: Rob Herring 
Signed-off-by: Emil Velikov 

---

 src/egl/drivers/dri2/platform_android.c | 15 +++
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index 25d02f5..70bbdff 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -814,10 +814,6 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *dpy)
 
dri2_dpy->is_render_node = drmGetNodeTypeFromFd(dri2_dpy->fd) == 
DRM_NODE_RENDER;
 
-   dri2_dpy->extensions[0] = _image_loader_extension.base;
-   dri2_dpy->extensions[1] = _invalidate.base;
-   dri2_dpy->extensions[2] = _lookup_extension.base;
-
/* render nodes cannot use Gem names, and thus do not support
 * the __DRI_DRI2_LOADER extension */
if (!dri2_dpy->is_render_node) {
@@ -827,10 +823,13 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *dpy)
   dri2_dpy->dri2_loader_extension.flushFrontBuffer = 
droid_flush_front_buffer;
   dri2_dpy->dri2_loader_extension.getBuffersWithFormat =
 droid_get_buffers_with_format;
-  dri2_dpy->extensions[3] = _dpy->dri2_loader_extension.base;
-  dri2_dpy->extensions[4] = NULL;
-   } else
-  dri2_dpy->extensions[3] = NULL;
+  dri2_dpy->extensions[0] = _dpy->dri2_loader_extension.base;
+   } else {
+  dri2_dpy->extensions[0] = _image_loader_extension.base;
+   }
+   dri2_dpy->extensions[1] = _invalidate.base;
+   dri2_dpy->extensions[2] = _lookup_extension.base;
+   dri2_dpy->extensions[3] = NULL;
 
 
if (!dri2_create_screen(dpy)) {

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Mesa (master): gallium/radeon: don' t discard DCC if an external user can write to it

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 9e5b5fbde0b445df1a3265b33e2ac890d6505409
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e5b5fbde0b445df1a3265b33e2ac890d6505409

Author: Marek Olšák 
Date:   Thu Jun  2 23:30:01 2016 +0200

gallium/radeon: don't discard DCC if an external user can write to it

We don't import textures with DCC now, but soon we will.

v2: if we can't disable DCC for image writes, at least decompress DCC
at bind time

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeon/r600_pipe_common.h |  2 +-
 src/gallium/drivers/radeon/r600_texture.c | 31 +++
 src/gallium/drivers/radeonsi/si_descriptors.c | 10 +++--
 3 files changed, 31 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 8072833..2d60da4 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -676,7 +676,7 @@ void evergreen_do_fast_color_clear(struct 
r600_common_context *rctx,
   struct r600_atom *fb_state,
   unsigned *buffers, unsigned *dirty_cbufs,
   const union pipe_color_union *color);
-void r600_texture_disable_dcc(struct r600_common_screen *rscreen,
+bool r600_texture_disable_dcc(struct r600_common_screen *rscreen,
  struct r600_texture *rtex);
 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 void r600_init_context_texture_functions(struct r600_common_context *rctx);
diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 71758c4..0f5c08f 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -32,7 +32,7 @@
 #include 
 #include 
 
-static void r600_texture_discard_dcc(struct r600_common_screen *rscreen,
+static bool r600_texture_discard_dcc(struct r600_common_screen *rscreen,
 struct r600_texture *rtex);
 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
   struct r600_texture *rtex);
@@ -86,7 +86,8 @@ bool r600_prepare_for_dma_blit(struct r600_common_context 
*rctx,
  src_box->height, 
src_box->depth))
return false;
 
-   r600_texture_discard_dcc(rctx->screen, rdst);
+   if (!r600_texture_discard_dcc(rctx->screen, rdst))
+   return false;
}
 
/* CMASK as:
@@ -376,25 +377,37 @@ static void r600_texture_discard_cmask(struct 
r600_common_screen *rscreen,
p_atomic_inc(>compressed_colortex_counter);
 }
 
-static void r600_texture_discard_dcc(struct r600_common_screen *rscreen,
+static bool r600_can_disable_dcc(struct r600_texture *rtex)
+{
+   /* We can't disable DCC if it can be written by another process. */
+   return rtex->dcc_offset &&
+  (!rtex->resource.is_shared ||
+   !(rtex->resource.external_usage & PIPE_HANDLE_USAGE_WRITE));
+}
+
+static bool r600_texture_discard_dcc(struct r600_common_screen *rscreen,
 struct r600_texture *rtex)
 {
+   if (!r600_can_disable_dcc(rtex))
+   return false;
+
/* Disable DCC. */
rtex->dcc_offset = 0;
rtex->cb_color_info &= ~VI_S_028C70_DCC_ENABLE(1);
 
/* Notify all contexts about the change. */
r600_dirty_all_framebuffer_states(rscreen);
+   return true;
 }
 
-void r600_texture_disable_dcc(struct r600_common_screen *rscreen,
+bool r600_texture_disable_dcc(struct r600_common_screen *rscreen,
  struct r600_texture *rtex)
 {
struct r600_common_context *rctx =
(struct r600_common_context *)rscreen->aux_context;
 
-   if (!rtex->dcc_offset)
-   return;
+   if (!r600_can_disable_dcc(rtex))
+   return false;
 
/* Decompress DCC. */
pipe_mutex_lock(rscreen->aux_context_lock);
@@ -402,7 +415,7 @@ void r600_texture_disable_dcc(struct r600_common_screen 
*rscreen,
rctx->b.flush(>b, NULL, 0);
pipe_mutex_unlock(rscreen->aux_context_lock);
 
-   r600_texture_discard_dcc(rscreen, rtex);
+   return r600_texture_discard_dcc(rscreen, rtex);
 }
 
 static void r600_degrade_tile_mode_to_linear(struct r600_common_context *rctx,
@@ -497,8 +510,8 @@ static boolean r600_texture_get_handle(struct pipe_screen* 
screen,
 * access.
 */
if (usage & PIPE_HANDLE_USAGE_WRITE && rtex->dcc_offset) {
-   r600_texture_disable_dcc(rscreen, rtex);
-   update_metadata = true;
+   if (r600_texture_disable_dcc(rscreen, rtex))
+

Mesa (master): gallium/radeon: add support for sharing textures with DCC between processes

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 095803a37aa67361fc68604e81f858f31ae59b1b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=095803a37aa67361fc68604e81f858f31ae59b1b

Author: Marek Olšák 
Date:   Thu Jun  2 23:36:43 2016 +0200

gallium/radeon: add support for sharing textures with DCC between processes

v2: use a function for calculating WORD1 of bo metadata

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeon/r600_pipe_common.h |  4 +++
 src/gallium/drivers/radeon/r600_texture.c | 16 +---
 src/gallium/drivers/radeonsi/si_state.c   | 35 ++-
 3 files changed, 51 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 2d60da4..fd658b6 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -379,6 +379,10 @@ struct r600_common_screen {
void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
  struct r600_texture *rtex,
  struct radeon_bo_metadata *md);
+
+   void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
+   struct r600_texture *rtex,
+   struct radeon_bo_metadata *md);
 };
 
 /* This encapsulates a state or an operation which can emitted into the GPU
diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 0f5c08f..920cc21 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1035,8 +1035,12 @@ r600_texture_create_object(struct pipe_screen *screen,
}
}
 
-   if (!buf && rtex->surface.dcc_size &&
-   !(rscreen->debug_flags & DBG_NO_DCC)) {
+   /* Shared textures must always set up DCC here.
+* If it's not present, it will be disabled by
+* apply_opaque_metadata later.
+*/
+   if (rtex->surface.dcc_size &&
+   (buf || !(rscreen->debug_flags & DBG_NO_DCC))) {
/* Reserve space for the DCC buffer. */
rtex->dcc_offset = align64(rtex->size, 
rtex->surface.dcc_alignment);
rtex->size = rtex->dcc_offset + rtex->surface.dcc_size;
@@ -1063,7 +1067,9 @@ r600_texture_create_object(struct pipe_screen *screen,
 rtex->cmask.offset, rtex->cmask.size,
 0x, R600_COHERENCY_NONE);
}
-   if (rtex->dcc_offset) {
+
+   /* Initialize DCC only if the texture is not being imported. */
+   if (!buf && rtex->dcc_offset) {
r600_screen_clear_buffer(rscreen, >resource.b.b,
 rtex->dcc_offset,
 rtex->surface.dcc_size,
@@ -1229,6 +1235,10 @@ static struct pipe_resource 
*r600_texture_from_handle(struct pipe_screen *screen
 
rtex->resource.is_shared = true;
rtex->resource.external_usage = usage;
+
+   if (rscreen->apply_opaque_metadata)
+   rscreen->apply_opaque_metadata(rscreen, rtex, );
+
return >resource.b.b;
 }
 
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 14520ca..e506ec9 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3398,6 +3398,11 @@ void si_init_state_functions(struct si_context *sctx)
si_init_config(sctx);
 }
 
+static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
+{
+   return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
+}
+
 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
 struct r600_texture *rtex,
 struct radeon_bo_metadata *md)
@@ -3432,7 +3437,7 @@ static void si_query_opaque_metadata(struct 
r600_common_screen *rscreen,
md->metadata[0] = 1; /* metadata image format version 1 */
 
/* TILE_MODE_INDEX is ambiguous without a PCI ID. */
-   md->metadata[1] = (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
+   md->metadata[1] = si_get_bo_metadata_word1(rscreen);
 
si_make_texture_descriptor(sscreen, rtex, true,
   res->target, res->format,
@@ -3459,9 +3464,37 @@ static void si_query_opaque_metadata(struct 
r600_common_screen *rscreen,
md->size_metadata = (11 + res->last_level) * 4;
 }
 
+static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
+struct r600_texture *rtex,
+struct radeon_bo_metadata *md)
+{
+   uint32_t *desc = >metadata[2];
+
+  

Mesa (master): i915: fix typo CAP.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: c6b14bafa446d1556eb0dd344de34288617e1278
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c6b14bafa446d1556eb0dd344de34288617e1278

Author: Dave Airlie 
Date:   Tue Jun  7 18:30:54 2016 +1000

i915: fix typo CAP.

Signed-off-by: Dave Airlie 

---

 src/gallium/drivers/i915/i915_screen.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/i915/i915_screen.c 
b/src/gallium/drivers/i915/i915_screen.c
index f927c73..a7ee381 100644
--- a/src/gallium/drivers/i915/i915_screen.c
+++ b/src/gallium/drivers/i915/i915_screen.c
@@ -273,7 +273,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap 
cap)
case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
case PIPE_CAP_CULL_DISTANCE:
case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
-   case PIPE_CAP_VOTE_TGSI:
+   case PIPE_CAP_TGSI_VOTE:
   return 0;
 
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:

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Mesa (master): glsl: initialise pointer to NULL

[Iago Toral Quiroga]

Module: Mesa
Branch: master
Commit: b450f29073c4129896fce37699ef3d7f152ed458
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b450f29073c4129896fce37699ef3d7f152ed458

Author: Jakob Sinclair 
Date:   Sat Jun  4 01:09:52 2016 +0200

glsl: initialise pointer to NULL

Could cause issues if you tried to read from an uninitialised pointer.
This just initalises the pointer to null to avoid that being a problem.
Discovered by Coverity.

CID: 1343616

Signed-off-by: Jakob Sinclair 
Reviewed-by: Iago Toral Quiroga 

---

 src/compiler/glsl/glsl_parser_extras.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
b/src/compiler/glsl/glsl_parser_extras.cpp
index fde8c19..09f7477 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -1603,6 +1603,7 @@ ast_struct_specifier::ast_struct_specifier(const char 
*identifier,
name = identifier;
this->declarations.push_degenerate_list_at_head(_list->link);
is_declaration = true;
+   layout = NULL;
 }
 
 void ast_subroutine_list::print(void) const

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