Mesa (master): i965: get outputs written from nir info

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 7ef8286487562e1e8678ccc514e4054a682c0c89
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ef8286487562e1e8678ccc514e4054a682c0c89

Author: Timothy Arceri 
Date:   Wed Oct  5 16:24:56 2016 +1100

i965: get outputs written from nir info

This is a step towards dropping the GLSL IR version of
do_set_program_inouts() in i965 and moving towards native nir support.

This is important because we want to eventually convert to nir and
use its optimisations passes before we can call this GLSL IR pass.

Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_gs.c   |  2 +-
 src/mesa/drivers/dri/i965/brw_tcs.c  | 10 ++
 src/mesa/drivers/dri/i965/brw_tes.c  | 10 ++
 src/mesa/drivers/dri/i965/brw_vs.c   | 15 +--
 src/mesa/drivers/dri/i965/brw_wm.c   | 10 +++---
 src/mesa/drivers/dri/i965/brw_wm_state.c |  9 +
 6 files changed, 34 insertions(+), 22 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_gs.c 
b/src/mesa/drivers/dri/i965/brw_gs.c
index a898260..12bc706 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -134,7 +134,7 @@ brw_codegen_gs_prog(struct brw_context *brw,
_data.base.base,
compiler->scalar_stage[MESA_SHADER_GEOMETRY]);
 
-   GLbitfield64 outputs_written = gp->program.Base.OutputsWritten;
+   uint64_t outputs_written = gp->program.Base.nir->info.outputs_written;
 
prog_data.base.cull_distance_mask =
   ((1 << gp->program.Base.CullDistanceArraySize) - 1) <<
diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c 
b/src/mesa/drivers/dri/i965/brw_tcs.c
index 8418861..0b69139 100644
--- a/src/mesa/drivers/dri/i965/brw_tcs.c
+++ b/src/mesa/drivers/dri/i965/brw_tcs.c
@@ -328,8 +328,10 @@ brw_tcs_populate_key(struct brw_context *brw,
memset(key, 0, sizeof(*key));
 
if (brw->tess_ctrl_program) {
-  per_vertex_slots |= brw->tess_ctrl_program->Base.OutputsWritten;
-  per_patch_slots |= brw->tess_ctrl_program->Base.PatchOutputsWritten;
+  per_vertex_slots |=
+ brw->tess_ctrl_program->Base.nir->info.outputs_written;
+  per_patch_slots |=
+ brw->tess_ctrl_program->Base.nir->info.patch_outputs_written;
}
 
if (brw->gen < 8 || !tcp)
@@ -424,8 +426,8 @@ brw_tcs_precompile(struct gl_context *ctx,
   key.tes_primitive_mode = GL_TRIANGLES;
}
 
-   key.outputs_written = prog->OutputsWritten;
-   key.patch_outputs_written = prog->PatchOutputsWritten;
+   key.outputs_written = prog->nir->info.outputs_written;
+   key.patch_outputs_written = prog->nir->info.patch_outputs_written;
 
success = brw_codegen_tcs_prog(brw, shader_prog, btcp, );
 
diff --git a/src/mesa/drivers/dri/i965/brw_tes.c 
b/src/mesa/drivers/dri/i965/brw_tes.c
index 2c43a3e..d1f56bd 100644
--- a/src/mesa/drivers/dri/i965/brw_tes.c
+++ b/src/mesa/drivers/dri/i965/brw_tes.c
@@ -250,8 +250,10 @@ brw_tes_populate_key(struct brw_context *brw,
 * be stored in the Patch URB Entry as well.
 */
if (brw->tess_ctrl_program) {
-  per_vertex_slots |= brw->tess_ctrl_program->Base.OutputsWritten;
-  per_patch_slots |= brw->tess_ctrl_program->Base.PatchOutputsWritten;
+  per_vertex_slots |=
+ brw->tess_ctrl_program->Base.nir->info.outputs_written;
+  per_patch_slots |=
+ brw->tess_ctrl_program->Base.nir->info.patch_outputs_written;
}
 
/* Ignore gl_TessLevelInner/Outer - we treat them as system values,
@@ -318,8 +320,8 @@ brw_tes_precompile(struct gl_context *ctx,
if (shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL]) {
   struct gl_program *tcp =
  shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL]->Program;
-  key.inputs_read |= tcp->OutputsWritten;
-  key.patch_inputs_read |= tcp->PatchOutputsWritten;
+  key.inputs_read |= tcp->nir->info.outputs_written;
+  key.patch_inputs_read |= tcp->nir->info.patch_outputs_written;
}
 
/* Ignore gl_TessLevelInner/Outer - they're system values. */
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c 
b/src/mesa/drivers/dri/i965/brw_vs.c
index bd194ca..aa1ae28 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -149,8 +149,9 @@ brw_codegen_vs_prog(struct brw_context *brw,
  _data.base.base);
}
 
-   GLbitfield64 outputs_written =
-  brw_vs_outputs_written(brw, key, vp->program.Base.OutputsWritten);
+   uint64_t outputs_written =
+  brw_vs_outputs_written(brw, key,
+ vp->program.Base.nir->info.outputs_written);
prog_data.inputs_read = vp->program.Base.InputsRead;
 
if (key->copy_edgeflag) {
@@ -339,8 +340,9 @@ brw_vs_populate_key(struct brw_context *brw,
   }
}
 
-   if (prog->OutputsWritten & (VARYING_BIT_COL0 | VARYING_BIT_COL1 |
-   VARYING_BIT_BFC0 | 

Mesa (master): i965: remove remaining tabs in brw_draw.c

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 88428fbe412e89c421da89808ef8bcc0fbddd845
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=88428fbe412e89c421da89808ef8bcc0fbddd845

Author: Timothy Arceri 
Date:   Wed Oct  5 16:46:39 2016 +1100

i965: remove remaining tabs in brw_draw.c

Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_draw.c | 26 +-
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index af98464..68add7f 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -102,8 +102,8 @@ brw_set_prim(struct brw_context *brw, const struct 
_mesa_prim *prim)
   brw->ctx.NewDriverState |= BRW_NEW_PRIMITIVE;
 
   if (reduced_prim[prim->mode] != brw->reduced_primitive) {
-brw->reduced_primitive = reduced_prim[prim->mode];
-brw->ctx.NewDriverState |= BRW_NEW_REDUCED_PRIMITIVE;
+ brw->reduced_primitive = reduced_prim[prim->mode];
+ brw->ctx.NewDriverState |= BRW_NEW_REDUCED_PRIMITIVE;
   }
}
 }
@@ -568,9 +568,9 @@ brw_try_draw_prims(struct gl_context *ctx,
  brw->ctx.NewDriverState |= BRW_NEW_VERTICES;
 
   if (brw->gen < 6)
-brw_set_prim(brw, [i]);
+ brw_set_prim(brw, [i]);
   else
-gen6_set_prim(brw, [i]);
+ gen6_set_prim(brw, [i]);
 
 retry:
 
@@ -580,8 +580,8 @@ retry:
* brw->ctx.NewDriverState.
*/
   if (brw->ctx.NewDriverState) {
-brw->no_batch_wrap = true;
-brw_upload_render_state(brw);
+ brw->no_batch_wrap = true;
+ brw_upload_render_state(brw);
   }
 
   brw_emit_prim(brw, [i], brw->primitive, xfb_obj, stream);
@@ -589,17 +589,17 @@ retry:
   brw->no_batch_wrap = false;
 
   if (dri_bufmgr_check_aperture_space(>batch.bo, 1)) {
-if (!fail_next) {
-   intel_batchbuffer_reset_to_saved(brw);
-   intel_batchbuffer_flush(brw);
-   fail_next = true;
-   goto retry;
-} else {
+ if (!fail_next) {
+intel_batchbuffer_reset_to_saved(brw);
+intel_batchbuffer_flush(brw);
+fail_next = true;
+goto retry;
+ } else {
 int ret = intel_batchbuffer_flush(brw);
 WARN_ONCE(ret == -ENOSPC,
   "i965: Single primitive emit exceeded "
   "available aperture space\n");
-}
+ }
   }
 
   /* Now that we know we haven't run out of aperture space, we can safely

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Mesa (master): mesa: remove the UsesDFdy flag

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 201f940d2e49d6ead5dfd6921b33bf6afefa4c68
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=201f940d2e49d6ead5dfd6921b33bf6afefa4c68

Author: Timothy Arceri 
Date:   Wed Oct  5 15:28:50 2016 +1100

mesa: remove the UsesDFdy flag

Seems the last user of this was removed in 08bc74e69.

Reviewed-by: Kenneth Graunke 

---

 src/compiler/glsl/ir_set_program_inouts.cpp | 19 ++-
 src/mesa/main/mtypes.h  |  1 -
 src/mesa/program/arbprogparse.c |  1 -
 src/mesa/program/program_parse.y|  2 --
 src/mesa/program/program_parser.h   |  1 -
 5 files changed, 2 insertions(+), 22 deletions(-)

diff --git a/src/compiler/glsl/ir_set_program_inouts.cpp 
b/src/compiler/glsl/ir_set_program_inouts.cpp
index 48ed3c5..f5b36df 100644
--- a/src/compiler/glsl/ir_set_program_inouts.cpp
+++ b/src/compiler/glsl/ir_set_program_inouts.cpp
@@ -26,8 +26,8 @@
  *
  * Sets the InputsRead and OutputsWritten of Mesa programs.
  *
- * Additionally, for fragment shaders, sets the InterpQualifier array, the
- * IsCentroid and IsSample bitfields, and the UsesDFdy flag.
+ * Additionally, for fragment shaders, sets the InterpQualifier array, and the
+ * IsCentroid and IsSample bitfields.
  *
  * Mesa programs (gl_program, not gl_shader_program) have a set of
  * flags indicating which varyings are read and written.  Computing
@@ -58,7 +58,6 @@ public:
 
virtual ir_visitor_status visit_enter(ir_dereference_array *);
virtual ir_visitor_status visit_enter(ir_function_signature *);
-   virtual ir_visitor_status visit_enter(ir_expression *);
virtual ir_visitor_status visit_enter(ir_discard *);
virtual ir_visitor_status visit_enter(ir_texture *);
virtual ir_visitor_status visit(ir_dereference_variable *);
@@ -412,19 +411,6 @@ 
ir_set_program_inouts_visitor::visit_enter(ir_function_signature *ir)
 }
 
 ir_visitor_status
-ir_set_program_inouts_visitor::visit_enter(ir_expression *ir)
-{
-   if (this->shader_stage == MESA_SHADER_FRAGMENT &&
-   (ir->operation == ir_unop_dFdy ||
-ir->operation == ir_unop_dFdy_coarse ||
-ir->operation == ir_unop_dFdy_fine)) {
-  gl_fragment_program *fprog = (gl_fragment_program *) prog;
-  fprog->UsesDFdy = true;
-   }
-   return visit_continue;
-}
-
-ir_visitor_status
 ir_set_program_inouts_visitor::visit_enter(ir_discard *)
 {
/* discards are only allowed in fragment shaders. */
@@ -462,7 +448,6 @@ do_set_program_inouts(exec_list *instructions, struct 
gl_program *prog,
   memset(fprog->InterpQualifier, 0, sizeof(fprog->InterpQualifier));
   fprog->IsCentroid = 0;
   fprog->IsSample = 0;
-  fprog->UsesDFdy = false;
   fprog->UsesKill = false;
}
visit_list_elements(, instructions);
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index b279fc4..d494872 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2039,7 +2039,6 @@ struct gl_fragment_program
 {
struct gl_program Base;   /**< base class */
GLboolean UsesKill;  /**< shader uses KIL instruction */
-   GLboolean UsesDFdy;  /**< shader uses DDY instruction */
GLboolean OriginUpperLeft;
GLboolean PixelCenterInteger;
enum gl_frag_depth_layout FragDepthLayout;
diff --git a/src/mesa/program/arbprogparse.c b/src/mesa/program/arbprogparse.c
index 3ddaeca..b7bddfe 100644
--- a/src/mesa/program/arbprogparse.c
+++ b/src/mesa/program/arbprogparse.c
@@ -120,7 +120,6 @@ _mesa_parse_arb_fragment_program(struct gl_context* ctx, 
GLenum target,
program->PixelCenterInteger = state.option.PixelCenterInteger;
 
program->UsesKill= state.fragment.UsesKill;
-   program->UsesDFdy= state.fragment.UsesDFdy;
 
free(program->Base.Instructions);
program->Base.Instructions = prog.Instructions;
diff --git a/src/mesa/program/program_parse.y b/src/mesa/program/program_parse.y
index ad94fe0..fc8eed7 100644
--- a/src/mesa/program/program_parse.y
+++ b/src/mesa/program/program_parse.y
@@ -388,8 +388,6 @@ ARL_instruction: ARL maskedAddrReg ',' scalarSrcReg
 
 VECTORop_instruction: VECTOR_OP maskedDstReg ',' swizzleSrcReg
{
-  if ($1.Opcode == OPCODE_DDY)
- state->fragment.UsesDFdy = 1;
   $$ = asm_instruction_copy_ctor(& $1, & $2, & $4, NULL, NULL);
}
;
diff --git a/src/mesa/program/program_parser.h 
b/src/mesa/program/program_parser.h
index af7b2a0..05ceb92 100644
--- a/src/mesa/program/program_parser.h
+++ b/src/mesa/program/program_parser.h
@@ -213,7 +213,6 @@ struct asm_parser_state {
 
struct {
   unsigned UsesKill:1;
-  unsigned UsesDFdy:1;
} fragment;
 };
 

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Mesa (master): i965: get outputs read from nir info

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: b526a9b708b48c3d1c394783cba99f11eb17d0b9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b526a9b708b48c3d1c394783cba99f11eb17d0b9

Author: Timothy Arceri 
Date:   Wed Oct  5 15:56:21 2016 +1100

i965: get outputs read from nir info

This is a step towards dropping the GLSL IR version of
do_set_program_inouts() in i965 and moving towards native nir support.

This is important because we want to eventually convert to nir and
use its optimisations passes before we can call this GLSL IR pass.

Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_context.c  | 3 ++-
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 7a39fe2..d6204fd 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -31,6 +31,7 @@
   */
 
 
+#include "compiler/nir/nir.h"
 #include "main/api_exec.h"
 #include "main/context.h"
 #include "main/fbobject.h"
@@ -304,7 +305,7 @@ intel_update_state(struct gl_context * ctx, GLuint 
new_state)
/* Resolve color buffers for non-coherent framebuffer fetch. */
if (!ctx->Extensions.MESA_shader_framebuffer_fetch &&
ctx->FragmentProgram._Current &&
-   ctx->FragmentProgram._Current->Base.OutputsRead) {
+   ctx->FragmentProgram._Current->Base.nir->info.outputs_read) {
   const struct gl_framebuffer *fb = ctx->DrawBuffer;
 
   for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 6ea3b04..c84fd53 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1145,7 +1145,7 @@ update_renderbuffer_read_surfaces(struct brw_context *brw)
/* BRW_NEW_FRAGMENT_PROGRAM */
if (!ctx->Extensions.MESA_shader_framebuffer_fetch &&
brw->fragment_program &&
-   brw->fragment_program->Base.OutputsRead) {
+   brw->fragment_program->Base.nir->info.outputs_read) {
   /* _NEW_BUFFERS */
   const struct gl_framebuffer *fb = ctx->DrawBuffer;
 

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Mesa (master): i965: remove remaining tabs in brw_wm.c

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: a38c809f6e2080da4100f3b4fe432e0b98950ebf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a38c809f6e2080da4100f3b4fe432e0b98950ebf

Author: Timothy Arceri 
Date:   Wed Oct  5 15:42:02 2016 +1100

i965: remove remaining tabs in brw_wm.c

Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_wm.c | 88 +++---
 1 file changed, 44 insertions(+), 44 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm.c 
b/src/mesa/drivers/dri/i965/brw_wm.c
index aac0469..6dcfb80 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -179,10 +179,10 @@ brw_codegen_wm_prog(struct brw_context *brw,
   fprintf(stderr, "\n");
 
brw_upload_cache(>cache, BRW_CACHE_FS_PROG,
-   key, sizeof(struct brw_wm_prog_key),
-   program, program_size,
-   _data, sizeof(prog_data),
-   >wm.base.prog_offset, >wm.base.prog_data);
+key, sizeof(struct brw_wm_prog_key),
+program, program_size,
+_data, sizeof(prog_data),
+>wm.base.prog_offset, >wm.base.prog_data);
 
ralloc_free(mem_ctx);
 
@@ -313,8 +313,8 @@ gen6_gather_workaround(GLenum internalformat)
 
 void
 brw_populate_sampler_prog_key_data(struct gl_context *ctx,
-  const struct gl_program *prog,
-  struct brw_sampler_prog_key_data *key)
+   const struct gl_program *prog,
+   struct brw_sampler_prog_key_data *key)
 {
struct brw_context *brw = brw_context(ctx);
GLbitfield mask = prog->SamplersUsed;
@@ -328,9 +328,9 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
   const struct gl_texture_unit *unit = >Texture.Unit[unit_id];
 
   if (unit->_Current && unit->_Current->Target != GL_TEXTURE_BUFFER) {
-const struct gl_texture_object *t = unit->_Current;
-const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
-struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit_id);
+ const struct gl_texture_object *t = unit->_Current;
+ const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
+ struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, 
unit_id);
 
  const bool alpha_depth = t->DepthMode == GL_ALPHA &&
 (img->_BaseFormat == GL_DEPTH_COMPONENT ||
@@ -342,16 +342,16 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
  if (alpha_depth || (brw->gen < 8 && !brw->is_haswell))
 key->swizzles[s] = brw_get_texture_swizzle(ctx, t);
 
-if (brw->gen < 8 &&
+ if (brw->gen < 8 &&
  sampler->MinFilter != GL_NEAREST &&
-sampler->MagFilter != GL_NEAREST) {
-   if (sampler->WrapS == GL_CLAMP)
-  key->gl_clamp_mask[0] |= 1 << s;
-   if (sampler->WrapT == GL_CLAMP)
-  key->gl_clamp_mask[1] |= 1 << s;
-   if (sampler->WrapR == GL_CLAMP)
-  key->gl_clamp_mask[2] |= 1 << s;
-}
+ sampler->MagFilter != GL_NEAREST) {
+if (sampler->WrapS == GL_CLAMP)
+   key->gl_clamp_mask[0] |= 1 << s;
+if (sampler->WrapT == GL_CLAMP)
+   key->gl_clamp_mask[1] |= 1 << s;
+if (sampler->WrapR == GL_CLAMP)
+   key->gl_clamp_mask[2] |= 1 << s;
+ }
 
  /* gather4's channel select for green from RG32F is broken; requires
   * a shader w/a on IVB; fixable with just SCS on HSW.
@@ -450,26 +450,26 @@ brw_wm_populate_key(struct brw_context *brw, struct 
brw_wm_prog_key *key)
   /* _NEW_COLOR */
   if (fp->program.Base.nir->info.fs.uses_discard ||
   ctx->Color.AlphaEnabled) {
-lookup |= IZ_PS_KILL_ALPHATEST_BIT;
+ lookup |= IZ_PS_KILL_ALPHATEST_BIT;
   }
 
   if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
-lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
+ lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
 
   /* _NEW_DEPTH */
   if (ctx->Depth.Test)
-lookup |= IZ_DEPTH_TEST_ENABLE_BIT;
+ lookup |= IZ_DEPTH_TEST_ENABLE_BIT;
 
   if (ctx->Depth.Test && ctx->Depth.Mask) /* ?? */
-lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
+ lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
 
   /* _NEW_STENCIL | _NEW_BUFFERS */
   if (ctx->Stencil._Enabled) {
-lookup |= IZ_STENCIL_TEST_ENABLE_BIT;
+ lookup |= IZ_STENCIL_TEST_ENABLE_BIT;
 
-if (ctx->Stencil.WriteMask[0] ||
-ctx->Stencil.WriteMask[ctx->Stencil._BackFace])
-   lookup |= IZ_STENCIL_WRITE_ENABLE_BIT;
+ if (ctx->Stencil.WriteMask[0] ||
+ ctx->Stencil.WriteMask[ctx->Stencil._BackFace])
+lookup |= 

Mesa (master): i965: get inputs read from nir info

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 7627fbd9b0ca5eb39acb4f0a2ce9b03c90931ebc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7627fbd9b0ca5eb39acb4f0a2ce9b03c90931ebc

Author: Timothy Arceri 
Date:   Wed Oct  5 16:45:27 2016 +1100

i965: get inputs read from nir info

This is a step towards dropping the GLSL IR version of
do_set_program_inouts() in i965 and moving towards native nir support.

This is important because we want to eventually convert to nir and
use its optimisations passes before we can call this GLSL IR pass.

Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_curbe.c |  4 +++-
 src/mesa/drivers/dri/i965/brw_draw.c  |  2 +-
 src/mesa/drivers/dri/i965/brw_interpolation_map.c |  3 ++-
 src/mesa/drivers/dri/i965/brw_sf.c|  7 +--
 src/mesa/drivers/dri/i965/brw_tcs.c   |  8 +---
 src/mesa/drivers/dri/i965/brw_tes.c   | 10 ++
 src/mesa/drivers/dri/i965/brw_vs.c|  2 +-
 src/mesa/drivers/dri/i965/brw_wm.c| 14 +-
 src/mesa/drivers/dri/i965/gen6_sf_state.c |  4 +++-
 src/mesa/drivers/dri/i965/gen8_sf_state.c |  5 -
 10 files changed, 39 insertions(+), 20 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c 
b/src/mesa/drivers/dri/i965/brw_curbe.c
index 9100a8f..7f9594c 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -50,6 +50,7 @@
  */
 
 
+#include "compiler/nir/nir.h"
 #include "main/context.h"
 #include "main/macros.h"
 #include "main/enums.h"
@@ -324,7 +325,8 @@ emit:
 * BRW_NEW_FRAGMENT_PROGRAM
 */
if (brw->gen == 4 && !brw->is_g4x &&
-   (brw->fragment_program->Base.InputsRead & (1 << VARYING_SLOT_POS))) {
+   (brw->fragment_program->Base.nir->info.inputs_read &
+(1 << VARYING_SLOT_POS))) {
   BEGIN_BATCH(2);
   OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
   OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 0eaa0f2..af98464 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -302,7 +302,7 @@ brw_merge_inputs(struct brw_context *brw,
}
 
if (brw->gen < 8 && !brw->is_haswell) {
-  GLbitfield64 mask = ctx->VertexProgram._Current->Base.InputsRead;
+  uint64_t mask = ctx->VertexProgram._Current->Base.nir->info.inputs_read;
   /* Prior to Haswell, the hardware can't natively support GL_FIXED or
* 2_10_10_10_REV vertex formats.  Set appropriate workaround flags.
*/
diff --git a/src/mesa/drivers/dri/i965/brw_interpolation_map.c 
b/src/mesa/drivers/dri/i965/brw_interpolation_map.c
index 6d0a813..7ca3c05 100644
--- a/src/mesa/drivers/dri/i965/brw_interpolation_map.c
+++ b/src/mesa/drivers/dri/i965/brw_interpolation_map.c
@@ -22,6 +22,7 @@
  */
 
 #include "brw_state.h"
+#include "compiler/nir/nir.h"
 
 static char const *get_qual_name(int mode)
 {
@@ -72,7 +73,7 @@ brw_setup_vue_interpolation(struct brw_context *brw)
   if (varying == VARYING_SLOT_BFC0 || varying == VARYING_SLOT_BFC1)
  frag_attrib = varying - VARYING_SLOT_BFC0 + VARYING_SLOT_COL0;
 
-  if (!(fprog->Base.InputsRead & BITFIELD64_BIT(frag_attrib)))
+  if (!(fprog->Base.nir->info.inputs_read & BITFIELD64_BIT(frag_attrib)))
  continue;
 
   enum glsl_interp_mode mode = fprog->InterpQualifier[frag_attrib];
diff --git a/src/mesa/drivers/dri/i965/brw_sf.c 
b/src/mesa/drivers/dri/i965/brw_sf.c
index 6d8cd74..2090737 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.c
+++ b/src/mesa/drivers/dri/i965/brw_sf.c
@@ -29,7 +29,7 @@
   *   Keith Whitwell 
   */
 
-
+#include "compiler/nir/nir.h"
 #include "main/macros.h"
 #include "main/mtypes.h"
 #include "main/enums.h"
@@ -192,8 +192,11 @@ brw_upload_sf_prog(struct brw_context *brw)
if (key.do_point_sprite) {
   key.point_sprite_coord_replace = ctx->Point.CoordReplace & 0xff;
}
-   if (brw->fragment_program->Base.InputsRead & 
BITFIELD64_BIT(VARYING_SLOT_PNTC))
+   if (brw->fragment_program->Base.nir->info.inputs_read &
+   BITFIELD64_BIT(VARYING_SLOT_PNTC)) {
   key.do_point_coord = 1;
+   }
+
/*
 * Window coordinates in a FBO are inverted, which means point
 * sprite origin must be inverted, too.
diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c 
b/src/mesa/drivers/dri/i965/brw_tcs.c
index 0b69139..f566e77 100644
--- a/src/mesa/drivers/dri/i965/brw_tcs.c
+++ b/src/mesa/drivers/dri/i965/brw_tcs.c
@@ -316,8 +316,10 @@ void
 brw_tcs_populate_key(struct brw_context *brw,
  struct brw_tcs_prog_key *key)
 {
-   uint64_t per_vertex_slots = brw->tess_eval_program->Base.InputsRead;
-   uint32_t per_patch_slots = brw->tess_eval_program->Base.PatchInputsRead;
+   uint64_t per_vertex_slots =
+  

Mesa (master): i965: get uses discard from nir info

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 556335eb9915fc6e00aafa15eaf0265ddc25b131
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=556335eb9915fc6e00aafa15eaf0265ddc25b131

Author: Timothy Arceri 
Date:   Wed Oct  5 15:13:23 2016 +1100

i965: get uses discard from nir info

This is a step towards dropping the GLSL IR version of
do_set_program_inouts() in i965 and moving towards native nir support.

This is important because we want to eventually convert to nir and
use its optimisations passes before we can call this GLSL IR pass.

Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_wm.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm.c 
b/src/mesa/drivers/dri/i965/brw_wm.c
index b0167d2..aac0469 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -448,8 +448,10 @@ brw_wm_populate_key(struct brw_context *brw, struct 
brw_wm_prog_key *key)
 */
if (brw->gen < 6) {
   /* _NEW_COLOR */
-  if (fp->program.UsesKill || ctx->Color.AlphaEnabled)
+  if (fp->program.Base.nir->info.fs.uses_discard ||
+  ctx->Color.AlphaEnabled) {
 lookup |= IZ_PS_KILL_ALPHATEST_BIT;
+  }
 
   if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
 lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
@@ -601,7 +603,7 @@ brw_fs_precompile(struct gl_context *ctx,
memset(, 0, sizeof(key));
 
if (brw->gen < 6) {
-  if (fp->UsesKill)
+  if (fp->Base.nir->info.fs.uses_discard)
  key.iz_lookup |= IZ_PS_KILL_ALPHATEST_BIT;
 
   if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))

___
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mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit

Mesa (master): i965: Eliminate brw->tes.prog_data pointer.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: e512941537fbc25e97ecd778433e130769e2c6ec
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e512941537fbc25e97ecd778433e130769e2c6ec

Author: Kenneth Graunke 
Date:   Thu Sep  8 23:48:53 2016 -0700

i965: Eliminate brw->tes.prog_data pointer.

Just say no to:

-   brw->tes.base.prog_data = >tes.prog_data->base.base;

We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_tes_prog_data as needed.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Timothy Arceri 

---

 src/mesa/drivers/dri/i965/brw_context.h   |  1 -
 src/mesa/drivers/dri/i965/brw_state_cache.c   |  1 -
 src/mesa/drivers/dri/i965/brw_state_upload.c  |  1 -
 src/mesa/drivers/dri/i965/brw_tes.c   | 10 +-
 src/mesa/drivers/dri/i965/brw_tes_surface_state.c |  8 
 src/mesa/drivers/dri/i965/gen6_clip_state.c   |  8 
 src/mesa/drivers/dri/i965/gen7_ds_state.c | 10 ++
 src/mesa/drivers/dri/i965/gen7_te_state.c |  3 ++-
 src/mesa/drivers/dri/i965/gen7_urb.c  |  4 +++-
 src/mesa/drivers/dri/i965/gen8_ds_state.c |  8 +---
 10 files changed, 29 insertions(+), 25 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 3016687..dc93d82 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1110,7 +1110,6 @@ struct brw_context
 
struct {
   struct brw_stage_state base;
-  struct brw_tes_prog_data *prog_data;
 
   /**
* True if the 3DSTATE_DS command most recently emitted to the 3D
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c 
b/src/mesa/drivers/dri/i965/brw_state_cache.c
index b3826f2..9e33182 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -400,7 +400,6 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache 
*cache)
/* Also, NULL out any stale program pointers. */
brw->vs.base.prog_data = NULL;
brw->tcs.base.prog_data = NULL;
-   brw->tes.prog_data = NULL;
brw->tes.base.prog_data = NULL;
brw->gs.prog_data = NULL;
brw->gs.base.prog_data = NULL;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 3a5ddbd..17d1b2d 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -687,7 +687,6 @@ brw_upload_tess_programs(struct brw_context *brw)
   brw_upload_tes_prog(brw);
} else {
   brw->tcs.base.prog_data = NULL;
-  brw->tes.prog_data = NULL;
   brw->tes.base.prog_data = NULL;
}
 }
diff --git a/src/mesa/drivers/dri/i965/brw_tes.c 
b/src/mesa/drivers/dri/i965/brw_tes.c
index ad0eb2e..2c43a3e 100644
--- a/src/mesa/drivers/dri/i965/brw_tes.c
+++ b/src/mesa/drivers/dri/i965/brw_tes.c
@@ -223,7 +223,7 @@ brw_codegen_tes_prog(struct brw_context *brw,
 key, sizeof(*key),
 program, program_size,
 _data, sizeof(prog_data),
-_state->prog_offset, >tes.prog_data);
+_state->prog_offset, >tes.base.prog_data);
ralloc_free(mem_ctx);
 
return true;
@@ -285,13 +285,13 @@ brw_upload_tes_prog(struct brw_context *brw)
 
if (!brw_search_cache(>cache, BRW_CACHE_TES_PROG,
  , sizeof(key),
- _state->prog_offset, >tes.prog_data)) {
+ _state->prog_offset,
+ >tes.base.prog_data)) {
   bool success = brw_codegen_tes_prog(brw, current[MESA_SHADER_TESS_EVAL],
   tep, );
   assert(success);
   (void)success;
}
-   brw->tes.base.prog_data = >tes.prog_data->base.base;
 }
 
 
@@ -303,7 +303,7 @@ brw_tes_precompile(struct gl_context *ctx,
struct brw_context *brw = brw_context(ctx);
struct brw_tes_prog_key key;
uint32_t old_prog_offset = brw->tes.base.prog_offset;
-   struct brw_tes_prog_data *old_prog_data = brw->tes.prog_data;
+   struct brw_stage_prog_data *old_prog_data = brw->tes.base.prog_data;
bool success;
 
struct gl_tess_eval_program *tep = (struct gl_tess_eval_program *)prog;
@@ -331,7 +331,7 @@ brw_tes_precompile(struct gl_context *ctx,
success = brw_codegen_tes_prog(brw, shader_prog, btep, );
 
brw->tes.base.prog_offset = old_prog_offset;
-   brw->tes.prog_data = old_prog_data;
+   brw->tes.base.prog_data = old_prog_data;
 
return success;
 }
diff --git a/src/mesa/drivers/dri/i965/brw_tes_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_tes_surface_state.c
index 13a55e1..b1e85ee 100644
--- a/src/mesa/drivers/dri/i965/brw_tes_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_tes_surface_state.c
@@ -48,7 +48,7 @@ brw_upload_tes_pull_constants(struct brw_context *brw)
   

Mesa (master): i965: Eliminate brw->wm.prog_data pointer.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 16d5536e55aed2aad0596e9385f1962b4ca5db2b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=16d5536e55aed2aad0596e9385f1962b4ca5db2b

Author: Kenneth Graunke 
Date:   Thu Sep  8 23:48:53 2016 -0700

i965: Eliminate brw->wm.prog_data pointer.

Just say no to:

-   brw->wm.base.prog_data = >wm.prog_data->base.base;

We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_wm_prog_data as needed.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Timothy Arceri 

---

 src/mesa/drivers/dri/i965/brw_context.h  |  1 -
 src/mesa/drivers/dri/i965/brw_curbe.c|  6 +++---
 src/mesa/drivers/dri/i965/brw_state_cache.c  |  1 -
 src/mesa/drivers/dri/i965/brw_wm.c   | 10 +-
 src/mesa/drivers/dri/i965/brw_wm_state.c |  3 ++-
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 21 ++---
 src/mesa/drivers/dri/i965/gen6_clip_state.c  |  2 +-
 src/mesa/drivers/dri/i965/gen6_sf_state.c| 12 
 src/mesa/drivers/dri/i965/gen6_wm_state.c|  7 ---
 src/mesa/drivers/dri/i965/gen7_sf_state.c|  6 --
 src/mesa/drivers/dri/i965/gen7_wm_state.c|  6 --
 src/mesa/drivers/dri/i965/gen8_depth_state.c | 19 +--
 src/mesa/drivers/dri/i965/gen8_ps_state.c| 18 ++
 src/mesa/drivers/dri/i965/gen8_sf_state.c|  6 --
 14 files changed, 68 insertions(+), 50 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 5081b07..198161f 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1180,7 +1180,6 @@ struct brw_context
 
struct {
   struct brw_stage_state base;
-  struct brw_wm_prog_data *prog_data;
 
   GLuint render_surf;
 
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c 
b/src/mesa/drivers/dri/i965/brw_curbe.c
index 45bdab1..9100a8f 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -76,7 +76,7 @@ static void calculate_curbe_offsets( struct brw_context *brw )
 {
struct gl_context *ctx = >ctx;
/* BRW_NEW_FS_PROG_DATA */
-   const GLuint nr_fp_regs = (brw->wm.prog_data->base.nr_params + 15) / 16;
+   const GLuint nr_fp_regs = (brw->wm.base.prog_data->nr_params + 15) / 16;
 
/* BRW_NEW_VS_PROG_DATA */
const GLuint nr_vp_regs = (brw->vs.base.prog_data->nr_params + 15) / 16;
@@ -219,8 +219,8 @@ brw_upload_constant_buffer(struct brw_context *brw)
   GLuint offset = brw->curbe.wm_start * 16;
 
   /* BRW_NEW_FS_PROG_DATA | _NEW_PROGRAM_CONSTANTS: copy uniform values */
-  for (i = 0; i < brw->wm.prog_data->base.nr_params; i++) {
-buf[offset + i] = *brw->wm.prog_data->base.param[i];
+  for (i = 0; i < brw->wm.base.prog_data->nr_params; i++) {
+buf[offset + i] = *brw->wm.base.prog_data->param[i];
   }
}
 
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c 
b/src/mesa/drivers/dri/i965/brw_state_cache.c
index ad716d2..ed19d71 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -402,7 +402,6 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache 
*cache)
brw->tcs.base.prog_data = NULL;
brw->tes.base.prog_data = NULL;
brw->gs.base.prog_data = NULL;
-   brw->wm.prog_data = NULL;
brw->wm.base.prog_data = NULL;
brw->cs.prog_data = NULL;
brw->cs.base.prog_data = NULL;
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c 
b/src/mesa/drivers/dri/i965/brw_wm.c
index 64cfd98..5da1a36 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -182,7 +182,7 @@ brw_codegen_wm_prog(struct brw_context *brw,
key, sizeof(struct brw_wm_prog_key),
program, program_size,
_data, sizeof(prog_data),
-   >wm.base.prog_offset, >wm.prog_data);
+   >wm.base.prog_offset, >wm.base.prog_data);
 
ralloc_free(mem_ctx);
 
@@ -578,12 +578,12 @@ brw_upload_wm_prog(struct brw_context *brw)
 
if (!brw_search_cache(>cache, BRW_CACHE_FS_PROG,
 , sizeof(key),
->wm.base.prog_offset, >wm.prog_data)) {
+>wm.base.prog_offset,
+ >wm.base.prog_data)) {
   bool success = brw_codegen_wm_prog(brw, current, fp, );
   (void) success;
   assert(success);
}
-   brw->wm.base.prog_data = >wm.prog_data->base;
 }
 
 bool
@@ -628,12 +628,12 @@ brw_fs_precompile(struct gl_context *ctx,
key.coherent_fb_fetch = ctx->Extensions.MESA_shader_framebuffer_fetch;
 
uint32_t old_prog_offset = brw->wm.base.prog_offset;
-   struct brw_wm_prog_data *old_prog_data = brw->wm.prog_data;
+   struct brw_stage_prog_data *old_prog_data = 

Mesa (master): i965: Eliminate brw->vs.prog_data pointer.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 40258a13d5bf81303585eaf1859fcb85e373be3e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=40258a13d5bf81303585eaf1859fcb85e373be3e

Author: Kenneth Graunke 
Date:   Thu Sep  8 23:48:53 2016 -0700

i965: Eliminate brw->vs.prog_data pointer.

Just say no to:

-   brw->vs.base.prog_data = >vs.prog_data->base.base;

We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_vs_prog_data as needed.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Timothy Arceri 

---

 src/mesa/drivers/dri/i965/brw_context.h  |  1 -
 src/mesa/drivers/dri/i965/brw_curbe.c|  6 ++--
 src/mesa/drivers/dri/i965/brw_draw.c | 14 
 src/mesa/drivers/dri/i965/brw_draw_upload.c  | 43 ++--
 src/mesa/drivers/dri/i965/brw_ff_gs.c|  4 +--
 src/mesa/drivers/dri/i965/brw_state_cache.c  |  1 -
 src/mesa/drivers/dri/i965/brw_state_upload.c |  9 +++--
 src/mesa/drivers/dri/i965/brw_urb.c  |  2 +-
 src/mesa/drivers/dri/i965/brw_vs.c   |  9 +++--
 src/mesa/drivers/dri/i965/brw_vs_state.c | 22 ++--
 src/mesa/drivers/dri/i965/brw_vs_surface_state.c |  8 ++---
 src/mesa/drivers/dri/i965/gen6_clip_state.c  |  2 +-
 src/mesa/drivers/dri/i965/gen6_urb.c |  4 ++-
 src/mesa/drivers/dri/i965/gen6_vs_state.c| 15 +
 src/mesa/drivers/dri/i965/gen7_urb.c |  4 ++-
 src/mesa/drivers/dri/i965/gen7_vs_state.c| 14 
 src/mesa/drivers/dri/i965/gen8_draw_upload.c | 35 ++-
 src/mesa/drivers/dri/i965/gen8_vs_state.c| 24 +++--
 18 files changed, 121 insertions(+), 96 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index dcda574..7bc91a8 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1096,7 +1096,6 @@ struct brw_context
 
struct {
   struct brw_stage_state base;
-  struct brw_vs_prog_data *prog_data;
} vs;
 
struct {
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c 
b/src/mesa/drivers/dri/i965/brw_curbe.c
index 02c4e38..45bdab1 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -79,7 +79,7 @@ static void calculate_curbe_offsets( struct brw_context *brw )
const GLuint nr_fp_regs = (brw->wm.prog_data->base.nr_params + 15) / 16;
 
/* BRW_NEW_VS_PROG_DATA */
-   const GLuint nr_vp_regs = (brw->vs.prog_data->base.base.nr_params + 15) / 
16;
+   const GLuint nr_vp_regs = (brw->vs.base.prog_data->nr_params + 15) / 16;
GLuint nr_clip_regs = 0;
GLuint total_regs;
 
@@ -260,8 +260,8 @@ brw_upload_constant_buffer(struct brw_context *brw)
   GLuint offset = brw->curbe.vs_start * 16;
 
   /* BRW_NEW_VS_PROG_DATA | _NEW_PROGRAM_CONSTANTS: copy uniform values */
-  for (i = 0; i < brw->vs.prog_data->base.base.nr_params; i++) {
- buf[offset + i] = *brw->vs.prog_data->base.base.param[i];
+  for (i = 0; i < brw->vs.base.prog_data->nr_params; i++) {
+ buf[offset + i] = *brw->vs.base.prog_data->param[i];
   }
}
 
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index cab67c9..0eaa0f2 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -521,15 +521,17 @@ brw_try_draw_prims(struct gl_context *ctx,
   const int new_basevertex =
  prims[i].indexed ? prims[i].basevertex : prims[i].start;
   const int new_baseinstance = prims[i].base_instance;
+  const struct brw_vs_prog_data *vs_prog_data =
+ brw_vs_prog_data(brw->vs.base.prog_data);
   if (i > 0) {
  const bool uses_draw_parameters =
-brw->vs.prog_data->uses_basevertex ||
-brw->vs.prog_data->uses_baseinstance;
+vs_prog_data->uses_basevertex ||
+vs_prog_data->uses_baseinstance;
 
  if ((uses_draw_parameters && prims[i].is_indirect) ||
- (brw->vs.prog_data->uses_basevertex &&
+ (vs_prog_data->uses_basevertex &&
   brw->draw.params.gl_basevertex != new_basevertex) ||
- (brw->vs.prog_data->uses_baseinstance &&
+ (vs_prog_data->uses_baseinstance &&
   brw->draw.params.gl_baseinstance != new_baseinstance))
 brw->ctx.NewDriverState |= BRW_NEW_VERTICES;
   }
@@ -556,13 +558,13 @@ brw_try_draw_prims(struct gl_context *ctx,
   /* gl_DrawID always needs its own vertex buffer since it's not part of
* the indirect parameter buffer. If the program uses gl_DrawID we need
* to flag BRW_NEW_VERTICES. For the first iteration, we don't have
-   * valid brw->vs.prog_data, but we always flag BRW_NEW_VERTICES before
+   * valid vs_prog_data, but we always flag BRW_NEW_VERTICES 

Mesa (master): i965: Eliminate brw->cs.prog_data pointer.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: a85a8ecd32202b22e560bdf714b5715a168cc76e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a85a8ecd32202b22e560bdf714b5715a168cc76e

Author: Kenneth Graunke 
Date:   Thu Sep  8 23:48:53 2016 -0700

i965: Eliminate brw->cs.prog_data pointer.

Just say no to:

-   brw->cs.base.prog_data = >cs.prog_data->base.base;

We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_cs_prog_data as needed.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Timothy Arceri 

---

 src/mesa/drivers/dri/i965/brw_compute.c  |  3 ++-
 src/mesa/drivers/dri/i965/brw_context.h  |  1 -
 src/mesa/drivers/dri/i965/brw_cs.c   | 10 +-
 src/mesa/drivers/dri/i965/brw_state_cache.c  |  1 -
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  9 +
 src/mesa/drivers/dri/i965/gen7_cs_state.c| 11 ++-
 6 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_compute.c 
b/src/mesa/drivers/dri/i965/brw_compute.c
index d1d39d3..6e6e425 100644
--- a/src/mesa/drivers/dri/i965/brw_compute.c
+++ b/src/mesa/drivers/dri/i965/brw_compute.c
@@ -115,7 +115,8 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
 static void
 brw_emit_gpgpu_walker(struct brw_context *brw)
 {
-   const struct brw_cs_prog_data *prog_data = brw->cs.prog_data;
+   const struct brw_cs_prog_data *prog_data =
+  brw_cs_prog_data(brw->cs.base.prog_data);
 
const GLuint *num_groups = brw->compute.num_work_groups;
uint32_t indirect_flag;
diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 198161f..c92bb9f 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1195,7 +1195,6 @@ struct brw_context
 
struct {
   struct brw_stage_state base;
-  struct brw_cs_prog_data *prog_data;
} cs;
 
/* RS hardware binding table */
diff --git a/src/mesa/drivers/dri/i965/brw_cs.c 
b/src/mesa/drivers/dri/i965/brw_cs.c
index 4e746fe..e7dcf47 100644
--- a/src/mesa/drivers/dri/i965/brw_cs.c
+++ b/src/mesa/drivers/dri/i965/brw_cs.c
@@ -180,7 +180,7 @@ brw_codegen_cs_prog(struct brw_context *brw,
 key, sizeof(*key),
 program, program_size,
 _data, sizeof(prog_data),
->cs.base.prog_offset, >cs.prog_data);
+>cs.base.prog_offset, >cs.base.prog_data);
ralloc_free(mem_ctx);
 
return true;
@@ -227,7 +227,8 @@ brw_upload_cs_prog(struct brw_context *brw)
 
if (!brw_search_cache(>cache, BRW_CACHE_CS_PROG,
  , sizeof(key),
- >cs.base.prog_offset, >cs.prog_data)) {
+ >cs.base.prog_offset,
+ >cs.base.prog_data)) {
   bool success =
  brw_codegen_cs_prog(brw,
  ctx->Shader.CurrentProgram[MESA_SHADER_COMPUTE],
@@ -235,7 +236,6 @@ brw_upload_cs_prog(struct brw_context *brw)
   (void) success;
   assert(success);
}
-   brw->cs.base.prog_data = >cs.prog_data->base;
 }
 
 
@@ -256,12 +256,12 @@ brw_cs_precompile(struct gl_context *ctx,
brw_setup_tex_for_precompile(brw, , prog);
 
uint32_t old_prog_offset = brw->cs.base.prog_offset;
-   struct brw_cs_prog_data *old_prog_data = brw->cs.prog_data;
+   struct brw_stage_prog_data *old_prog_data = brw->cs.base.prog_data;
 
bool success = brw_codegen_cs_prog(brw, shader_prog, bcp, );
 
brw->cs.base.prog_offset = old_prog_offset;
-   brw->cs.prog_data = old_prog_data;
+   brw->cs.base.prog_data = old_prog_data;
 
return success;
 }
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c 
b/src/mesa/drivers/dri/i965/brw_state_cache.c
index ed19d71..e8e71ab 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -403,7 +403,6 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache 
*cache)
brw->tes.base.prog_data = NULL;
brw->gs.base.prog_data = NULL;
brw->wm.base.prog_data = NULL;
-   brw->cs.prog_data = NULL;
brw->cs.base.prog_data = NULL;
 
intel_batchbuffer_flush(brw);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 11dc7f0..8d5d9a2 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1464,7 +1464,7 @@ brw_upload_cs_ubo_surfaces(struct brw_context *brw)
 
/* BRW_NEW_CS_PROG_DATA */
brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_COMPUTE],
-   >cs.base, >cs.prog_data->base);
+   >cs.base, brw->cs.base.prog_data);
 }
 
 const struct brw_tracked_state brw_cs_ubo_surfaces = {
@@ -1542,7 +1542,7 @@ brw_upload_cs_abo_surfaces(struct brw_context 

Mesa (master): i965: Eliminate brw->gs.prog_data pointer.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: ff366f3db4a117244c6076e5babd440c912200f9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff366f3db4a117244c6076e5babd440c912200f9

Author: Kenneth Graunke 
Date:   Thu Sep  8 23:48:53 2016 -0700

i965: Eliminate brw->gs.prog_data pointer.

Just say no to:

-   brw->gs.base.prog_data = >gs.prog_data->base.base;

We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_gs_prog_data as needed.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Timothy Arceri 

---

 src/mesa/drivers/dri/i965/brw_context.h  |  1 -
 src/mesa/drivers/dri/i965/brw_gs.c   | 11 +++
 src/mesa/drivers/dri/i965/brw_gs_surface_state.c | 12 +++
 src/mesa/drivers/dri/i965/brw_state_cache.c  |  1 -
 src/mesa/drivers/dri/i965/gen6_clip_state.c  | 10 +++---
 src/mesa/drivers/dri/i965/gen6_gs_state.c| 18 ++-
 src/mesa/drivers/dri/i965/gen6_urb.c |  4 ++-
 src/mesa/drivers/dri/i965/gen7_gs_state.c| 31 +-
 src/mesa/drivers/dri/i965/gen7_urb.c |  4 ++-
 src/mesa/drivers/dri/i965/gen8_gs_state.c| 40 +---
 10 files changed, 73 insertions(+), 59 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index dc93d82..5081b07 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1120,7 +1120,6 @@ struct brw_context
 
struct {
   struct brw_stage_state base;
-  struct brw_gs_prog_data *prog_data;
 
   /**
* True if the 3DSTATE_GS command most recently emitted to the 3D
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c 
b/src/mesa/drivers/dri/i965/brw_gs.c
index 9c37d96..a898260 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -191,7 +191,7 @@ brw_codegen_gs_prog(struct brw_context *brw,
 key, sizeof(*key),
 program, program_size,
 _data, sizeof(prog_data),
-_state->prog_offset, >gs.prog_data);
+_state->prog_offset, >gs.base.prog_data);
ralloc_free(mem_ctx);
 
return true;
@@ -248,7 +248,6 @@ brw_upload_gs_prog(struct brw_context *brw)
   /* Other state atoms had better not try to access prog_data, since
* there's no GS program.
*/
-  brw->gs.prog_data = NULL;
   brw->gs.base.prog_data = NULL;
 
   return;
@@ -258,13 +257,13 @@ brw_upload_gs_prog(struct brw_context *brw)
 
if (!brw_search_cache(>cache, BRW_CACHE_GS_PROG,
  , sizeof(key),
- _state->prog_offset, >gs.prog_data)) {
+ _state->prog_offset,
+ >gs.base.prog_data)) {
   bool success = brw_codegen_gs_prog(brw, current[MESA_SHADER_GEOMETRY],
  gp, );
   assert(success);
   (void)success;
}
-   brw->gs.base.prog_data = >gs.prog_data->base.base;
 }
 
 bool
@@ -275,7 +274,7 @@ brw_gs_precompile(struct gl_context *ctx,
struct brw_context *brw = brw_context(ctx);
struct brw_gs_prog_key key;
uint32_t old_prog_offset = brw->gs.base.prog_offset;
-   struct brw_gs_prog_data *old_prog_data = brw->gs.prog_data;
+   struct brw_stage_prog_data *old_prog_data = brw->gs.base.prog_data;
bool success;
 
struct gl_geometry_program *gp = (struct gl_geometry_program *) prog;
@@ -289,7 +288,7 @@ brw_gs_precompile(struct gl_context *ctx,
success = brw_codegen_gs_prog(brw, shader_prog, bgp, );
 
brw->gs.base.prog_offset = old_prog_offset;
-   brw->gs.prog_data = old_prog_data;
+   brw->gs.base.prog_data = old_prog_data;
 
return success;
 }
diff --git a/src/mesa/drivers/dri/i965/brw_gs_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
index f41b449..371255c 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
@@ -48,12 +48,12 @@ brw_upload_gs_pull_constants(struct brw_context *brw)
   return;
 
/* BRW_NEW_GS_PROG_DATA */
-   const struct brw_vue_prog_data *prog_data = >gs.prog_data->base;
+   const struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data;
 
_mesa_shader_write_subroutine_indices(>ctx, MESA_SHADER_GEOMETRY);
/* _NEW_PROGRAM_CONSTANTS */
brw_upload_pull_constants(brw, BRW_NEW_GS_CONSTBUF, >program.Base,
- stage_state, _data->base);
+ stage_state, prog_data);
 }
 
 const struct brw_tracked_state brw_gs_pull_constants = {
@@ -80,10 +80,10 @@ brw_upload_gs_ubo_surfaces(struct brw_context *brw)
   return;
 
/* BRW_NEW_GS_PROG_DATA */
-   struct brw_vue_prog_data *prog_data = >gs.prog_data->base;
+   struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data;
 

Mesa (master): i965: Introduce downcast helpers for prog_data structures.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: e51e055fcdf8107aafaba358fa65b00f963e1728
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e51e055fcdf8107aafaba358fa65b00f963e1728

Author: Kenneth Graunke 
Date:   Thu Sep  8 23:48:51 2016 -0700

i965: Introduce downcast helpers for prog_data structures.

Similar to brw_context(...), intel_texture_object(...), and so on.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Timothy Arceri 

---

 src/mesa/drivers/dri/i965/brw_compiler.h   | 17 ++
 src/mesa/drivers/dri/i965/brw_fs.cpp   | 43 --
 src/mesa/drivers/dri/i965/brw_fs_builder.h |  2 +-
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp |  7 ++---
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp   | 35 +
 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp   | 22 ++---
 src/mesa/drivers/dri/i965/brw_wm_iz.cpp|  2 +-
 7 files changed, 66 insertions(+), 62 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h 
b/src/mesa/drivers/dri/i965/brw_compiler.h
index 445c166..447d05b 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.h
+++ b/src/mesa/drivers/dri/i965/brw_compiler.h
@@ -731,6 +731,23 @@ struct brw_gs_prog_data
unsigned char transform_feedback_swizzles[64 /* BRW_MAX_SOL_BINDINGS */];
 };
 
+#define DEFINE_PROG_DATA_DOWNCAST(stage)   \
+static inline struct brw_##stage##_prog_data * \
+brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
+{  \
+   return (struct brw_##stage##_prog_data *) prog_data;\
+}
+DEFINE_PROG_DATA_DOWNCAST(vue)
+DEFINE_PROG_DATA_DOWNCAST(vs)
+DEFINE_PROG_DATA_DOWNCAST(tcs)
+DEFINE_PROG_DATA_DOWNCAST(tes)
+DEFINE_PROG_DATA_DOWNCAST(gs)
+DEFINE_PROG_DATA_DOWNCAST(wm)
+DEFINE_PROG_DATA_DOWNCAST(cs)
+DEFINE_PROG_DATA_DOWNCAST(ff_gs)
+DEFINE_PROG_DATA_DOWNCAST(clip)
+DEFINE_PROG_DATA_DOWNCAST(sf)
+#undef DEFINE_PROG_DATA_DOWNCAST
 
 /** @} */
 
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 58f5415..1c7a6e6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1125,7 +1125,7 @@ void
 fs_visitor::compute_sample_position(fs_reg dst, fs_reg int_sample_pos)
 {
assert(stage == MESA_SHADER_FRAGMENT);
-   brw_wm_prog_data *wm_prog_data = (brw_wm_prog_data *) this->prog_data;
+   struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(this->prog_data);
assert(dst.type == BRW_REGISTER_TYPE_F);
 
if (wm_prog_data->persample_dispatch) {
@@ -1293,7 +1293,7 @@ fs_reg *
 fs_visitor::emit_samplemaskin_setup()
 {
assert(stage == MESA_SHADER_FRAGMENT);
-   brw_wm_prog_data *wm_prog_data = (brw_wm_prog_data *) this->prog_data;
+   struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(this->prog_data);
assert(devinfo->gen >= 6);
 
fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::int_type));
@@ -1344,7 +1344,7 @@ fs_visitor::resolve_source_modifiers(const fs_reg )
 void
 fs_visitor::emit_discard_jump()
 {
-   assert(((brw_wm_prog_data*) this->prog_data)->uses_kill);
+   assert(brw_wm_prog_data(this->prog_data)->uses_kill);
 
/* For performance, after a discard, jump to the end of the
 * shader if all relevant channels have been discarded.
@@ -1361,8 +1361,7 @@ fs_visitor::emit_gs_thread_end()
 {
assert(stage == MESA_SHADER_GEOMETRY);
 
-   struct brw_gs_prog_data *gs_prog_data =
-  (struct brw_gs_prog_data *) prog_data;
+   struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(prog_data);
 
if (gs_compile->control_data_header_size_bits > 0) {
   emit_gs_control_data_bits(this->final_gs_vertex_count);
@@ -1451,7 +1450,7 @@ void
 fs_visitor::calculate_urb_setup()
 {
assert(stage == MESA_SHADER_FRAGMENT);
-   brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
+   struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
 
memset(prog_data->urb_setup, -1,
@@ -1542,7 +1541,7 @@ void
 fs_visitor::assign_urb_setup()
 {
assert(stage == MESA_SHADER_FRAGMENT);
-   brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
+   struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
 
int urb_start = payload.num_regs + prog_data->base.curb_read_length;
 
@@ -1609,7 +1608,7 @@ fs_visitor::convert_attr_sources_to_hw_regs(fs_inst *inst)
 void
 fs_visitor::assign_vs_urb_setup()
 {
-   brw_vs_prog_data *vs_prog_data = (brw_vs_prog_data *) prog_data;
+   struct brw_vs_prog_data *vs_prog_data = brw_vs_prog_data(prog_data);
 
assert(stage == MESA_SHADER_VERTEX);
 
@@ -1640,7 +1639,7 @@ fs_visitor::assign_tes_urb_setup()
 {
assert(stage == MESA_SHADER_TESS_EVAL);
 
-   brw_vue_prog_data *vue_prog_data = (brw_vue_prog_data *) prog_data;
+   struct brw_vue_prog_data 

Mesa (master): i965: Eliminate brw->tcs.prog_data pointer.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 82c97ac710e31bea1f954060950f8b9faf2fb4d6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=82c97ac710e31bea1f954060950f8b9faf2fb4d6

Author: Kenneth Graunke 
Date:   Thu Sep  8 23:48:53 2016 -0700

i965: Eliminate brw->tcs.prog_data pointer.

Just say no to:

-   brw->tcs.base.prog_data = >tcs.prog_data->base.base;

We'll just use the brw_stage_prog_data pointer in brw_stage_state
and downcast it to brw_tcs_prog_data as needed.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Timothy Arceri 

---

 src/mesa/drivers/dri/i965/brw_context.h   |  1 -
 src/mesa/drivers/dri/i965/brw_state_cache.c   |  1 -
 src/mesa/drivers/dri/i965/brw_state_upload.c  |  1 -
 src/mesa/drivers/dri/i965/brw_tcs.c   | 10 +-
 src/mesa/drivers/dri/i965/brw_tcs_surface_state.c |  8 
 src/mesa/drivers/dri/i965/gen7_hs_state.c | 14 --
 src/mesa/drivers/dri/i965/gen7_urb.c  |  4 +++-
 src/mesa/drivers/dri/i965/gen8_hs_state.c | 14 --
 8 files changed, 28 insertions(+), 25 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 7bc91a8..3016687 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1100,7 +1100,6 @@ struct brw_context
 
struct {
   struct brw_stage_state base;
-  struct brw_tcs_prog_data *prog_data;
 
   /**
* True if the 3DSTATE_HS command most recently emitted to the 3D
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c 
b/src/mesa/drivers/dri/i965/brw_state_cache.c
index 7fc8aa5..b3826f2 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -399,7 +399,6 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache 
*cache)
 
/* Also, NULL out any stale program pointers. */
brw->vs.base.prog_data = NULL;
-   brw->tcs.prog_data = NULL;
brw->tcs.base.prog_data = NULL;
brw->tes.prog_data = NULL;
brw->tes.base.prog_data = NULL;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 6ace37b..3a5ddbd 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -686,7 +686,6 @@ brw_upload_tess_programs(struct brw_context *brw)
   brw_upload_tcs_prog(brw);
   brw_upload_tes_prog(brw);
} else {
-  brw->tcs.prog_data = NULL;
   brw->tcs.base.prog_data = NULL;
   brw->tes.prog_data = NULL;
   brw->tes.base.prog_data = NULL;
diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c 
b/src/mesa/drivers/dri/i965/brw_tcs.c
index 7209ae2..8418861 100644
--- a/src/mesa/drivers/dri/i965/brw_tcs.c
+++ b/src/mesa/drivers/dri/i965/brw_tcs.c
@@ -304,7 +304,7 @@ brw_codegen_tcs_prog(struct brw_context *brw,
 key, sizeof(*key),
 program, program_size,
 _data, sizeof(prog_data),
-_state->prog_offset, >tcs.prog_data);
+_state->prog_offset, >tcs.base.prog_data);
ralloc_free(mem_ctx);
if (!tcs)
   ralloc_free(nir);
@@ -378,13 +378,13 @@ brw_upload_tcs_prog(struct brw_context *brw)
 
if (!brw_search_cache(>cache, BRW_CACHE_TCS_PROG,
  , sizeof(key),
- _state->prog_offset, >tcs.prog_data)) {
+ _state->prog_offset,
+ >tcs.base.prog_data)) {
   bool success = brw_codegen_tcs_prog(brw, current[MESA_SHADER_TESS_CTRL],
   tcp, );
   assert(success);
   (void)success;
}
-   brw->tcs.base.prog_data = >tcs.prog_data->base.base;
 }
 
 
@@ -396,7 +396,7 @@ brw_tcs_precompile(struct gl_context *ctx,
struct brw_context *brw = brw_context(ctx);
struct brw_tcs_prog_key key;
uint32_t old_prog_offset = brw->tcs.base.prog_offset;
-   struct brw_tcs_prog_data *old_prog_data = brw->tcs.prog_data;
+   struct brw_stage_prog_data *old_prog_data = brw->tcs.base.prog_data;
bool success;
 
struct gl_tess_ctrl_program *tcp = (struct gl_tess_ctrl_program *)prog;
@@ -430,7 +430,7 @@ brw_tcs_precompile(struct gl_context *ctx,
success = brw_codegen_tcs_prog(brw, shader_prog, btcp, );
 
brw->tcs.base.prog_offset = old_prog_offset;
-   brw->tcs.prog_data = old_prog_data;
+   brw->tcs.base.prog_data = old_prog_data;
 
return success;
 }
diff --git a/src/mesa/drivers/dri/i965/brw_tcs_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_tcs_surface_state.c
index 4f7759e..5021e10 100644
--- a/src/mesa/drivers/dri/i965/brw_tcs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_tcs_surface_state.c
@@ -48,7 +48,7 @@ brw_upload_tcs_pull_constants(struct brw_context *brw)
   return;
 
/* BRW_NEW_TCS_PROG_DATA */
-   const struct 

Mesa (master): i965/sync: Rename awkward variable

[Chad Versace]

Module: Mesa
Branch: master
Commit: 74b02a744913ffaaf409feb0df30aaa92188e250
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=74b02a744913ffaaf409feb0df30aaa92188e250

Author: Chad Versace 
Date:   Tue Sep 27 23:33:46 2016 -0700

i965/sync: Rename awkward variable

What is the difference between a 'driver_fence' and a 'fence'? Do the
characters 'driver_' add anything helpful? Nope. They do, though, add an
extra 7 chars and pull your eyeballs away to ask "huh? what's that?" one
microsecond too many.

Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_sync.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_sync.c 
b/src/mesa/drivers/dri/i965/brw_sync.c
index cecf3c3..1df5610 100644
--- a/src/mesa/drivers/dri/i965/brw_sync.c
+++ b/src/mesa/drivers/dri/i965/brw_sync.c
@@ -258,27 +258,27 @@ brw_dri_create_fence(__DRIcontext *ctx)
 }
 
 static void
-brw_dri_destroy_fence(__DRIscreen *dri_screen, void *driver_fence)
+brw_dri_destroy_fence(__DRIscreen *dri_screen, void *_fence)
 {
-   struct brw_fence *fence = driver_fence;
+   struct brw_fence *fence = _fence;
 
brw_fence_finish(fence);
free(fence);
 }
 
 static GLboolean
-brw_dri_client_wait_sync(__DRIcontext *ctx, void *driver_fence, unsigned flags,
+brw_dri_client_wait_sync(__DRIcontext *ctx, void *_fence, unsigned flags,
  uint64_t timeout)
 {
-   struct brw_fence *fence = driver_fence;
+   struct brw_fence *fence = _fence;
 
return brw_fence_client_wait(fence->brw, fence, timeout);
 }
 
 static void
-brw_dri_server_wait_sync(__DRIcontext *ctx, void *driver_fence, unsigned flags)
+brw_dri_server_wait_sync(__DRIcontext *ctx, void *_fence, unsigned flags)
 {
-   struct brw_fence *fence = driver_fence;
+   struct brw_fence *fence = _fence;
 
/* We might be called here with a NULL fence as a result of WaitSyncKHR
 * on a EGL_KHR_reusable_sync fence. Nothing to do here in such case.

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Mesa (master): i965/sync: Fix uninitalized usage and leak of mutex

[Chad Versace]

Module: Mesa
Branch: master
Commit: ce1d67c2e5916e97bb65c0bd3b782efca7d3dea5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ce1d67c2e5916e97bb65c0bd3b782efca7d3dea5

Author: Chad Versace 
Date:   Tue Sep 27 23:33:45 2016 -0700

i965/sync: Fix uninitalized usage and leak of mutex

We locked an unitialized mutex in the callstack
glClientWaitSync
intel_gl_client_wait_sync
brw_fence_client_wait_sync
because we forgot to initialize it in intel_gl_fence_sync.
(The EGLSync codepath didn't have this bug. It initialized the mutex in
intel_dri_create_sync).

We also forgot to tear down (mtx_destroy) the mutex when destroying
the sync object.

Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/intel_syncobj.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_syncobj.c 
b/src/mesa/drivers/dri/i965/intel_syncobj.c
index dfda448..4276f3f 100644
--- a/src/mesa/drivers/dri/i965/intel_syncobj.c
+++ b/src/mesa/drivers/dri/i965/intel_syncobj.c
@@ -58,10 +58,20 @@ struct intel_gl_sync_object {
 };
 
 static void
+brw_fence_init(struct brw_context *brw, struct brw_fence *fence)
+{
+   fence->brw = brw;
+   fence->batch_bo = NULL;
+   mtx_init(>mutex, mtx_plain);
+}
+
+static void
 brw_fence_finish(struct brw_fence *fence)
 {
if (fence->batch_bo)
   drm_intel_bo_unreference(fence->batch_bo);
+
+   mtx_destroy(>mutex);
 }
 
 static void
@@ -186,6 +196,7 @@ intel_gl_fence_sync(struct gl_context *ctx, struct 
gl_sync_object *s,
struct brw_context *brw = brw_context(ctx);
struct intel_gl_sync_object *sync = (struct intel_gl_sync_object *)s;
 
+   brw_fence_init(brw, >fence);
brw_fence_insert(brw, >fence);
 }
 
@@ -240,8 +251,7 @@ intel_dri_create_fence(__DRIcontext *ctx)
if (!fence)
   return NULL;
 
-   mtx_init(>mutex, mtx_plain);
-   fence->brw = brw;
+   brw_fence_init(brw, fence);
brw_fence_insert(brw, fence);
 
return fence;

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Mesa (master): i965/sync: Replace 'intel' prefix with 'brw'

[Chad Versace]

Module: Mesa
Branch: master
Commit: 9ea48fc877f1b0d78edb37cafb4067bab776a74a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ea48fc877f1b0d78edb37cafb4067bab776a74a

Author: Chad Versace 
Date:   Tue Sep 27 23:33:45 2016 -0700

i965/sync: Replace 'intel' prefix with 'brw'

This is yet another patch for the great renaming begun long ago.

Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_context.c   |  2 +-
 src/mesa/drivers/dri/i965/brw_context.h   |  2 +-
 src/mesa/drivers/dri/i965/intel_syncobj.c | 70 +++
 3 files changed, 37 insertions(+), 37 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index db63d92..7a39fe2 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -444,7 +444,7 @@ brw_init_driver_functions(struct brw_context *brw,
intelInitBufferFuncs(functions);
intelInitPixelFuncs(functions);
intelInitBufferObjectFuncs(functions);
-   intel_init_syncobj_functions(functions);
+   brw_init_syncobj_functions(functions);
brw_init_object_purgeable_functions(functions);
 
brwInitFragProgFuncs( functions );
diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index b27fe51..a737c2d 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1604,7 +1604,7 @@ extern int intel_translate_stencil_op(GLenum op);
 extern int intel_translate_logic_op(GLenum opcode);
 
 /* intel_syncobj.c */
-void intel_init_syncobj_functions(struct dd_function_table *functions);
+void brw_init_syncobj_functions(struct dd_function_table *functions);
 
 /* gen6_sol.c */
 struct gl_transform_feedback_object *
diff --git a/src/mesa/drivers/dri/i965/intel_syncobj.c 
b/src/mesa/drivers/dri/i965/intel_syncobj.c
index 4276f3f..cecf3c3 100644
--- a/src/mesa/drivers/dri/i965/intel_syncobj.c
+++ b/src/mesa/drivers/dri/i965/intel_syncobj.c
@@ -52,8 +52,8 @@ struct brw_fence {
bool signalled;
 };
 
-struct intel_gl_sync_object {
-   struct gl_sync_object Base;
+struct brw_gl_sync {
+   struct gl_sync_object gl;
struct brw_fence fence;
 };
 
@@ -169,80 +169,80 @@ brw_fence_server_wait(struct brw_context *brw, struct 
brw_fence *fence)
 }
 
 static struct gl_sync_object *
-intel_gl_new_sync_object(struct gl_context *ctx, GLuint id)
+brw_gl_new_sync(struct gl_context *ctx, GLuint id)
 {
-   struct intel_gl_sync_object *sync;
+   struct brw_gl_sync *sync;
 
sync = calloc(1, sizeof(*sync));
if (!sync)
   return NULL;
 
-   return >Base;
+   return >gl;
 }
 
 static void
-intel_gl_delete_sync_object(struct gl_context *ctx, struct gl_sync_object *s)
+brw_gl_delete_sync(struct gl_context *ctx, struct gl_sync_object *_sync)
 {
-   struct intel_gl_sync_object *sync = (struct intel_gl_sync_object *)s;
+   struct brw_gl_sync *sync = (struct brw_gl_sync *) _sync;
 
brw_fence_finish(>fence);
free(sync);
 }
 
 static void
-intel_gl_fence_sync(struct gl_context *ctx, struct gl_sync_object *s,
-GLenum condition, GLbitfield flags)
+brw_gl_fence_sync(struct gl_context *ctx, struct gl_sync_object *_sync,
+  GLenum condition, GLbitfield flags)
 {
struct brw_context *brw = brw_context(ctx);
-   struct intel_gl_sync_object *sync = (struct intel_gl_sync_object *)s;
+   struct brw_gl_sync *sync = (struct brw_gl_sync *) _sync;
 
brw_fence_init(brw, >fence);
brw_fence_insert(brw, >fence);
 }
 
 static void
-intel_gl_client_wait_sync(struct gl_context *ctx, struct gl_sync_object *s,
-  GLbitfield flags, GLuint64 timeout)
+brw_gl_client_wait_sync(struct gl_context *ctx, struct gl_sync_object *_sync,
+GLbitfield flags, GLuint64 timeout)
 {
struct brw_context *brw = brw_context(ctx);
-   struct intel_gl_sync_object *sync = (struct intel_gl_sync_object *)s;
+   struct brw_gl_sync *sync = (struct brw_gl_sync *) _sync;
 
if (brw_fence_client_wait(brw, >fence, timeout))
-  s->StatusFlag = 1;
+  sync->gl.StatusFlag = 1;
 }
 
 static void
-intel_gl_server_wait_sync(struct gl_context *ctx, struct gl_sync_object *s,
+brw_gl_server_wait_sync(struct gl_context *ctx, struct gl_sync_object *_sync,
   GLbitfield flags, GLuint64 timeout)
 {
struct brw_context *brw = brw_context(ctx);
-   struct intel_gl_sync_object *sync = (struct intel_gl_sync_object *)s;
+   struct brw_gl_sync *sync = (struct brw_gl_sync *) _sync;
 
brw_fence_server_wait(brw, >fence);
 }
 
 static void
-intel_gl_check_sync(struct gl_context *ctx, struct gl_sync_object *s)
+brw_gl_check_sync(struct gl_context *ctx, struct gl_sync_object *_sync)
 {
-   struct intel_gl_sync_object *sync = (struct intel_gl_sync_object *)s;
+   struct brw_gl_sync *sync = (struct brw_gl_sync *) _sync;
 
   

Mesa (master): nir: Use the correct infos structure for copying atomic sources

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 28ab2570c8994993acf199e6c728c0f316bf253a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=28ab2570c8994993acf199e6c728c0f316bf253a

Author: Jason Ekstrand 
Date:   Wed Oct  5 12:12:33 2016 -0700

nir: Use the correct infos structure for copying atomic sources

Signed-off-by: Jason Ekstrand 
Reviewed-by: Connor Abbott 
Tested-by: Mark Janes 
Cc: "12.0" 

---

 src/compiler/nir/nir_lower_io.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c
index d469b61..a3b1423 100644
--- a/src/compiler/nir/nir_lower_io.c
+++ b/src/compiler/nir/nir_lower_io.c
@@ -327,7 +327,7 @@ lower_atomic(nir_intrinsic_instr *intrin, struct 
lower_io_state *state,
nir_intrinsic_set_base(atomic, var->data.driver_location);
 
atomic->src[0] = nir_src_for_ssa(offset);
-   for (unsigned i = 0; i < nir_op_infos[intrin->intrinsic].num_inputs; i++) {
+   for (unsigned i = 0; i < nir_intrinsic_infos[intrin->intrinsic].num_srcs; 
i++) {
   nir_src_copy(>src[i+1], >src[i], atomic);
}
 

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Mesa (master): radeonsi: interpolate colors after interpolation weight shuffling

[Marek Olšák]

Module: Mesa
Branch: master
Commit: d4a8bf89ce357ef153e9a1f712f3c3ec3d8904d6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4a8bf89ce357ef153e9a1f712f3c3ec3d8904d6

Author: Marek Olšák 
Date:   Tue Oct  4 21:08:17 2016 +0200

radeonsi: interpolate colors after interpolation weight shuffling

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_shader.c | 96 
 1 file changed, 48 insertions(+), 48 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index aa0a578..bb9131b 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -7285,54 +7285,6 @@ static bool si_compile_ps_prolog(struct si_screen 
*sscreen,
}
}
 
-   /* Interpolate colors. */
-   for (i = 0; i < 2; i++) {
-   unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 
0xf;
-   unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
-key->ps_prolog.face_vgpr_index;
-   LLVMValueRef interp[2], color[4];
-   LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
-
-   if (!writemask)
-   continue;
-
-   /* If the interpolation qualifier is not CONSTANT (-1). */
-   if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
-   unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
-  
key->ps_prolog.color_interp_vgpr_index[i];
-
-   /* Get the (i,j) updated by bc_optimize handling. */
-   interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
- interp_vgpr, "");
-   interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
- interp_vgpr + 1, "");
-   interp_ij = lp_build_gather_values(gallivm, interp, 2);
-   interp_ij = LLVMBuildBitCast(gallivm->builder, 
interp_ij,
-ctx.v2i32, "");
-   }
-
-   /* Use the absolute location of the input. */
-   prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
-
-   if (key->ps_prolog.states.color_two_side) {
-   face = LLVMGetParam(func, face_vgpr);
-   face = LLVMBuildBitCast(gallivm->builder, face, 
ctx.i32, "");
-   }
-
-   interp_fs_input(,
-   key->ps_prolog.color_attr_index[i],
-   TGSI_SEMANTIC_COLOR, i,
-   key->ps_prolog.num_interp_inputs,
-   key->ps_prolog.colors_read, interp_ij,
-   prim_mask, face, color);
-
-   while (writemask) {
-   unsigned chan = u_bit_scan();
-   ret = LLVMBuildInsertValue(gallivm->builder, ret, 
color[chan],
-  num_params++, "");
-   }
-   }
-
/* Force per-sample interpolation. */
if (key->ps_prolog.states.force_persp_sample_interp) {
unsigned i, base = key->ps_prolog.num_input_sgprs;
@@ -7401,6 +7353,54 @@ static bool si_compile_ps_prolog(struct si_screen 
*sscreen,
   linear_center[i], base + 10 
+ i, "");
}
 
+   /* Interpolate colors. */
+   for (i = 0; i < 2; i++) {
+   unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 
0xf;
+   unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
+key->ps_prolog.face_vgpr_index;
+   LLVMValueRef interp[2], color[4];
+   LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
+
+   if (!writemask)
+   continue;
+
+   /* If the interpolation qualifier is not CONSTANT (-1). */
+   if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
+   unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
+  
key->ps_prolog.color_interp_vgpr_index[i];
+
+   /* Get the (i,j) updated by bc_optimize handling. */
+   interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
+ interp_vgpr, "");
+   interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
+ interp_vgpr + 1, "");
+   interp_ij = lp_build_gather_values(gallivm, interp, 2);
+   interp_ij = 

Mesa (master): radeonsi: fix interpolateAt opcodes for .zw components

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 1b37e5541c7d74c50124e5220936bd4b0234df6d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b37e5541c7d74c50124e5220936bd4b0234df6d

Author: Marek Olšák 
Date:   Tue Oct  4 22:33:03 2016 +0200

radeonsi: fix interpolateAt opcodes for .zw components

Not returning garbage in .zw seems pretty important.

This fixes:
GL45-CTS.shader_multisample_interpolation.render.interpolate_at_*_check.*

Cc: 11.2 12.0 
Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_shader.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index bb9131b..ff51c8b 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -5208,7 +5208,7 @@ static void build_interp_intrinsic(const struct 
lp_build_tgsi_action *action,
}
 
intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
-   for (chan = 0; chan < 2; chan++) {
+   for (chan = 0; chan < 4; chan++) {
LLVMValueRef args[4];
LLVMValueRef llvm_chan;
unsigned schan;

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Mesa (master): tgsi/scan: don' t set interp flags for inputs only used by INTERP (v2)

[Marek Olšák]

Module: Mesa
Branch: master
Commit: faee2d6dda6498bde60ff13e1753f7d32019890c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=faee2d6dda6498bde60ff13e1753f7d32019890c

Author: Marek Olšák 
Date:   Thu Sep  8 19:12:00 2016 +0200

tgsi/scan: don't set interp flags for inputs only used by INTERP (v2)

(v1 pushed, then reverted)

This fixes 9 randomly failing tests on radeonsi:
  GL45-CTS.shader_multisample_interpolation.render.interpolate_at_centroid.*

v2: use input_interpolate[input] (correct) instead of
input_interpolate[index] (incorrect)

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/auxiliary/tgsi/tgsi_scan.c | 105 ++---
 1 file changed, 57 insertions(+), 48 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c 
b/src/gallium/auxiliary/tgsi/tgsi_scan.c
index a3b0d9f..c7745ce 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
@@ -102,6 +102,7 @@ scan_instruction(struct tgsi_shader_info *info,
 {
unsigned i;
bool is_mem_inst = false;
+   bool is_interp_instruction = false;
 
assert(fullinst->Instruction.Opcode < TGSI_OPCODE_LAST);
info->opcode_count[fullinst->Instruction.Opcode]++;
@@ -127,6 +128,8 @@ scan_instruction(struct tgsi_shader_info *info,
   const struct tgsi_full_src_register *src0 = >Src[0];
   unsigned input;
 
+  is_interp_instruction = true;
+
   if (src0->Register.Indirect && src0->Indirect.ArrayID)
  input = info->input_array_first[src0->Indirect.ArrayID];
   else
@@ -190,12 +193,16 @@ scan_instruction(struct tgsi_shader_info *info,
 info->input_usage_mask[ind] |= usage_mask;
  }
 
- if (info->processor == PIPE_SHADER_FRAGMENT &&
- !src->Register.Indirect) {
-unsigned name =
-   info->input_semantic_name[src->Register.Index];
-unsigned index =
-   info->input_semantic_index[src->Register.Index];
+ if (info->processor == PIPE_SHADER_FRAGMENT) {
+unsigned name, index, input;
+
+if (src->Register.Indirect && src->Indirect.ArrayID)
+   input = info->input_array_first[src->Indirect.ArrayID];
+else
+   input = src->Register.Index;
+
+name = info->input_semantic_name[input];
+index = info->input_semantic_index[input];
 
 if (name == TGSI_SEMANTIC_POSITION &&
 (src->Register.SwizzleX == TGSI_SWIZZLE_Z ||
@@ -213,6 +220,50 @@ scan_instruction(struct tgsi_shader_info *info,
 
info->colors_read |= mask << (index * 4);
 }
+
+/* Process only interpolated varyings. Don't include POSITION.
+ * Don't include integer varyings, because they are not
+ * interpolated. Don't process inputs interpolated by INTERP
+ * opcodes. Those are tracked separately.
+ */
+if ((!is_interp_instruction || i != 0) &&
+(name == TGSI_SEMANTIC_GENERIC ||
+ name == TGSI_SEMANTIC_TEXCOORD ||
+ name == TGSI_SEMANTIC_COLOR ||
+ name == TGSI_SEMANTIC_BCOLOR ||
+ name == TGSI_SEMANTIC_FOG ||
+ name == TGSI_SEMANTIC_CLIPDIST)) {
+   switch (info->input_interpolate[input]) {
+   case TGSI_INTERPOLATE_COLOR:
+   case TGSI_INTERPOLATE_PERSPECTIVE:
+  switch (info->input_interpolate_loc[input]) {
+  case TGSI_INTERPOLATE_LOC_CENTER:
+ info->uses_persp_center = TRUE;
+ break;
+  case TGSI_INTERPOLATE_LOC_CENTROID:
+ info->uses_persp_centroid = TRUE;
+ break;
+  case TGSI_INTERPOLATE_LOC_SAMPLE:
+ info->uses_persp_sample = TRUE;
+ break;
+  }
+  break;
+   case TGSI_INTERPOLATE_LINEAR:
+  switch (info->input_interpolate_loc[input]) {
+  case TGSI_INTERPOLATE_LOC_CENTER:
+ info->uses_linear_center = TRUE;
+ break;
+  case TGSI_INTERPOLATE_LOC_CENTROID:
+ info->uses_linear_centroid = TRUE;
+ break;
+  case TGSI_INTERPOLATE_LOC_SAMPLE:
+ info->uses_linear_sample = TRUE;
+ break;
+  }
+  break;
+  /* TGSI_INTERPOLATE_CONSTANT doesn't do any interpolation. */
+   }
+}
  }
   }
 
@@ -357,48 +408,6 @@ scan_declaration(struct tgsi_shader_info *info,
 assert(reg < info->num_inputs);
  }
 
- /* Only interpolated varyings. Don't include POSITION.
-  * Don't include integer varyings, because they are not
-  

Mesa (master): radeonsi: add assertions to validate interpolation flags

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 300a8221e92b91c1c759cdd331052a53506d6e93
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=300a8221e92b91c1c759cdd331052a53506d6e93

Author: Marek Olšák 
Date:   Tue Oct  4 19:53:53 2016 +0200

radeonsi: add assertions to validate interpolation flags

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_state_shaders.c | 34 +
 1 file changed, 34 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c 
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 9662625..f6bd129 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -693,6 +693,40 @@ static void si_shader_ps(struct si_shader *shader)
   G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
   G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
   G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
+   /* POS_W_FLOAT_ENA requires one of the perspective weights. */
+   assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
+  G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
+  G_0286CC_PERSP_CENTER_ENA(input_ena) ||
+  G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
+  G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
+
+   /* Validate interpolation optimization flags (read as implications). */
+   assert(!shader->key.ps.prolog.bc_optimize_for_persp ||
+  (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
+   G_0286CC_PERSP_CENTROID_ENA(input_ena)));
+   assert(!shader->key.ps.prolog.bc_optimize_for_linear ||
+  (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
+   G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
+   assert(!shader->key.ps.prolog.force_persp_center_interp ||
+  (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
+   !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
+   assert(!shader->key.ps.prolog.force_linear_center_interp ||
+  (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
+   !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
+   assert(!shader->key.ps.prolog.force_persp_sample_interp ||
+  (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
+   !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
+   assert(!shader->key.ps.prolog.force_linear_sample_interp ||
+  (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
+   !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
+
+   /* Validate cases when the optimizations are off (read as 
implications). */
+   assert(shader->key.ps.prolog.bc_optimize_for_persp ||
+  !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
+  !G_0286CC_PERSP_CENTROID_ENA(input_ena));
+   assert(shader->key.ps.prolog.bc_optimize_for_linear ||
+  !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
+  !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
 
pm4 = si_get_shader_pm4_state(shader);
if (!pm4)

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Mesa (master): gallium/radeon/winsyses: set reasonable max_alloc_size

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 844f8268e1cde496a854a72e080558f3c5700583
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=844f8268e1cde496a854a72e080558f3c5700583

Author: Marek Olšák 
Date:   Tue Oct  4 23:29:27 2016 +0200

gallium/radeon/winsyses: set reasonable max_alloc_size

which is returned for GL_MAX_TEXTURE_BUFFER_SIZE.
It doesn't have any other use at the moment.
Bigger allocations are not rejected.

This fixes GL45-CTS.texture_buffer.texture_buffer_max_size on Bonaire.

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 4 ++--
 src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 4 +++-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index c28e1ca..98d72bd 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -318,8 +318,8 @@ static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
/* Set hardware information. */
ws->info.gart_size = gtt.heap_size;
ws->info.vram_size = vram.heap_size;
-   /* TODO: the kernel reports vram/gart.max_allocation == 251 MB (bug?) */
-   ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size);
+   /* The kernel can split large buffers, so we can do large allocations. */
+   ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size) * 
0.9;
/* convert the shader clock from KHz to MHz */
ws->info.max_shader_clock = ws->amdinfo.max_engine_clk / 1000;
ws->info.max_se = ws->amdinfo.num_shader_engines;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index c7ceee2..70f061c 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -373,7 +373,9 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
 ws->info.gart_size = gem_info.gart_size;
 ws->info.vram_size = gem_info.vram_size;
 
-ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size);
+/* Radeon allocates all buffers as contigous, which makes large allocations
+ * unlikely to succeed. */
+ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size) * 
0.7;
 if (ws->info.drm_minor < 40)
 ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 256*1024*1024);
 

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Mesa (master): radeonsi: fix texture border colors for compute shaders

[Marek Olšák]

Module: Mesa
Branch: master
Commit: cc4a19c4ad5b617af632ce732ccbfeb4b4043114
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc4a19c4ad5b617af632ce732ccbfeb4b4043114

Author: Marek Olšák 
Date:   Wed Oct  5 01:49:30 2016 +0200

radeonsi: fix texture border colors for compute shaders

There are VM faults without this.

Cc: 12.0 
Acked-by: Edward O'Callaghan 
Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_compute.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_compute.c 
b/src/gallium/drivers/radeonsi/si_compute.c
index 9a5a4a9..1d1df2f 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -208,6 +208,7 @@ static void si_set_global_binding(
 static void si_initialize_compute(struct si_context *sctx)
 {
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+   uint64_t bc_va;
 
radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
radeon_emit(cs, 0);
@@ -242,6 +243,17 @@ static void si_initialize_compute(struct si_context *sctx)
  0x190 /* Default value */);
}
 
+   /* Set the pointer to border colors. */
+   bc_va = sctx->border_color_buffer->gpu_address;
+
+   if (sctx->b.chip_class >= CIK) {
+   radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
+   radeon_emit(cs, bc_va >> 8);  /* R_030E00_TA_CS_BC_BASE_ADDR */
+   radeon_emit(cs, bc_va >> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI 
*/
+   } else {
+   radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 
8);
+   }
+
sctx->cs_shader_state.emitted_program = NULL;
sctx->cs_shader_state.initialized = true;
 }

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Mesa (master): ddebug: dump most driver information with GALLIUM_DDEBUG= always

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 10e5f126dd08849d9d209c8c0b80f2d2f6527571
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=10e5f126dd08849d9d209c8c0b80f2d2f6527571

Author: Marek Olšák 
Date:   Wed Oct  5 00:06:10 2016 +0200

ddebug: dump most driver information with GALLIUM_DDEBUG=always

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/ddebug/dd_draw.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/ddebug/dd_draw.c 
b/src/gallium/drivers/ddebug/dd_draw.c
index 511daf4..970712c 100644
--- a/src/gallium/drivers/ddebug/dd_draw.c
+++ b/src/gallium/drivers/ddebug/dd_draw.c
@@ -1110,7 +1110,11 @@ dd_after_draw(struct dd_context *dctx, struct dd_call 
*call)
   case DD_DUMP_ALL_CALLS:
  if (!dscreen->no_flush)
 pipe->flush(pipe, NULL, 0);
- dd_write_report(dctx, call, 0, false);
+ dd_write_report(dctx, call,
+ PIPE_DUMP_CURRENT_STATES |
+ PIPE_DUMP_CURRENT_SHADERS |
+ PIPE_DUMP_LAST_COMMAND_BUFFER,
+ false);
  break;
   case DD_DUMP_APITRACE_CALL:
  if (dscreen->apitrace_dump_call ==

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Mesa (master): nv50/ra: let simplify return an error and handle that

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: d8bcd3ef3723e14a9deabd1cab35b13d80fbbcea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8bcd3ef3723e14a9deabd1cab35b13d80fbbcea

Author: Karol Herbst 
Date:   Mon Oct  3 18:55:09 2016 +0200

nv50/ra: let simplify return an error and handle that

fixes a crash in the case simplify reports an error

Signed-off-by: Karol Herbst 
Reviewed-by: Ilia Mirkin 
Reviewed-by: Samuel Pitoiset 

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index 2d3486b..7e64f7c 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
@@ -771,7 +771,7 @@ private:
bool coalesce(ArrayList&);
bool doCoalesce(ArrayList&, unsigned int mask);
void calculateSpillWeights();
-   void simplify();
+   bool simplify();
bool selectRegisters();
void cleanup(const bool success);
 
@@ -1305,7 +1305,7 @@ GCRA::simplifyNode(RIG_Node *node)
 (node->degree < node->degreeLimit) ? "" : "(spill)");
 }
 
-void
+bool
 GCRA::simplify()
 {
for (;;) {
@@ -1330,11 +1330,11 @@ GCRA::simplify()
  }
  if (isinf(bestScore)) {
 ERROR("no viable spill candidates left\n");
-break;
+return false;
  }
  simplifyNode(best);
   } else {
- break;
+ return true;
   }
}
 }
@@ -1493,7 +1493,9 @@ GCRA::allocateRegisters(ArrayList& insns)
 
buildRIG(insns);
calculateSpillWeights();
-   simplify();
+   ret = simplify();
+   if (!ret)
+  goto out;
 
ret = selectRegisters();
if (!ret) {

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Mesa (master): intel/blorp: Use documented RECTLIST vertex positions

[Nanley Chery]

Module: Mesa
Branch: master
Commit: f315c4f18987dc22d367361c1641a990eded42d6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f315c4f18987dc22d367361c1641a990eded42d6

Author: Nanley Chery 
Date:   Wed Oct  5 09:32:52 2016 -0700

intel/blorp: Use documented RECTLIST vertex positions

Use the vertex positions described in the PRMs. This has no effect on
rendering but quiets the simulator warnings seen when the vertices
appear out of order.

Signed-off-by: Nanley Chery 
Reviewed-by: Jason Ekstrand 
Reviewed-by: Ben Widawsky 

---

 src/intel/blorp/blorp_genX_exec.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index eb4a5b9..62f16a3 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -171,8 +171,8 @@ blorp_emit_vertex_data(struct blorp_batch *batch,
uint32_t *size)
 {
const float vertices[] = {
-  /* v0 */ (float)params->x0, (float)params->y1,
-  /* v1 */ (float)params->x1, (float)params->y1,
+  /* v0 */ (float)params->x1, (float)params->y1,
+  /* v1 */ (float)params->x0, (float)params->y1,
   /* v2 */ (float)params->x0, (float)params->y0,
};
 
@@ -287,7 +287,7 @@ blorp_emit_vertex_elements(struct blorp_batch *batch,
 *   v2 -- implied
 *||
 *||
-*   v0 - v1
+*   v1 - v0
 *
 * Since the VS is disabled, the clipper loads each VUE directly from
 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and

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Mesa (master): anv: Use blorp for VkCmdFillBuffer

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: f027609a64dffbe09fdf4b24fed4bcdc8e0cafb2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f027609a64dffbe09fdf4b24fed4bcdc8e0cafb2

Author: Jason Ekstrand 
Date:   Sun Sep 25 08:44:40 2016 -0700

anv: Use blorp for VkCmdFillBuffer

Signed-off-by: Jason Ekstrand 
Reviewed-by: Nanley Chery 

---

 src/intel/vulkan/anv_blorp.c  | 106 +
 src/intel/vulkan/anv_meta_clear.c | 120 --
 2 files changed, 96 insertions(+), 130 deletions(-)

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index cb61070..f149f84 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -480,6 +480,20 @@ void anv_CmdBlitImage(
blorp_batch_finish();
 }
 
+static enum isl_format
+isl_format_for_size(unsigned size_B)
+{
+   switch (size_B) {
+   case 1:  return ISL_FORMAT_R8_UINT;
+   case 2:  return ISL_FORMAT_R8G8_UINT;
+   case 4:  return ISL_FORMAT_R8G8B8A8_UINT;
+   case 8:  return ISL_FORMAT_R16G16B16A16_UINT;
+   case 16: return ISL_FORMAT_R32G32B32A32_UINT;
+   default:
+  unreachable("Not a power-of-two format size");
+   }
+}
+
 static void
 do_buffer_copy(struct blorp_batch *batch,
struct anv_bo *src, uint64_t src_offset,
@@ -491,16 +505,7 @@ do_buffer_copy(struct blorp_batch *batch,
/* The actual format we pick doesn't matter as blorp will throw it away.
 * The only thing that actually matters is the size.
 */
-   enum isl_format format;
-   switch (block_size) {
-   case 1:  format = ISL_FORMAT_R8_UINT;  break;
-   case 2:  format = ISL_FORMAT_R8G8_UINT;break;
-   case 4:  format = ISL_FORMAT_R8G8B8A8_UNORM;   break;
-   case 8:  format = ISL_FORMAT_R16G16B16A16_UNORM;   break;
-   case 16: format = ISL_FORMAT_R32G32B32A32_UINT;break;
-   default:
-  unreachable("Not a power-of-two format size");
-   }
+   enum isl_format format = isl_format_for_size(block_size);
 
struct isl_surf surf;
isl_surf_init(>isl_dev, ,
@@ -667,6 +672,87 @@ void anv_CmdUpdateBuffer(
blorp_batch_finish();
 }
 
+void anv_CmdFillBuffer(
+VkCommandBuffer commandBuffer,
+VkBufferdstBuffer,
+VkDeviceSizedstOffset,
+VkDeviceSizefillSize,
+uint32_tdata)
+{
+   ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
+   ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
+   struct blorp_surf surf;
+   struct isl_surf isl_surf;
+
+   struct blorp_batch batch;
+   blorp_batch_init(_buffer->device->blorp, , cmd_buffer);
+
+   if (fillSize == VK_WHOLE_SIZE) {
+  fillSize = dst_buffer->size - dstOffset;
+  /* Make sure fillSize is a multiple of 4 */
+  fillSize &= ~3ull;
+   }
+
+   /* First, we compute the biggest format that can be used with the
+* given offsets and size.
+*/
+   int bs = 16;
+   bs = gcd_pow2_u64(bs, dstOffset);
+   bs = gcd_pow2_u64(bs, fillSize);
+   enum isl_format isl_format = isl_format_for_size(bs);
+
+   union isl_color_value color = {
+  .u32 = { data, data, data, data },
+   };
+
+   const uint64_t max_fill_size = MAX_SURFACE_DIM * MAX_SURFACE_DIM * bs;
+   while (fillSize >= max_fill_size) {
+  get_blorp_surf_for_anv_buffer(cmd_buffer->device,
+dst_buffer, dstOffset,
+MAX_SURFACE_DIM, MAX_SURFACE_DIM,
+MAX_SURFACE_DIM * bs, isl_format,
+, _surf);
+
+  blorp_clear(, , isl_format, ISL_SWIZZLE_IDENTITY,
+  0, 0, 1, 0, 0, MAX_SURFACE_DIM, MAX_SURFACE_DIM,
+  color, NULL);
+  fillSize -= max_fill_size;
+  dstOffset += max_fill_size;
+   }
+
+   uint64_t height = fillSize / (MAX_SURFACE_DIM * bs);
+   assert(height < MAX_SURFACE_DIM);
+   if (height != 0) {
+  const uint64_t rect_fill_size = height * MAX_SURFACE_DIM * bs;
+  get_blorp_surf_for_anv_buffer(cmd_buffer->device,
+dst_buffer, dstOffset,
+MAX_SURFACE_DIM, height,
+MAX_SURFACE_DIM * bs, isl_format,
+, _surf);
+
+  blorp_clear(, , isl_format, ISL_SWIZZLE_IDENTITY,
+  0, 0, 1, 0, 0, MAX_SURFACE_DIM, height,
+  color, NULL);
+  fillSize -= rect_fill_size;
+  dstOffset += rect_fill_size;
+   }
+
+   if (fillSize != 0) {
+  const uint32_t width = fillSize / bs;
+  get_blorp_surf_for_anv_buffer(cmd_buffer->device,
+dst_buffer, dstOffset,
+width, 1,
+width * bs, 

Mesa (master): anv/meta: Roll clear_image into CmdClearDepthStencilImage

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: e3a1d33077251987f52284afc6d59a154ec4c2bc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e3a1d33077251987f52284afc6d59a154ec4c2bc

Author: Jason Ekstrand 
Date:   Sun Sep 25 09:41:27 2016 -0700

anv/meta: Roll clear_image into CmdClearDepthStencilImage

It is now the only caller so there's no sense in keeping things split out.

Signed-off-by: Jason Ekstrand 
Reviewed-by: Nanley Chery 

---

 src/intel/vulkan/anv_meta_clear.c | 84 +--
 1 file changed, 28 insertions(+), 56 deletions(-)

diff --git a/src/intel/vulkan/anv_meta_clear.c 
b/src/intel/vulkan/anv_meta_clear.c
index 5579454..11b471f 100644
--- a/src/intel/vulkan/anv_meta_clear.c
+++ b/src/intel/vulkan/anv_meta_clear.c
@@ -752,28 +752,24 @@ anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer 
*cmd_buffer)
meta_clear_end(_state, cmd_buffer);
 }
 
-static void
-anv_cmd_clear_image(struct anv_cmd_buffer *cmd_buffer,
-struct anv_image *image,
-VkImageLayout image_layout,
-VkClearValue clear_value,
-uint32_t range_count,
-const VkImageSubresourceRange *ranges)
+void anv_CmdClearDepthStencilImage(
+VkCommandBuffer commandBuffer,
+VkImage image_h,
+VkImageLayout   imageLayout,
+const VkClearDepthStencilValue* pDepthStencil,
+uint32_trangeCount,
+const VkImageSubresourceRange*  pRanges)
 {
-   VkDevice device_h = anv_device_to_handle(cmd_buffer->device);
+   ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
+   ANV_FROM_HANDLE(anv_image, image, image_h);
+   struct anv_meta_saved_state saved_state;
 
-   VkFormat vk_format = image->vk_format;
-   if (vk_format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
-  /* We can't actually render to this format so we have to work around it
-   * by manually unpacking and using R32_UINT.
-   */
-  clear_value.color.uint32[0] =
- float3_to_rgb9e5(clear_value.color.float32);
-  vk_format = VK_FORMAT_R32_UINT;
-   }
+   meta_clear_begin(_state, cmd_buffer);
+
+   VkDevice device_h = anv_device_to_handle(cmd_buffer->device);
 
-   for (uint32_t r = 0; r < range_count; r++) {
-  const VkImageSubresourceRange *range = [r];
+   for (uint32_t r = 0; r < rangeCount; r++) {
+  const VkImageSubresourceRange *range = [r];
   for (uint32_t l = 0; l < anv_get_levelCount(image, range); ++l) {
  const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
   anv_minify(image->extent.depth, l) :
@@ -785,7 +781,7 @@ anv_cmd_clear_image(struct anv_cmd_buffer *cmd_buffer,
   .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
   .image = anv_image_to_handle(image),
   .viewType = anv_meta_get_view_type(image),
-  .format = vk_format,
+  .format = image->vk_format,
   .subresourceRange = {
  .aspectMask = range->aspectMask,
  .baseMipLevel = range->baseMipLevel + l,
@@ -812,13 +808,18 @@ anv_cmd_clear_image(struct anv_cmd_buffer *cmd_buffer,
);
 
 VkAttachmentDescription att_desc = {
-   .format = vk_format,
+   .format = image->vk_format,
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
.stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
.stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
-   .initialLayout = image_layout,
-   .finalLayout = image_layout,
+   .initialLayout = imageLayout,
+   .finalLayout = imageLayout,
+};
+
+const VkAttachmentReference att_ref = {
+   .attachment = 0,
+   .layout = imageLayout,
 };
 
 VkSubpassDescription subpass_desc = {
@@ -827,23 +828,11 @@ anv_cmd_clear_image(struct anv_cmd_buffer *cmd_buffer,
.colorAttachmentCount = 0,
.pColorAttachments = NULL,
.pResolveAttachments = NULL,
-   .pDepthStencilAttachment = NULL,
+   .pDepthStencilAttachment = _ref,
.preserveAttachmentCount = 0,
.pPreserveAttachments = NULL,
 };
 
-const VkAttachmentReference att_ref = {
-   .attachment = 0,
-   .layout = image_layout,
-};
-
-if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
-   subpass_desc.colorAttachmentCount = 1;
-   subpass_desc.pColorAttachments = _ref;
-} else {
-   

Mesa (master): egl: Track EGL_KHR_debug state when going through EGL API calls (v3)

[Adam Jackson]

Module: Mesa
Branch: master
Commit: 6a5545d3ba60a19a3bce8f62141e0991a595eeaf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a5545d3ba60a19a3bce8f62141e0991a595eeaf

Author: Kyle Brenneman 
Date:   Mon Sep 12 17:50:40 2016 -0400

egl: Track EGL_KHR_debug state when going through EGL API calls (v3)

This decorates every EGL entrypoint with _EGL_FUNC_START, which records
the function name and primary dispatch object label in the current
thread state. It also adds debug report functions and calls them when
appropriate.

This would be useful enough for debugging on its own, if the user set a
breakpoint when the report function was called. We will also need this
state tracked in order to expose EGL_KHR_debug.

v2:
- Clear the object label in more cases in _eglSetFuncName
- Pass draw surface (if any) to _EGL_FUNC_START in eglSwapInterval

v3:
- Set dummy thread's CurrentAPI to EGL_OPENGL_ES_API not zero
- Less ?: in _eglSetFuncName

Reviewed-by: Adam Jackson 
Reviewed-by: Emil Velikov 

---

 src/egl/main/eglapi.c | 151 +++---
 src/egl/main/eglcurrent.c |  91 +++-
 src/egl/main/eglcurrent.h |  22 +++
 src/egl/main/eglglobals.h |   5 ++
 4 files changed, 257 insertions(+), 12 deletions(-)

diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index 697957e..88cdf06 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -250,6 +250,37 @@ _eglUnlockDisplay(_EGLDisplay *dpy)
mtx_unlock(>Mutex);
 }
 
+static EGLBoolean
+_eglSetFuncName(const char *funcName, _EGLDisplay *disp, EGLenum objectType, 
_EGLResource *object)
+{
+   _EGLThreadInfo *thr = _eglGetCurrentThread();
+   if (!_eglIsCurrentThreadDummy()) {
+  thr->CurrentFuncName = funcName;
+  thr->CurrentObjectLabel = NULL;
+
+  if (objectType == EGL_OBJECT_THREAD_KHR)
+ thr->CurrentObjectLabel = thr->Label;
+  else if (objectType == EGL_OBJECT_DISPLAY_KHR && disp)
+ thr->CurrentObjectLabel = disp->Label;
+  else if (object)
+ thr->CurrentObjectLabel = object->Label;
+
+  return EGL_TRUE;
+   }
+
+   _eglDebugReportFull(EGL_BAD_ALLOC, funcName, funcName,
+  EGL_DEBUG_MSG_CRITICAL_KHR, NULL, NULL);
+   return EGL_FALSE;
+}
+
+#define _EGL_FUNC_START(disp, objectType, object, ret) \
+   do { \
+  if (!_eglSetFuncName(__func__, disp, objectType, (_EGLResource *) 
object)) { \
+ if (disp) \
+_eglUnlockDisplay(disp);   \
+ return ret; \
+  } \
+   } while(0)
 
 /**
  * Convert an attribute list from EGLint[] to EGLAttrib[].
@@ -328,6 +359,8 @@ eglGetDisplay(EGLNativeDisplayType nativeDisplay)
_EGLDisplay *dpy;
void *native_display_ptr;
 
+   _EGL_FUNC_START(NULL, EGL_OBJECT_THREAD_KHR, NULL, EGL_NO_DISPLAY);
+
STATIC_ASSERT(sizeof(void*) == sizeof(nativeDisplay));
native_display_ptr = (void*) nativeDisplay;
 
@@ -371,6 +404,7 @@ static EGLDisplay EGLAPIENTRY
 eglGetPlatformDisplayEXT(EGLenum platform, void *native_display,
  const EGLint *attrib_list)
 {
+   _EGL_FUNC_START(NULL, EGL_OBJECT_THREAD_KHR, NULL, EGL_NO_DISPLAY);
return _eglGetPlatformDisplayCommon(platform, native_display, attrib_list);
 }
 
@@ -381,6 +415,8 @@ eglGetPlatformDisplay(EGLenum platform, void 
*native_display,
EGLDisplay display;
EGLint *int_attribs;
 
+   _EGL_FUNC_START(NULL, EGL_OBJECT_THREAD_KHR, NULL, EGL_NO_DISPLAY);
+
int_attribs = _eglConvertAttribsToInt(attrib_list);
if (attrib_list && !int_attribs)
   RETURN_EGL_ERROR(NULL, EGL_BAD_ALLOC, NULL);
@@ -524,6 +560,8 @@ eglInitialize(EGLDisplay dpy, EGLint *major, EGLint *minor)
 {
_EGLDisplay *disp = _eglLockDisplay(dpy);
 
+   _EGL_FUNC_START(disp, EGL_OBJECT_DISPLAY_KHR, NULL, EGL_FALSE);
+
if (!disp)
   RETURN_EGL_ERROR(NULL, EGL_BAD_DISPLAY, EGL_FALSE);
 
@@ -574,6 +612,8 @@ eglTerminate(EGLDisplay dpy)
 {
_EGLDisplay *disp = _eglLockDisplay(dpy);
 
+   _EGL_FUNC_START(disp, EGL_OBJECT_DISPLAY_KHR, NULL, EGL_FALSE);
+
if (!disp)
   RETURN_EGL_ERROR(NULL, EGL_BAD_DISPLAY, EGL_FALSE);
 
@@ -601,6 +641,7 @@ eglQueryString(EGLDisplay dpy, EGLint name)
}
 
disp = _eglLockDisplay(dpy);
+   _EGL_FUNC_START(disp, EGL_OBJECT_DISPLAY_KHR, NULL, NULL);
_EGL_CHECK_DISPLAY(disp, NULL, drv);
 
switch (name) {
@@ -626,6 +667,8 @@ eglGetConfigs(EGLDisplay dpy, EGLConfig *configs,
_EGLDriver *drv;
EGLBoolean ret;
 
+   _EGL_FUNC_START(disp, EGL_OBJECT_DISPLAY_KHR, NULL, EGL_FALSE);
+
_EGL_CHECK_DISPLAY(disp, EGL_FALSE, drv);
ret = drv->API.GetConfigs(drv, disp, configs, config_size, num_config);
 
@@ -641,6 +684,8 @@ eglChooseConfig(EGLDisplay dpy, const EGLint *attrib_list, 
EGLConfig *configs,
_EGLDriver *drv;
EGLBoolean ret;
 
+   _EGL_FUNC_START(disp, EGL_OBJECT_DISPLAY_KHR, NULL, EGL_FALSE);
+

Mesa (master): egl: Implement EGL_KHR_debug (v2)

[Adam Jackson]

Module: Mesa
Branch: master
Commit: ca9f26ac6fcb0afb68101fb3f74fcb3100507c0c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca9f26ac6fcb0afb68101fb3f74fcb3100507c0c

Author: Kyle Brenneman 
Date:   Mon Sep 12 17:51:22 2016 -0400

egl: Implement EGL_KHR_debug (v2)

Wire up the debug entrypoints to EGL dispatch, and add the extension
string to the client extension list.

v2:
- Lots of style fixes
- Fix missing EGLAPIENTRYs
- Factor out valid attribute check
- Lock display in eglLabelObjectKHR as needed, and use RETURN_EGL_*
- Move "EGL_KHR_debug" into asciibetical order in client extension
  string

Reviewed-by: Adam Jackson 
Reviewed-by: Emil Velikov 

---

 src/egl/main/eglapi.c | 145 ++
 src/egl/main/eglglobals.c |   1 +
 2 files changed, 146 insertions(+)

diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index 88cdf06..d2a89af 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -2028,6 +2028,148 @@ eglExportDMABUFImageMESA(EGLDisplay dpy, EGLImage image,
RETURN_EGL_EVAL(disp, ret);
 }
 
+static EGLint EGLAPIENTRY
+eglLabelObjectKHR(EGLDisplay dpy, EGLenum objectType, EGLObjectKHR object,
+ EGLLabelKHR label)
+{
+   _EGLDisplay *disp = NULL;
+   _EGLResourceType type;
+
+   _EGL_FUNC_START(NULL, EGL_NONE, NULL, EGL_BAD_ALLOC);
+
+   if (objectType == EGL_OBJECT_THREAD_KHR) {
+  _EGLThreadInfo *t = _eglGetCurrentThread();
+
+  if (!_eglIsCurrentThreadDummy()) {
+ t->Label = label;
+ return EGL_SUCCESS;
+  }
+
+  RETURN_EGL_ERROR(NULL, EGL_BAD_ALLOC, EGL_BAD_ALLOC);
+   }
+
+   disp = _eglLockDisplay(dpy);
+   if (disp == NULL)
+  RETURN_EGL_ERROR(disp, EGL_BAD_DISPLAY, EGL_BAD_DISPLAY);
+
+   if (objectType == EGL_OBJECT_DISPLAY_KHR) {
+  if (dpy != (EGLDisplay) object)
+ RETURN_EGL_ERROR(disp, EGL_BAD_PARAMETER, EGL_BAD_PARAMETER);
+
+  disp->Label = label;
+  RETURN_EGL_EVAL(disp, EGL_SUCCESS);
+   }
+
+   switch (objectType) {
+  case EGL_OBJECT_CONTEXT_KHR:
+ type = _EGL_RESOURCE_CONTEXT;
+ break;
+  case EGL_OBJECT_SURFACE_KHR:
+ type = _EGL_RESOURCE_SURFACE;
+ break;
+  case EGL_OBJECT_IMAGE_KHR:
+ type = _EGL_RESOURCE_IMAGE;
+ break;
+  case EGL_OBJECT_SYNC_KHR:
+ type = _EGL_RESOURCE_SYNC;
+ break;
+  case EGL_OBJECT_STREAM_KHR:
+  default:
+ RETURN_EGL_ERROR(disp, EGL_BAD_PARAMETER, EGL_BAD_PARAMETER);
+   }
+
+   if (_eglCheckResource(object, type, disp)) {
+  _EGLResource *res = (_EGLResource *) object;
+
+  res->Label = label;
+  RETURN_EGL_EVAL(disp, EGL_SUCCESS);
+   }
+
+   RETURN_EGL_ERROR(disp, EGL_BAD_PARAMETER, EGL_BAD_PARAMETER);
+}
+
+static EGLBoolean
+validDebugMessageLevel(EGLAttrib level)
+{
+   return (level >= EGL_DEBUG_MSG_CRITICAL_KHR &&
+   level <= EGL_DEBUG_MSG_INFO_KHR);
+}
+
+static EGLint EGLAPIENTRY
+eglDebugMessageControlKHR(EGLDEBUGPROCKHR callback,
+ const EGLAttrib *attrib_list)
+{
+   unsigned int newEnabled;
+
+   _EGL_FUNC_START(NULL, EGL_NONE, NULL, EGL_BAD_ALLOC);
+
+   mtx_lock(_eglGlobal.Mutex);
+
+   newEnabled = _eglGlobal.debugTypesEnabled;
+   if (attrib_list != NULL) {
+  int i;
+
+  for (i = 0; attrib_list[i] != EGL_NONE; i += 2) {
+ if (validDebugMessageLevel(attrib_list[i])) {
+if (attrib_list[i + 1])
+   newEnabled |= DebugBitFromType(attrib_list[i]);
+else
+   newEnabled &= ~DebugBitFromType(attrib_list[i]);
+continue;
+ }
+
+ // On error, set the last error code, call the current
+ // debug callback, and return the error code.
+ mtx_unlock(_eglGlobal.Mutex);
+ _eglReportError(EGL_BAD_ATTRIBUTE, NULL,
+   "Invalid attribute 0x%04lx", (unsigned long) attrib_list[i]);
+ return EGL_BAD_ATTRIBUTE;
+  }
+   }
+
+   if (callback != NULL) {
+  _eglGlobal.debugCallback = callback;
+  _eglGlobal.debugTypesEnabled = newEnabled;
+   } else {
+  _eglGlobal.debugCallback = NULL;
+  _eglGlobal.debugTypesEnabled = _EGL_DEBUG_BIT_CRITICAL | 
_EGL_DEBUG_BIT_ERROR;
+   }
+
+   mtx_unlock(_eglGlobal.Mutex);
+   return EGL_SUCCESS;
+}
+
+static EGLBoolean EGLAPIENTRY
+eglQueryDebugKHR(EGLint attribute, EGLAttrib *value)
+{
+   _EGL_FUNC_START(NULL, EGL_NONE, NULL, EGL_BAD_ALLOC);
+
+   mtx_lock(_eglGlobal.Mutex);
+
+   do {
+  if (validDebugMessageLevel(attribute)) {
+ if (_eglGlobal.debugTypesEnabled & DebugBitFromType(attribute))
+*value = EGL_TRUE;
+ else
+*value = EGL_FALSE;
+ break;
+  }
+
+  if (attribute == EGL_DEBUG_CALLBACK_KHR) {
+ *value = (EGLAttrib) _eglGlobal.debugCallback;
+ break;
+  }
+
+  mtx_unlock(_eglGlobal.Mutex);
+  

Mesa (master): i965/l3: Add explicit way size calculation for bxt

[Ben Widawsky]

Module: Mesa
Branch: master
Commit: 2dc06e23245429bceaac16e8a31e29ddc822ebc9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2dc06e23245429bceaac16e8a31e29ddc822ebc9

Author: Ben Widawsky 
Date:   Tue Oct  4 20:42:30 2016 -0700

i965/l3: Add explicit way size calculation for bxt

There should be no functional change here because Broxton and CHV are
both gt1. Without this code however, it might seem like broxton support
is missing.

While here, put the gt1 check in front to hopefully short-circuit the
condition for the mobile cases.

Signed-off-by: Ben Widawsky 
Reviewed-by: Anuj Phogat 
Reviewed-by: Francisco Jerez 

---

 src/intel/common/gen_l3_config.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index 0d99f12..0783217 100644
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -257,7 +257,9 @@ get_l3_way_size(const struct gen_device_info *devinfo)
if (devinfo->is_baytrail)
   return 2;
 
-   else if (devinfo->is_cherryview || devinfo->gt == 1)
+   else if (devinfo->gt == 1 ||
+devinfo->is_cherryview ||
+devinfo->is_broxton)
   return 4;
 
else

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Mesa (master): virgl: Fix build regression of commit 8a943564

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 11cc59afcaf85ec7081587326ac56b24e545d59a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=11cc59afcaf85ec7081587326ac56b24e545d59a

Author: Nicolai Hähnle 
Date:   Wed Oct  5 16:27:29 2016 +0200

virgl: Fix build regression of commit 8a943564

---

 src/gallium/drivers/virgl/virgl_context.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/virgl/virgl_context.c 
b/src/gallium/drivers/virgl/virgl_context.c
index e693a73..bda9515 100644
--- a/src/gallium/drivers/virgl/virgl_context.c
+++ b/src/gallium/drivers/virgl/virgl_context.c
@@ -943,7 +943,7 @@ struct pipe_context *virgl_context_create(struct 
pipe_screen *pscreen,
virgl_init_so_functions(vctx);
 
list_inithead(>to_flush_bufs);
-   slab_create_child(>texture_transfer_pool, rs->texture_transfer_pool);
+   slab_create_child(>texture_transfer_pool, >texture_transfer_pool);
 
vctx->primconvert = util_primconvert_create(>base, 
rs->caps.caps.v1.prim_mask);
vctx->uploader = u_upload_create(>base, 1024 * 1024,

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Mesa (master): r300: use the new parent/child pools for transfers (v2)

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 616e36674a1079dcfa131b3c9155cc473441b3de
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=616e36674a1079dcfa131b3c9155cc473441b3de

Author: Nicolai Hähnle 
Date:   Tue Sep 27 18:59:56 2016 +0200

r300: use the new parent/child pools for transfers (v2)

v2: slab_alloc_st -> slab_alloc

Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/r300/r300_context.c   | 5 ++---
 src/gallium/drivers/r300/r300_context.h   | 2 +-
 src/gallium/drivers/r300/r300_screen.c| 3 +++
 src/gallium/drivers/r300/r300_screen.h| 2 ++
 src/gallium/drivers/r300/r300_screen_buffer.c | 6 +++---
 5 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/r300/r300_context.c 
b/src/gallium/drivers/r300/r300_context.c
index 3e5f1d6..b914cdb 100644
--- a/src/gallium/drivers/r300/r300_context.c
+++ b/src/gallium/drivers/r300/r300_context.c
@@ -100,7 +100,7 @@ static void r300_destroy_context(struct pipe_context* 
context)
 rc_destroy_regalloc_state(>fs_regalloc_state);
 
 /* XXX: No way to tell if this was initialized or not? */
-slab_destroy(>pool_transfers);
+slab_destroy_child(>pool_transfers);
 
 /* Free the structs allocated in r300_setup_atoms() */
 if (r300->aa_state.state) {
@@ -385,8 +385,7 @@ struct pipe_context* r300_create_context(struct 
pipe_screen* screen,
 
 r300->context.destroy = r300_destroy_context;
 
-slab_create(>pool_transfers,
- sizeof(struct pipe_transfer), 64);
+slab_create_child(>pool_transfers, >pool_transfers);
 
 r300->ctx = rws->ctx_create(rws);
 if (!r300->ctx)
diff --git a/src/gallium/drivers/r300/r300_context.h 
b/src/gallium/drivers/r300/r300_context.h
index 592479a..264ace5 100644
--- a/src/gallium/drivers/r300/r300_context.h
+++ b/src/gallium/drivers/r300/r300_context.h
@@ -596,7 +596,7 @@ struct r300_context {
 unsigned nr_vertex_buffers;
 struct u_upload_mgr *uploader;
 
-struct slab_mempool pool_transfers;
+struct slab_child_pool pool_transfers;
 
 /* Stat counter. */
 uint64_t flush_counter;
diff --git a/src/gallium/drivers/r300/r300_screen.c 
b/src/gallium/drivers/r300/r300_screen.c
index f6949ce..4d41693 100644
--- a/src/gallium/drivers/r300/r300_screen.c
+++ b/src/gallium/drivers/r300/r300_screen.c
@@ -676,6 +676,7 @@ static void r300_destroy_screen(struct pipe_screen* pscreen)
   return;
 
 pipe_mutex_destroy(r300screen->cmask_mutex);
+slab_destroy_parent(>pool_transfers);
 
 if (rws)
   rws->destroy(rws);
@@ -738,6 +739,8 @@ struct pipe_screen* r300_screen_create(struct radeon_winsys 
*rws)
 
 r300_init_screen_resource_functions(r300screen);
 
+slab_create_parent(>pool_transfers, sizeof(struct 
pipe_transfer), 64);
+
 util_format_s3tc_init();
 pipe_mutex_init(r300screen->cmask_mutex);
 
diff --git a/src/gallium/drivers/r300/r300_screen.h 
b/src/gallium/drivers/r300/r300_screen.h
index 5cd5a40..4b783af 100644
--- a/src/gallium/drivers/r300/r300_screen.h
+++ b/src/gallium/drivers/r300/r300_screen.h
@@ -44,6 +44,8 @@ struct r300_screen {
 /** Combination of DBG_xxx flags */
 unsigned debug;
 
+struct slab_parent_pool pool_transfers;
+
 /* The MSAA texture with CMASK access; */
 struct pipe_resource *cmask_resource;
 pipe_mutex cmask_mutex;
diff --git a/src/gallium/drivers/r300/r300_screen_buffer.c 
b/src/gallium/drivers/r300/r300_screen_buffer.c
index 4747058..95ada57 100644
--- a/src/gallium/drivers/r300/r300_screen_buffer.c
+++ b/src/gallium/drivers/r300/r300_screen_buffer.c
@@ -77,7 +77,7 @@ r300_buffer_transfer_map( struct pipe_context *context,
 struct pipe_transfer *transfer;
 uint8_t *map;
 
-transfer = slab_alloc_st(>pool_transfers);
+transfer = slab_alloc(>pool_transfers);
 transfer->resource = resource;
 transfer->level = level;
 transfer->usage = usage;
@@ -129,7 +129,7 @@ r300_buffer_transfer_map( struct pipe_context *context,
 map = rws->buffer_map(rbuf->buf, r300->cs, usage);
 
 if (!map) {
-slab_free_st(>pool_transfers, transfer);
+slab_free(>pool_transfers, transfer);
 return NULL;
 }
 
@@ -142,7 +142,7 @@ static void r300_buffer_transfer_unmap( struct pipe_context 
*pipe,
 {
 struct r300_context *r300 = r300_context(pipe);
 
-slab_free_st(>pool_transfers, transfer);
+slab_free(>pool_transfers, transfer);
 }
 
 static const struct u_resource_vtbl r300_buffer_vtbl =

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Mesa (master): util: use GCC atomic intrinsics with explicit memory model

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 8915f0c0de84fa593ca6c31518c1292f94b3bb7b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8915f0c0de84fa593ca6c31518c1292f94b3bb7b

Author: Nicolai Hähnle 
Date:   Tue Oct  4 16:06:31 2016 +0200

util: use GCC atomic intrinsics with explicit memory model

This is motivated by the fact that p_atomic_read and p_atomic_set may
somewhat surprisingly not do the right thing in the old version: while
stores and loads are de facto atomic at least on x86, the compiler may
apply re-ordering and speculation quite liberally. Basically, the old
version uses the "relaxed" memory ordering.

The new ordering always uses acquire/release ordering. This is the
strongest possible memory ordering that doesn't require additional
fence instructions on x86. (And the only stronger ordering is
"sequentially consistent", which is usually more than you need anyway.)

I would feel more comfortable if p_atomic_set/read in the old
implementation were at least using volatile loads and stores, but I
don't see a way to get there without typeof (which we cannot use here
since the code is compiled with -std=c99).

Eventually, we should really just move to something that is based on
the atomics in C11 / C++11.

Acked-by: Marek Olšák 
Reviewed-by: Emil Velikov 

---

 configure.ac| 11 +++
 src/util/u_atomic.h | 21 +
 2 files changed, 32 insertions(+)

diff --git a/configure.ac b/configure.ac
index 1bfac3b..421f4f3 100644
--- a/configure.ac
+++ b/configure.ac
@@ -387,6 +387,17 @@ fi
 AM_CONDITIONAL([SSE41_SUPPORTED], [test x$SSE41_SUPPORTED = x1])
 AC_SUBST([SSE41_CFLAGS], $SSE41_CFLAGS)
 
+dnl Check for new-style atomic builtins
+AC_COMPILE_IFELSE([AC_LANG_SOURCE([[
+int main() {
+int n;
+return __atomic_load_n(, __ATOMIC_ACQUIRE);
+}]])], GCC_ATOMIC_BUILTINS_SUPPORTED=1)
+if test "x$GCC_ATOMIC_BUILTINS_SUPPORTED" = x1; then
+DEFINES="$DEFINES -DUSE_GCC_ATOMIC_BUILTINS"
+fi
+AM_CONDITIONAL([GCC_ATOMIC_BUILTINS_SUPPORTED], [test 
x$GCC_ATOMIC_BUILTINS_SUPPORTED = x1])
+
 dnl Check for Endianness
 AC_C_BIGENDIAN(
little_endian=no,
diff --git a/src/util/u_atomic.h b/src/util/u_atomic.h
index 8675903..2a5bbae 100644
--- a/src/util/u_atomic.h
+++ b/src/util/u_atomic.h
@@ -36,6 +36,20 @@
 
 #define PIPE_ATOMIC "GCC Sync Intrinsics"
 
+#if defined(USE_GCC_ATOMIC_BUILTINS)
+
+/* The builtins with explicit memory model are available since GCC 4.7. */
+#define p_atomic_set(_v, _i) __atomic_store_n((_v), (_i), __ATOMIC_RELEASE)
+#define p_atomic_read(_v) __atomic_load_n((_v), __ATOMIC_ACQUIRE)
+#define p_atomic_dec_zero(v) (__atomic_sub_fetch((v), 1, __ATOMIC_ACQ_REL) == 
0)
+#define p_atomic_inc(v) (void) __atomic_add_fetch((v), 1, __ATOMIC_ACQ_REL)
+#define p_atomic_dec(v) (void) __atomic_sub_fetch((v), 1, __ATOMIC_ACQ_REL)
+#define p_atomic_add(v, i) (void) __atomic_add_fetch((v), (i), 
__ATOMIC_ACQ_REL)
+#define p_atomic_inc_return(v) __atomic_add_fetch((v), 1, __ATOMIC_ACQ_REL)
+#define p_atomic_dec_return(v) __atomic_sub_fetch((v), 1, __ATOMIC_ACQ_REL)
+
+#else
+
 #define p_atomic_set(_v, _i) (*(_v) = (_i))
 #define p_atomic_read(_v) (*(_v))
 #define p_atomic_dec_zero(v) (__sync_sub_and_fetch((v), 1) == 0)
@@ -44,6 +58,13 @@
 #define p_atomic_add(v, i) (void) __sync_add_and_fetch((v), (i))
 #define p_atomic_inc_return(v) __sync_add_and_fetch((v), 1)
 #define p_atomic_dec_return(v) __sync_sub_and_fetch((v), 1)
+
+#endif
+
+/* There is no __atomic_* compare and exchange that returns the current value.
+ * Also, GCC 5.4 seems unable to optimize a compound statement expression that
+ * uses an additional stack variable with __atomic_compare_exchange[_n].
+ */
 #define p_atomic_cmpxchg(v, old, _new) \
__sync_val_compare_and_swap((v), (old), (_new))
 

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Mesa (master): freedreno: use the new parent/child pools for transfers

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 0334ba150f429b7d6b0bdc003c4301e0ad5fa21d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0334ba150f429b7d6b0bdc003c4301e0ad5fa21d

Author: Nicolai Hähnle 
Date:   Tue Sep 27 19:06:13 2016 +0200

freedreno: use the new parent/child pools for transfers

Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/freedreno/freedreno_context.c  | 5 ++---
 src/gallium/drivers/freedreno/freedreno_context.h  | 2 +-
 src/gallium/drivers/freedreno/freedreno_resource.c | 4 ++--
 src/gallium/drivers/freedreno/freedreno_screen.c   | 4 
 src/gallium/drivers/freedreno/freedreno_screen.h   | 3 +++
 5 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/freedreno/freedreno_context.c 
b/src/gallium/drivers/freedreno/freedreno_context.c
index f8604f1..0b12409 100644
--- a/src/gallium/drivers/freedreno/freedreno_context.c
+++ b/src/gallium/drivers/freedreno/freedreno_context.c
@@ -121,7 +121,7 @@ fd_context_destroy(struct pipe_context *pctx)
if (ctx->primconvert)
util_primconvert_destroy(ctx->primconvert);
 
-   slab_destroy(>transfer_pool);
+   slab_destroy_child(>transfer_pool);
 
for (i = 0; i < ARRAY_SIZE(ctx->pipe); i++) {
struct fd_vsc_pipe *pipe = >pipe[i];
@@ -265,8 +265,7 @@ fd_context_init(struct fd_context *ctx, struct pipe_screen 
*pscreen,
ctx->batch = fd_bc_alloc_batch(>batch_cache, ctx);
}
 
-   slab_create(>transfer_pool, sizeof(struct fd_transfer),
-   16);
+   slab_create_child(>transfer_pool, >transfer_pool);
 
fd_draw_init(pctx);
fd_resource_context_init(pctx);
diff --git a/src/gallium/drivers/freedreno/freedreno_context.h 
b/src/gallium/drivers/freedreno/freedreno_context.h
index e1b7b23..c4c08a6 100644
--- a/src/gallium/drivers/freedreno/freedreno_context.h
+++ b/src/gallium/drivers/freedreno/freedreno_context.h
@@ -121,7 +121,7 @@ struct fd_context {
struct primconvert_context *primconvert;
 
/* slab for pipe_transfer allocations: */
-   struct slab_mempool transfer_pool;
+   struct slab_child_pool transfer_pool;
 
/* slabs for fd_hw_sample and fd_hw_sample_period allocations: */
struct slab_mempool sample_pool;
diff --git a/src/gallium/drivers/freedreno/freedreno_resource.c 
b/src/gallium/drivers/freedreno/freedreno_resource.c
index 1874271..addfc40 100644
--- a/src/gallium/drivers/freedreno/freedreno_resource.c
+++ b/src/gallium/drivers/freedreno/freedreno_resource.c
@@ -425,7 +425,7 @@ fd_resource_transfer_unmap(struct pipe_context *pctx,
   ptrans->box.x + ptrans->box.width);
 
pipe_resource_reference(>resource, NULL);
-   slab_free_st(>transfer_pool, ptrans);
+   slab_free(>transfer_pool, ptrans);
 
free(trans->staging);
 }
@@ -451,7 +451,7 @@ fd_resource_transfer_map(struct pipe_context *pctx,
DBG("prsc=%p, level=%u, usage=%x, box=%dx%d+%d,%d", prsc, level, usage,
box->width, box->height, box->x, box->y);
 
-   ptrans = slab_alloc_st(>transfer_pool);
+   ptrans = slab_alloc(>transfer_pool);
if (!ptrans)
return NULL;
 
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c 
b/src/gallium/drivers/freedreno/freedreno_screen.c
index 598a811..bc54539 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -138,6 +138,8 @@ fd_screen_destroy(struct pipe_screen *pscreen)
 
fd_bc_fini(>batch_cache);
 
+   slab_destroy_parent(>transfer_pool);
+
pipe_mutex_destroy(screen->lock);
 
free(screen);
@@ -696,6 +698,8 @@ fd_screen_create(struct fd_device *dev)
pscreen->fence_reference = fd_screen_fence_ref;
pscreen->fence_finish = fd_screen_fence_finish;
 
+   slab_create_parent(>transfer_pool, sizeof(struct fd_transfer), 
16);
+
util_format_s3tc_init();
 
return pscreen;
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.h 
b/src/gallium/drivers/freedreno/freedreno_screen.h
index 03ee90a..db9050e 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.h
+++ b/src/gallium/drivers/freedreno/freedreno_screen.h
@@ -34,6 +34,7 @@
 
 #include "pipe/p_screen.h"
 #include "util/u_memory.h"
+#include "util/slab.h"
 #include "os/os_thread.h"
 
 #include "freedreno_batch_cache.h"
@@ -55,6 +56,8 @@ struct fd_screen {
/* place for winsys to stash it's own stuff: */
void *winsys_priv;
 
+   struct slab_parent_pool transfer_pool;
+
uint32_t gmemsize_bytes;
uint32_t device_id;
uint32_t gpu_id; /* 220, 305, etc */

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Mesa (master): util/slab: re-design to allow migration between pools (v3)

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: d8cff811dfb0172684fe3ec01c98fc847b0c17a7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8cff811dfb0172684fe3ec01c98fc847b0c17a7

Author: Nicolai Hähnle 
Date:   Tue Sep 27 18:30:18 2016 +0200

util/slab: re-design to allow migration between pools (v3)

This is basically a re-write of the slab allocator into a design where
multiple child pools are linked to a parent pool. The intention is that
every (GL, pipe) context has its own child pool, while the corresponding
parent pool is held by the winsys or screen, or possibly the GL share group.

The fast path is still used when objects are freed by the same child pool
that allocated them. However, it is now also possible to free an object in a
different pool, as long as they belong to the same parent. Objects also
survive the destruction of the (child) pool from which they were allocated.

The slow path will return freed objects to the child pool from which they
were originally allocated. If that child pool was destroyed, the corresponding
page is considered an orphan and will be freed once all objects in it have
been freed.

This allocation pattern is required for pipe_transfers that correspond to
(GL) buffer object mappings when the mapping is created in one context
which is later destroyed while other contexts of the same share group live
on -- see the bug report referenced below.

Note that individual drivers do need to migrate to the new interface in
order to benefit and fix the bug.

v2: use singly-linked lists everywhere
v3: use p_atomic_set for page->u.num_remaining

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97894

---

 src/util/slab.c | 285 +---
 src/util/slab.h |  62 +---
 2 files changed, 258 insertions(+), 89 deletions(-)

diff --git a/src/util/slab.c b/src/util/slab.c
index af75152..cbe4c88 100644
--- a/src/util/slab.c
+++ b/src/util/slab.c
@@ -23,143 +23,283 @@
 
 #include "slab.h"
 #include "macros.h"
-#include "simple_list.h"
+#include "u_atomic.h"
 #include 
 #include 
 #include 
 
 #define ALIGN(value, align) (((value) + (align) - 1) & ~((align) - 1))
 
+#define SLAB_MAGIC_ALLOCATED 0xcafe4321
+#define SLAB_MAGIC_FREE 0x7ee01234
+
 #ifdef DEBUG
-#define SLAB_MAGIC 0xcafe4321
-#define SET_MAGIC(element)   (element)->magic = SLAB_MAGIC
-#define CHECK_MAGIC(element) assert((element)->magic == SLAB_MAGIC)
+#define SET_MAGIC(element, value)   (element)->magic = (value)
+#define CHECK_MAGIC(element, value) assert((element)->magic == (value))
 #else
-#define SET_MAGIC(element)
-#define CHECK_MAGIC(element)
+#define SET_MAGIC(element, value)
+#define CHECK_MAGIC(element, value)
 #endif
 
 /* One array element within a big buffer. */
 struct slab_element_header {
-   /* The next free element. */
-   struct slab_element_header *next_free;
+   /* The next element in the free or migrated list. */
+   struct slab_element_header *next;
+
+   /* This is either
+* - a pointer to the child pool to which this element belongs, or
+* - a pointer to the orphaned page of the element, with the least
+*   significant bit set to 1.
+*/
+   intptr_t owner;
 
 #ifdef DEBUG
-   /* Use intptr_t to keep the header aligned to a pointer size. */
intptr_t magic;
 #endif
 };
 
+/* The page is an array of allocations in one block. */
+struct slab_page_header {
+   union {
+  /* Next page in the same child pool. */
+  struct slab_page_header *next;
+
+  /* Number of remaining, non-freed elements (for orphaned pages). */
+  unsigned num_remaining;
+   } u;
+   /* Memory after the last member is dedicated to the page itself.
+* The allocated size is always larger than this structure.
+*/
+};
+
+
 static struct slab_element_header *
-slab_get_element(struct slab_mempool *pool,
+slab_get_element(struct slab_parent_pool *parent,
  struct slab_page_header *page, unsigned index)
 {
return (struct slab_element_header*)
-  ((uint8_t*)[1] + (pool->element_size * index));
+  ((uint8_t*)[1] + (parent->element_size * index));
+}
+
+/* The given object/element belongs to an orphaned page (i.e. the owning child
+ * pool has been destroyed). Mark the element as freed and free the whole page
+ * when no elements are left in it.
+ */
+static void
+slab_free_orphaned(struct slab_element_header *elt)
+{
+   struct slab_page_header *page;
+
+   assert(elt->owner & 1);
+
+   page = (struct slab_page_header *)(elt->owner & ~(intptr_t)1);
+   if (!p_atomic_dec_return(>u.num_remaining))
+  free(page);
+}
+
+/**
+ * Create a parent pool for the allocation of same-sized objects.
+ *
+ * \param item_size Size of one object.
+ * \param num_items Number of objects to allocate at once.
+ */
+void
+slab_create_parent(struct slab_parent_pool *parent,
+   unsigned item_size,
+   unsigned num_items)
+{
+   mtx_init(>mutex, mtx_plain);
+   

Mesa (master): st/mesa: extract conversion from pipe_reset_status to GLenum

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: d856130025be12230ed84fc31fcf5691641f1952
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d856130025be12230ed84fc31fcf5691641f1952

Author: Nicolai Hähnle 
Date:   Fri Sep 30 13:02:00 2016 +0200

st/mesa: extract conversion from pipe_reset_status to GLenum

Reviewed-by: Edward O'Callaghan 
Reviewed-by: Marek Olšák 

---

 src/mesa/state_tracker/st_cb_flush.c | 29 ++---
 1 file changed, 18 insertions(+), 11 deletions(-)

diff --git a/src/mesa/state_tracker/st_cb_flush.c 
b/src/mesa/state_tracker/st_cb_flush.c
index 5cab5a7..87c3d81 100644
--- a/src/mesa/state_tracker/st_cb_flush.c
+++ b/src/mesa/state_tracker/st_cb_flush.c
@@ -141,19 +141,9 @@ static void st_glFinish(struct gl_context *ctx)
 }
 
 
-/**
- * Query information about GPU resets observed by this context
- *
- * Called via \c dd_function_table::GetGraphicsResetStatus.
- */
 static GLenum
-st_get_graphics_reset_status(struct gl_context *ctx)
+gl_reset_status_from_pipe_reset_status(enum pipe_reset_status status)
 {
-   struct st_context *st = st_context(ctx);
-   enum pipe_reset_status status;
-
-   status = st->pipe->get_device_reset_status(st->pipe);
-
switch (status) {
case PIPE_NO_RESET:
   return GL_NO_ERROR;
@@ -170,6 +160,23 @@ st_get_graphics_reset_status(struct gl_context *ctx)
 }
 
 
+/**
+ * Query information about GPU resets observed by this context
+ *
+ * Called via \c dd_function_table::GetGraphicsResetStatus.
+ */
+static GLenum
+st_get_graphics_reset_status(struct gl_context *ctx)
+{
+   struct st_context *st = st_context(ctx);
+   enum pipe_reset_status status;
+
+   status = st->pipe->get_device_reset_status(st->pipe);
+
+   return gl_reset_status_from_pipe_reset_status(status);
+}
+
+
 void st_init_flush_functions(struct pipe_screen *screen,
  struct dd_function_table *functions)
 {

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Mesa (master): gallium: add pipe_context::set_device_reset_callback

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 1a3c75e30ecb343a990823a838356c063652c237
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a3c75e30ecb343a990823a838356c063652c237

Author: Nicolai Hähnle 
Date:   Fri Sep 30 12:32:02 2016 +0200

gallium: add pipe_context::set_device_reset_callback

Reviewed-by: Edward O'Callaghan 
Reviewed-by: Marek Olšák 

---

 src/gallium/docs/source/context.rst  | 15 +++
 src/gallium/include/pipe/p_context.h |  8 
 src/gallium/include/pipe/p_state.h   | 19 +++
 3 files changed, 42 insertions(+)

diff --git a/src/gallium/docs/source/context.rst 
b/src/gallium/docs/source/context.rst
index 13dd606..e190cef 100644
--- a/src/gallium/docs/source/context.rst
+++ b/src/gallium/docs/source/context.rst
@@ -692,3 +692,18 @@ last_level for layers range from first_layer through 
last_layer.
 It returns TRUE if mipmap generation succeeds, otherwise it
 returns FALSE. Mipmap generation may fail when it is not supported
 for particular texture types or formats.
+
+Device resets
+^
+
+The state tracker can query or request notifications of when the GPU
+is reset for whatever reason (application error, driver error). When
+a GPU reset happens, the context becomes unusable and all related state
+should be considered lost and undefined. Despite that, context
+notifications are single-shot, i.e. subsequent calls to
+``get_device_reset_status`` will return PIPE_NO_RESET.
+
+* ``get_device_reset_status`` queries whether a device reset has happened
+  since the last call or since the last notification by callback.
+* ``set_device_reset_callback`` sets a callback which will be called when
+  a device reset is detected. The callback is only called synchronously.
diff --git a/src/gallium/include/pipe/p_context.h 
b/src/gallium/include/pipe/p_context.h
index f5841d7..b97aad5 100644
--- a/src/gallium/include/pipe/p_context.h
+++ b/src/gallium/include/pipe/p_context.h
@@ -47,6 +47,7 @@ struct pipe_clip_state;
 struct pipe_constant_buffer;
 struct pipe_debug_callback;
 struct pipe_depth_stencil_alpha_state;
+struct pipe_device_reset_callback;
 struct pipe_draw_info;
 struct pipe_grid_info;
 struct pipe_fence_handle;
@@ -691,6 +692,13 @@ struct pipe_context {
enum pipe_reset_status (*get_device_reset_status)(struct pipe_context *ctx);
 
/**
+* Sets the reset status callback. If the pointer is null, then no callback
+* is set, otherwise a copy of the data should be made.
+*/
+   void (*set_device_reset_callback)(struct pipe_context *ctx,
+ const struct pipe_device_reset_callback 
*cb);
+
+   /**
 * Dump driver-specific debug information into a stream. This is
 * used by debugging tools.
 *
diff --git a/src/gallium/include/pipe/p_state.h 
b/src/gallium/include/pipe/p_state.h
index 415ea85..46df196 100644
--- a/src/gallium/include/pipe/p_state.h
+++ b/src/gallium/include/pipe/p_state.h
@@ -831,6 +831,25 @@ struct pipe_debug_callback
 };
 
 /**
+ * Structure that contains a callback for device reset messages from the driver
+ * back to the state tracker.
+ *
+ * The callback must not be called from driver-created threads.
+ */
+struct pipe_device_reset_callback
+{
+   /**
+* Callback for the driver to report when a device reset is detected.
+*
+* \param data   user-supplied data pointer
+* \param status PIPE_*_RESET
+*/
+   void (*reset)(void *data, enum pipe_reset_status status);
+
+   void *data;
+};
+
+/**
  * Information about memory usage. All sizes are in kilobytes.
  */
 struct pipe_memory_info

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Mesa (master): ddebug: add pass-through of set_device_reset_callback

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 07bea09c643b15307dc4282332291514276640fd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=07bea09c643b15307dc4282332291514276640fd

Author: Nicolai Hähnle 
Date:   Fri Sep 30 12:53:00 2016 +0200

ddebug: add pass-through of set_device_reset_callback

Reviewed-by: Edward O'Callaghan 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/ddebug/dd_context.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/src/gallium/drivers/ddebug/dd_context.c 
b/src/gallium/drivers/ddebug/dd_context.c
index 4bcbbff..edcbf2c 100644
--- a/src/gallium/drivers/ddebug/dd_context.c
+++ b/src/gallium/drivers/ddebug/dd_context.c
@@ -720,6 +720,15 @@ dd_context_get_device_reset_status(struct pipe_context 
*_pipe)
 }
 
 static void
+dd_context_set_device_reset_callback(struct pipe_context *_pipe,
+ const struct pipe_device_reset_callback 
*cb)
+{
+   struct pipe_context *pipe = dd_context(_pipe)->pipe;
+
+   return pipe->set_device_reset_callback(pipe, cb);
+}
+
+static void
 dd_context_emit_string_marker(struct pipe_context *_pipe,
   const char *string, int len)
 {
@@ -835,6 +844,7 @@ dd_context_create(struct dd_screen *dscreen, struct 
pipe_context *pipe)
CTX_INIT(get_sample_position);
CTX_INIT(invalidate_resource);
CTX_INIT(get_device_reset_status);
+   CTX_INIT(set_device_reset_callback);
CTX_INIT(dump_debug_state);
CTX_INIT(emit_string_marker);
 

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Mesa (master): st/mesa: set a device reset callback when available

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: a1fa8b731fc5ae12b3f4961dd3a841b384177564
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1fa8b731fc5ae12b3f4961dd3a841b384177564

Author: Nicolai Hähnle 
Date:   Fri Sep 30 14:06:04 2016 +0200

st/mesa: set a device reset callback when available

Reviewed-by: Edward O'Callaghan 
Reviewed-by: Marek Olšák 

---

 src/mesa/state_tracker/st_cb_flush.c | 31 ++-
 src/mesa/state_tracker/st_cb_flush.h |  3 +++
 src/mesa/state_tracker/st_context.h  |  2 ++
 src/mesa/state_tracker/st_manager.c  |  4 +++-
 4 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/src/mesa/state_tracker/st_cb_flush.c 
b/src/mesa/state_tracker/st_cb_flush.c
index 87c3d81..6442fc9 100644
--- a/src/mesa/state_tracker/st_cb_flush.c
+++ b/src/mesa/state_tracker/st_cb_flush.c
@@ -171,12 +171,41 @@ st_get_graphics_reset_status(struct gl_context *ctx)
struct st_context *st = st_context(ctx);
enum pipe_reset_status status;
 
-   status = st->pipe->get_device_reset_status(st->pipe);
+   if (st->reset_status != PIPE_NO_RESET) {
+  status = st->reset_status;
+  st->reset_status = PIPE_NO_RESET;
+   } else {
+  status = st->pipe->get_device_reset_status(st->pipe);
+   }
 
return gl_reset_status_from_pipe_reset_status(status);
 }
 
 
+static void
+st_device_reset_callback(void *data, enum pipe_reset_status status)
+{
+   struct st_context *st = data;
+
+   assert(status != PIPE_NO_RESET);
+
+   st->reset_status = status;
+   _mesa_set_context_lost_dispatch(st->ctx);
+}
+
+
+void
+st_install_device_reset_callback(struct st_context *st)
+{
+   if (st->pipe->set_device_reset_callback) {
+  struct pipe_device_reset_callback cb;
+  cb.reset = st_device_reset_callback;
+  cb.data = st;
+  st->pipe->set_device_reset_callback(st->pipe, );
+   }
+}
+
+
 void st_init_flush_functions(struct pipe_screen *screen,
  struct dd_function_table *functions)
 {
diff --git a/src/mesa/state_tracker/st_cb_flush.h 
b/src/mesa/state_tracker/st_cb_flush.h
index f92dcd5..5be68c9 100644
--- a/src/mesa/state_tracker/st_cb_flush.h
+++ b/src/mesa/state_tracker/st_cb_flush.h
@@ -48,6 +48,9 @@ st_flush(struct st_context *st,
 extern void
 st_finish(struct st_context *st);
 
+extern void
+st_install_device_reset_callback(struct st_context *st);
+
 
 #endif /* ST_CB_FLUSH_H */
 
diff --git a/src/mesa/state_tracker/st_context.h 
b/src/mesa/state_tracker/st_context.h
index 2b783e0..83d77fd 100644
--- a/src/mesa/state_tracker/st_context.h
+++ b/src/mesa/state_tracker/st_context.h
@@ -253,6 +253,8 @@ struct st_context
struct st_config_options options;
 
struct st_perf_monitor_group *perfmon;
+
+   enum pipe_reset_status reset_status;
 };
 
 
diff --git a/src/mesa/state_tracker/st_manager.c 
b/src/mesa/state_tracker/st_manager.c
index fece5d5..6922454 100644
--- a/src/mesa/state_tracker/st_manager.c
+++ b/src/mesa/state_tracker/st_manager.c
@@ -688,8 +688,10 @@ st_api_create_context(struct st_api *stapi, struct 
st_manager *smapi,
   st->ctx->Const.ContextFlags |= GL_CONTEXT_FLAG_FORWARD_COMPATIBLE_BIT;
if (attribs->flags & ST_CONTEXT_FLAG_ROBUST_ACCESS)
   st->ctx->Const.ContextFlags |= GL_CONTEXT_FLAG_ROBUST_ACCESS_BIT_ARB;
-   if (attribs->flags & ST_CONTEXT_FLAG_RESET_NOTIFICATION_ENABLED)
+   if (attribs->flags & ST_CONTEXT_FLAG_RESET_NOTIFICATION_ENABLED) {
   st->ctx->Const.ResetStrategy = GL_LOSE_CONTEXT_ON_RESET_ARB;
+  st_install_device_reset_callback(st);
+   }
 
/* need to perform version check */
if (attribs->major > 1 || attribs->minor > 0) {

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Mesa (master): gallium/radeon: implement set_device_reset_callback

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: b5cd7dfe3e9a04bf6edd5d100f7c74b8fcb5c277
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5cd7dfe3e9a04bf6edd5d100f7c74b8fcb5c277

Author: Nicolai Hähnle 
Date:   Fri Sep 30 15:21:00 2016 +0200

gallium/radeon: implement set_device_reset_callback

Check for device reset on flush. It would be nicer if the kernel just
reported this as an error on the submit ioctl (and similarly for fences),
but this will do for now.

Reviewed-by: Edward O'Callaghan 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/r600/r600_hw_context.c|  3 +++
 src/gallium/drivers/radeon/r600_pipe_common.c | 32 +++
 src/gallium/drivers/radeon/r600_pipe_common.h |  2 ++
 src/gallium/drivers/radeonsi/si_hw_context.c  |  3 +++
 4 files changed, 40 insertions(+)

diff --git a/src/gallium/drivers/r600/r600_hw_context.c 
b/src/gallium/drivers/r600/r600_hw_context.c
index dc5ad75..bc6217a 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -258,6 +258,9 @@ void r600_context_gfx_flush(void *context, unsigned flags,
if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size))
return;
 
+   if (r600_check_device_reset(>b))
+   return;
+
r600_preflush_suspend_features(>b);
 
/* flush the framebuffer cache */
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 3a5a854..6f71ef6 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -484,6 +484,36 @@ static void r600_set_debug_callback(struct pipe_context 
*ctx,
memset(>debug, 0, sizeof(rctx->debug));
 }
 
+static void r600_set_device_reset_callback(struct pipe_context *ctx,
+  const struct 
pipe_device_reset_callback *cb)
+{
+   struct r600_common_context *rctx = (struct r600_common_context *)ctx;
+
+   if (cb)
+   rctx->device_reset_callback = *cb;
+   else
+   memset(>device_reset_callback, 0,
+  sizeof(rctx->device_reset_callback));
+}
+
+bool r600_check_device_reset(struct r600_common_context *rctx)
+{
+   enum pipe_reset_status status;
+
+   if (!rctx->device_reset_callback.reset)
+   return false;
+
+   if (!rctx->b.get_device_reset_status)
+   return false;
+
+   status = rctx->b.get_device_reset_status(>b);
+   if (status == PIPE_NO_RESET)
+   return false;
+
+   rctx->device_reset_callback.reset(rctx->device_reset_callback.data, 
status);
+   return true;
+}
+
 bool r600_common_context_init(struct r600_common_context *rctx,
  struct r600_common_screen *rscreen,
  unsigned context_flags)
@@ -527,6 +557,8 @@ bool r600_common_context_init(struct r600_common_context 
*rctx,
  RADEON_GPU_RESET_COUNTER);
}
 
+   rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
+
r600_init_context_texture_functions(rctx);
r600_init_viewport_functions(rctx);
r600_streamout_init(rctx);
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 4ee7daa..54991e8 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -619,6 +619,7 @@ struct r600_common_context {
} dcc_stats[5];
 
struct pipe_debug_callback  debug;
+   struct pipe_device_reset_callback device_reset_callback;
 
void*query_result_shader;
 
@@ -733,6 +734,7 @@ void r600_dma_emit_wait_idle(struct r600_common_context 
*rctx);
 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
struct radeon_saved_cs *saved);
 void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
+bool r600_check_device_reset(struct r600_common_context *rctx);
 
 /* r600_gpu_load.c */
 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c 
b/src/gallium/drivers/radeonsi/si_hw_context.c
index 3373fb8..7c11baf 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -103,6 +103,9 @@ void si_context_gfx_flush(void *context, unsigned flags,
if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size))
return;
 
+   if (r600_check_device_reset(>b))
+   return;
+
ctx->gfx_flush_in_progress = true;
 
r600_preflush_suspend_features(>b);

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Mesa (master): st/mesa: enable GL_KHR_robustness

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 0cba7b771a40c87e6a47ccf2381f1d300e9217ef
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0cba7b771a40c87e6a47ccf2381f1d300e9217ef

Author: Nicolai Hähnle 
Date:   Wed Sep 28 10:54:34 2016 +0200

st/mesa: enable GL_KHR_robustness

The difference to the virtually identical ARB_robustness (which is already
enabled unconditionally) is miniscule and handled elsewhere, but this cap
seems like the right thing to require for this extension.

v2: drop the device reset cap requirement (Ilia)

Reviewed-by: Marek Olšák  (v1)
Reviewed-by: Ilia Mirkin 
Reviewed-by: Edward O'Callaghan 

---

 docs/features.txt  | 2 +-
 docs/relnotes/12.1.0.html  | 1 +
 src/mesa/state_tracker/st_extensions.c | 2 ++
 3 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/docs/features.txt b/docs/features.txt
index 037ee97..85ad1a1 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -218,7 +218,7 @@ GL 4.5, GLSL 4.50:
   GL_ARB_shader_texture_image_samples   DONE (i965, nv50, 
nvc0, r600, radeonsi)
   GL_ARB_texture_barrierDONE (i965, nv50, 
nvc0, r600, radeonsi)
   GL_KHR_context_flush_control  DONE (all - but needs 
GLX/EGL extension to be useful)
-  GL_KHR_robustness DONE (i965)
+  GL_KHR_robustness DONE (i965, nvc0, 
radeonsi)
   GL_EXT_shader_integer_mix DONE (all drivers that 
support GLSL)
 
 These are the extensions cherry-picked to make GLES 3.1
diff --git a/docs/relnotes/12.1.0.html b/docs/relnotes/12.1.0.html
index dd17979..aff4dd3 100644
--- a/docs/relnotes/12.1.0.html
+++ b/docs/relnotes/12.1.0.html
@@ -60,6 +60,7 @@ Note: some of the new features are only available with 
certain drivers.
 GL_ARB_texture_stencil8 on i965/hsw
 GL_EXT_window_rectangles on nv50, nvc0
 GL_KHR_blend_equation_advanced on i965
+GL_KHR_robustness on nvc0, radeonsi
 GL_KHR_texture_compression_astc_sliced_3d on i965
 GL_OES_copy_image on nv50, nvc0, r600, radeonsi, softpipe, llvmpipe
 GL_OES_geometry_shader on i965/gen8+, nvc0, radeonsi
diff --git a/src/mesa/state_tracker/st_extensions.c 
b/src/mesa/state_tracker/st_extensions.c
index 4f42217..2282dc7 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -1199,6 +1199,8 @@ void st_init_extensions(struct pipe_screen *screen,
   }
}
 
+   extensions->KHR_robustness = extensions->ARB_robust_buffer_access_behavior;
+
/* If we support ES 3.1, we support the ES3_1_compatibility ext. However
 * there's no clean way of telling whether we would support ES 3.1 from
 * here, so copy the condition from compute_version_es2 here. A lot of

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Mesa (master): vc4: use the new parent/child pools for transfers

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 2a83036fe29262c8761812c65d6e81c7198da54e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a83036fe29262c8761812c65d6e81c7198da54e

Author: Nicolai Hähnle 
Date:   Tue Sep 27 19:09:24 2016 +0200

vc4: use the new parent/child pools for transfers

Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/vc4/vc4_context.c  | 5 ++---
 src/gallium/drivers/vc4/vc4_context.h  | 2 +-
 src/gallium/drivers/vc4/vc4_resource.c | 4 ++--
 src/gallium/drivers/vc4/vc4_screen.c   | 3 +++
 src/gallium/drivers/vc4/vc4_screen.h   | 3 +++
 5 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/vc4/vc4_context.c 
b/src/gallium/drivers/vc4/vc4_context.c
index 3863e44..b780b13 100644
--- a/src/gallium/drivers/vc4/vc4_context.c
+++ b/src/gallium/drivers/vc4/vc4_context.c
@@ -96,7 +96,7 @@ vc4_context_destroy(struct pipe_context *pctx)
 if (vc4->uploader)
 u_upload_destroy(vc4->uploader);
 
-slab_destroy(>transfer_pool);
+slab_destroy_child(>transfer_pool);
 
 pipe_surface_reference(>framebuffer.cbufs[0], NULL);
 pipe_surface_reference(>framebuffer.zsbuf, NULL);
@@ -139,8 +139,7 @@ vc4_context_create(struct pipe_screen *pscreen, void *priv, 
unsigned flags)
 
 vc4->fd = screen->fd;
 
-slab_create(>transfer_pool, sizeof(struct vc4_transfer),
- 16);
+slab_create_child(>transfer_pool, >transfer_pool);
 vc4->blitter = util_blitter_create(pctx);
 if (!vc4->blitter)
 goto fail;
diff --git a/src/gallium/drivers/vc4/vc4_context.h 
b/src/gallium/drivers/vc4/vc4_context.h
index 87d8c79..0d6b8d0 100644
--- a/src/gallium/drivers/vc4/vc4_context.h
+++ b/src/gallium/drivers/vc4/vc4_context.h
@@ -297,7 +297,7 @@ struct vc4_context {
  */
 struct hash_table *write_jobs;
 
-struct slab_mempool transfer_pool;
+struct slab_child_pool transfer_pool;
 struct blitter_context *blitter;
 
 /** bitfield of VC4_DIRTY_* */
diff --git a/src/gallium/drivers/vc4/vc4_resource.c 
b/src/gallium/drivers/vc4/vc4_resource.c
index bfa8f40..9932bb3 100644
--- a/src/gallium/drivers/vc4/vc4_resource.c
+++ b/src/gallium/drivers/vc4/vc4_resource.c
@@ -120,7 +120,7 @@ vc4_resource_transfer_unmap(struct pipe_context *pctx,
 }
 
 pipe_resource_reference(>resource, NULL);
-slab_free_st(>transfer_pool, ptrans);
+slab_free(>transfer_pool, ptrans);
 }
 
 static struct pipe_resource *
@@ -196,7 +196,7 @@ vc4_resource_transfer_map(struct pipe_context *pctx,
 if (usage & PIPE_TRANSFER_WRITE)
 rsc->writes++;
 
-trans = slab_alloc_st(>transfer_pool);
+trans = slab_alloc(>transfer_pool);
 if (!trans)
 return NULL;
 
diff --git a/src/gallium/drivers/vc4/vc4_screen.c 
b/src/gallium/drivers/vc4/vc4_screen.c
index 3dc85d5..64bff5d 100644
--- a/src/gallium/drivers/vc4/vc4_screen.c
+++ b/src/gallium/drivers/vc4/vc4_screen.c
@@ -98,6 +98,7 @@ vc4_screen_destroy(struct pipe_screen *pscreen)
 
 util_hash_table_destroy(screen->bo_handles);
 vc4_bufmgr_destroy(pscreen);
+slab_destroy_parent(>transfer_pool);
 close(screen->fd);
 ralloc_free(pscreen);
 }
@@ -614,6 +615,8 @@ vc4_screen_create(int fd)
 if (!vc4_get_chip_info(screen))
 goto fail;
 
+slab_create_parent(>transfer_pool, sizeof(struct 
vc4_transfer), 16);
+
 vc4_fence_init(screen);
 
 vc4_debug = debug_get_option_vc4_debug();
diff --git a/src/gallium/drivers/vc4/vc4_screen.h 
b/src/gallium/drivers/vc4/vc4_screen.h
index 36fe1c7..16003cf 100644
--- a/src/gallium/drivers/vc4/vc4_screen.h
+++ b/src/gallium/drivers/vc4/vc4_screen.h
@@ -28,6 +28,7 @@
 #include "os/os_thread.h"
 #include "state_tracker/drm_driver.h"
 #include "util/list.h"
+#include "util/slab.h"
 
 struct vc4_bo;
 
@@ -64,6 +65,8 @@ struct vc4_screen {
  */
 uint64_t finished_seqno;
 
+struct slab_parent_pool transfer_pool;
+
 struct vc4_bo_cache {
 /** List of struct vc4_bo freed, by age. */
 struct list_head time_list;

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Mesa (master): gallium/radeon: use the new parent/ child pools for transfers

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: e56e1f8119f28eebbe6fbe7040c80a6dd884f5fd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e56e1f8119f28eebbe6fbe7040c80a6dd884f5fd

Author: Nicolai Hähnle 
Date:   Tue Sep 27 18:53:45 2016 +0200

gallium/radeon: use the new parent/child pools for transfers

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97894
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeon/r600_buffer_common.c | 4 ++--
 src/gallium/drivers/radeon/r600_pipe_common.c   | 9 ++---
 src/gallium/drivers/radeon/r600_pipe_common.h   | 4 +++-
 3 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c 
b/src/gallium/drivers/radeon/r600_buffer_common.c
index 228674a..74bec26 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -283,7 +283,7 @@ static void *r600_buffer_get_transfer(struct pipe_context 
*ctx,
  unsigned offset)
 {
struct r600_common_context *rctx = (struct r600_common_context*)ctx;
-   struct r600_transfer *transfer = slab_alloc_st(>pool_transfers);
+   struct r600_transfer *transfer = slab_alloc(>pool_transfers);
 
transfer->transfer.resource = resource;
transfer->transfer.level = level;
@@ -468,7 +468,7 @@ static void r600_buffer_transfer_unmap(struct pipe_context 
*ctx,
if (rtransfer->staging)
r600_resource_reference(>staging, NULL);
 
-   slab_free_st(>pool_transfers, transfer);
+   slab_free(>pool_transfers, transfer);
 }
 
 void r600_buffer_subdata(struct pipe_context *ctx,
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 9e03aaa..3a5a854 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -488,8 +488,7 @@ bool r600_common_context_init(struct r600_common_context 
*rctx,
  struct r600_common_screen *rscreen,
  unsigned context_flags)
 {
-   slab_create(>pool_transfers,
-sizeof(struct r600_transfer), 64);
+   slab_create_child(>pool_transfers, >pool_transfers);
 
rctx->screen = rscreen;
rctx->ws = rscreen->ws;
@@ -590,7 +589,7 @@ void r600_common_context_cleanup(struct r600_common_context 
*rctx)
u_upload_destroy(rctx->uploader);
}
 
-   slab_destroy(>pool_transfers);
+   slab_destroy_child(>pool_transfers);
 
if (rctx->allocator_zeroed_memory) {
u_suballocator_destroy(rctx->allocator_zeroed_memory);
@@ -1183,6 +1182,8 @@ bool r600_common_screen_init(struct r600_common_screen 
*rscreen,
rscreen->chip_class = rscreen->info.chip_class;
rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", 
common_debug_options, 0);
 
+   slab_create_parent(>pool_transfers, sizeof(struct 
r600_transfer), 64);
+
rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", 
-1));
if (rscreen->force_aniso >= 0) {
printf("radeon: Forcing anisotropy filter to %ix\n",
@@ -1242,6 +1243,8 @@ void r600_destroy_common_screen(struct r600_common_screen 
*rscreen)
pipe_mutex_destroy(rscreen->aux_context_lock);
rscreen->aux_context->destroy(rscreen->aux_context);
 
+   slab_destroy_parent(>pool_transfers);
+
rscreen->ws->destroy(rscreen->ws);
FREE(rscreen);
 }
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 6d03db6..4ee7daa 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -370,6 +370,8 @@ struct r600_common_screen {
boolhas_cp_dma;
boolhas_streamout;
 
+   struct slab_parent_pool pool_transfers;
+
/* Texture filter settings. */
int force_aniso; /* -1 = disabled */
 
@@ -542,7 +544,7 @@ struct r600_common_context {
 
struct u_upload_mgr *uploader;
struct u_suballocator   *allocator_zeroed_memory;
-   struct slab_mempool pool_transfers;
+   struct slab_child_pool  pool_transfers;
 
/* Current unaccounted memory usage. */
uint64_tvram;

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Mesa (master): virgl: use the new parent/child pools for transfers

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 8a943564fd7ebacd2437bb907535b7765ff448e4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a943564fd7ebacd2437bb907535b7765ff448e4

Author: Nicolai Hähnle 
Date:   Tue Sep 27 19:12:24 2016 +0200

virgl: use the new parent/child pools for transfers

Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/virgl/virgl_buffer.c  | 4 ++--
 src/gallium/drivers/virgl/virgl_context.c | 5 ++---
 src/gallium/drivers/virgl/virgl_context.h | 2 +-
 src/gallium/drivers/virgl/virgl_screen.c  | 4 
 src/gallium/drivers/virgl/virgl_screen.h  | 3 +++
 src/gallium/drivers/virgl/virgl_texture.c | 4 ++--
 6 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_buffer.c 
b/src/gallium/drivers/virgl/virgl_buffer.c
index de99796..2e63aeb 100644
--- a/src/gallium/drivers/virgl/virgl_buffer.c
+++ b/src/gallium/drivers/virgl/virgl_buffer.c
@@ -62,7 +62,7 @@ static void *virgl_buffer_transfer_map(struct pipe_context 
*ctx,
if (doflushwait)
   ctx->flush(ctx, NULL, 0);
 
-   trans = slab_alloc_st(>texture_transfer_pool);
+   trans = slab_alloc(>texture_transfer_pool);
if (!trans)
   return NULL;
 
@@ -114,7 +114,7 @@ static void virgl_buffer_transfer_unmap(struct pipe_context 
*ctx,
   }
}
 
-   slab_free_st(>texture_transfer_pool, trans);
+   slab_free(>texture_transfer_pool, trans);
 }
 
 static void virgl_buffer_transfer_flush_region(struct pipe_context *ctx,
diff --git a/src/gallium/drivers/virgl/virgl_context.c 
b/src/gallium/drivers/virgl/virgl_context.c
index a6c0597..e693a73 100644
--- a/src/gallium/drivers/virgl/virgl_context.c
+++ b/src/gallium/drivers/virgl/virgl_context.c
@@ -862,7 +862,7 @@ virgl_context_destroy( struct pipe_context *ctx )
   u_upload_destroy(vctx->uploader);
util_primconvert_destroy(vctx->primconvert);
 
-   slab_destroy(>texture_transfer_pool);
+   slab_destroy_child(>texture_transfer_pool);
FREE(vctx);
 }
 
@@ -943,8 +943,7 @@ struct pipe_context *virgl_context_create(struct 
pipe_screen *pscreen,
virgl_init_so_functions(vctx);
 
list_inithead(>to_flush_bufs);
-   slab_create(>texture_transfer_pool, sizeof(struct virgl_transfer),
-16);
+   slab_create_child(>texture_transfer_pool, rs->texture_transfer_pool);
 
vctx->primconvert = util_primconvert_create(>base, 
rs->caps.caps.v1.prim_mask);
vctx->uploader = u_upload_create(>base, 1024 * 1024,
diff --git a/src/gallium/drivers/virgl/virgl_context.h 
b/src/gallium/drivers/virgl/virgl_context.h
index 3b9901f..597ed49 100644
--- a/src/gallium/drivers/virgl/virgl_context.h
+++ b/src/gallium/drivers/virgl/virgl_context.h
@@ -56,7 +56,7 @@ struct virgl_context {
 
struct pipe_framebuffer_state framebuffer;
 
-   struct slab_mempool texture_transfer_pool;
+   struct slab_child_pool texture_transfer_pool;
 
struct pipe_index_buffer index_buffer;
struct u_upload_mgr *uploader;
diff --git a/src/gallium/drivers/virgl/virgl_screen.c 
b/src/gallium/drivers/virgl/virgl_screen.c
index dd135a7..5f98754 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -547,6 +547,8 @@ virgl_destroy_screen(struct pipe_screen *screen)
struct virgl_screen *vscreen = virgl_screen(screen);
struct virgl_winsys *vws = vscreen->vws;
 
+   slab_destroy_parent(>texture_transfer_pool);
+
if (vws)
   vws->destroy(vws);
FREE(vscreen);
@@ -581,6 +583,8 @@ virgl_create_screen(struct virgl_winsys *vws)
 
screen->refcnt = 1;
 
+   slab_create_parent(>texture_transfer_pool, sizeof(struct 
virgl_transfer), 16);
+
util_format_s3tc_init();
return >base;
 }
diff --git a/src/gallium/drivers/virgl/virgl_screen.h 
b/src/gallium/drivers/virgl/virgl_screen.h
index 8cac38d..dcf5816 100644
--- a/src/gallium/drivers/virgl/virgl_screen.h
+++ b/src/gallium/drivers/virgl/virgl_screen.h
@@ -24,6 +24,7 @@
 #define VIRGL_H
 
 #include "pipe/p_screen.h"
+#include "util/slab.h"
 #include "virgl_winsys.h"
 
 struct virgl_screen {
@@ -38,6 +39,8 @@ struct virgl_screen {
 
struct virgl_drm_caps caps;
 
+   struct slab_parent_pool texture_transfer_pool;
+
uint32_t sub_ctx_id;
 };
 
diff --git a/src/gallium/drivers/virgl/virgl_texture.c 
b/src/gallium/drivers/virgl/virgl_texture.c
index 24bbc3c..150a5eb 100644
--- a/src/gallium/drivers/virgl/virgl_texture.c
+++ b/src/gallium/drivers/virgl/virgl_texture.c
@@ -145,7 +145,7 @@ static void *virgl_texture_transfer_map(struct pipe_context 
*ctx,
if (doflushwait)
   ctx->flush(ctx, NULL, 0);
 
-   trans = slab_alloc_st(>texture_transfer_pool);
+   trans = slab_alloc(>texture_transfer_pool);
if (!trans)
   return NULL;
 
@@ -235,7 +235,7 @@ static void virgl_texture_transfer_unmap(struct 
pipe_context *ctx,
if (trans->resolve_tmp)
   pipe_resource_reference((struct pipe_resource **)>resolve_tmp, 
NULL);
 
-   slab_free_st(>texture_transfer_pool, trans);
+   

Mesa (master): i965: use L3 data cache for SSBOs

[Lionel Landwerlin]

Module: Mesa
Branch: master
Commit: d51c1f9d51ef0e80873a9a32c48606cdce25a209
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d51c1f9d51ef0e80873a9a32c48606cdce25a209

Author: Lionel Landwerlin 
Date:   Mon Sep 26 15:08:52 2016 +0100

i965: use L3 data cache for SSBOs

Anv programs the hardware to use L3 data cache if we use either SSBOs or
images in the shaders, we can program i965 the same way.

gl_shader_program has a bit of a confusing named field with
'NumAtomicBuffers'. It doesn't tell how many buffers are accessed by the
shader in an atomic way but instead the number of atomic counters
manipulated by the shader.

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Francisco Jerez 

---

 src/mesa/drivers/dri/i965/gen7_l3_state.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c 
b/src/mesa/drivers/dri/i965/gen7_l3_state.c
index ad70491..0692b08 100644
--- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
@@ -53,7 +53,8 @@ get_pipeline_state_l3_weights(const struct brw_context *brw)
  brw->ctx._Shader->CurrentProgram[stage_states[i]->stage];
   const struct brw_stage_prog_data *prog_data = stage_states[i]->prog_data;
 
-  needs_dc |= (prog && prog->NumAtomicBuffers) ||
+  needs_dc |= (prog && (prog->NumAtomicBuffers ||
+prog->NumShaderStorageBlocks)) ||
  (prog_data && (prog_data->total_scratch || 
prog_data->nr_image_params));
   needs_slm |= prog_data && prog_data->total_shared;
}

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