Mesa (master): i965: Fix gl_InvocationID in dual object GS where invocations == 1.

2016-10-17 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: 9f677d6541741af483c22f29e81f0d883f86028a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f677d6541741af483c22f29e81f0d883f86028a

Author: Kenneth Graunke 
Date:   Fri Oct 14 20:08:47 2016 -0700

i965: Fix gl_InvocationID in dual object GS where invocations == 1.

dEQP-GLES31.functional.geometry_shading.instanced.geometry_1_invocations
draws using a geometry shader that specifies

   layout(points, invocations = 1) in;

and then uses gl_InvocationID.  According to the Haswell PRM, the
"GS Instance ID 0" (and 1) thread payload fields are undefined in
dual object mode:

   "If 'dispatch mode' is DUAL_OBJECT this field is not valid."

But there's no point in using them - if there's only one invocation,
the ID will be 0.  So just load a constant.

Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Kenneth Graunke 
Reviewed-by: Anuj Phogat 

---

 src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index c5886d4..59c7d21 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -59,7 +59,10 @@ vec4_gs_visitor::make_reg_for_system_value(int location)
switch (location) {
case SYSTEM_VALUE_INVOCATION_ID:
   this->current_annotation = "initialize gl_InvocationID";
-  emit(GS_OPCODE_GET_INSTANCE_ID, *reg);
+  if (gs_prog_data->invocations > 1)
+ emit(GS_OPCODE_GET_INSTANCE_ID, *reg);
+  else
+ emit(MOV(*reg, brw_imm_ud(0)));
   break;
default:
   unreachable("not reached");

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Mesa (master): anv/cmd_buffer: Expose ensure_push_constant_*

2016-10-17 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: eddaa237c0d3bf03afe3448a6134ebcb8cc8ad0b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eddaa237c0d3bf03afe3448a6134ebcb8cc8ad0b

Author: Jason Ekstrand 
Date:   Mon Oct 17 10:10:26 2016 -0700

anv/cmd_buffer: Expose ensure_push_constant_*

Signed-off-by: Jason Ekstrand 
Reviewed-by: Anuj Phogat 

---

 src/intel/vulkan/anv_cmd_buffer.c | 7 +--
 src/intel/vulkan/anv_private.h| 8 
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index 3c2d032..98257f8 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -200,7 +200,7 @@ anv_cmd_state_setup_attachments(struct anv_cmd_buffer 
*cmd_buffer,
}
 }
 
-static VkResult
+VkResult
 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
   gl_shader_stage stage, uint32_t size)
 {
@@ -222,11 +222,6 @@ anv_cmd_buffer_ensure_push_constants_size(struct 
anv_cmd_buffer *cmd_buffer,
return VK_SUCCESS;
 }
 
-#define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
-   anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
-  (offsetof(struct anv_push_constants, field) + \
-   sizeof(cmd_buffer->state.push_constants[0]->field)))
-
 static VkResult anv_create_cmd_buffer(
 struct anv_device * device,
 struct anv_cmd_pool *   pool,
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 9454e08..5584d56 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1286,6 +1286,14 @@ void anv_cmd_buffer_prepare_execbuf(struct 
anv_cmd_buffer *cmd_buffer);
 
 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
 
+VkResult
+anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
+  gl_shader_stage stage, uint32_t 
size);
+#define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
+   anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
+  (offsetof(struct anv_push_constants, field) + \
+   sizeof(cmd_buffer->state.push_constants[0]->field)))
+
 VkResult anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
unsigned stage, struct anv_state 
*bt_state);
 VkResult anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer *cmd_buffer,

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Mesa (master): anv/cmd_buffer: Move state base address re-emit into ExecuteCommands

2016-10-17 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: ac0ca066de654fd80a6f18c9c32555d7d91c0335
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac0ca066de654fd80a6f18c9c32555d7d91c0335

Author: Jason Ekstrand 
Date:   Mon Oct 17 09:14:48 2016 -0700

anv/cmd_buffer: Move state base address re-emit into ExecuteCommands

This has two primary advantages.  First, it means that the batch_chain code
knows less about the actual command buffer contents which is good because
improves separation.  Second, it means that it only gets re-emitted once
after all of the secondaries instead of once after each secondary which is
just wasteful.  It also has the advantage of cleaning the code up a bit.

Signed-off-by: Jason Ekstrand 
Reviewed-by: Anuj Phogat 

---

 src/intel/vulkan/anv_batch_chain.c | 6 --
 src/intel/vulkan/anv_cmd_buffer.c  | 9 +
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/intel/vulkan/anv_batch_chain.c 
b/src/intel/vulkan/anv_batch_chain.c
index a98a0a9..95854f4 100644
--- a/src/intel/vulkan/anv_batch_chain.c
+++ b/src/intel/vulkan/anv_batch_chain.c
@@ -777,7 +777,6 @@ anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
switch (secondary->exec_mode) {
case ANV_CMD_BUFFER_EXEC_MODE_EMIT:
   anv_batch_emit_batch(>batch, >batch);
-  anv_cmd_buffer_emit_state_base_address(primary);
   break;
case ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT: {
   struct anv_batch_bo *bbo = anv_cmd_buffer_current_batch_bo(primary);
@@ -785,7 +784,6 @@ anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
   anv_batch_bo_grow(primary, bbo, >batch, length,
 GEN8_MI_BATCH_BUFFER_START_length * 4);
   anv_batch_emit_batch(>batch, >batch);
-  anv_cmd_buffer_emit_state_base_address(primary);
   break;
}
case ANV_CMD_BUFFER_EXEC_MODE_CHAIN: {
@@ -826,8 +824,6 @@ anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
 p += CACHELINE_SIZE;
  }
   }
-
-  anv_cmd_buffer_emit_state_base_address(primary);
   break;
}
case ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN: {
@@ -851,8 +847,6 @@ anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
 
   anv_batch_bo_continue(last_bbo, >batch,
 GEN8_MI_BATCH_BUFFER_START_length * 4);
-
-  anv_cmd_buffer_emit_state_base_address(primary);
   break;
}
default:
diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index 5bcd5e0..b55a070 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -1180,6 +1180,15 @@ void anv_CmdExecuteCommands(
 
   anv_cmd_buffer_add_secondary(primary, secondary);
}
+
+   /* Each of the secondary command buffers will use its own state base
+* address.  We need to re-emit state base address for the primary after
+* all of the secondaries are done.
+*
+* TODO: Maybe we want to make this a dirty bit to avoid extra state base
+* address calls?
+*/
+   anv_cmd_buffer_emit_state_base_address(primary);
 }
 
 VkResult anv_CreateCommandPool(

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Mesa (master): anv: Get rid of anv_cmd_buffer_emit_state_base_address

2016-10-17 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: 52904ba85c7e1e3092601e3497bfbc246b00b84a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=52904ba85c7e1e3092601e3497bfbc246b00b84a

Author: Jason Ekstrand 
Date:   Mon Oct 17 10:13:07 2016 -0700

anv: Get rid of anv_cmd_buffer_emit_state_base_address

All code that would have once called this can now call the gen-specific
version.  The switching version is no longer needed.

Signed-off-by: Jason Ekstrand 
Reviewed-by: Anuj Phogat 

---

 src/intel/vulkan/anv_cmd_buffer.c  | 18 --
 src/intel/vulkan/anv_private.h |  2 --
 src/intel/vulkan/genX_blorp_exec.c |  2 +-
 3 files changed, 1 insertion(+), 21 deletions(-)

diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index 26a2be6..72f4f28 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -348,24 +348,6 @@ VkResult anv_ResetCommandBuffer(
return anv_cmd_buffer_reset(cmd_buffer);
 }
 
-void
-anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
-{
-   switch (cmd_buffer->device->info.gen) {
-   case 7:
-  if (cmd_buffer->device->info.is_haswell)
- return gen75_cmd_buffer_emit_state_base_address(cmd_buffer);
-  else
- return gen7_cmd_buffer_emit_state_base_address(cmd_buffer);
-   case 8:
-  return gen8_cmd_buffer_emit_state_base_address(cmd_buffer);
-   case 9:
-  return gen9_cmd_buffer_emit_state_base_address(cmd_buffer);
-   default:
-  unreachable("unsupported gen\n");
-   }
-}
-
 void anv_CmdBindPipeline(
 VkCommandBuffer commandBuffer,
 VkPipelineBindPoint pipelineBindPoint,
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 49b3398..a4a1dd0 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1319,8 +1319,6 @@ void gen8_cmd_buffer_emit_depth_viewport(struct 
anv_cmd_buffer *cmd_buffer,
  bool depth_clamp_enable);
 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
 
-void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
-
 void anv_cmd_state_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
  const VkRenderPassBeginInfo *info);
 
diff --git a/src/intel/vulkan/genX_blorp_exec.c 
b/src/intel/vulkan/genX_blorp_exec.c
index d43de91..185aff6 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -97,7 +97,7 @@ blorp_alloc_binding_table(struct blorp_batch *batch, unsigned 
num_entries,
   /* Re-emit state base addresses so we get the new surface state base
* address before we start emitting binding tables etc.
*/
-  anv_cmd_buffer_emit_state_base_address(cmd_buffer);
+  genX(cmd_buffer_emit_state_base_address)(cmd_buffer);
 
   bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
 _offset);

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Mesa (master): anv/cmd_buffer: Move Begin/End/Execute to genX_cmd_buffer.c

2016-10-17 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: 2314c9ed2e39bcf4ac6b206344acb05fec876a41
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2314c9ed2e39bcf4ac6b206344acb05fec876a41

Author: Jason Ekstrand 
Date:   Mon Oct 17 09:28:46 2016 -0700

anv/cmd_buffer: Move Begin/End/Execute to genX_cmd_buffer.c

vkBeginCommandBuffer and vkCmdExecuteCommands both call into the
gen-specific emit_state_base_address function and vkEndCommandBuffer
belongs with begin.

Signed-off-by: Jason Ekstrand 
Reviewed-by: Anuj Phogat 

---

 src/intel/vulkan/anv_cmd_buffer.c  | 94 +
 src/intel/vulkan/anv_dump.c| 11 -
 src/intel/vulkan/anv_private.h |  2 +
 src/intel/vulkan/genX_cmd_buffer.c | 95 ++
 4 files changed, 107 insertions(+), 95 deletions(-)

diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index b55a070..3c2d032 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -327,7 +327,7 @@ void anv_FreeCommandBuffers(
}
 }
 
-static VkResult
+VkResult
 anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer)
 {
cmd_buffer->usage_flags = 0;
@@ -371,71 +371,6 @@ anv_cmd_buffer_emit_state_base_address(struct 
anv_cmd_buffer *cmd_buffer)
}
 }
 
-VkResult anv_BeginCommandBuffer(
-VkCommandBuffer commandBuffer,
-const VkCommandBufferBeginInfo* pBeginInfo)
-{
-   ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
-
-   /* If this is the first vkBeginCommandBuffer, we must *initialize* the
-* command buffer's state. Otherwise, we must *reset* its state. In both
-* cases we reset it.
-*
-* From the Vulkan 1.0 spec:
-*
-*If a command buffer is in the executable state and the command buffer
-*was allocated from a command pool with the
-*VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
-*vkBeginCommandBuffer implicitly resets the command buffer, behaving
-*as if vkResetCommandBuffer had been called with
-*VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
-*the command buffer in the recording state.
-*/
-   anv_cmd_buffer_reset(cmd_buffer);
-
-   cmd_buffer->usage_flags = pBeginInfo->flags;
-
-   assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY ||
-  !(cmd_buffer->usage_flags & 
VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT));
-
-   anv_cmd_buffer_emit_state_base_address(cmd_buffer);
-
-   if (cmd_buffer->usage_flags &
-   VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
-  cmd_buffer->state.framebuffer =
- 
anv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
-  cmd_buffer->state.pass =
- anv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
-  cmd_buffer->state.subpass =
- 
_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
-
-  cmd_buffer->state.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
-   }
-
-   return VK_SUCCESS;
-}
-
-VkResult anv_EndCommandBuffer(
-VkCommandBuffer commandBuffer)
-{
-   ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
-   struct anv_device *device = cmd_buffer->device;
-
-   anv_cmd_buffer_end_batch_buffer(cmd_buffer);
-
-   if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
-  /* The algorithm used to compute the validate list is not threadsafe as
-   * it uses the bo->index field.  We have to lock the device around it.
-   * Fortunately, the chances for contention here are probably very low.
-   */
-  pthread_mutex_lock(>mutex);
-  anv_cmd_buffer_prepare_execbuf(cmd_buffer);
-  pthread_mutex_unlock(>mutex);
-   }
-
-   return VK_SUCCESS;
-}
-
 void anv_CmdBindPipeline(
 VkCommandBuffer commandBuffer,
 VkPipelineBindPoint pipelineBindPoint,
@@ -1164,33 +1099,6 @@ void anv_CmdPushConstants(
cmd_buffer->state.push_constants_dirty |= stageFlags;
 }
 
-void anv_CmdExecuteCommands(
-VkCommandBuffer commandBuffer,
-uint32_tcommandBufferCount,
-const VkCommandBuffer*  pCmdBuffers)
-{
-   ANV_FROM_HANDLE(anv_cmd_buffer, primary, commandBuffer);
-
-   assert(primary->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
-
-   for (uint32_t i = 0; i < commandBufferCount; i++) {
-  ANV_FROM_HANDLE(anv_cmd_buffer, secondary, pCmdBuffers[i]);
-
-  assert(secondary->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY);
-
-  anv_cmd_buffer_add_secondary(primary, secondary);
-   }
-
-   /* Each of the secondary command buffers will use its own state base
-* address.  We need to re-emit state base address for the primary after
-* all of the secondaries are done.
-*
-

Mesa (master): anv/cmd_buffer: Unify flush_compute_state across gens

2016-10-17 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: 1f3e6468d2a3efd9f2da99fa337dfe4b804bcda6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f3e6468d2a3efd9f2da99fa337dfe4b804bcda6

Author: Jason Ekstrand 
Date:   Mon Oct 17 10:03:16 2016 -0700

anv/cmd_buffer: Unify flush_compute_state across gens

With one small genxml change, the two versions were basically identical.
The only differences were one #define for HSW+ and a field that is missing
on Haswell but exists everywhere else.

Signed-off-by: Jason Ekstrand 
Reviewed-by: Anuj Phogat 

---

 src/intel/genxml/gen8.xml  |  2 +-
 src/intel/genxml/gen9.xml  |  2 +-
 src/intel/vulkan/gen7_cmd_buffer.c | 88 
 src/intel/vulkan/gen8_cmd_buffer.c | 87 
 src/intel/vulkan/genX_cmd_buffer.c | 91 ++
 5 files changed, 93 insertions(+), 177 deletions(-)

diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index ee62614..1455aa1 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -214,7 +214,7 @@
 
 
 
-
+
 
 
   
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 9c81c5a..bf6ce80 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -203,7 +203,7 @@
 
 
 
-
+
 
 
   
diff --git a/src/intel/vulkan/gen7_cmd_buffer.c 
b/src/intel/vulkan/gen7_cmd_buffer.c
index 225533c..c1b7724 100644
--- a/src/intel/vulkan/gen7_cmd_buffer.c
+++ b/src/intel/vulkan/gen7_cmd_buffer.c
@@ -121,94 +121,6 @@ void genX(CmdBindIndexBuffer)(
cmd_buffer->state.gen7.index_offset = offset;
 }
 
-static VkResult
-flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
-{
-   struct anv_device *device = cmd_buffer->device;
-   struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
-   struct anv_state surfaces = { 0, }, samplers = { 0, };
-   VkResult result;
-
-   result = anv_cmd_buffer_emit_samplers(cmd_buffer,
- MESA_SHADER_COMPUTE, );
-   if (result != VK_SUCCESS)
-  return result;
-   result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
-  MESA_SHADER_COMPUTE, );
-   if (result != VK_SUCCESS)
-  return result;
-
-   struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
-
-   const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
-   const struct brw_stage_prog_data *prog_data = _prog_data->base;
-
-   if (push_state.alloc_size) {
-  anv_batch_emit(_buffer->batch, GENX(MEDIA_CURBE_LOAD), curbe) {
- curbe.CURBETotalDataLength= push_state.alloc_size;
- curbe.CURBEDataStartAddress   = push_state.offset;
-  }
-   }
-
-   const uint32_t slm_size = encode_slm_size(GEN_GEN, prog_data->total_shared);
-
-   struct anv_state state =
-  anv_state_pool_emit(>dynamic_state_pool,
-  GENX(INTERFACE_DESCRIPTOR_DATA), 64,
-  .KernelStartPointer = pipeline->cs_simd,
-  .BindingTablePointer = surfaces.offset,
-  .SamplerStatePointer = samplers.offset,
-  .ConstantURBEntryReadLength =
- cs_prog_data->push.per_thread.regs,
-#if GEN_IS_HASWELL
-  .CrossThreadConstantDataReadLength =
- cs_prog_data->push.cross_thread.regs,
-#else
-  .ConstantURBEntryReadOffset = 0,
-#endif
-  .BarrierEnable = cs_prog_data->uses_barrier,
-  .SharedLocalMemorySize = slm_size,
-  .NumberofThreadsinGPGPUThreadGroup =
- cs_prog_data->threads);
-
-   const uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * 
sizeof(uint32_t);
-   anv_batch_emit(_buffer->batch,
-  GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), idl) {
-  idl.InterfaceDescriptorTotalLength= size;
-  idl.InterfaceDescriptorDataStartAddress = state.offset;
-   }
-
-   return VK_SUCCESS;
-}
-
-void
-genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
-{
-   struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
-   MAYBE_UNUSED VkResult result;
-
-   assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
-
-   genX(cmd_buffer_config_l3)(cmd_buffer, pipeline->urb.l3_config);
-
-   genX(flush_pipeline_select_gpgpu)(cmd_buffer);
-
-   if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
-  anv_batch_emit_batch(_buffer->batch, >batch);
-
-   if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
-   (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
-  /* FIXME: figure out descriptors for gen7 */
-  result =

Mesa (master): anv/cmd_buffer: Move descriptor flushing into genX_cmd_buffer.c

2016-10-17 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: 7998e37774c9589b456d9a951d47db98c16d6202
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7998e37774c9589b456d9a951d47db98c16d6202

Author: Jason Ekstrand 
Date:   Mon Oct 17 10:11:55 2016 -0700

anv/cmd_buffer: Move descriptor flushing into genX_cmd_buffer.c

It really should have gone here all along.  We were trying a bit too hard
to make it gen-agnostic just because it didn't have any #if's.

Signed-off-by: Jason Ekstrand 
Reviewed-by: Anuj Phogat 

---

 src/intel/vulkan/anv_cmd_buffer.c  | 314 
 src/intel/vulkan/anv_genX.h|   4 -
 src/intel/vulkan/anv_private.h |   6 -
 src/intel/vulkan/genX_cmd_buffer.c | 362 +
 4 files changed, 327 insertions(+), 359 deletions(-)

diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index 98257f8..26a2be6 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -609,20 +609,6 @@ void anv_CmdBindVertexBuffers(
}
 }
 
-static void
-add_surface_state_reloc(struct anv_cmd_buffer *cmd_buffer,
-struct anv_state state, struct anv_bo *bo, uint32_t 
offset)
-{
-   /* The address goes in SURFACE_STATE dword 1 for gens < 8 and dwords 8 and
-* 9 for gen8+.  We only write the first dword for gen8+ here and rely on
-* the initial state to set the high bits to 0. */
-
-   const uint32_t dword = cmd_buffer->device->info.gen < 8 ? 1 : 8;
-
-   anv_reloc_list_add(_buffer->surface_relocs, _buffer->pool->alloc,
-  state.offset + dword * 4, bo, offset);
-}
-
 enum isl_format
 anv_isl_format_for_descriptor_type(VkDescriptorType type)
 {
@@ -640,306 +626,6 @@ anv_isl_format_for_descriptor_type(VkDescriptorType type)
}
 }
 
-static struct anv_state
-anv_cmd_buffer_alloc_null_surface_state(struct anv_cmd_buffer *cmd_buffer,
-struct anv_framebuffer *fb)
-{
-   switch (cmd_buffer->device->info.gen) {
-   case 7:
-  if (cmd_buffer->device->info.is_haswell) {
- return gen75_cmd_buffer_alloc_null_surface_state(cmd_buffer, fb);
-  } else {
- return gen7_cmd_buffer_alloc_null_surface_state(cmd_buffer, fb);
-  }
-   case 8:
-  return gen8_cmd_buffer_alloc_null_surface_state(cmd_buffer, fb);
-   case 9:
-  return gen9_cmd_buffer_alloc_null_surface_state(cmd_buffer, fb);
-   default:
-  unreachable("Invalid hardware generation");
-   }
-}
-
-VkResult
-anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
-  gl_shader_stage stage,
-  struct anv_state *bt_state)
-{
-   struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
-   struct anv_subpass *subpass = cmd_buffer->state.subpass;
-   struct anv_pipeline *pipeline;
-   uint32_t bias, state_offset;
-
-   switch (stage) {
-   case  MESA_SHADER_COMPUTE:
-  pipeline = cmd_buffer->state.compute_pipeline;
-  bias = 1;
-  break;
-   default:
-  pipeline = cmd_buffer->state.pipeline;
-  bias = 0;
-  break;
-   }
-
-   if (!anv_pipeline_has_stage(pipeline, stage)) {
-  *bt_state = (struct anv_state) { 0, };
-  return VK_SUCCESS;
-   }
-
-   struct anv_pipeline_bind_map *map = >shaders[stage]->bind_map;
-   if (bias + map->surface_count == 0) {
-  *bt_state = (struct anv_state) { 0, };
-  return VK_SUCCESS;
-   }
-
-   *bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer,
-  bias + map->surface_count,
-  _offset);
-   uint32_t *bt_map = bt_state->map;
-
-   if (bt_state->map == NULL)
-  return VK_ERROR_OUT_OF_DEVICE_MEMORY;
-
-   if (stage == MESA_SHADER_COMPUTE &&
-   
get_cs_prog_data(cmd_buffer->state.compute_pipeline)->uses_num_work_groups) {
-  struct anv_bo *bo = cmd_buffer->state.num_workgroups_bo;
-  uint32_t bo_offset = cmd_buffer->state.num_workgroups_offset;
-
-  struct anv_state surface_state;
-  surface_state =
- anv_cmd_buffer_alloc_surface_state(cmd_buffer);
-
-  const enum isl_format format =
- anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER);
-  anv_fill_buffer_surface_state(cmd_buffer->device, surface_state,
-format, bo_offset, 12, 1);
-
-  bt_map[0] = surface_state.offset + state_offset;
-  add_surface_state_reloc(cmd_buffer, surface_state, bo, bo_offset);
-   }
-
-   if (map->surface_count == 0)
-  goto out;
-
-   if (map->image_count > 0) {
-  VkResult result =
- anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, images);
-  if (result != VK_SUCCESS)
- return result;
-
-  cmd_buffer->state.push_constants_dirty |= 1 << stage;
-   }
-
-   uint32_t image = 0;
-   for (uint32_t

Mesa (master): doc/features.txt: factor out radeonsi as GL45 complete

2016-10-17 Thread Edward O'Callaghan 
Module: Mesa
Branch: master
Commit: 1c05f92590d9ad9bb0635b93b3a917f8d571596c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c05f92590d9ad9bb0635b93b3a917f8d571596c

Author: Edward O'Callaghan 
Date:   Fri Oct 14 15:30:50 2016 +1100

doc/features.txt: factor out radeonsi as GL45 complete

V2. add i965/hsw+ to list
V3. rebased on master.
V4. 'DONE' -> 'DONE ()'.
V5. remove i965/hsw+ from list :/

Signed-off-by: Edward O'Callaghan 
Reviewed-by: Marek Olšák 

---

 docs/features.txt | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/docs/features.txt b/docs/features.txt
index 0d6c16a..a677bfb 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -206,19 +206,19 @@ GL 4.4, GLSL 4.40 -- all DONE: i965/gen8+, nvc0, radeonsi
   GL_ARB_texture_stencil8   DONE (i965/hsw+, nv50, 
r600, llvmpipe, softpipe, swr)
   GL_ARB_vertex_type_10f_11f_11f_revDONE (i965, nv50, 
r600, llvmpipe, softpipe, swr)
 
-GL 4.5, GLSL 4.50 -- all DONE: nvc0
+GL 4.5, GLSL 4.50 -- all DONE: nvc0, radeonsi
 
-  GL_ARB_ES3_1_compatibilityDONE (i965/hsw+, 
radeonsi)
-  GL_ARB_clip_control   DONE (i965, nv50, 
r600, radeonsi, llvmpipe, softpipe, swr)
-  GL_ARB_conditional_render_invertedDONE (i965, nv50, 
r600, radeonsi, llvmpipe, softpipe, swr)
-  GL_ARB_cull_distance  DONE (i965, nv50, 
radeonsi, llvmpipe, softpipe, swr)
-  GL_ARB_derivative_control DONE (i965, nv50, 
r600, radeonsi)
+  GL_ARB_ES3_1_compatibilityDONE (i965/hsw+)
+  GL_ARB_clip_control   DONE (i965, nv50, 
r600, llvmpipe, softpipe, swr)
+  GL_ARB_conditional_render_invertedDONE (i965, nv50, 
r600, llvmpipe, softpipe, swr)
+  GL_ARB_cull_distance  DONE (i965, nv50, 
llvmpipe, softpipe, swr)
+  GL_ARB_derivative_control DONE (i965, nv50, r600)
   GL_ARB_direct_state_accessDONE (all drivers)
   GL_ARB_get_texture_sub_image  DONE (all drivers)
-  GL_ARB_shader_texture_image_samples   DONE (i965, nv50, 
r600, radeonsi)
-  GL_ARB_texture_barrierDONE (i965, nv50, 
r600, radeonsi)
+  GL_ARB_shader_texture_image_samples   DONE (i965, nv50, r600)
+  GL_ARB_texture_barrierDONE (i965, nv50, r600)
   GL_KHR_context_flush_control  DONE (all - but needs 
GLX/EGL extension to be useful)
-  GL_KHR_robustness DONE (i965, radeonsi)
+  GL_KHR_robustness DONE (i965)
   GL_EXT_shader_integer_mix DONE (all drivers that 
support GLSL)
 
 These are the extensions cherry-picked to make GLES 3.1

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Mesa (master): glsl: Remove prototypes for nonexistent functions

2016-10-17 Thread Ian Romanick 
Module: Mesa
Branch: master
Commit: 5c025ea6fca5f4b6c4ac168205355b805365e09e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c025ea6fca5f4b6c4ac168205355b805365e09e

Author: Ian Romanick 
Date:   Fri Oct 14 10:38:04 2016 -0700

glsl: Remove prototypes for nonexistent functions

Signed-off-by: Ian Romanick 
Reviewed-by: Kenneth Graunke 
Reviewed-by: Eric Engestrom 

---

 src/compiler/glsl/ir.h | 9 -
 1 file changed, 9 deletions(-)

diff --git a/src/compiler/glsl/ir.h b/src/compiler/glsl/ir.h
index 83b810b..7e06d42 100644
--- a/src/compiler/glsl/ir.h
+++ b/src/compiler/glsl/ir.h
@@ -2357,9 +2357,6 @@ _mesa_glsl_initialize_derived_variables(struct gl_context 
*ctx,
 gl_shader *shader);
 
 extern void
-_mesa_glsl_initialize_functions(_mesa_glsl_parse_state *state);
-
-extern void
 _mesa_glsl_initialize_builtin_functions();
 
 extern ir_function_signature *
@@ -2376,9 +2373,6 @@ extern ir_function_signature *
 _mesa_get_main_function_signature(glsl_symbol_table *symbols);
 
 extern void
-_mesa_glsl_release_functions(void);
-
-extern void
 _mesa_glsl_release_builtin_functions(void);
 
 extern void
@@ -2390,9 +2384,6 @@ extern void
 import_prototypes(const exec_list *source, exec_list *dest,
  struct glsl_symbol_table *symbols, void *mem_ctx);
 
-extern bool
-ir_has_call(ir_instruction *ir);
-
 extern void
 do_set_program_inouts(exec_list *instructions, struct gl_program *prog,
   gl_shader_stage shader_stage);

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Mesa (master): glsl: Replace assert with unreachable

2016-10-17 Thread Ian Romanick 
Module: Mesa
Branch: master
Commit: fde48c1262161ea809fa63527dca55f781fda771
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fde48c1262161ea809fa63527dca55f781fda771

Author: Ian Romanick 
Date:   Fri Sep  2 13:15:24 2016 -0700

glsl: Replace assert with unreachable

Signed-off-by: Ian Romanick 
Reviewed-by: Kenneth Graunke 
Reviewed-by: Eric Engestrom 

---

 src/compiler/glsl/ir_print_visitor.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/compiler/glsl/ir_print_visitor.cpp 
b/src/compiler/glsl/ir_print_visitor.cpp
index efb728b..cdbe184 100644
--- a/src/compiler/glsl/ir_print_visitor.cpp
+++ b/src/compiler/glsl/ir_print_visitor.cpp
@@ -478,7 +478,8 @@ void ir_print_visitor::visit(ir_constant *ir)
 else
fprintf(f, "%f", ir->value.d[i]);
 break;
-default: assert(0);
+default:
+unreachable("Invalid constant type");
 }
   }
}

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Mesa (master): i965: Silence unused parameter warnings

2016-10-17 Thread Ian Romanick 
Module: Mesa
Branch: master
Commit: 89e1436e2d4ff0c15202708979eb36761cae4167
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=89e1436e2d4ff0c15202708979eb36761cae4167

Author: Ian Romanick 
Date:   Mon Oct 10 17:11:34 2016 -0700

i965: Silence unused parameter warnings

brw_link.cpp:76:44: warning: unused parameter ‘shader_type’ [-Wunused-parameter]
gl_shader_stage shader_type,
^
brw_nir.c: In function ‘brw_nir_lower_vs_inputs’:
brw_nir.c:194:55: warning: unused parameter ‘devinfo’ [-Wunused-parameter]
 const struct gen_device_info *devinfo,
   ^
brw_vec4_visitor.cpp:914:37: warning: unused parameter ‘sampler’ 
[-Wunused-parameter]
uint32_t sampler,
 ^
brw_vec4_visitor.cpp:1146:34: warning: unused parameter ‘stream_id’ 
[-Wunused-parameter]
 vec4_visitor::gs_emit_vertex(int stream_id)
  ^

Signed-off-by: Ian Romanick 
Reviewed-by: Kenneth Graunke 
Reviewed-by: Eric Engestrom 

---

 src/mesa/drivers/dri/i965/brw_link.cpp | 3 +--
 src/mesa/drivers/dri/i965/brw_nir.c| 1 -
 src/mesa/drivers/dri/i965/brw_nir.h| 1 -
 src/mesa/drivers/dri/i965/brw_vec4.cpp | 2 +-
 src/mesa/drivers/dri/i965/brw_vec4.h   | 2 +-
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 2 +-
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 3 +--
 7 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index 02151d6..5ea9773 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -73,7 +73,6 @@ brw_shader_precompile(struct gl_context *ctx,
 
 static void
 brw_lower_packing_builtins(struct brw_context *brw,
-   gl_shader_stage shader_type,
exec_list *ir)
 {
/* Gens < 7 don't have instructions to convert to or from half-precision,
@@ -105,7 +104,7 @@ process_glsl_ir(struct brw_context *brw,
/* lower_packing_builtins() inserts arithmetic instructions, so it
 * must precede lower_instructions().
 */
-   brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
+   brw_lower_packing_builtins(brw, shader->ir);
do_mat_op_to_vec(shader->ir);
 
unsigned instructions_to_lower = (DIV_TO_MUL_RCP |
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c 
b/src/mesa/drivers/dri/i965/brw_nir.c
index 744865b..a935f42 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -191,7 +191,6 @@ remap_patch_urb_offsets(nir_block *block, nir_builder *b,
 
 void
 brw_nir_lower_vs_inputs(nir_shader *nir,
-const struct gen_device_info *devinfo,
 bool is_scalar,
 bool use_legacy_snorm_formula,
 const uint8_t *vs_attrib_wa_flags)
diff --git a/src/mesa/drivers/dri/i965/brw_nir.h 
b/src/mesa/drivers/dri/i965/brw_nir.h
index 425d6ce..aef5c53 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.h
+++ b/src/mesa/drivers/dri/i965/brw_nir.h
@@ -99,7 +99,6 @@ nir_shader *brw_preprocess_nir(const struct brw_compiler 
*compiler,
 bool brw_nir_lower_intrinsics(nir_shader *nir,
   struct brw_stage_prog_data *prog_data);
 void brw_nir_lower_vs_inputs(nir_shader *nir,
- const struct gen_device_info *devinfo,
  bool is_scalar,
  bool use_legacy_snorm_formula,
  const uint8_t *vs_attrib_wa_flags);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 6aa9102..362f32b 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -2114,7 +2114,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void 
*log_data,
nir_shader *shader = nir_shader_clone(mem_ctx, src_shader);
shader = brw_nir_apply_sampler_key(shader, compiler->devinfo, >tex,
   is_scalar);
-   brw_nir_lower_vs_inputs(shader, compiler->devinfo, is_scalar,
+   brw_nir_lower_vs_inputs(shader, is_scalar,
use_legacy_snorm_formula, key->gl_attrib_wa_flags);
brw_nir_lower_vue_outputs(shader, is_scalar);
shader = brw_postprocess_nir(shader, compiler->devinfo, is_scalar);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 1505ba6..62c6007 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -262,7 +262,7 @@ public:
  src_reg offset_value,
  src_reg mcs,
  uint32_t surface,

Mesa (master): glsl: Remove unused function import_prototypes

2016-10-17 Thread Ian Romanick 
Module: Mesa
Branch: master
Commit: 7c0c3740f01179cc2929cb3343e098d35c927092
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c0c3740f01179cc2929cb3343e098d35c927092

Author: Ian Romanick 
Date:   Fri Oct 14 10:45:14 2016 -0700

glsl: Remove unused function import_prototypes

Once upon a time, this was used to extract prototypes from the shader
containing GLSL built-in functions.  This was removed by f5692f45 in
November 2010 for Mesa 7.10.

Signed-off-by: Ian Romanick 
Reviewed-by: Kenneth Graunke 
Reviewed-by: Eric Engestrom 

---

 src/compiler/Makefile.sources  |   1 -
 src/compiler/glsl/ir.h |   6 --
 src/compiler/glsl/ir_import_prototypes.cpp | 125 -
 3 files changed, 132 deletions(-)

diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index 712b33a..a30443d 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -46,7 +46,6 @@ LIBGLSL_FILES = \
glsl/ir_hierarchical_visitor.cpp \
glsl/ir_hierarchical_visitor.h \
glsl/ir_hv_accept.cpp \
-   glsl/ir_import_prototypes.cpp \
glsl/ir_optimization.h \
glsl/ir_print_visitor.cpp \
glsl/ir_print_visitor.h \
diff --git a/src/compiler/glsl/ir.h b/src/compiler/glsl/ir.h
index 7e06d42..3d28dd5 100644
--- a/src/compiler/glsl/ir.h
+++ b/src/compiler/glsl/ir.h
@@ -2378,12 +2378,6 @@ _mesa_glsl_release_builtin_functions(void);
 extern void
 reparent_ir(exec_list *list, void *mem_ctx);
 
-struct glsl_symbol_table;
-
-extern void
-import_prototypes(const exec_list *source, exec_list *dest,
- struct glsl_symbol_table *symbols, void *mem_ctx);
-
 extern void
 do_set_program_inouts(exec_list *instructions, struct gl_program *prog,
   gl_shader_stage shader_stage);
diff --git a/src/compiler/glsl/ir_import_prototypes.cpp 
b/src/compiler/glsl/ir_import_prototypes.cpp
deleted file mode 100644
index b0429fb..000
--- a/src/compiler/glsl/ir_import_prototypes.cpp
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Copyright © 2010 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-/**
- * \file ir_import_prototypes.cpp
- * Import function prototypes from one IR tree into another.
- *
- * \author Ian Romanick
- */
-#include "ir.h"
-#include "glsl_symbol_table.h"
-
-namespace {
-
-/**
- * Visitor used to import function prototypes
- *
- * Normally the \c clone method of either \c ir_function or
- * \c ir_function_signature could be used.  However, we don't want a complete
- * clone of the \c ir_function_signature.  We want everything \b except the
- * body of the function.
- */
-class import_prototype_visitor : public ir_hierarchical_visitor {
-public:
-   /**
-*/
-   import_prototype_visitor(exec_list *list, glsl_symbol_table *symbols,
-   void *mem_ctx)
-   {
-  this->mem_ctx = mem_ctx;
-  this->list = list;
-  this->symbols = symbols;
-  this->function = NULL;
-   }
-
-   virtual ir_visitor_status visit_enter(ir_function *ir)
-   {
-  assert(this->function == NULL);
-
-  this->function = this->symbols->get_function(ir->name);
-  if (!this->function) {
-this->function = new(this->mem_ctx) ir_function(ir->name);
-
-list->push_tail(this->function);
-
-/* Add the new function to the symbol table.
- */
-this->symbols->add_function(this->function);
-  }
-  return visit_continue;
-   }
-
-   virtual ir_visitor_status visit_leave(ir_function *ir)
-   {
-  (void) ir;
-  assert(this->function != NULL);
-
-  this->function = NULL;
-  return visit_continue;
-   }
-
-   ir_visitor_status visit_enter(ir_function_signature *ir)
-   {
-  assert(this->function != NULL);
-
-  ir_function_signature

Mesa (master): st/glsl_to_tgsi: fix atomic counter addressing

2016-10-17 Thread Nicolai Hähnle 
Module: Mesa
Branch: master
Commit: 1dd99a15a4e0ffeabe0d50cbb402045e8e34d875
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1dd99a15a4e0ffeabe0d50cbb402045e8e34d875

Author: Nicolai Hähnle 
Date:   Thu Oct 13 12:36:42 2016 +0200

st/glsl_to_tgsi: fix atomic counter addressing

When more than one atomic counter buffer is in use, UniformStorage[n].opaque
is set up to contain indices that are contiguous across all used buffers.

This appears to be used by i965 via NIR, but for TGSI we do not treat atomic
counter buffers as opaque, so using the data in the opaque array is incorrect.

Fixes GL45-CTS.compute_shader.resource-atomic-counter.

Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Marek Olšák 

---

 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 15 +--
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index a7ea19f..682c034 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -552,7 +552,8 @@ public:
   unsigned *array_size,
   unsigned *base,
   unsigned *index,
-  st_src_reg *reladdr);
+  st_src_reg *reladdr,
+  bool opaque);
   void calc_deref_offsets(ir_dereference *head,
   ir_dereference *tail,
   unsigned *array_elements,
@@ -3254,7 +3255,7 @@ 
glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call *ir)
st_src_reg offset;
unsigned array_size = 0, base = 0, index = 0;
 
-   get_deref_offsets(deref, _size, , , );
+   get_deref_offsets(deref, _size, , , , false);
 
if (offset.file != PROGRAM_UNDEFINED) {
   emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(offset),
@@ -3585,7 +3586,7 @@ glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call *ir)
st_src_reg image(PROGRAM_IMAGE, 0, GLSL_TYPE_UINT);
 
get_deref_offsets(img, _array_size, _base,
- (unsigned int *), );
+ (unsigned int *), , true);
if (reladdr.file != PROGRAM_UNDEFINED) {
   image.reladdr = ralloc(mem_ctx, st_src_reg);
   *image.reladdr = reladdr;
@@ -3967,7 +3968,8 @@ glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference 
*ir,
 unsigned *array_size,
 unsigned *base,
 unsigned *index,
-st_src_reg *reladdr)
+st_src_reg *reladdr,
+bool opaque)
 {
GLuint shader = _mesa_program_enum_to_shader_stage(this->prog->Target);
unsigned location = 0;
@@ -3992,7 +3994,8 @@ glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference 
*ir,
   *array_size = 1;
}
 
-   if (location != 0x) {
+   if (opaque) {
+  assert(location != 0x);
   *base += 
this->shader_program->UniformStorage[location].opaque[shader].index;
   *index += 
this->shader_program->UniformStorage[location].opaque[shader].index;
}
@@ -4246,7 +4249,7 @@ glsl_to_tgsi_visitor::visit(ir_texture *ir)
}
 
get_deref_offsets(ir->sampler, _array_size, _base,
- _index, );
+ _index, , true);
if (reladdr.file != PROGRAM_UNDEFINED)
   emit_arl(ir, sampler_reladdr, reladdr);
 

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Mesa (master): intel: aubinator: use different colors to signal batch start/end

2016-10-17 Thread Lionel Landwerlin 
Module: Mesa
Branch: master
Commit: 6b17e3a6da82df47056e1c6f8a79af2fab629b2c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b17e3a6da82df47056e1c6f8a79af2fab629b2c

Author: Lionel Landwerlin 
Date:   Mon Oct 17 09:11:04 2016 -0700

intel: aubinator: use different colors to signal batch start/end

This makes the stream of commands a bit easier to read.

v2 (Ken): Use bold text on green headers for easier readability;
  swap the green and blue headers so the majority stay blue.

Signed-off-by: Lionel Landwerlin 
Signed-off-by: Kenneth Graunke 
Reviewed-by: Lionel Landwerlin 

---

 src/intel/tools/aubinator.c | 15 ++-
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index d716a65..31c1f89 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -50,8 +50,9 @@
 #define AUB_MI_BATCH_BUFFER_END (0x0500 << 16)
 
 #define CSI "\e["
-#define HEADER CSI "37;44m"
-#define NORMAL CSI "0m"
+#define BLUE_HEADER  CSI "0;44m"
+#define GREEN_HEADER CSI "1;42m"
+#define NORMAL   CSI "0m"
 
 /* options */
 
@@ -727,9 +728,13 @@ parse_commands(struct gen_spec *spec, uint32_t *cmds, int 
size, int engine)
   const char *color, *reset_color = NORMAL;
   uint64_t offset;
 
-  if (option_full_decode)
- color = HEADER;
-  else
+  if (option_full_decode) {
+ if ((p[0] & 0x) == AUB_MI_BATCH_BUFFER_START ||
+ (p[0] & 0x) == AUB_MI_BATCH_BUFFER_END)
+color = GREEN_HEADER;
+ else
+color = BLUE_HEADER;
+  } else
  color = NORMAL;
 
   if (option_color == COLOR_NEVER) {

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Mesa (master): anv: replace , with ; in anv_batch_emit()

2016-10-17 Thread Lionel Landwerlin 
Module: Mesa
Branch: master
Commit: 696f5c1853df39359b9dbd733f4c2a1177481556
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=696f5c1853df39359b9dbd733f4c2a1177481556

Author: Lionel Landwerlin 
Date:   Wed Oct 12 23:28:03 2016 +0100

anv: replace , with ; in anv_batch_emit()

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Kenneth Graunke 

---

 src/intel/vulkan/genX_cmd_buffer.c| 20 ++--
 src/intel/vulkan/genX_pipeline_util.h |  4 ++--
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 236afa5..02f8405 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -80,8 +80,8 @@ genX(cmd_buffer_emit_state_base_address)(struct 
anv_cmd_buffer *cmd_buffer)
 
   sba.DynamicStateBaseAddress =
  (struct anv_address) { >dynamic_state_block_pool.bo, 0 };
-  sba.DynamicStateMemoryObjectControlState = GENX(MOCS),
-  sba.DynamicStateBaseAddressModifyEnable = true,
+  sba.DynamicStateMemoryObjectControlState = GENX(MOCS);
+  sba.DynamicStateBaseAddressModifyEnable = true;
 
   sba.IndirectObjectBaseAddress = (struct anv_address) { NULL, 0 };
   sba.IndirectObjectMemoryObjectControlState = GENX(MOCS);
@@ -1230,7 +1230,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer 
*cmd_buffer)
 .bo = image->bo,
 .offset = image->offset + image->depth_surface.offset,
  };
- db.DepthBufferObjectControlState = GENX(MOCS),
+ db.DepthBufferObjectControlState = GENX(MOCS);
 
  db.SurfacePitch = image->depth_surface.isl.row_pitch - 1;
  db.Height   = image->extent.height - 1;
@@ -1241,7 +1241,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer 
*cmd_buffer)
 
 #if GEN_GEN >= 8
  db.SurfaceQPitch =
-isl_surf_get_array_pitch_el_rows(>depth_surface.isl) >> 2,
+isl_surf_get_array_pitch_el_rows(>depth_surface.isl) >> 2;
 #endif
  db.RenderTargetViewExtent = 1 - 1;
   }
@@ -1304,14 +1304,14 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer 
*cmd_buffer)
if (has_stencil) {
   anv_batch_emit(_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER), sb) {
 #if GEN_GEN >= 8 || GEN_IS_HASWELL
- sb.StencilBufferEnable = true,
+ sb.StencilBufferEnable = true;
 #endif
- sb.StencilBufferObjectControlState = GENX(MOCS),
+ sb.StencilBufferObjectControlState = GENX(MOCS);
 
- sb.SurfacePitch = image->stencil_surface.isl.row_pitch - 1,
+ sb.SurfacePitch = image->stencil_surface.isl.row_pitch - 1;
 
 #if GEN_GEN >= 8
- sb.SurfaceQPitch = 
isl_surf_get_array_pitch_el_rows(>stencil_surface.isl) >> 2,
+ sb.SurfaceQPitch = 
isl_surf_get_array_pitch_el_rows(>stencil_surface.isl) >> 2;
 #endif
  sb.SurfaceBaseAddress = (struct anv_address) {
 .bo = image->bo,
@@ -1515,8 +1515,8 @@ void genX(CmdWriteTimestamp)(
default:
   /* Everything else is bottom-of-pipe */
   anv_batch_emit(_buffer->batch, GENX(PIPE_CONTROL), pc) {
- pc.DestinationAddressType  = DAT_PPGTT,
- pc.PostSyncOperation   = WriteTimestamp,
+ pc.DestinationAddressType  = DAT_PPGTT;
+ pc.PostSyncOperation   = WriteTimestamp;
  pc.Address = (struct anv_address) { >bo, offset };
   }
   break;
diff --git a/src/intel/vulkan/genX_pipeline_util.h 
b/src/intel/vulkan/genX_pipeline_util.h
index c2de523..129ae94 100644
--- a/src/intel/vulkan/genX_pipeline_util.h
+++ b/src/intel/vulkan/genX_pipeline_util.h
@@ -126,8 +126,8 @@ emit_vertex_input(struct anv_pipeline *pipeline,
* VERTEX_BUFFER_STATE which we emit later.
*/
   anv_batch_emit(>batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
- vfi.InstancingEnable = pipeline->instancing_enable[desc->binding],
- vfi.VertexElementIndex = slot,
+ vfi.InstancingEnable = pipeline->instancing_enable[desc->binding];
+ vfi.VertexElementIndex = slot;
  /* Vulkan so far doesn't have an instance divisor, so
   * this is always 1 (ignored if not instancing). */
  vfi.InstanceDataStepRate = 1;

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Mesa (master): radeonsi: fix indirect loads of 64 bit constants

2016-10-17 Thread Nicolai Hähnle 
Module: Mesa
Branch: master
Commit: 51f9b38ce80d904b9cd39cb204ff792cac74f9c0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=51f9b38ce80d904b9cd39cb204ff792cac74f9c0

Author: Nicolai Hähnle 
Date:   Thu Oct 13 11:19:50 2016 +0200

radeonsi: fix indirect loads of 64 bit constants

This fixes GL45-CTS.compute_shader.fp64-case3.

Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_shader.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index e6edd90..1ae111a 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1914,11 +1914,11 @@ static LLVMValueRef fetch_constant(
result = bitcast(bld_base, type, result);
else {
LLVMValueRef addr2, result2;
-   addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 
1];
+   addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr 
reg2");
addr2 = lp_build_mul_imm(_base->uint_bld, addr2, 16);
addr2 = lp_build_add(_base->uint_bld, addr2,
-lp_build_const_int32(base->gallivm, idx * 
4));
+lp_build_const_int32(base->gallivm, (idx + 
1) * 4));
 
result2 = buffer_load_const(ctx, bufp, addr2);
 

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Mesa (master): st/glsl_to_tgsi: fix a corner case of std140 layout in uniform buffers

2016-10-17 Thread Nicolai Hähnle 
Module: Mesa
Branch: master
Commit: 9d6f82320c8a7f0df10f0b7868d966be907e6b21
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d6f82320c8a7f0df10f0b7868d966be907e6b21

Author: Nicolai Hähnle 
Date:   Thu Oct 13 09:54:02 2016 +0200

st/glsl_to_tgsi: fix a corner case of std140 layout in uniform buffers

See the comment in the code for an explanation. This fixes
GL45-CTS.buffer_storage.map_persistent_draw.

Reviewed-by: Marek Olšák 

---

 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 29 -
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index fd2485d..a7ea19f 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -2110,8 +2110,35 @@ glsl_to_tgsi_visitor::visit_expression(ir_expression* 
ir, st_src_reg *op)
  cbuf.index = const_offset / 16;
   }
   else {
+ ir_expression *offset_expr = ir->operands[1]->as_expression();
+ st_src_reg offset = op[1];
+
+ /* The OpenGL spec is written in such a way that accesses with
+  * non-constant offset are almost always vec4-aligned. The only
+  * exception to this are members of structs in arrays of structs:
+  * each struct in an array of structs is at least vec4-aligned,
+  * but single-element and [ui]vec2 members of the struct may be at
+  * an offset that is not a multiple of 16 bytes.
+  *
+  * Here, we extract that offset, relying on previous passes to always
+  * generate offset expressions of the form (+ expr constant_offset).
+  *
+  * Note that the std430 layout, which allows more cases of alignment
+  * less than vec4 in arrays, is not supported for uniform blocks, so
+  * we do not have to deal with it here.
+  */
+ if (offset_expr && offset_expr->operation == ir_binop_add) {
+const_offset_ir = offset_expr->operands[1]->as_constant();
+if (const_offset_ir) {
+   const_offset = const_offset_ir->value.u[0];
+   cbuf.index = const_offset / 16;
+   offset_expr->operands[0]->accept(this);
+   offset = this->result;
+}
+ }
+
  /* Relative/variable index into constant buffer */
- emit_asm(ir, TGSI_OPCODE_USHR, st_dst_reg(index_reg), op[1],
+ emit_asm(ir, TGSI_OPCODE_USHR, st_dst_reg(index_reg), offset,
   st_src_reg_for_int(4));
  cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
  memcpy(cbuf.reladdr, _reg, sizeof(index_reg));

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Mesa (master): glsl: print non-zero bindings of variables

2016-10-17 Thread Nicolai Hähnle 
Module: Mesa
Branch: master
Commit: e0213f36bb9e2aebd84845d3c06fcc74cc749f0f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e0213f36bb9e2aebd84845d3c06fcc74cc749f0f

Author: Nicolai Hähnle 
Date:   Thu Oct 13 15:27:00 2016 +0200

glsl: print non-zero bindings of variables

Reviewed-by: Marek Olšák 

---

 src/compiler/glsl/ir_print_visitor.cpp | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/compiler/glsl/ir_print_visitor.cpp 
b/src/compiler/glsl/ir_print_visitor.cpp
index c238c16..efb728b 100644
--- a/src/compiler/glsl/ir_print_visitor.cpp
+++ b/src/compiler/glsl/ir_print_visitor.cpp
@@ -165,6 +165,10 @@ void ir_print_visitor::visit(ir_variable *ir)
 {
fprintf(f, "(declare ");
 
+   char binding[32] = {0};
+   if (ir->data.binding)
+  snprintf(binding, sizeof(binding), "binding=%i ", ir->data.binding);
+
char loc[32] = {0};
if (ir->data.location != -1)
   snprintf(loc, sizeof(loc), "location=%i ", ir->data.location);
@@ -187,8 +191,8 @@ void ir_print_visitor::visit(ir_variable *ir)
const char *const interp[] = { "", "smooth", "flat", "noperspective" };
STATIC_ASSERT(ARRAY_SIZE(interp) == INTERP_MODE_COUNT);
 
-   fprintf(f, "(%s%s%s%s%s%s%s%s%s%s) ",
-   loc, component, cent, samp, patc, inv, prec, mode[ir->data.mode],
+   fprintf(f, "(%s%s%s%s%s%s%s%s%s%s%s) ",
+   binding, loc, component, cent, samp, patc, inv, prec, 
mode[ir->data.mode],
stream[ir->data.stream],
interp[ir->data.interpolation]);
 

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Mesa (master): radeonsi: unify the constant load paths

2016-10-17 Thread Nicolai Hähnle 
Module: Mesa
Branch: master
Commit: 9160b4d9810163b907eaff4142f3b67b7d633720
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9160b4d9810163b907eaff4142f3b67b7d633720

Author: Nicolai Hähnle 
Date:   Thu Oct 13 11:26:23 2016 +0200

radeonsi: unify the constant load paths

Remove the split between direct and indirect.

Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_shader.c | 39 +---
 1 file changed, 11 insertions(+), 28 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 1ae111a..a361418 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1874,24 +1874,6 @@ static LLVMValueRef fetch_constant(
buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
idx = reg->Register.Index * 4 + swizzle;
 
-   if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
-   LLVMValueRef c0, c1, desc;
-
-   desc = load_const_buffer_desc(ctx, buf);
-   c0 = buffer_load_const(ctx, desc,
-  LLVMConstInt(ctx->i32, idx * 4, 0));
-
-   if (!tgsi_type_is_64bit(type))
-   return bitcast(bld_base, type, c0);
-   else {
-   c1 = buffer_load_const(ctx, desc,
-  LLVMConstInt(ctx->i32,
-   (idx + 1) * 4, 0));
-   return radeon_llvm_emit_fetch_64bit(bld_base, type,
-   c0, c1);
-   }
-   }
-
if (reg->Register.Dimension && reg->Dimension.Indirect) {
LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, 
SI_PARAM_CONST_BUFFERS);
LLVMValueRef index;
@@ -1902,11 +1884,15 @@ static LLVMValueRef fetch_constant(
} else
bufp = load_const_buffer_desc(ctx, buf);
 
-   addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
-   addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
-   addr = lp_build_mul_imm(_base->uint_bld, addr, 16);
-   addr = lp_build_add(_base->uint_bld, addr,
-   lp_build_const_int32(base->gallivm, idx * 4));
+   if (reg->Register.Indirect) {
+   addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
+   addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr 
reg");
+   addr = lp_build_mul_imm(_base->uint_bld, addr, 16);
+   addr = lp_build_add(_base->uint_bld, addr,
+   lp_build_const_int32(base->gallivm, idx * 
4));
+   } else {
+   addr = LLVMConstInt(ctx->i32, idx * 4, 0);
+   }
 
result = buffer_load_const(ctx, bufp, addr);
 
@@ -1914,12 +1900,9 @@ static LLVMValueRef fetch_constant(
result = bitcast(bld_base, type, result);
else {
LLVMValueRef addr2, result2;
-   addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
-   addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr 
reg2");
-   addr2 = lp_build_mul_imm(_base->uint_bld, addr2, 16);
-   addr2 = lp_build_add(_base->uint_bld, addr2,
-lp_build_const_int32(base->gallivm, (idx + 
1) * 4));
 
+   addr2 = lp_build_add(_base->uint_bld, addr,
+LLVMConstInt(ctx->i32, 4, 0));
result2 = buffer_load_const(ctx, bufp, addr2);
 
result = radeon_llvm_emit_fetch_64bit(bld_base, type,

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Mesa (master): st/glsl_to_tgsi: fix [ui]vec[34] conversion to double

2016-10-17 Thread Nicolai Hähnle 
Module: Mesa
Branch: master
Commit: c3ce0d22b4cf95992cf402a70beca3f2877bcf98
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c3ce0d22b4cf95992cf402a70beca3f2877bcf98

Author: Nicolai Hähnle 
Date:   Thu Oct 13 16:40:11 2016 +0200

st/glsl_to_tgsi: fix [ui]vec[34] conversion to double

The corresponding opcodes for integers need to be treated the same as F2D.

Fixes GL45-CTS.gpu_shader_fp64.conversions.

Reviewed-by: Marek Olšák 

---

 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 682c034..f49a873 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -869,8 +869,9 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned 
op,
 
 } else {
/* some opcodes are special case in what they use as sources
-  - F2D is a float src0, DLDEXP is integer src1 */
-   if (op == TGSI_OPCODE_F2D ||
+  - [FUI]2D/[UI]2I64 is a float/[u]int src0, DLDEXP is integer 
src1 */
+   if (op == TGSI_OPCODE_F2D || op == TGSI_OPCODE_U2D || op == 
TGSI_OPCODE_I2D ||
+   op == TGSI_OPCODE_I2I64 || op == TGSI_OPCODE_U2I64 ||
op == TGSI_OPCODE_DLDEXP ||
(op == TGSI_OPCODE_UCMP && dst_is_64bit[0])) {
   dinst->src[j].swizzle = MAKE_SWIZZLE4(swz, swz, swz, swz);

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Mesa (master): st/mesa: fix fragment shader output mapping

2016-10-17 Thread Nicolai Hähnle 
Module: Mesa
Branch: master
Commit: 57a15142037e3eea3581a6c690b8e8e93729b5b3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=57a15142037e3eea3581a6c690b8e8e93729b5b3

Author: Nicolai Hähnle 
Date:   Thu Oct 13 09:49:11 2016 +0200

st/mesa: fix fragment shader output mapping

Properly handle the case where there is a gap in the assigned output locations,
e.g. a fragment shader writes to color buffer 2 but not to color buffers 0 & 1.

Fixes 
GL45-CTS.gtf33.GL3Tests.explicit_attrib_location.explicit_attrib_location_pipeline.

Reviewed-by: Marek Olšák 

---

 src/mesa/state_tracker/st_program.c | 17 +
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/mesa/state_tracker/st_program.c 
b/src/mesa/state_tracker/st_program.c
index 91887dc..7cc36b4 100644
--- a/src/mesa/state_tracker/st_program.c
+++ b/src/mesa/state_tracker/st_program.c
@@ -782,7 +782,6 @@ st_translate_fragment_program(struct st_context *st,
 * Semantics and mapping for outputs
 */
{
-  uint numColors = 0;
   GLbitfield64 outputsWritten = stfp->Base.Base.OutputsWritten;
 
   /* if z is written, emit that first */
@@ -826,15 +825,25 @@ st_translate_fragment_program(struct st_context *st,
break;
 case FRAG_RESULT_COLOR:
write_all = GL_TRUE; /* fallthrough */
-default:
+default: {
+   int index;
assert(loc == FRAG_RESULT_COLOR ||
   (FRAG_RESULT_DATA0 <= loc && loc < FRAG_RESULT_MAX));
+
+   index = (loc == FRAG_RESULT_COLOR) ? 0 : (loc - 
FRAG_RESULT_DATA0);
+
+   if (attr >= FRAG_RESULT_MAX) {
+  /* Secondary color for dual source blending. */
+  assert(index == 0);
+  index++;
+   }
+
fs_output_semantic_name[fs_num_outputs] = TGSI_SEMANTIC_COLOR;
-   fs_output_semantic_index[fs_num_outputs] = numColors;
+   fs_output_semantic_index[fs_num_outputs] = index;
outputMapping[attr] = fs_num_outputs;
-   numColors++;
break;
 }
+}
 
 fs_num_outputs++;
  }

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Mesa (master): gbm: add a couple missing includes

2016-10-17 Thread Ben Widawsky 
Module: Mesa
Branch: master
Commit: e9864f93c619a9e4c7c5c1eb40268e9241341d7d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9864f93c619a9e4c7c5c1eb40268e9241341d7d

Author: Eric Engestrom 
Date:   Mon Oct 17 11:39:27 2016 +0100

gbm: add a couple missing includes

Needed for memset() and drmIoctl().

Signed-off-by: Eric Engestrom 
Reviewed-by: Edward O'Callaghan 

---

 src/gbm/backends/dri/gbm_driint.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gbm/backends/dri/gbm_driint.h 
b/src/gbm/backends/dri/gbm_driint.h
index 1644fac..26376ef 100644
--- a/src/gbm/backends/dri/gbm_driint.h
+++ b/src/gbm/backends/dri/gbm_driint.h
@@ -28,6 +28,8 @@
 #ifndef _GBM_DRI_INTERNAL_H_
 #define _GBM_DRI_INTERNAL_H_
 
+#include 
+#include 
 #include 
 #include "gbmint.h"
 #include "c11/threads.h"

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Mesa (master): glsl: fail compilation of compute shaders when unsupported

2016-10-17 Thread Iago Toral Quiroga 
Module: Mesa
Branch: master
Commit: 8785a8ff8948385a913e9bd75e8cdd1092bd750f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8785a8ff8948385a913e9bd75e8cdd1092bd750f

Author: Iago Toral Quiroga 
Date:   Fri Oct 14 14:21:18 2016 +0200

glsl: fail compilation of compute shaders when unsupported

Generally, we only check for the presence of compute shaders during
parsing when we find any language (like layout qualifiers) that are
specific to compute shaders, however, it is possible to define an
empty compute shader does not use any language specific to compute
shaders at all and we should fail the compilation anyway. dEQP checks
this.

This patch adds a check for compute shader availability after we have
parsed the source code. At this point we know the effective GLSL version
and also extensions enabled in the shader.

Fixes a subcase of the following dEQP tests:
dEQP-GLES31.functional.debug.negative_coverage.callbacks.shader.compile_compute_shader
dEQP-GLES31.functional.debug.negative_coverage.get_error.shader.compile_compute_shader
dEQP-GLES31.functional.debug.negative_coverage.log.shader.compile_compute_shader

The tests still fail because there is one more subcase that fails that needs
another fix.

Reviewed-by: Timothy Arceri 

---

 src/compiler/glsl/glsl_parser_extras.cpp | 13 +
 1 file changed, 13 insertions(+)

diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
b/src/compiler/glsl/glsl_parser_extras.cpp
index 6270e8e..b351180 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -1877,6 +1877,18 @@ add_builtin_defines(struct _mesa_glsl_parse_state *state,
}
 }
 
+/* Implements parsing checks that we can't do during parsing */
+static void
+do_late_parsing_checks(struct _mesa_glsl_parse_state *state)
+{
+   if (state->stage == MESA_SHADER_COMPUTE && !state->has_compute_shader()) {
+  YYLTYPE loc;
+  memset(, 0, sizeof(loc));
+  _mesa_glsl_error(, state, "Compute shaders require "
+   "GLSL 4.30 or GLSL ES 3.10");
+   }
+}
+
 void
 _mesa_glsl_compile_shader(struct gl_context *ctx, struct gl_shader *shader,
   bool dump_ast, bool dump_hir)
@@ -1896,6 +1908,7 @@ _mesa_glsl_compile_shader(struct gl_context *ctx, struct 
gl_shader *shader,
  _mesa_glsl_lexer_ctor(state, source);
  _mesa_glsl_parse(state);
  _mesa_glsl_lexer_dtor(state);
+ do_late_parsing_checks(state);
}
 
if (dump_ast) {

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Mesa (master): egl/android: fix error in droid_add_configs_for_visuals()

2016-10-17 Thread Emil Velikov 
Module: Mesa
Branch: master
Commit: 3d48353e299c1f6ab4dc331c70074fe69dbfcc6d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d48353e299c1f6ab4dc331c70074fe69dbfcc6d

Author: Tapani Pälli 
Date:   Mon Oct 17 09:04:56 2016 +0300

egl/android: fix error in droid_add_configs_for_visuals()

This was some kind of leftover in commit acd35c8 and format_count
array variable (declared in outer scope) should be used instead.

Signed-off-by: Tapani Pälli 
Fixes: acd35c8758dc73240903 ("egl/android: tweak 
droid_add_configs_for_visuals()")
Reviewed-by: Eric Engestrom 
Reviewed-by: Emil Velikov 

---

 src/egl/drivers/dri2/platform_android.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index 6a4122a..6a110e2 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -787,8 +787,6 @@ droid_add_configs_for_visuals(_EGLDriver *drv, _EGLDisplay 
*dpy)
  continue;
 
   for (j = 0; j < ARRAY_SIZE(visuals); j++) {
- int format_count = 0;
-
  config_attrs[1] = visuals[j].format;
  config_attrs[3] = visuals[j].format;
 

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Mesa (master): radeonsi: shorten "shader->selector" to "sel" in si_shader_create

2016-10-17 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: 74d145f4a8ec42c3bf03b95fa0bf0fc34eee47d2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=74d145f4a8ec42c3bf03b95fa0bf0fc34eee47d2

Author: Marek Olšák 
Date:   Tue Oct  4 21:46:00 2016 +0200

radeonsi: shorten "shader->selector" to "sel" in si_shader_create

Reviewed-by: Edward O'Callaghan 
Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_shader.c | 15 ---
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index b2d7699..e6edd90 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -7857,21 +7857,22 @@ int si_shader_create(struct si_screen *sscreen, 
LLVMTargetMachineRef tm,
 struct si_shader *shader,
 struct pipe_debug_callback *debug)
 {
-   struct si_shader *mainp = shader->selector->main_shader_part;
+   struct si_shader_selector *sel = shader->selector;
+   struct si_shader *mainp = sel->main_shader_part;
int r;
 
/* LS, ES, VS are compiled on demand if the main part hasn't been
 * compiled for that stage.
 */
if (!mainp ||
-   (shader->selector->type == PIPE_SHADER_VERTEX &&
+   (sel->type == PIPE_SHADER_VERTEX &&
 (shader->key.vs.as_es != mainp->key.vs.as_es ||
  shader->key.vs.as_ls != mainp->key.vs.as_ls)) ||
-   (shader->selector->type == PIPE_SHADER_TESS_EVAL &&
+   (sel->type == PIPE_SHADER_TESS_EVAL &&
 shader->key.tes.as_es != mainp->key.tes.as_es) ||
-   (shader->selector->type == PIPE_SHADER_TESS_CTRL &&
+   (sel->type == PIPE_SHADER_TESS_CTRL &&
 shader->key.tcs.epilog.inputs_to_copy) ||
-   shader->selector->type == PIPE_SHADER_COMPUTE) {
+   sel->type == PIPE_SHADER_COMPUTE) {
/* Monolithic shader (compiled as a whole, has many variants,
 * may take a long time to compile).
 */
@@ -7905,7 +7906,7 @@ int si_shader_create(struct si_screen *sscreen, 
LLVMTargetMachineRef tm,
shader->info.nr_param_exports = mainp->info.nr_param_exports;
 
/* Select prologs and/or epilogs. */
-   switch (shader->selector->type) {
+   switch (sel->type) {
case PIPE_SHADER_VERTEX:
if (!si_shader_select_vs_parts(sscreen, tm, shader, 
debug))
return -1;
@@ -7946,7 +7947,7 @@ int si_shader_create(struct si_screen *sscreen, 
LLVMTargetMachineRef tm,
}
 
si_fix_num_sgprs(shader);
-   si_shader_dump(sscreen, shader, debug, shader->selector->info.processor,
+   si_shader_dump(sscreen, shader, debug, sel->info.processor,
   stderr);
 
/* Upload. */

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Mesa (master): radeonsi: clear DB_RENDER_OVERRIDE

2016-10-17 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: 2e74e8ead99dec2563f0d298a135020ed34a7175
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e74e8ead99dec2563f0d298a135020ed34a7175

Author: Marek Olšák 
Date:   Thu Oct 13 00:20:43 2016 +0200

radeonsi: clear DB_RENDER_OVERRIDE

Vulkan doesn't set these fields even though it doesn't use HiS.
HiS is disabled by programming DB_SRESULTS_COMPARE_STATEn to 0.

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_state.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index b23749c..732f9e9 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3925,9 +3925,7 @@ static void si_init_config(struct si_context *sctx)
si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
-   si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
-  S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
-  S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
+   si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
 
si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);

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