Mesa (master): freedreno/ir3: fix linkage::var size

2016-12-27 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: ec01ef2db187bfb2af4ce264c2f3ed24bbf005b4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec01ef2db187bfb2af4ce264c2f3ed24bbf005b4

Author: Rob Clark 
Date:   Mon Dec 26 14:16:57 2016 -0500

freedreno/ir3: fix linkage::var size

It should actually be 32 for a4xx/a5xx.. we still only advertise 16 but
for a5xx the linkage map includes position/psize.

Signed-off-by: Rob Clark 

---

 src/gallium/drivers/freedreno/ir3/ir3_shader.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.h 
b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
index 7a0ff98..678a630 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
@@ -342,7 +342,7 @@ struct ir3_shader_linkage {
uint8_t regid;
uint8_t compmask;
uint8_t loc;
-   } var[16];
+   } var[32];
 };
 
 static inline void

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Mesa (master): freedreno/a5xx: fix emit for bo addresses

2016-12-27 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: 09202cde7e6a11b689676cafd25cc965014415f3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=09202cde7e6a11b689676cafd25cc965014415f3

Author: Rob Clark 
Date:   Wed Dec 21 22:47:42 2016 -0500

freedreno/a5xx: fix emit for bo addresses

Reloc for the buffer address is two dwords on 64b devices (a5xx+)

Signed-off-by: Rob Clark 

---

 src/gallium/drivers/freedreno/a5xx/fd5_emit.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c 
b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
index 1b93361..90d8168 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
@@ -95,16 +95,16 @@ static void
 fd5_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean 
write,
uint32_t regid, uint32_t num, struct pipe_resource **prscs, 
uint32_t *offsets)
 {
+   uint32_t anum = align(num, 2);
uint32_t i;
 
debug_assert((regid % 4) == 0);
-   debug_assert((num % 4) == 0);
 
-   OUT_PKT7(ring, CP_LOAD_STATE, 3 + num);
+   OUT_PKT7(ring, CP_LOAD_STATE, 3 + (2 * anum));
OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
-   CP_LOAD_STATE_0_NUM_UNIT(num/4));
+   CP_LOAD_STATE_0_NUM_UNIT(anum/2));
OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
OUT_RING(ring, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
@@ -118,8 +118,14 @@ fd5_emit_const_bo(struct fd_ringbuffer *ring, enum 
shader_t type, boolean write,
}
} else {
OUT_RING(ring, 0xbad0 | (i << 16));
+   OUT_RING(ring, 0xbad0 | (i << 16));
}
}
+
+   for (; i < anum; i++) {
+   OUT_RING(ring, 0x);
+   OUT_RING(ring, 0x);
+   }
 }
 
 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be

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Mesa (master): freedreno: update generated headers

2016-12-27 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: 928e9bd60247f1826816e6e452b08c51897bc2c6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=928e9bd60247f1826816e6e452b08c51897bc2c6

Author: Rob Clark 
Date:   Sat Dec 24 11:57:35 2016 -0500

freedreno: update generated headers

Pull in a5xx streamout related regs.  Also fixes a couple incorrect
register definitions.

Signed-off-by: Rob Clark 

---

 src/gallium/drivers/freedreno/a2xx/a2xx.xml.h |  6 +--
 src/gallium/drivers/freedreno/a3xx/a3xx.xml.h |  6 +--
 src/gallium/drivers/freedreno/a4xx/a4xx.xml.h | 13 +++--
 src/gallium/drivers/freedreno/a5xx/a5xx.xml.h | 63 ++-
 src/gallium/drivers/freedreno/a5xx/fd5_emit.c | 20 +++
 src/gallium/drivers/freedreno/adreno_common.xml.h |  6 +--
 src/gallium/drivers/freedreno/adreno_pm4.xml.h| 10 ++--
 7 files changed, 81 insertions(+), 43 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h 
b/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
index bc86afc..ca81ae8 100644
--- a/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
+++ b/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
@@ -12,10 +12,10 @@ The rules-ng-ng source files this header was generated from 
are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   
1572 bytes, from 2016-02-10 17:07:21)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml  (  
32907 bytes, from 2016-11-26 23:01:08)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  
12025 bytes, from 2016-11-26 23:01:08)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml(  
22914 bytes, from 2016-12-12 16:26:45)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml(  
23277 bytes, from 2016-12-24 05:01:47)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml  (  
83840 bytes, from 2016-11-26 23:01:08)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml  ( 
110765 bytes, from 2016-11-26 23:01:48)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml  (  
96819 bytes, from 2016-12-15 15:23:48)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml  ( 
110757 bytes, from 2016-12-26 17:51:07)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml  (  
99224 bytes, from 2016-12-26 18:40:41)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml (   
1773 bytes, from 2015-09-24 17:30:00)
 
 Copyright (C) 2013-2016 by the following authors:
diff --git a/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h 
b/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
index 947ede2..5e593f1 100644
--- a/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
+++ b/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
@@ -12,10 +12,10 @@ The rules-ng-ng source files this header was generated from 
are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   
1572 bytes, from 2016-02-10 17:07:21)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml  (  
32907 bytes, from 2016-11-26 23:01:08)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  
12025 bytes, from 2016-11-26 23:01:08)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml(  
22914 bytes, from 2016-12-12 16:26:45)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml(  
23277 bytes, from 2016-12-24 05:01:47)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml  (  
83840 bytes, from 2016-11-26 23:01:08)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml  ( 
110765 bytes, from 2016-11-26 23:01:48)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml  (  
96819 bytes, from 2016-12-15 15:23:48)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml  ( 
110757 bytes, from 2016-12-26 17:51:07)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml  (  
99224 bytes, from 2016-12-26 18:40:41)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml (   
1773 bytes, from 2015-09-24 17:30:00)
 
 Copyright (C) 2013-2016 by the following authors:
diff --git a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h 
b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
index 7418825..439bf81 100644
--- a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
+++ b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
@@ -12,10 +12,10 @@ The rules-ng-ng source files this header was generated from 
are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   
1572 bytes, from 2016-02-10 17:07:21)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml  (  
32907 bytes, from 2016-11-26 23:01:08)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  
12025 bytes, from 2016-11-26 23:01:08)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml

Mesa (master): freedreno/ir3: rework location of driver constants

2016-12-27 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: fc10dc9fdea6ad7d04dfcdb8fd2e2d59ea67f68b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc10dc9fdea6ad7d04dfcdb8fd2e2d59ea67f68b

Author: Rob Clark 
Date:   Wed Dec 21 22:43:52 2016 -0500

freedreno/ir3: rework location of driver constants

Rework how we lay out driver constants (driver-params, UBO/TFBO buffer
addresses, immediates) for more flexibility.  For a5xx+ we need to deal
with the fact that gpu ptrs are 64b instead of 32b, which makes the
fixed offset scheme not work so well.  While we are dealing with that
we might also make the layout more dynamic to account for varying # of
UBOs, etc.

Signed-off-by: Rob Clark 

---

 src/gallium/drivers/freedreno/a3xx/fd3_emit.c  |  9 ++--
 src/gallium/drivers/freedreno/a4xx/fd4_emit.c  |  9 ++--
 .../drivers/freedreno/ir3/ir3_compiler_nir.c   | 54 +++---
 src/gallium/drivers/freedreno/ir3/ir3_cp.c |  2 +-
 src/gallium/drivers/freedreno/ir3/ir3_shader.c | 16 +++
 src/gallium/drivers/freedreno/ir3/ir3_shader.h | 38 +++
 6 files changed, 75 insertions(+), 53 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c 
b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
index 95e6d26..6c3458a 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
@@ -96,16 +96,16 @@ static void
 fd3_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean 
write,
uint32_t regid, uint32_t num, struct pipe_resource **prscs, 
uint32_t *offsets)
 {
+   uint32_t anum = align(num, 4);
uint32_t i;
 
debug_assert((regid % 4) == 0);
-   debug_assert((num % 4) == 0);
 
-   OUT_PKT3(ring, CP_LOAD_STATE, 2 + num);
+   OUT_PKT3(ring, CP_LOAD_STATE, 2 + anum);
OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
-   CP_LOAD_STATE_0_NUM_UNIT(num/2));
+   CP_LOAD_STATE_0_NUM_UNIT(anum/2));
OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
 
@@ -120,6 +120,9 @@ fd3_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t 
type, boolean write,
OUT_RING(ring, 0xbad0 | (i << 16));
}
}
+
+   for (; i < anum; i++)
+   OUT_RING(ring, 0x);
 }
 
 #define VERT_TEX_OFF0
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c 
b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
index 9231823..2f3e0a6 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
@@ -96,16 +96,16 @@ static void
 fd4_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean 
write,
uint32_t regid, uint32_t num, struct pipe_resource **prscs, 
uint32_t *offsets)
 {
+   uint32_t anum = align(num, 4);
uint32_t i;
 
debug_assert((regid % 4) == 0);
-   debug_assert((num % 4) == 0);
 
-   OUT_PKT3(ring, CP_LOAD_STATE, 2 + num);
+   OUT_PKT3(ring, CP_LOAD_STATE, 2 + anum);
OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
-   CP_LOAD_STATE_0_NUM_UNIT(num/4));
+   CP_LOAD_STATE_0_NUM_UNIT(anum/4));
OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
 
@@ -120,6 +120,9 @@ fd4_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t 
type, boolean write,
OUT_RING(ring, 0xbad0 | (i << 16));
}
}
+
+   for (; i < anum; i++)
+   OUT_RING(ring, 0x);
 }
 
 static void
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c 
b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index ac6840c..e0fc2aa 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
@@ -119,6 +119,11 @@ struct ir3_compile {
bool error;
 };
 
+/* gpu pointer size in units of 32bit registers/slots */
+static unsigned pointer_size(struct ir3_compile *ctx)
+{
+   return (ctx->compiler->gpu_id >= 500) ? 2 : 1;
+}
 
 static struct ir3_instruction * create_immed(struct ir3_block *block, uint32_t 
val);
 static struct ir3_block * get_block(struct ir3_compile *ctx, nir_block 
*nblock);
@@ -181,31 +186,46 @@ compile_init(struct ir3_compiler *compiler,
nir_print_shader(ctx->s, stdout);
}
 
-   so->first_driver_param = so->first_immediate = 
align(ctx->s->num_uniforms, 4);
+   so->num_uniforms = ctx->s->num_uniforms;
+   so->num_ubos =

Mesa (master): freedreno/ir3: UBO support for 64b GPUs (a5xx)

2016-12-27 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: 6d77ceb701b889e76c93092b845986fc53e89257
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d77ceb701b889e76c93092b845986fc53e89257

Author: Rob Clark 
Date:   Fri Dec 23 19:19:01 2016 -0500

freedreno/ir3: UBO support for 64b GPUs (a5xx)

Update address calculation to support 64b addresses.

Signed-off-by: Rob Clark 

---

 .../drivers/freedreno/ir3/ir3_compiler_nir.c   | 27 +++---
 1 file changed, 24 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c 
b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index e0fc2aa..095e7f2 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
@@ -992,21 +992,28 @@ emit_intrinsic_load_ubo(struct ir3_compile *ctx, 
nir_intrinsic_instr *intr,
struct ir3_instruction **dst)
 {
struct ir3_block *b = ctx->block;
-   struct ir3_instruction *addr, *src0, *src1;
+   struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
nir_const_value *const_offset;
/* UBO addresses are the first driver params: */
unsigned ubo = regid(ctx->so->constbase.ubo, 0);
+   const unsigned ptrsz = pointer_size(ctx);
+
int off = 0;
 
/* First src is ubo index, which could either be an immed or not: */
src0 = get_src(ctx, >src[0])[0];
if (is_same_type_mov(src0) &&
(src0->regs[1]->flags & IR3_REG_IMMED)) {
-   addr = create_uniform(ctx, ubo + src0->regs[1]->iim_val);
+   base_lo = create_uniform(ctx, ubo + (src0->regs[1]->iim_val * 
ptrsz));
+   base_hi = create_uniform(ctx, ubo + (src0->regs[1]->iim_val * 
ptrsz) + 1);
} else {
-   addr = create_uniform_indirect(ctx, ubo, get_addr(ctx, src0));
+   base_lo = create_uniform_indirect(ctx, ubo, get_addr(ctx, 
src0));
+   base_hi = create_uniform_indirect(ctx, ubo + 1, get_addr(ctx, 
src0));
}
 
+   /* note: on 32bit gpu's base_hi is ignored and DCE'd */
+   addr = base_lo;
+
const_offset = nir_src_as_const_value(intr->src[1]);
if (const_offset) {
off += const_offset->u32[0];
@@ -1028,6 +1035,20 @@ emit_intrinsic_load_ubo(struct ir3_compile *ctx, 
nir_intrinsic_instr *intr,
off -= off2;
}
 
+   if (ptrsz == 2) {
+   struct ir3_instruction *carry;
+
+   /* handle 32b rollover, ie:
+*   if (addr < base_lo)
+*  base_hi++
+*/
+   carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
+   carry->cat2.condition = IR3_COND_LT;
+   base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
+
+   addr = create_collect(b, (struct ir3_instruction*[]){ addr, 
base_hi }, 2);
+   }
+
for (int i = 0; i < intr->num_components; i++) {
struct ir3_instruction *load =
ir3_LDG(b, addr, 0, create_immed(b, 1), 0);

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Mesa (master): freedreno/a5xx: transform-feedback support

2016-12-27 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: d10c5a24818b39585acfa60ceb6dbbae22b5be09
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d10c5a24818b39585acfa60ceb6dbbae22b5be09

Author: Rob Clark 
Date:   Sat Dec 24 14:44:26 2016 -0500

freedreno/a5xx: transform-feedback support

We'll need to revisit when adding hw binning pass support, whether we
can still do this in main draw step, as we do w/ a3xx/a4xx, or if we
needed to move it to the binning stage.

Still some failing piglits but most tests pass and the common cases seem
to work.

Signed-off-by: Rob Clark 

---

 src/gallium/drivers/freedreno/a5xx/fd5_draw.c  |  11 ++
 src/gallium/drivers/freedreno/a5xx/fd5_emit.c  |  56 ++-
 src/gallium/drivers/freedreno/a5xx/fd5_emit.h  |   2 +
 src/gallium/drivers/freedreno/a5xx/fd5_program.c   | 167 +
 src/gallium/drivers/freedreno/a5xx/fd5_program.h   |   3 +-
 .../drivers/freedreno/ir3/ir3_compiler_nir.c   |   6 +-
 src/gallium/drivers/freedreno/ir3/ir3_shader.c |   2 +
 7 files changed, 209 insertions(+), 38 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_draw.c 
b/src/gallium/drivers/freedreno/a5xx/fd5_draw.c
index e6b42bf..ffd3e3b 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_draw.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_draw.c
@@ -173,6 +173,17 @@ fd5_draw_vbo(struct fd_context *ctx, const struct 
pipe_draw_info *info)
 // emit.fp = NULL;
 // draw_impl(ctx, ctx->batch->binning, );
 
+   if (emit.streamout_mask) {
+   struct fd_ringbuffer *ring = ctx->batch->draw;
+
+   for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
+   if (emit.streamout_mask & (1 << i)) {
+   OUT_PKT7(ring, CP_EVENT_WRITE, 1);
+   OUT_RING(ring, FLUSH_SO_0 + i);
+   }
+   }
+   }
+
return true;
 }
 
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c 
b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
index 756ffb7..2404389 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
@@ -526,19 +526,63 @@ fd5_emit_state(struct fd_context *ctx, struct 
fd_ringbuffer *ring,
OUT_RING(ring, 
A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
}
 
-   if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
+   if (dirty & FD_DIRTY_PROG)
+   fd5_program_emit(ring, emit);
+
+   if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER)) {
struct pipe_framebuffer_state *pfb = >batch->framebuffer;
-   unsigned n = pfb->nr_cbufs;
-   /* if we have depth/stencil, we need at least on MRT: */
-   if (pfb->zsbuf)
-   n = MAX2(1, n);
-   fd5_program_emit(ring, emit, n, pfb->cbufs);
+   uint32_t posz_regid = ir3_find_output_regid(fp, 
FRAG_RESULT_DEPTH);
+   unsigned nr = pfb->nr_cbufs;
+
+   if (emit->key.binning_pass)
+   nr = 0;
+   else if (ctx->rasterizer->rasterizer_discard)
+   nr = 0;
+
+   OUT_PKT4(ring, REG_A5XX_RB_FS_OUTPUT_CNTL, 1);
+   OUT_RING(ring, A5XX_RB_FS_OUTPUT_CNTL_MRT(nr) |
+   COND(fp->writes_pos, 
A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z));
+
+   OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_CNTL, 1);
+   OUT_RING(ring, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr) |
+   A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid) |
+   
A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
}
 
if (emit->prog == >prog) { /* evil hack to deal sanely with clear 
path */
ir3_emit_consts(vp, ring, ctx, emit->info, dirty);
if (!emit->key.binning_pass)
ir3_emit_consts(fp, ring, ctx, emit->info, dirty);
+
+   struct pipe_stream_output_info *info = 
>shader->stream_output;
+   if (info->num_outputs) {
+   struct fd_streamout_stateobj *so = >streamout;
+
+   for (unsigned i = 0; i < so->num_targets; i++) {
+   struct pipe_stream_output_target *target = 
so->targets[i];
+
+   if (!target)
+   continue;
+
+   unsigned offset = (so->offsets[i] * 
info->stride[i] * 4) +
+   target->buffer_offset;
+
+   OUT_PKT4(ring, 
REG_A5XX_VPC_SO_BUFFER_BASE_LO(i), 3);
+   /* VPC_SO[i].BUFFER_BASE_LO: */
+   OUT_RELOCW(ring, 
fd_resource(target->buffer)->bo, 0, 0, 0);
+   OUT_RING(ring, target->buffer_size + offset);
+
+

Mesa (master): freedreno/ir3: treat clipvertex like a normal varying

2016-12-27 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: c416ea31cfe50e3d8ac3e433f9e4490a850b8e56
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c416ea31cfe50e3d8ac3e433f9e4490a850b8e56

Author: Rob Clark 
Date:   Sun Dec 25 13:16:51 2016 -0500

freedreno/ir3: treat clipvertex like a normal varying

We need this in case it is streamed out.  Not sure why we were treating
it specially before.  Having it as a VS out is harmless if FS doesn't
have a matching input.

Signed-off-by: Rob Clark 

---

 src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c 
b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index bfc04a7..b0f40f1 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
@@ -2151,10 +2151,8 @@ setup_output(struct ir3_compile *ctx, nir_variable *out)
case VARYING_SLOT_FOGC:
case VARYING_SLOT_CLIP_DIST0:
case VARYING_SLOT_CLIP_DIST1:
-   break;
case VARYING_SLOT_CLIP_VERTEX:
-   /* handled entirely in nir_lower_clip: */
-   return;
+   break;
default:
if (slot >= VARYING_SLOT_VAR0)
break;

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Mesa (master): freedreno/a5xx: texture layout

2016-12-27 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: f0439040808f81d5b9a4072de7469dacdda96fa7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0439040808f81d5b9a4072de7469dacdda96fa7

Author: Rob Clark 
Date:   Tue Dec  6 13:32:31 2016 -0500

freedreno/a5xx: texture layout

Seems to be imilar to a4xx, and sampler state "array-pitch" needs
to be aligned to page size.

Signed-off-by: Rob Clark 

---

 src/gallium/drivers/freedreno/a5xx/fd5_texture.c   | 2 +-
 src/gallium/drivers/freedreno/freedreno_resource.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_texture.c 
b/src/gallium/drivers/freedreno/a5xx/fd5_texture.c
index 588e914..47b07b8 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_texture.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_texture.c
@@ -281,7 +281,7 @@ fd5_sampler_view_create(struct pipe_context *pctx, struct 
pipe_resource *prsc,
case PIPE_TEXTURE_1D:
case PIPE_TEXTURE_2D:
so->texconst3 =
-   A5XX_TEX_CONST_3_ARRAY_PITCH(rsc->slices[lvl].size0);
+   A5XX_TEX_CONST_3_ARRAY_PITCH(rsc->layer_size);
so->texconst5 =
A5XX_TEX_CONST_5_DEPTH(1);
break;
diff --git a/src/gallium/drivers/freedreno/freedreno_resource.c 
b/src/gallium/drivers/freedreno/freedreno_resource.c
index 174c1d4..5a2bdfc 100644
--- a/src/gallium/drivers/freedreno/freedreno_resource.c
+++ b/src/gallium/drivers/freedreno/freedreno_resource.c
@@ -819,7 +819,7 @@ fd_resource_create(struct pipe_screen *pscreen,
assert(rsc->cpp);
 
alignment = slice_alignment(pscreen, tmpl);
-   if (is_a4xx(fd_screen(pscreen))) {
+   if (is_a4xx(fd_screen(pscreen)) || is_a5xx(fd_screen(pscreen))) {
switch (tmpl->target) {
case PIPE_TEXTURE_3D:
rsc->layer_first = false;

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Mesa (master): ttn: set ->info->num_ubos

2016-12-27 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: 859cb24d94f3b0b7f8f0e98642ff4b92b1f7f2f1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=859cb24d94f3b0b7f8f0e98642ff4b92b1f7f2f1

Author: Rob Clark 
Date:   Thu Dec 22 00:56:48 2016 -0500

ttn: set ->info->num_ubos

For dealing w/ 32b vs 64b gpu addresses, I need to rework how we pass
UBO buffer addresses to shader, and knowing up front the # of UBOs is
useful.  But I noticed ttn wasn't setting this.

Signed-off-by: Rob Clark 
Reviewed-by: Eric Anholt 

---

 src/gallium/auxiliary/nir/tgsi_to_nir.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c 
b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index f50a5a6..c7afe96 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -314,8 +314,11 @@ ttn_emit_declaration(struct ttn_compile *c)
  file == TGSI_FILE_CONSTANT);
 
   /* nothing to do for UBOs: */
-  if ((file == TGSI_FILE_CONSTANT) && decl->Declaration.Dimension)
+  if ((file == TGSI_FILE_CONSTANT) && decl->Declaration.Dimension) {
+ b->shader->info->num_ubos =
+MAX2(b->shader->info->num_ubos, decl->Dim.Index2D);
  return;
+  }
 
   if ((file == TGSI_FILE_INPUT) || (file == TGSI_FILE_OUTPUT)) {
  is_array = (is_array && decl->Declaration.Array &&

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Mesa (master): anv: Handle vkGetPhysicalDeviceQueueFamilyProperties with count == 0

2016-12-27 Thread Chad Versace 
Module: Mesa
Branch: master
Commit: d6545f234593fb00d02fdc07f9b2a803d2b569f6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6545f234593fb00d02fdc07f9b2a803d2b569f6

Author: Chad Versace 
Date:   Tue Dec 27 10:25:58 2016 -0800

anv: Handle vkGetPhysicalDeviceQueueFamilyProperties with count == 0

The spec implicitly allows the incoming count to be 0. From the Vulkan
1.0.38 spec, Section 4.1 Physical Devices:

If the value referenced by pQueueFamilyPropertyCount is not 0 [then
do stuff].

Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Anuj Phogat 
Reviewed-by: Jason Ekstrand 

---

 src/intel/vulkan/anv_device.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 037ef82..323cae4 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -646,7 +646,14 @@ void anv_GetPhysicalDeviceQueueFamilyProperties(
   return;
}
 
-   assert(*pCount >= 1);
+   /* The spec implicitly allows the incoming count to be 0. From the Vulkan
+* 1.0.38 spec, Section 4.1 Physical Devices:
+*
+* If the value referenced by pQueueFamilyPropertyCount is not 0 [then
+* do stuff].
+*/
+   if (*pCount == 0)
+  return;
 
*pQueueFamilyProperties = (VkQueueFamilyProperties) {
   .queueFlags = VK_QUEUE_GRAPHICS_BIT |

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Mesa (master): egl: Emit correct error when robust context creation fails

2016-12-27 Thread Chad Versace 
Module: Mesa
Branch: master
Commit: b85c0b569fe133b71a767a068e8608868158134e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b85c0b569fe133b71a767a068e8608868158134e

Author: Chad Versace 
Date:   Thu Dec 22 17:06:14 2016 -0800

egl: Emit correct error when robust context creation fails

Fixes dEQP-EGL.functional.create_context_ext.robust_*
on Intel with GBM.

If the user sets the EGL_CONTEXT_OPENGL_ROBUST_ACCESS_BIT_KHR in
EGL_CONTEXT_FLAGS_KHR when creating an OpenGL ES context, then
EGL_KHR_create_context spec requires that we unconditionally emit
EGL_BAD_ATTRIBUTE because that flag does not exist for OpenGL ES. When
creating an OpenGL context, the spec requires that we emit EGL_BAD_MATCH
if we can't support the request; that error is generated in the egl_dri2
layer where the driver capability is actually checked.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99188
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Tapani Pälli 

---

 src/egl/main/eglcontext.c | 38 ++
 1 file changed, 26 insertions(+), 12 deletions(-)

diff --git a/src/egl/main/eglcontext.c b/src/egl/main/eglcontext.c
index 60625f6..5313e1da 100644
--- a/src/egl/main/eglcontext.c
+++ b/src/egl/main/eglcontext.c
@@ -184,19 +184,33 @@ _eglParseContextAttribList(_EGLContext *ctx, _EGLDisplay 
*dpy,
 break;
  }
 
- /* The EGL_KHR_create_context_spec says:
-  *
-  * "If the EGL_CONTEXT_OPENGL_ROBUST_ACCESS_BIT_KHR bit is set in
-  * EGL_CONTEXT_FLAGS_KHR, then a context supporting  will be created. Robust buffer access is defined in the
-  * GL_ARB_robustness extension specification, and the resulting
-  * context must also support either the GL_ARB_robustness
-  * extension, or a version of OpenGL incorporating equivalent
-  * functionality. This bit is supported for OpenGL contexts.
-  */
  if ((val & EGL_CONTEXT_OPENGL_ROBUST_ACCESS_BIT_KHR) &&
- (api != EGL_OPENGL_API ||
-  !dpy->Extensions.EXT_create_context_robustness)) {
+ api != EGL_OPENGL_API) {
+/* The EGL_KHR_create_context spec says:
+ *
+ *   10) Which error should be generated if robust buffer access
+ *   or reset notifications are requested under OpenGL ES?
+ *
+ *   As per Issue 6, this extension does not support creating
+ *   robust contexts for OpenGL ES. This is only supported via
+ *   the EGL_EXT_create_context_robustness extension.
+ *
+ *   Attempting to use this extension to create robust OpenGL
+ *   ES context will generate an EGL_BAD_ATTRIBUTE error. This
+ *   specific error is generated because this extension does
+ *   not define the EGL_CONTEXT_OPENGL_ROBUST_ACCESS_BIT_KHR
+ *   and EGL_CONTEXT_OPENGL_RESET_NOTIFICATION_STRATEGY_KHR
+ *   bits for OpenGL ES contexts. Thus, use of these bits fall
+ *   under condition described by: "If an attribute is
+ *   specified that is not meaningful for the client API
+ *   type.." in the above specification.
+ *
+ * The spec requires that we emit the error even if the display
+ * supports EGL_EXT_create_context_robustness. To create a robust
+ * GLES context, the *attribute*
+ * EGL_CONTEXT_OPENGL_ROBUST_ACCESS_EXT must be used, not the
+ * *flag* EGL_CONTEXT_OPENGL_ROBUST_ACCESS_BIT_KHR.
+ */
 err = EGL_BAD_ATTRIBUTE;
 break;
  }

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Mesa (master): anv: return count of queue families written

2016-12-27 Thread Chad Versace 
Module: Mesa
Branch: master
Commit: 75252826e82ffa9c091ebe5bcf303c9d7569c3a3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=75252826e82ffa9c091ebe5bcf303c9d7569c3a3

Author: Damien Grassart 
Date:   Sun Dec 25 01:00:58 2016 +0100

anv: return count of queue families written

The Vulkan spec indicates that
vkGetPhysicalDeviceQueueFamilyProperties() should overwrite
pQueueFamilyPropertyCount with the number of structures actually
written to pQueueFamilyProperties.

Signed-off-by: Damien Grassart 
Reviewed-by: Chad Versace 
Cc: mesa-sta...@lists.freedesktop.org

---

 src/intel/vulkan/anv_device.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 9245e5c..037ef82 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -656,6 +656,8 @@ void anv_GetPhysicalDeviceQueueFamilyProperties(
   .timestampValidBits = 36, /* XXX: Real value here */
   .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
};
+
+   *pCount = 1;
 }
 
 void anv_GetPhysicalDeviceMemoryProperties(

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Mesa (master): mesa/texformat: Handle GL_RGBA + GL_UNSIGNED_SHORT_5_5_5_1

2016-12-27 Thread Chad Versace 
Module: Mesa
Branch: master
Commit: f3739810e337d0f03514b9b967594c8dc010dfa4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f3739810e337d0f03514b9b967594c8dc010dfa4

Author: Chad Versace 
Date:   Thu Dec 22 14:39:44 2016 -0800

mesa/texformat: Handle GL_RGBA + GL_UNSIGNED_SHORT_5_5_5_1

_mesa_choose_tex_format() already handles GL_RGBA + 
GL_UNSIGNED_SHORT_1_5_5_5_REV
by converting it to MESA_FORMAT_B5G5R5A1_UNORM. Teach it do the same for
the non-reversed type. Otherwise, the switch's fallthrough converts it
to an  format, which has incompatible precision in the alpha
channel.

Patch 2/2 to fix dEQP-EGL.functional.image.modify.tex_rgb5_a1_tex_subimage_rgba8
on Intel.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99185
Cc: Haixia Shi 
Reviewed-by: Tapani Pälli 
Cc: "13.0" 

---

 src/mesa/main/texformat.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/main/texformat.c b/src/mesa/main/texformat.c
index be2581b..baa3988 100644
--- a/src/mesa/main/texformat.c
+++ b/src/mesa/main/texformat.c
@@ -74,6 +74,8 @@ _mesa_choose_tex_format(struct gl_context *ctx, GLenum target,
  RETURN_IF_SUPPORTED(MESA_FORMAT_B4G4R4A4_UNORM);
   } else if (type == GL_UNSIGNED_SHORT_1_5_5_5_REV) {
  RETURN_IF_SUPPORTED(MESA_FORMAT_B5G5R5A1_UNORM);
+  } else if (type == GL_UNSIGNED_SHORT_5_5_5_1) {
+ RETURN_IF_SUPPORTED(MESA_FORMAT_B5G5R5A1_UNORM);
   } else if (type == GL_UNSIGNED_INT_2_10_10_10_REV) {
  RETURN_IF_SUPPORTED(MESA_FORMAT_B10G10R10A2_UNORM);
   }

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Mesa (master): i965: Allow import/export of ARGB1555 images

2016-12-27 Thread Chad Versace 
Module: Mesa
Branch: master
Commit: e2d69d5e2da0208b7e66c342fbe5323161df2e51
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2d69d5e2da0208b7e66c342fbe5323161df2e51

Author: Chad Versace 
Date:   Thu Dec 22 15:00:12 2016 -0800

i965: Allow import/export of ARGB1555 images

To my knowledge, this fixes no tests. I simply wrote the patch for
completeness as a follow-up to the previous two patches.

Reviewed-by: Tapani Pälli 

---

 src/mesa/drivers/dri/i965/intel_screen.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index e1c3c19..d0e3ac6 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -230,6 +230,9 @@ static struct intel_image_format intel_image_formats[] = {
{ __DRI_IMAGE_FOURCC_XBGR, __DRI_IMAGE_COMPONENTS_RGB, 1,
  { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR, 4 }, } },
 
+   { __DRI_IMAGE_FOURCC_ARGB1555, __DRI_IMAGE_COMPONENTS_RGBA, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555, 2 } } },
+
{ __DRI_IMAGE_FOURCC_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1,
  { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565, 2 } } },
 

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Mesa (master): dri: Add __DRI_IMAGE_FORMAT_ARGB1555

2016-12-27 Thread Chad Versace 
Module: Mesa
Branch: master
Commit: 9aa6ab074876dfa853863a74edad0b5b017fb8c7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9aa6ab074876dfa853863a74edad0b5b017fb8c7

Author: Chad Versace 
Date:   Thu Dec 22 14:44:47 2016 -0800

dri: Add __DRI_IMAGE_FORMAT_ARGB1555

This allows eglCreateImage() to accept textures of said format.

Patch 1/2 to fix
dEQP-EGL.functional.image.modify.tex_rgb5_a1_tex_subimage_rgba8
on Intel.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99185
Cc: Haixia Shi 
Reviewed-by: Tapani Pälli 
Cc: "13.0" 

---

 include/GL/internal/dri_interface.h| 2 ++
 src/mesa/drivers/dri/common/dri_util.c | 4 
 2 files changed, 6 insertions(+)

diff --git a/include/GL/internal/dri_interface.h 
b/include/GL/internal/dri_interface.h
index c6ea464..8922356 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -1163,6 +1163,7 @@ struct __DRIdri2ExtensionRec {
 #define __DRI_IMAGE_FORMAT_XRGB2101010  0x1009
 #define __DRI_IMAGE_FORMAT_ARGB2101010  0x100a
 #define __DRI_IMAGE_FORMAT_SARGB8   0x100b
+#define __DRI_IMAGE_FORMAT_ARGB1555 0x100c
 
 #define __DRI_IMAGE_USE_SHARE  0x0001
 #define __DRI_IMAGE_USE_SCANOUT0x0002
@@ -1190,6 +1191,7 @@ struct __DRIdri2ExtensionRec {
 
 #define __DRI_IMAGE_FOURCC_R8  0x20203852
 #define __DRI_IMAGE_FOURCC_GR880x38385247
+#define __DRI_IMAGE_FOURCC_ARGB15550x35315241
 #define __DRI_IMAGE_FOURCC_RGB565  0x36314752
 #define __DRI_IMAGE_FOURCC_ARGB0x34325241
 #define __DRI_IMAGE_FOURCC_XRGB0x34325258
diff --git a/src/mesa/drivers/dri/common/dri_util.c 
b/src/mesa/drivers/dri/common/dri_util.c
index 3b81799..209a42a 100644
--- a/src/mesa/drivers/dri/common/dri_util.c
+++ b/src/mesa/drivers/dri/common/dri_util.c
@@ -830,6 +830,8 @@ driGLFormatToImageFormat(mesa_format format)
switch (format) {
case MESA_FORMAT_B5G6R5_UNORM:
   return __DRI_IMAGE_FORMAT_RGB565;
+   case MESA_FORMAT_B5G5R5A1_UNORM:
+  return __DRI_IMAGE_FORMAT_ARGB1555;
case MESA_FORMAT_B8G8R8X8_UNORM:
   return __DRI_IMAGE_FORMAT_XRGB;
case MESA_FORMAT_B10G10R10A2_UNORM:
@@ -863,6 +865,8 @@ driImageFormatToGLFormat(uint32_t image_format)
switch (image_format) {
case __DRI_IMAGE_FORMAT_RGB565:
   return MESA_FORMAT_B5G6R5_UNORM;
+   case __DRI_IMAGE_FORMAT_ARGB1555:
+  return MESA_FORMAT_B5G5R5A1_UNORM;
case __DRI_IMAGE_FORMAT_XRGB:
   return MESA_FORMAT_B8G8R8X8_UNORM;
case __DRI_IMAGE_FORMAT_ARGB2101010:

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