Mesa (master): i965: Unbind deleted shaders from brw_context, fixing malloc heisenbug.

2017-01-27 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: 7c5629a26912af9164bda17b7af5370f6b4302e4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c5629a26912af9164bda17b7af5370f6b4302e4

Author: Kenneth Graunke 
Date:   Wed Jan 25 00:59:42 2017 -0800

i965: Unbind deleted shaders from brw_context, fixing malloc heisenbug.

Applications may delete a shader program, create a new one, and bind it
before the next draw.  With terrible luck, malloc may randomly return a
chunk of memory for the new gl_program that happened to be the exact
same pointer as our previously bound gl_program.  In this case, our
logic to detect new programs in brw_upload_pipeline_state() would break:

  if (brw->vertex_program != ctx->VertexProgram._Current) {
 brw->vertex_program = ctx->VertexProgram._Current;
 brw->ctx.NewDriverState |= BRW_NEW_VERTEX_PROGRAM;
  }

Because the pointer is the same, we'd think it was the same program.
But it could be wildly different - a different stage altogether,
different sets of resources, and so on.  This causes utter chaos.

As unlikely as this seems, I believe I hit this when running a subset
of the CTS in a loop, in a group of tests that churns through simple
programs, deleting and rebuilding them.  Presumably malloc uses a
bucketing cache of sorts, and so freeing up a gl_program and allocating
a new one fairly quickly causes it to reuse that memory.

The result was that brw->vertex_program->info.num_ssbos claimed the
program had SSBOs, while brw->vs.base.prog_data.binding_table claimed
that there were none.  This was crazy, because the binding table is
calculated from info.num_ssbos - the shader info appeared to change
between shader compile time and draw time.  Careful use of watchpoints
revealed that it was being clobbered by rzalloc's memset when building
an entirely different program...

Fortunately, our 0xd0d0d0d0 canary for unused binding table entries
caused us to crash out of bounds when trying to upload SSBOs, or we
may have never discovered this heisenbug.

Fixes crashes in GL45-CTS.compute_shader.sso-case2 when using a hacked
cts-runner that only runs GL45-CTS.compute_shader.s* in EGL config ID 5
at 64x64 in a loop with 100 iterations.

Cc: "17.0 13.0 12.0" 
Signed-off-by: Kenneth Graunke 
Reviewed-by: Timothy Arceri 
Reviewed-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_program.c | 43 +
 1 file changed, 43 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index e81f6b1..673dc50 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -177,6 +177,49 @@ static struct gl_program *brwNewProgram(struct gl_context 
*ctx, GLenum target,
 static void brwDeleteProgram( struct gl_context *ctx,
  struct gl_program *prog )
 {
+   struct brw_context *brw = brw_context(ctx);
+
+   /* Beware!  prog's refcount has reached zero, and it's about to be freed.
+*
+* In brw_upload_pipeline_state(), we compare brw->foo_program to
+* ctx->FooProgram._Current, and flag BRW_NEW_FOO_PROGRAM if the
+* pointer has changed.
+*
+* We cannot leave brw->foo_program as a dangling pointer to the dead
+* program.  malloc() may allocate the same memory for a new gl_program,
+* causing us to see matching pointers...but totally different programs.
+*
+* We cannot set brw->foo_program to NULL, either.  If we've deleted the
+* active program, Mesa may set ctx->FooProgram._Current to NULL.  That
+* would cause us to see matching pointers (NULL == NULL), and fail to
+* detect that a program has changed since our last draw.
+*
+* So, set it to a bogus gl_program pointer that will never match,
+* causing us to properly reevaluate the state on our next draw.
+*
+* Getting this wrong causes heisenbugs which are very hard to catch,
+* as you need a very specific allocation pattern to hit the problem.
+*/
+   static const struct gl_program deleted_program;
+
+   if (brw->vertex_program == prog)
+  brw->vertex_program = _program;
+
+   if (brw->tess_ctrl_program == prog)
+  brw->tess_ctrl_program = _program;
+
+   if (brw->tess_eval_program == prog)
+  brw->tess_eval_program = _program;
+
+   if (brw->geometry_program == prog)
+  brw->geometry_program = _program;
+
+   if (brw->fragment_program == prog)
+  brw->fragment_program = _program;
+
+   if (brw->compute_program == prog)
+  brw->compute_program = _program;
+
_mesa_delete_program( ctx, prog );
 }
 

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Mesa (master): radv/ac: Use base in push constant loads.

2017-01-27 Thread Bas Nieuwenhuizen 
Module: Mesa
Branch: master
Commit: 96c60b7f07e626d9ca0fc5789117f0c725ba1da2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=96c60b7f07e626d9ca0fc5789117f0c725ba1da2

Author: Bas Nieuwenhuizen 
Date:   Sat Jan 28 01:32:20 2017 +0100

radv/ac: Use base in push constant loads.

Apparently the source is not an address but an offset, so we actually
need to use the base.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Dave Airlie 
CC: 

---

 src/amd/common/ac_nir_to_llvm.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 26b87e8..72ae6eb 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1745,9 +1745,12 @@ static LLVMValueRef visit_vulkan_resource_index(struct 
nir_to_llvm_context *ctx,
 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
  nir_intrinsic_instr *instr)
 {
-   LLVMValueRef ptr;
+   LLVMValueRef ptr, addr;
+
+   addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
+   addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), 
"");
 
-   ptr = build_gep0(ctx, ctx->push_constants, get_src(ctx, instr->src[0]));
+   ptr = build_gep0(ctx, ctx->push_constants, addr);
ptr = cast_ptr(ctx, ptr, get_def_type(ctx, >dest.ssa));
 
return LLVMBuildLoad(ctx->builder, ptr, "");

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Mesa (master): radv: drop support for VK_AMD_NEGATIVE_VIEWPORT_HEIGHT

2017-01-27 Thread Dave Airlie 
Module: Mesa
Branch: master
Commit: e8047980d2814198988e9124036f702c4518df8b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8047980d2814198988e9124036f702c4518df8b

Author: Andres Rodriguez 
Date:   Fri Jan 27 00:09:58 2017 -0500

radv: drop support for VK_AMD_NEGATIVE_VIEWPORT_HEIGHT

This extension was not correctly supported, and it conflicts with the
VK_KHR_MAINTENANCE1 spec.

Reviewed-by: Fredrik Höglund 
Signed-off-by: Dave Airlie 

---

 src/amd/vulkan/radv_device.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 5ee18e7..1505498 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -116,10 +116,6 @@ static const VkExtensionProperties 
common_device_extensions[] = {
.specVersion = 1,
},
{
-   .extensionName = VK_AMD_NEGATIVE_VIEWPORT_HEIGHT_EXTENSION_NAME,
-   .specVersion = 1,
-   },
-   {
.extensionName = 
VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
.specVersion = 1,
},

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Mesa (master): radv: implement VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2

2017-01-27 Thread Dave Airlie 
Module: Mesa
Branch: master
Commit: e9b16c74faae8db418305d2a88514c6c62a477bb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9b16c74faae8db418305d2a88514c6c62a477bb

Author: Dave Airlie 
Date:   Fri Nov 11 02:27:21 2016 +

radv: implement VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2

Signed-off-by: Dave Airlie 

---

 src/amd/vulkan/radv_device.c  | 38 +-
 src/amd/vulkan/radv_formats.c | 36 
 2 files changed, 73 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index a4b1295..5ee18e7 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -119,6 +119,10 @@ static const VkExtensionProperties 
common_device_extensions[] = {
.extensionName = VK_AMD_NEGATIVE_VIEWPORT_HEIGHT_EXTENSION_NAME,
.specVersion = 1,
},
+   {
+   .extensionName = 
VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
+   .specVersion = 1,
+   },
 };
 
 static VkResult
@@ -467,6 +471,13 @@ void radv_GetPhysicalDeviceFeatures(
};
 }
 
+void radv_GetPhysicalDeviceFeatures2KHR(
+   VkPhysicalDevicephysicalDevice,
+   VkPhysicalDeviceFeatures2KHR   *pFeatures)
+{
+   return radv_GetPhysicalDeviceFeatures(physicalDevice, 
>features);
+}
+
 void radv_GetPhysicalDeviceProperties(
VkPhysicalDevicephysicalDevice,
VkPhysicalDeviceProperties* pProperties)
@@ -600,6 +611,13 @@ void radv_GetPhysicalDeviceProperties(
memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
 }
 
+void radv_GetPhysicalDeviceProperties2KHR(
+   VkPhysicalDevicephysicalDevice,
+   VkPhysicalDeviceProperties2KHR *pProperties)
+{
+   return radv_GetPhysicalDeviceProperties(physicalDevice, 
>properties);
+}
+
 void radv_GetPhysicalDeviceQueueFamilyProperties(
VkPhysicalDevicephysicalDevice,
uint32_t*   pCount,
@@ -650,9 +668,19 @@ void radv_GetPhysicalDeviceQueueFamilyProperties(
*pCount = idx;
 }
 
+void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
+   VkPhysicalDevicephysicalDevice,
+   uint32_t*   pCount,
+   VkQueueFamilyProperties2KHR*pQueueFamilyProperties)
+{
+   return radv_GetPhysicalDeviceQueueFamilyProperties(physicalDevice,
+  pCount,
+  
>queueFamilyProperties);
+}
+
 void radv_GetPhysicalDeviceMemoryProperties(
VkPhysicalDevicephysicalDevice,
-   VkPhysicalDeviceMemoryProperties*   pMemoryProperties)
+   VkPhysicalDeviceMemoryProperties   *pMemoryProperties)
 {
RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
 
@@ -699,6 +727,14 @@ void radv_GetPhysicalDeviceMemoryProperties(
};
 }
 
+void radv_GetPhysicalDeviceMemoryProperties2KHR(
+   VkPhysicalDevicephysicalDevice,
+   VkPhysicalDeviceMemoryProperties2KHR   *pMemoryProperties)
+{
+   return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
+ 
>memoryProperties);
+}
+
 static int
 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
int queue_family_index, int idx)
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index e276432..87c28f1 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -957,6 +957,18 @@ void radv_GetPhysicalDeviceFormatProperties(
   pFormatProperties);
 }
 
+void radv_GetPhysicalDeviceFormatProperties2KHR(
+   VkPhysicalDevicephysicalDevice,
+   VkFormatformat,
+   VkFormatProperties2KHR* pFormatProperties)
+{
+   RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
+
+   radv_physical_device_get_format_properties(physical_device,
+  format,
+  
>formatProperties);
+}
+
 VkResult radv_GetPhysicalDeviceImageFormatProperties(
VkPhysicalDevicephysicalDevice,
VkFormatformat,
@@ -1071,6 +1083,20 @@ unsupported:
return VK_ERROR_FORMAT_NOT_SUPPORTED;
 }
 
+VkResult radv_GetPhysicalDeviceImageFormatProperties2KHR(
+   VkPhysicalDevicephysicalDevice,
+   const

Mesa (master): radv: use proper maximum slice for layered view

2017-01-27 Thread Dave Airlie 
Module: Mesa
Branch: master
Commit: 989ec617031ac5642e7d0a8358a09c5c8ed93b53
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=989ec617031ac5642e7d0a8358a09c5c8ed93b53

Author: Dave Airlie 
Date:   Mon Jan  9 07:02:17 2017 +

radv: use proper maximum slice for layered view

this fixes deferred shadows with geom shaders enabled.

but I think this fix is fine by itself.

Reviewed-by: Bas Nieuwenhuizen 
Signed-off-by: Dave Airlie 

---

 src/amd/vulkan/radv_device.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 4aa6af2..a4b1295 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1608,8 +1608,9 @@ radv_initialise_color_surface(struct radv_device *device,
va += iview->image->dcc_offset;
cb->cb_dcc_base = va >> 8;
 
+   uint32_t max_slice = iview->type == VK_IMAGE_VIEW_TYPE_3D ? 
iview->extent.depth : iview->layer_count;
cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
-   S_028C6C_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
+   S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
 
cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
pitch_tile_max = level_info->nblk_x / 8 - 1;
@@ -1761,8 +1762,9 @@ radv_initialise_ds_surface(struct radv_device *device,
z_offs += iview->image->surface.level[level].offset;
s_offs += iview->image->surface.stencil_level[level].offset;
 
+   uint32_t max_slice = iview->type == VK_IMAGE_VIEW_TYPE_3D ? 
iview->extent.depth : iview->layer_count;
ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
-   S_028008_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
+   S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
 

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Mesa (master): i965/sync: Add brw_fence::type

2017-01-27 Thread Chad Versace 
Module: Mesa
Branch: master
Commit: 014d0e0f88a8c4201e16db9428758d7119cee021
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=014d0e0f88a8c4201e16db9428758d7119cee021

Author: Chad Versace 
Date:   Fri Jan 13 10:46:49 2017 -0800

i965/sync: Add brw_fence::type

This a refactor patch; no expected changed in behavior.

Add `enum brw_fence_type` and brw_fence::type. There is only one type
currently, BRW_FENCE_TYPE_BO_WAIT. This patch reduces a lot of noise in
the next, which adds new type BRW_FENCE_TYPE_SYNC_FD.

Reviewed-by: Rafael Antognolli 
Tested-by: Rafael Antognolli 
Acked-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_sync.c | 103 ---
 1 file changed, 71 insertions(+), 32 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_sync.c 
b/src/mesa/drivers/dri/i965/brw_sync.c
index 1df5610..f9127a4 100644
--- a/src/mesa/drivers/dri/i965/brw_sync.c
+++ b/src/mesa/drivers/dri/i965/brw_sync.c
@@ -45,6 +45,11 @@
 
 struct brw_fence {
struct brw_context *brw;
+
+   enum brw_fence_type {
+  BRW_FENCE_TYPE_BO_WAIT,
+   } type;
+
/** The fence waits for completion of this batch. */
drm_intel_bo *batch_bo;
 
@@ -58,18 +63,29 @@ struct brw_gl_sync {
 };
 
 static void
-brw_fence_init(struct brw_context *brw, struct brw_fence *fence)
+brw_fence_init(struct brw_context *brw, struct brw_fence *fence,
+   enum brw_fence_type type)
 {
fence->brw = brw;
-   fence->batch_bo = NULL;
+   fence->type = type;
mtx_init(>mutex, mtx_plain);
+
+   switch (type) {
+   case BRW_FENCE_TYPE_BO_WAIT:
+  fence->batch_bo = NULL;
+  break;
+   }
 }
 
 static void
 brw_fence_finish(struct brw_fence *fence)
 {
-   if (fence->batch_bo)
-  drm_intel_bo_unreference(fence->batch_bo);
+   switch (fence->type) {
+   case BRW_FENCE_TYPE_BO_WAIT:
+  if (fence->batch_bo)
+ drm_intel_bo_unreference(fence->batch_bo);
+  break;
+   }
 
mtx_destroy(>mutex);
 }
@@ -77,13 +93,18 @@ brw_fence_finish(struct brw_fence *fence)
 static void
 brw_fence_insert(struct brw_context *brw, struct brw_fence *fence)
 {
-   assert(!fence->batch_bo);
-   assert(!fence->signalled);
-
brw_emit_mi_flush(brw);
-   fence->batch_bo = brw->batch.bo;
-   drm_intel_bo_reference(fence->batch_bo);
-   intel_batchbuffer_flush(brw);
+
+   switch (fence->type) {
+   case BRW_FENCE_TYPE_BO_WAIT:
+  assert(!fence->batch_bo);
+  assert(!fence->signalled);
+
+  fence->batch_bo = brw->batch.bo;
+  drm_intel_bo_reference(fence->batch_bo);
+  intel_batchbuffer_flush(brw);
+  break;
+   }
 }
 
 static bool
@@ -92,10 +113,18 @@ brw_fence_has_completed_locked(struct brw_fence *fence)
if (fence->signalled)
   return true;
 
-   if (fence->batch_bo && !drm_intel_bo_busy(fence->batch_bo)) {
+   switch (fence->type) {
+   case BRW_FENCE_TYPE_BO_WAIT:
+  if (!fence->batch_bo)
+ return false;
+
+  if (drm_intel_bo_busy(fence->batch_bo))
+ return false;
+
   drm_intel_bo_unreference(fence->batch_bo);
   fence->batch_bo = NULL;
   fence->signalled = true;
+
   return true;
}
 
@@ -121,24 +150,30 @@ brw_fence_client_wait_locked(struct brw_context *brw, 
struct brw_fence *fence,
if (fence->signalled)
   return true;
 
-   assert(fence->batch_bo);
+   switch (fence->type) {
+   case BRW_FENCE_TYPE_BO_WAIT:
+  assert(fence->batch_bo);
 
-   /* DRM_IOCTL_I915_GEM_WAIT uses a signed 64 bit timeout and returns
-* immediately for timeouts <= 0.  The best we can do is to clamp the
-* timeout to INT64_MAX.  This limits the maximum timeout from 584 years to
-* 292 years - likely not a big deal.
-*/
-   if (timeout > INT64_MAX)
-  timeout = INT64_MAX;
+  /* DRM_IOCTL_I915_GEM_WAIT uses a signed 64 bit timeout and returns
+   * immediately for timeouts <= 0.  The best we can do is to clamp the
+   * timeout to INT64_MAX.  This limits the maximum timeout from 584 years 
to
+   * 292 years - likely not a big deal.
+   */
+  if (timeout > INT64_MAX)
+ timeout = INT64_MAX;
 
-   if (drm_intel_gem_bo_wait(fence->batch_bo, timeout) != 0)
-  return false;
+  if (drm_intel_gem_bo_wait(fence->batch_bo, timeout) != 0)
+ return false;
+
+  fence->signalled = true;
+  drm_intel_bo_unreference(fence->batch_bo);
+  fence->batch_bo = NULL;
 
-   fence->signalled = true;
-   drm_intel_bo_unreference(fence->batch_bo);
-   fence->batch_bo = NULL;
+  return true;
+   }
 
-   return true;
+   assert(!"bad enum brw_fence_type");
+   return false;
 }
 
 /**
@@ -161,11 +196,15 @@ brw_fence_client_wait(struct brw_context *brw, struct 
brw_fence *fence,
 static void
 brw_fence_server_wait(struct brw_context *brw, struct brw_fence *fence)
 {
-   /* We have nothing to do for WaitSync.  Our GL command stream is sequential,
-* so given that

Mesa (master): i965/sync: Implement fences based on Linux sync_file

2017-01-27 Thread Chad Versace 
Module: Mesa
Branch: master
Commit: 6403e3765114b4f540ed1f5a714fbf1ff4d1bedc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6403e3765114b4f540ed1f5a714fbf1ff4d1bedc

Author: Chad Versace 
Date:   Fri Jan 13 10:46:49 2017 -0800

i965/sync: Implement fences based on Linux sync_file

This patch implements a new type of struct brw_fence, one that is based
struct sync_file.

This completes support for EGL_ANDROID_native_fence_sync.

* Background

  Linux 4.7 added a new file type, struct sync_file. See

commit 460bfc41fd52959311ed0328163f785e023857af
Author:  Gustavo Padovan 
Date:Thu Apr 28 10:46:57 2016 -0300
Subject: dma-buf/sync_file: de-stage sync_file headers

  A sync file is a cross-driver explicit synchronization primitive. In a
  sense, sync_file's relation to synchronization is similar to dma_buf's
  relation to memory: both are primitives that can be imported and
  exported across drivers (at least in theory).

Reviewed-by: Rafael Antognolli 
Tested-by: Rafael Antognolli 
Acked-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_sync.c | 162 ++-
 1 file changed, 159 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_sync.c 
b/src/mesa/drivers/dri/i965/brw_sync.c
index 77d382c..1c5d5a5 100644
--- a/src/mesa/drivers/dri/i965/brw_sync.c
+++ b/src/mesa/drivers/dri/i965/brw_sync.c
@@ -38,6 +38,8 @@
  * performance bottleneck, though.
  */
 
+#include  /* Requires Android or libdrm-2.4.72 */
+
 #include "main/imports.h"
 
 #include "brw_context.h"
@@ -47,11 +49,19 @@ struct brw_fence {
struct brw_context *brw;
 
enum brw_fence_type {
+  /** The fence waits for completion of brw_fence::batch_bo. */
   BRW_FENCE_TYPE_BO_WAIT,
+
+  /** The fence waits for brw_fence::sync_fd to signal. */
+  BRW_FENCE_TYPE_SYNC_FD,
} type;
 
-   /** The fence waits for completion of this batch. */
-   drm_intel_bo *batch_bo;
+   union {
+  drm_intel_bo *batch_bo;
+
+  /* This struct owns the fd. */
+  int sync_fd;
+   };
 
mtx_t mutex;
bool signalled;
@@ -74,6 +84,9 @@ brw_fence_init(struct brw_context *brw, struct brw_fence 
*fence,
case BRW_FENCE_TYPE_BO_WAIT:
   fence->batch_bo = NULL;
   break;
+case BRW_FENCE_TYPE_SYNC_FD:
+  fence->sync_fd = -1;
+  break;
}
 }
 
@@ -85,6 +98,10 @@ brw_fence_finish(struct brw_fence *fence)
   if (fence->batch_bo)
  drm_intel_bo_unreference(fence->batch_bo);
   break;
+   case BRW_FENCE_TYPE_SYNC_FD:
+  if (fence->sync_fd != -1)
+ close(fence->sync_fd);
+  break;
}
 
mtx_destroy(>mutex);
@@ -109,11 +126,46 @@ brw_fence_insert_locked(struct brw_context *brw, struct 
brw_fence *fence)
  return false;
   }
   break;
+   case BRW_FENCE_TYPE_SYNC_FD:
+  assert(!fence->signalled);
+
+  if (fence->sync_fd == -1) {
+ /* Create an out-fence that signals after all pending commands
+  * complete.
+  */
+ if (intel_batchbuffer_flush_fence(brw, -1, >sync_fd) < 0)
+return false;
+ assert(fence->sync_fd != -1);
+  } else {
+ /* Wait on the in-fence before executing any subsequently submitted
+  * commands.
+  */
+ if (intel_batchbuffer_flush(brw) < 0)
+return false;
+
+ /* Emit a dummy batch just for the fence. */
+ brw_emit_mi_flush(brw);
+ if (intel_batchbuffer_flush_fence(brw, fence->sync_fd, NULL) < 0)
+return false;
+  }
+  break;
}
 
return true;
 }
 
+static bool MUST_CHECK
+brw_fence_insert(struct brw_context *brw, struct brw_fence *fence)
+{
+   bool ret;
+
+   mtx_lock(>mutex);
+   ret = brw_fence_insert_locked(brw, fence);
+   mtx_unlock(>mutex);
+
+   return ret;
+}
+
 static bool
 brw_fence_has_completed_locked(struct brw_fence *fence)
 {
@@ -135,6 +187,16 @@ brw_fence_has_completed_locked(struct brw_fence *fence)
   fence->signalled = true;
 
   return true;
+
+   case BRW_FENCE_TYPE_SYNC_FD:
+  assert(fence->sync_fd != -1);
+
+  if (sync_wait(fence->sync_fd, 0) == -1)
+ return false;
+
+  fence->signalled = true;
+
+  return true;
}
 
return false;
@@ -156,6 +218,8 @@ static bool
 brw_fence_client_wait_locked(struct brw_context *brw, struct brw_fence *fence,
  uint64_t timeout)
 {
+   int32_t timeout_i32;
+
if (fence->signalled)
   return true;
 
@@ -182,6 +246,20 @@ brw_fence_client_wait_locked(struct brw_context *brw, 
struct brw_fence *fence,
   fence->batch_bo = NULL;
 
   return true;
+   case BRW_FENCE_TYPE_SYNC_FD:
+  if (fence->sync_fd == -1)
+ return false;
+
+  if (timeout > INT32_MAX)
+ timeout_i32 = -1;
+  else
+ timeout_i32 = timeout;
+
+

Mesa (master): i965/sync: Rename brw_fence_insert()

2017-01-27 Thread Chad Versace 
Module: Mesa
Branch: master
Commit: 0b6dd31d681060db6920ac9b8f1bcf6970d2a45e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b6dd31d681060db6920ac9b8f1bcf6970d2a45e

Author: Chad Versace 
Date:   Fri Jan 13 10:46:49 2017 -0800

i965/sync: Rename brw_fence_insert()

Rename to brw_fence_insert_locked(). This is correct because the fence's
mutex is effectively locked, as all callers are also *creators* of the
fence, and have not yet returned the new fence.

This reduces noise in the next patch, which defines and uses
brw_fence_insert(), an unlocked variant.

Reviewed-by: Rafael Antognolli 
Tested-by: Rafael Antognolli 
Acked-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_sync.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_sync.c 
b/src/mesa/drivers/dri/i965/brw_sync.c
index 24c8cbd..77d382c 100644
--- a/src/mesa/drivers/dri/i965/brw_sync.c
+++ b/src/mesa/drivers/dri/i965/brw_sync.c
@@ -91,7 +91,7 @@ brw_fence_finish(struct brw_fence *fence)
 }
 
 static bool MUST_CHECK
-brw_fence_insert(struct brw_context *brw, struct brw_fence *fence)
+brw_fence_insert_locked(struct brw_context *brw, struct brw_fence *fence)
 {
brw_emit_mi_flush(brw);
 
@@ -249,7 +249,7 @@ brw_gl_fence_sync(struct gl_context *ctx, struct 
gl_sync_object *_sync,
 
brw_fence_init(brw, >fence, BRW_FENCE_TYPE_BO_WAIT);
 
-   if (!brw_fence_insert(brw, >fence)) {
+   if (!brw_fence_insert_locked(brw, >fence)) {
   /* FIXME: There exists no way to report a GL error here. If an error
* occurs, continue silently and hope for the best.
*/
@@ -309,7 +309,7 @@ brw_dri_create_fence(__DRIcontext *ctx)
 
brw_fence_init(brw, fence, BRW_FENCE_TYPE_BO_WAIT);
 
-   if (!brw_fence_insert(brw, fence)) {
+   if (!brw_fence_insert_locked(brw, fence)) {
   brw_fence_finish(fence);
   free(fence);
   return NULL;

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Mesa (master): configure: Require libdrm >= 2.4.75

2017-01-27 Thread Chad Versace 
Module: Mesa
Branch: master
Commit: b8acb6b1798151d1038acec035835243706a4a6a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b8acb6b1798151d1038acec035835243706a4a6a

Author: Chad Versace 
Date:   Fri Jan 13 10:46:49 2017 -0800

configure: Require libdrm >= 2.4.75

Required to implement EGL_ANDROID_native_fence_sync on i965.
Specifically, i965 needs drm_intel_gem_bo_exec_fence(),
I915_PARAM_HAS_EXEC_FENCE, and libsync.h.

Reviewed-by: Rafael Antognolli 
Tested-by: Rafael Antognolli 
Acked-by: Kenneth Graunke 

---

 configure.ac | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configure.ac b/configure.ac
index 72be7dd..92339b4 100644
--- a/configure.ac
+++ b/configure.ac
@@ -67,7 +67,7 @@ OPENCL_VERSION=1
 AC_SUBST([OPENCL_VERSION])
 
 dnl Versions for external dependencies
-LIBDRM_REQUIRED=2.4.66
+LIBDRM_REQUIRED=2.4.75
 LIBDRM_RADEON_REQUIRED=2.4.56
 LIBDRM_AMDGPU_REQUIRED=2.4.63
 LIBDRM_INTEL_REQUIRED=2.4.61

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Mesa (master): i965: Add intel_screen::has_fence_fd

2017-01-27 Thread Chad Versace 
Module: Mesa
Branch: master
Commit: 358661c794573b9a361309d477fe09880773ef73
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=358661c794573b9a361309d477fe09880773ef73

Author: Chad Versace 
Date:   Fri Jan 13 10:46:48 2017 -0800

i965: Add intel_screen::has_fence_fd

This bool maps to I915_PARAM_HAS_EXEC_FENCE_FD.

Reviewed-by: Rafael Antognolli 
Tested-by: Rafael Antognolli 
Acked-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/intel_screen.c | 3 +++
 src/mesa/drivers/dri/i965/intel_screen.h | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 5f8..469d16c 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1817,6 +1817,9 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
 intel_get_boolean(screen, I915_PARAM_HAS_RESOURCE_STREAMER);
}
 
+   screen->has_exec_fence =
+ intel_get_boolean(screen, I915_PARAM_HAS_EXEC_FENCE);
+
return (const __DRIconfig**) intel_screen_make_configs(dri_screen);
 }
 
diff --git a/src/mesa/drivers/dri/i965/intel_screen.h 
b/src/mesa/drivers/dri/i965/intel_screen.h
index 890dd90..a1e2b31 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.h
+++ b/src/mesa/drivers/dri/i965/intel_screen.h
@@ -47,8 +47,8 @@ struct intel_screen
uint64_t max_gtt_map_object_size;
 
bool no_hw;
-
bool hw_has_swizzling;
+   bool has_exec_fence; /**< I915_PARAM_HAS_EXEC_FENCE */
 
int hw_has_timestamp;
 

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Mesa (master): i965: Add intel_batchbuffer_flush_fence()

2017-01-27 Thread Chad Versace 
Module: Mesa
Branch: master
Commit: d1ce499daed333d528911be4b89c023dcb41d0a9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1ce499daed333d528911be4b89c023dcb41d0a9

Author: Chad Versace 
Date:   Fri Jan 13 10:46:49 2017 -0800

i965: Add intel_batchbuffer_flush_fence()

A variant of intel_batchbuffer_flush() with parameters for in and out
fence fds.

Reviewed-by: Rafael Antognolli 
Tested-by: Rafael Antognolli 
Acked-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 24 ++--
 src/mesa/drivers/dri/i965/intel_batchbuffer.h | 14 --
 2 files changed, 26 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index d1b9317..67054cf 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -319,7 +319,7 @@ throttle(struct brw_context *brw)
 /* TODO: Push this whole function into bufmgr.
  */
 static int
-do_flush_locked(struct brw_context *brw)
+do_flush_locked(struct brw_context *brw, int in_fence_fd, int *out_fence_fd)
 {
struct intel_batchbuffer *batch = >batch;
int ret = 0;
@@ -353,11 +353,15 @@ do_flush_locked(struct brw_context *brw)
 brw_annotate_aub(brw);
 
 if (brw->hw_ctx == NULL || batch->ring != RENDER_RING) {
+assert(in_fence_fd == -1);
+assert(out_fence_fd == NULL);
 ret = drm_intel_bo_mrb_exec(batch->bo, 4 * USED_BATCH(*batch),
 NULL, 0, 0, flags);
 } else {
-   ret = drm_intel_gem_bo_context_exec(batch->bo, brw->hw_ctx,
-4 * USED_BATCH(*batch), flags);
+   ret = drm_intel_gem_bo_fence_exec(batch->bo, brw->hw_ctx,
+4 * USED_BATCH(*batch),
+in_fence_fd, out_fence_fd,
+flags);
 }
   }
 
@@ -378,9 +382,17 @@ do_flush_locked(struct brw_context *brw)
return ret;
 }
 
+/**
+ * The in_fence_fd is ignored if -1.  Otherwise this function takes ownership
+ * of the fd.
+ *
+ * The out_fence_fd is ignored if NULL. Otherwise, the caller takes ownership
+ * of the returned fd.
+ */
 int
-_intel_batchbuffer_flush(struct brw_context *brw,
-const char *file, int line)
+_intel_batchbuffer_flush_fence(struct brw_context *brw,
+   int in_fence_fd, int *out_fence_fd,
+   const char *file, int line)
 {
int ret;
 
@@ -419,7 +431,7 @@ _intel_batchbuffer_flush(struct brw_context *brw,
/* Check that we didn't just wrap our batchbuffer at a bad time. */
assert(!brw->no_batch_wrap);
 
-   ret = do_flush_locked(brw);
+   ret = do_flush_locked(brw, in_fence_fd, out_fence_fd);
 
if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
   fprintf(stderr, "waiting for idle\n");
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index ee03a44..bf7cadf 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -46,14 +46,16 @@ void intel_batchbuffer_save_state(struct brw_context *brw);
 void intel_batchbuffer_reset_to_saved(struct brw_context *brw);
 void intel_batchbuffer_require_space(struct brw_context *brw, GLuint sz,
  enum brw_gpu_ring ring);
+int _intel_batchbuffer_flush_fence(struct brw_context *brw,
+   int in_fence_fd, int *out_fence_fd,
+   const char *file, int line);
 
-int _intel_batchbuffer_flush(struct brw_context *brw,
-const char *file, int line);
-
-#define intel_batchbuffer_flush(intel) \
-   _intel_batchbuffer_flush(intel, __FILE__, __LINE__)
-
+#define intel_batchbuffer_flush(brw) \
+   _intel_batchbuffer_flush_fence((brw), -1, NULL, __FILE__, __LINE__)
 
+#define intel_batchbuffer_flush_fence(brw, in_fence_fd, out_fence_fd) \
+   _intel_batchbuffer_flush_fence((brw), (in_fence_fd), (out_fence_fd), \
+  __FILE__, __LINE__)
 
 /* Unlike bmBufferData, this currently requires the buffer be mapped.
  * Consider it a convenience function wrapping multple

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Mesa (master): i965/sync: Fail sync creation when batchbuffer flush fails

2017-01-27 Thread Chad Versace 
Module: Mesa
Branch: master
Commit: a5c17f5c29c14e7fc989f2555f1f7e32f07d6bf3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5c17f5c29c14e7fc989f2555f1f7e32f07d6bf3

Author: Chad Versace 
Date:   Fri Jan 13 10:46:49 2017 -0800

i965/sync: Fail sync creation when batchbuffer flush fails

Pre-patch, brw_sync.c ignored the return value of
intel_batchbuffer_flush().

When intel_batchbuffer_flush() fails during eglCreateSync
(brw_dri_create_fence), we now give up, cleanup, and return NULL.

When it fails during glFenceSync, however, we blindly continue and hope
for the best because there does not exist yet a way to tell core GL that
sync creation failed.

Reviewed-by: Rafael Antognolli 
Tested-by: Rafael Antognolli 
Acked-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_sync.c | 34 --
 1 file changed, 28 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_sync.c 
b/src/mesa/drivers/dri/i965/brw_sync.c
index f9127a4..24c8cbd 100644
--- a/src/mesa/drivers/dri/i965/brw_sync.c
+++ b/src/mesa/drivers/dri/i965/brw_sync.c
@@ -90,7 +90,7 @@ brw_fence_finish(struct brw_fence *fence)
mtx_destroy(>mutex);
 }
 
-static void
+static bool MUST_CHECK
 brw_fence_insert(struct brw_context *brw, struct brw_fence *fence)
 {
brw_emit_mi_flush(brw);
@@ -102,9 +102,16 @@ brw_fence_insert(struct brw_context *brw, struct brw_fence 
*fence)
 
   fence->batch_bo = brw->batch.bo;
   drm_intel_bo_reference(fence->batch_bo);
-  intel_batchbuffer_flush(brw);
+
+  if (intel_batchbuffer_flush(brw) < 0) {
+ drm_intel_bo_unreference(fence->batch_bo);
+ fence->batch_bo = NULL;
+ return false;
+  }
   break;
}
+
+   return true;
 }
 
 static bool
@@ -115,8 +122,10 @@ brw_fence_has_completed_locked(struct brw_fence *fence)
 
switch (fence->type) {
case BRW_FENCE_TYPE_BO_WAIT:
-  if (!fence->batch_bo)
+  if (!fence->batch_bo) {
+ /* There may be no batch if intel_batchbuffer_flush() failed. */
  return false;
+  }
 
   if (drm_intel_bo_busy(fence->batch_bo))
  return false;
@@ -152,7 +161,10 @@ brw_fence_client_wait_locked(struct brw_context *brw, 
struct brw_fence *fence,
 
switch (fence->type) {
case BRW_FENCE_TYPE_BO_WAIT:
-  assert(fence->batch_bo);
+  if (!fence->batch_bo) {
+ /* There may be no batch if intel_batchbuffer_flush() failed. */
+ return false;
+  }
 
   /* DRM_IOCTL_I915_GEM_WAIT uses a signed 64 bit timeout and returns
* immediately for timeouts <= 0.  The best we can do is to clamp the
@@ -236,7 +248,12 @@ brw_gl_fence_sync(struct gl_context *ctx, struct 
gl_sync_object *_sync,
struct brw_gl_sync *sync = (struct brw_gl_sync *) _sync;
 
brw_fence_init(brw, >fence, BRW_FENCE_TYPE_BO_WAIT);
-   brw_fence_insert(brw, >fence);
+
+   if (!brw_fence_insert(brw, >fence)) {
+  /* FIXME: There exists no way to report a GL error here. If an error
+   * occurs, continue silently and hope for the best.
+   */
+   }
 }
 
 static void
@@ -291,7 +308,12 @@ brw_dri_create_fence(__DRIcontext *ctx)
   return NULL;
 
brw_fence_init(brw, fence, BRW_FENCE_TYPE_BO_WAIT);
-   brw_fence_insert(brw, fence);
+
+   if (!brw_fence_insert(brw, fence)) {
+  brw_fence_finish(fence);
+  free(fence);
+  return NULL;
+   }
 
return fence;
 }

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Mesa (master): configure.ac: list radeon in --with-vulkan-drivers help string

2017-01-27 Thread Emil Velikov 
Module: Mesa
Branch: master
Commit: cb6be5c8c05fa1af20ebd4f014d686244826f987
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb6be5c8c05fa1af20ebd4f014d686244826f987

Author: Emil Velikov 
Date:   Fri Jan 27 18:29:38 2017 +

configure.ac: list radeon in --with-vulkan-drivers help string

Analogous to what we do for the dri and gallium drivers.

Cc: 17.0 13.0 
Signed-off-by: Emil Velikov 
Reviewed-by: Bas Nieuwenhuizen 

---

 configure.ac | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configure.ac b/configure.ac
index 8ce5b80..72be7dd 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1738,7 +1738,7 @@ fi
 AC_ARG_WITH([vulkan-drivers],
 [AS_HELP_STRING([--with-vulkan-drivers@<:@=DIRS...@:>@],
 [comma delimited Vulkan drivers list, e.g.
-"intel"
+"intel,radeon"
 @<:@default=no@:>@])],
 [with_vulkan_drivers="$withval"],
 [with_vulkan_drivers="no"])

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Mesa (master): radv: automake: Don't install vk_platform.h or vulkan.h.

2017-01-27 Thread Emil Velikov 
Module: Mesa
Branch: master
Commit: 6f2dec0a235694779310979fd1cbf48a8d7ba27b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f2dec0a235694779310979fd1cbf48a8d7ba27b

Author: Emil Velikov 
Date:   Fri Jan 27 18:05:13 2017 +

radv: automake: Don't install vk_platform.h or vulkan.h.

These files belong to the vulkan loader.

Identical to
045f38a5075 vulkan: Don't install vk_platform.h or vulkan.h.

Cc: Dave Airlie 
Cc: Bas Nieuwenhuizen 
Cc: 17.0 
Signed-off-by: Emil Velikov 
Reviewed-by: Matt Turner 

---

 src/amd/vulkan/Makefile.am | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
index b47109b..66708cb 100644
--- a/src/amd/vulkan/Makefile.am
+++ b/src/amd/vulkan/Makefile.am
@@ -21,9 +21,7 @@
 
 include Makefile.sources
 
-vulkan_includedir = $(includedir)/vulkan
-
-vulkan_include_HEADERS = \
+noinst_HEADERS = \
$(top_srcdir)/include/vulkan/vk_platform.h \
$(top_srcdir)/include/vulkan/vulkan.h
 

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Mesa (master): anv: Advertise API version 1.0.39

2017-01-27 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: d96ade1c4c2708efc27cb6eea8f33c6eb04e5095
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d96ade1c4c2708efc27cb6eea8f33c6eb04e5095

Author: Jason Ekstrand 
Date:   Wed Jan 25 20:57:47 2017 -0800

anv: Advertise API version 1.0.39

I'm pretty sure we've kept up with the bug fixes.

Reviewed-by: Iago Toral Quiroga 

---

 src/intel/vulkan/anv_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index f40e9b2..27f06ac 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -646,7 +646,7 @@ void anv_GetPhysicalDeviceProperties(
};
 
*pProperties = (VkPhysicalDeviceProperties) {
-  .apiVersion = VK_MAKE_VERSION(1, 0, 5),
+  .apiVersion = VK_MAKE_VERSION(1, 0, 39),
   .driverVersion = 1,
   .vendorID = 0x8086,
   .deviceID = pdevice->chipset_id,

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Mesa (master): 37 new commits

2017-01-27 Thread Emil Velikov 
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f301fe2e681e72988f00d610a617a1c90c80b51
Author: Eric Engestrom 
Date:   Fri Jan 27 17:29:05 2017 +

gbm/dri: fix memory leaks in error path

Signed-off-by: Eric Engestrom 
[Emil Velikov: make sure it builds]
Signed-off-by: Emil Velikov 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d104f9aa71aae1ef7c64f3a52dbfb1f62ddaa31
Author: Emil Velikov 
Date:   Thu Jan 26 19:26:13 2017 +

docs/releasing: add a note about the relnotes template

Signed-off-by: Emil Velikov 
Reviewed-by: Nicolai Hähnle 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e076af0674671fd47ff7f0f78e3ed1a39d0b2e7
Author: Emil Velikov 
Date:   Thu Jan 26 13:24:10 2017 +

mesa: remove explicit __STDC_FORMAT_MACROS define

Analogous to previous commits.

Signed-off-by: Emil Velikov 
Reviewed-by: Eric Engestrom 
Reviewed-by: Jose Fonseca 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1cfe97ff0e083c71bd14caf16c58b859c551f549
Author: Emil Velikov 
Date:   Thu Jan 26 13:24:09 2017 +

nouveau: remove explicit __STDC_FORMAT_MACROS define

Already handled by the build.

Signed-off-by: Emil Velikov 
Reviewed-by: Eric Engestrom 
Reviewed-by: Jose Fonseca 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=027e04932ad0401dc1f950bd3cd6cf50794dcc7f
Author: Emil Velikov 
Date:   Thu Jan 26 13:24:08 2017 +

scons: swr: remove explicit __STDC_.*_MACROS defines

Analogous to previous commits.

Cc: George Kyriazis 
Signed-off-by: Emil Velikov 
Reviewed-by: Eric Engestrom 
Reviewed-by: Jose Fonseca 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e809fadb86e06956a3610e5327ca9d5cccbe4f60
Author: Emil Velikov 
Date:   Thu Jan 26 13:24:07 2017 +

gallium: remove explicit __STDC_.*_MACROS defines

Analogous to previous commits.

Signed-off-by: Emil Velikov 
Reviewed-by: Eric Engestrom 
Reviewed-by: Jose Fonseca 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=01e28c6cf54a9f05b3f3712348212235065b1515
Author: Emil Velikov 
Date:   Thu Jan 26 13:24:06 2017 +

gallivm: remove explicit __STDC_.*_MACROS defines

Correctly handled by the build systems.

Cc: Roland Scheidegger 
Signed-off-by: Emil Velikov 
Reviewed-by: Roland Scheidegger 
Reviewed-by: Eric Engestrom 
Reviewed-by: Jose Fonseca 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=74a174e12fe10452410adc84f69ef50d351ca2f7
Author: Emil Velikov 
Date:   Thu Jan 26 13:24:05 2017 +

glsl: remove explicit __STDC_FORMAT_MACROS define

Correctly handled by all the build systems.

Signed-off-by: Emil Velikov 
Reviewed-by: Eric Engestrom 
Reviewed-by: Jose Fonseca 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e9e917c263898bf1a787c5ebb263ef87ef9604e
Author: Emil Velikov 
Date:   Thu Jan 26 13:24:04 2017 +

autoconf: set all __STDC_*_MACROS

Analogous to previous commit(s), with a minor detail - here we set the
macros when building both C and C++ sources.

Resolving that is a more challenging task that we'll sort out another
day.

Signed-off-by: Emil Velikov 
Reviewed-by: Eric Engestrom 
Reviewed-by: Jose Fonseca 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d68ffa9446c6f05ae3bbb92b7b8136450e6dc94d
Author: Emil Velikov 
Date:   Thu Jan 26 13:24:03 2017 +

scons: always set __STDC_*_MACROS for C++ sources

Analogous to previous commit - just set the lot once throughout.

Cc: Jose Fonseca 
Signed-off-by: Emil Velikov 
Reviewed-by: Eric Engestrom 
Reviewed-by: Jose Fonseca 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=13e2928d57fc974158dd3e5cf74ac32dfa8ca622

Mesa (master): anv: add missing core errors in vk_errorf()

2017-01-27 Thread Lionel Landwerlin 
Module: Mesa
Branch: master
Commit: 86879bf4ed8adf5e209ae50f34cffbc01168af7f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=86879bf4ed8adf5e209ae50f34cffbc01168af7f

Author: Eric Engestrom 
Date:   Thu Jan 26 13:48:17 2017 +

anv: add missing core errors in vk_errorf()

Signed-off-by: Eric Engestrom 
Reviewed-by: Lionel Landwerlin 

---

 src/intel/vulkan/anv_util.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/intel/vulkan/anv_util.c b/src/intel/vulkan/anv_util.c
index 5fbc7cc..289d01e 100644
--- a/src/intel/vulkan/anv_util.c
+++ b/src/intel/vulkan/anv_util.c
@@ -82,7 +82,10 @@ __vk_errorf(VkResult error, const char *file, int line, 
const char *format, ...)
ERROR_CASE(VK_ERROR_MEMORY_MAP_FAILED)
ERROR_CASE(VK_ERROR_LAYER_NOT_PRESENT)
ERROR_CASE(VK_ERROR_EXTENSION_NOT_PRESENT)
+   ERROR_CASE(VK_ERROR_FEATURE_NOT_PRESENT)
ERROR_CASE(VK_ERROR_INCOMPATIBLE_DRIVER)
+   ERROR_CASE(VK_ERROR_TOO_MANY_OBJECTS)
+   ERROR_CASE(VK_ERROR_FORMAT_NOT_SUPPORTED)
ERROR_CASE(VK_ERROR_FRAGMENTED_POOL)
 
/* Extension errors */

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Mesa (master): anv: don' t assert on out of memory descriptor pool in debug mode

2017-01-27 Thread Lionel Landwerlin 
Module: Mesa
Branch: master
Commit: ba26c791573727acf802787a3c7b5e19504d946c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba26c791573727acf802787a3c7b5e19504d946c

Author: Lionel Landwerlin 
Date:   Thu Jan 26 11:25:44 2017 +

anv: don't assert on out of memory descriptor pool in debug mode

Fixes:
   dEQP-VK.api.descriptor_pool.out_of_pool_memory

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Eric Engestrom 

---

 src/intel/vulkan/anv_util.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/intel/vulkan/anv_util.c b/src/intel/vulkan/anv_util.c
index 6408ac8..5fbc7cc 100644
--- a/src/intel/vulkan/anv_util.c
+++ b/src/intel/vulkan/anv_util.c
@@ -83,9 +83,11 @@ __vk_errorf(VkResult error, const char *file, int line, 
const char *format, ...)
ERROR_CASE(VK_ERROR_LAYER_NOT_PRESENT)
ERROR_CASE(VK_ERROR_EXTENSION_NOT_PRESENT)
ERROR_CASE(VK_ERROR_INCOMPATIBLE_DRIVER)
+   ERROR_CASE(VK_ERROR_FRAGMENTED_POOL)
 
/* Extension errors */
ERROR_CASE(VK_ERROR_OUT_OF_DATE_KHR)
+   ERROR_CASE(VK_ERROR_OUT_OF_POOL_MEMORY_KHR)
 
default:
   assert(!"Unknown error");

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Mesa (master): anv: add missing extension errors in vk_errorf()

2017-01-27 Thread Lionel Landwerlin 
Module: Mesa
Branch: master
Commit: 1ee2ae834865c38470a051c26c7b60e398c8b94e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1ee2ae834865c38470a051c26c7b60e398c8b94e

Author: Eric Engestrom 
Date:   Thu Jan 26 13:48:18 2017 +

anv: add missing extension errors in vk_errorf()

Signed-off-by: Eric Engestrom 
Reviewed-by: Lionel Landwerlin 

---

 src/intel/vulkan/anv_util.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/intel/vulkan/anv_util.c b/src/intel/vulkan/anv_util.c
index 289d01e..6d75187 100644
--- a/src/intel/vulkan/anv_util.c
+++ b/src/intel/vulkan/anv_util.c
@@ -89,7 +89,12 @@ __vk_errorf(VkResult error, const char *file, int line, 
const char *format, ...)
ERROR_CASE(VK_ERROR_FRAGMENTED_POOL)
 
/* Extension errors */
+   ERROR_CASE(VK_ERROR_SURFACE_LOST_KHR)
+   ERROR_CASE(VK_ERROR_NATIVE_WINDOW_IN_USE_KHR)
ERROR_CASE(VK_ERROR_OUT_OF_DATE_KHR)
+   ERROR_CASE(VK_ERROR_INCOMPATIBLE_DISPLAY_KHR)
+   ERROR_CASE(VK_ERROR_VALIDATION_FAILED_EXT)
+   ERROR_CASE(VK_ERROR_INVALID_SHADER_NV)
ERROR_CASE(VK_ERROR_OUT_OF_POOL_MEMORY_KHR)
 
default:

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Mesa (master): egl: update headers from registry

2017-01-27 Thread Emil Velikov 
Module: Mesa
Branch: master
Commit: a98b3a0872f9c542e6db75d17b7875a3f0374a14
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a98b3a0872f9c542e6db75d17b7875a3f0374a14

Author: Eric Engestrom 
Date:   Tue Jan 24 18:07:05 2017 +

egl: update headers from registry

Khronos introduced a new macro (suggested by Google) to avoid using
C-style casts in C++ code, as those generate warnings.

Khronos Bugzilla: https://cvs.khronos.org/bugzilla/show_bug.cgi?id=16113
Signed-off-by: Eric Engestrom 
Reviewed-by: Emil Velikov 
Reviewed-by: Chad Versace 

---

 include/EGL/egl.h |  24 +++---
 include/EGL/eglext.h  | 197 +++---
 include/EGL/eglplatform.h |  10 ++-
 3 files changed, 206 insertions(+), 25 deletions(-)

diff --git a/include/EGL/egl.h b/include/EGL/egl.h
index 0d514e4..29f30d9 100644
--- a/include/EGL/egl.h
+++ b/include/EGL/egl.h
@@ -6,7 +6,7 @@ extern "C" {
 #endif
 
 /*
-** Copyright (c) 2013-2014 The Khronos Group Inc.
+** Copyright (c) 2013-2017 The Khronos Group Inc.
 **
 ** Permission is hereby granted, free of charge, to any person obtaining a
 ** copy of this software and/or associated documentation files (the
@@ -31,14 +31,14 @@ extern "C" {
 ** This header is generated from the Khronos OpenGL / OpenGL ES XML
 ** API Registry. The current version of the Registry, generator scripts
 ** used to make the header, and the header can be found at
-**   http://www.opengl.org/registry/
+**   http://www.opengl.org/registry/egl
 **
-** Khronos $Revision: 31039 $ on $Date: 2015-05-04 17:01:57 -0700 (Mon, 04 May 
2015) $
+** Khronos $Revision$ on $Date$
 */
 
 #include 
 
-/* Generated on date 20150504 */
+/* Generated on date 20161230 */
 
 /* Generated C header for:
  * API: egl
@@ -78,7 +78,7 @@ typedef void 
(*__eglMustCastToProperFunctionPointerType)(void);
 #define EGL_CONFIG_ID 0x3028
 #define EGL_CORE_NATIVE_ENGINE0x305B
 #define EGL_DEPTH_SIZE0x3025
-#define EGL_DONT_CARE ((EGLint)-1)
+#define EGL_DONT_CARE EGL_CAST(EGLint,-1)
 #define EGL_DRAW  0x3059
 #define EGL_EXTENSIONS0x3055
 #define EGL_FALSE 0
@@ -95,9 +95,9 @@ typedef void 
(*__eglMustCastToProperFunctionPointerType)(void);
 #define EGL_NONE  0x3038
 #define EGL_NON_CONFORMANT_CONFIG 0x3051
 #define EGL_NOT_INITIALIZED   0x3001
-#define EGL_NO_CONTEXT((EGLContext)0)
-#define EGL_NO_DISPLAY((EGLDisplay)0)
-#define EGL_NO_SURFACE((EGLSurface)0)
+#define EGL_NO_CONTEXTEGL_CAST(EGLContext,0)
+#define EGL_NO_DISPLAYEGL_CAST(EGLDisplay,0)
+#define EGL_NO_SURFACEEGL_CAST(EGLSurface,0)
 #define EGL_PBUFFER_BIT   0x0001
 #define EGL_PIXMAP_BIT0x0002
 #define EGL_READ  0x305A
@@ -197,7 +197,7 @@ typedef void *EGLClientBuffer;
 #define EGL_RGB_BUFFER0x308E
 #define EGL_SINGLE_BUFFER 0x3085
 #define EGL_SWAP_BEHAVIOR 0x3093
-#define EGL_UNKNOWN   ((EGLint)-1)
+#define EGL_UNKNOWN   EGL_CAST(EGLint,-1)
 #define EGL_VERTICAL_RESOLUTION   0x3091
 EGLAPI EGLBoolean EGLAPIENTRY eglBindAPI (EGLenum api);
 EGLAPI EGLenum EGLAPIENTRY eglQueryAPI (void);
@@ -224,7 +224,7 @@ EGLAPI EGLBoolean EGLAPIENTRY eglWaitClient (void);
 
 #ifndef EGL_VERSION_1_4
 #define EGL_VERSION_1_4 1
-#define EGL_DEFAULT_DISPLAY   ((EGLNativeDisplayType)0)
+#define EGL_DEFAULT_DISPLAY   EGL_CAST(EGLNativeDisplayType,0)
 #define EGL_MULTISAMPLE_RESOLVE_BOX_BIT   0x0200
 #define EGL_MULTISAMPLE_RESOLVE   0x3099
 #define EGL_MULTISAMPLE_RESOLVE_DEFAULT   0x309A
@@ -266,7 +266,7 @@ typedef void *EGLImage;
 #define EGL_FOREVER   0xull
 #define EGL_TIMEOUT_EXPIRED   0x30F5
 #define EGL_CONDITION_SATISFIED   0x30F6
-#define EGL_NO_SYNC   ((EGLSync)0)
+#define EGL_NO_SYNC   EGL_CAST(EGLSync,0)
 #define EGL_SYNC_FENCE0x30F9
 #define EGL_GL_COLORSPACE 0x309D
 #define EGL_GL_COLORSPACE_SRGB0x3089
@@ -283,7 +283,7 @@ typedef void *EGLImage;
 #define EGL_GL_TEXTURE_CUBE_MAP_POSITIVE_Z 0x30B7
 #define EGL_GL_TEXTURE_CUBE_MAP_NEGATIVE_Z 0x30B8
 #define EGL_IMAGE_PRESERVED   0x30D2
-#define EGL_NO_IMAGE  ((EGLImage)0)
+#define EGL_NO_IMAGE  EGL_CAST(EGLImage,0)
 EGLAPI EGLSync EGLAPIENTRY eglCreateSync (EGLDisplay dpy, EGLenum type, const 
EGLAttrib *attrib_list);
 EGLAPI EGLBoolean EGLAPIENTRY eglDestroySync (EGLDisplay dpy, EGLSync

Mesa (master): egl: EGL_PLATFORM_SURFACELESS_MESA is now upstream

2017-01-27 Thread Emil Velikov 
Module: Mesa
Branch: master
Commit: 87619a1a6acbaddfdd72a364b15524e5d0b99afc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=87619a1a6acbaddfdd72a364b15524e5d0b99afc

Author: Eric Engestrom 
Date:   Tue Jan 24 18:07:06 2017 +

egl: EGL_PLATFORM_SURFACELESS_MESA is now upstream

EGL_PLATFORM_SURFACELESS_MESA is in eglext.h as of last commit.

Signed-off-by: Eric Engestrom 
Reviewed-by: Emil Velikov 
Reviewed-by: Chad Versace 

---

 include/EGL/eglmesaext.h | 5 -
 1 file changed, 5 deletions(-)

diff --git a/include/EGL/eglmesaext.h b/include/EGL/eglmesaext.h
index 405d0e9..3a1b88e 100644
--- a/include/EGL/eglmesaext.h
+++ b/include/EGL/eglmesaext.h
@@ -85,11 +85,6 @@ typedef EGLBoolean (EGLAPIENTRYP PFNEGLSWAPBUFFERSREGIONNOK) 
(EGLDisplay dpy, EG
 #define EGL_NO_CONFIG_MESA ((EGLConfig)0)
 #endif
 
-#ifndef EGL_MESA_platform_surfaceless
-#define EGL_MESA_platform_surfaceless 1
-#define EGL_PLATFORM_SURFACELESS_MESA   0x31DD
-#endif /* EGL_MESA_platform_surfaceless */
-
 #ifdef __cplusplus
 }
 #endif

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Mesa (master): docs/repository: fix name of main branch

2017-01-27 Thread Emil Velikov 
Module: Mesa
Branch: master
Commit: 4da0d1c59a6e42e56036827328b98d72d3f4a8e0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4da0d1c59a6e42e56036827328b98d72d3f4a8e0

Author: Eric Engestrom 
Date:   Thu Jan 26 18:11:10 2017 +

docs/repository: fix name of main branch

This is git, not svn :P

Signed-off-by: Eric Engestrom 
Reviewed-by: Matt Turner 

---

 docs/repository.html | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/repository.html b/docs/repository.html
index 1fb88bf..714074f 100644
--- a/docs/repository.html
+++ b/docs/repository.html
@@ -144,7 +144,7 @@ Unix users don't need to set this option.
 
 At any given time, there may be several active branches in Mesa's
 repository.
-Generally, the trunk contains the latest development (unstable)
+Generally, master contains the latest development (unstable)
 code while a branch has the latest stable code.
 
 

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Mesa (master): radv: add missing extension errors in vk_errorf()

2017-01-27 Thread Bas Nieuwenhuizen 
Module: Mesa
Branch: master
Commit: 06842585df830a710ec59c2385bcef5badd8ecc6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=06842585df830a710ec59c2385bcef5badd8ecc6

Author: Eric Engestrom 
Date:   Thu Jan 26 14:20:24 2017 +

radv: add missing extension errors in vk_errorf()

v2(Bas): Remove the extra VK_ERROR_FRAGMENTED_POOL cases.

Signed-off-by: Eric Engestrom 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/amd/vulkan/radv_util.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/amd/vulkan/radv_util.c b/src/amd/vulkan/radv_util.c
index 494bf7e..684956e 100644
--- a/src/amd/vulkan/radv_util.c
+++ b/src/amd/vulkan/radv_util.c
@@ -91,7 +91,13 @@ __vk_errorf(VkResult error, const char *file, int line, 
const char *format, ...)
ERROR_CASE(VK_ERROR_FRAGMENTED_POOL)
 
/* Extension errors */
+   ERROR_CASE(VK_ERROR_SURFACE_LOST_KHR)
+   ERROR_CASE(VK_ERROR_NATIVE_WINDOW_IN_USE_KHR)
ERROR_CASE(VK_ERROR_OUT_OF_DATE_KHR)
+   ERROR_CASE(VK_ERROR_INCOMPATIBLE_DISPLAY_KHR)
+   ERROR_CASE(VK_ERROR_VALIDATION_FAILED_EXT)
+   ERROR_CASE(VK_ERROR_INVALID_SHADER_NV)
+   ERROR_CASE(VK_ERROR_OUT_OF_POOL_MEMORY_KHR)
 
default:
assert(!"Unknown error");

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Mesa (master): radv: add missing core errors in vk_errorf()

2017-01-27 Thread Bas Nieuwenhuizen 
Module: Mesa
Branch: master
Commit: 43cf96751277f76d726a0829e7fa733f85e70061
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=43cf96751277f76d726a0829e7fa733f85e70061

Author: Eric Engestrom 
Date:   Thu Jan 26 14:20:23 2017 +

radv: add missing core errors in vk_errorf()

Signed-off-by: Eric Engestrom 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/amd/vulkan/radv_util.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/amd/vulkan/radv_util.c b/src/amd/vulkan/radv_util.c
index c642bb7..494bf7e 100644
--- a/src/amd/vulkan/radv_util.c
+++ b/src/amd/vulkan/radv_util.c
@@ -84,7 +84,11 @@ __vk_errorf(VkResult error, const char *file, int line, 
const char *format, ...)
ERROR_CASE(VK_ERROR_MEMORY_MAP_FAILED)
ERROR_CASE(VK_ERROR_LAYER_NOT_PRESENT)
ERROR_CASE(VK_ERROR_EXTENSION_NOT_PRESENT)
+   ERROR_CASE(VK_ERROR_FEATURE_NOT_PRESENT)
ERROR_CASE(VK_ERROR_INCOMPATIBLE_DRIVER)
+   ERROR_CASE(VK_ERROR_TOO_MANY_OBJECTS)
+   ERROR_CASE(VK_ERROR_FORMAT_NOT_SUPPORTED)
+   ERROR_CASE(VK_ERROR_FRAGMENTED_POOL)
 
/* Extension errors */
ERROR_CASE(VK_ERROR_OUT_OF_DATE_KHR)

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Mesa (master): configure.ac: Require LLVM for r300 only on x86 and x86_64

2017-01-27 Thread Andreas Boll 
Module: Mesa
Branch: master
Commit: 1f2a890ace07f2709ca8f7ef5fe12051222aafed
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f2a890ace07f2709ca8f7ef5fe12051222aafed

Author: Andreas Boll 
Date:   Tue Jan 24 16:44:12 2017 +0100

configure.ac: Require LLVM for r300 only on x86 and x86_64

b3119a3 introduced a strict LLVM requirement for r300 on all
architectures and thus configure fails on architectures where LLVM is
not available or buggy.

r300 doesn't strictly require LLVM, but for performance reasons we
highly recommend LLVM usage. So require it at least on x86 and x86_64
architectures as we have done before b3119a3.

Fixes: b3119a3 ("configure.ac: Check gallium LLVM version in 
gallium_require_llvm")
Cc: 17.0 
Signed-off-by: Andreas Boll 
Reviewed-by: Marek Olšák 
Reviewed-by: Emil Velikov 

---

 configure.ac | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/configure.ac b/configure.ac
index 64ace9d..b35adc8 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2213,6 +2213,19 @@ gallium_require_llvm() {
 }
 
 dnl
+dnl r300 doesn't strictly require LLVM, but for performance reasons we
+dnl highly recommend LLVM usage. So require it at least on x86 and x86_64
+dnl architectures.
+dnl
+r300_require_llvm() {
+case "$host" in *gnux32) return;; esac
+case "$host_cpu" in
+i*86|x86_64|amd64) gallium_require_llvm $1
+;;
+esac
+}
+
+dnl
 dnl DRM is needed by X, Wayland, and offscreen rendering.
 dnl Surfaceless is an alternative for the last one.
 dnl
@@ -2298,7 +2311,7 @@ if test -n "$with_gallium_drivers"; then
 HAVE_GALLIUM_R300=yes
 PKG_CHECK_MODULES([RADEON], [libdrm_radeon >= 
$LIBDRM_RADEON_REQUIRED])
 require_libdrm "r300"
-gallium_require_llvm "r300"
+r300_require_llvm "r300"
 ;;
 xr600)
 HAVE_GALLIUM_R600=yes

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Mesa (master): gallium: enable int64 on radeonsi, llvmpipe, softpipe

2017-01-27 Thread Nicolai Hähnle 
Module: Mesa
Branch: master
Commit: c5e76a262a4246267bbbfa803aebeeb733388e11
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c5e76a262a4246267bbbfa803aebeeb733388e11

Author: Nicolai Hähnle 
Date:   Tue Jan 24 21:22:32 2017 +0100

gallium: enable int64 on radeonsi, llvmpipe, softpipe

All of these have had support for the TGSI opcodes since before most of
the glsl compiler work landed.

Also update the docs accordingly, including the missing note about i965.

Reviewed-by: Marek Olšák 

---

 docs/features.txt|  2 +-
 docs/relnotes/17.1.0.html| 61 
 src/gallium/drivers/llvmpipe/lp_screen.c |  2 +-
 src/gallium/drivers/radeonsi/si_pipe.c   |  4 +--
 src/gallium/drivers/softpipe/sp_screen.c |  2 +-
 5 files changed, 66 insertions(+), 5 deletions(-)

diff --git a/docs/features.txt b/docs/features.txt
index aff0016..55b1fbb 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -283,7 +283,7 @@ Khronos, ARB, and OES extensions that are not part of any 
OpenGL or OpenGL ES ve
   GL_ARB_ES3_2_compatibilityDONE (i965/gen8+)
   GL_ARB_fragment_shader_interlock  not started
   GL_ARB_gl_spirv   not started
-  GL_ARB_gpu_shader_int64   started (airlied for 
core and Gallium, idr for i965)
+  GL_ARB_gpu_shader_int64   DONE (i965/gen8+, 
radeonsi, softpipe, llvmpipe)
   GL_ARB_indirect_parametersDONE (nvc0, radeonsi)
   GL_ARB_parallel_shader_compilenot started, but 
Chia-I Wu did some related work in 2014
   GL_ARB_pipeline_statistics_query  DONE (i965, nvc0, 
radeonsi, softpipe, swr)
diff --git a/docs/relnotes/17.1.0.html b/docs/relnotes/17.1.0.html
new file mode 100644
index 000..1b5535b
--- /dev/null
+++ b/docs/relnotes/17.1.0.html
@@ -0,0 +1,61 @@
+http://www.w3.org/TR/html4/loose.dtd;>
+
+
+  
+  Mesa Release Notes
+  
+
+
+
+
+  The Mesa 3D Graphics Library
+
+
+
+
+
+Mesa 17.1.0 Release Notes / TBD
+
+
+Mesa 17.1.0 is a new development release.
+People who are concerned with stability and reliability should stick
+with a previous release or wait for Mesa 17.1.1.
+
+
+Mesa 17.1.0 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is only available if requested at context creation
+because compatibility contexts are not supported.
+
+
+
+SHA256 checksums
+
+TBD.
+
+
+
+New features
+
+
+Note: some of the new features are only available with certain drivers.
+
+
+
+GL_ARB_gpu_shader_int64 on i965/gen8+, radeonsi, softpipe, llvmpipe
+
+
+Bug fixes
+
+
+
+
+Changes
+
+TBD.
+
+
+
+
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c 
b/src/gallium/drivers/llvmpipe/lp_screen.c
index 6ef22b8..0982c35 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -267,6 +267,7 @@ llvmpipe_get_param(struct pipe_screen *screen, enum 
pipe_cap param)
   return 1;
case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
+   case PIPE_CAP_INT64:
   return 1;
 
case PIPE_CAP_VENDOR_ID:
@@ -343,7 +344,6 @@ llvmpipe_get_param(struct pipe_screen *screen, enum 
pipe_cap param)
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_TGSI_FS_FBFETCH:
case PIPE_CAP_TGSI_MUL_ZERO_WINS:
-   case PIPE_CAP_INT64:
   return 0;
}
/* should only get here on unhandled cases */
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 9f3cd05..1fe8b9f 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -413,7 +413,8 @@ static int si_get_param(struct pipe_screen* pscreen, enum 
pipe_cap param)
case PIPE_CAP_CULL_DISTANCE:
case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
-case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
+   case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
+   case PIPE_CAP_INT64:
return 1;
 
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
@@ -466,7 +467,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum 
pipe_cap param)
case PIPE_CAP_NATIVE_FENCE_FD:
case PIPE_CAP_TGSI_FS_FBFETCH:
case PIPE_CAP_TGSI_MUL_ZERO_WINS:
-   case PIPE_CAP_INT64:
return 0;
 
case PIPE_CAP_QUERY_BUFFER_OBJECT:
diff --git a/src/gallium/drivers/softpipe/sp_screen.c 
b/src/gallium/drivers/softpipe/sp_screen.c
index f5216b0..ec530a4 100644
--- a/src/gallium/drivers/softpipe/sp_screen.c
+++ b/src/gallium/drivers/softpipe/sp_screen.c
@@ -165,6 +165,7 @@

Mesa (master): gallium: Add integer 64 capability

2017-01-27 Thread Nicolai Hähnle 
Module: Mesa
Branch: master
Commit: f804506d4d4aa1299ce0b1026848321641311672
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f804506d4d4aa1299ce0b1026848321641311672

Author: Dave Airlie 
Date:   Thu Jun  9 10:13:03 2016 +1000

gallium: Add integer 64 capability

v1.1: move to using a normal CAP. (Marek)

v2: fill in the cap everywhere

Signed-off-by: Dave Airlie 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/etnaviv/etnaviv_screen.c | 1 +
 src/gallium/drivers/freedreno/freedreno_screen.c | 1 +
 src/gallium/drivers/i915/i915_screen.c   | 1 +
 src/gallium/drivers/ilo/ilo_screen.c | 1 +
 src/gallium/drivers/llvmpipe/lp_screen.c | 1 +
 src/gallium/drivers/nouveau/nv30/nv30_screen.c   | 1 +
 src/gallium/drivers/nouveau/nv50/nv50_screen.c   | 1 +
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c   | 1 +
 src/gallium/drivers/r300/r300_screen.c   | 1 +
 src/gallium/drivers/r600/r600_pipe.c | 1 +
 src/gallium/drivers/radeonsi/si_pipe.c   | 1 +
 src/gallium/drivers/softpipe/sp_screen.c | 1 +
 src/gallium/drivers/svga/svga_screen.c   | 1 +
 src/gallium/drivers/swr/swr_screen.cpp   | 1 +
 src/gallium/drivers/vc4/vc4_screen.c | 1 +
 src/gallium/drivers/virgl/virgl_screen.c | 1 +
 src/gallium/include/pipe/p_defines.h | 1 +
 17 files changed, 17 insertions(+)

diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c 
b/src/gallium/drivers/etnaviv/etnaviv_screen.c
index 66c530d..c045f7e 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_screen.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c
@@ -241,6 +241,7 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_TGSI_FS_FBFETCH:
case PIPE_CAP_TGSI_MUL_ZERO_WINS:
+   case PIPE_CAP_INT64:
   return 0;
 
/* Stream output. */
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c 
b/src/gallium/drivers/freedreno/freedreno_screen.c
index a1c026c..abb8787 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -298,6 +298,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_TGSI_FS_FBFETCH:
case PIPE_CAP_TGSI_MUL_ZERO_WINS:
+   case PIPE_CAP_INT64:
return 0;
 
case PIPE_CAP_MAX_VIEWPORTS:
diff --git a/src/gallium/drivers/i915/i915_screen.c 
b/src/gallium/drivers/i915/i915_screen.c
index 7889873..07d1488 100644
--- a/src/gallium/drivers/i915/i915_screen.c
+++ b/src/gallium/drivers/i915/i915_screen.c
@@ -299,6 +299,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap 
cap)
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_TGSI_FS_FBFETCH:
case PIPE_CAP_TGSI_MUL_ZERO_WINS:
+   case PIPE_CAP_INT64:
   return 0;
 
case PIPE_CAP_MAX_VIEWPORTS:
diff --git a/src/gallium/drivers/ilo/ilo_screen.c 
b/src/gallium/drivers/ilo/ilo_screen.c
index 6018cd1..960fd71 100644
--- a/src/gallium/drivers/ilo/ilo_screen.c
+++ b/src/gallium/drivers/ilo/ilo_screen.c
@@ -522,6 +522,7 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_TGSI_FS_FBFETCH:
case PIPE_CAP_TGSI_MUL_ZERO_WINS:
+   case PIPE_CAP_INT64:
   return 0;
 
case PIPE_CAP_VENDOR_ID:
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c 
b/src/gallium/drivers/llvmpipe/lp_screen.c
index 89a1dc8..6ef22b8 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -343,6 +343,7 @@ llvmpipe_get_param(struct pipe_screen *screen, enum 
pipe_cap param)
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_TGSI_FS_FBFETCH:
case PIPE_CAP_TGSI_MUL_ZERO_WINS:
+   case PIPE_CAP_INT64:
   return 0;
}
/* should only get here on unhandled cases */
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c 
b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
index b6c2636..2451e01 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
@@ -208,6 +208,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_TGSI_FS_FBFETCH:
case PIPE_CAP_TGSI_MUL_ZERO_WINS:
+   case PIPE_CAP_INT64:
   return 0;
 
case PIPE_CAP_VENDOR_ID:
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index d09b41a..cab0ce6 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -260,6 +260,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
case PIPE_CAP_NATIVE_FENCE_FD:
case

Mesa (master): st/glsl_to_tgsi: add support for 64-bit integers

2017-01-27 Thread Nicolai Hähnle 
Module: Mesa
Branch: master
Commit: 278580729a574a72460b013f4efc134a5523cb8d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=278580729a574a72460b013f4efc134a5523cb8d

Author: Dave Airlie 
Date:   Thu Jun  9 10:17:26 2016 +1000

st/glsl_to_tgsi: add support for 64-bit integers

v2: add conversion opcodes.

v3 (idr): Rebase on replacemtn of TGSI_OPCODE_I2U64 with
TGSI_OPCODE_I2I64.

v4 (idr): "cut them down later" => Remove ir_unop_b2u64 and
ir_unop_u642b.  Handle these with extra i2u or u2i casts just like
uint(bool) and bool(uint) conversion is done.

v5 (nha): add clarifying comment about a subtle assumption

Signed-off-by: Dave Airlie 
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Marek Olšák 

---

 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 220 ++---
 1 file changed, 202 insertions(+), 18 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index a437645..224789e 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -901,6 +901,10 @@ glsl_to_tgsi_visitor::get_opcode(unsigned op,
 
if (is_resource_instruction(op))
   type = src1.type;
+   else if (src0.type == GLSL_TYPE_INT64 || src1.type == GLSL_TYPE_INT64)
+  type = GLSL_TYPE_INT64;
+   else if (src0.type == GLSL_TYPE_UINT64 || src1.type == GLSL_TYPE_UINT64)
+  type = GLSL_TYPE_UINT64;
else if (src0.type == GLSL_TYPE_DOUBLE || src1.type == GLSL_TYPE_DOUBLE)
   type = GLSL_TYPE_DOUBLE;
else if (src0.type == GLSL_TYPE_FLOAT || src1.type == GLSL_TYPE_FLOAT)
@@ -908,6 +912,21 @@ glsl_to_tgsi_visitor::get_opcode(unsigned op,
else if (native_integers)
   type = src0.type == GLSL_TYPE_BOOL ? GLSL_TYPE_INT : src0.type;
 
+#define case7(c, f, i, u, d, i64, ui64) \
+   case TGSI_OPCODE_##c: \
+  if (type == GLSL_TYPE_UINT64)   \
+ op = TGSI_OPCODE_##ui64; \
+  else if (type == GLSL_TYPE_INT64)   \
+ op = TGSI_OPCODE_##i64; \
+  else if (type == GLSL_TYPE_DOUBLE)   \
+ op = TGSI_OPCODE_##d; \
+  else if (type == GLSL_TYPE_INT)   \
+ op = TGSI_OPCODE_##i; \
+  else if (type == GLSL_TYPE_UINT) \
+ op = TGSI_OPCODE_##u; \
+  else \
+ op = TGSI_OPCODE_##f; \
+  break;
 #define case5(c, f, i, u, d)\
case TGSI_OPCODE_##c: \
   if (type == GLSL_TYPE_DOUBLE)   \
@@ -931,14 +950,22 @@ glsl_to_tgsi_visitor::get_opcode(unsigned op,
   break;
 
 #define case3(f, i, u)  case4(f, f, i, u)
-#define case4d(f, i, u, d)  case5(f, f, i, u, d)
+#define case6d(f, i, u, d, i64, u64)  case7(f, f, i, u, d, i64, u64)
 #define case3fid(f, i, d) case5(f, f, i, i, d)
+#define case3fid64(f, i, d, i64) case7(f, f, i, i, d, i64, i64)
 #define case2fi(f, i)   case4(f, f, i, i)
 #define case2iu(i, u)   case4(i, LAST, i, u)
 
-#define casecomp(c, f, i, u, d)   \
+#define case2iu64(i, i64)   case7(i, LAST, i, i, LAST, i64, i64)
+#define case4iu64(i, u, i64, u64)   case7(i, LAST, i, u, LAST, i64, u64)
+
+#define casecomp(c, f, i, u, d, i64, ui64)   \
case TGSI_OPCODE_##c: \
-  if (type == GLSL_TYPE_DOUBLE) \
+  if (type == GLSL_TYPE_INT64) \
+ op = TGSI_OPCODE_##i64; \
+  else if (type == GLSL_TYPE_UINT64)\
+ op = TGSI_OPCODE_##ui64; \
+  else if (type == GLSL_TYPE_DOUBLE)   \
  op = TGSI_OPCODE_##d; \
   else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE)   \
  op = TGSI_OPCODE_##i; \
@@ -951,23 +978,24 @@ glsl_to_tgsi_visitor::get_opcode(unsigned op,
   break;
 
switch(op) {
-  case3fid(ADD, UADD, DADD);
-  case3fid(MUL, UMUL, DMUL);
+  case3fid64(ADD, UADD, DADD, U64ADD);
+  case3fid64(MUL, UMUL, DMUL, U64MUL);
   case3fid(MAD, UMAD, DMAD);
   case3fid(FMA, UMAD, DFMA);
-  case4d(DIV, IDIV, UDIV, DDIV);
-  case4d(MAX, IMAX, UMAX, DMAX);
-  case4d(MIN, IMIN, UMIN, DMIN);
-  case2iu(MOD, UMOD);
+  case6d(DIV, IDIV, UDIV, DDIV, I64DIV, U64DIV);
+  case6d(MAX, IMAX, UMAX, DMAX, I64MAX, U64MAX);
+  case6d(MIN, IMIN, UMIN, DMIN, I64MIN, U64MIN);
+  case4iu64(MOD, UMOD, I64MOD, U64MOD);
 
-  casecomp(SEQ, FSEQ, USEQ, USEQ, DSEQ);
-  casecomp(SNE, FSNE, USNE, USNE, DSNE);
-  casecomp(SGE, FSGE, ISGE, USGE, DSGE);
-  casecomp(SLT, FSLT, ISLT, USLT, DSLT);
+  casecomp(SEQ, FSEQ, USEQ, USEQ, DSEQ, U64SEQ, U64SEQ);
+  casecomp(SNE, FSNE, USNE, USNE, DSNE, U64SNE, U64SNE);
+  casecomp(SGE, FSGE, ISGE, USGE, DSGE, I64SGE, U64SGE);
+  casecomp(SLT, FSLT, ISLT, USLT, DSLT, I64SLT, U64SLT);
 
-  case2iu(ISHR, USHR);
+  case2iu64(SHL, U64SHL);
+  case4iu64(ISHR, USHR, I64SHR, U64SHR);
 
-  case3fid(SSG, ISSG, DSSG);
+  case3fid64(SSG, ISSG, DSSG, I64SSG);

Mesa (master): st/mesa: add support for enabling ARB_gpu_shader_int64.

2017-01-27 Thread Nicolai Hähnle 
Module: Mesa
Branch: master
Commit: 93dc5c1a06e4c7e1038e9adfc9349c3e8a1a0052
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=93dc5c1a06e4c7e1038e9adfc9349c3e8a1a0052

Author: Dave Airlie 
Date:   Thu Jun  9 10:17:58 2016 +1000

st/mesa: add support for enabling ARB_gpu_shader_int64.

Signed-off-by: Dave Airlie 
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Marek Olšák 

---

 src/mesa/state_tracker/st_extensions.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/state_tracker/st_extensions.c 
b/src/mesa/state_tracker/st_extensions.c
index 5ccc5d9..4600b88 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -588,6 +588,7 @@ void st_init_extensions(struct pipe_screen *screen,
   { o(ARB_draw_instanced),   PIPE_CAP_TGSI_INSTANCEID  
},
   { o(ARB_fragment_program_shadow),  PIPE_CAP_TEXTURE_SHADOW_MAP   
},
   { o(ARB_framebuffer_object),   PIPE_CAP_MIXED_FRAMEBUFFER_SIZES  
},
+  { o(ARB_gpu_shader_int64), PIPE_CAP_INT64
},
   { o(ARB_indirect_parameters),  
PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS   },
   { o(ARB_instanced_arrays), 
PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR  },
   { o(ARB_occlusion_query),  PIPE_CAP_OCCLUSION_QUERY  
},

___
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