date:20170603

Mesa (master): radv: Dirty all descriptors sets when changing the pipeline.

2017-06-03 Thread Bas Nieuwenhuizen

Module: Mesa
Branch: master
Commit: 4415a46be2cbb752b94b62bdf5bc7d4d4bbe9fab
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4415a46be2cbb752b94b62bdf5bc7d4d4bbe9fab

Author: Bas Nieuwenhuizen 
Date:   Sat Jun  3 00:01:36 2017 +0200

radv: Dirty all descriptors sets when changing the pipeline.

Sets could have been ignored during previous descriptor set flush
due to the shader not using them and therefore no SGPR being assigned.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Dave Airlie 
Fixes: ae61ddabe8c "radv: move userdata sgpr ownership to compiler side."

---

 src/amd/vulkan/radv_cmd_buffer.c | 17 -
 src/amd/vulkan/radv_meta.c   |  5 ++---
 2 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 0f7b754da9..6826ec5aa3 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2186,6 +2186,13 @@ radv_emit_compute_pipeline(struct radv_cmd_buffer 
*cmd_buffer)
assert(cmd_buffer->cs->cdw <= cdw_max);
 }
 
+static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
+{
+   for (unsigned i = 0; i < MAX_SETS; i++) {
+   if (cmd_buffer->state.descriptors[i])
+   cmd_buffer->state.descriptors_dirty |= (1u << i);
+   }
+}
 
 void radv_CmdBindPipeline(
VkCommandBuffer commandBuffer,
@@ -2195,10 +2202,7 @@ void radv_CmdBindPipeline(
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
 
-   for (unsigned i = 0; i < MAX_SETS; i++) {
-   if (cmd_buffer->state.descriptors[i])
-   cmd_buffer->state.descriptors_dirty |= (1u << i);
-   }
+   radv_mark_descriptor_sets_dirty(cmd_buffer);
 
switch (pipelineBindPoint) {
case VK_PIPELINE_BIND_POINT_COMPUTE:
@@ -2207,6 +2211,9 @@ void radv_CmdBindPipeline(
break;
case VK_PIPELINE_BIND_POINT_GRAPHICS:
cmd_buffer->state.pipeline = pipeline;
+   if (!pipeline)
+   break;
+
cmd_buffer->state.vertex_descriptors_dirty = true;
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
cmd_buffer->push_constant_stages |= pipeline->active_stages;
@@ -2369,7 +2376,6 @@ void radv_CmdSetStencilReference(
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
 }
 
-
 void radv_CmdExecuteCommands(
VkCommandBuffer commandBuffer,
uint32_tcommandBufferCount,
@@ -2414,6 +2420,7 @@ void radv_CmdExecuteCommands(
primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
primary->state.last_primitive_reset_en = -1;
primary->state.last_primitive_reset_index = 0;
+   radv_mark_descriptor_sets_dirty(primary);
}
 }
 
diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index 4f359bd6a9..263181a57f 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -50,9 +50,9 @@ void
 radv_meta_restore(const struct radv_meta_saved_state *state,
  struct radv_cmd_buffer *cmd_buffer)
 {
-   cmd_buffer->state.pipeline = state->old_pipeline;
+   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), 
VK_PIPELINE_BIND_POINT_GRAPHICS,
+radv_pipeline_to_handle(state->old_pipeline));
cmd_buffer->state.descriptors[0] = state->old_descriptor_set0;
-   cmd_buffer->state.descriptors_dirty |= (1u << 0);
if (state->vertex_saved) {
memcpy(cmd_buffer->state.vertex_bindings, 
state->old_vertex_bindings,
   sizeof(state->old_vertex_bindings));
@@ -114,7 +114,6 @@ radv_meta_restore_compute(const struct 
radv_meta_saved_compute_state *state,
 radv_pipeline_to_handle(state->old_pipeline));
 
cmd_buffer->state.descriptors[0] = state->old_descriptor_set0;
-   cmd_buffer->state.descriptors_dirty |= (1u << 0);
 
if (push_constant_size) {
memcpy(cmd_buffer->push_constants, state->push_constants, 
push_constant_size);

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Mesa (master): radv: Set both compute and graphics SGPRS on descriptor set flush.

2017-06-03 Thread Bas Nieuwenhuizen

Module: Mesa
Branch: master
Commit: 5fb8bb306534d633ceb4e33d89984718326773ba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5fb8bb306534d633ceb4e33d89984718326773ba

Author: Bas Nieuwenhuizen 
Date:   Fri Jun  2 23:51:50 2017 +0200

radv: Set both compute and graphics SGPRS on descriptor set flush.

We clear the descriptors_dirty array afterwards, so the SGPRs for
the other pipeline don't get updated on the flush for that other
draw/dispatch, so we have to make sure we do it immediately.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Dave Airlie 
Fixes: ae61ddabe8c "radv: move userdata sgpr ownership to compiler side."

---

 src/amd/vulkan/radv_cmd_buffer.c | 100 +++
 1 file changed, 50 insertions(+), 50 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 64eab2d573..0f7b754da9 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1243,38 +1243,39 @@ emit_stage_descriptor_set_userdata(struct 
radv_cmd_buffer *cmd_buffer,
 
 static void
 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
- struct radv_pipeline *pipeline,
  VkShaderStageFlags stages,
  struct radv_descriptor_set *set,
  unsigned idx)
 {
-   if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
-   emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
-  idx, set->va,
-  MESA_SHADER_FRAGMENT);
+   if (cmd_buffer->state.pipeline) {
+   if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
+   emit_stage_descriptor_set_userdata(cmd_buffer, 
cmd_buffer->state.pipeline,
+  idx, set->va,
+  
MESA_SHADER_FRAGMENT);
 
-   if (stages & VK_SHADER_STAGE_VERTEX_BIT)
-   emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
-  idx, set->va,
-  MESA_SHADER_VERTEX);
+   if (stages & VK_SHADER_STAGE_VERTEX_BIT)
+   emit_stage_descriptor_set_userdata(cmd_buffer, 
cmd_buffer->state.pipeline,
+  idx, set->va,
+  MESA_SHADER_VERTEX);
 
-   if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && 
radv_pipeline_has_gs(pipeline))
-   emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
-  idx, set->va,
-  MESA_SHADER_GEOMETRY);
+   if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && 
radv_pipeline_has_gs(cmd_buffer->state.pipeline))
+   emit_stage_descriptor_set_userdata(cmd_buffer, 
cmd_buffer->state.pipeline,
+  idx, set->va,
+  
MESA_SHADER_GEOMETRY);
 
-   if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && 
radv_pipeline_has_tess(pipeline))
-   emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
-  idx, set->va,
-  MESA_SHADER_TESS_CTRL);
+   if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && 
radv_pipeline_has_tess(cmd_buffer->state.pipeline))
+   emit_stage_descriptor_set_userdata(cmd_buffer, 
cmd_buffer->state.pipeline,
+  idx, set->va,
+  
MESA_SHADER_TESS_CTRL);
 
-   if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && 
radv_pipeline_has_tess(pipeline))
-   emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
-  idx, set->va,
-  MESA_SHADER_TESS_EVAL);
+   if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && 
radv_pipeline_has_tess(cmd_buffer->state.pipeline))
+   emit_stage_descriptor_set_userdata(cmd_buffer, 
cmd_buffer->state.pipeline,
+  idx, set->va,
+  
MESA_SHADER_TESS_EVAL);
+   }
 
-   if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
-   emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
+   if (cmd_buffer->state.compute_pipeline && (stages & 
VK_SHADER_STAGE_COMPUTE_BIT))
+

Mesa (17.1): anv: Advertise both 32-bit and 48-bit heaps when we have enough memory

2017-06-03 Thread Juan Antonio Suárez Romero

Module: Mesa
Branch: 17.1
Commit: f967ae7b3f6e6e685c23ac1eec658bec3a81078e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f967ae7b3f6e6e685c23ac1eec658bec3a81078e

Author: Jason Ekstrand 
Date:   Wed May 17 11:54:12 2017 -0700

anv: Advertise both 32-bit and 48-bit heaps when we have enough memory

Reviewed-by: Nanley Chery 
Cc: "17.1" 
(cherry picked from commit 50d0eb5096bd9514821a641f25c0b3455c0f8a88)
Signed-off-by: Juan A. Suarez Romero 

---

 src/intel/vulkan/anv_device.c | 42 --
 1 file changed, 36 insertions(+), 6 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 52181f1259..726ccce085 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -112,12 +112,42 @@ anv_physical_device_init_heaps(struct anv_physical_device 
*device, int fd)
if (result != VK_SUCCESS)
   return result;
 
-   device->memory.heap_count = 1;
-   device->memory.heaps[0] = (struct anv_memory_heap) {
-  .size = heap_size,
-  .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
-  .supports_48bit_addresses = device->supports_48bit_addresses,
-   };
+   if (heap_size <= 3ull * (1ull << 30)) {
+  /* In this case, everything fits nicely into the 32-bit address space,
+   * so there's no need for supporting 48bit addresses on client-allocated
+   * memory objects.
+   */
+  device->memory.heap_count = 1;
+  device->memory.heaps[0] = (struct anv_memory_heap) {
+ .size = heap_size,
+ .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
+ .supports_48bit_addresses = false,
+  };
+   } else {
+  /* Not everything will fit nicely into a 32-bit address space.  In this
+   * case we need a 64-bit heap.  Advertise a small 32-bit heap and a
+   * larger 48-bit heap.  If we're in this case, then we have a total heap
+   * size larger than 3GiB which most likely means they have 8 GiB of
+   * video memory and so carving off 1 GiB for the 32-bit heap should be
+   * reasonable.
+   */
+  const uint64_t heap_size_32bit = 1ull << 30;
+  const uint64_t heap_size_48bit = heap_size - heap_size_32bit;
+
+  assert(device->supports_48bit_addresses);
+
+  device->memory.heap_count = 2;
+  device->memory.heaps[0] = (struct anv_memory_heap) {
+ .size = heap_size_48bit,
+ .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
+ .supports_48bit_addresses = true,
+  };
+  device->memory.heaps[1] = (struct anv_memory_heap) {
+ .size = heap_size_32bit,
+ .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
+ .supports_48bit_addresses = false,
+  };
+   }
 
uint32_t type_count = 0;
for (uint32_t heap = 0; heap < device->memory.heap_count; heap++) {

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Mesa (17.1): anv: Add valid_bufer_usage to the memory type metadata

2017-06-03 Thread Juan Antonio Suárez Romero

Module: Mesa
Branch: 17.1
Commit: 0f042901e3cd451f9a7630376083a805328aebe3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f042901e3cd451f9a7630376083a805328aebe3

Author: Jason Ekstrand 
Date:   Wed May 17 11:14:06 2017 -0700

anv: Add valid_bufer_usage to the memory type metadata

Instead of returning valid types as just a number, we now walk the list
and check the buffer's usage against the usage flags we store in the new
anv_memory_type structure.  Currently, valid_buffer_usage == ~0.

Reviewed-by: Nanley Chery 
Cc: "17.1" 
(cherry picked from commit f7736ccf53eaeb66c4270afe0916e2cb29ab8667)
[Juan A. Suarez: resolve trivial conflicts]
Signed-off-by: Juan A. Suarez Romero 

Conflicts:
src/intel/vulkan/anv_device.c
src/intel/vulkan/anv_private.h

---

 src/intel/vulkan/anv_device.c  | 21 +++--
 src/intel/vulkan/anv_private.h | 13 +++--
 2 files changed, 26 insertions(+), 8 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 0add7812ab..e8ddf9faee 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -117,12 +117,13 @@ anv_physical_device_init_heaps(struct anv_physical_device 
*device, int fd)
* both cached and coherent at the same time.
*/
   device->memory.type_count = 1;
-  device->memory.types[0] = (VkMemoryType) {
+  device->memory.types[0] = (struct anv_memory_type) {
  .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
   VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
   VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
   VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
  .heapIndex = 0,
+ .valid_buffer_usage = ~0,
   };
} else {
   /* The spec requires that we expose a host-visible, coherent memory
@@ -131,17 +132,19 @@ anv_physical_device_init_heaps(struct anv_physical_device 
*device, int fd)
* coherent but uncached (WC though).
*/
   device->memory.type_count = 2;
-  device->memory.types[0] = (VkMemoryType) {
+  device->memory.types[0] = (struct anv_memory_type) {
  .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
   VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
   VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
  .heapIndex = 0,
+ .valid_buffer_usage = ~0,
   };
-  device->memory.types[1] = (VkMemoryType) {
+  device->memory.types[1] = (struct anv_memory_type) {
  .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
   VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
   VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
  .heapIndex = 0,
+ .valid_buffer_usage = ~0,
   };
}
 
@@ -1792,6 +1795,7 @@ void anv_GetBufferMemoryRequirements(
 {
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
ANV_FROM_HANDLE(anv_device, device, _device);
+   struct anv_physical_device *pdevice = >instance->physicalDevice;
 
/* The Vulkan spec (git aaed022) says:
 *
@@ -1799,13 +1803,17 @@ void anv_GetBufferMemoryRequirements(
 *supported memory type for the resource. The bit `1<memoryTypeBits = device->info.has_llc ? 1 : 3;
+   uint32_t memory_types = 0;
+   for (uint32_t i = 0; i < pdevice->memory.type_count; i++) {
+  uint32_t valid_usage = pdevice->memory.types[i].valid_buffer_usage;
+  if ((valid_usage & buffer->usage) == buffer->usage)
+ memory_types |= (1u << i);
+   }
 
pMemoryRequirements->size = buffer->size;
pMemoryRequirements->alignment = 16;
+   pMemoryRequirements->memoryTypeBits = memory_types;
 }
 
 void anv_GetImageMemoryRequirements(
@@ -1860,6 +1868,7 @@ VkResult anv_BindBufferMemory(
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 
if (mem) {
+  assert((buffer->usage & mem->type->valid_buffer_usage) == buffer->usage);
   buffer->bo = >bo;
   buffer->offset = memoryOffset;
} else {
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 21432b4c35..61f90ea1ae 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -604,6 +604,15 @@ struct anv_bo *anv_scratch_pool_alloc(struct anv_device 
*device,
   gl_shader_stage stage,
   unsigned per_thread_scratch);
 
+struct anv_memory_type {
+   /* Standard bits passed on to the client */
+   VkMemoryPropertyFlags   propertyFlags;
+   uint32_theapIndex;
+
+   /* Driver-internal book-keeping */
+

Mesa (17.1): i965: Rework Sandy Bridge HiZ and stencil layouts

2017-06-03 Thread Juan Antonio Suárez Romero

Module: Mesa
Branch: 17.1
Commit: 2c2338992224b683457a18dd3a026a7686dd1e95
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c2338992224b683457a18dd3a026a7686dd1e95

Author: Jason Ekstrand 
Date:   Sat May 27 10:36:23 2017 -0700

i965: Rework Sandy Bridge HiZ and stencil layouts

Sandy Bridge does not technically support mipmapped depth/stencil.  In
order to work around this, we allocate what are effectively completely
separate images for each miplevel, ensure that they are page-aligned,
and manually offset to them.  Prior to layered rendering, this was a
simple matter of setting a large enough halign/valign.

With the advent of layered rendering, however, things got more
complicated.  Now, things weren't as simple as just handing a surface
off to the hardware.  Any miplevel of a normally mipmapped surface can
be considered as just an array surface given the right qpitch.  However,
the hardware gives us no capability to specify qpitch so this won't
work.  Instead, the chosen solution was to use a new "all slices at each
LOD" layout which laid things out as a mipmap of arrays rather than an
array of mipmaps.  This way you can easily offset to any of the
miplevels and each is a valid array.

Unfortunately, the "all slices at each lod" concept missed one
fundamental thing about SNB HiZ and stencil hardware:  It doesn't just
always act as if you're always working with a non-mipmapped surface, it
acts as if you're always working on a non-mipmapped surface of the same
size as LOD0.  In other words, even though it may only write the
upper-left corner of each array slice, the qpitch for the array is for a
surface the size of LOD0 of the depth surface.  This mistake causes us
to under-allocate HiZ and stencil in some cases and also to accidentally
allow different miplevels to overlap.  Sadly, piglit test coverage
didn't quite catch this until I started making changes to the resolve
code that caused additional HiZ resolves in certain tests.

This commit switches Sandy Bridge HiZ and stencil over to a new scheme
that lays out the non-zero miplevels horizontally below LOD0.  This way
they can all have the same qpitch without interfering with each other.
Technically, the miplevels still overlap, but things are spaced out
enough that each page is only in the "written area" of one LOD.

Cc: "17.0 17.1" 
Reviewed-by: Topi Pohjolainen 
(cherry picked from commit 10903d228919085cdb160c563c481ed1cc09e34c)
Signed-off-by: Juan A. Suarez Romero 

---

 src/mesa/drivers/dri/i965/brw_blorp.c |  11 ++-
 src/mesa/drivers/dri/i965/brw_tex_layout.c| 100 ++
 src/mesa/drivers/dri/i965/gen6_depth_state.c  |   4 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c |  11 +--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  37 +-
 5 files changed, 134 insertions(+), 29 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index ebc4612684..423ce1f342 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -113,7 +113,7 @@ apply_gen6_stencil_hiz_offset(struct isl_surf *surf,
   uint32_t lod,
   uint32_t *offset)
 {
-   assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD);
+   assert(mt->array_layout == GEN6_HIZ_STENCIL);
 
if (mt->format == MESA_FORMAT_S_UINT8) {
   /* Note: we can't compute the stencil offset using
@@ -172,12 +172,12 @@ blorp_surf_for_miptree(struct brw_context *brw,
};
 
if (brw->gen == 6 && mt->format == MESA_FORMAT_S_UINT8 &&
-   mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
-  /* Sandy bridge stencil and HiZ use this ALL_SLICES_AT_EACH_LOD hack in
+   mt->array_layout == GEN6_HIZ_STENCIL) {
+  /* Sandy bridge stencil and HiZ use this GEN6_HIZ_STENCIL hack in
* order to allow for layered rendering.  The hack makes each LOD of the
* stencil or HiZ buffer a single tightly packed array surface at some
* offset into the surface.  Since ISL doesn't know how to deal with the
-   * crazy ALL_SLICES_AT_EACH_LOD layout and since we have to do a manual
+   * crazy GEN6_HIZ_STENCIL layout and since we have to do a manual
* offset of it anyway, we might as well do the offset here and keep the
* hacks inside the i965 driver.
*
@@ -251,8 +251,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
 
  struct intel_mipmap_tree *hiz_mt = mt->hiz_buf->mt;
  if (hiz_mt) {
-assert(brw->gen == 6 &&
-   hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD);
+assert(brw->gen == 6 && hiz_mt->array_layout == GEN6_HIZ_STENCIL);
 
 /* gen6 requires the HiZ buffer to be manually offset to the
  * right location.  We could fixup the surf but it doesn't
diff --git

Mesa (17.1): anv: Stop setting BO flags in bo_init_new

2017-06-03 Thread Juan Antonio Suárez Romero

Module: Mesa
Branch: 17.1
Commit: 86a8854b118fd42d157a5b640fa7a3a1cad92301
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=86a8854b118fd42d157a5b640fa7a3a1cad92301

Author: Jason Ekstrand 
Date:   Wed May 17 11:31:02 2017 -0700

anv: Stop setting BO flags in bo_init_new

The idea behind doing this was to make it easier to set various flags.
However, we have enough custom flag settings floating around the driver
that this is more of a nuisance than a help.  This commit has the
following functional changes:

 1) The workaround_bo created in anv_CreateDevice loses both flags.
This shouldn't matter because it's very small and entirely internal
to the driver.

 2) The bo created in anv_CreateDmaBufImageINTEL loses the
EXEC_OBJECT_ASYNC flag.  In retrospect, it never should have gotten
EXEC_OBJECT_ASYNC in the first place.

Reviewed-by: Nanley Chery 
Cc: "17.1" 
(cherry picked from commit 00df1cd9d6234cdfc9fb2bf3615196ff83a3c956)
[Juan A. Suarez: resolve trivial conflicts]
Signed-off-by: Juan A. Suarez Romero 

Conflicts:
src/intel/vulkan/anv_allocator.c
src/intel/vulkan/anv_device.c
src/intel/vulkan/anv_queue.c

---

 src/intel/vulkan/anv_allocator.c | 11 ++-
 src/intel/vulkan/anv_device.c| 12 ++--
 src/intel/vulkan/genX_query.c|  7 +++
 3 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index b1efd324f5..ab825cdbc3 100644
--- a/src/intel/vulkan/anv_allocator.c
+++ b/src/intel/vulkan/anv_allocator.c
@@ -884,6 +884,12 @@ anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo 
*bo, uint32_t size)
if (result != VK_SUCCESS)
   return result;
 
+   if (pool->device->instance->physicalDevice.supports_48bit_addresses)
+  new_bo.flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+
+   if (pool->device->instance->physicalDevice.has_exec_async)
+  new_bo.flags |= EXEC_OBJECT_ASYNC;
+
assert(new_bo.size == pow2_size);
 
new_bo.map = anv_gem_mmap(pool->device, new_bo.gem_handle, 0, pow2_size, 0);
@@ -1013,7 +1019,10 @@ anv_scratch_pool_alloc(struct anv_device *device, struct 
anv_scratch_pool *pool,
 *
 * so nothing will ever touch the top page.
 */
-   bo->bo.flags &= ~EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+   assert(!(bo->bo.flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS));
+
+   if (device->instance->physicalDevice.has_exec_async)
+  bo->bo.flags |= EXEC_OBJECT_ASYNC;
 
/* Set the exists last because it may be read by other threads */
__sync_synchronize();
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index e8ddf9faee..b07def9628 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1562,12 +1562,6 @@ anv_bo_init_new(struct anv_bo *bo, struct anv_device 
*device, uint64_t size)
 
anv_bo_init(bo, gem_handle, size);
 
-   if (device->instance->physicalDevice.supports_48bit_addresses)
-  bo->flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
-
-   if (device->instance->physicalDevice.has_exec_async)
-  bo->flags |= EXEC_OBJECT_ASYNC;
-
return VK_SUCCESS;
 }
 
@@ -1627,6 +1621,12 @@ VkResult anv_AllocateMemory(
mem->map = NULL;
mem->map_size = 0;
 
+   if (pdevice->supports_48bit_addresses)
+  mem->bo.flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+
+   if (pdevice->has_exec_async)
+  mem->bo.flags |= EXEC_OBJECT_ASYNC;
+
*pMem = anv_device_memory_to_handle(mem);
 
return VK_SUCCESS;
diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c
index 2c70b4f528..d5052b7f2e 100644
--- a/src/intel/vulkan/genX_query.c
+++ b/src/intel/vulkan/genX_query.c
@@ -39,6 +39,7 @@ VkResult genX(CreateQueryPool)(
 VkQueryPool*pQueryPool)
 {
ANV_FROM_HANDLE(anv_device, device, _device);
+   const struct anv_physical_device *pdevice = 
>instance->physicalDevice;
struct anv_query_pool *pool;
VkResult result;
 
@@ -90,6 +91,12 @@ VkResult genX(CreateQueryPool)(
if (result != VK_SUCCESS)
   goto fail;
 
+   if (pdevice->supports_48bit_addresses)
+  pool->bo.flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+
+   if (pdevice->has_exec_async)
+  pool->bo.flags |= EXEC_OBJECT_ASYNC;
+
/* For query pools, we set the caching mode to I915_CACHING_CACHED.  On LLC
 * platforms, this does nothing.  On non-LLC platforms, this means snooping
 * which comes at a slight cost.  However, the buffers aren't big, won't be

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Mesa (17.1): Revert "cherry-ignore: anv: [...]"

2017-06-03 Thread Juan Antonio Suárez Romero

Module: Mesa
Branch: 17.1
Commit: b7b3c0fce76a8b5fa61b6b5ce4b8ebb38c1d9e6e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7b3c0fce76a8b5fa61b6b5ce4b8ebb38c1d9e6e

Author: Juan A. Suarez Romero 
Date:   Fri Jun  2 10:33:41 2017 +

Revert "cherry-ignore: anv: [...]"

Revert "cherry-ignore: anv: Refactor memory type setup"
This reverts commit eab4a503a0b04dfe1fdcfc2dcde62eb09c038aca.

Revert "cherry-ignore: anv: Add valid_bufer_usage to the memory type metadata"
This reverts commit c31e814a85a27249e2a57cb7350240c01a1cad58.

Revert "cherry-ignore: anv: Advertise both 32-bit and 48-bit heaps when we have 
enough memory"
This reverts commit e391144853640ee39fca8dfe0e9387bbf1d90a76.

Revert "cherry-ignore: anv: Make supports_48bit_addresses a heap property"
This reverts commit dbadd066321786ea9b8f0259413740a10f753f36.

Revert "cherry-ignore: anv: Stop setting BO flags in bo_init_new"
This reverts commit 07867f72cf53209d230b3fb13f24f9371ab9d4b4.

Revert "cherry-ignore: anv: Determine the type of mapping based on type 
metadata"
This reverts commit 9299466b83ce88c911b30b35d9f4f6addb25c92a.

---

 bin/.cherry-ignore | 12 +---
 1 file changed, 1 insertion(+), 11 deletions(-)

diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index 88277a69ac..209c0ec92e 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -1,16 +1,6 @@
 # This commit depends on 9fd9a7d0ba3 and 678d568c7b2, neither of which is in 
branch.
 b84b631c6381d9b36bca5d0e7cc67dd23af188c1 radeonsi: load patch_id for TES-as-ES 
when exporting for PS
-# This commit depends on commit c3c61d210f which did not land in branch.
-92325a7efc769c32e03031323e21700dc55171e4 anv: Determine the type of mapping 
based on type metadata
-# This commit depends on commit 35e626bd0e which did not land in branch.
-00df1cd9d6234cdfc9fb2bf3615196ff83a3c956 anv: Stop setting BO flags in 
bo_init_new
-# This commit depends on commit 00df1cd9d6 which did not land in branch.
-b83b1af6f6936f36db42a8f8b8e0854d0f9491fd anv: Make supports_48bit_addresses a 
heap property
-# These commits depend on commit b83b1af6f6 which did not land in branch.
-50d0eb5096bd9514821a641f25c0b3455c0f8a88 anv: Advertise both 32-bit and 48-bit 
heaps when we have enough memory
+# This commit causes regressions in the crucible testsuite
 39adea9330376a64a4b5e8da98f5e055ebd3331e anv: Require vertex buffers to come 
from a 32-bit heap
 # This commit addressed an earlier commit 126d5ad which did not land in branch.
 9da104593386f6e8ddec8f0d9d288aceb8908fe1 radv: fix regression in descriptor 
set freeing.
-# These commits depend on commit 9da1045933 which did not land in branch.
-f7736ccf53eaeb66c4270afe0916e2cb29ab8667 anv: Add valid_bufer_usage to the 
memory type metadata
-34581fdd4f149894dfa51777a2f7eb289bd08b71 anv: Refactor memory type setup

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Mesa (17.1): anv: Make supports_48bit_addresses a heap property

2017-06-03 Thread Juan Antonio Suárez Romero

Module: Mesa
Branch: 17.1
Commit: 2562b3252b63f2e938d6e6614e1f9a2fa2064140
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2562b3252b63f2e938d6e6614e1f9a2fa2064140

Author: Jason Ekstrand 
Date:   Wed May 17 11:38:16 2017 -0700

anv: Make supports_48bit_addresses a heap property

Reviewed-by: Nanley Chery 
Cc: "17.1" 
(cherry picked from commit b83b1af6f6936f36db42a8f8b8e0854d0f9491fd)
[Juan A. Suarez: resolve trivial conflicts]
Signed-off-by: Juan A. Suarez Romero 

Conflicts:
src/intel/vulkan/anv_device.c

---

 src/intel/vulkan/anv_device.c  |  6 --
 src/intel/vulkan/anv_private.h | 11 ++-
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index b07def9628..95a29ab72d 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -149,9 +149,10 @@ anv_physical_device_init_heaps(struct anv_physical_device 
*device, int fd)
}
 
device->memory.heap_count = 1;
-   device->memory.heaps[0] = (VkMemoryHeap) {
+   device->memory.heaps[0] = (struct anv_memory_heap) {
   .size = heap_size,
   .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
+  .supports_48bit_addresses = device->supports_48bit_addresses,
};
 
return VK_SUCCESS;
@@ -1621,7 +1622,8 @@ VkResult anv_AllocateMemory(
mem->map = NULL;
mem->map_size = 0;
 
-   if (pdevice->supports_48bit_addresses)
+   assert(mem->type->heapIndex < pdevice->memory.heap_count);
+   if (pdevice->memory.heaps[mem->type->heapIndex].supports_48bit_addresses)
   mem->bo.flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
 
if (pdevice->has_exec_async)
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 61f90ea1ae..ad82c77ec1 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -613,6 +613,15 @@ struct anv_memory_type {
VkBufferUsageFlags  valid_buffer_usage;
 };
 
+struct anv_memory_heap {
+   /* Standard bits passed on to the client */
+   VkDeviceSize  size;
+   VkMemoryHeapFlags flags;
+
+   /* Driver-internal book-keeping */
+   bool  supports_48bit_addresses;
+};
+
 struct anv_physical_device {
 VK_LOADER_DATA  _loader_data;
 
@@ -644,7 +653,7 @@ struct anv_physical_device {
   uint32_t  type_count;
   struct anv_memory_typetypes[VK_MAX_MEMORY_TYPES];
   uint32_t  heap_count;
-  VkMemoryHeap  heaps[VK_MAX_MEMORY_HEAPS];
+  struct anv_memory_heapheaps[VK_MAX_MEMORY_HEAPS];
 } memory;
 
 uint8_t 
pipeline_cache_uuid[VK_UUID_SIZE];

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Mesa (17.1): anv: Set EXEC_OBJECT_ASYNC when available

2017-06-03 Thread Juan Antonio Suárez Romero

Module: Mesa
Branch: 17.1
Commit: 0aa1e6acdefd25128e26e13b33384b862a87aee9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0aa1e6acdefd25128e26e13b33384b862a87aee9

Author: Jason Ekstrand 
Date:   Thu Apr 13 16:30:19 2017 -0700

anv: Set EXEC_OBJECT_ASYNC when available

Reviewed-by: Chad Versace 
(cherry picked from commit 35e626bd0e59e7ce9fd97ccef66b2468c09206a4)
Signed-off-by: Juan A. Suarez Romero 

Squashed with:

anv/tests: Create a dummy instance as well as device

This fixes crashes caused by 35e626bd0e59e7ce9fd97ccef66b2468c09206a4
which made us start referencing the instance in the allocators.  With
this commit, the tests now happily pass again.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100877
Tested-by: Vinson Lee 
(cherry picked from commit 6ef1bd4fa57b36efc7919773fd26c36fd43d2ea9)
Signed-off-by: Juan A. Suarez Romero 

---

 src/intel/vulkan/anv_allocator.c   | 3 +++
 src/intel/vulkan/anv_device.c  | 5 +
 src/intel/vulkan/anv_private.h | 1 +
 src/intel/vulkan/anv_wsi.c | 1 +
 src/intel/vulkan/tests/block_pool_no_free.c| 5 -
 src/intel/vulkan/tests/state_pool.c| 5 -
 src/intel/vulkan/tests/state_pool_free_list_only.c | 5 -
 src/intel/vulkan/tests/state_pool_no_free.c| 5 -
 8 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index f3e83bc679..b1efd324f5 100644
--- a/src/intel/vulkan/anv_allocator.c
+++ b/src/intel/vulkan/anv_allocator.c
@@ -504,6 +504,9 @@ anv_block_pool_grow(struct anv_block_pool *pool, struct 
anv_block_state *state)
anv_bo_init(>bo, gem_handle, size);
pool->bo.map = map;
 
+   if (pool->device->instance->physicalDevice.has_exec_async)
+  pool->bo.flags |= EXEC_OBJECT_ASYNC;
+
 done:
pthread_mutex_unlock(>device->mutex);
 
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 7ad14b59f9..d22da8be0b 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -257,6 +257,8 @@ anv_physical_device_init(struct anv_physical_device *device,
if (result != VK_SUCCESS)
   goto fail;
 
+   device->has_exec_async = anv_gem_get_param(fd, I915_PARAM_HAS_EXEC_ASYNC);
+
if (!anv_device_get_cache_uuid(device->uuid, device->chipset_id)) {
   result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
  "cannot generate UUID");
@@ -1560,6 +1562,9 @@ anv_bo_init_new(struct anv_bo *bo, struct anv_device 
*device, uint64_t size)
if (device->instance->physicalDevice.supports_48bit_addresses)
   bo->flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
 
+   if (device->instance->physicalDevice.has_exec_async)
+  bo->flags |= EXEC_OBJECT_ASYNC;
+
return VK_SUCCESS;
 }
 
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 57b39a72af..599badedfd 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -624,6 +624,7 @@ struct anv_physical_device {
 struct brw_compiler *   compiler;
 struct isl_device   isl_dev;
 int cmd_parser_version;
+boolhas_exec_async;
 
 uint32_teu_total;
 uint32_tsubslice_total;
diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c
index ba66ea6d46..a024561c94 100644
--- a/src/intel/vulkan/anv_wsi.c
+++ b/src/intel/vulkan/anv_wsi.c
@@ -208,6 +208,7 @@ x11_anv_wsi_image_create(VkDevice device_h,
 * know we're writing to them and synchronize uses on other rings (eg if
 * the display server uses the blitter ring).
 */
+   memory->bo.flags &= ~EXEC_OBJECT_ASYNC;
memory->bo.flags |= EXEC_OBJECT_WRITE;
 
anv_BindImageMemory(device_h, image_h, memory_h, 0);
diff --git a/src/intel/vulkan/tests/block_pool_no_free.c 
b/src/intel/vulkan/tests/block_pool_no_free.c
index 86d1a76151..0a61818e42 100644
--- a/src/intel/vulkan/tests/block_pool_no_free.c
+++ b/src/intel/vulkan/tests/block_pool_no_free.c
@@ -107,7 +107,10 @@ static void validate_monotonic(uint32_t **blocks)
 
 static void run_test()
 {
-   struct anv_device device;
+   struct anv_instance instance;
+   struct anv_device device = {
+  .instance = ,
+   };
struct anv_block_pool pool;
 
pthread_mutex_init(, NULL);
diff --git a/src/intel/vulkan/tests/state_pool.c 
b/src/intel/vulkan/tests/state_pool.c
index 878ec19a59..90c9bdea51 100644
--- a/src/intel/vulkan/tests/state_pool.c
+++ b/src/intel/vulkan/tests/state_pool.c
@@ -34,7 +34,10 @@
 
 int main(int argc, char **argv)
 {
-   struct anv_device device;
+   struct anv_instance instance;
+   struct anv_device device = {
+

Mesa (17.1): anv: Determine the type of mapping based on type metadata

2017-06-03 Thread Juan Antonio Suárez Romero

Module: Mesa
Branch: 17.1
Commit: 15bc6d4d210eee051407a816811012eba0a3be3b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=15bc6d4d210eee051407a816811012eba0a3be3b

Author: Jason Ekstrand 
Date:   Wed May 17 11:13:01 2017 -0700

anv: Determine the type of mapping based on type metadata

Before, we were just comparing the type index to 0.  Now we actually
look the type up in the table and check its properties to determine what
kind of mapping we want to do.

Reviewed-by: Nanley Chery 
Cc: "17.1" 
(cherry picked from commit 92325a7efc769c32e03031323e21700dc55171e4)
[Juan A. Suarez: resolve trivial conflicts]
Signed-off-by: Juan A. Suarez Romero 

Conflicts:
src/intel/vulkan/anv_device.c
src/intel/vulkan/anv_private.h

---

 src/intel/vulkan/anv_device.c  | 12 ++--
 src/intel/vulkan/anv_private.h |  2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index d22da8be0b..0add7812ab 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1575,6 +1575,7 @@ VkResult anv_AllocateMemory(
 VkDeviceMemory* pMem)
 {
ANV_FROM_HANDLE(anv_device, device, _device);
+   struct anv_physical_device *pdevice = >instance->physicalDevice;
struct anv_device_memory *mem;
VkResult result;
 
@@ -1583,10 +1584,6 @@ VkResult anv_AllocateMemory(
/* The Vulkan 1.0.33 spec says "allocationSize must be greater than 0". */
assert(pAllocateInfo->allocationSize > 0);
 
-   /* We support exactly one memory heap. */
-   assert(pAllocateInfo->memoryTypeIndex == 0 ||
-  (!device->info.has_llc && pAllocateInfo->memoryTypeIndex < 2));
-
/* The kernel relocation API has a limitation of a 32-bit delta value
 * applied to the address before it is written which, in spite of it being
 * unsigned, is treated as signed .  Because of the way that this maps to
@@ -1621,7 +1618,8 @@ VkResult anv_AllocateMemory(
if (result != VK_SUCCESS)
   goto fail;
 
-   mem->type_index = pAllocateInfo->memoryTypeIndex;
+   assert(pAllocateInfo->memoryTypeIndex < pdevice->memory.type_count);
+   mem->type = >memory.types[pAllocateInfo->memoryTypeIndex];
 
mem->map = NULL;
mem->map_size = 0;
@@ -1695,7 +1693,9 @@ VkResult anv_MapMemory(
 * userspace. */
 
uint32_t gem_flags = 0;
-   if (!device->info.has_llc && mem->type_index == 0)
+
+   if (!device->info.has_llc &&
+   (mem->type->propertyFlags & VK_MEMORY_PROPERTY_HOST_COHERENT_BIT))
   gem_flags |= I915_MMAP_WC;
 
/* GEM will fail to map if the offset isn't 4k-aligned.  Round down. */
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 599badedfd..21432b4c35 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -971,7 +971,7 @@ _anv_combine_address(struct anv_batch *batch, void 
*location,
 
 struct anv_device_memory {
struct anv_bobo;
-   uint32_t type_index;
+   VkMemoryType *   type;
VkDeviceSize map_size;
void *   map;
 };

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Mesa (master): i965: Order write of query availablity with earlier writes

2017-06-03 Thread Chris Wilson

Module: Mesa
Branch: master
Commit: 8d07cb125c6afc11b6b8c7a97ec848868814b1d6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d07cb125c6afc11b6b8c7a97ec848868814b1d6

Author: Chris Wilson 
Date:   Thu Oct  6 21:07:18 2016 +0100

i965: Order write of query availablity with earlier writes

Currently we signal the availabilty of the query result using an
unordered pipe-control write. As it is unordered, it may be executed
before the write of the query result itself - and so an observer may
read the query result too early. Fix this by requesting that the write
of the availablity flag is ordered after earlier pipe control writes.

Testcase: piglit/arb_query_buffer_object-qbo/*async*
Signed-off-by: Chris Wilson 
Reviewed-by: Alejandro Piñeiro 

---

 src/mesa/drivers/dri/i965/gen6_queryobj.c | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c 
b/src/mesa/drivers/dri/i965/gen6_queryobj.c
index cb4f46c28b..a28f83af1d 100644
--- a/src/mesa/drivers/dri/i965/gen6_queryobj.c
+++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c
@@ -60,8 +60,17 @@ set_query_availability(struct brw_context *brw, struct 
brw_query_object *query,
 */
if (brw->ctx.Extensions.ARB_query_buffer_object &&
brw_is_query_pipelined(query)) {
-  brw_emit_pipe_control_write(brw,
-  PIPE_CONTROL_WRITE_IMMEDIATE,
+  unsigned flags = PIPE_CONTROL_WRITE_IMMEDIATE;
+
+  if (available) {
+ /* Order available *after* the query results. */
+ flags |= PIPE_CONTROL_FLUSH_ENABLE;
+  } else {
+ /* Make it unavailable *before* any pipelined reads. */
+ flags |= PIPE_CONTROL_CS_STALL;
+  }
+
+  brw_emit_pipe_control_write(brw, flags,
   query->bo, 2 * sizeof(uint64_t),
   available, 0);
}

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Mesa (master): radv: Dirty all descriptors sets when changing the pipeline.

Mesa (master): radv: Set both compute and graphics SGPRS on descriptor set flush.

Mesa (17.1): anv: Advertise both 32-bit and 48-bit heaps when we have enough memory

Mesa (17.1): anv: Add valid_bufer_usage to the memory type metadata

Mesa (17.1): i965: Rework Sandy Bridge HiZ and stencil layouts

Mesa (17.1): anv: Stop setting BO flags in bo_init_new

Mesa (17.1): Revert "cherry-ignore: anv: [...]"

Mesa (17.1): anv: Make supports_48bit_addresses a heap property

Mesa (17.1): anv: Set EXEC_OBJECT_ASYNC when available

Mesa (17.1): anv: Determine the type of mapping based on type metadata

Mesa (master): i965: Order write of query availablity with earlier writes

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