Mesa (master): svga: fix texture swizzle writemasking

[Brian Paul]

Module: Mesa
Branch: master
Commit: f7e78abdf45b26f3991dc336120162ae01b208f1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7e78abdf45b26f3991dc336120162ae01b208f1

Author: Brian Paul 
Date:   Tue Jul 11 14:56:00 2017 -0600

svga: fix texture swizzle writemasking

Commit bfe1e7737a76e3b046 changed how texture swizzles are set up.
This exposed a latent bug in the VMware driver: we were ignoring
the texture instruction's writemask when applying the 0 and 1
swizzle terms.

This wasn't caught by the Piglit texture swizzle test because it
only exercises fixed function (no write masking).

Fixes issues seen with ETQW apitrace.

CC: 
Reviewed-by: Charmaine Lee 

---

 src/gallium/drivers/svga/svga_tgsi_vgpu10.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c 
b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
index d29ac28240..96269cb872 100644
--- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
+++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
@@ -5047,6 +5047,7 @@ end_tex_swizzle(struct svga_shader_emitter_v10 *emit,
  ((swz_g == PIPE_SWIZZLE_0) << 1) |
  ((swz_b == PIPE_SWIZZLE_0) << 2) |
  ((swz_a == PIPE_SWIZZLE_0) << 3));
+  writemask_0 &= swz->inst_dst->Register.WriteMask;
 
   if (writemask_0) {
  struct tgsi_full_src_register zero = int_tex ?
@@ -5065,6 +5066,7 @@ end_tex_swizzle(struct svga_shader_emitter_v10 *emit,
  ((swz_g == PIPE_SWIZZLE_1) << 1) |
  ((swz_b == PIPE_SWIZZLE_1) << 2) |
  ((swz_a == PIPE_SWIZZLE_1) << 3));
+  writemask_1 &= swz->inst_dst->Register.WriteMask;
 
   if (writemask_1) {
  struct tgsi_full_src_register one = int_tex ?

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Mesa (master): i965: Use VALGRIND_MAKE_MEM_x in place of MALLOCLIKE/ FREELIKE

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: cead51a0c63df1613f9f6400657597679126024c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cead51a0c63df1613f9f6400657597679126024c

Author: Chris Wilson 
Date:   Tue Jul 11 16:54:25 2017 +0100

i965: Use VALGRIND_MAKE_MEM_x in place of MALLOCLIKE/FREELIKE

Valgrind doesn't actually implement VALGRIND_FREELIKE_BLOCK as the
exact inverse of VALGRIND_MALLOCLIKE_BLOCK. It makes the block
inaccessible, but still leaves it defined in its allocation tracker i.e.
it will report the mmap as lost despite the call to FREELIKE!

Instead of treating the mmap as an allocation, treat it as changing the
access bits upon the memory, i.e. that it becomes defined (because of
the buffer objects always contain valid content from the user's
perspective) upon mmap and inaccessible upon munmap. This makes memcheck
happy without leaving it thinking there is a very large leak.

Finally for consistency, we treat all the mmap/munmap paths the same
even though valgrind can intercept the regular mmap used for GTT. We
could move this in the drm_mmap/drm_munmap macros, but that quickly
looks ugly given the desire for those to support different OSes, but I
didn't try that hard!

Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_bufmgr.c | 34 +++---
 1 file changed, 27 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 26f194e192..98a75dd4a6 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -78,6 +78,16 @@
 #define VG(x)
 #endif
 
+/* VALGRIND_FREELIKE_BLOCK unfortunately does not actually undo the earlier
+ * VALGRIND_MALLOCLIKE_BLOCK but instead leaves vg convinced the memory is
+ * leaked. All because it does not call VG(cli_free) from its
+ * VG_USERREQ__FREELIKE_BLOCK handler. Instead of treating the memory like
+ * and allocation, we mark it available for use upon mmapping and remove
+ * it upon unmapping.
+ */
+#define VG_DEFINED(ptr, size) VG(VALGRIND_MAKE_MEM_DEFINED(ptr, size))
+#define VG_NOACCESS(ptr, size) VG(VALGRIND_MAKE_MEM_NOACCESS(ptr, size))
+
 #define memclear(s) memset(, 0, sizeof(s))
 
 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
@@ -519,14 +529,15 @@ bo_free(struct brw_bo *bo)
int ret;
 
if (bo->map_cpu) {
-  VG(VALGRIND_FREELIKE_BLOCK(bo->map_cpu, 0));
+  VG_NOACCESS(bo->map_cpu, bo->size);
   drm_munmap(bo->map_cpu, bo->size);
}
if (bo->map_wc) {
-  VG(VALGRIND_FREELIKE_BLOCK(bo->map_wc, 0));
+  VG_NOACCESS(bo->map_wc, bo->size);
   drm_munmap(bo->map_wc, bo->size);
}
if (bo->map_gtt) {
+  VG_NOACCESS(bo->map_gtt, bo->size);
   drm_munmap(bo->map_gtt, bo->size);
}
 
@@ -692,14 +703,16 @@ brw_bo_map_cpu(struct brw_context *brw, struct brw_bo 
*bo, unsigned flags)
  __FILE__, __LINE__, bo->gem_handle, bo->name, strerror(errno));
  return NULL;
   }
-  VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
   map = (void *) (uintptr_t) mmap_arg.addr_ptr;
+  VG_DEFINED(map, bo->size);
 
   if (p_atomic_cmpxchg(>map_cpu, NULL, map)) {
- VG(VALGRIND_FREELIKE_BLOCK(map, 0));
+ VG_NOACCESS(map, bo->size);
  drm_munmap(map, bo->size);
   }
}
+   assert(bo->map_cpu);
+
DBG("brw_bo_map_cpu: %d (%s) -> %p, ", bo->gem_handle, bo->name,
bo->map_cpu);
print_flags(flags);
@@ -750,9 +763,7 @@ brw_bo_map_gtt(struct brw_context *brw, struct brw_bo *bo, 
unsigned flags)
  return NULL;
   }
 
-  /* and mmap it.  We don't need to use VALGRIND_MALLOCLIKE_BLOCK
-   * because Valgrind will already intercept this mmap call.
-   */
+  /* and mmap it. */
   map = drm_mmap(0, bo->size, PROT_READ | PROT_WRITE,
  MAP_SHARED, bufmgr->fd, mmap_arg.offset);
   if (map == MAP_FAILED) {
@@ -761,10 +772,19 @@ brw_bo_map_gtt(struct brw_context *brw, struct brw_bo 
*bo, unsigned flags)
  return NULL;
   }
 
+  /* We don't need to use VALGRIND_MALLOCLIKE_BLOCK because Valgrind will
+   * already intercept this mmap call. However, for consistency between
+   * all the mmap paths, we mark the pointer as defined now and mark it
+   * as inaccessible afterwards.
+   */
+  VG_DEFINED(map, bo->size);
+
   if (p_atomic_cmpxchg(>map_gtt, NULL, map)) {
+ VG_NOACCESS(map, bo->size);
  drm_munmap(map, bo->size);
   }
}
+   assert(bo->map_gtt);
 
DBG("bo_map_gtt: %d (%s) -> %p, ", bo->gem_handle, bo->name, bo->map_gtt);
print_flags(flags);

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Mesa (master): i965: Don't use PREAD for glGetBufferSubData().

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 20104f1926436e00171c8e64ca37fff9ffbd7096
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=20104f1926436e00171c8e64ca37fff9ffbd7096

Author: Kenneth Graunke 
Date:   Sat Jul  1 11:33:35 2017 -0700

i965: Don't use PREAD for glGetBufferSubData().

Just map the buffer and memcpy.  This will do a CPU mmap, which should
be reasonably efficient, and doing this gives us full control over the
domains and caching instead of leaving it to the kernel.

This prevents regressions on Braswell in the next commit.  Specifically
GL45-CTS.shader_atomic_counters.basic-buffer-operations.  Because async
maps start skipping set-domain, the pread thought everything was nicely
still in the CPU domain, and returned stale data.

v2: Use _mesa_error_no_memory() if the map fails instead of crashing.

Reviewed-by: Chris Wilson 

---

 src/mesa/drivers/dri/i965/brw_bufmgr.c   | 24 
 src/mesa/drivers/dri/i965/brw_bufmgr.h   |  3 ---
 src/mesa/drivers/dri/i965/intel_buffer_objects.c | 11 ++-
 3 files changed, 10 insertions(+), 28 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 11251f15ed..30e4b28b9e 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -820,30 +820,6 @@ brw_bo_subdata(struct brw_bo *bo, uint64_t offset,
return ret;
 }
 
-int
-brw_bo_get_subdata(struct brw_bo *bo, uint64_t offset,
-   uint64_t size, void *data)
-{
-   struct brw_bufmgr *bufmgr = bo->bufmgr;
-   struct drm_i915_gem_pread pread;
-   int ret;
-
-   memclear(pread);
-   pread.handle = bo->gem_handle;
-   pread.offset = offset;
-   pread.size = size;
-   pread.data_ptr = (uint64_t) (uintptr_t) data;
-   ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_PREAD, );
-   if (ret != 0) {
-  ret = -errno;
-  DBG("%s:%d: Error reading data from buffer %d: "
-  "(%"PRIu64" %"PRIu64") %s .\n",
-  __FILE__, __LINE__, bo->gem_handle, offset, size, strerror(errno));
-   }
-
-   return ret;
-}
-
 /** Waits for all GPU rendering with the object to have completed. */
 void
 brw_bo_wait_rendering(struct brw_bo *bo)
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index d388e5ad15..01a540f531 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -222,9 +222,6 @@ static inline int brw_bo_unmap(struct brw_bo *bo) { return 
0; }
 /** Write data into an object. */
 int brw_bo_subdata(struct brw_bo *bo, uint64_t offset,
uint64_t size, const void *data);
-/** Read data from an object. */
-int brw_bo_get_subdata(struct brw_bo *bo, uint64_t offset,
-   uint64_t size, void *data);
 /**
  * Waits for rendering to an object by the GPU to have completed.
  *
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c 
b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index a9ac29a6a8..85cc1a694b 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -289,7 +289,16 @@ brw_get_buffer_subdata(struct gl_context *ctx,
if (brw_batch_references(>batch, intel_obj->buffer)) {
   intel_batchbuffer_flush(brw);
}
-   brw_bo_get_subdata(intel_obj->buffer, offset, size, data);
+
+   void *map = brw_bo_map(brw, intel_obj->buffer, MAP_READ);
+
+   if (unlikely(!map)) {
+  _mesa_error_no_memory(__func__);
+  return;
+   }
+
+   memcpy(data, map + offset, size);
+   brw_bo_unmap(intel_obj->buffer);
 
mark_buffer_inactive(intel_obj);
 }

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Mesa (master): i965: Fix asynchronous mappings on !LLC platforms.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 314879f7fec07cedb5263681173a22d522a8ac9a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=314879f7fec07cedb5263681173a22d522a8ac9a

Author: Kenneth Graunke 
Date:   Sat Jul  1 01:55:55 2017 -0700

i965: Fix asynchronous mappings on !LLC platforms.

When using a read-only CPU mapping, we may encounter stale buffer
contents.  For example, the Piglit primitive-restart test offers the
following scenario:

   1. Read data via a CPU map.
   2. Destroy that buffer.
   3. Create a new buffer - obtaining the same one via the BO cache.
   4. Call BufferSubData, which does a GTT map with MAP_WRITE | MAP_ASYNC.
  (We avoid set_domain for async mappings, so no flushing occurs.)
   5. Read data via a CPU map.
  (Without explicit clflushing, this will contain data from step 1!)

Otherwise, everything ought to work, keeping in mind that we never use
CPU maps for writing - just read-only CPU maps.

This restores the performance gains after Matt's revert in commit
71651b3139c501f50e6547c21a1cdb816b0a9dde.

v2: Do the invalidate later, and even when asking for a brand new map.
v3: Add more comments from Chris.

Reviewed-by: Chris Wilson 

---

 src/mesa/drivers/dri/i965/brw_bufmgr.c | 19 +--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 30e4b28b9e..26f194e192 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -56,6 +56,7 @@
 #ifndef ETIME
 #define ETIME ETIMEDOUT
 #endif
+#include "common/gen_clflush.h"
 #include "common/gen_debug.h"
 #include "common/gen_device_info.h"
 #include "libdrm_macros.h"
@@ -703,11 +704,25 @@ brw_bo_map_cpu(struct brw_context *brw, struct brw_bo 
*bo, unsigned flags)
bo->map_cpu);
print_flags(flags);
 
-   if (!(flags & MAP_ASYNC) || !bufmgr->has_llc) {
+   if (!(flags & MAP_ASYNC)) {
   set_domain(brw, "CPU mapping", bo, I915_GEM_DOMAIN_CPU,
  flags & MAP_WRITE ? I915_GEM_DOMAIN_CPU : 0);
}
 
+   if (!bo->cache_coherent) {
+  /* If we're reusing an existing CPU mapping, the CPU caches may
+   * contain stale data from the last time we read from that mapping.
+   * (With the BO cache, it might even be data from a previous buffer!)
+   * Even if it's a brand new mapping, the kernel may have zeroed the
+   * buffer via CPU writes.
+   *
+   * We need to invalidate those cachelines so that we see the latest
+   * contents, and so long as we only read from the CPU mmap we do not
+   * need to write those cachelines back afterwards.
+   */
+  gen_invalidate_range(bo->map_cpu, bo->size);
+   }
+
return bo->map_cpu;
 }
 
@@ -754,7 +769,7 @@ brw_bo_map_gtt(struct brw_context *brw, struct brw_bo *bo, 
unsigned flags)
DBG("bo_map_gtt: %d (%s) -> %p, ", bo->gem_handle, bo->name, bo->map_gtt);
print_flags(flags);
 
-   if (!(flags & MAP_ASYNC) || !bufmgr->has_llc) {
+   if (!(flags & MAP_ASYNC)) {
   set_domain(brw, "GTT mapping", bo,
  I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
}

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Mesa (master): swr/rast: make SWR_VISIBLE attribute work for windows

[Tim Rowley]

Module: Mesa
Branch: master
Commit: 27c5568de3674ec95f02816a06b13180bad0838b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=27c5568de3674ec95f02816a06b13180bad0838b

Author: George Kyriazis 
Date:   Tue Jul 11 08:13:49 2017 -0600

swr/rast: make SWR_VISIBLE attribute work for windows

Needed to expose SwrGetInterface

Reviewed-by: Bruce Cherniak 

---

 src/gallium/drivers/swr/rasterizer/common/os.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/swr/rasterizer/common/os.h 
b/src/gallium/drivers/swr/rasterizer/common/os.h
index 8657709405..a16f5779d8 100644
--- a/src/gallium/drivers/swr/rasterizer/common/os.h
+++ b/src/gallium/drivers/swr/rasterizer/common/os.h
@@ -30,7 +30,7 @@
 #if (defined(FORCE_WINDOWS) || defined(_WIN32)) && !defined(FORCE_LINUX)
 
 #define SWR_API __cdecl
-#define SWR_VISIBLE
+#define SWR_VISIBLE  __declspec(dllexport)
 
 #ifndef NOMINMAX
 #define NOMINMAX

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Mesa (master): swr: switch to using SwrGetInterface api table

[Tim Rowley]

Module: Mesa
Branch: master
Commit: 50cd222116b40e4df2462cb25a92960d557c9144
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=50cd222116b40e4df2462cb25a92960d557c9144

Author: Tim Rowley 
Date:   Thu Jun 29 14:03:43 2017 -0500

swr: switch to using SwrGetInterface api table

Use the SWR rasterizer API through the table returned from
SwrGetInterface rather than referencing the functions directly.
This will allow us to move to a model of having the driver dynamically
load the appropriate swr architecture library.

Reviewed-by: Bruce Cherniak 

---

 src/gallium/drivers/swr/swr_clear.cpp   |  6 ++---
 src/gallium/drivers/swr/swr_context.cpp | 19 --
 src/gallium/drivers/swr/swr_context.h   |  5 +++-
 src/gallium/drivers/swr/swr_draw.cpp| 46 -
 src/gallium/drivers/swr/swr_fence.cpp   |  2 +-
 src/gallium/drivers/swr/swr_memory.h|  6 ++---
 src/gallium/drivers/swr/swr_query.cpp   |  8 +++---
 src/gallium/drivers/swr/swr_scratch.cpp |  2 +-
 src/gallium/drivers/swr/swr_screen.cpp  |  3 ++-
 src/gallium/drivers/swr/swr_state.cpp   | 40 ++--
 10 files changed, 72 insertions(+), 65 deletions(-)

diff --git a/src/gallium/drivers/swr/swr_clear.cpp 
b/src/gallium/drivers/swr/swr_clear.cpp
index 3a35805a7a..233432ee34 100644
--- a/src/gallium/drivers/swr/swr_clear.cpp
+++ b/src/gallium/drivers/swr/swr_clear.cpp
@@ -78,9 +78,9 @@ swr_clear(struct pipe_context *pipe,
 
for (unsigned i = 0; i < layers; ++i) {
   swr_update_draw_context(ctx);
-  SwrClearRenderTarget(ctx->swrContext, clearMask, i,
-   color->f, depth, stencil,
-   clear_rect);
+  ctx->api.pfnSwrClearRenderTarget(ctx->swrContext, clearMask, i,
+   color->f, depth, stencil,
+   clear_rect);
 
   // Mask out the attachments that are out of layers.
   if (fb->zsbuf &&
diff --git a/src/gallium/drivers/swr/swr_context.cpp 
b/src/gallium/drivers/swr/swr_context.cpp
index f2d971a22e..9648278c69 100644
--- a/src/gallium/drivers/swr/swr_context.cpp
+++ b/src/gallium/drivers/swr/swr_context.cpp
@@ -311,8 +311,8 @@ swr_blit(struct pipe_context *pipe, const struct 
pipe_blit_info *blit_info)
}
 
if (ctx->active_queries) {
-  SwrEnableStatsFE(ctx->swrContext, FALSE);
-  SwrEnableStatsBE(ctx->swrContext, FALSE);
+  ctx->api.pfnSwrEnableStatsFE(ctx->swrContext, FALSE);
+  ctx->api.pfnSwrEnableStatsBE(ctx->swrContext, FALSE);
}
 
util_blitter_save_vertex_buffer_slot(ctx->blitter, ctx->vertex_buffer);
@@ -349,8 +349,8 @@ swr_blit(struct pipe_context *pipe, const struct 
pipe_blit_info *blit_info)
util_blitter_blit(ctx->blitter, );
 
if (ctx->active_queries) {
-  SwrEnableStatsFE(ctx->swrContext, TRUE);
-  SwrEnableStatsBE(ctx->swrContext, TRUE);
+  ctx->api.pfnSwrEnableStatsFE(ctx->swrContext, TRUE);
+  ctx->api.pfnSwrEnableStatsBE(ctx->swrContext, TRUE);
}
 }
 
@@ -383,10 +383,10 @@ swr_destroy(struct pipe_context *pipe)
 
/* Idle core after destroying buffer resources, but before deleting
 * context.  Destroying resources has potentially called StoreTiles.*/
-   SwrWaitForIdle(ctx->swrContext);
+   ctx->api.pfnSwrWaitForIdle(ctx->swrContext);
 
if (ctx->swrContext)
-  SwrDestroyContext(ctx->swrContext);
+  ctx->api.pfnSwrDestroyContext(ctx->swrContext);
 
delete ctx->blendJIT;
 
@@ -467,6 +467,9 @@ swr_create_context(struct pipe_screen *p_screen, void 
*priv, unsigned flags)
   AlignedMalloc(sizeof(struct swr_context), KNOB_SIMD_BYTES);
memset(ctx, 0, sizeof(struct swr_context));
 
+   SwrGetInterface(ctx->api);
+   ctx->swrDC.pAPI = >api;
+
ctx->blendJIT =
   new std::unordered_map;
 
@@ -478,9 +481,9 @@ swr_create_context(struct pipe_screen *p_screen, void 
*priv, unsigned flags)
createInfo.pfnClearTile = swr_StoreHotTileClear;
createInfo.pfnUpdateStats = swr_UpdateStats;
createInfo.pfnUpdateStatsFE = swr_UpdateStatsFE;
-   ctx->swrContext = SwrCreateContext();
+   ctx->swrContext = ctx->api.pfnSwrCreateContext();
 
-   SwrInit();
+   ctx->api.pfnSwrInit();
 
if (ctx->swrContext == NULL)
   goto fail;
diff --git a/src/gallium/drivers/swr/swr_context.h 
b/src/gallium/drivers/swr/swr_context.h
index 3ff4bf3e2f..753cbf3115 100644
--- a/src/gallium/drivers/swr/swr_context.h
+++ b/src/gallium/drivers/swr/swr_context.h
@@ -102,6 +102,7 @@ struct swr_draw_context {
 
SWR_SURFACE_STATE renderTargets[SWR_NUM_ATTACHMENTS];
struct swr_query_result *pStats; // @llvm_struct
+   SWR_INTERFACE *pAPI; // @llvm_struct - Needed for the swr_memory callbacks
 };
 
 /* gen_llvm_types FINI */
@@ -169,6 +170,8 @@ struct swr_context {
struct swr_draw_context swrDC;
 
unsigned dirty; /**< Mask of SWR_NEW_x flags */
+
+   SWR_INTERFACE api;
 };
 

Mesa (master): swr: build driver proper separate from rasterizer

[Tim Rowley]

Module: Mesa
Branch: master
Commit: f50aa21456d82c8cb6fbaa565835f1acc1720a5d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f50aa21456d82c8cb6fbaa565835f1acc1720a5d

Author: Tim Rowley 
Date:   Thu Jun 29 14:37:07 2017 -0500

swr: build driver proper separate from rasterizer

swr used to build and link the rasterizer to the driver, and to support
multiple architectures we needed to have multiple versions of the
driver/rasterizer combination, which needed to link in much of mesa.

Changing to having one instance of the driver and just building
architecture specific versions of the rasterizer gives a large reduction
in disk space.

libGL.so6464 Kb ->  7000 Kb
libswrAVX.so   10068 Kb ->  5432 Kb
libswrAVX2.so   9828 Kb ->  5200 Kb

Total  26360 Kb -> 17632 Kb

Reviewed-by: Emil Velikov 

---

 src/gallium/drivers/swr/Makefile.am | 31 ++-
 src/gallium/drivers/swr/SConscript  | 26 +-
 src/gallium/drivers/swr/swr_context.cpp |  2 +-
 src/gallium/drivers/swr/swr_loader.cpp  | 14 ++
 src/gallium/drivers/swr/swr_screen.h|  2 ++
 5 files changed, 36 insertions(+), 39 deletions(-)

diff --git a/src/gallium/drivers/swr/Makefile.am 
b/src/gallium/drivers/swr/Makefile.am
index 4b4bd3793b..74612280fe 100644
--- a/src/gallium/drivers/swr/Makefile.am
+++ b/src/gallium/drivers/swr/Makefile.am
@@ -26,7 +26,14 @@ AM_CXXFLAGS = $(GALLIUM_DRIVER_CFLAGS) $(SWR_CXX11_CXXFLAGS)
 
 noinst_LTLIBRARIES = libmesaswr.la
 
-libmesaswr_la_SOURCES = $(LOADER_SOURCES)
+# gen_knobs.* included here to provide driver access to swr configuration
+libmesaswr_la_SOURCES = \
+   $(CXX_SOURCES) \
+   $(COMMON_CXX_SOURCES) \
+   $(JITTER_CXX_SOURCES) \
+   rasterizer/codegen/gen_knobs.cpp \
+   rasterizer/codegen/gen_knobs.h \
+   $(LOADER_SOURCES)
 
 COMMON_CXXFLAGS = \
-fno-strict-aliasing \
@@ -43,12 +50,15 @@ COMMON_CXXFLAGS = \
-I$(srcdir)/rasterizer/jitter \
-I$(srcdir)/rasterizer/archrast
 
+# SWR_AVX_CXXFLAGS needed for intrinsic usage in swr api headers
+libmesaswr_la_CXXFLAGS = \
+   $(SWR_AVX_CXXFLAGS) \
+   $(COMMON_CXXFLAGS)
+
 COMMON_SOURCES = \
-   $(CXX_SOURCES) \
$(ARCHRAST_CXX_SOURCES) \
$(COMMON_CXX_SOURCES) \
$(CORE_CXX_SOURCES) \
-   $(JITTER_CXX_SOURCES) \
$(MEMORY_CXX_SOURCES) \
$(BUILT_SOURCES)
 
@@ -207,19 +217,12 @@ rasterizer.intermediate: 
rasterizer/codegen/gen_backends.py rasterizer/codegen/t
--cpp \
--hpp
 
-COMMON_LIBADD = \
-   $(top_builddir)/src/gallium/auxiliary/libgallium.la \
-   $(top_builddir)/src/mesa/libmesagallium.la \
-   $(LLVM_LIBS)
-
 COMMON_LDFLAGS = \
-shared \
-module \
-no-undefined \
$(GC_SECTIONS) \
-   $(NO_UNDEFINED) \
-   $(LLVM_LDFLAGS)
-
+   $(NO_UNDEFINED)
 
 lib_LTLIBRARIES = libswrAVX.la libswrAVX2.la
 
@@ -231,9 +234,6 @@ libswrAVX_la_CXXFLAGS = \
 libswrAVX_la_SOURCES = \
$(COMMON_SOURCES)
 
-libswrAVX_la_LIBADD = \
-   $(COMMON_LIBADD)
-
 libswrAVX_la_LDFLAGS = \
$(COMMON_LDFLAGS)
 
@@ -245,9 +245,6 @@ libswrAVX2_la_CXXFLAGS = \
 libswrAVX2_la_SOURCES = \
$(COMMON_SOURCES)
 
-libswrAVX2_la_LIBADD = \
-   $(COMMON_LIBADD)
-
 libswrAVX2_la_LDFLAGS = \
$(COMMON_LDFLAGS)
 
diff --git a/src/gallium/drivers/swr/SConscript 
b/src/gallium/drivers/swr/SConscript
index 512269afbe..cdfb91a5bb 100644
--- a/src/gallium/drivers/swr/SConscript
+++ b/src/gallium/drivers/swr/SConscript
@@ -30,12 +30,6 @@ else:
 llvm_includedir = env.backtick('%s --includedir' % llvm_config).rstrip()
 print "llvm include dir %s" % llvm_includedir
 
-# the loader is included in the mesa lib itself
-# All the remaining files are in loadable modules
-loadersource = env.ParseSourceList('Makefile.sources', [
-'LOADER_SOURCES'
-])
-
 if not env['msvc'] :
 env.Append(CCFLAGS = [
 '-std=c++11',
@@ -191,16 +185,12 @@ built_sources += [backendPixelRateFiles, 
genRasterizerFiles]
 
 source = built_sources
 source += env.ParseSourceList(swrroot + 'Makefile.sources', [
-'CXX_SOURCES',
 'ARCHRAST_CXX_SOURCES',
 'COMMON_CXX_SOURCES',
 'CORE_CXX_SOURCES',
-'JITTER_CXX_SOURCES',
 'MEMORY_CXX_SOURCES'
 ])
 
-env.Prepend(LIBS = [ mesautil, mesa, gallium ])
-
 env.Prepend(CPPPATH = [
 '.',
 'rasterizer',
@@ -242,14 +232,24 @@ swrAVX2 = envavx2.SharedLibrary(
 )
 env.Alias('swrAVX2', swrAVX2)
 
+source = env.ParseSourceList(swrroot + 'Makefile.sources', [
+'CXX_SOURCES',
+'COMMON_CXX_SOURCES',
+'JITTER_CXX_SOURCES',
+'LOADER_SOURCES'
+])
+source += [
+'rasterizer/codegen/gen_knobs.cpp',
+'rasterizer/archrast/gen_ar_event.cpp',
+]
 
 # main SWR lib
-swr = env.ConvenienceLibrary(
+envSWR = envavx.Clone() # pick up the arch flag for intrinsic usage
+swr = 

Mesa (master): i965: perf: use new subslices numbers from device info

[Lionel Landwerlin]

Module: Mesa
Branch: master
Commit: 9d681a7a18880cc10e2c19afc6e0624331d67d25
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d681a7a18880cc10e2c19afc6e0624331d67d25

Author: Lionel Landwerlin 
Date:   Wed Jun 21 17:48:14 2017 +0100

i965: perf: use new subslices numbers from device info

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Ben Widawsky 

---

 src/mesa/drivers/dri/i965/brw_performance_query.c | 49 ---
 1 file changed, 17 insertions(+), 32 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 57feae7245..d7902de836 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1826,26 +1826,25 @@ init_oa_sys_vars(struct brw_context *brw, const char 
*sysfs_dev_dir)
brw->perfquery.sys_vars.gt_min_freq = min_freq_mhz * 100;
brw->perfquery.sys_vars.gt_max_freq = max_freq_mhz * 100;
brw->perfquery.sys_vars.timestamp_frequency = devinfo->timestamp_frequency;
+   brw->perfquery.sys_vars.n_eu_slices = devinfo->num_slices;
+   /* Assuming uniform distribution of subslices per slices. */
+   brw->perfquery.sys_vars.n_eu_sub_slices = devinfo->num_subslices[0];
 
if (devinfo->is_haswell) {
+  brw->perfquery.sys_vars.slice_mask = 0;
+  brw->perfquery.sys_vars.subslice_mask = 0;
+
+  for (int s = 0; s < devinfo->num_slices; s++)
+ brw->perfquery.sys_vars.slice_mask |= 1U << s;
+  for (int ss = 0; ss < devinfo->num_subslices[0]; ss++)
+ brw->perfquery.sys_vars.subslice_mask |= 1U << ss;
+
   if (devinfo->gt == 1) {
  brw->perfquery.sys_vars.n_eus = 10;
- brw->perfquery.sys_vars.n_eu_slices = 1;
- brw->perfquery.sys_vars.n_eu_sub_slices = 1;
- brw->perfquery.sys_vars.slice_mask = 0x1;
- brw->perfquery.sys_vars.subslice_mask = 0x1;
   } else if (devinfo->gt == 2) {
  brw->perfquery.sys_vars.n_eus = 20;
- brw->perfquery.sys_vars.n_eu_slices = 1;
- brw->perfquery.sys_vars.n_eu_sub_slices = 2;
- brw->perfquery.sys_vars.slice_mask = 0x1;
- brw->perfquery.sys_vars.subslice_mask = 0x3;
   } else if (devinfo->gt == 3) {
  brw->perfquery.sys_vars.n_eus = 40;
- brw->perfquery.sys_vars.n_eu_slices = 2;
- brw->perfquery.sys_vars.n_eu_sub_slices = 2;
- brw->perfquery.sys_vars.slice_mask = 0x3;
- brw->perfquery.sys_vars.subslice_mask = 0xf;
   } else
  unreachable("not reached");
} else {
@@ -1854,29 +1853,15 @@ init_oa_sys_vars(struct brw_context *brw, const char 
*sysfs_dev_dir)
   int ret;
   int slice_mask = 0;
   int ss_mask = 0;
-  int s_max = devinfo->num_slices; /* maximum number of slices */
-  int ss_max = 0; /* maximum number of subslices per slice */
+  /* maximum number of slices */
+  int s_max = devinfo->num_slices;
+  /* maximum number of subslices per slice (assuming uniform subslices per
+   * slices)
+   */
+  int ss_max = devinfo->num_subslices[0];
   uint64_t subslice_mask = 0;
   int s;
 
-  if (devinfo->gen == 8) {
- if (devinfo->gt == 1) {
-ss_max = 2;
- } else {
-ss_max = 3;
- }
-  } else if (devinfo->gen == 9) {
- /* XXX: beware that the kernel (as of writing) actually works as if
-  * ss_max == 4 since the HW register that reports the global subslice
-  * mask has 4 bits while in practice the limit is 3. It's also
-  * important that we initialize $SubsliceMask with 3 bits per slice
-  * since that's what the counter availability expressions in XML
-  * expect.
-  */
- ss_max = 3;
-  } else
- return false;
-
   gp.param = I915_PARAM_SLICE_MASK;
   gp.value = _mask;
   ret = drmIoctl(screen->fd, DRM_IOCTL_I915_GETPARAM, );

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Mesa (master): i965: Use already existing eu_total

[Lionel Landwerlin]

Module: Mesa
Branch: master
Commit: 25c1a7cc7aea7e9c95ef70116fafc9a14d837939
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=25c1a7cc7aea7e9c95ef70116fafc9a14d837939

Author: Ben Widawsky 
Date:   Wed Jul  5 17:04:16 2017 -0700

i965: Use already existing eu_total

Reduces IOCTL calls by 1, and provides a centralized place to override
such configurations if we have a need to do so.

Signed-off-by: Ben Widawsky 
Reviewed-by: Lionel Landwerlin 

---

 src/mesa/drivers/dri/i965/brw_performance_query.c | 9 +
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index e4e1854bf2..57feae7245 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1852,7 +1852,6 @@ init_oa_sys_vars(struct brw_context *brw, const char 
*sysfs_dev_dir)
   __DRIscreen *screen = brw->screen->driScrnPriv;
   drm_i915_getparam_t gp;
   int ret;
-  int n_eus = 0;
   int slice_mask = 0;
   int ss_mask = 0;
   int s_max = devinfo->num_slices; /* maximum number of slices */
@@ -1878,12 +1877,6 @@ init_oa_sys_vars(struct brw_context *brw, const char 
*sysfs_dev_dir)
   } else
  return false;
 
-  gp.param = I915_PARAM_EU_TOTAL;
-  gp.value = _eus;
-  ret = drmIoctl(screen->fd, DRM_IOCTL_I915_GETPARAM, );
-  if (ret)
- return false;
-
   gp.param = I915_PARAM_SLICE_MASK;
   gp.value = _mask;
   ret = drmIoctl(screen->fd, DRM_IOCTL_I915_GETPARAM, );
@@ -1896,7 +1889,7 @@ init_oa_sys_vars(struct brw_context *brw, const char 
*sysfs_dev_dir)
   if (ret)
  return false;
 
-  brw->perfquery.sys_vars.n_eus = n_eus;
+  brw->perfquery.sys_vars.n_eus = brw->screen->eu_total;
   brw->perfquery.sys_vars.n_eu_slices = __builtin_popcount(slice_mask);
   brw->perfquery.sys_vars.slice_mask = slice_mask;
 

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Mesa (master): intel: add number of subslices to device info

[Lionel Landwerlin]

Module: Mesa
Branch: master
Commit: 384aaa4d3f0789f3765ba51a30c0defc631803f5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=384aaa4d3f0789f3765ba51a30c0defc631803f5

Author: Lionel Landwerlin 
Date:   Wed Jun 21 17:44:17 2017 +0100

intel: add number of subslices to device info

We could have used a single integer to store that value, but
Cannonlake has different number of subslices per slice depending on
the GT.

v2: Add CFL subslice numbers (Lionel)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Ben Widawsky 

---

 src/intel/common/gen_device_info.c | 57 --
 src/intel/common/gen_device_info.h |  5 
 2 files changed, 54 insertions(+), 8 deletions(-)

diff --git a/src/intel/common/gen_device_info.c 
b/src/intel/common/gen_device_info.c
index f008b76ea4..c0eb7c3c35 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -21,15 +21,18 @@
  * IN THE SOFTWARE.
  */
 
+#include 
 #include 
 #include 
 #include "gen_device_info.h"
 #include "compiler/shader_enums.h"
+#include "util/macros.h"
 
 static const struct gen_device_info gen_device_info_i965 = {
.gen = 4,
.has_negative_rhw_bug = true,
.num_slices = 1,
+   .num_subslices = { 1, },
.num_thread_per_eu = 4,
.max_vs_threads = 16,
.max_gs_threads = 2,
@@ -47,6 +50,7 @@ static const struct gen_device_info gen_device_info_g4x = {
.has_surface_tile_offset = true,
.is_g4x = true,
.num_slices = 1,
+   .num_subslices = { 1, },
.num_thread_per_eu = 5,
.max_vs_threads = 32,
.max_gs_threads = 2,
@@ -63,6 +67,7 @@ static const struct gen_device_info gen_device_info_ilk = {
.has_compr4 = true,
.has_surface_tile_offset = true,
.num_slices = 1,
+   .num_subslices = { 1, },
.num_thread_per_eu = 6,
.max_vs_threads = 72,
.max_gs_threads = 32,
@@ -82,6 +87,7 @@ static const struct gen_device_info gen_device_info_snb_gt1 = 
{
.has_surface_tile_offset = true,
.needs_unlit_centroid_workaround = true,
.num_slices = 1,
+   .num_subslices = { 1, },
.num_thread_per_eu = 6, /* Not confirmed */
.max_vs_threads = 24,
.max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
@@ -108,6 +114,7 @@ static const struct gen_device_info gen_device_info_snb_gt2 
= {
.has_surface_tile_offset = true,
.needs_unlit_centroid_workaround = true,
.num_slices = 1,
+   .num_subslices = { 1, },
.num_thread_per_eu = 6, /* Not confirmed */
.max_vs_threads = 60,
.max_gs_threads = 60,
@@ -137,6 +144,7 @@ static const struct gen_device_info gen_device_info_snb_gt2 
= {
 static const struct gen_device_info gen_device_info_ivb_gt1 = {
GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
.num_slices = 1,
+   .num_subslices = { 1, },
.num_thread_per_eu = 6,
.l3_banks = 2,
.max_vs_threads = 36,
@@ -163,6 +171,7 @@ static const struct gen_device_info gen_device_info_ivb_gt1 
= {
 static const struct gen_device_info gen_device_info_ivb_gt2 = {
GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
.num_slices = 1,
+   .num_subslices = { 1, },
.num_thread_per_eu = 8, /* Not sure why this isn't a multiple of
 * @max_wm_threads ... */
.l3_banks = 4,
@@ -190,6 +199,7 @@ static const struct gen_device_info gen_device_info_ivb_gt2 
= {
 static const struct gen_device_info gen_device_info_byt = {
GEN7_FEATURES, .is_baytrail = true, .gt = 1,
.num_slices = 1,
+   .num_subslices = { 1, },
.num_thread_per_eu = 8,
.l3_banks = 1,
.has_llc = false,
@@ -223,6 +233,7 @@ static const struct gen_device_info gen_device_info_byt = {
 static const struct gen_device_info gen_device_info_hsw_gt1 = {
HSW_FEATURES, .gt = 1,
.num_slices = 1,
+   .num_subslices = { 1, },
.num_thread_per_eu = 7,
.l3_banks = 2,
.max_vs_threads = 70,
@@ -249,6 +260,7 @@ static const struct gen_device_info gen_device_info_hsw_gt1 
= {
 static const struct gen_device_info gen_device_info_hsw_gt2 = {
HSW_FEATURES, .gt = 2,
.num_slices = 1,
+   .num_subslices = { 2, },
.num_thread_per_eu = 7,
.l3_banks = 4,
.max_vs_threads = 280,
@@ -275,6 +287,7 @@ static const struct gen_device_info gen_device_info_hsw_gt2 
= {
 static const struct gen_device_info gen_device_info_hsw_gt3 = {
HSW_FEATURES, .gt = 3,
.num_slices = 2,
+   .num_subslices = { 2, },
.num_thread_per_eu = 7,
.l3_banks = 8,
.max_vs_threads = 280,
@@ -318,6 +331,7 @@ static const struct gen_device_info gen_device_info_bdw_gt1 
= {
GEN8_FEATURES, .gt = 1,
.is_broadwell = true,
.num_slices = 1,
+   .num_subslices = { 2, },
.num_thread_per_eu = 7,
.l3_banks = 2,
.max_cs_threads = 42,
@@ -340,6 +354,7 @@ static const struct gen_device_info gen_device_info_bdw_gt2 
= {
GEN8_FEATURES, .gt = 2,
.is_broadwell = true,
.num_slices = 1,
+   .num_subslices = { 3, 

Mesa (master): i965: Resolve framebuffers before signaling the fence

[Chris Wilson]

Module: Mesa
Branch: master
Commit: 618be8cc1ad1760103930b69ffbf528d7b861ab3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=618be8cc1ad1760103930b69ffbf528d7b861ab3

Author: Chris Wilson 
Date:   Mon Jun 12 15:17:20 2017 +0100

i965: Resolve framebuffers before signaling the fence

From KHR_fence_sync:

  When the condition of the sync object is satisfied by the fence
  command, the sync is signaled by the associated client API context,
  causing any eglClientWaitSyncKHR commands (see below) blocking on
   to unblock. The only condition currently supported is
  EGL_SYNC_PRIOR_COMMANDS_COMPLETE_KHR, which is satisfied by
  completion of the fence command corresponding to the sync object,
  and all preceding commands in the associated client API context's
  command stream. The sync object will not be signaled until all
  effects from these commands on the client API's internal and
  framebuffer state are fully realized. No other state is affected by
  execution of the fence command.

If clients are passing the fence fd (from EGL_ANDROID_native_fence_sync)
to a compositor, that fence must only be signaled once the framebuffer
is resolved and not before as is currently the case.

v2: fixup assert to use GL_SYNC_GPU_COMMANDS_COMPLETE (Chad)

Reported-by: Sergi Granell 
Fixes: c636284ee8ee ("i965/sync: Implement DRI2_Fence extension")
Signed-off-by: Chris Wilson 
Cc: Sergi Granell 
Cc: Rob Clark 
Cc: Chad Versace 
Cc: Daniel Stone 
Cc: Kenneth Graunke 
Reviewed-by: Chad Versace 

---

 src/mesa/drivers/dri/i965/brw_sync.c | 32 
 1 file changed, 32 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_sync.c 
b/src/mesa/drivers/dri/i965/brw_sync.c
index a8356c304f..edfb1881bc 100644
--- a/src/mesa/drivers/dri/i965/brw_sync.c
+++ b/src/mesa/drivers/dri/i965/brw_sync.c
@@ -110,6 +110,35 @@ brw_fence_finish(struct brw_fence *fence)
 static bool MUST_CHECK
 brw_fence_insert_locked(struct brw_context *brw, struct brw_fence *fence)
 {
+   __DRIcontext *driContext = brw->driContext;
+   __DRIdrawable *driDrawable = driContext->driDrawablePriv;
+
+   /*
+* From KHR_fence_sync:
+*
+*   When the condition of the sync object is satisfied by the fence
+*   command, the sync is signaled by the associated client API context,
+*   causing any eglClientWaitSyncKHR commands (see below) blocking on
+*to unblock. The only condition currently supported is
+*   EGL_SYNC_PRIOR_COMMANDS_COMPLETE_KHR, which is satisfied by
+*   completion of the fence command corresponding to the sync object,
+*   and all preceding commands in the associated client API context's
+*   command stream. The sync object will not be signaled until all
+*   effects from these commands on the client API's internal and
+*   framebuffer state are fully realized. No other state is affected by
+*   execution of the fence command.
+*
+* Note the emphasis there on ensuring that the framebuffer is fully
+* realised before the fence is signaled. We cannot just flush the batch,
+* but must also resolve the drawable first. The importance of this is,
+* for example, in creating a fence for a frame to be passed to a
+* remote compositor. Without us flushing the drawable explicitly, the
+* resolve will be in a following batch (when the client finally calls
+* SwapBuffers, or triggers a resolve via some other path) and so the
+* compositor may read the incomplete framebuffer instead.
+*/
+   if (driDrawable)
+  intel_resolve_for_dri2_flush(brw, driDrawable);
brw_emit_mi_flush(brw);
 
switch (fence->type) {
@@ -335,6 +364,9 @@ brw_gl_fence_sync(struct gl_context *ctx, struct 
gl_sync_object *_sync,
struct brw_context *brw = brw_context(ctx);
struct brw_gl_sync *sync = (struct brw_gl_sync *) _sync;
 
+   /* brw_fence_insert_locked() assumes it must do a complete flush */
+   assert(condition == GL_SYNC_GPU_COMMANDS_COMPLETE);
+
brw_fence_init(brw, >fence, BRW_FENCE_TYPE_BO_WAIT);
 
if (!brw_fence_insert_locked(brw, >fence)) {

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Mesa (master): svga: s/unsigned/enum tgsi_interpolate_mode/

[Brian Paul]

Module: Mesa
Branch: master
Commit: 3effacf1725d90d14701e59dbbc4ff636b23a04d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3effacf1725d90d14701e59dbbc4ff636b23a04d

Author: Brian Paul 
Date:   Mon Jul 10 14:09:25 2017 -0600

svga: s/unsigned/enum tgsi_interpolate_mode/

And s/unsigned/enum tgsi_interpolate_loc/

Reviewed-by: Charmaine Lee 
Reviewed-by: Neha Bhende 

---

 src/gallium/drivers/svga/svga_tgsi_vgpu10.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c 
b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
index cd4cab4586..d02dbb6222 100644
--- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
+++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
@@ -1843,7 +1843,8 @@ emit_vgpu10_immediates_block(struct 
svga_shader_emitter_v10 *emit)
  */
 static unsigned
 translate_interpolation(const struct svga_shader_emitter_v10 *emit,
-unsigned interp, unsigned interpolate_loc)
+enum tgsi_interpolate_mode interp,
+enum tgsi_interpolate_loc interpolate_loc)
 {
if (interp == TGSI_INTERPOLATE_COLOR) {
   interp = emit->key.fs.flatshade ?

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Mesa (master): svga: s/unsigned/enum tgsi_semantic/

[Brian Paul]

Module: Mesa
Branch: master
Commit: 1b5e88becde0122ebe58f8ae3a8669d4842b2623
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b5e88becde0122ebe58f8ae3a8669d4842b2623

Author: Brian Paul 
Date:   Mon Jul 10 14:03:48 2017 -0600

svga: s/unsigned/enum tgsi_semantic/

Makes gdb debugging a little nicer.

Reviewed-by: Charmaine Lee 
Reviewed-by: Neha Bhende 

---

 src/gallium/drivers/svga/svga_link.c   |  2 +-
 src/gallium/drivers/svga/svga_pipe_streamout.c |  3 ++-
 src/gallium/drivers/svga/svga_swtnl_state.c|  2 +-
 src/gallium/drivers/svga/svga_tgsi_vgpu10.c| 11 ++-
 4 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_link.c 
b/src/gallium/drivers/svga/svga_link.c
index 5bc7f6164d..9c1df0c7f3 100644
--- a/src/gallium/drivers/svga/svga_link.c
+++ b/src/gallium/drivers/svga/svga_link.c
@@ -62,7 +62,7 @@ svga_link_shaders(const struct tgsi_shader_info 
*outshader_info,
free_slot = outshader_info->num_outputs + 1;
 
for (i = 0; i < inshader_info->num_inputs; i++) {
-  unsigned sem_name = inshader_info->input_semantic_name[i];
+  enum tgsi_semantic sem_name = inshader_info->input_semantic_name[i];
   unsigned sem_index = inshader_info->input_semantic_index[i];
   unsigned j;
   /**
diff --git a/src/gallium/drivers/svga/svga_pipe_streamout.c 
b/src/gallium/drivers/svga/svga_pipe_streamout.c
index 3f30e648c0..0c6c034751 100644
--- a/src/gallium/drivers/svga/svga_pipe_streamout.c
+++ b/src/gallium/drivers/svga/svga_pipe_streamout.c
@@ -92,7 +92,8 @@ svga_create_stream_output(struct svga_context *svga,
for (i = 0; i < info->num_outputs; i++) {
   unsigned reg_idx = info->output[i].register_index;
   unsigned buf_idx = info->output[i].output_buffer;
-  const unsigned sem_name = shader->info.output_semantic_name[reg_idx];
+  const enum tgsi_semantic sem_name =
+ shader->info.output_semantic_name[reg_idx];
 
   assert(buf_idx <= PIPE_MAX_SO_BUFFERS);
 
diff --git a/src/gallium/drivers/svga/svga_swtnl_state.c 
b/src/gallium/drivers/svga/svga_swtnl_state.c
index 71faf3a610..8b7a8e7fbf 100644
--- a/src/gallium/drivers/svga/svga_swtnl_state.c
+++ b/src/gallium/drivers/svga/svga_swtnl_state.c
@@ -253,7 +253,7 @@ svga_swtnl_update_vdecl( struct svga_context *svga )
nr_decls++;
 
for (i = 0; i < fs->base.info.num_inputs; i++) {
-  const unsigned sem_name = fs->base.info.input_semantic_name[i];
+  const enum tgsi_semantic sem_name = fs->base.info.input_semantic_name[i];
   const unsigned sem_index = fs->base.info.input_semantic_index[i];
 
   src = draw_find_shader_output(draw, sem_name, sem_index);
diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c 
b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
index 1dd76ccda1..070d67f278 100644
--- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
+++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
@@ -851,7 +851,7 @@ emit_dst_register(struct svga_shader_emitter_v10 *emit,
 {
unsigned file = reg->Register.File;
unsigned index = reg->Register.Index;
-   const unsigned sem_name = emit->info.output_semantic_name[index];
+   const enum tgsi_semantic sem_name = emit->info.output_semantic_name[index];
const unsigned sem_index = emit->info.output_semantic_index[index];
unsigned writemask = reg->Register.WriteMask;
const unsigned indirect = reg->Register.Indirect;
@@ -2178,7 +2178,7 @@ emit_fragdepth_output_declaration(struct 
svga_shader_emitter_v10 *emit)
  */
 static void
 emit_system_value_declaration(struct svga_shader_emitter_v10 *emit,
-  unsigned semantic_name, unsigned index)
+  enum tgsi_semantic semantic_name, unsigned index)
 {
switch (semantic_name) {
case TGSI_SEMANTIC_INSTANCEID:
@@ -2345,7 +2345,7 @@ emit_input_declarations(struct svga_shader_emitter_v10 
*emit)
if (emit->unit == PIPE_SHADER_FRAGMENT) {
 
   for (i = 0; i < emit->linkage.num_inputs; i++) {
- unsigned semantic_name = emit->info.input_semantic_name[i];
+ enum tgsi_semantic semantic_name = emit->info.input_semantic_name[i];
  unsigned usage_mask = emit->info.input_usage_mask[i];
  unsigned index = emit->linkage.input_map[i];
  unsigned type, interpolationMode, name;
@@ -2404,7 +2404,7 @@ emit_input_declarations(struct svga_shader_emitter_v10 
*emit)
else if (emit->unit == PIPE_SHADER_GEOMETRY) {
 
   for (i = 0; i < emit->info.num_inputs; i++) {
- unsigned semantic_name = emit->info.input_semantic_name[i];
+ enum tgsi_semantic semantic_name = emit->info.input_semantic_name[i];
  unsigned usage_mask = emit->info.input_usage_mask[i];
  unsigned index = emit->linkage.input_map[i];
  unsigned opcodeType, operandType;
@@ -2487,7 +2487,8 @@ emit_output_declarations(struct svga_shader_emitter_v10 
*emit)
 
for (i = 0; i < 

Mesa (master): svga: s/unsigned/enum tgsi_swizzle

[Brian Paul]

Module: Mesa
Branch: master
Commit: 1d826749696c267398fc12c49fce74f5cbc5efc7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d826749696c267398fc12c49fce74f5cbc5efc7

Author: Brian Paul 
Date:   Mon Jul 10 14:12:27 2017 -0600

svga: s/unsigned/enum tgsi_swizzle

Reviewed-by: Charmaine Lee 
Reviewed-by: Neha Bhende 

---

 src/gallium/drivers/svga/svga_tgsi_vgpu10.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c 
b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
index d02dbb6222..bbaad20b60 100644
--- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
+++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
@@ -1470,7 +1470,7 @@ absolute_src(const struct tgsi_full_src_register *reg)
 
 /** Return the named swizzle term from the src register */
 static inline unsigned
-get_swizzle(const struct tgsi_full_src_register *reg, unsigned term)
+get_swizzle(const struct tgsi_full_src_register *reg, enum tgsi_swizzle term)
 {
switch (term) {
case TGSI_SWIZZLE_X:
@@ -1493,8 +1493,8 @@ get_swizzle(const struct tgsi_full_src_register *reg, 
unsigned term)
  */
 static struct tgsi_full_src_register
 swizzle_src(const struct tgsi_full_src_register *reg,
-unsigned swizzleX, unsigned swizzleY,
-unsigned swizzleZ, unsigned swizzleW)
+enum tgsi_swizzle swizzleX, enum tgsi_swizzle swizzleY,
+enum tgsi_swizzle swizzleZ, enum tgsi_swizzle swizzleW)
 {
struct tgsi_full_src_register swizzled = *reg;
/* Note: we swizzle the current swizzle */
@@ -1511,7 +1511,7 @@ swizzle_src(const struct tgsi_full_src_register *reg,
  * terms are the same.
  */
 static struct tgsi_full_src_register
-scalar_src(const struct tgsi_full_src_register *reg, unsigned swizzle)
+scalar_src(const struct tgsi_full_src_register *reg, enum tgsi_swizzle swizzle)
 {
struct tgsi_full_src_register swizzled = *reg;
/* Note: we swizzle the current swizzle */

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Mesa (master): svga: s/unsigned/enum tgsi_file_type/

[Brian Paul]

Module: Mesa
Branch: master
Commit: 9330112b3539ddb9aa565140cf23f2c3fd1583c2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9330112b3539ddb9aa565140cf23f2c3fd1583c2

Author: Brian Paul 
Date:   Mon Jul 10 14:08:36 2017 -0600

svga: s/unsigned/enum tgsi_file_type/

Reviewed-by: Charmaine Lee 
Reviewed-by: Neha Bhende 

---

 src/gallium/drivers/svga/svga_tgsi_vgpu10.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c 
b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
index 070d67f278..cd4cab4586 100644
--- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
+++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
@@ -706,7 +706,7 @@ emit_null_dst_register(struct svga_shader_emitter_v10 *emit)
  */
 static unsigned
 get_temp_array_id(const struct svga_shader_emitter_v10 *emit,
-  unsigned file, unsigned index)
+  enum tgsi_file_type file, unsigned index)
 {
if (file == TGSI_FILE_TEMPORARY) {
   return emit->temp_map[index].arrayId;
@@ -723,7 +723,7 @@ get_temp_array_id(const struct svga_shader_emitter_v10 
*emit,
  */
 static unsigned
 remap_temp_index(const struct svga_shader_emitter_v10 *emit,
- unsigned file, unsigned index)
+ enum tgsi_file_type file, unsigned index)
 {
if (file == TGSI_FILE_TEMPORARY) {
   return emit->temp_map[index].index;
@@ -741,7 +741,7 @@ remap_temp_index(const struct svga_shader_emitter_v10 *emit,
 static VGPU10OperandToken0
 setup_operand0_indexing(struct svga_shader_emitter_v10 *emit,
 VGPU10OperandToken0 operand0,
-unsigned file,
+enum tgsi_file_type file,
 boolean indirect, boolean index2D,
 unsigned tempArrayID)
 {
@@ -849,7 +849,7 @@ static void
 emit_dst_register(struct svga_shader_emitter_v10 *emit,
   const struct tgsi_full_dst_register *reg)
 {
-   unsigned file = reg->Register.File;
+   enum tgsi_file_type file = reg->Register.File;
unsigned index = reg->Register.Index;
const enum tgsi_semantic sem_name = emit->info.output_semantic_name[index];
const unsigned sem_index = emit->info.output_semantic_index[index];
@@ -967,7 +967,7 @@ static void
 emit_src_register(struct svga_shader_emitter_v10 *emit,
   const struct tgsi_full_src_register *reg)
 {
-   unsigned file = reg->Register.File;
+   enum tgsi_file_type file = reg->Register.File;
unsigned index = reg->Register.Index;
const unsigned indirect = reg->Register.Indirect;
const unsigned tempArrayId = get_temp_array_id(emit, file, index);
@@ -1364,7 +1364,7 @@ free_temp_indexes(struct svga_shader_emitter_v10 *emit)
  * Create a tgsi_full_src_register.
  */
 static struct tgsi_full_src_register
-make_src_reg(unsigned file, unsigned index)
+make_src_reg(enum tgsi_file_type file, unsigned index)
 {
struct tgsi_full_src_register reg;
 
@@ -1413,7 +1413,7 @@ make_src_immediate_reg(unsigned index)
  * Create a tgsi_full_dst_register.
  */
 static struct tgsi_full_dst_register
-make_dst_reg(unsigned file, unsigned index)
+make_dst_reg(enum tgsi_file_type file, unsigned index)
 {
struct tgsi_full_dst_register reg;
 

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Mesa (master): svga: s/unsigned/enum tgsi_texture_type/

[Brian Paul]

Module: Mesa
Branch: master
Commit: bf7a4f444110a153268e72cf6bc0a4f610ab05a4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf7a4f444110a153268e72cf6bc0a4f610ab05a4

Author: Brian Paul 
Date:   Mon Jul 10 14:14:17 2017 -0600

svga: s/unsigned/enum tgsi_texture_type/

Reviewed-by: Charmaine Lee 
Reviewed-by: Neha Bhende 

---

 src/gallium/drivers/svga/svga_tgsi_vgpu10.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c 
b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
index bbaad20b60..d29ac28240 100644
--- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
+++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
@@ -2955,7 +2955,8 @@ emit_sampler_declarations(struct svga_shader_emitter_v10 
*emit)
  * Translate TGSI_TEXTURE_x to VGAPU10_RESOURCE_DIMENSION_x.
  */
 static unsigned
-tgsi_texture_to_resource_dimension(unsigned target, boolean is_array)
+tgsi_texture_to_resource_dimension(enum tgsi_texture_type target,
+   boolean is_array)
 {
switch (target) {
case TGSI_TEXTURE_BUFFER:
@@ -4867,7 +4868,7 @@ setup_texcoord(struct svga_shader_emitter_v10 *emit,
  */
 static void
 emit_tex_compare_refcoord(struct svga_shader_emitter_v10 *emit,
-  unsigned target,
+  enum tgsi_texture_type target,
   const struct tgsi_full_src_register *coord)
 {
struct tgsi_full_src_register coord_src_ref;
@@ -4901,7 +4902,7 @@ struct tex_swizzle_info
boolean swizzled;
boolean shadow_compare;
unsigned unit;
-   unsigned texture_target;  /**< TGSI_TEXTURE_x */
+   enum tgsi_texture_type texture_target;  /**< TGSI_TEXTURE_x */
struct tgsi_full_src_register tmp_src;
struct tgsi_full_dst_register tmp_dst;
const struct tgsi_full_dst_register *inst_dst;

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