Mesa (master): st/mesa: only try to create 1x msaa surfaces for "fake" msaa drivers
Module: Mesa
Branch: master
Commit: 9eca7e0ddb58808af77c6f251f5d368ea328c894
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9eca7e0ddb58808af77c6f251f5d368ea328c894
Author: Brian Paul
Date: Mon Aug 21 20:53:25 2017 -0600
st/mesa: only try to create 1x msaa surfaces for "fake" msaa drivers
For software drivers where we want "fake" msaa support for GL 3.x, we
treat 1 sample as being msaa.
For drivers with real msaa support, start format probing at 2x msaa.
For drivers with fake msaa support, start format probing at 1x msaa.
This also tweaks the MaxSamples code in st_init_extensions() so that
we use MaxSamples=1 for fake msaa. This allows the format proble loops
to run at least one iteration.
This fixes a llvmpipe/VTK regression from commit 6839d3369905eb02151.
And for drivers with fake msaa support, calls such as
glTexImage2DMultisample(samples=1) will now succeed.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102038
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102125
Reviewed-by: Roland Scheidegger
---
src/mesa/state_tracker/st_cb_fbo.c | 13 ++---
src/mesa/state_tracker/st_cb_texture.c | 11 ---
src/mesa/state_tracker/st_extensions.c | 14 ++
3 files changed, 24 insertions(+), 14 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_fbo.c
b/src/mesa/state_tracker/st_cb_fbo.c
index afc7700306..a7c286bcc5 100644
--- a/src/mesa/state_tracker/st_cb_fbo.c
+++ b/src/mesa/state_tracker/st_cb_fbo.c
@@ -155,12 +155,19 @@ st_renderbuffer_alloc_storage(struct gl_context * ctx,
* to and no more than the next larger sample count supported
* by the implementation.
*
-* So let's find the supported number of samples closest to NumSamples.
+* Find the supported number of samples >= rb->NumSamples
*/
if (rb->NumSamples > 0) {
- unsigned i;
+ unsigned start, i;
- for (i = MAX2(2, rb->NumSamples); i <= ctx->Const.MaxSamples; i++) {
+ if (ctx->Const.MaxSamples > 1 && rb->NumSamples == 1) {
+ /* don't try num_samples = 1 with drivers that support real msaa */
+ start = 2;
+ } else {
+ start = rb->NumSamples;
+ }
+
+ for (i = start; i <= ctx->Const.MaxSamples; i++) {
format = st_choose_renderbuffer_format(st, internalFormat, i);
if (format != PIPE_FORMAT_NONE) {
diff --git a/src/mesa/state_tracker/st_cb_texture.c
b/src/mesa/state_tracker/st_cb_texture.c
index af2052db24..b5006b05a7 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -2739,13 +2739,18 @@ st_texture_storage(struct gl_context *ctx,
bindings = default_bindings(st, fmt);
- /* Raise the sample count if the requested one is unsupported. */
if (num_samples > 0) {
+ /* Find msaa sample count which is actually supported. For example,
+ * if the user requests 1x but only 4x or 8x msaa is supported, we'll
+ * choose 4x here.
+ */
enum pipe_texture_target ptarget = gl_target_to_pipe(texObj->Target);
boolean found = FALSE;
- /* start the query with at least two samples */
- num_samples = MAX2(num_samples, 2);
+ if (ctx->Const.MaxSamples > 1 && num_samples == 1) {
+ /* don't try num_samples = 1 with drivers that support real msaa */
+ num_samples = 2;
+ }
for (; num_samples <= ctx->Const.MaxSamples; num_samples++) {
if (screen->is_format_supported(screen, fmt, ptarget,
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index 8785903251..bc206df3bf 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -1046,17 +1046,15 @@ void st_init_extensions(struct pipe_screen *screen,
void_formats, 32,
PIPE_BIND_RENDER_TARGET);
}
- if (consts->MaxSamples == 1) {
- /* one sample doesn't really make sense */
- consts->MaxSamples = 0;
- }
- else if (consts->MaxSamples >= 2) {
+
+ if (consts->MaxSamples >= 2) {
+ /* Real MSAA support */
extensions->EXT_framebuffer_multisample = GL_TRUE;
extensions->EXT_framebuffer_multisample_blit_scaled = GL_TRUE;
}
-
- if (consts->MaxSamples == 0 &&
- screen->get_param(screen, PIPE_CAP_FAKE_SW_MSAA)) {
+ else if (consts->MaxSamples > 0 &&
+screen->get_param(screen, PIPE_CAP_FAKE_SW_MSAA)) {
+ /* fake MSAA support */
consts->FakeSWMSAA = GL_TRUE;
extensions->EXT_framebuffer_multisample = GL_TRUE;
extensions->EXT_framebuffer_multisample_blit_scaled = GL_TRUE;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nvc0/ir: propagate immediates to CALL input MOVs
Module: Mesa
Branch: master
Commit: 1c4e6d7ca83578caf5212f7a484538cb1b4ae2a3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c4e6d7ca83578caf5212f7a484538cb1b4ae2a3
Author: Tobias Klausmann
Date: Sun Aug 13 03:02:39 2017 +0200
nvc0/ir: propagate immediates to CALL input MOVs
On using builtin functions we have to move the input to registers $0 and $1, if
one of the input value is an immediate, we fail to propagate the immediate:
...
mov u32 $r477 0x0003 (0)
...
mov u32 $r0 %r473 (0)
mov u32 $r1 $r477 (0)
call abs BUILTIN:0 (0)
mov u32 %r495 $r1 (0)
...
With this patch the immediate is propagated, potentially causing the first MOV
to be superfluous, which we'd remove in that case:
...
mov u32 $r0 %r473 (0)
mov u32 $r1 0x0003 (0)
call abs BUILTIN:0 (0)
mov u32 %r495 $r1 (0)
...
Shaderdb stats:
total instructions in shared programs : 4893460 -> 4893324 (-0.00%)
total gprs used in shared programs: 582972 -> 582881 (-0.02%)
total local used in shared programs : 17960 -> 17960 (0.00%)
localgpr inst bytes
helped 0 91 112 112
hurt 0 0 0 0
v2:
implement some changes proposed by imirkin, the manual deletion of the dead
mov is necessary after ea22ac23e0 ("nvc0/ir: unlink values pre- and post-call
to division function") as the potentially dead mov is unlinked properly,
causing later passes to not notice the mov op at all and thus not cleaning it
up. That makes up a big chunk of the regression the above commit caused.
Keep the deletion of the op where it is, deleting it later unnecessarily blows
up size of the change.
Signed-off-by: Tobias Klausmann
Reviewed-by: Ilia Mirkin
---
.../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index c8f0701572..7243b1d2e4 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -47,8 +47,25 @@ NVC0LegalizeSSA::handleDIV(Instruction *i)
int builtin;
bld.setPosition(i, false);
- bld.mkMovToReg(0, i->getSrc(0));
- bld.mkMovToReg(1, i->getSrc(1));
+
+ // Generate movs to the input regs for the call we want to generate
+ for (int s = 0; i->srcExists(s); ++s) {
+ Instruction *ld = i->getSrc(s)->getInsn();
+ assert(ld->getSrc(0) != NULL);
+ // check if we are moving an immediate, propagate it in that case
+ if (!ld || ld->fixed || (ld->op != OP_LOAD && ld->op != OP_MOV) ||
+!(ld->src(0).getFile() == FILE_IMMEDIATE))
+ bld.mkMovToReg(s, i->getSrc(s));
+ else {
+ bld.mkMovToReg(s, ld->getSrc(0));
+ // Clear the src, to make code elimination possible here before we
+ // delete the instruction i later
+ i->setSrc(s, NULL);
+ if (ld->isDead())
+delete_Instruction(prog, ld);
+ }
+ }
+
switch (i->dType) {
case TYPE_U32: builtin = NVC0_BUILTIN_DIV_U32; break;
case TYPE_S32: builtin = NVC0_BUILTIN_DIV_S32; break;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nvc0: write 0 to pipeline_statistics.cs_invocations
Module: Mesa Branch: master Commit: b672c3833b7ea51c09a6bcbed86b8fb6789448f1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b672c3833b7ea51c09a6bcbed86b8fb6789448f1 Author: Karol Herbst Date: Sun Aug 27 18:00:52 2017 +0200 nvc0: write 0 to pipeline_statistics.cs_invocations cs_invocations are currently unsupported, but leaving the field uninitialized is even worse. fixes on nvc0: * KHR-GL45.pipeline_statistics_query_tests_ARB.functional_default_qo_values * KHR-GL45.pipeline_statistics_query_tests_ARB.functional_non_rendering_commands_do_not_affect_queries Signed-off-by: Karol Herbst Reviewed-by: Ilia Mirkin Cc: mesa-sta...@lists.freedesktop.org --- src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c index 0991af872b..d8d82de865 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c @@ -346,6 +346,7 @@ nvc0_hw_get_query_result(struct nvc0_context *nvc0, struct nvc0_query *q, case PIPE_QUERY_PIPELINE_STATISTICS: for (i = 0; i < 10; ++i) res64[i] = data64[i * 2] - data64[24 + i * 2]; + result->pipeline_statistics.cs_invocations = 0; break; case NVC0_HW_QUERY_TFB_BUFFER_OFFSET: res32[0] = hq->data[1]; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): util: only use SCHED_IDLE in pthread_setschedparam() when it's defined
Module: Mesa
Branch: master
Commit: c92fe8a8c50968a6ac37cbecdd54208f0eea246c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c92fe8a8c50968a6ac37cbecdd54208f0eea246c
Author: Roland Scheidegger
Date: Sat Aug 26 17:08:07 2017 +0200
util: only use SCHED_IDLE in pthread_setschedparam() when it's defined
Fixes build error when it's not.
Reviewed-by: Jose Fonseca
---
src/util/u_queue.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/util/u_queue.c b/src/util/u_queue.c
index 49361c3dad..449da7dc9a 100644
--- a/src/util/u_queue.c
+++ b/src/util/u_queue.c
@@ -246,7 +246,7 @@ util_queue_init(struct util_queue *queue,
}
if (flags & UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY) {
- #if defined(__linux__)
+ #if defined(__linux__) && defined(SCHED_IDLE)
struct sched_param sched_param = {0};
/* The nice() function can only set a maximum of 19.
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): llvmpipe: lp_build_gather_elem_vec BE fix for 3x16 load
Module: Mesa
Branch: master
Commit: 57c8ead0cd08e6aaf88a389f7ce528c4f0face65
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=57c8ead0cd08e6aaf88a389f7ce528c4f0face65
Author: Ben Crocker
Date: Wed Aug 23 16:32:43 2017 -0400
llvmpipe: lp_build_gather_elem_vec BE fix for 3x16 load
Fix loading of a 3x16 vector as a single 48-bit load
on big-endian systems (PPC64, S390).
Roland Scheidegger's commit e827d9175675aaa6cfc0b981e2a80685fb7b3a74
plus Ray Strode's patch reduce pre-Roland Piglit failures from ~4000 to ~2000.
This patch fixes
three of the four regressions observed by Ray:
- draw-vertices
- draw-vertices-half-float
- draw-vertices-half-float_gles2
One regression remains:
- draw-vertices-2101010
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100613
Cc: "17.2" "17.1"
Signed-off-by: Ben Crocker
Reviewed-by: Roland Scheidegger
---
src/gallium/auxiliary/gallivm/lp_bld_gather.c | 30 +--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_gather.c
b/src/gallium/auxiliary/gallivm/lp_bld_gather.c
index ccd03765c7..7d11dcd3b6 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_gather.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_gather.c
@@ -234,13 +234,39 @@ lp_build_gather_elem_vec(struct gallivm_state *gallivm,
*/
res = LLVMBuildZExt(gallivm->builder, res, dst_elem_type, "");
- if (vector_justify) {
#ifdef PIPE_ARCH_BIG_ENDIAN
+ if (vector_justify) {
res = LLVMBuildShl(gallivm->builder, res,
LLVMConstInt(dst_elem_type,
dst_type.width - src_width, 0), "");
-#endif
}
+ if (src_width == 48) {
+/* Load 3x16 bit vector.
+ * The sequence of loads on big-endian hardware proceeds as
follows.
+ * 16-bit fields are denoted by X, Y, Z, and 0. In memory, the
sequence
+ * of three fields appears in the order X, Y, Z.
+ *
+ * Load 32-bit word: 0.0.X.Y
+ * Load 16-bit halfword: 0.0.0.Z
+ * Rotate left: 0.X.Y.0
+ * Bitwise OR: 0.X.Y.Z
+ *
+ * The order in which we need the fields in the result is 0.Z.Y.X,
+ * the same as on little-endian; permute 16-bit fields accordingly
+ * within 64-bit register:
+ */
+LLVMValueRef shuffles[4] = {
+ lp_build_const_int32(gallivm, 2),
+ lp_build_const_int32(gallivm, 1),
+ lp_build_const_int32(gallivm, 0),
+ lp_build_const_int32(gallivm, 3),
+};
+res = LLVMBuildBitCast(gallivm->builder, res,
+ lp_build_vec_type(gallivm,
lp_type_uint_vec(16, 4*16)), "");
+res = LLVMBuildShuffleVector(gallivm->builder, res, res,
LLVMConstVector(shuffles, 4), "");
+res = LLVMBuildBitCast(gallivm->builder, res, dst_elem_type, "");
+ }
+#endif
}
}
return res;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): gallivm: correct channel shift logic on big endian
Module: Mesa
Branch: master
Commit: 75cb6e36178b9474bbb59b76cbbcce2a67bf88d2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=75cb6e36178b9474bbb59b76cbbcce2a67bf88d2
Author: Ray Strode
Date: Wed Aug 23 16:32:42 2017 -0400
gallivm: correct channel shift logic on big endian
lp_build_fetch_rgba_soa fetches a texel from a texture.
Part of that process involves first gathering the element
together from memory into a packed format, and then breaking
out the individual color channels into separate, parallel
arrays.
The code fails to account for endianess when reading the packed
values.
This commit attempts to correct the problem by reversing the order
the packed values are read on big endian systems.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100613
Cc: "17.2" "17.1"
Signed-off-by: Ray Strode
Reviewed-by: Roland Scheidegger
---
src/gallium/auxiliary/gallivm/lp_bld_format_soa.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_format_soa.c
b/src/gallium/auxiliary/gallivm/lp_bld_format_soa.c
index 98eb694c1f..22c19b10db 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_format_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_format_soa.c
@@ -650,7 +650,13 @@ lp_build_fetch_rgba_soa(struct gallivm_state *gallivm,
for (i = 0; i < format_desc->nr_channels; i++) {
struct util_format_channel_description chan_desc =
format_desc->channel[i];
unsigned blockbits = type.width;
-unsigned vec_nr = chan_desc.shift / type.width;
+unsigned vec_nr;
+
+#ifdef PIPE_ARCH_BIG_ENDIAN
+vec_nr = (format_desc->block.bits - (chan_desc.shift +
chan_desc.size)) / type.width;
+#else
+vec_nr = chan_desc.shift / type.width;
+#endif
chan_desc.shift %= type.width;
output[i] = lp_build_extract_soa_chan(&bld,
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv/formats: Nicely handle unknown VkFormat enums
Module: Mesa
Branch: master
Commit: 242211933a06826961709c2689a1d30f735ab7b9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=242211933a06826961709c2689a1d30f735ab7b9
Author: Jason Ekstrand
Date: Thu Jul 27 15:04:25 2017 -0700
anv/formats: Nicely handle unknown VkFormat enums
This fixes some crashes in the dEQP-VK.memory.requirements.core.* tests.
I'm not sure whether or not passing out-of-bound formats into the query
is supposed to be allowed but there's no harm in protecting ourselves
from it.
Reviewed-by: Lionel Landwerlin
Bugzilla: https://bugs.freedesktop.org/101956
Cc: mesa-sta...@lists.freedesktop.org
---
src/intel/vulkan/anv_formats.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 6ce609ae8d..c23b143cac 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -250,6 +250,15 @@ static const struct anv_format anv_formats[] = {
#undef fmt
+static bool
+format_supported(VkFormat vk_format)
+{
+ if (vk_format > ARRAY_SIZE(anv_formats))
+ return false;
+
+ return anv_formats[vk_format].isl_format != ISL_FORMAT_UNSUPPORTED;
+}
+
/**
* Exactly one bit must be set in \a aspect.
*/
@@ -257,10 +266,10 @@ struct anv_format
anv_get_format(const struct gen_device_info *devinfo, VkFormat vk_format,
VkImageAspectFlags aspect, VkImageTiling tiling)
{
- struct anv_format format = anv_formats[vk_format];
+ if (!format_supported(vk_format))
+ return anv_formats[VK_FORMAT_UNDEFINED];
- if (format.isl_format == ISL_FORMAT_UNSUPPORTED)
- return format;
+ struct anv_format format = anv_formats[vk_format];
if (aspect == VK_IMAGE_ASPECT_STENCIL_BIT) {
assert(vk_format_aspects(vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT);
@@ -391,7 +400,7 @@ anv_physical_device_get_format_properties(struct
anv_physical_device *physical_d
gen += 5;
VkFormatFeatureFlags linear = 0, tiled = 0, buffer = 0;
- if (anv_formats[format].isl_format == ISL_FORMAT_UNSUPPORTED) {
+ if (!format_supported(format)) {
/* Nothing to do here */
} else if (vk_format_is_depth_or_stencil(format)) {
tiled |= VK_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT;
@@ -489,7 +498,7 @@ anv_get_image_format_properties(
uint32_t maxArraySize;
VkSampleCountFlags sampleCounts = VK_SAMPLE_COUNT_1_BIT;
- if (anv_formats[info->format].isl_format == ISL_FORMAT_UNSUPPORTED)
+ if (!format_supported(info->format))
goto unsupported;
anv_physical_device_get_format_properties(physical_device, info->format,
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): vbo: fix offset in minmax cache key
Module: Mesa
Branch: master
Commit: 2d93b462b4d978b0da417b35a7470e336bc4e783
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d93b462b4d978b0da417b35a7470e336bc4e783
Author: Charmaine Lee
Date: Wed Aug 30 14:26:41 2017 -0700
vbo: fix offset in minmax cache key
Instead of saving primitive offset in the minmax cache key,
save the actual buffer offset which is used in the cache lookup.
Fixes rendering artifact seen with GoogleEarth when run with
VMware driver.
v2: Per Brian's comment, initialize offset to avoid compiler warning.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Brian Paul
---
src/mesa/vbo/vbo_minmax_index.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/mesa/vbo/vbo_minmax_index.c b/src/mesa/vbo/vbo_minmax_index.c
index 4c17a08662..58a2af49ac 100644
--- a/src/mesa/vbo/vbo_minmax_index.c
+++ b/src/mesa/vbo/vbo_minmax_index.c
@@ -245,6 +245,7 @@ vbo_get_minmax_index(struct gl_context *ctx,
_mesa_primitive_restart_index(ctx, ib->index_size);
const char *indices;
GLuint i;
+ GLintptr offset = 0;
indices = (char *) ib->ptr + prim->start * ib->index_size;
if (_mesa_is_bufferobj(ib->obj)) {
@@ -254,7 +255,8 @@ vbo_get_minmax_index(struct gl_context *ctx,
count, min_index, max_index))
return;
- indices = ctx->Driver.MapBufferRange(ctx, (GLintptr) indices, size,
+ offset = indices;
+ indices = ctx->Driver.MapBufferRange(ctx, offset, size,
GL_MAP_READ_BIT, ib->obj,
MAP_INTERNAL);
}
@@ -337,8 +339,8 @@ vbo_get_minmax_index(struct gl_context *ctx,
}
if (_mesa_is_bufferobj(ib->obj)) {
- vbo_minmax_cache_store(ctx, ib->obj, ib->index_size, prim->start, count,
- *min_index, *max_index);
+ vbo_minmax_cache_store(ctx, ib->obj, ib->index_size, offset,
+ count, *min_index, *max_index);
ctx->Driver.UnmapBuffer(ctx, ib->obj, MAP_INTERNAL);
}
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv: fix build errors on android
Module: Mesa
Branch: master
Commit: 15b61dec94ceccd66bcbeb8c22c7f2019de7f173
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=15b61dec94ceccd66bcbeb8c22c7f2019de7f173
Author: Tapani Pälli
Date: Thu Aug 31 08:52:27 2017 +0300
anv: fix build errors on android
error: incompatible pointer to integer conversion initializing 'VkFence'
(aka 'unsigned long long') with an expression of type 'void *'
[-Werror,-Wint-conversion]
Signed-off-by: Tapani Pälli
Reviewed-by: Samuel Iglesias Gonsálvez
Reviewed-by: Jason Ekstrand
---
src/intel/vulkan/anv_queue.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/intel/vulkan/anv_queue.c b/src/intel/vulkan/anv_queue.c
index 429bac9739..21ca66757e 100644
--- a/src/intel/vulkan/anv_queue.c
+++ b/src/intel/vulkan/anv_queue.c
@@ -169,7 +169,7 @@ VkResult anv_QueueSubmit(
for (uint32_t i = 0; i < submitCount; i++) {
/* Fence for this submit. NULL for all but the last one */
- VkFence submit_fence = (i == submitCount - 1) ? fence : NULL;
+ VkFence submit_fence = (i == submitCount - 1) ? fence : VK_NULL_HANDLE;
if (pSubmits[i].commandBufferCount == 0) {
/* If we don't have any command buffers, we need to submit a dummy
@@ -197,7 +197,8 @@ VkResult anv_QueueSubmit(
/* Fence for this execbuf. NULL for all but the last one */
VkFence execbuf_fence =
-(j == pSubmits[i].commandBufferCount - 1) ? submit_fence : NULL;
+(j == pSubmits[i].commandBufferCount - 1) ?
+submit_fence : VK_NULL_HANDLE;
const VkSemaphore *in_semaphores = NULL, *out_semaphores = NULL;
uint32_t num_in_semaphores = 0, num_out_semaphores = 0;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: set a per-buffer flag that disables inter-process sharing (v4)
Module: Mesa
Branch: master
Commit: 8b3a257851905ff444d981e52938cbf2b36ba830
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b3a257851905ff444d981e52938cbf2b36ba830
Author: Marek Olšák
Date: Tue Jul 18 16:08:44 2017 -0400
radeonsi: set a per-buffer flag that disables inter-process sharing (v4)
For lower overhead in the CS ioctl.
Winsys allocators are not used with interprocess-sharable resources.
v2: It shouldn't crash anymore, but the kernel will reject the new flag.
v3 (christian): Rename the flag, avoid sending those buffers in the BO list.
v4 (christian): Remove setting the kernel flag for now
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeon/r600_buffer_common.c | 7 ++
src/gallium/drivers/radeon/radeon_winsys.h | 20 +
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 30 ++---
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 27 +-
4 files changed, 56 insertions(+), 28 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c
b/src/gallium/drivers/radeon/r600_buffer_common.c
index 076faa9330..4f5e17d5c8 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -167,6 +167,13 @@ void r600_init_resource_fields(struct r600_common_screen
*rscreen,
RADEON_FLAG_GTT_WC;
}
+ /* Only displayable single-sample textures can be shared between
+* processes. */
+ if (res->b.b.target == PIPE_BUFFER ||
+ res->b.b.nr_samples >= 2 ||
+ rtex->surface.micro_tile_mode != RADEON_MICRO_MODE_DISPLAY)
+ res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
+
/* If VRAM is just stolen system memory, allow both VRAM and
* GTT, whichever has free space. If a buffer is evicted from
* VRAM to GTT, it will stay there.
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index b00b1443e7..f0a0a922a1 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -54,6 +54,7 @@ enum radeon_bo_flag { /* bitfield */
RADEON_FLAG_NO_CPU_ACCESS = (1 << 1),
RADEON_FLAG_NO_SUBALLOC = (1 << 2),
RADEON_FLAG_SPARSE =(1 << 3),
+RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 4),
};
enum radeon_bo_usage { /* bitfield */
@@ -661,14 +662,19 @@ static inline unsigned radeon_flags_from_heap(enum
radeon_heap heap)
{
switch (heap) {
case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
-return RADEON_FLAG_GTT_WC | RADEON_FLAG_NO_CPU_ACCESS;
+return RADEON_FLAG_GTT_WC |
+ RADEON_FLAG_NO_CPU_ACCESS |
+ RADEON_FLAG_NO_INTERPROCESS_SHARING;
+
case RADEON_HEAP_VRAM:
case RADEON_HEAP_VRAM_GTT:
case RADEON_HEAP_GTT_WC:
-return RADEON_FLAG_GTT_WC;
+return RADEON_FLAG_GTT_WC |
+ RADEON_FLAG_NO_INTERPROCESS_SHARING;
+
case RADEON_HEAP_GTT:
default:
-return 0;
+return RADEON_FLAG_NO_INTERPROCESS_SHARING;
}
}
@@ -700,8 +706,14 @@ static inline int radeon_get_heap_index(enum
radeon_bo_domain domain,
/* NO_CPU_ACCESS implies VRAM only. */
assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain ==
RADEON_DOMAIN_VRAM);
+/* Resources with interprocess sharing don't use any winsys allocators. */
+if (!(flags & RADEON_FLAG_NO_INTERPROCESS_SHARING))
+return -1;
+
/* Unsupported flags: NO_SUBALLOC, SPARSE. */
-if (flags & ~(RADEON_FLAG_GTT_WC | RADEON_FLAG_NO_CPU_ACCESS))
+if (flags & ~(RADEON_FLAG_GTT_WC |
+ RADEON_FLAG_NO_CPU_ACCESS |
+ RADEON_FLAG_NO_INTERPROCESS_SHARING))
return -1;
switch (domain) {
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 1323be8356..883a7c18e3 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -1138,7 +1138,7 @@ amdgpu_bo_create(struct radeon_winsys *rws,
{
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
struct amdgpu_winsys_bo *bo;
- unsigned usage = 0, pb_cache_bucket;
+ unsigned usage = 0, pb_cache_bucket = 0;
/* VRAM implies WC. This is not optional. */
assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
@@ -1193,19 +1193,23 @@ no_slab:
size = align64(size, ws->info.gart_page_size);
alignment = align(alignment, ws->info.gart_page_size);
- int heap = radeon_get_heap_index(domain, flags);
- assert(heap >= 0 && heap < RADEON_MAX_CACHED_HEAPS);
- usage = 1 << heap; /* Only set one usage bit for each heap. */
+ bool use_reusable_pool = flags & RADEON_FLAG_NO_INTERPROCESS_SHARING;
- pb_cache_bucket = radeon_get_pb_cache_bucket_index(heap);
- assert(pb_cache_bucket < ARRAY_SIZE(ws->bo_cache.buckets));
+ if (use_reusable_pool) {
+ int heap = radeon_get_hea
Mesa (master): winsys/amdgpu: set AMDGPU_GEM_CREATE_VM_ALWAYS_VALID if possible v2
Module: Mesa
Branch: master
Commit: 214b565bc28bc4419f3eec29ab7bbe34080459fe
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=214b565bc28bc4419f3eec29ab7bbe34080459fe
Author: Christian König
Date: Tue Aug 29 16:45:46 2017 +0200
winsys/amdgpu: set AMDGPU_GEM_CREATE_VM_ALWAYS_VALID if possible v2
When the kernel supports it set the local flag and
stop adding those BOs to the BO list.
Can probably be optimized much more.
v2: rename new flag to AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
Reviewed-by: Marek Olšák
---
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 8
src/gallium/winsys/amdgpu/drm/amdgpu_bo.h | 2 ++
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 22 +-
3 files changed, 27 insertions(+), 5 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 883a7c18e3..897b4f0596 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -38,6 +38,10 @@
#include
#include
+#ifndef AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
+#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
+#endif
+
/* Set to 1 for verbose output showing committed sparse buffer ranges. */
#define DEBUG_SPARSE_COMMITS 0
@@ -406,6 +410,9 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct
amdgpu_winsys *ws,
request.flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
if (flags & RADEON_FLAG_GTT_WC)
request.flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
+ if (flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
+ ws->info.drm_minor >= 20)
+ request.flags |= AMDGPU_GEM_CREATE_VM_ALWAYS_VALID;
r = amdgpu_bo_alloc(ws->dev, &request, &buf_handle);
if (r) {
@@ -439,6 +446,7 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct
amdgpu_winsys *ws,
bo->u.real.va_handle = va_handle;
bo->initial_domain = initial_domain;
bo->unique_id = __sync_fetch_and_add(&ws->next_bo_unique_id, 1);
+ bo->is_local = !!(request.flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID);
if (initial_domain & RADEON_DOMAIN_VRAM)
ws->allocated_vram += align64(size, ws->info.gart_page_size);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
index 1311344b81..10b095d7a1 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
@@ -115,6 +115,8 @@ struct amdgpu_winsys_bo {
unsigned num_fences;
unsigned max_fences;
struct pipe_fence_handle **fences;
+
+ bool is_local;
};
struct amdgpu_slab {
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 5ddde8e794..f68071abc8 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -1121,6 +1121,8 @@ void amdgpu_cs_submit_ib(void *job, int thread_index)
free(handles);
mtx_unlock(&ws->global_bo_list_lock);
} else {
+ unsigned num_handles;
+
if (!amdgpu_add_sparse_backing_buffers(cs)) {
r = -ENOMEM;
goto bo_list_error;
@@ -1140,21 +1142,31 @@ void amdgpu_cs_submit_ib(void *job, int thread_index)
}
}
+ num_handles = 0;
for (i = 0; i < cs->num_real_buffers; ++i) {
struct amdgpu_cs_buffer *buffer = &cs->real_buffers[i];
+if (buffer->bo->is_local)
+continue;
+
assert(buffer->u.real.priority_usage != 0);
- cs->handles[i] = buffer->bo->bo;
- cs->flags[i] = (util_last_bit64(buffer->u.real.priority_usage) - 1) /
4;
+ cs->handles[num_handles] = buffer->bo->bo;
+ cs->flags[num_handles] =
(util_last_bit64(buffer->u.real.priority_usage) - 1) / 4;
+++num_handles;
}
if (acs->ring_type == RING_GFX)
ws->gfx_bo_list_counter += cs->num_real_buffers;
- r = amdgpu_bo_list_create(ws->dev, cs->num_real_buffers,
-cs->handles, cs->flags,
-&cs->request.resources);
+ if (num_handles) {
+ r = amdgpu_bo_list_create(ws->dev, num_handles,
+ cs->handles, cs->flags,
+ &cs->request.resources);
+ } else {
+ r = 0;
+cs->request.resources = 0;
+ }
}
bo_list_error:
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa: tag mesa-17.2.0-rc6: mesa-17.2.0-rc6
Module: Mesa Branch: refs/tags/mesa-17.2.0-rc6 Tag:56c821e5d88dbcca0186316649389503571dce0d URL: http://cgit.freedesktop.org/mesa/mesa/tag/?id=56c821e5d88dbcca0186316649389503571dce0d Tagger: Emil Velikov Date: Thu Aug 31 10:10:40 2017 +0100 mesa-17.2.0-rc6 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (17.2): 56 new commits
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=909f2b6aa26b29514724d958eb1bd2d2b3c68438
Author: Emil Velikov
Date: Thu Aug 31 10:06:29 2017 +0100
Update version to 17.2.0-rc6
Signed-off-by: Emil Velikov
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3666d9ab994ba58ac8b7d6a4d2b6a554953c2442
Author: Emil Velikov
Date: Sun Aug 27 11:20:35 2017 +0100
egl/wayland: make sure HAS_$FORMAT is set for wl_dmabuf
Otherwise eglCreateWaylandBufferFromImageWL will fail, since we
have no "supported" format.
Fixes: 02cc35937277 ("egl/wayland: Use linux-dmabuf interface for buffers")
Signed-off-by: Emil Velikov
Reviewed-by: Daniel Stone
(cherry picked from commit 9e07005e8709a51f9236e78e8d47d71ab3243e4d)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5303f0c2468f47392e5bc580b55b2d3b245258d7
Author: Emil Velikov
Date: Sun Aug 27 11:20:32 2017 +0100
egl/wayland: set correct format with wl_dmabuf as wl_drm is missing
For most/all cases today, we have wl_drm available alongside wl_dmabuf.
Yet in the long run, we want to make sure the latter can operate without
any traces of the former.
Fixes: 02cc35937277 ("egl/wayland: Use linux-dmabuf interface for buffers")
Signed-off-by: Emil Velikov
Reviewed-by: Daniel Stone
(cherry picked from commit da100fe6970ac8ca34ced69c6c5dfe8a4f5bec90)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d51747dc07ad2b64b028ffe0d3416c1271d5d26
Author: Emil Velikov
Date: Sun Aug 27 11:20:28 2017 +0100
egl/wayland: polish object teardown in dri2_wl_destroy_surface
The wl_drm wrapper is created before the wl display/surface ones.
Thus make sure we destroy it after them. In reality it should not make
any difference either way.
Fixes: 03dd9a88b0b ("egl/wayland: Use per-surface event queues")
Signed-off-by: Emil Velikov
Reviewed-by: Daniel Stone
(cherry picked from commit 1a8015e753c6f52b24a473ea60e3ce0b38de7d42)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b41bef9a420325623fa50a1103075a24f56eb0f
Author: Emil Velikov
Date: Sun Aug 27 11:20:27 2017 +0100
egl/wayland: plug leaks in dri2_wl_create_window_surface() error path
We forgot to teardown the wl display/surface wrappers.
Fixes: 03dd9a88b0b ("egl/wayland: Use per-surface event queues")
Signed-off-by: Emil Velikov
Reviewed-by: Daniel Stone
(cherry picked from commit 83442112d7136b6d0c2f6d84c409c04664aeb154)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e040bdbc8a8d8170d54fcad5cb084d5ff9008f3b
Author: Grazvydas Ignotas
Date: Mon Aug 28 02:01:21 2017 +0300
radv: clear dynamic_shader_stages on create
Valgrind reports it's being used uninitialized.
Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Signed-off-by: Grazvydas Ignotas
Reviewed-by: Bas Nieuwenhuizen
(cherry picked from commit 77803748336713854a4ade192253c0ba01c49047)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e4c4b0dbcbd037ccf3abc40bb168d68c30e8c40e
Author: Dave Airlie
Date: Tue Aug 15 15:35:52 2017 +1000
radv/wsi: Compute correct row_pitch for GFX9.
(commit split out by Bas Nieuwenhuizen)
Fixes: 65477bae9cf "radv: enable GFX9 on radv"
Reviewed-by: Bas Nieuwenhuizen
(cherry picked from commit 9573bd70e1e7e32527d9c40716174c30fcc9720e)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca9817a6e87bbbd6bb8a9d5218068d6dc2417063
Author: Emil Velikov
Date: Mon Aug 7 17:23:19 2017 +0100
egl: don't NULL deref the .get_capabilities function pointer
One could easily introduce version 3 of the DRI2fenceExtension,
extending the struct, while not implementing the above function.
Thus we'll end up with NULL pointer, and dereferencing it won't fare
too well.
Fixes: 0201f01dc4e ("egl: add EGL_ANDROID_native_fence_sync")
Cc: Rob Clark
Signed-off-by: Emil Velikov
Reviewed-by: Tapani Pälli
(cherry picked from commit f0d053cb6dda908d554d84629bd98e05d383a8f6)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=df8e65feb7980319b7e6d382990a8f44cefb8bf4
Author: Bas Nieuwenhuizen
Date: Fri Aug 25 22:18:24 2017 +0200
radv: Fix sparse BO mapping merging.
If we merge a mapping with the mapping before it, we also need
to not only change the offset, but also the bo offset.
Fixes: 715df30a4e2 "radv/amdgpu: Add winsys implementation of virtual
buffers."
Reviewed-by: Dave Airlie
(cherry picked from commit 9b7e663da1d88f398a349e158c27b38a66b73fe3)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec94b874c4758e558aceb0fdfb23d9bf70d2f1cc
Author: Bas Nieuwenhuizen
Date: Fri Aug 25 14:14:12 2017 +0200
radv: Fix off by one in MAX_VBS assert.
e.g. 0 + 32 <= 32 should be valid.
Fixes: f4e499ec791 "radv: add ini
