Mesa (master): glsl: cleanup shader_cache header guard
Module: Mesa Branch: master Commit: f2c0e47d9cf3fa86cdf746beb862164bf0056e20 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2c0e47d9cf3fa86cdf746beb862164bf0056e20 Author: Tapani Pälli Date: Thu Dec 28 09:30:08 2017 +0200 glsl: cleanup shader_cache header guard Signed-off-by: Tapani Pälli Reviewed-by: Timothy Arceri --- src/compiler/glsl/shader_cache.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/compiler/glsl/shader_cache.h b/src/compiler/glsl/shader_cache.h index c0598f37e8..eeefb3aeb2 100644 --- a/src/compiler/glsl/shader_cache.h +++ b/src/compiler/glsl/shader_cache.h @@ -21,8 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef SHADER_CACHE -#define SHADER_CACHE +#ifndef SHADER_CACHE_H +#define SHADER_CACHE_H #include "util/disk_cache.h" @@ -34,4 +34,4 @@ bool shader_cache_read_program_metadata(struct gl_context *ctx, struct gl_shader_program *prog); -#endif /* GLSL_SYMBOL_TABLE */ +#endif /* SHADER_CACHE_H */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv: fix maxDescriptorSet* limits
Module: Mesa Branch: master Commit: c0816389c24384abf2571d60d0cb4c23055f3780 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0816389c24384abf2571d60d0cb4c23055f3780 Author: Samuel Iglesias Gonsálvez Date: Wed Jan 10 09:15:50 2018 +0100 anv: fix maxDescriptorSet* limits "The maxDescriptorSet* limit is n times the corresponding maxPerStageDescriptor* limit, where n is the number of shader stages supported by the VkPhysicalDevice. If all shader stages are supported, n = 6 (vertex, tessellation control, tessellation evaluation, geometry, fragment, compute)." Fixes: dEQP-VK.api.info.device.properties Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Jason Ekstrand --- src/intel/vulkan/anv_device.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 680f5a752d..90fdda66c5 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -797,13 +797,13 @@ void anv_GetPhysicalDeviceProperties( .maxPerStageDescriptorStorageImages = 64, .maxPerStageDescriptorInputAttachments= 64, .maxPerStageResources = 250, - .maxDescriptorSetSamplers = 256, - .maxDescriptorSetUniformBuffers = 256, + .maxDescriptorSetSamplers = 6 * max_samplers, /* number of stages * maxPerStageDescriptorSamplers */ + .maxDescriptorSetUniformBuffers = 6 * 64, /* number of stages * maxPerStageDescriptorUniformBuffers */ .maxDescriptorSetUniformBuffersDynamic= MAX_DYNAMIC_BUFFERS / 2, - .maxDescriptorSetStorageBuffers = 256, + .maxDescriptorSetStorageBuffers = 6 * 64, /* number of stages * maxPerStageDescriptorStorageBuffers */ .maxDescriptorSetStorageBuffersDynamic= MAX_DYNAMIC_BUFFERS / 2, - .maxDescriptorSetSampledImages= 256, - .maxDescriptorSetStorageImages= 256, + .maxDescriptorSetSampledImages= 6 * max_samplers, /* number of stages * maxPerStageDescriptorSampledImages */ + .maxDescriptorSetStorageImages= 6 * 64, /* number of stages * maxPerStageDescriptorStorageImages */ .maxDescriptorSetInputAttachments = 256, .maxVertexInputAttributes = MAX_VBS, .maxVertexInputBindings = MAX_VBS, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): ac: add load_patch_vertices_in() to the abi
Module: Mesa
Branch: master
Commit: c797cd605ac9cb42795a40b1967b6dd10184b763
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c797cd605ac9cb42795a40b1967b6dd10184b763
Author: Timothy Arceri
Date: Wed Jan 10 17:01:10 2018 +1100
ac: add load_patch_vertices_in() to the abi
Fixes the follow test for radeonsi nir:
tests/spec/arb_tessellation_shader/execution/quads.shader_test
Also stops 8 other tests from crashing, they now just fail e.g.
tcs-output-array-float-index-rd-after-barrier.shader_test
Reviewed-by: Marek Olšák
Reviewed-by: Samuel Pitoiset
---
src/amd/common/ac_nir_to_llvm.c | 11 ++-
src/amd/common/ac_shader_abi.h | 2 ++
src/gallium/drivers/radeonsi/si_shader.c | 20 ++--
3 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 8301b16057..7153c9708d 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4166,6 +4166,13 @@ load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef
type,
return LLVMBuildBitCast(ctx->builder, result, type, "");
}
+static LLVMValueRef
+load_patch_vertices_in(struct ac_shader_abi *abi)
+{
+ struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+ return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices,
false);
+}
+
static void visit_intrinsic(struct ac_nir_context *ctx,
nir_intrinsic_instr *instr)
{
@@ -4366,7 +4373,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
result = ctx->abi->load_tess_level(ctx->abi,
VARYING_SLOT_TESS_LEVEL_INNER);
break;
case nir_intrinsic_load_patch_vertices_in:
- result = LLVMConstInt(ctx->ac.i32,
ctx->nctx->options->key.tcs.input_vertices, false);
+ result = ctx->abi->load_patch_vertices_in(ctx->abi);
break;
default:
fprintf(stderr, "Unknown intrinsic: ");
@@ -6698,11 +6705,13 @@ LLVMModuleRef
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
ctx.tcs_patch_outputs_read =
shaders[i]->info.patch_outputs_read;
ctx.abi.load_tess_inputs = load_tcs_input;
+ ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
ctx.abi.store_tcs_outputs = store_tcs_output;
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
ctx.tes_primitive_mode =
shaders[i]->info.tess.primitive_mode;
ctx.abi.load_tess_inputs = load_tes_input;
ctx.abi.load_tess_coord = load_tess_coord;
+ ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
if (shader_info->info.vs.needs_instance_id) {
if (ctx.ac.chip_class == GFX9 &&
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index e3a47089a5..06e61207ec 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -103,6 +103,8 @@ struct ac_shader_abi {
LLVMTypeRef type,
unsigned num_components);
+ LLVMValueRef (*load_patch_vertices_in)(struct ac_shader_abi *abi);
+
LLVMValueRef (*load_tess_level)(struct ac_shader_abi *abi,
unsigned varying_id);
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 86f3f7a8ba..dd635ae203 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1955,6 +1955,17 @@ static LLVMValueRef si_load_tess_level(struct
ac_shader_abi *abi,
}
+static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
+{
+ struct si_shader_context *ctx = si_shader_context_from_abi(abi);
+ if (ctx->type == PIPE_SHADER_TESS_CTRL)
+ return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
+ else if (ctx->type == PIPE_SHADER_TESS_EVAL)
+ return get_num_tcs_out_vertices(ctx);
+ else
+ assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
+}
+
void si_load_system_value(struct si_shader_context *ctx,
unsigned index,
const struct tgsi_full_declaration *decl)
@@ -2063,12 +2074,7 @@ void si_load_system_value(struct si_shader_context *ctx,
break;
case TGSI_SEMANTIC_VERTICESIN:
- if (ctx->type == PIPE_SHADER_TESS_CTRL)
- value = unpack_param(ctx,
ctx->param_tcs_out_lds_layout, 26, 6);
- else if (ctx->type == PIPE_SHADER_TESS_EVAL)
-
Mesa (master): ac/nir: Sanitize location_frac for local variables.
Module: Mesa
Branch: master
Commit: 67e09c8b451e1db8bd901279160b982b0df0fa41
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=67e09c8b451e1db8bd901279160b982b0df0fa41
Author: Bas Nieuwenhuizen
Date: Wed Jan 10 17:05:10 2018 +0100
ac/nir: Sanitize location_frac for local variables.
If they were promoted from inputs/outputs, they could have a
non-zero value left over, which messed with our store handling.
Fixes: 06f05040eb "radv: Link shaders."
Reviewed-by: Timothy Arceri
---
src/amd/common/ac_nir_to_llvm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 5885c70ef8..8301b16057 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -5556,6 +5556,7 @@ setup_locals(struct ac_nir_context *ctx,
nir_foreach_variable(variable, &func->impl->locals) {
unsigned attrib_count =
glsl_count_attribute_slots(variable->type, false);
variable->data.driver_location = ctx->num_locals * 4;
+ variable->data.location_frac = 0;
ctx->num_locals += attrib_count;
}
ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
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Mesa (master): tgsi: include struct definitions for tgsi_build declarations
Module: Mesa
Branch: master
Commit: af8fd389961aabdac0a5b0e6171b17950a659f30
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=af8fd389961aabdac0a5b0e6171b17950a659f30
Author: Rob Herring
Date: Mon Jan 8 15:17:48 2018 -0600
tgsi: include struct definitions for tgsi_build declarations
Many of the functions declared in tgsi_build.h return structs (not struct
pointers). Therefore the full struct definitions are needed to avoid
warnings or errors:
In file included from
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp:23:
external/mesa3d/src/gallium/auxiliary/tgsi/tgsi_build.h:47:1: error:
'tgsi_build_header' has C-linkage specified, but returns incomplete type
'struct tgsi_header' which could be incompatible with C
[-Werror,-Wreturn-type-c-linkage]
This error shows up on Android builds using clang and -Werror.
Cc: Ilia Mirkin
Signed-off-by: Rob Herring
---
src/gallium/auxiliary/tgsi/tgsi_build.h | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_build.h
b/src/gallium/auxiliary/tgsi/tgsi_build.h
index 53f31932c0..31de76fe53 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_build.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_build.h
@@ -28,11 +28,7 @@
#ifndef TGSI_BUILD_H
#define TGSI_BUILD_H
-
-struct tgsi_token;
-struct tgsi_full_dst_register;
-struct tgsi_full_src_register;
-
+#include "tgsi/tgsi_parse.h"
#if defined __cplusplus
extern "C" {
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Mesa (master): swr: Handle indirect indices in GS
Module: Mesa
Branch: master
Commit: 5c4081d66d4a45d20e7520c6b6411135780b6bdd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c4081d66d4a45d20e7520c6b6411135780b6bdd
Author: George Kyriazis
Date: Wed Dec 20 13:56:45 2017 -0600
swr: Handle indirect indices in GS
BuilderSWR::swr_gs_llvm_fetch_input() (and consequently
swr_gs_llvm_fetch_input()), did not handle the case where
is_vindex_indirect or is_aindex_direct is set.
Implement it, using the code in draw_llvm.c as a guideline.
Fixes the following piglit tests:
dynamic_input_array_index (crash)
gs-input-array-vec4-index-rd
vs-output-array-vec4-index-wr-before-gs
Reviewed-by: Bruce Cherniak
---
src/gallium/drivers/swr/swr_shader.cpp | 47 --
1 file changed, 39 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/swr/swr_shader.cpp
b/src/gallium/drivers/swr/swr_shader.cpp
index 599dc43698..257a6aae30 100644
--- a/src/gallium/drivers/swr/swr_shader.cpp
+++ b/src/gallium/drivers/swr/swr_shader.cpp
@@ -339,22 +339,53 @@ BuilderSWR::swr_gs_llvm_fetch_input(const struct
lp_build_tgsi_gs_iface *gs_ifac
LLVMValueRef swizzle_index)
{
swr_gs_llvm_iface *iface = (swr_gs_llvm_iface*)gs_iface;
+Value *vert_index = unwrap(vertex_index);
+Value *attr_index = unwrap(attrib_index);
IRB()->SetInsertPoint(unwrap(LLVMGetInsertBlock(gallivm->builder)));
-assert(is_vindex_indirect == false && is_aindex_indirect == false);
+if (is_vindex_indirect || is_aindex_indirect) {
+ int i;
+ Value *res = unwrap(bld_base->base.zero);
+ struct lp_type type = bld_base->base.type;
-Value *attrib =
- LOAD(GEP(iface->pVtxAttribMap, {C(0), unwrap(attrib_index)}));
+ for (i = 0; i < type.length; i++) {
+ Value *vert_chan_index = vert_index;
+ Value *attr_chan_index = attr_index;
-Value *pVertex = LOAD(iface->pGsCtx, {0, SWR_GS_CONTEXT_pVerts});
-Value *pInputVertStride = LOAD(iface->pGsCtx, {0,
SWR_GS_CONTEXT_inputVertStride});
+ if (is_vindex_indirect) {
+ vert_chan_index = VEXTRACT(vert_index, C(i));
+ }
+ if (is_aindex_indirect) {
+ attr_chan_index = VEXTRACT(attr_index, C(i));
+ }
+
+ Value *attrib =
+ LOAD(GEP(iface->pVtxAttribMap, {C(0), attr_chan_index}));
+
+ Value *pVertex = LOAD(iface->pGsCtx, {0, SWR_GS_CONTEXT_pVerts});
+ Value *pInputVertStride = LOAD(iface->pGsCtx, {0,
SWR_GS_CONTEXT_inputVertStride});
+
+ Value *pVector = ADD(MUL(vert_chan_index, pInputVertStride), attrib);
+ Value *pInput = LOAD(GEP(pVertex, {pVector, unwrap(swizzle_index)}));
-Value *pVector = ADD(MUL(unwrap(vertex_index), pInputVertStride), attrib);
+ Value *value = VEXTRACT(pInput, C(i));
+ res = VINSERT(res, value, C(i));
+ }
+
+ return wrap(res);
+} else {
+ Value *attrib = LOAD(GEP(iface->pVtxAttribMap, {C(0), attr_index}));
+
+ Value *pVertex = LOAD(iface->pGsCtx, {0, SWR_GS_CONTEXT_pVerts});
+ Value *pInputVertStride = LOAD(iface->pGsCtx, {0,
SWR_GS_CONTEXT_inputVertStride});
-Value *pInput = LOAD(GEP(pVertex, {pVector, unwrap(swizzle_index)}));
+ Value *pVector = ADD(MUL(vert_index, pInputVertStride), attrib);
-return wrap(pInput);
+ Value *pInput = LOAD(GEP(pVertex, {pVector, unwrap(swizzle_index)}));
+
+ return wrap(pInput);
+}
}
// GS output stream layout
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Mesa (master): amd/common: import get_{load,store}_intr_attribs() from RadeonSI
Module: Mesa
Branch: master
Commit: 7239e265ebe200891f161a07337cd31a92bf6ff8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7239e265ebe200891f161a07337cd31a92bf6ff8
Author: Samuel Pitoiset
Date: Wed Jan 10 12:57:19 2018 +0100
amd/common: import get_{load,store}_intr_attribs() from RadeonSI
v2: move those helpers to the header and use static inline
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen (v1)
---
src/amd/common/ac_llvm_build.c| 12 ++-
src/amd/common/ac_llvm_util.h | 18
src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c | 26 +--
3 files changed, 25 insertions(+), 31 deletions(-)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index efc6fa12e5..07044142b0 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -983,11 +983,7 @@ ac_build_buffer_load(struct ac_llvm_context *ctx,
return ac_build_intrinsic(ctx, name, types[func], args,
ARRAY_SIZE(args),
- /* READNONE means writes can't affect it,
while
- * READONLY means that writes can affect it.
*/
- can_speculate && HAVE_LLVM >= 0x0400 ?
- AC_FUNC_ATTR_READNONE :
- AC_FUNC_ATTR_READONLY);
+ ac_get_load_intr_attribs(can_speculate));
}
LLVMValueRef ac_build_buffer_load_format(struct ac_llvm_context *ctx,
@@ -1007,11 +1003,7 @@ LLVMValueRef ac_build_buffer_load_format(struct
ac_llvm_context *ctx,
return ac_build_intrinsic(ctx,
"llvm.amdgcn.buffer.load.format.v4f32",
ctx->v4f32, args, ARRAY_SIZE(args),
- /* READNONE means writes can't affect it,
while
- * READONLY means that writes can affect it.
*/
- can_speculate && HAVE_LLVM >= 0x0400 ?
- AC_FUNC_ATTR_READNONE :
- AC_FUNC_ATTR_READONLY);
+ ac_get_load_intr_attribs(can_speculate));
}
/**
diff --git a/src/amd/common/ac_llvm_util.h b/src/amd/common/ac_llvm_util.h
index 7c8b6b0a13..61bcc4e54e 100644
--- a/src/amd/common/ac_llvm_util.h
+++ b/src/amd/common/ac_llvm_util.h
@@ -81,6 +81,24 @@ void
ac_llvm_add_target_dep_function_attr(LLVMValueRef F,
const char *name, int value);
+static inline unsigned
+ac_get_load_intr_attribs(bool can_speculate)
+{
+ /* READNONE means writes can't affect it, while READONLY means that
+* writes can affect it. */
+ return can_speculate && HAVE_LLVM >= 0x0400 ?
+AC_FUNC_ATTR_READNONE :
+AC_FUNC_ATTR_READONLY;
+}
+
+static inline unsigned
+ac_get_store_intr_attribs(bool writeonly_memory)
+{
+ return writeonly_memory && HAVE_LLVM >= 0x0400 ?
+ AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
+ AC_FUNC_ATTR_WRITEONLY;
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
index fe0cfcef99..d5c9470974 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
@@ -390,22 +390,6 @@ static void load_fetch_args(
}
}
-static unsigned get_load_intr_attribs(bool can_speculate)
-{
- /* READNONE means writes can't affect it, while READONLY means that
-* writes can affect it. */
- return can_speculate && HAVE_LLVM >= 0x0400 ?
-LP_FUNC_ATTR_READNONE :
-LP_FUNC_ATTR_READONLY;
-}
-
-static unsigned get_store_intr_attribs(bool writeonly_memory)
-{
- return writeonly_memory && HAVE_LLVM >= 0x0400 ?
- LP_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
- LP_FUNC_ATTR_WRITEONLY;
-}
-
static void load_emit_buffer(struct si_shader_context *ctx,
struct lp_build_emit_data *emit_data,
bool can_speculate, bool allow_smem)
@@ -586,7 +570,7 @@ static void load_emit(
lp_build_intrinsic(
builder,
"llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
emit_data->args, emit_data->arg_count,
- get_load_intr_attribs(can_speculate));
+ ac_get_load_intr_attribs(can_speculate));
} else {
ac_get_image_intr_name("llvm.amdgcn.image.load",
emit_data-
Mesa (master): amd/common: use ac_build_buffer_load() for emitting UBO loads
Module: Mesa
Branch: master
Commit: 41c36c4549e12b2627d8eb6599caa1e7bd61103f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=41c36c4549e12b2627d8eb6599caa1e7bd61103f
Author: Samuel Pitoiset
Date: Wed Jan 10 12:57:20 2018 +0100
amd/common: use ac_build_buffer_load() for emitting UBO loads
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/common/ac_nir_to_llvm.c | 17 +++--
1 file changed, 3 insertions(+), 14 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 932d648082..5885c70ef8 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2580,7 +2580,7 @@ static LLVMValueRef visit_load_buffer(struct
ac_nir_context *ctx,
static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
const nir_intrinsic_instr *instr)
{
- LLVMValueRef results[8], ret;
+ LLVMValueRef ret;
LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
LLVMValueRef offset = get_src(ctx, instr->src[1]);
int num_components = instr->num_components;
@@ -2591,20 +2591,9 @@ static LLVMValueRef visit_load_ubo_buffer(struct
ac_nir_context *ctx,
if (instr->dest.ssa.bit_size == 64)
num_components *= 2;
- for (unsigned i = 0; i < num_components; ++i) {
- LLVMValueRef params[] = {
- rsrc,
- LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32,
4 * i, 0),
-offset, "")
- };
- results[i] = ac_build_intrinsic(&ctx->ac,
"llvm.SI.load.const.v4i32", ctx->ac.f32,
- params, 2,
- AC_FUNC_ATTR_READNONE |
- AC_FUNC_ATTR_LEGACY);
- }
-
+ ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
+ NULL, 0, false, false, true, true);
- ret = ac_build_gather_values(&ctx->ac, results, num_components);
return LLVMBuildBitCast(ctx->ac.builder, ret,
get_def_type(ctx, &instr->dest.ssa), "");
}
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Mesa (master): dri_util: remove ALLOW_RGB10_CONFIGS option (v2)
Module: Mesa
Branch: master
Commit: b391fb26df9f1b0c1673cb79be2478b0fe459f9e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b391fb26df9f1b0c1673cb79be2478b0fe459f9e
Author: Marek Olšák
Date: Mon Jan 8 17:58:27 2018 +0100
dri_util: remove ALLOW_RGB10_CONFIGS option (v2)
This is unused because it's for libGL/libEGL, not drivers.
v2: i965 was wrong, because it used dri_util instead of its own config.
Reviewed-by: Tapani Pälli
---
src/mesa/drivers/dri/common/dri_util.c | 4
src/mesa/drivers/dri/i965/intel_screen.c | 3 ++-
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/common/dri_util.c
b/src/mesa/drivers/dri/common/dri_util.c
index d4fba0b274..e6a7d2391a 100644
--- a/src/mesa/drivers/dri/common/dri_util.c
+++ b/src/mesa/drivers/dri/common/dri_util.c
@@ -55,10 +55,6 @@ const char __dri2ConfigOptions[] =
DRI_CONF_SECTION_PERFORMANCE
DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_1)
DRI_CONF_SECTION_END
-
- DRI_CONF_SECTION_MISCELLANEOUS
- DRI_CONF_ALLOW_RGB10_CONFIGS("true")
- DRI_CONF_SECTION_END
DRI_CONF_END;
/*/
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index 3e016b5b7a..08032c9b22 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -92,6 +92,7 @@ DRI_CONF_BEGIN
DRI_CONF_SECTION_MISCELLANEOUS
DRI_CONF_GLSL_ZERO_INIT("false")
+ DRI_CONF_ALLOW_RGB10_CONFIGS("false")
DRI_CONF_SECTION_END
DRI_CONF_END
};
@@ -2064,7 +2065,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
num_formats = ARRAY_SIZE(formats) - 2; /* all - RGBA_ORDERING formats */
/* Shall we expose 10 bpc formats? */
- bool allow_rgb10_configs = driQueryOptionb(&dri_screen->optionCache,
+ bool allow_rgb10_configs = driQueryOptionb(&screen->optionCache,
"allow_rgb10_configs");
/* Generate singlesample configs without accumulation buffer. */
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Mesa (master): swr/rast: SIMD16 builder - cleanup naming (simd2 -> simd16)
Module: Mesa
Branch: master
Commit: e14b48e00e56b59de4bb916be994756295d7b685
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e14b48e00e56b59de4bb916be994756295d7b685
Author: Tim Rowley
Date: Tue Dec 19 13:39:09 2017 -0600
swr/rast: SIMD16 builder - cleanup naming (simd2 -> simd16)
Reviewed-by: Bruce Cherniak
---
.../drivers/swr/rasterizer/jitter/builder.cpp | 76 +-
.../drivers/swr/rasterizer/jitter/builder.h| 45 +++---
.../drivers/swr/rasterizer/jitter/builder_misc.cpp | 133
.../drivers/swr/rasterizer/jitter/builder_misc.h | 50 +++---
.../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 168 +++--
5 files changed, 239 insertions(+), 233 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder.cpp
b/src/gallium/drivers/swr/rasterizer/jitter/builder.cpp
index 4b83a3204c..c46159a35a 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/builder.cpp
+++ b/src/gallium/drivers/swr/rasterizer/jitter/builder.cpp
@@ -40,52 +40,56 @@ namespace SwrJit
Builder::Builder(JitManager *pJitMgr)
: mpJitMgr(pJitMgr)
{
+SWR_ASSERT(pJitMgr->mVWidth == 8);
+
mVWidth = pJitMgr->mVWidth;
-#if USE_SIMD16_BUILDER
-mVWidth2 = pJitMgr->mVWidth * 2;
-#endif
+mVWidth16 = pJitMgr->mVWidth * 2;
mpIRBuilder = &pJitMgr->mBuilder;
-mVoidTy = Type::getVoidTy(pJitMgr->mContext);
-mFP16Ty = Type::getHalfTy(pJitMgr->mContext);
-mFP32Ty = Type::getFloatTy(pJitMgr->mContext);
-mFP32PtrTy = PointerType::get(mFP32Ty, 0);
-mDoubleTy = Type::getDoubleTy(pJitMgr->mContext);
-mInt1Ty = Type::getInt1Ty(pJitMgr->mContext);
-mInt8Ty = Type::getInt8Ty(pJitMgr->mContext);
-mInt16Ty = Type::getInt16Ty(pJitMgr->mContext);
-mInt32Ty = Type::getInt32Ty(pJitMgr->mContext);
-mInt8PtrTy = PointerType::get(mInt8Ty, 0);
+// Built in types: scalar
+
+mVoidTy = Type::getVoidTy(pJitMgr->mContext);
+mFP16Ty = Type::getHalfTy(pJitMgr->mContext);
+mFP32Ty = Type::getFloatTy(pJitMgr->mContext);
+mFP32PtrTy = PointerType::get(mFP32Ty, 0);
+mDoubleTy = Type::getDoubleTy(pJitMgr->mContext);
+mInt1Ty = Type::getInt1Ty(pJitMgr->mContext);
+mInt8Ty = Type::getInt8Ty(pJitMgr->mContext);
+mInt16Ty= Type::getInt16Ty(pJitMgr->mContext);
+mInt32Ty= Type::getInt32Ty(pJitMgr->mContext);
+mInt8PtrTy = PointerType::get(mInt8Ty, 0);
mInt16PtrTy = PointerType::get(mInt16Ty, 0);
mInt32PtrTy = PointerType::get(mInt32Ty, 0);
-mInt64Ty = Type::getInt64Ty(pJitMgr->mContext);
-mSimdInt1Ty = VectorType::get(mInt1Ty, mVWidth);
-mSimdInt16Ty = VectorType::get(mInt16Ty, mVWidth);
-mSimdInt32Ty = VectorType::get(mInt32Ty, mVWidth);
-mSimdInt64Ty = VectorType::get(mInt64Ty, mVWidth);
-mSimdFP16Ty = VectorType::get(mFP16Ty, mVWidth);
-mSimdFP32Ty = VectorType::get(mFP32Ty, mVWidth);
-mSimdVectorTy = ArrayType::get(mSimdFP32Ty, 4);
+mInt64Ty= Type::getInt64Ty(pJitMgr->mContext);
+
+// Built in types: simd8
+
+mSimdInt1Ty = VectorType::get(mInt1Ty, mVWidth);
+mSimdInt16Ty= VectorType::get(mInt16Ty, mVWidth);
+mSimdInt32Ty= VectorType::get(mInt32Ty, mVWidth);
+mSimdInt64Ty= VectorType::get(mInt64Ty, mVWidth);
+mSimdFP16Ty = VectorType::get(mFP16Ty, mVWidth);
+mSimdFP32Ty = VectorType::get(mFP32Ty, mVWidth);
+mSimdVectorTy = ArrayType::get(mSimdFP32Ty, 4);
mSimdVectorTRTy = ArrayType::get(mSimdFP32Ty, 5);
-#if USE_SIMD16_BUILDER
-mSimd2Int1Ty = VectorType::get(mInt1Ty, mVWidth2);
-mSimd2Int16Ty = VectorType::get(mInt16Ty, mVWidth2);
-mSimd2Int32Ty = VectorType::get(mInt32Ty, mVWidth2);
-mSimd2Int64Ty = VectorType::get(mInt64Ty, mVWidth2);
-mSimd2FP16Ty = VectorType::get(mFP16Ty, mVWidth2);
-mSimd2FP32Ty = VectorType::get(mFP32Ty, mVWidth2);
-mSimd2VectorTy = ArrayType::get(mSimd2FP32Ty, 4);
-mSimd2VectorTRTy = ArrayType::get(mSimd2FP32Ty, 5);
-#endif
+
+// Built in types: simd16
+
+mSimd16Int1Ty = VectorType::get(mInt1Ty, mVWidth16);
+mSimd16Int16Ty = VectorType::get(mInt16Ty, mVWidth16);
+mSimd16Int32Ty = VectorType::get(mInt32Ty, mVWidth16);
+mSimd16Int64Ty = VectorType::get(mInt64Ty, mVWidth16);
+mSimd16FP16Ty = VectorType::get(mFP16Ty, mVWidth16);
+mSimd16FP32Ty = VectorType::get(mFP32Ty, mVWidth16);
+mSimd16VectorTy = ArrayType::get(mSimd16FP32Ty, 4);
+mSimd16VectorTRTy = ArrayType::get(mSimd16FP32Ty, 5);
if (sizeof(uint32_t*) == 4)
{
mIntPtrTy = mInt32Ty;
mSimdIntPtrTy = mSimdInt32Ty;
-#if USE_SIMD16_BUILDER
-mSimd
Mesa (master): swr/rast: SIMD16 fetch shader jitter cleanup
Module: Mesa Branch: master Commit: 04d0bfde3962ee76ee7310b3dee5e0f72d2b4c17 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=04d0bfde3962ee76ee7310b3dee5e0f72d2b4c17 Author: Tim Rowley Date: Fri Dec 22 13:58:08 2017 -0600 swr/rast: SIMD16 fetch shader jitter cleanup Bake in USE_SIMD16_BUILDER code paths (for USE_SIMD16_SHADER defined), remove USE_SIMD16_BUILDER define, remove deprecated psuedo-SIMD16 code paths. Reviewed-by: Bruce Cherniak --- .../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 1118 +++- 1 file changed, 383 insertions(+), 735 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=04d0bfde3962ee76ee7310b3dee5e0f72d2b4c17 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): swr/rast: autogenerate named structs instead of literal structs
Module: Mesa
Branch: master
Commit: f5f1bbcb5c66c55a45e47c71685ca6709b714390
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5f1bbcb5c66c55a45e47c71685ca6709b714390
Author: Tim Rowley
Date: Thu Dec 28 17:56:03 2017 -0600
swr/rast: autogenerate named structs instead of literal structs
Results in far smaller and useful IR output.
Reviewed-by: Bruce Cherniak
---
.../swr/rasterizer/codegen/templates/gen_llvm.hpp | 23 ++
1 file changed, 15 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_llvm.hpp
b/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_llvm.hpp
index 18ea781713..574ee5aaa7 100644
--- a/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_llvm.hpp
+++ b/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_llvm.hpp
@@ -40,15 +40,22 @@ namespace SwrJit
INLINE static StructType *Gen_${type['name']}(JitManager* pJitMgr)
{
LLVMContext& ctx = pJitMgr->mContext;
-std::vector members;
-<%
-(max_type_len, max_name_len) = calc_max_len(type['members'])
-%>
-%for member in type['members']:
-/* ${member['name']} ${pad(len(member['name']), max_name_len)}*/
members.push_back( ${member['type']} );
-%endfor
-return StructType::get(ctx, members, false);
+StructType* pRetType =
pJitMgr->mpCurrentModule->getTypeByName("${type['name']}");
+if (pRetType == nullptr)
+{
+std::vector members;
+<%
+(max_type_len, max_name_len) = calc_max_len(type['members'])
+%>
+%for member in type['members']:
+/* ${member['name']} ${pad(len(member['name']), max_name_len)}*/
members.push_back(${ member['type'] });
+%endfor
+
+pRetType = StructType::create(members, "${type['name']}", false);
+}
+
+return pRetType;
}
%for member in type['members']:
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Mesa (master): swr/rast: shuffle header files for msvc pre-compiled header usage
Module: Mesa
Branch: master
Commit: d3a4c8057dfd31b562a8007a511f1de88a153528
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d3a4c8057dfd31b562a8007a511f1de88a153528
Author: Tim Rowley
Date: Thu Dec 21 11:01:37 2017 -0600
swr/rast: shuffle header files for msvc pre-compiled header usage
Reviewed-by: Bruce Cherniak
---
src/gallium/drivers/swr/Makefile.sources | 1 +
.../drivers/swr/rasterizer/jitter/JitManager.cpp | 36 +-
.../drivers/swr/rasterizer/jitter/JitManager.h | 46 +--
.../drivers/swr/rasterizer/jitter/blend_jit.cpp| 3 +-
.../drivers/swr/rasterizer/jitter/builder.cpp | 1 +
.../drivers/swr/rasterizer/jitter/builder_misc.cpp | 1 +
.../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 3 +-
.../drivers/swr/rasterizer/jitter/jit_api.h| 1 -
.../drivers/swr/rasterizer/jitter/jit_pch.hpp | 134 +
.../swr/rasterizer/jitter/streamout_jit.cpp| 5 +-
10 files changed, 143 insertions(+), 88 deletions(-)
diff --git a/src/gallium/drivers/swr/Makefile.sources
b/src/gallium/drivers/swr/Makefile.sources
index 53f8bf011b..cd2040e137 100644
--- a/src/gallium/drivers/swr/Makefile.sources
+++ b/src/gallium/drivers/swr/Makefile.sources
@@ -145,6 +145,7 @@ JITTER_CXX_SOURCES := \
rasterizer/jitter/fetch_jit.cpp \
rasterizer/jitter/fetch_jit.h \
rasterizer/jitter/jit_api.h \
+ rasterizer/jitter/jit_pch.hpp \
rasterizer/jitter/JitManager.cpp \
rasterizer/jitter/JitManager.h \
rasterizer/jitter/streamout_jit.cpp \
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp
b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp
index 59672bb545..883ac77482 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp
+++ b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp
@@ -27,41 +27,7 @@
* Notes:
*
**/
-#if defined(_WIN32)
-#pragma warning(disable: 4800 4146 4244 4267 4355 4996)
-#endif
-
-#pragma push_macro("DEBUG")
-#undef DEBUG
-
-#if defined(_WIN32)
-#include "llvm/ADT/Triple.h"
-#endif
-#include "llvm/IR/Function.h"
-
-#include "llvm/Support/MemoryBuffer.h"
-#include "llvm/Support/SourceMgr.h"
-
-#include "llvm/Analysis/CFGPrinter.h"
-#include "llvm/IRReader/IRReader.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Support/FormattedStream.h"
-#include "llvm/Support/Path.h"
-#include "llvm/Support/MemoryBuffer.h"
-#include "llvm/Config/llvm-config.h"
-
-#if LLVM_VERSION_MAJOR < 4
-#include "llvm/Bitcode/ReaderWriter.h"
-#else
-#include "llvm/Bitcode/BitcodeWriter.h"
-#include "llvm/Bitcode/BitcodeReader.h"
-#endif
-
-#if LLVM_USE_INTEL_JITEVENTS
-#include "llvm/ExecutionEngine/JITEventListener.h"
-#endif
-
-#pragma pop_macro("DEBUG")
+#include "jit_pch.hpp"
#include "JitManager.h"
#include "jit_api.h"
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h
b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h
index c30a807222..9e5e4cf2b6 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h
+++ b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h
@@ -29,52 +29,9 @@
**/
#pragma once
-#if defined(_WIN32)
-#pragma warning(disable : 4146 4244 4267 4800 4996)
-#endif
-
-// llvm 3.7+ reuses "DEBUG" as an enum value
-#pragma push_macro("DEBUG")
-#undef DEBUG
-
-#include "llvm/IR/DataLayout.h"
-#include "llvm/IR/Instructions.h"
-#include "llvm/IR/LLVMContext.h"
-#include "llvm/IR/Module.h"
-#include "llvm/IR/Type.h"
-#include "llvm/IR/IRBuilder.h"
-#include "llvm/IR/IntrinsicInst.h"
-#include "llvm/ExecutionEngine/ObjectCache.h"
-
-#include "llvm/Config/llvm-config.h"
-
-#include "llvm/IR/Verifier.h"
-#include "llvm/ExecutionEngine/MCJIT.h"
-#include "llvm/Support/FileSystem.h"
-#define LLVM_F_NONE sys::fs::F_None
-
-#include "llvm/Analysis/Passes.h"
-
-#include "llvm/IR/LegacyPassManager.h"
-using FunctionPassManager = llvm::legacy::FunctionPassManager;
-using PassManager = llvm::legacy::PassManager;
-
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/ExecutionEngine/ExecutionEngine.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/Support/TargetSelect.h"
-#include "llvm/Transforms/IPO.h"
-#include "llvm/Transforms/Scalar.h"
-#include "llvm/Support/Host.h"
-#include "llvm/Support/DynamicLibrary.h"
-
-
-#include "common/os.h"
+#include "jit_pch.hpp"
#include "common/isa.hpp"
-#include
-
-#pragma pop_macro("DEBUG")
//
/// JitInstructionSet
@@ -173,6 +130,7 @@ struct JitManager
uint32_t mVWidth;
+
// Built in types.
llvm::Type*mInt8Ty;
llvm::Type*mInt32Ty;
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp
b/src/gallium/drivers/swr/rasterizer/jitter/bl
Mesa (master): swr/rast: don't use 32-bit gathers for elements < 32-bits in size
Module: Mesa
Branch: master
Commit: 3d4d34e380f33e9daa86ff3aa4c06a56c5fa1318
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d4d34e380f33e9daa86ff3aa4c06a56c5fa1318
Author: Tim Rowley
Date: Wed Jan 3 11:58:50 2018 -0600
swr/rast: don't use 32-bit gathers for elements < 32-bits in size
Using a gather for elements less than 32-bits in size can cause
pagefaults when loading the last elements in a page-aligned-sized
buffer.
Reviewed-by: Bruce Cherniak
---
.../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 61 +-
1 file changed, 60 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp
b/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp
index 99a936d176..ad70cbe95d 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp
+++ b/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp
@@ -741,7 +741,66 @@ void FetchJit::CreateGatherOddFormats(SWR_FORMAT format,
Value* pMask, Value* pB
// only works if pixel size is <= 32bits
SWR_ASSERT(info.bpp <= 32);
-Value *pGather = GATHERDD(VIMMED1(0), pBase, pOffsets, pMask);
+Value *pGather;
+if (info.bpp == 32)
+{
+pGather = GATHERDD(VIMMED1(0), pBase, pOffsets, pMask);
+}
+else
+{
+// Can't use 32-bit gather for items less than 32-bits, could cause
page faults.
+Value *pMem = ALLOCA(mSimdInt32Ty);
+STORE(VIMMED1(0u), pMem);
+
+pBase = BITCAST(pBase, PointerType::get(mInt8Ty, 0));
+Value* pDstMem = BITCAST(pMem, mInt32PtrTy);
+
+for (uint32_t lane = 0; lane < mVWidth; ++lane)
+{
+// Get index
+Value* index = VEXTRACT(pOffsets, C(lane));
+Value* mask = VEXTRACT(pMask, C(lane));
+switch (info.bpp)
+{
+case 8:
+{
+Value* pDst = BITCAST(GEP(pDstMem, C(lane)),
PointerType::get(mInt8Ty, 0));
+Value* pSrc = BITCAST(GEP(pBase, index),
PointerType::get(mInt8Ty, 0));
+STORE(LOAD(SELECT(mask, pSrc, pDst)), pDst);
+break;
+}
+
+case 16:
+{
+Value* pDst = BITCAST(GEP(pDstMem, C(lane)),
PointerType::get(mInt16Ty, 0));
+Value* pSrc = BITCAST(GEP(pBase, index),
PointerType::get(mInt16Ty, 0));
+STORE(LOAD(SELECT(mask, pSrc, pDst)), pDst);
+break;
+}
+break;
+
+case 24:
+{
+// First 16-bits of data
+Value* pDst = BITCAST(GEP(pDstMem, C(lane)),
PointerType::get(mInt16Ty, 0));
+Value* pSrc = BITCAST(GEP(pBase, index),
PointerType::get(mInt16Ty, 0));
+STORE(LOAD(SELECT(mask, pSrc, pDst)), pDst);
+
+// Last 8-bits of data
+pDst = BITCAST(GEP(pDst, C(1)), PointerType::get(mInt8Ty, 0));
+pSrc = BITCAST(GEP(pSrc, C(1)), PointerType::get(mInt8Ty, 0));
+STORE(LOAD(SELECT(mask, pSrc, pDst)), pDst);
+break;
+}
+
+default:
+SWR_INVALID("Shouldn't have BPP = %d now", info.bpp);
+break;
+}
+}
+
+pGather = LOAD(pMem);
+}
for (uint32_t comp = 0; comp < 4; ++comp)
{
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Mesa (master): swr/rast: switch win32 jit format to COFF
Module: Mesa Branch: master Commit: c259888c52a3cd9f6dd39cc33e919540435e5f5a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c259888c52a3cd9f6dd39cc33e919540435e5f5a Author: Tim Rowley Date: Thu Jan 4 10:27:13 2018 -0600 swr/rast: switch win32 jit format to COFF Allows for call-stack and exception handling for jitted functions. Reviewed-by: Bruce Cherniak --- src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp index 883ac77482..508bc027dd 100644 --- a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp +++ b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp @@ -92,7 +92,7 @@ JitManager::JitManager(uint32_t simdWidth, const char *arch, const char* core) #if defined(_WIN32) // Needed for MCJIT on windows Triple hostTriple(sys::getProcessTriple()); -hostTriple.setObjectFormat(Triple::ELF); +hostTriple.setObjectFormat(Triple::COFF); mpCurrentModule->setTargetTriple(hostTriple.getTriple()); #endif // _WIN32 @@ -486,4 +486,4 @@ std::unique_ptr JitCache::getObject(const llvm::Module* M) fclose(fpIn); return pBuf; -} +} \ No newline at end of file ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl: Remove unnecessary assignments to type
Module: Mesa
Branch: master
Commit: a170f279581fc0cbdd112a1e01d37e8858895bb3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a170f279581fc0cbdd112a1e01d37e8858895bb3
Author: Ian Romanick
Date: Fri Jan 5 17:50:24 2018 -0800
glsl: Remove unnecessary assignments to type
None of these are necessary because result->type is the only thing used
outside the giant switch-statement.
CID: 1230983, 1230984
Signed-off-by: Ian Romanick
Reviewed-by: Alejandro Piñeiro
---
src/compiler/glsl/ast_to_hir.cpp | 4
1 file changed, 4 deletions(-)
diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index 7abb8199e1..41e74815f3 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -1589,7 +1589,6 @@ ast_expression::do_hir(exec_list *instructions,
if (rhs_instructions.is_empty()) {
result = new(ctx) ir_expression(ir_binop_logic_and, op[0], op[1]);
- type = result->type;
} else {
ir_variable *const tmp = new(ctx) ir_variable(glsl_type::bool_type,
"and_tmp",
@@ -1611,7 +1610,6 @@ ast_expression::do_hir(exec_list *instructions,
stmt->else_instructions.push_tail(else_assign);
result = new(ctx) ir_dereference_variable(tmp);
- type = tmp->type;
}
break;
}
@@ -1625,7 +1623,6 @@ ast_expression::do_hir(exec_list *instructions,
if (rhs_instructions.is_empty()) {
result = new(ctx) ir_expression(ir_binop_logic_or, op[0], op[1]);
- type = result->type;
} else {
ir_variable *const tmp = new(ctx) ir_variable(glsl_type::bool_type,
"or_tmp",
@@ -1647,7 +1644,6 @@ ast_expression::do_hir(exec_list *instructions,
stmt->else_instructions.push_tail(else_assign);
result = new(ctx) ir_dereference_variable(tmp);
- type = tmp->type;
}
break;
}
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Mesa (master): glsl/linker: Safely generate mask of possible locations
Module: Mesa
Branch: master
Commit: 336afe7d7a8e066e1286bb93791d5c3d96ccc317
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=336afe7d7a8e066e1286bb93791d5c3d96ccc317
Author: Ian Romanick
Date: Fri Jan 5 18:43:32 2018 -0800
glsl/linker: Safely generate mask of possible locations
If MaxAttribs were ever raised to 32, undefined behavior would occur.
We had already gone to the effort (albeit incorrectly) handle this in
one case, so fix them all.
CID: 1369628
Signed-off-by: Ian Romanick
Reviewed-by: Alejandro Piñeiro
---
src/compiler/glsl/linker.cpp | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index d1f10eeecd..86ef5831b7 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -2552,6 +2552,8 @@ find_available_slots(unsigned used_mask, unsigned
needed_count)
}
+#define SAFE_MASK_FROM_INDEX(i) (((i) >= 32) ? ~0 : ((1 << (i)) - 1))
+
/**
* Assign locations for either VS inputs or FS outputs
*
@@ -2582,8 +2584,7 @@ assign_attribute_or_color_locations(void *mem_ctx,
/* Mark invalid locations as being used.
*/
- unsigned used_locations = (max_index >= 32)
- ? 0 : ~((1 << max_index) - 1);
+ unsigned used_locations = ~SAFE_MASK_FROM_INDEX(max_index);
unsigned double_storage_locations = 0;
assert((target_index == MESA_SHADER_VERTEX)
@@ -2936,7 +2937,7 @@ assign_attribute_or_color_locations(void *mem_ctx,
if (target_index == MESA_SHADER_VERTEX) {
unsigned total_attribs_size =
- _mesa_bitcount(used_locations & ((1 << max_index) - 1)) +
+ _mesa_bitcount(used_locations & SAFE_MASK_FROM_INDEX(max_index)) +
_mesa_bitcount(double_storage_locations);
if (total_attribs_size > max_index) {
linker_error(prog,
@@ -3000,7 +3001,7 @@ assign_attribute_or_color_locations(void *mem_ctx,
*/
if (target_index == MESA_SHADER_VERTEX) {
unsigned total_attribs_size =
- _mesa_bitcount(used_locations & ((1 << max_index) - 1)) +
+ _mesa_bitcount(used_locations & SAFE_MASK_FROM_INDEX(max_index)) +
_mesa_bitcount(double_storage_locations);
if (total_attribs_size > max_index) {
linker_error(prog,
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Mesa (master): nir: Silence unused parameter warnings
Module: Mesa
Branch: master
Commit: fd2f4f507fe863567045b9a60c7fca71d73fcd8b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fd2f4f507fe863567045b9a60c7fca71d73fcd8b
Author: Ian Romanick
Date: Thu Jan 4 15:28:30 2018 -0800
nir: Silence unused parameter warnings
In file included from src/compiler/nir/nir_opt_algebraic.c:4:0:
src/compiler/nir/nir_search_helpers.h: In function ‘is_not_const’:
src/compiler/nir/nir_search_helpers.h:118:59: warning: unused parameter
‘num_components’ [-Wunused-parameter]
is_not_const(nir_alu_instr *instr, unsigned src, unsigned num_components,
^~
src/compiler/nir/nir_search_helpers.h:119:29: warning: unused parameter
‘swizzle ’ [-Wunused-parameter]
const uint8_t *swizzle)
^~~
Signed-off-by: Ian Romanick
Reviewed-by: Alejandro Piñeiro
---
src/compiler/nir/nir_search_helpers.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/compiler/nir/nir_search_helpers.h
b/src/compiler/nir/nir_search_helpers.h
index 200f2471f8..2e3bd137d6 100644
--- a/src/compiler/nir/nir_search_helpers.h
+++ b/src/compiler/nir/nir_search_helpers.h
@@ -115,8 +115,8 @@ is_zero_to_one(nir_alu_instr *instr, unsigned src, unsigned
num_components,
}
static inline bool
-is_not_const(nir_alu_instr *instr, unsigned src, unsigned num_components,
- const uint8_t *swizzle)
+is_not_const(nir_alu_instr *instr, unsigned src, UNUSED unsigned
num_components,
+ UNUSED const uint8_t *swizzle)
{
nir_const_value *val = nir_src_as_const_value(instr->src[src].src);
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Mesa (master): glsl: Don't handle visit_stop in several ::accept methods
Module: Mesa Branch: master Commit: 702dc43f7eda025103df8adaf9a57067f8f56f87 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=702dc43f7eda025103df8adaf9a57067f8f56f87 Author: Ian Romanick Date: Fri Jan 5 18:19:42 2018 -0800 glsl: Don't handle visit_stop in several ::accept methods All cases where the result could be non-visit_continue would have already returned. CID: 401351, 1224465, 1224466 Signed-off-by: Ian Romanick Reviewed-by: Alejandro Piñeiro --- src/compiler/glsl/ir_hv_accept.cpp | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/compiler/glsl/ir_hv_accept.cpp b/src/compiler/glsl/ir_hv_accept.cpp index bf3f3d4f04..f04a5b6fd1 100644 --- a/src/compiler/glsl/ir_hv_accept.cpp +++ b/src/compiler/glsl/ir_hv_accept.cpp @@ -230,7 +230,8 @@ ir_texture::accept(ir_hierarchical_visitor *v) break; } - return (s == visit_stop) ? s : v->visit_leave(this); + assert(s == visit_continue); + return v->visit_leave(this); } @@ -414,7 +415,8 @@ ir_emit_vertex::accept(ir_hierarchical_visitor *v) if (s != visit_continue) return (s == visit_continue_with_parent) ? visit_continue : s; - return (s == visit_stop) ? s : v->visit_leave(this); + assert(s == visit_continue); + return v->visit_leave(this); } @@ -429,7 +431,8 @@ ir_end_primitive::accept(ir_hierarchical_visitor *v) if (s != visit_continue) return (s == visit_continue_with_parent) ? visit_continue : s; - return (s == visit_stop) ? s : v->visit_leave(this); + assert(s == visit_continue); + return v->visit_leave(this); } ir_visitor_status ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl/linker: Mark no locations as invalid instead of marking all locations
Module: Mesa Branch: master Commit: 0c9df36157aca1e725f037e5adc54100aa387bd3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c9df36157aca1e725f037e5adc54100aa387bd3 Author: Ian Romanick Date: Fri Jan 5 18:40:21 2018 -0800 glsl/linker: Mark no locations as invalid instead of marking all locations If max_index were ever 32, the linker would have marked all 32 locations as invalid instead of marking none of them as invalid. It's a good thing the maximum value actually set by any driver for MaxAttribs is 16. Found by inspection while investigating CID 1369628. Signed-off-by: Ian Romanick Reviewed-by: Alejandro Piñeiro --- src/compiler/glsl/linker.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp index 6f9680aae7..d1f10eeecd 100644 --- a/src/compiler/glsl/linker.cpp +++ b/src/compiler/glsl/linker.cpp @@ -2583,7 +2583,7 @@ assign_attribute_or_color_locations(void *mem_ctx, /* Mark invalid locations as being used. */ unsigned used_locations = (max_index >= 32) - ? ~0 : ~((1 << max_index) - 1); + ? 0 : ~((1 << max_index) - 1); unsigned double_storage_locations = 0; assert((target_index == MESA_SHADER_VERTEX) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: Implement VK_EXT_discard_rectangles.
Module: Mesa
Branch: master
Commit: 5db0bf99944ff2d3e83ef27d2aebe8f074d93d59
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5db0bf99944ff2d3e83ef27d2aebe8f074d93d59
Author: Bas Nieuwenhuizen
Date: Wed Jan 10 02:41:30 2018 +0100
radv: Implement VK_EXT_discard_rectangles.
Tested with a modified deferred demo and no regressions in a 1.0.2
mustpass run.
Reviewed-by: Samuel Pitoiset
Reviewed-by: Dave Airlie
---
src/amd/vulkan/radv_cmd_buffer.c | 51 +++
src/amd/vulkan/radv_device.c | 6 +
src/amd/vulkan/radv_extensions.py | 1 +
src/amd/vulkan/radv_pipeline.c| 35 +++
src/amd/vulkan/radv_private.h | 23 +-
5 files changed, 110 insertions(+), 6 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 3114ae9fb4..4b5556bcc6 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -91,6 +91,7 @@ radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
*/
dest->viewport.count = src->viewport.count;
dest->scissor.count = src->scissor.count;
+ dest->discard_rectangle.count = src->discard_rectangle.count;
if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
@@ -168,6 +169,16 @@ radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
}
}
+ if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
+ if (memcmp(&dest->discard_rectangle.rectangles,
&src->discard_rectangle.rectangles,
+ src->discard_rectangle.count * sizeof(VkRect2D))) {
+ typed_memcpy(dest->discard_rectangle.rectangles,
+src->discard_rectangle.rectangles,
+src->discard_rectangle.count);
+ dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
+ }
+ }
+
cmd_buffer->state.dirty |= dest_mask;
}
@@ -1098,6 +1109,8 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer)
}
radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
pipeline->graphics.gs_out);
+ radeon_set_context_reg(cmd_buffer->cs, R_02820C_PA_SC_CLIPRECT_RULE,
pipeline->graphics.pa_sc_cliprect_rule);
+
if (unlikely(cmd_buffer->device->trace_bo))
radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
@@ -1135,6 +1148,22 @@ radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
}
static void
+radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
+{
+ if (!cmd_buffer->state.dynamic.discard_rectangle.count)
+ return;
+
+ radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
+
cmd_buffer->state.dynamic.discard_rectangle.count * 2);
+ for (unsigned i = 0; i <
cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
+ VkRect2D rect =
cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
+ radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) |
S_028210_TL_Y(rect.offset.y));
+ radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x +
rect.extent.width) |
+ S_028214_BR_Y(rect.offset.y +
rect.extent.height));
+ }
+}
+
+static void
radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
{
unsigned width = cmd_buffer->state.dynamic.line_width * 8;
@@ -1627,6 +1656,9 @@ radv_cmd_buffer_flush_dynamic_state(struct
radv_cmd_buffer *cmd_buffer)
RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
radv_emit_depth_biais(cmd_buffer);
+ if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
+ radv_emit_discard_rectangle(cmd_buffer);
+
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
}
@@ -2882,6 +2914,25 @@ void radv_CmdSetStencilReference(
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
}
+void radv_CmdSetDiscardRectangleEXT(
+ VkCommandBuffer commandBuffer,
+ uint32_tfirstDiscardRectangle,
+ uint32_tdiscardRectangleCount,
+ const VkRect2D* pDiscardRectangles)
+{
+ RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
+ struct radv_cmd_state *state = &cmd_buffer->state;
+ MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle +
discardRectangleCount;
+
+ assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
+ assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
+
+
typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
+pDiscardRectangles, di
Mesa (master): radv: Remove some typos.
Module: Mesa
Branch: master
Commit: d0ef3d4bb0f381ac08232ad89c6510e05f03a3d4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0ef3d4bb0f381ac08232ad89c6510e05f03a3d4
Author: Bas Nieuwenhuizen
Date: Wed Jan 10 13:01:29 2018 +0100
radv: Remove some typos.
Trivial.
---
src/amd/vulkan/radv_cmd_buffer.c | 4 ++--
src/amd/vulkan/radv_device.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 4b5556bcc6..fb48691ca1 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1212,7 +1212,7 @@ radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
}
static void
-radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
+radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
{
struct radv_raster_state *raster =
&cmd_buffer->state.pipeline->graphics.raster;
struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
@@ -1654,7 +1654,7 @@ radv_cmd_buffer_flush_dynamic_state(struct
radv_cmd_buffer *cmd_buffer)
if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
- radv_emit_depth_biais(cmd_buffer);
+ radv_emit_depth_bias(cmd_buffer);
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
radv_emit_discard_rectangle(cmd_buffer);
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index baffa41d31..24aa861780 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -627,8 +627,8 @@ void radv_GetPhysicalDeviceProperties(
* there is no set limit, so we just set a pipeline limit. I don't think
* any app is going to hit this soon. */
size_t max_descriptor_set_size = ((1ull << 31) - 16 *
MAX_DYNAMIC_BUFFERS) /
- (32 /* uniform buffer, 32 due to potential space wasted on
alignement */ +
- 32 /* storage buffer, 32 due to potential space wasted on
alignement */ +
+ (32 /* uniform buffer, 32 due to potential space wasted on
alignment */ +
+ 32 /* storage buffer, 32 due to potential space wasted on
alignment */ +
32 /* sampler, largest when combined with image */ +
64 /* sampled image */ +
64 /* storage image */);
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Mesa (master): radv: Add mapping between dynamic state mask and external enum.
Module: Mesa
Branch: master
Commit: 11b9cdd2d702e4de3b66ef63aa23f4319b4bc74b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=11b9cdd2d702e4de3b66ef63aa23f4319b4bc74b
Author: Bas Nieuwenhuizen
Date: Tue Jan 9 22:22:59 2018 +0100
radv: Add mapping between dynamic state mask and external enum.
The EXT values are really large, e.g.
VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT = 199000, so 1 << value
is not going to fit into a 32-bit mask.
Reviewed-by: Samuel Pitoiset
Reviewed-by: Dave Airlie
---
src/amd/vulkan/radv_cmd_buffer.c | 36 ++---
src/amd/vulkan/radv_pipeline.c | 49 +++-
src/amd/vulkan/radv_private.h| 32 ++
3 files changed, 79 insertions(+), 38 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index d8f780cfd7..3114ae9fb4 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -92,79 +92,79 @@ radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
dest->viewport.count = src->viewport.count;
dest->scissor.count = src->scissor.count;
- if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
+ if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
src->viewport.count * sizeof(VkViewport))) {
typed_memcpy(dest->viewport.viewports,
src->viewport.viewports,
src->viewport.count);
- dest_mask |= 1 << VK_DYNAMIC_STATE_VIEWPORT;
+ dest_mask |= RADV_DYNAMIC_VIEWPORT;
}
}
- if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
+ if (copy_mask & RADV_DYNAMIC_SCISSOR) {
if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
src->scissor.count * sizeof(VkRect2D))) {
typed_memcpy(dest->scissor.scissors,
src->scissor.scissors, src->scissor.count);
- dest_mask |= 1 << VK_DYNAMIC_STATE_SCISSOR;
+ dest_mask |= RADV_DYNAMIC_SCISSOR;
}
}
- if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
+ if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
if (dest->line_width != src->line_width) {
dest->line_width = src->line_width;
- dest_mask |= 1 << VK_DYNAMIC_STATE_LINE_WIDTH;
+ dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
}
}
- if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
+ if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
if (memcmp(&dest->depth_bias, &src->depth_bias,
sizeof(src->depth_bias))) {
dest->depth_bias = src->depth_bias;
- dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BIAS;
+ dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
}
}
- if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
+ if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
if (memcmp(&dest->blend_constants, &src->blend_constants,
sizeof(src->blend_constants))) {
typed_memcpy(dest->blend_constants,
src->blend_constants, 4);
- dest_mask |= 1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS;
+ dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
}
}
- if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
+ if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
if (memcmp(&dest->depth_bounds, &src->depth_bounds,
sizeof(src->depth_bounds))) {
dest->depth_bounds = src->depth_bounds;
- dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS;
+ dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
}
}
- if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
+ if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
if (memcmp(&dest->stencil_compare_mask,
&src->stencil_compare_mask,
sizeof(src->stencil_compare_mask))) {
dest->stencil_compare_mask = src->stencil_compare_mask;
- dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK;
+ dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
}
}
- if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
+ if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
Mesa (master): amd/common: bump the number of available user SGPRS to 32 on GFX9
Module: Mesa
Branch: master
Commit: 7145b20afb3eaf40b3b40b9a191d05d7fd23a4cb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7145b20afb3eaf40b3b40b9a191d05d7fd23a4cb
Author: Samuel Pitoiset
Date: Mon Jan 8 15:19:34 2018 +0100
amd/common: bump the number of available user SGPRS to 32 on GFX9
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/common/ac_nir_to_llvm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 840d27e7a8..932d648082 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -600,7 +600,9 @@ static void allocate_user_sgprs(struct nir_to_llvm_context
*ctx,
if (ctx->shader_info->info.loads_push_constants)
user_sgpr_info->sgpr_count += 2;
- uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
+ uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
+ uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
+
if (remaining_sgprs / 2 <
util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
user_sgpr_info->sgpr_count += 2;
user_sgpr_info->indirect_all_descriptor_sets = true;
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Mesa (master): radv/gfx9: enable LDS for GS only if the ES type is TES
Module: Mesa
Branch: master
Commit: 232c418af5fabbfcd97104028d489d65cfdbc3cb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=232c418af5fabbfcd97104028d489d65cfdbc3cb
Author: Samuel Pitoiset
Date: Tue Jan 9 16:01:09 2018 +0100
radv/gfx9: enable LDS for GS only if the ES type is TES
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_shader.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 5d777a05e5..58d991e452 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -415,6 +415,7 @@ radv_fill_shader_variant(struct radv_device *device,
if (device->physical_device->rad_info.chip_class >= GFX9 &&
stage == MESA_SHADER_GEOMETRY) {
struct ac_shader_info *info = &variant->info.info;
+ unsigned es_type = variant->info.gs.es_type;
unsigned gs_vgpr_comp_cnt;
/* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
@@ -432,7 +433,7 @@ radv_fill_shader_variant(struct radv_device *device,
/* TODO: Figure out how many we actually need. */
variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(3) |
- S_00B22C_OC_LDS_EN(1);
+ S_00B22C_OC_LDS_EN(es_type ==
MESA_SHADER_TESS_EVAL);
} else if (device->physical_device->rad_info.chip_class >= GFX9 &&
stage == MESA_SHADER_TESS_CTRL)
variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
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Mesa (master): radv: remove radv_pipeline_layout:: push_constant_stages field
Module: Mesa
Branch: master
Commit: a1f1f708c0d3f7ee8fb9ba013aeec1a2d20608d2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1f1f708c0d3f7ee8fb9ba013aeec1a2d20608d2
Author: Samuel Pitoiset
Date: Tue Jan 9 18:09:44 2018 +0100
radv: remove radv_pipeline_layout::push_constant_stages field
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_descriptor_set.c | 2 --
src/amd/vulkan/radv_descriptor_set.h | 1 -
2 files changed, 3 deletions(-)
diff --git a/src/amd/vulkan/radv_descriptor_set.c
b/src/amd/vulkan/radv_descriptor_set.c
index 19a560a6b3..b1ef66308d 100644
--- a/src/amd/vulkan/radv_descriptor_set.c
+++ b/src/amd/vulkan/radv_descriptor_set.c
@@ -228,13 +228,11 @@ VkResult radv_CreatePipelineLayout(
layout->dynamic_offset_count = dynamic_offset_count;
layout->push_constant_size = 0;
- layout->push_constant_stages = 0;
for (unsigned i = 0; i < pCreateInfo->pushConstantRangeCount; ++i) {
const VkPushConstantRange *range =
pCreateInfo->pPushConstantRanges + i;
layout->push_constant_size = MAX2(layout->push_constant_size,
range->offset + range->size);
- layout->push_constant_stages |= range->stageFlags;
}
layout->push_constant_size = align(layout->push_constant_size, 16);
diff --git a/src/amd/vulkan/radv_descriptor_set.h
b/src/amd/vulkan/radv_descriptor_set.h
index 083a61fd99..7fa79186a1 100644
--- a/src/amd/vulkan/radv_descriptor_set.h
+++ b/src/amd/vulkan/radv_descriptor_set.h
@@ -83,7 +83,6 @@ struct radv_pipeline_layout {
uint32_t num_sets;
uint32_t push_constant_size;
- VkShaderStageFlags push_constant_stages;
uint32_t dynamic_offset_count;
unsigned char sha1[20];
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Mesa (master): radv/gfx9: calculate the number of ES VGPRs for merged shaders
Module: Mesa
Branch: master
Commit: 4e701cf75c89dbe8dd731698f2652beb7863e69b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e701cf75c89dbe8dd731698f2652beb7863e69b
Author: Samuel Pitoiset
Date: Tue Jan 9 16:01:10 2018 +0100
radv/gfx9: calculate the number of ES VGPRs for merged shaders
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_shader.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 58d991e452..6f622dd996 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -416,7 +416,15 @@ radv_fill_shader_variant(struct radv_device *device,
stage == MESA_SHADER_GEOMETRY) {
struct ac_shader_info *info = &variant->info.info;
unsigned es_type = variant->info.gs.es_type;
- unsigned gs_vgpr_comp_cnt;
+ unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
+
+ if (es_type == MESA_SHADER_VERTEX) {
+ es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
+ } else if (es_type == MESA_SHADER_TESS_EVAL) {
+ es_vgpr_comp_cnt = 3;
+ } else {
+ assert(!"invalid shader ES type");
+ }
/* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
* VGPR[0:4] are always loaded.
@@ -430,9 +438,8 @@ radv_fill_shader_variant(struct radv_device *device,
else
gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
- /* TODO: Figure out how many we actually need. */
variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
- variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(3) |
+ variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
S_00B22C_OC_LDS_EN(es_type ==
MESA_SHADER_TESS_EVAL);
} else if (device->physical_device->rad_info.chip_class >= GFX9 &&
stage == MESA_SHADER_TESS_CTRL)
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Mesa (master): amd/common: determine the ES type (VS or TES) for the GS on GFX9
Module: Mesa
Branch: master
Commit: 9e2395faf5470bf6b613ca9a8f04a470c92bbfde
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e2395faf5470bf6b613ca9a8f04a470c92bbfde
Author: Samuel Pitoiset
Date: Tue Jan 9 16:01:08 2018 +0100
amd/common: determine the ES type (VS or TES) for the GS on GFX9
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/common/ac_nir_to_llvm.c | 8
src/amd/common/ac_nir_to_llvm.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 70876cfc69..34ab0a4a36 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -6984,6 +6984,14 @@ void ac_compile_nir_shader(LLVMTargetMachineRef tm,
ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info,
nir[0]->info.stage, dump_shader, options->supports_spill);
for (int i = 0; i < nir_count; ++i)
ac_fill_shader_info(shader_info, nir[i], options);
+
+ /* Determine the ES type (VS or TES) for the GS on GFX9. */
+ if (options->chip_class == GFX9) {
+ if (nir_count == 2 &&
+ nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
+ shader_info->gs.es_type = nir[0]->info.stage;
+ }
+ }
}
static void
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index 6c59ab916c..b3ad0a0985 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -191,6 +191,7 @@ struct ac_shader_variant_info {
unsigned invocations;
unsigned gsvs_vertex_size;
unsigned max_gsvs_emit_size;
+ unsigned es_type; /* GFX9: VS or TES */
} gs;
struct {
unsigned tcs_vertices_out;
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Mesa (master): amd/common: do not rely on the pipeline for the push constants logic
Module: Mesa
Branch: master
Commit: d43f50c00b8172abd0c9e934c3e193bdc85b5089
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d43f50c00b8172abd0c9e934c3e193bdc85b5089
Author: Samuel Pitoiset
Date: Tue Jan 9 18:09:43 2018 +0100
amd/common: do not rely on the pipeline for the push constants logic
It makes more sense to rely on nir_intrinsic_load_push_constant
instead of the pipeline layout.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/common/ac_nir_to_llvm.c | 6 +++---
src/amd/common/ac_shader_info.c | 10 +-
src/amd/common/ac_shader_info.h | 2 +-
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 34ab0a4a36..840d27e7a8 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -597,7 +597,7 @@ static void allocate_user_sgprs(struct nir_to_llvm_context
*ctx,
break;
}
- if (ctx->shader_info->info.needs_push_constants)
+ if (ctx->shader_info->info.loads_push_constants)
user_sgpr_info->sgpr_count += 2;
uint32_t remaining_sgprs = 16 - user_sgpr_info->sgpr_count;
@@ -638,7 +638,7 @@ declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
add_array_arg(args, const_array(type, 32), desc_sets);
}
- if (ctx->shader_info->info.needs_push_constants) {
+ if (ctx->shader_info->info.loads_push_constants) {
/* 1 for push constants and dynamic descriptors */
add_array_arg(args, type, &ctx->push_constants);
}
@@ -729,7 +729,7 @@ set_global_input_locs(struct nir_to_llvm_context *ctx,
gl_shader_stage stage,
ctx->shader_info->need_indirect_descriptor_sets = true;
}
- if (ctx->shader_info->info.needs_push_constants) {
+ if (ctx->shader_info->info.loads_push_constants) {
set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
}
}
diff --git a/src/amd/common/ac_shader_info.c b/src/amd/common/ac_shader_info.c
index 27896a26bb..443980c7d1 100644
--- a/src/amd/common/ac_shader_info.c
+++ b/src/amd/common/ac_shader_info.c
@@ -76,6 +76,9 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, struct
ac_shader_info *info)
case nir_intrinsic_load_primitive_id:
info->uses_prim_id = true;
break;
+ case nir_intrinsic_load_push_constant:
+ info->loads_push_constants = true;
+ break;
case nir_intrinsic_vulkan_resource_index:
info->desc_set_used_mask |= (1 <<
nir_intrinsic_desc_set(instr));
break;
@@ -154,11 +157,8 @@ ac_nir_shader_info_pass(struct nir_shader *nir,
{
struct nir_function *func = (struct nir_function
*)exec_list_get_head(&nir->functions);
- info->needs_push_constants = false;
- if ((options->layout->push_constant_size &&
-options->layout->push_constant_stages & (1 << nir->info.stage)) ||
- options->layout->dynamic_offset_count)
- info->needs_push_constants = true;
+ if (options->layout->dynamic_offset_count)
+ info->loads_push_constants = true;
nir_foreach_variable(variable, &nir->inputs)
gather_info_input_decl(nir, options, variable, info);
diff --git a/src/amd/common/ac_shader_info.h b/src/amd/common/ac_shader_info.h
index 437859f891..9c9a8473a4 100644
--- a/src/amd/common/ac_shader_info.h
+++ b/src/amd/common/ac_shader_info.h
@@ -28,7 +28,7 @@ struct nir_shader;
struct ac_nir_compiler_options;
struct ac_shader_info {
- bool needs_push_constants;
+ bool loads_push_constants;
uint32_t desc_set_used_mask;
bool needs_multiview_view_index;
bool uses_invocation_id;
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