Mesa (master): st/glsl_to_nir: disable io lowering to temps for tess
Module: Mesa
Branch: master
Commit: f69cbb2b53ac3edf7b201ba77430a61471edfa6e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f69cbb2b53ac3edf7b201ba77430a61471edfa6e
Author: Timothy Arceri
Date: Thu Jan 11 12:47:31 2018 +1100
st/glsl_to_nir: disable io lowering to temps for tess
Lowering these to temps makes a big mess, and results in some
piglit test failures. Also the radeonsi backend (the only backend
to support tess) has support for indirects so there is no need to
lower them anyway.
Fixes the following piglit tests on radeonsi:
tests/spec/arb_tessellation_shader/execution/variable-indexing/tes-input-array-vec3-index-rd.shader_test
tests/spec/arb_tessellation_shader/execution/variable-indexing/tes-input-array-vec4-index-rd.shader_test
Reviewed-by: Marek Olšák
---
src/mesa/state_tracker/st_glsl_to_nir.cpp | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 1c5de3d5de..bd6d588a98 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -490,9 +490,12 @@ st_nir_get_mesa_program(struct gl_context *ctx,
set_st_program(prog, shader_program, nir);
prog->nir = nir;
- NIR_PASS_V(nir, nir_lower_io_to_temporaries,
- nir_shader_get_entrypoint(nir),
- true, true);
+ if (nir->info.stage != MESA_SHADER_TESS_CTRL &&
+ nir->info.stage != MESA_SHADER_TESS_EVAL) {
+ NIR_PASS_V(nir, nir_lower_io_to_temporaries,
+ nir_shader_get_entrypoint(nir),
+ true, true);
+ }
NIR_PASS_V(nir, nir_lower_global_vars_to_local);
NIR_PASS_V(nir, nir_split_var_copies);
NIR_PASS_V(nir, nir_lower_var_copies);
@@ -665,7 +668,8 @@ st_finalize_nir(struct st_context *st, struct gl_program
*prog,
NIR_PASS_V(nir, nir_split_var_copies);
NIR_PASS_V(nir, nir_lower_var_copies);
- if (nir->info.stage != MESA_SHADER_TESS_CTRL)
+ if (nir->info.stage != MESA_SHADER_TESS_CTRL &&
+ nir->info.stage != MESA_SHADER_TESS_EVAL)
NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects);
if (nir->info.stage == MESA_SHADER_VERTEX) {
___
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Mesa (master): i965/draw: Do resolves properly for textures used by TXF
Module: Mesa
Branch: master
Commit: 96aa5587155e7de87e80d617725cc66f6807c5d1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=96aa5587155e7de87e80d617725cc66f6807c5d1
Author: Jason Ekstrand
Date: Tue Oct 31 16:29:22 2017 -0700
i965/draw: Do resolves properly for textures used by TXF
Reviewed-by: Iago Toral Quiroga
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_draw.c | 41
1 file changed, 41 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 96e014dc1f..fc349adf7f 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -40,6 +40,7 @@
#include "swrast_setup/swrast_setup.h"
#include "drivers/common/meta.h"
#include "util/bitscan.h"
+#include "util/bitset.h"
#include "brw_blorp.h"
#include "brw_draw.h"
@@ -371,6 +372,20 @@ intel_disable_rb_aux_buffer(struct brw_context *brw,
return found;
}
+static void
+mark_textures_used_for_txf(BITSET_WORD *used_for_txf,
+ const struct gl_program *prog)
+{
+ if (!prog)
+ return;
+
+ unsigned mask = prog->SamplersUsed & prog->info.textures_used_by_txf;
+ while (mask) {
+ int s = u_bit_scan(&mask);
+ BITSET_SET(used_for_txf, prog->SamplerUnits[s]);
+ }
+}
+
/**
* \brief Resolve buffers before drawing.
*
@@ -386,6 +401,18 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool
rendering)
memset(brw->draw_aux_buffer_disabled, 0,
sizeof(brw->draw_aux_buffer_disabled));
+ BITSET_DECLARE(used_for_txf, MAX_COMBINED_TEXTURE_IMAGE_UNITS);
+ memset(used_for_txf, 0, sizeof(used_for_txf));
+ if (rendering) {
+ mark_textures_used_for_txf(used_for_txf, ctx->VertexProgram._Current);
+ mark_textures_used_for_txf(used_for_txf, ctx->TessCtrlProgram._Current);
+ mark_textures_used_for_txf(used_for_txf, ctx->TessEvalProgram._Current);
+ mark_textures_used_for_txf(used_for_txf, ctx->GeometryProgram._Current);
+ mark_textures_used_for_txf(used_for_txf, ctx->FragmentProgram._Current);
+ } else {
+ mark_textures_used_for_txf(used_for_txf, ctx->ComputeProgram._Current);
+ }
+
/* Resolve depth buffer and render cache of each enabled texture. */
int maxEnabledUnit = ctx->Texture._MaxEnabledTexImageUnit;
for (int i = 0; i <= maxEnabledUnit; i++) {
@@ -422,6 +449,20 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool
rendering)
min_layer, num_layers,
disable_aux);
+ /* If any programs are using it with texelFetch, we may need to also do
+ * a prepare with an sRGB format to ensure texelFetch works "properly".
+ */
+ if (BITSET_TEST(used_for_txf, i)) {
+ enum isl_format txf_format =
+translate_tex_format(brw, tex_obj->_Format, GL_DECODE_EXT);
+ if (txf_format != view_format) {
+intel_miptree_prepare_texture(brw, tex_obj->mt, txf_format,
+ min_level, num_levels,
+ min_layer, num_layers,
+ disable_aux);
+ }
+ }
+
brw_cache_flush_for_read(brw, tex_obj->mt->bo);
if (tex_obj->base.StencilSampling ||
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Mesa (master): i965: Enable CCS_E sampling of sRGB textures as UNORM
Module: Mesa
Branch: master
Commit: af10ce21fffdbe5222115950878878175823bb27
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=af10ce21fffdbe5222115950878878175823bb27
Author: Jason Ekstrand
Date: Fri Dec 8 22:21:09 2017 -0800
i965: Enable CCS_E sampling of sRGB textures as UNORM
Reviewed-by: Iago Toral Quiroga
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index c61042e14b..b56a51e6f6 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2570,9 +2570,8 @@ can_texture_with_ccs(struct brw_context *brw,
if (mt->aux_usage != ISL_AUX_USAGE_CCS_E)
return false;
- /* TODO: Replace with format_ccs_e_compat_with_miptree for better perf. */
- if (!isl_formats_are_ccs_e_compatible(&brw->screen->devinfo,
- mt->surf.format, view_format)) {
+ if (!format_ccs_e_compat_with_miptree(&brw->screen->devinfo,
+ mt, view_format)) {
perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
isl_format_get_layout(view_format)->name,
_mesa_get_format_name(mt->format));
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Mesa (master): i965: Track format and aux usage in the render cache
Module: Mesa
Branch: master
Commit: d84275b884244a2fd3a6e67ceb2a5277e5edf89a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d84275b884244a2fd3a6e67ceb2a5277e5edf89a
Author: Jason Ekstrand
Date: Wed Dec 13 17:25:26 2017 -0800
i965: Track format and aux usage in the render cache
This lets us perform render cache flushes whenever a surface goes from
being used with one aux+format to a different aux+format.
This is the "proper" fix for https://bugs.freedesktop.org/102435.
ee57b15ec764736e2d5360beaef9fb2045ed0f68 which was really just a partial
revert of 3e57e9494c2279580ad6a83ab8c065d01e7e634e was just a hack to
get rid of a hang in a bunch of Valve games. This solves the actual
problem responsible for the hang and lets us enable CCS_E once again.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102435
Reviewed-by: Iago Toral Quiroga
Reviewed-by: Kenneth Graunke
Cc: "17.3"
---
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
src/mesa/drivers/dri/i965/brw_draw.c| 20 +---
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 14 --
src/mesa/drivers/dri/i965/intel_fbo.c | 75 +++--
src/mesa/drivers/dri/i965/intel_fbo.h | 8 ++-
5 files changed, 92 insertions(+), 27 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 8d8ab71093..3cbc2e8c13 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -764,7 +764,7 @@ struct brw_context
* and would need flushing before being used from another cache domain that
* isn't coherent with it (i.e. the sampler).
*/
- struct set *render_cache;
+ struct hash_table *render_cache;
/**
* Set of struct brw_bo * that have been used as a depth buffer within this
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 1f86378f5e..96e014dc1f 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -503,13 +503,17 @@ brw_predraw_resolve_framebuffer(struct brw_context *brw)
mesa_format mesa_format =
_mesa_get_render_format(ctx, intel_rb_format(irb));
enum isl_format isl_format = brw_isl_format_for_mesa_format(mesa_format);
+ bool blend_enabled = ctx->Color.BlendEnabled & (1 << i);
+ enum isl_aux_usage aux_usage =
+ intel_miptree_render_aux_usage(brw, irb->mt, isl_format,
+blend_enabled);
intel_miptree_prepare_render(brw, irb->mt, irb->mt_level,
irb->mt_layer, irb->layer_count,
- isl_format,
- ctx->Color.BlendEnabled & (1 << i));
+ isl_format, blend_enabled);
- brw_cache_flush_for_render(brw, irb->mt->bo);
+ brw_cache_flush_for_render(brw, irb->mt->bo,
+ isl_format, aux_usage);
}
}
@@ -575,12 +579,16 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context
*brw)
mesa_format mesa_format =
_mesa_get_render_format(ctx, intel_rb_format(irb));
enum isl_format isl_format = brw_isl_format_for_mesa_format(mesa_format);
+ bool blend_enabled = ctx->Color.BlendEnabled & (1 << i);
+ enum isl_aux_usage aux_usage =
+ intel_miptree_render_aux_usage(brw, irb->mt, isl_format,
+blend_enabled);
+
+ brw_render_cache_add_bo(brw, irb->mt->bo, isl_format, aux_usage);
- brw_render_cache_add_bo(brw, irb->mt->bo);
intel_miptree_finish_render(brw, irb->mt, irb->mt_level,
irb->mt_layer, irb->layer_count,
- isl_format,
- ctx->Color.BlendEnabled & (1 << i));
+ isl_format, blend_enabled);
}
}
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index e8bc52e5d7..062171af60 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -239,8 +239,11 @@ genX(blorp_exec)(struct blorp_batch *batch,
*/
if (params->src.enabled)
brw_cache_flush_for_read(brw, params->src.addr.buffer);
- if (params->dst.enabled)
- brw_cache_flush_for_render(brw, params->dst.addr.buffer);
+ if (params->dst.enabled) {
+ brw_cache_flush_for_render(brw, params->dst.addr.buffer,
+ params->dst.view.format,
+ params->dst.aux_usage);
+ }
if (params->depth.enabled)
brw_cache_flush_for_depth(brw, params->depth.addr.buffer);
if (params->stencil.enabled)
@@ -310,8 +313,11 @@ retry:
!params->stencil.enabled;
brw->ib.index_size = -1;
- if (params->dst.enabled)
- brw_render_cache_add_bo(brw, params->ds
Mesa (master): i965/miptree: Refactor CCS_E and CCS_D cases in render_aux_usage
Module: Mesa
Branch: master
Commit: 361e1df1edb23b08e36027136f1dc73f52dea536
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=361e1df1edb23b08e36027136f1dc73f52dea536
Author: Jason Ekstrand
Date: Sun Dec 17 19:42:09 2017 -0800
i965/miptree: Refactor CCS_E and CCS_D cases in render_aux_usage
This commit unifies the CCS_E and CCS_D cases. This should fix a couple
of subtle issues. One is that when you use INTEL_DEBUG=norbc to disable
CCS_E, we don't get the sRGB blending workaround. By unifying the code,
we give CCS_D that workaround as well.
The second issue fixed by this refactor is that the blending workaround
was appears to be enabled on all gens but really only applies on gen9.
Due to a happy accident in the way code was laid out, it was only
getting enabled on gen9: gen8 and earlier don't support non-zero-one
clear colors, and gen10 supports sRGB for CCS_E so it got caught in the
format_ccs_e_compat_with_miptree case. This refactor moves it above the
format_ccs_e_compat_with_miptree case so it's an explicit early exit and
makes it explicitly only on gen9.
Reviewed-by: Nanley Chery
Reviewed-by: Iago Toral Quiroga
Reviewed-by: Kenneth Graunke
Cc: "17.3"
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 28 ++-
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index abdaa6a753..c61042e14b 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2679,34 +2679,36 @@ intel_miptree_render_aux_usage(struct brw_context *brw,
enum isl_format render_format,
bool blend_enabled)
{
+ struct gen_device_info *devinfo = &brw->screen->devinfo;
+
switch (mt->aux_usage) {
case ISL_AUX_USAGE_MCS:
assert(mt->mcs_buf);
return ISL_AUX_USAGE_MCS;
case ISL_AUX_USAGE_CCS_D:
- return mt->mcs_buf ? ISL_AUX_USAGE_CCS_D : ISL_AUX_USAGE_NONE;
-
- case ISL_AUX_USAGE_CCS_E: {
- /* If the format supports CCS_E and is compatible with the miptree,
- * then we can use it.
- */
- if (format_ccs_e_compat_with_miptree(&brw->screen->devinfo,
- mt, render_format))
- return ISL_AUX_USAGE_CCS_E;
-
- /* Otherwise, we have to fall back to CCS_D */
+ case ISL_AUX_USAGE_CCS_E:
+ if (!mt->mcs_buf) {
+ assert(mt->aux_usage == ISL_AUX_USAGE_CCS_D);
+ return ISL_AUX_USAGE_NONE;
+ }
/* gen9 hardware technically supports non-0/1 clear colors with sRGB
* formats. However, there are issues with blending where it doesn't
* properly apply the sRGB curve to the clear color when blending.
*/
- if (blend_enabled && isl_format_is_srgb(render_format) &&
+ if (devinfo->gen == 9 && blend_enabled &&
+ isl_format_is_srgb(render_format) &&
!isl_color_value_is_zero_one(mt->fast_clear_color, render_format))
return ISL_AUX_USAGE_NONE;
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E &&
+ format_ccs_e_compat_with_miptree(&brw->screen->devinfo,
+ mt, render_format))
+ return ISL_AUX_USAGE_CCS_E;
+
+ /* Otherwise, we have to fall back to CCS_D */
return ISL_AUX_USAGE_CCS_D;
- }
default:
return ISL_AUX_USAGE_NONE;
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Mesa (master): i965: Call brw_cache_flush_for_render in predraw_resolve_framebuffer
Module: Mesa Branch: master Commit: 622786c20c6cd073071b00ddf6e50c447f8c5768 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=622786c20c6cd073071b00ddf6e50c447f8c5768 Author: Jason Ekstrand Date: Wed Dec 13 17:23:41 2017 -0800 i965: Call brw_cache_flush_for_render in predraw_resolve_framebuffer This makes sure we flush things out of other caches prior to using a surface through the render cache. Currently, this is a no-op because GL won't let you bind anything other than a color surface as color so it should never end up in the depth cache. However, this does complete the flush/add_bo pair for regular drawing which will be required for the next commit. Reviewed-by: Iago Toral Quiroga Reviewed-by: Kenneth Graunke Cc: "17.3" --- src/mesa/drivers/dri/i965/brw_draw.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 7e29dcfd4e..1f86378f5e 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -508,6 +508,8 @@ brw_predraw_resolve_framebuffer(struct brw_context *brw) irb->mt_layer, irb->layer_count, isl_format, ctx->Color.BlendEnabled & (1 << i)); + + brw_cache_flush_for_render(brw, irb->mt->bo); } } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): Re-enable regular fast-clears (CCS_D) on gen9+
Module: Mesa
Branch: master
Commit: f79bb2e651f329364dfb3db0aac4b72f91f130cc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f79bb2e651f329364dfb3db0aac4b72f91f130cc
Author: Jason Ekstrand
Date: Tue Dec 5 14:41:48 2017 -0800
Re-enable regular fast-clears (CCS_D) on gen9+
This reverts commit ee57b15ec764736e2d5360beaef9fb2045ed0f68, "i965:
Disable regular fast-clears (CCS_D) on gen9+". How taht we've fixed the
issue with too many different aux usages in the render cache, it should
be safe to re-enable CCS_D for sRGB.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104163
Tested-by: Eero Tamminen
Reviewed-by: Iago Toral Quiroga
Reviewed-by: Kenneth Graunke
Cc: "17.3"
---
src/mesa/drivers/dri/i965/brw_meta_util.c | 10 -
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 57 ---
2 files changed, 25 insertions(+), 42 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c
b/src/mesa/drivers/dri/i965/brw_meta_util.c
index 54dc6a5ff9..b31181521c 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -293,17 +293,7 @@ brw_is_color_fast_clear_compatible(struct brw_context *brw,
brw->mesa_to_isl_render_format[mt->format])
return false;
- /* Gen9 doesn't support fast clear on single-sampled SRGB buffers. When
-* GL_FRAMEBUFFER_SRGB is enabled any color renderbuffers will be
-* resolved in intel_update_state. In that case it's pointless to do a
-* fast clear because it's very likely to be immediately resolved.
-*/
const bool srgb_rb = _mesa_get_srgb_format_linear(mt->format) != mt->format;
- if (devinfo->gen >= 9 &&
- mt->surf.samples == 1 &&
- ctx->Color.sRGBEnabled && srgb_rb)
- return false;
-
/* Gen10 doesn't automatically decode the clear color of sRGB buffers. Since
* we currently don't perform this decode in software, avoid a fast-clear
* altogether. TODO: Do this in software.
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index ead0c359c0..abdaa6a753 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -211,13 +211,7 @@ intel_miptree_supports_ccs(struct brw_context *brw,
if (!brw->mesa_format_supports_render[mt->format])
return false;
- if (devinfo->gen >= 9) {
- mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
- const enum isl_format isl_format =
- brw_isl_format_for_mesa_format(linear_format);
- return isl_format_supports_ccs_e(&brw->screen->devinfo, isl_format);
- } else
- return true;
+ return true;
}
static bool
@@ -260,7 +254,7 @@ intel_miptree_supports_hiz(const struct brw_context *brw,
* our HW tends to support more linear formats than sRGB ones, we use this
* format variant for check for CCS_E compatibility.
*/
-MAYBE_UNUSED static bool
+static bool
format_ccs_e_compat_with_miptree(const struct gen_device_info *devinfo,
const struct intel_mipmap_tree *mt,
enum isl_format access_format)
@@ -294,12 +288,13 @@ intel_miptree_supports_ccs_e(struct brw_context *brw,
if (!intel_miptree_supports_ccs(brw, mt))
return false;
- /* Fast clear can be also used to clear srgb surfaces by using equivalent
-* linear format. This trick, however, can't be extended to be used with
-* lossless compression and therefore a check is needed to see if the format
-* really is linear.
+ /* Many window system buffers are sRGB even if they are never rendered as
+* sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
+* surface is used as sRGB, we fall back to CCS_D.
*/
- return _mesa_get_srgb_format_linear(mt->format) == mt->format;
+ mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
+ enum isl_format isl_format = brw_isl_format_for_mesa_format(linear_format);
+ return isl_format_supports_ccs_e(&brw->screen->devinfo, isl_format);
}
/**
@@ -2690,29 +2685,27 @@ intel_miptree_render_aux_usage(struct brw_context *brw,
return ISL_AUX_USAGE_MCS;
case ISL_AUX_USAGE_CCS_D:
- /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
- * the single-sampled color renderbuffers because the CCS buffer isn't
- * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
- * enabled because otherwise the surface state will be programmed with
- * the linear equivalent format anyway.
- */
- if (isl_format_is_srgb(render_format) &&
- _mesa_get_srgb_format_linear(mt->format) != mt->format) {
- return ISL_AUX_USAGE_NONE;
- } else if (!mt->mcs_buf) {
- return ISL_AUX_USAGE_NONE;
- } else {
- return ISL_AUX_USAGE_CCS_D;
- }
+ return mt->mcs_buf ? ISL_AUX_USAGE_CCS_D : ISL_AUX_U
Mesa (master): i965/gen6-7/sol: Keep independent counters for the current and previous begin/end block.
Module: Mesa
Branch: master
Commit: f476b3f6e7b9f61c5bd93cf463005fd88aacaeba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f476b3f6e7b9f61c5bd93cf463005fd88aacaeba
Author: Francisco Jerez
Date: Thu Nov 16 14:27:41 2017 -0800
i965/gen6-7/sol: Keep independent counters for the current and previous
begin/end block.
This allows us to aggregate the primitive counts of a completed
transform feedback begin/end block lazily, which in the most typical
case (where glDrawTransformFeedback is not used) will allow us to
avoid aggregating the primitive counters on the CPU altogether,
preventing a stall on previous rendering during
glBeginTransformFeedback(), which dramatically improves performance of
applications that rely heavily on transform feedback.
Improves performance of SynMark2 OglGSCloth by 65.52% ±0.25% (data
gathered on VLV).
Tested-By: Eero Tamminen
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_context.h| 9 ---
src/mesa/drivers/dri/i965/gen6_sol.c | 39 +-
src/mesa/drivers/dri/i965/gen7_sol_state.c | 15 ++--
3 files changed, 36 insertions(+), 27 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 950ede05fc..8d8ab71093 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -579,6 +579,12 @@ struct brw_transform_feedback_object {
struct brw_transform_feedback_counter counter;
/**
+* Count of primitives generated during the previous transform feedback
+* operation. Used to implement DrawTransformFeedback().
+*/
+ struct brw_transform_feedback_counter previous_counter;
+
+ /**
* Number of vertices written between last Begin/EndTransformFeedback().
*
* Used to implement DrawTransformFeedback().
@@ -1519,9 +1525,6 @@ brw_resume_transform_feedback(struct gl_context *ctx,
void
brw_save_primitives_written_counters(struct brw_context *brw,
struct brw_transform_feedback_object
*obj);
-void
-brw_compute_xfb_vertices_written(struct brw_context *brw,
- struct brw_transform_feedback_object *obj);
GLsizei
brw_get_transform_feedback_vertex_count(struct gl_context *ctx,
struct gl_transform_feedback_object
*obj,
diff --git a/src/mesa/drivers/dri/i965/gen6_sol.c
b/src/mesa/drivers/dri/i965/gen6_sol.c
index a909339e16..b1baf01bcd 100644
--- a/src/mesa/drivers/dri/i965/gen6_sol.c
+++ b/src/mesa/drivers/dri/i965/gen6_sol.c
@@ -289,6 +289,8 @@ brw_save_primitives_written_counters(struct brw_context
*brw,
/* Check if there's enough space for a new pair of four values. */
if ((obj->counter.bo_end + 2) * streams * sizeof(uint64_t) >= 4096) {
aggregate_transform_feedback_counter(brw, obj->prim_count_bo,
+ &obj->previous_counter);
+ aggregate_transform_feedback_counter(brw, obj->prim_count_bo,
&obj->counter);
}
@@ -316,6 +318,7 @@ brw_save_primitives_written_counters(struct brw_context
*brw,
static void
compute_vertices_written_so_far(struct brw_context *brw,
struct brw_transform_feedback_object *obj,
+struct brw_transform_feedback_counter *counter,
uint64_t *vertices_written)
{
const struct gl_context *ctx = &brw->ctx;
@@ -336,25 +339,26 @@ compute_vertices_written_so_far(struct brw_context *brw,
}
/* Get the number of primitives generated. */
- aggregate_transform_feedback_counter(brw, obj->prim_count_bo,
&obj->counter);
+ aggregate_transform_feedback_counter(brw, obj->prim_count_bo, counter);
for (int i = 0; i < ctx->Const.MaxVertexStreams; i++) {
- vertices_written[i] = vertices_per_prim * obj->counter.accum[i];
+ vertices_written[i] = vertices_per_prim * counter->accum[i];
}
}
/**
- * Compute the number of vertices written by this transform feedback operation.
+ * Compute the number of vertices written by the last transform feedback
+ * begin/end block.
*/
-void
-brw_compute_xfb_vertices_written(struct brw_context *brw,
- struct brw_transform_feedback_object *obj)
+static void
+compute_xfb_vertices_written(struct brw_context *brw,
+ struct brw_transform_feedback_object *obj)
{
if (obj->vertices_written_valid || !obj->base.EndedAnytime)
return;
- compute_vertices_written_so_far(brw, obj, obj->vertices_written);
-
+ compute_vertices_written_so_far(brw, obj, &obj->previous_counter,
+ obj->vertices_written);
obj->vertices_written_valid = true;
}
@@ -376,7 +380,7 @@ brw_get_transform_feedback_vertex_count(struct gl_context
*ctx,
assert(obj->EndedAnytime);
assert(stream < ctx->Const.MaxVertexStre
Mesa (master): i965/gen6-7/sol: Restructure primitive counter into a separate type.
Module: Mesa
Branch: master
Commit: b0c8d61281d5e09cd216e1ff3f2c441f7c550a47
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0c8d61281d5e09cd216e1ff3f2c441f7c550a47
Author: Francisco Jerez
Date: Fri Nov 17 14:06:04 2017 -0800
i965/gen6-7/sol: Restructure primitive counter into a separate type.
A primitive counter encapsulates a scalar aggregating counter for each
vertex stream along with a section within the primitive tally buffer
which hasn't been read out yet. Defining this as a separate type will
allow us to keep multiple counter objects around for the same
transform feedback object without any code duplication.
Tested-By: Eero Tamminen
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_context.h| 38 ++---
src/mesa/drivers/dri/i965/gen6_sol.c | 53 ++
src/mesa/drivers/dri/i965/gen7_sol_state.c | 6 +---
3 files changed, 58 insertions(+), 39 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 0f0aad8534..950ede05fc 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -523,6 +523,36 @@ struct intel_batchbuffer {
#define BRW_MAX_XFB_STREAMS 4
+struct brw_transform_feedback_counter {
+ /**
+* Index of the first entry of this counter within the primitive count BO.
+* An entry is considered to be an N-tuple of 64bit values, where N is the
+* number of vertex streams supported by the platform.
+*/
+ unsigned bo_start;
+
+ /**
+* Index one past the last entry of this counter within the primitive
+* count BO.
+*/
+ unsigned bo_end;
+
+ /**
+* Primitive count values accumulated while this counter was active,
+* excluding any entries buffered between \c bo_start and \c bo_end, which
+* haven't been accounted for yet.
+*/
+ uint64_t accum[BRW_MAX_XFB_STREAMS];
+};
+
+static inline void
+brw_reset_transform_feedback_counter(
+ struct brw_transform_feedback_counter *counter)
+{
+ counter->bo_start = counter->bo_end;
+ memset(&counter->accum, 0, sizeof(counter->accum));
+}
+
struct brw_transform_feedback_object {
struct gl_transform_feedback_object base;
@@ -541,14 +571,12 @@ struct brw_transform_feedback_object {
*/
unsigned max_index;
+ struct brw_bo *prim_count_bo;
+
/**
* Count of primitives generated during this transform feedback operation.
-* @{
*/
- uint64_t prims_generated[BRW_MAX_XFB_STREAMS];
- struct brw_bo *prim_count_bo;
- unsigned prim_count_buffer_index; /**< in number of uint64_t units */
- /** @} */
+ struct brw_transform_feedback_counter counter;
/**
* Number of vertices written between last Begin/EndTransformFeedback().
diff --git a/src/mesa/drivers/dri/i965/gen6_sol.c
b/src/mesa/drivers/dri/i965/gen6_sol.c
index 7a510940c8..a909339e16 100644
--- a/src/mesa/drivers/dri/i965/gen6_sol.c
+++ b/src/mesa/drivers/dri/i965/gen6_sol.c
@@ -233,37 +233,36 @@ brw_delete_transform_feedback(struct gl_context *ctx,
* Note that we expose one stream pre-Gen7, so the above is just (start, end).
*/
static void
-tally_prims_generated(struct brw_context *brw,
- struct brw_transform_feedback_object *obj)
+aggregate_transform_feedback_counter(
+ struct brw_context *brw,
+ struct brw_bo *bo,
+ struct brw_transform_feedback_counter *counter)
{
- const struct gl_context *ctx = &brw->ctx;
- const int streams = ctx->Const.MaxVertexStreams;
+ const unsigned streams = brw->ctx.Const.MaxVertexStreams;
/* If the current batch is still contributing to the number of primitives
* generated, flush it now so the results will be present when mapped.
*/
- if (brw_batch_references(&brw->batch, obj->prim_count_bo))
+ if (brw_batch_references(&brw->batch, bo))
intel_batchbuffer_flush(brw);
- if (unlikely(brw->perf_debug && brw_bo_busy(obj->prim_count_bo)))
+ if (unlikely(brw->perf_debug && brw_bo_busy(bo)))
perf_debug("Stalling for # of transform feedback primitives written.\n");
- uint64_t *prim_counts = brw_bo_map(brw, obj->prim_count_bo, MAP_READ);
+ uint64_t *prim_counts = brw_bo_map(brw, bo, MAP_READ);
+ prim_counts += counter->bo_start * streams;
- assert(obj->prim_count_buffer_index % (2 * streams) == 0);
- int pairs = obj->prim_count_buffer_index / (2 * streams);
+ for (unsigned i = counter->bo_start; i + 1 < counter->bo_end; i += 2) {
+ for (unsigned s = 0; s < streams; s++)
+ counter->accum[s] += prim_counts[streams + s] - prim_counts[s];
- for (int i = 0; i < pairs; i++) {
- for (int s = 0; s < streams; s++) {
- obj->prims_generated[s] += prim_counts[streams + s] - prim_counts[s];
- }
- prim_counts += 2 * streams; /* move to the next pair */
+ prim_counts += 2 * streams;
}
- brw_bo_unmap(obj->prim_count_bo);
+ brw_bo_unmap(bo);
/* We've already gat
Mesa (master): i965/gen6-7/sol: Bump primitive counter BO size.
Module: Mesa
Branch: master
Commit: 53d8508f1d964423123b7a444e07eabe2d723f7e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=53d8508f1d964423123b7a444e07eabe2d723f7e
Author: Francisco Jerez
Date: Fri Nov 17 14:07:21 2017 -0800
i965/gen6-7/sol: Bump primitive counter BO size.
Improves performance of SynMark2 OglGSCloth by a further 9.65%±0.59%
due to the reduction in overwraps of the primitive count buffer that
lead to a CPU stall on previous rendering. Cummulative performance
improvement from the series 81.50% ±0.96% (data gathered on VLV).
Tested-By: Eero Tamminen
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/gen6_sol.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_sol.c
b/src/mesa/drivers/dri/i965/gen6_sol.c
index b1baf01bcd..355acd4218 100644
--- a/src/mesa/drivers/dri/i965/gen6_sol.c
+++ b/src/mesa/drivers/dri/i965/gen6_sol.c
@@ -197,7 +197,7 @@ brw_new_transform_feedback(struct gl_context *ctx, GLuint
name)
brw_obj->offset_bo =
brw_bo_alloc(brw->bufmgr, "transform feedback offsets", 16, 64);
brw_obj->prim_count_bo =
- brw_bo_alloc(brw->bufmgr, "xfb primitive counts", 4096, 64);
+ brw_bo_alloc(brw->bufmgr, "xfb primitive counts", 16384, 64);
return &brw_obj->base;
}
@@ -287,7 +287,8 @@ brw_save_primitives_written_counters(struct brw_context
*brw,
assert(obj->prim_count_bo != NULL);
/* Check if there's enough space for a new pair of four values. */
- if ((obj->counter.bo_end + 2) * streams * sizeof(uint64_t) >= 4096) {
+ if ((obj->counter.bo_end + 2) * streams * sizeof(uint64_t) >=
+ obj->prim_count_bo->size) {
aggregate_transform_feedback_counter(brw, obj->prim_count_bo,
&obj->previous_counter);
aggregate_transform_feedback_counter(brw, obj->prim_count_bo,
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Mesa (master): st/mesa: enable ARB_enhanced_layouts on nir drivers
Module: Mesa
Branch: master
Commit: dc520dafdcfccd20071dc560b39e3d93ffdbafe4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc520dafdcfccd20071dc560b39e3d93ffdbafe4
Author: Timothy Arceri
Date: Fri Jan 12 16:42:47 2018 +1100
st/mesa: enable ARB_enhanced_layouts on nir drivers
I'm guessing this may have been disable because of missing
component packing support. However recent nir linking changes
required nir based gallium drivers to support component packing
so this should now be ok to enable.
Reviewed-by: Marek Olšák
---
src/mesa/state_tracker/st_extensions.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index 9ef0df1e92..c8411a6995 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -956,9 +956,7 @@ void st_init_extensions(struct pipe_screen *screen,
}
if (consts->GLSLVersion >= 140) {
- if (screen->get_param(screen, PIPE_CAP_TGSI_ARRAY_COMPONENTS) &&
- screen->get_shader_param(screen, PIPE_SHADER_FRAGMENT,
- PIPE_SHADER_CAP_PREFERRED_IR) ==
PIPE_SHADER_IR_TGSI)
+ if (screen->get_param(screen, PIPE_CAP_TGSI_ARRAY_COMPONENTS))
extensions->ARB_enhanced_layouts = GL_TRUE;
}
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Mesa (master): draw: fix vsplit code when the (post-bias) index value is -1
Module: Mesa
Branch: master
Commit: 1f462eaf394517dac98b0c41f09e995f2940fdb8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f462eaf394517dac98b0c41f09e995f2940fdb8
Author: Roland Scheidegger
Date: Tue Jan 16 03:01:56 2018 +0100
draw: fix vsplit code when the (post-bias) index value is -1
vsplit_add_cache uses the post-bias index for hashing, but the
vsplit_add_cache_uint/ushort/ubyte ones used the pre-bias index, therefore
the code for handling the special case (because -1 matches the initialization
value of the cache) wasn't actually working.
Commit 78a997f72841310620d18daa9015633343d04db1 actually simplified the
cache logic somewhat, but it looks like this particular problem carried over
(and duplicated to the ushort/ubyte cases, since before only uint needed it).
This could lead to the vsplit cache doing the wrong thing, in particular
later fetch_info might indicate there are 0 values to fetch. This only really
affected edge cases which were bogus to begin with, but it could lead to a
crash with the jit vertex shader, since it cannot handle this case correctly
(the count loop is always executed at least once and we would not allocate
any memory for the shader outputs), so add another assert to catch it there.
Reviewed-by: Brian Paul
Reviewed-by: Jose Fonseca
---
src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline_llvm.c | 1 +
src/gallium/auxiliary/draw/draw_pt_vsplit.c| 6 +++---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline_llvm.c
b/src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline_llvm.c
index c6492a18cf..5e0c562256 100644
--- a/src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline_llvm.c
+++ b/src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline_llvm.c
@@ -368,6 +368,7 @@ llvm_pipeline_generic(struct draw_pt_middle_end *middle,
unsigned start_or_maxelt, vid_base;
const unsigned *elts;
+ assert(fetch_info->count > 0);
llvm_vert_info.count = fetch_info->count;
llvm_vert_info.vertex_size = fpme->vertex_size;
llvm_vert_info.stride = fpme->vertex_size;
diff --git a/src/gallium/auxiliary/draw/draw_pt_vsplit.c
b/src/gallium/auxiliary/draw/draw_pt_vsplit.c
index a68d5bf971..3ff077b760 100644
--- a/src/gallium/auxiliary/draw/draw_pt_vsplit.c
+++ b/src/gallium/auxiliary/draw/draw_pt_vsplit.c
@@ -133,7 +133,7 @@ vsplit_add_cache_ubyte(struct vsplit_frontend *vsplit,
const ubyte *elts,
VSPLIT_CREATE_IDX(elts, start, fetch, elt_bias);
/* unlike the uint case this can only happen with elt_bias */
if (elt_bias && elt_idx == DRAW_MAX_FETCH_IDX &&
!vsplit->cache.has_max_fetch) {
- unsigned hash = fetch % MAP_SIZE;
+ unsigned hash = elt_idx % MAP_SIZE;
vsplit->cache.fetches[hash] = 0;
vsplit->cache.has_max_fetch = TRUE;
}
@@ -148,7 +148,7 @@ vsplit_add_cache_ushort(struct vsplit_frontend *vsplit,
const ushort *elts,
VSPLIT_CREATE_IDX(elts, start, fetch, elt_bias);
/* unlike the uint case this can only happen with elt_bias */
if (elt_bias && elt_idx == DRAW_MAX_FETCH_IDX &&
!vsplit->cache.has_max_fetch) {
- unsigned hash = fetch % MAP_SIZE;
+ unsigned hash = elt_idx % MAP_SIZE;
vsplit->cache.fetches[hash] = 0;
vsplit->cache.has_max_fetch = TRUE;
}
@@ -168,7 +168,7 @@ vsplit_add_cache_uint(struct vsplit_frontend *vsplit, const
uint *elts,
VSPLIT_CREATE_IDX(elts, start, fetch, elt_bias);
/* Take care for DRAW_MAX_FETCH_IDX (since cache is initialized to -1). */
if (elt_idx == DRAW_MAX_FETCH_IDX && !vsplit->cache.has_max_fetch) {
- unsigned hash = fetch % MAP_SIZE;
+ unsigned hash = elt_idx % MAP_SIZE;
/* force update - any value will do except DRAW_MAX_FETCH_IDX */
vsplit->cache.fetches[hash] = 0;
vsplit->cache.has_max_fetch = TRUE;
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Mesa (master): draw: remove VSPLIT_CREATE_IDX macro
Module: Mesa
Branch: master
Commit: b0413cfd8b84634db4a5bf57d550b21d0d2fa8f7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0413cfd8b84634db4a5bf57d550b21d0d2fa8f7
Author: Roland Scheidegger
Date: Tue Jan 16 17:55:00 2018 +0100
draw: remove VSPLIT_CREATE_IDX macro
Just inline the little bit of code.
Reviewed-by: Jose Fonseca
Reviewed-by: Brian Paul
---
src/gallium/auxiliary/draw/draw_pt_vsplit.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/src/gallium/auxiliary/draw/draw_pt_vsplit.c
b/src/gallium/auxiliary/draw/draw_pt_vsplit.c
index 3ff077b760..653deab28c 100644
--- a/src/gallium/auxiliary/draw/draw_pt_vsplit.c
+++ b/src/gallium/auxiliary/draw/draw_pt_vsplit.c
@@ -116,21 +116,15 @@ vsplit_get_base_idx(unsigned start, unsigned fetch)
return draw_overflow_uadd(start, fetch, MAX_ELT_IDX);
}
-/*
- * The final element index is just element index plus element bias.
- */
-#define VSPLIT_CREATE_IDX(elts, start, fetch, elt_bias)\
- unsigned elt_idx; \
- elt_idx = vsplit_get_base_idx(start, fetch);\
- elt_idx = (unsigned)((int)(DRAW_GET_IDX(elts, elt_idx)) + (int)elt_bias);
-
static inline void
vsplit_add_cache_ubyte(struct vsplit_frontend *vsplit, const ubyte *elts,
unsigned start, unsigned fetch, int elt_bias)
{
struct draw_context *draw = vsplit->draw;
- VSPLIT_CREATE_IDX(elts, start, fetch, elt_bias);
+ unsigned elt_idx;
+ elt_idx = vsplit_get_base_idx(start, fetch);
+ elt_idx = (unsigned)((int)(DRAW_GET_IDX(elts, elt_idx)) + elt_bias);
/* unlike the uint case this can only happen with elt_bias */
if (elt_bias && elt_idx == DRAW_MAX_FETCH_IDX &&
!vsplit->cache.has_max_fetch) {
unsigned hash = elt_idx % MAP_SIZE;
@@ -145,7 +139,9 @@ vsplit_add_cache_ushort(struct vsplit_frontend *vsplit,
const ushort *elts,
unsigned start, unsigned fetch, int elt_bias)
{
struct draw_context *draw = vsplit->draw;
- VSPLIT_CREATE_IDX(elts, start, fetch, elt_bias);
+ unsigned elt_idx;
+ elt_idx = vsplit_get_base_idx(start, fetch);
+ elt_idx = (unsigned)((int)(DRAW_GET_IDX(elts, elt_idx)) + elt_bias);
/* unlike the uint case this can only happen with elt_bias */
if (elt_bias && elt_idx == DRAW_MAX_FETCH_IDX &&
!vsplit->cache.has_max_fetch) {
unsigned hash = elt_idx % MAP_SIZE;
@@ -165,7 +161,12 @@ vsplit_add_cache_uint(struct vsplit_frontend *vsplit,
const uint *elts,
unsigned start, unsigned fetch, int elt_bias)
{
struct draw_context *draw = vsplit->draw;
- VSPLIT_CREATE_IDX(elts, start, fetch, elt_bias);
+ unsigned elt_idx;
+ /*
+* The final element index is just element index plus element bias.
+*/
+ elt_idx = vsplit_get_base_idx(start, fetch);
+ elt_idx = (unsigned)((int)(DRAW_GET_IDX(elts, elt_idx)) + elt_bias);
/* Take care for DRAW_MAX_FETCH_IDX (since cache is initialized to -1). */
if (elt_idx == DRAW_MAX_FETCH_IDX && !vsplit->cache.has_max_fetch) {
unsigned hash = elt_idx % MAP_SIZE;
___
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Mesa (master): osmesa: don't check SmoothFlag twice
Module: Mesa Branch: master Commit: 6129c03cc7328696f69c5aaa7e204c8257174933 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6129c03cc7328696f69c5aaa7e204c8257174933 Author: Grazvydas Ignotas Date: Sun Jan 14 21:52:52 2018 +0200 osmesa: don't check SmoothFlag twice Trivial. Found by Coccinelle. Reviewed-by: Eric Engestrom --- src/mesa/drivers/osmesa/osmesa.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mesa/drivers/osmesa/osmesa.c b/src/mesa/drivers/osmesa/osmesa.c index 1df3da4cd2..e0f87b850a 100644 --- a/src/mesa/drivers/osmesa/osmesa.c +++ b/src/mesa/drivers/osmesa/osmesa.c @@ -214,7 +214,6 @@ osmesa_choose_line_function( struct gl_context *ctx ) } if (ctx->RenderMode != GL_RENDER || - ctx->Line.SmoothFlag || ctx->Texture._MaxEnabledTexImageUnit == -1 || ctx->Light.ShadeModel != GL_FLAT || ctx->Line.Width != 1.0F || ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeon: remove unneeded semicolons
Module: Mesa
Branch: master
Commit: e3adb1abaf739f317df3a67f61aea2013e88c840
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e3adb1abaf739f317df3a67f61aea2013e88c840
Author: Grazvydas Ignotas
Date: Sun Jan 14 23:40:25 2018 +0200
radeon: remove unneeded semicolons
Trivial. Found by Coccinelle.
Reviewed-by: Eric Engestrom
---
src/gallium/drivers/radeon/radeon_vcn_dec.c | 6 +++---
src/mesa/drivers/dri/radeon/radeon_debug.c | 2 +-
src/mesa/drivers/dri/radeon/radeon_state_init.c | 2 +-
src/mesa/drivers/dri/radeon/radeon_swtcl.c | 2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index d51eb6e394..f83e9e5fc4 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -640,10 +640,10 @@ static struct pb_buffer *rvcn_dec_message_decode(struct
radeon_decoder *dec,
index->size = sizeof(rvcn_dec_message_avc_t);
index->filled = 0;
- decode->stream_type = dec->stream_type;;
+ decode->stream_type = dec->stream_type;
decode->decode_flags = 0x1;
- decode->width_in_samples = dec->base.width;;
- decode->height_in_samples = dec->base.height;;
+ decode->width_in_samples = dec->base.width;
+ decode->height_in_samples = dec->base.height;
decode->bsd_size = align(dec->bs_size, 128);
decode->dpb_size = dec->dpb.res->buf->size;
diff --git a/src/mesa/drivers/dri/radeon/radeon_debug.c
b/src/mesa/drivers/dri/radeon/radeon_debug.c
index 383a5df674..91f86a96b5 100644
--- a/src/mesa/drivers/dri/radeon/radeon_debug.c
+++ b/src/mesa/drivers/dri/radeon/radeon_debug.c
@@ -75,7 +75,7 @@ void _radeon_debug_add_indent(void)
if (radeon->debug.indent_depth < length - 1) {
radeon->debug.indent[radeon->debug.indent_depth] = '\t';
++radeon->debug.indent_depth;
- };
+ }
}
void _radeon_debug_remove_indent(void)
diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c
b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index 99c535a49c..b847be54c4 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -440,7 +440,7 @@ static void cube_emit_cs(struct gl_context *ctx, struct
radeon_state_atom *atom)
case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break;
default:
case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break;
- };
+ }
BEGIN_BATCH(dwords);
OUT_BATCH_TABLE(atom->cmd, 2);
lvl = &t->mt->levels[0];
diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c
b/src/mesa/drivers/dri/radeon/radeon_swtcl.c
index d5365cddcd..860bba6d32 100644
--- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c
@@ -209,7 +209,7 @@ static void radeonSetVertexFormat( struct gl_context *ctx )
break;
default:
continue;
- };
+ }
}
}
}
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Mesa (master): st/va: release held locks in error paths
Module: Mesa
Branch: master
Commit: 0ad73031ec2f9dee6d3ad20dd625b0134ea8ec8b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ad73031ec2f9dee6d3ad20dd625b0134ea8ec8b
Author: Grazvydas Ignotas
Date: Mon Jan 15 23:59:20 2018 +0200
st/va: release held locks in error paths
Found with the help of following Coccinelle semantic patch:
//
@@
expression E;
@@
\(pthread_mutex_lock\|mtx_lock\|simple_mtx_lock\)(E)
...
(
\(pthread_mutex_unlock\|mtx_unlock\|simple_mtx_unlock\)(E);
...
return ...;
|
+ maybe need_unlock(E);
return ...;
)
//
Signed-off-by: Grazvydas Ignotas
Reviewed-by: Christian König
Cc: mesa-sta...@lists.freedesktop.org
---
src/gallium/state_trackers/va/config.c | 4 +++-
src/gallium/state_trackers/va/image.c | 4 +++-
src/gallium/state_trackers/va/picture.c | 4 +++-
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/gallium/state_trackers/va/config.c
b/src/gallium/state_trackers/va/config.c
index 25043d6374..7bc031a1a2 100644
--- a/src/gallium/state_trackers/va/config.c
+++ b/src/gallium/state_trackers/va/config.c
@@ -308,8 +308,10 @@ vlVaDestroyConfig(VADriverContextP ctx, VAConfigID
config_id)
mtx_lock(&drv->mutex);
config = handle_table_get(drv->htab, config_id);
- if (!config)
+ if (!config) {
+ mtx_unlock(&drv->mutex);
return VA_STATUS_ERROR_INVALID_CONFIG;
+ }
FREE(config);
handle_table_remove(drv->htab, config_id);
diff --git a/src/gallium/state_trackers/va/image.c
b/src/gallium/state_trackers/va/image.c
index 86ae868580..3f892c9842 100644
--- a/src/gallium/state_trackers/va/image.c
+++ b/src/gallium/state_trackers/va/image.c
@@ -548,8 +548,10 @@ vlVaPutImage(VADriverContextP ctx, VASurfaceID surface,
VAImageID image,
PIPE_TRANSFER_WRITE |
PIPE_TRANSFER_DISCARD_RANGE,
&dst_box, &transfer);
-if (map == NULL)
+if (map == NULL) {
+ mtx_unlock(&drv->mutex);
return VA_STATUS_ERROR_OPERATION_FAILED;
+}
u_copy_nv12_from_yv12((const void * const*) data, pitches, i, j,
transfer->stride, tex->array_size,
diff --git a/src/gallium/state_trackers/va/picture.c
b/src/gallium/state_trackers/va/picture.c
index 23a4b524d7..22934e43cc 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -682,9 +682,11 @@ vlVaEndPicture(VADriverContextP ctx, VAContextID
context_id)
vl_compositor_yuv_deint_full(&drv->cstate, &drv->compositor,
old_buf, surf->buffer,
&src_rect, &dst_rect,
VL_COMPOSITOR_WEAVE);
- } else
+ } else {
/* Can't convert from progressive to interlaced yet */
+mtx_unlock(&drv->mutex);
return VA_STATUS_ERROR_INVALID_SURFACE;
+ }
}
old_buf->destroy(old_buf);
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Mesa (master): mesa: remove unneeded semicolons
Module: Mesa
Branch: master
Commit: cce982a70be5e24c6f6ee222c17c47eb8cba6921
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cce982a70be5e24c6f6ee222c17c47eb8cba6921
Author: Grazvydas Ignotas
Date: Sun Jan 14 23:45:05 2018 +0200
mesa: remove unneeded semicolons
Trivial. Found by Coccinelle.
Reviewed-by: Eric Engestrom
---
src/gbm/backends/dri/gbm_dri.c | 2 +-
src/mesa/main/dlist.c| 2 +-
src/mesa/main/program_resource.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gbm/backends/dri/gbm_dri.c b/src/gbm/backends/dri/gbm_dri.c
index b2121cbc34..fd5fb4b91c 100644
--- a/src/gbm/backends/dri/gbm_dri.c
+++ b/src/gbm/backends/dri/gbm_dri.c
@@ -440,7 +440,7 @@ dri_screen_create_dri2(struct gbm_dri_device *dri, char
*driver_name)
if (ret) {
fprintf(stderr, "failed to load driver: %s\n", dri->driver_name);
return ret;
- };
+ }
dri->loader_extensions = gbm_dri_screen_extensions;
diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
index b7d1406eb7..a6b212e25e 100644
--- a/src/mesa/main/dlist.c
+++ b/src/mesa/main/dlist.c
@@ -1912,7 +1912,7 @@ save_CallLists(GLsizei num, GLenum type, const GLvoid *
lists)
n[1].i = num;
n[2].e = type;
save_pointer(&n[3], lists_copy);
- };
+ }
/* After this, we don't know what state we're in. Invalidate all
* cached information previously gathered:
diff --git a/src/mesa/main/program_resource.c b/src/mesa/main/program_resource.c
index 4eacdfb9e9..5fa5d7573b 100644
--- a/src/mesa/main/program_resource.c
+++ b/src/mesa/main/program_resource.c
@@ -200,7 +200,7 @@ _mesa_GetProgramInterfaceiv(GLuint program, GLenum
programInterface,
"glGetProgramInterfaceiv(%s pname %s)",
_mesa_enum_to_string(programInterface),
_mesa_enum_to_string(pname));
- };
+ }
break;
case GL_MAX_NUM_COMPATIBLE_SUBROUTINES:
switch (programInterface) {
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Mesa (master): ac: import lp_create_builder() from gallivm
Module: Mesa
Branch: master
Commit: 2091206ad3764c94317bd700cc551f9c31a2847d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2091206ad3764c94317bd700cc551f9c31a2847d
Author: Samuel Pitoiset
Date: Mon Jan 15 14:51:43 2018 +0100
ac: import lp_create_builder() from gallivm
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/common/ac_llvm_helper.cpp | 30 ++
src/amd/common/ac_llvm_util.h | 9 +++
src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 29 -
src/gallium/auxiliary/gallivm/lp_bld_misc.h| 9 ---
.../drivers/radeonsi/si_shader_tgsi_setup.c| 8 +++---
5 files changed, 43 insertions(+), 42 deletions(-)
diff --git a/src/amd/common/ac_llvm_helper.cpp
b/src/amd/common/ac_llvm_helper.cpp
index 4db703622c..e42d00280b 100644
--- a/src/amd/common/ac_llvm_helper.cpp
+++ b/src/amd/common/ac_llvm_helper.cpp
@@ -35,6 +35,7 @@
#include
#include
#include
+#include
#if HAVE_LLVM < 0x0500
namespace llvm {
@@ -80,3 +81,32 @@ bool ac_llvm_is_function(LLVMValueRef v)
return llvm::isa(llvm::unwrap(v));
#endif
}
+
+LLVMBuilderRef ac_create_builder(LLVMContextRef ctx,
+enum ac_float_mode float_mode)
+{
+ LLVMBuilderRef builder = LLVMCreateBuilderInContext(ctx);
+
+#if HAVE_LLVM >= 0x0308
+ llvm::FastMathFlags flags;
+
+ switch (float_mode) {
+ case AC_FLOAT_MODE_DEFAULT:
+ break;
+ case AC_FLOAT_MODE_NO_SIGNED_ZEROS_FP_MATH:
+ flags.setNoSignedZeros();
+ llvm::unwrap(builder)->setFastMathFlags(flags);
+ break;
+ case AC_FLOAT_MODE_UNSAFE_FP_MATH:
+#if HAVE_LLVM >= 0x0600
+ flags.setFast();
+#else
+ flags.setUnsafeAlgebra();
+#endif
+ llvm::unwrap(builder)->setFastMathFlags(flags);
+ break;
+ }
+#endif
+
+ return builder;
+}
diff --git a/src/amd/common/ac_llvm_util.h b/src/amd/common/ac_llvm_util.h
index 61bcc4e54e..84fcbf111c 100644
--- a/src/amd/common/ac_llvm_util.h
+++ b/src/amd/common/ac_llvm_util.h
@@ -62,6 +62,12 @@ enum ac_target_machine_options {
AC_TM_PROMOTE_ALLOCA_TO_SCRATCH = (1 << 4),
};
+enum ac_float_mode {
+ AC_FLOAT_MODE_DEFAULT,
+ AC_FLOAT_MODE_NO_SIGNED_ZEROS_FP_MATH,
+ AC_FLOAT_MODE_UNSAFE_FP_MATH,
+};
+
const char *ac_get_llvm_processor_name(enum radeon_family family);
LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family, enum
ac_target_machine_options tm_options);
@@ -77,6 +83,9 @@ void ac_dump_module(LLVMModuleRef module);
LLVMValueRef ac_llvm_get_called_value(LLVMValueRef call);
bool ac_llvm_is_function(LLVMValueRef v);
+LLVMBuilderRef ac_create_builder(LLVMContextRef ctx,
+enum ac_float_mode float_mode);
+
void
ac_llvm_add_target_dep_function_attr(LLVMValueRef F,
const char *name, int value);
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
index 1319407290..79dbedbb56 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
+++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
@@ -813,32 +813,3 @@ lp_is_function(LLVMValueRef v)
return llvm::isa(llvm::unwrap(v));
#endif
}
-
-extern "C" LLVMBuilderRef
-lp_create_builder(LLVMContextRef ctx, enum lp_float_mode float_mode)
-{
- LLVMBuilderRef builder = LLVMCreateBuilderInContext(ctx);
-
-#if HAVE_LLVM >= 0x0308
- llvm::FastMathFlags flags;
-
- switch (float_mode) {
- case LP_FLOAT_MODE_DEFAULT:
- break;
- case LP_FLOAT_MODE_NO_SIGNED_ZEROS_FP_MATH:
- flags.setNoSignedZeros();
- llvm::unwrap(builder)->setFastMathFlags(flags);
- break;
- case LP_FLOAT_MODE_UNSAFE_FP_MATH:
-#if HAVE_LLVM >= 0x0600
- flags.setFast();
-#else
- flags.setUnsafeAlgebra();
-#endif
- llvm::unwrap(builder)->setFastMathFlags(flags);
- break;
- }
-#endif
-
- return builder;
-}
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.h
b/src/gallium/auxiliary/gallivm/lp_bld_misc.h
index 1b725d10d7..ca5ba5c44f 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.h
@@ -76,15 +76,6 @@ lp_get_called_value(LLVMValueRef call);
extern bool
lp_is_function(LLVMValueRef v);
-enum lp_float_mode {
- LP_FLOAT_MODE_DEFAULT,
- LP_FLOAT_MODE_NO_SIGNED_ZEROS_FP_MATH,
- LP_FLOAT_MODE_UNSAFE_FP_MATH,
-};
-
-extern LLVMBuilderRef
-lp_create_builder(LLVMContextRef ctx, enum lp_float_mode float_mode);
-
#ifdef __cplusplus
}
#endif
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
index 2ca036e67d..fc141ca1e0 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
@@ -1160,11 +1160,11 @@ void si_llvm_con
Mesa (master): ac: set fast math flags when RADV_DEBUG="unsafemath" is used
Module: Mesa Branch: master Commit: 4f5318df2cba4f4a455cf3a5aaa020908806987d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f5318df2cba4f4a455cf3a5aaa020908806987d Author: Samuel Pitoiset Date: Mon Jan 15 14:51:44 2018 +0100 ac: set fast math flags when RADV_DEBUG="unsafemath" is used When that debug option is not used, we use the default float mode because the no signed zeros optimisation is not Vulkan compatible. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/common/ac_nir_to_llvm.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index aca9a0a260..635a74d243 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -6683,7 +6683,11 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm, LLVMDisposeTargetData(data_layout); LLVMDisposeMessage(data_layout_str); - ctx.builder = LLVMCreateBuilderInContext(ctx.context); + enum ac_float_mode float_mode = + options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH : + AC_FLOAT_MODE_DEFAULT; + + ctx.builder = ac_create_builder(ctx.context, float_mode); ctx.ac.builder = ctx.builder; memset(shader_info, 0, sizeof(*shader_info)); @@ -7095,7 +7099,11 @@ void ac_create_gs_copy_shader(LLVMTargetMachineRef tm, ctx.is_gs_copy_shader = true; LLVMSetTarget(ctx.module, "amdgcn--"); - ctx.builder = LLVMCreateBuilderInContext(ctx.context); + enum ac_float_mode float_mode = + options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH : + AC_FLOAT_MODE_DEFAULT; + + ctx.builder = ac_create_builder(ctx.context, float_mode); ctx.ac.builder = ctx.builder; ctx.stage = MESA_SHADER_VERTEX; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): ac: set no-signed-zeros-fp-math when RADV_DEBUG="unsafemath" is used
Module: Mesa Branch: master Commit: 05f73b96721518314729e49b7cadfb2d915a9ff5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=05f73b96721518314729e49b7cadfb2d915a9ff5 Author: Samuel Pitoiset Date: Mon Jan 15 14:51:45 2018 +0100 ac: set no-signed-zeros-fp-math when RADV_DEBUG="unsafemath" is used This is an optimisation that is recommended by Matt Arsenault, and used by RadeonSI, but it's not compatible with Vulkan. Note that AC_FLOAT_MODE_UNSAFE_FP_MATH includes the no signed zeros flag in LLVM. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/common/ac_nir_to_llvm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 635a74d243..5a8ddf13d7 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -352,6 +352,9 @@ create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module, LLVMAddTargetDependentFunctionAttr(main_function, "unsafe-fp-math", "true"); + LLVMAddTargetDependentFunctionAttr(main_function, + "no-signed-zeros-fp-math", + "true"); } return main_function; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): ac: replace llvm.AMDGPU.kilp by llvm.amdgcn.kill with LLVM 6
Module: Mesa
Branch: master
Commit: ad2b3b2a9cefc28f8bd78a116ab549a08d35ec35
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad2b3b2a9cefc28f8bd78a116ab549a08d35ec35
Author: Samuel Pitoiset
Date: Thu Jan 11 16:45:11 2018 +0100
ac: replace llvm.AMDGPU.kilp by llvm.amdgcn.kill with LLVM 6
This also replaces llvm.AMDGPU.kilp by llvm.AMDGPU.kill with
LLVM < 6. Similar to RadeonSI codepath.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/common/ac_nir_to_llvm.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 2034039543..aca9a0a260 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3867,14 +3867,20 @@ static void emit_barrier(struct ac_llvm_context *ac,
gl_shader_stage stage)
ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
}
-static void emit_discard_if(struct ac_nir_context *ctx,
- const nir_intrinsic_instr *instr)
+static void emit_discard(struct ac_nir_context *ctx,
+const nir_intrinsic_instr *instr)
{
LLVMValueRef cond;
- cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
-get_src(ctx, instr->src[0]),
-ctx->ac.i32_0, "");
+ if (instr->intrinsic == nir_intrinsic_discard_if) {
+ cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
+get_src(ctx, instr->src[0]),
+ctx->ac.i32_0, "");
+ } else {
+ assert(instr->intrinsic == nir_intrinsic_discard);
+ cond = LLVMConstInt(ctx->ac.i1, false, 0);
+ }
+
ac_build_kill_if_false(&ctx->ac, cond);
}
@@ -4348,12 +4354,8 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
result = visit_image_size(ctx, instr);
break;
case nir_intrinsic_discard:
- ac_build_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
- LLVMVoidTypeInContext(ctx->ac.context),
- NULL, 0, AC_FUNC_ATTR_LEGACY);
- break;
case nir_intrinsic_discard_if:
- emit_discard_if(ctx, instr);
+ emit_discard(ctx, instr);
break;
case nir_intrinsic_memory_barrier:
case nir_intrinsic_group_memory_barrier:
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Mesa (master): glsl/linker: link-error using the same name in unnamed block and outside
Module: Mesa
Branch: master
Commit: 9b894c88a688904860d0f37221b78fbcb168f216
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b894c88a688904860d0f37221b78fbcb168f216
Author: Juan A. Suarez Romero
Date: Tue Jan 16 19:42:35 2018 +0100
glsl/linker: link-error using the same name in unnamed block and outside
According with OpenGL GLSL 4.20 spec, section 4.3.9, page 57:
"It is a link-time error if any particular shader interface
contains:
- two different blocks, each having no instance name, and each
having a member of the same name, or
- a variable outside a block, and a block with no instance name,
where the variable has the same name as a member in the block."
This means that it is a link error if for example we have a vertex
shader with the following definition.
"layout(location=0) uniform Data { float a; float b; };"
and a fragment shader with:
"uniform float a;"
As in both cases we refer to both uniforms as "a", and thus using
glGetUniformLocation() wouldn't know which one we mean.
This fixes KHR-GL*.shaders.uniform_block.common.name_matching.
v2: add fixed tests (Tapani)
Reviewed-by: Tapani Pälli
---
src/compiler/glsl/linker.cpp | 23 +++
1 file changed, 23 insertions(+)
diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index 86ef5831b7..39fc3459d3 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -,6 +,29 @@ cross_validate_globals(struct gl_shader_program *prog,
return;
}
+ /* In OpenGL GLSL 4.20 spec, section 4.3.9, page 57:
+ *
+ * "It is a link-time error if any particular shader interface
+ *contains:
+ *
+ *- two different blocks, each having no instance name, and each
+ * having a member of the same name, or
+ *
+ *- a variable outside a block, and a block with no instance name,
+ * where the variable has the same name as a member in the
block."
+ */
+ if (var->data.mode == existing->data.mode &&
+ var->get_interface_type() != existing->get_interface_type()) {
+linker_error(prog, "declarations for %s `%s` are in "
+ "%s and %s\n",
+ mode_string(var), var->name,
+ existing->get_interface_type() ?
+ existing->get_interface_type()->name : "outside a
block",
+ var->get_interface_type() ?
+ var->get_interface_type()->name : "outside a
block");
+
+return;
+ }
/* Only in GLSL ES 3.10, the precision qualifier should not match
* between block members defined in matched block names within a
* shader interface.
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Mesa (master): glx: fix non-dri build
Module: Mesa
Branch: master
Commit: 47ac11bcf8bd9e4525e0fb4308d0bca87a8900c6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=47ac11bcf8bd9e4525e0fb4308d0bca87a8900c6
Author: Samuel Thibault
Date: Mon Jan 15 15:38:25 2018 +0100
glx: fix non-dri build
glXGetDriverConfig parameters do not provide a context to dynamically
check for the presence of the function, so the dispatcher directly calls
glXGetDriverConfig, but in non-dri builds dri_glx.c didn't provide
glXGetDriverConfig.
This change make it just return NULL in that case.
Fixes: 84f764a7591 "glxglvnddispatch: Add missing dispatch for GetDriverConfig
Reviewed-by: Nicolai Hähnle
Reviewed-by: Hans de Goede
Reviewed-by: Emil Velikov
---
src/glx/g_glxglvnddispatchfuncs.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/glx/g_glxglvnddispatchfuncs.c
b/src/glx/g_glxglvnddispatchfuncs.c
index 56d894eda7..5b65afc860 100644
--- a/src/glx/g_glxglvnddispatchfuncs.c
+++ b/src/glx/g_glxglvnddispatchfuncs.c
@@ -338,11 +338,15 @@ static Display *dispatch_GetCurrentDisplayEXT(void)
static const char *dispatch_GetDriverConfig(const char *driverName)
{
+#if defined(GLX_DIRECT_RENDERING) && !defined(GLX_USE_APPLEGL)
/*
* The options are constant for a given driverName, so we do not need
* a context (and apps expect to be able to call this without one).
*/
return glXGetDriverConfig(driverName);
+#else
+return NULL;
+#endif
}
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Mesa (17.3): 36 new commits
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2416223f1d7b6d23a3f4f6df4f9726bd12eab200
Author: Florian Will
Date: Fri Jan 5 15:33:31 2018 +0100
glsl: Respect std430 layout in lower_buffer_access
Respect the std430 rules for determining offset and size of struct
members when using a std430 buffer. std140 rules lead to wrong buffer
offsets in that case.
Fixes my test case attached in Bugzilla. No piglit changes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104492
Reviewed-by: Timothy Arceri
(cherry picked from commit 7e025def6d7d3d6bf94facd6ec6d956f40cbb31e)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a7ffd93c28e4e36fa02d4d707f55815c2e8c074
Author: Józef Kucia
Date: Sun Dec 31 10:19:15 2017 +0100
radeonsi: fix alpha-to-coverage if color writes are disabled
If alpha-to-coverage is enabled, we have to compute alpha
even if color writes are disabled.
Signed-off-by: Józef Kucia
Signed-off-by: Marek Olšák
(cherry picked from commit f222cf3c6d6fc5d9dee3742d20aa77cfff9c39f8)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9be5e0cf7cea644916ad81f74288d4a1d86ae55d
Author: Thomas Hellstrom
Date: Thu Jan 11 10:19:23 2018 +0100
loader/dri3: Avoid freeing renderbuffers in use
Upon reception of an event that lowered the number of active back buffers,
the code would immediately try to free all back buffers with an id equal to
or
higher than the new number of active back buffers.
However, that could lead to an active or to-be-active back buffer being
freed,
since the old number of back buffers was used when obtaining an idle back
buffer for use.
This lead to crashes when lowering the number of active back buffers by
transitioning from page-flipping to non-page-flipping presents.
Fix this by computing the number of active back buffers only when trying to
obtain a new back buffer.
Fixes: 15e208c4cc ("loader/dri3: Don't accidently free buffer holding new
back content")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104214
Cc: "17.3"
Tested-by: Andriy.Khulap
Tested-by: Vadym Shovkoplias
Reviewed-by: Michel Dänzer
Signed-off-by: Thomas Hellstrom
(cherry picked from commit 897c54d522ab960a879b763a15e489f630c491ee)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d774fe8ef94799b1b036d1b5cbf4f4f80964aa11
Author: Andres Gomez
Date: Wed Jan 10 23:11:51 2018 +0200
anv: Import mako templates only during execution of anv_extensions
anv_extensions usage from anv_icd was bringing the unwanted dependency
of mako templates for the latter. We don't want that since it will
force the dependency even for distributable tarballs which was not
needed until now.
Jason suggested this approach.
v2: Patch simplification (Jason).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104551
Fixes: 0ab04ba979b ("anv: Use python to generate ICD json files")
Cc: Jason Ekstrand
Cc: Emil Velikov
Signed-off-by: Andres Gomez
Reviewed-by: Jason Ekstrand
(cherry picked from commit a1901d092c053485cdfff0a65a83f9f0987ffc62)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc2b5d6163f04d4c5869b1186a64110787c4dd64
Author: Bas Nieuwenhuizen
Date: Wed Jan 10 17:05:10 2018 +0100
ac/nir: Sanitize location_frac for local variables.
If they were promoted from inputs/outputs, they could have a
non-zero value left over, which messed with our store handling.
Fixes: 06f05040eb "radv: Link shaders."
Reviewed-by: Timothy Arceri
(cherry picked from commit 67e09c8b451e1db8bd901279160b982b0df0fa41)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ecf2e33760f9de3ac6d66558f686c5b574db67a2
Author: Bas Nieuwenhuizen
Date: Thu Jan 4 01:45:15 2018 +0100
radv: Invalidate L1 for VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT.
These are just shaders reads, so we need to invalidate L1.
Fixes: 6dbb0eaccc "radv: handle subpass cache flushes"
Reviewed-by: Samuel Pitoiset
(cherry picked from commit f2c9f13ec2fdab99f5aa7f32845ee94dd1942fe9)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3561eabf8793bac5e0a6505a37dcee1f4b6f38ab
Author: Bas Nieuwenhuizen
Date: Tue Jan 2 00:04:14 2018 +0100
ac/nir: Handle loading data from compact arrays.
Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Dave Airlie
(cherry picked from commit c99426ea831f9e38624bbd1d2f0bc54bdfaf2b6b)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5fe6c5fdfbd52cdf6b6b59c2c451fbc38debd15b
Author: Bas Nieuwenhuizen
Date: Tue Jan 2 03:32:14 2018 +0100
radv: Allow writing 0 scissors.
When rasterization is disabled we can have that few.
Fixes: 76603aa90b8 "radv: Drop the default viewport when 0 v
Mesa (master): radeon/uvd: update quantiser matrices only when requested
Module: Mesa
Branch: master
Commit: 38dee62c9a0ced17fb1f25256f9da3b163a16f81
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=38dee62c9a0ced17fb1f25256f9da3b163a16f81
Author: Indrajit Das
Date: Wed Jan 10 15:28:17 2018 +0530
radeon/uvd: update quantiser matrices only when requested
Only upload them when the pointers are valid.
Signed-off-by: Indrajit Das
Reviewed-by: Christian König
---
src/gallium/drivers/radeon/radeon_uvd.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c
b/src/gallium/drivers/radeon/radeon_uvd.c
index b46ee6e3c4..78ced179bb 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -871,12 +871,17 @@ static struct ruvd_mpeg2 get_mpeg2_msg(struct
ruvd_decoder *dec,
for (i = 0; i < 2; ++i)
result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]);
- result.load_intra_quantiser_matrix = 1;
- result.load_nonintra_quantiser_matrix = 1;
-
- for (i = 0; i < 64; ++i) {
- result.intra_quantiser_matrix[i] = pic->intra_matrix[zscan[i]];
- result.nonintra_quantiser_matrix[i] =
pic->non_intra_matrix[zscan[i]];
+ if(pic->intra_matrix) {
+ result.load_intra_quantiser_matrix = 1;
+ for (i = 0; i < 64; ++i) {
+ result.intra_quantiser_matrix[i] =
pic->intra_matrix[zscan[i]];
+ }
+ }
+ if(pic->non_intra_matrix) {
+ result.load_nonintra_quantiser_matrix = 1;
+ for (i = 0; i < 64; ++i) {
+ result.nonintra_quantiser_matrix[i] =
pic->non_intra_matrix[zscan[i]];
+ }
}
result.profile_and_level_indication = 0;
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Mesa (master): st/va: clear pointers for mpeg2 quantiser matrices
Module: Mesa
Branch: master
Commit: 338638a8afc9f330bacc1cdd7e6392a3ea9d828a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=338638a8afc9f330bacc1cdd7e6392a3ea9d828a
Author: Indrajit Das
Date: Wed Jan 10 15:31:37 2018 +0530
st/va: clear pointers for mpeg2 quantiser matrices
This is to fix VA-API issues with GStreamer and MPEG2.
Since gstreamer does not pass quantiser matrices with each frame, invalid
pointers were being passed to the driver. This patch addresses the same.
Signed-off-by: Indrajit Das
Reviewed-by: Christian König
---
src/gallium/state_trackers/va/picture.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/gallium/state_trackers/va/picture.c
b/src/gallium/state_trackers/va/picture.c
index 895157375a..23a4b524d7 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -57,6 +57,11 @@ vlVaBeginPicture(VADriverContextP ctx, VAContextID
context_id, VASurfaceID rende
return VA_STATUS_ERROR_INVALID_CONTEXT;
}
+ if (u_reduce_video_profile(context->templat.profile) ==
PIPE_VIDEO_FORMAT_MPEG12) {
+ context->desc.mpeg12.intra_matrix = NULL;
+ context->desc.mpeg12.non_intra_matrix = NULL;
+ }
+
surf = handle_table_get(drv->htab, render_target);
mtx_unlock(&drv->mutex);
if (!surf || !surf->buffer)
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Mesa (master): radeon/vcn: update quantiser matrices only when requested
Module: Mesa
Branch: master
Commit: f5277e84925b69b0bf01340122684becd45c1f7d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5277e84925b69b0bf01340122684becd45c1f7d
Author: Indrajit Das
Date: Wed Jan 10 15:30:44 2018 +0530
radeon/vcn: update quantiser matrices only when requested
Only update them when the pointers are valid.
Signed-off-by: Indrajit Das
Reviewed-by: Christian König
---
src/gallium/drivers/radeon/radeon_vcn_dec.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 8be95382cc..d51eb6e394 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -498,12 +498,17 @@ static rvcn_dec_message_mpeg2_vld_t get_mpeg2_msg(struct
radeon_decoder *dec,
result.forward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[0]);
result.backward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[1]);
- result.load_intra_quantiser_matrix = 1;
- result.load_nonintra_quantiser_matrix = 1;
-
- for (i = 0; i < 64; ++i) {
- result.intra_quantiser_matrix[i] = pic->intra_matrix[zscan[i]];
- result.nonintra_quantiser_matrix[i] =
pic->non_intra_matrix[zscan[i]];
+ if(pic->intra_matrix) {
+ result.load_intra_quantiser_matrix = 1;
+ for (i = 0; i < 64; ++i) {
+ result.intra_quantiser_matrix[i] =
pic->intra_matrix[zscan[i]];
+ }
+ }
+ if(pic->non_intra_matrix) {
+ result.load_nonintra_quantiser_matrix = 1;
+ for (i = 0; i < 64; ++i) {
+ result.nonintra_quantiser_matrix[i] =
pic->non_intra_matrix[zscan[i]];
+ }
}
result.profile_and_level_indication = 0;
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