Mesa (master): intel/compiler: Silence unused parameter warnings in release builds

[Ian Romanick]

Module: Mesa
Branch: master
Commit: feefb7810e694ab902adda36b9d92bdaf1802178
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=feefb7810e694ab902adda36b9d92bdaf1802178

Author: Ian Romanick 
Date:   Mon Feb 12 10:57:06 2018 -0800

intel/compiler: Silence unused parameter warnings in release builds

Reduces my build from 7005 warnings to 6451 warnings by silencing 554
instances of

In file included from ../../SOURCE/master/src/intel/compiler/brw_disasm.c:28:0:
../../SOURCE/master/src/intel/compiler/brw_inst.h: In function 
‘brw_inst_3src_a1_src0_imm’:
../../SOURCE/master/src/intel/compiler/brw_inst.h:346:57: warning: unused 
parameter ‘devinfo’ [-Wunused-parameter]
 brw_inst_3src_a1_src0_imm(const struct gen_device_info *devinfo,
 ^~~
../../SOURCE/master/src/intel/compiler/brw_inst.h: In function 
‘brw_inst_3src_a1_src2_imm’:
../../SOURCE/master/src/intel/compiler/brw_inst.h:354:57: warning: unused 
parameter ‘devinfo’ [-Wunused-parameter]
 brw_inst_3src_a1_src2_imm(const struct gen_device_info *devinfo,
 ^~~
../../SOURCE/master/src/intel/compiler/brw_inst.h: In function 
‘brw_inst_set_3src_a1_src0_imm’:
../../SOURCE/master/src/intel/compiler/brw_inst.h:362:61: warning: unused 
parameter ‘devinfo’ [-Wunused-parameter]
 brw_inst_set_3src_a1_src0_imm(const struct gen_device_info *devinfo,
 ^~~
../../SOURCE/master/src/intel/compiler/brw_inst.h: In function 
‘brw_inst_set_3src_a1_src2_imm’:
../../SOURCE/master/src/intel/compiler/brw_inst.h:370:61: warning: unused 
parameter ‘devinfo’ [-Wunused-parameter]
 brw_inst_set_3src_a1_src2_imm(const struct gen_device_info *devinfo,
 ^~~
../../SOURCE/master/src/intel/compiler/brw_inst.h: In function 
‘brw_inst_imm_uq’:
../../SOURCE/master/src/intel/compiler/brw_inst.h:703:47: warning: unused 
parameter ‘devinfo’ [-Wunused-parameter]
 brw_inst_imm_uq(const struct gen_device_info *devinfo, const brw_inst *insn)
   ^~~
In file included from ../../SOURCE/master/src/intel/compiler/brw_shader.h:29:0,
 from ../../SOURCE/master/src/intel/compiler/brw_disasm.c:29:
../../SOURCE/master/src/intel/compiler/brw_compiler.h: In function 
‘brw_stage_has_packed_dispatch’:
../../SOURCE/master/src/intel/compiler/brw_compiler.h:1277:61: warning: unused 
parameter ‘devinfo’ [-Wunused-parameter]
 brw_stage_has_packed_dispatch(const struct gen_device_info *devinfo,
 ^~~
../../SOURCE/master/src/intel/compiler/brw_disasm.c: In function ‘src_ia1’:
../../SOURCE/master/src/intel/compiler/brw_disasm.c:849:18: warning: unused 
parameter ‘_reg_file’ [-Wunused-parameter]
 unsigned _reg_file,
  ^

Signed-off-by: Ian Romanick 
Reviewed-by: Samuel Iglesias Gonsálvez 

---

 src/intel/compiler/brw_compiler.h |  2 +-
 src/intel/compiler/brw_inst.h | 11 ++-
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/intel/compiler/brw_compiler.h 
b/src/intel/compiler/brw_compiler.h
index b1086bbcee..fb68a34ab9 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -1274,7 +1274,7 @@ encode_slm_size(unsigned gen, uint32_t bytes)
  * '2^n - 1' for some n.
  */
 static inline bool
-brw_stage_has_packed_dispatch(const struct gen_device_info *devinfo,
+brw_stage_has_packed_dispatch(MAYBE_UNUSED const struct gen_device_info 
*devinfo,
   gl_shader_stage stage,
   const struct brw_stage_prog_data *prog_data)
 {
diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
index 99e637e660..0f5e4ac988 100644
--- a/src/intel/compiler/brw_inst.h
+++ b/src/intel/compiler/brw_inst.h
@@ -343,7 +343,7 @@ REG_TYPE(src2)
  *  @{
  */
 static inline uint16_t
-brw_inst_3src_a1_src0_imm(const struct gen_device_info *devinfo,
+brw_inst_3src_a1_src0_imm(MAYBE_UNUSED const struct gen_device_info *devinfo,
   const brw_inst *insn)
 {
assert(devinfo->gen >= 10);
@@ -351,7 +351,7 @@ brw_inst_3src_a1_src0_imm(const struct gen_device_info 
*devinfo,
 }
 
 static inline uint16_t
-brw_inst_3src_a1_src2_imm(const struct gen_device_info *devinfo,
+brw_inst_3src_a1_src2_imm(MAYBE_UNUSED const struct gen_device_info *devinfo,
   const brw_inst *insn)
 {
assert(devinfo->gen >= 10);
@@ -359,7 +359,7 @@ brw_inst_3src_a1_src2_imm(const struct gen_device_info 
*devinfo,
 }
 
 static inline void
-brw_inst_set_3src_a1_src0_imm(const struct gen_device_info *devinfo,
+brw_inst_set_3src_a1_src0_imm(MAYBE_UNUSED const struct gen_device_info 
*devinfo,
   brw_inst 

Mesa (master): isl: Silence unused parameter warnings in __gen_combine_address implementations

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 50bf1868295ecd5ef5d9673d4f5c1259b9fa2b3f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=50bf1868295ecd5ef5d9673d4f5c1259b9fa2b3f

Author: Ian Romanick 
Date:   Tue Feb 20 18:42:02 2018 -0800

isl: Silence unused parameter warnings in __gen_combine_address implementations

Reduces my build from 1808 warnings to 1772 warnings by silencing 36
instances of things like

../../SOURCE/master/src/intel/isl/isl_emit_depth_stencil.c: In function 
‘__gen_combine_address’:
../../SOURCE/master/src/intel/isl/isl_emit_depth_stencil.c:30:29: warning: 
unused parameter ‘data’ [-Wunused-parameter]
 __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
 ^~~~
../../SOURCE/master/src/intel/isl/isl_emit_depth_stencil.c:30:41: warning: 
unused parameter ‘loc’ [-Wunused-parameter]
 __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
 ^~~

Signed-off-by: Ian Romanick 
Reviewed-by: Samuel Iglesias Gonsálvez 

---

 src/intel/isl/isl_emit_depth_stencil.c | 4 +++-
 src/intel/isl/isl_surface_state.c  | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/intel/isl/isl_emit_depth_stencil.c 
b/src/intel/isl/isl_emit_depth_stencil.c
index 90ce8893e5..51b3f005c0 100644
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -27,7 +27,9 @@
 #define __gen_user_data void
 
 static uint64_t
-__gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
+__gen_combine_address(__attribute__((unused)) void *data,
+  __attribute__((unused)) void *loc, uint64_t addr,
+  uint32_t delta)
 {
return addr + delta;
 }
diff --git a/src/intel/isl/isl_surface_state.c 
b/src/intel/isl/isl_surface_state.c
index c205b3d2c0..1f729f89f4 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -27,7 +27,9 @@
 #define __gen_user_data void
 
 static uint64_t
-__gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
+__gen_combine_address(__attribute__((unused)) void *data,
+  __attribute__((unused)) void *loc, uint64_t addr,
+  uint32_t delta)
 {
return addr + delta;
 }

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Mesa (master): nir: Silence unused parameter warnings in generated nir_constant_expressions code

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 3a944316c44621ad824c812907d9d1e0d3ddda46
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a944316c44621ad824c812907d9d1e0d3ddda46

Author: Ian Romanick 
Date:   Fri Feb 16 17:48:57 2018 -0800

nir: Silence unused parameter warnings in generated nir_constant_expressions 
code

Reduces my build from 2075 warnings to 2023 warnings by silencing 52
instances of things like

src/compiler/nir/nir_constant_expressions.c: In function ‘evaluate_bfi’:
src/compiler/nir/nir_constant_expressions.c:1812:61: warning: unused parameter 
‘bit_size’ [-Wunused-parameter]
 evaluate_bfi(MAYBE_UNUSED unsigned num_components, unsigned bit_size,
 ^~~~

Signed-off-by: Ian Romanick 
Reviewed-by: Samuel Iglesias Gonsálvez 

---

 src/compiler/nir/nir_constant_expressions.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir_constant_expressions.py 
b/src/compiler/nir/nir_constant_expressions.py
index 6571d3b98b..ee92be51db 100644
--- a/src/compiler/nir/nir_constant_expressions.py
+++ b/src/compiler/nir/nir_constant_expressions.py
@@ -389,7 +389,8 @@ struct bool32_vec {
 
 % for name, op in sorted(opcodes.iteritems()):
 static nir_const_value
-evaluate_${name}(MAYBE_UNUSED unsigned num_components, unsigned bit_size,
+evaluate_${name}(MAYBE_UNUSED unsigned num_components,
+ ${"UNUSED" if op_bit_sizes(op) is None else ""} unsigned 
bit_size,
  MAYBE_UNUSED nir_const_value *_src)
 {
nir_const_value _dst_val = { {0, } };

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Mesa (master): mesa: Silence unused parameter warnings from TEXSTORE_PARAMS

[Ian Romanick]

Module: Mesa
Branch: master
Commit: a9eb455e297d227bc4ca423e8470ed897d82b57b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9eb455e297d227bc4ca423e8470ed897d82b57b

Author: Ian Romanick 
Date:   Wed Feb 21 19:23:44 2018 -0800

mesa: Silence unused parameter warnings from TEXSTORE_PARAMS

Reduces my build from 1717 warnings to 1547 warnings by silencing 170
instances of things like

In file included from ../../SOURCE/master/src/mesa/main/texcompress_bptc.h:30:0,
 from ../../SOURCE/master/src/mesa/main/texcompress_bptc.c:31:
../../SOURCE/master/src/mesa/main/texcompress_bptc.c: In function 
‘_mesa_texstore_bptc_rgba_unorm’:
../../SOURCE/master/src/mesa/main/texstore.h:60:14: warning: unused parameter 
‘dstFormat’ [-Wunused-parameter]
  mesa_format dstFormat, \
  ^
../../SOURCE/master/src/mesa/main/texcompress_bptc.c:1276:32: note: in 
expansion of macro ‘TEXSTORE_PARAMS’
 _mesa_texstore_bptc_rgba_unorm(TEXSTORE_PARAMS)
^~~

Signed-off-by: Ian Romanick 
Reviewed-by: Samuel Iglesias Gonsálvez 

---

 src/mesa/main/texcompress_etc.c | 22 +++---
 src/mesa/main/texstore.h| 18 --
 2 files changed, 27 insertions(+), 13 deletions(-)

diff --git a/src/mesa/main/texcompress_etc.c b/src/mesa/main/texcompress_etc.c
index d465010985..faeaae9093 100644
--- a/src/mesa/main/texcompress_etc.c
+++ b/src/mesa/main/texcompress_etc.c
@@ -105,7 +105,7 @@ static const int etc2_modifier_tables_non_opaque[8][4] = {
 #undef UINT8_TYPE
 
 GLboolean
-_mesa_texstore_etc1_rgb8(TEXSTORE_PARAMS)
+_mesa_texstore_etc1_rgb8(UNUSED_TEXSTORE_PARAMS)
 {
/* GL_ETC1_RGB8_OES is only valid in glCompressedTexImage2D */
assert(0);
@@ -1097,7 +1097,7 @@ etc2_unpack_srgb8_punchthrough_alpha1(uint8_t *dst_row,
 /* ETC2 texture formats are valid in glCompressedTexImage2D and
  * glCompressedTexSubImage2D functions */
 GLboolean
-_mesa_texstore_etc2_rgb8(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_rgb8(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
@@ -1105,7 +1105,7 @@ _mesa_texstore_etc2_rgb8(TEXSTORE_PARAMS)
 }
 
 GLboolean
-_mesa_texstore_etc2_srgb8(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_srgb8(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
@@ -1113,7 +1113,7 @@ _mesa_texstore_etc2_srgb8(TEXSTORE_PARAMS)
 }
 
 GLboolean
-_mesa_texstore_etc2_rgba8_eac(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_rgba8_eac(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
@@ -1121,7 +1121,7 @@ _mesa_texstore_etc2_rgba8_eac(TEXSTORE_PARAMS)
 }
 
 GLboolean
-_mesa_texstore_etc2_srgb8_alpha8_eac(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_srgb8_alpha8_eac(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
@@ -1129,7 +1129,7 @@ _mesa_texstore_etc2_srgb8_alpha8_eac(TEXSTORE_PARAMS)
 }
 
 GLboolean
-_mesa_texstore_etc2_r11_eac(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_r11_eac(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
@@ -1137,7 +1137,7 @@ _mesa_texstore_etc2_r11_eac(TEXSTORE_PARAMS)
 }
 
 GLboolean
-_mesa_texstore_etc2_signed_r11_eac(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_signed_r11_eac(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
@@ -1145,7 +1145,7 @@ _mesa_texstore_etc2_signed_r11_eac(TEXSTORE_PARAMS)
 }
 
 GLboolean
-_mesa_texstore_etc2_rg11_eac(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_rg11_eac(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
@@ -1153,7 +1153,7 @@ _mesa_texstore_etc2_rg11_eac(TEXSTORE_PARAMS)
 }
 
 GLboolean
-_mesa_texstore_etc2_signed_rg11_eac(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_signed_rg11_eac(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
@@ -1161,7 +1161,7 @@ _mesa_texstore_etc2_signed_rg11_eac(TEXSTORE_PARAMS)
 }
 
 GLboolean
-_mesa_texstore_etc2_rgb8_punchthrough_alpha1(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_rgb8_punchthrough_alpha1(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
@@ -1169,7 +1169,7 @@ 
_mesa_texstore_etc2_rgb8_punchthrough_alpha1(TEXSTORE_PARAMS)
 }
 
 GLboolean
-_mesa_texstore_etc2_srgb8_punchthrough_alpha1(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_srgb8_punchthrough_alpha1(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
diff --git a/src/mesa/main/texstore.h b/src/mesa/main/texstore.h
index f08dc08edd..b8281c51e2 100644
--- a/src/mesa/main/texstore.h
+++ b/src/mesa/main/texstore.h
@@ -56,8 +56,8 @@
  */
 #define TEXSTORE_PARAMS \
struct gl_context *ctx, GLuint dims, \
-   GLenum baseInternalFormat, \
-   mesa_format dstFormat, \
+MAYBE_UNUSED GLenum baseInternalFormat, \
+MAYBE_UNUSED mesa_format dstFormat, \
 GLint dstRowStride, \
 GLubyte **dstSlices, \
GLint srcWidth, GLint srcHeight, GLint srcDepth, \
@@ -65,6 +65,20 @@
const GLvoid *srcAddr, \
const struct gl_pixelstore_attrib *srcPacking
 
+/* This macro must be kept in sync with TEXSTORE_PARAMS.  It is used in the
+ * few places where none of the parameters are used (i.e., the ETC texstore
+ * functions).
+ */
+#define UNUSED_TEXSTORE_PARAMS   

Mesa (master): i965: Silence warnings about mixing enum and non-enum in conditional

[Ian Romanick]

Module: Mesa
Branch: master
Commit: a55dae6ea2cdf37d0ddd06d5f3b34ac1faf3848c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a55dae6ea2cdf37d0ddd06d5f3b34ac1faf3848c

Author: Ian Romanick 
Date:   Mon Feb 12 11:16:55 2018 -0800

i965: Silence warnings about mixing enum and non-enum in conditional

Reduces my build from 6451 warnings to 6301 warnings by silencing 150
instances of

../../SOURCE/master/src/intel/compiler/brw_inst.h: In function ‘brw_reg_type 
brw_inst_src1_type(const gen_device_info*, const brw_inst*)’:
../../SOURCE/master/src/intel/compiler/brw_inst.h:802:55: warning: enumeral and 
non-enumeral type in conditional expression [-Wextra]
unsigned file = __builtin_strcmp("dst", #reg) == 0 ?   \
~~~^
BRW_GENERAL_REGISTER_FILE :\

brw_inst_##reg##_reg_file(devinfo, inst);  \

../../SOURCE/master/src/intel/compiler/brw_inst.h:811:1: note: in expansion of 
macro ‘REG_TYPE’
 REG_TYPE(src1)
 ^~~~

Signed-off-by: Ian Romanick 
Reviewed-by: Samuel Iglesias Gonsálvez 

---

 src/intel/compiler/brw_inst.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
index 0f5e4ac988..a67225ca6b 100644
--- a/src/intel/compiler/brw_inst.h
+++ b/src/intel/compiler/brw_inst.h
@@ -800,7 +800,7 @@ brw_inst_##reg##_type(const struct gen_device_info 
*devinfo,  \
   const brw_inst *inst)   \
 { \
unsigned file = __builtin_strcmp("dst", #reg) == 0 ?   \
-   BRW_GENERAL_REGISTER_FILE :\
+   (unsigned) BRW_GENERAL_REGISTER_FILE : \
brw_inst_##reg##_reg_file(devinfo, inst);  \
unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst);\
return brw_hw_type_to_reg_type(devinfo, (enum brw_reg_file)file, hw_type); \

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Mesa (master): i965: Silence unused parameter warnings in generated OA code

[Ian Romanick]

Module: Mesa
Branch: master
Commit: ab8f2e30b8ea3565c00a76b546b7ef3b78ab7ff6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ab8f2e30b8ea3565c00a76b546b7ef3b78ab7ff6

Author: Ian Romanick 
Date:   Mon Feb 12 11:26:39 2018 -0800

i965: Silence unused parameter warnings in generated OA code

Reduces my build from 6301 warnings to 2075 warnings by silencing 4226
instances of things like

src/mesa/drivers/dri/i965/i965@sta/brw_oa_hsw.c: In function 
‘hsw__render_basic__gpu_core_clocks__read’:
src/mesa/drivers/dri/i965/i965@sta/brw_oa_hsw.c:41:62: warning: unused 
parameter ‘brw’ [-Wunused-parameter]
 hsw__render_basic__gpu_core_clocks__read(struct brw_context *brw,
  ^~~

Signed-off-by: Ian Romanick 
Reviewed-by: Lionel Landwerlin 
Reviewed-by: Samuel Iglesias Gonsálvez 

---

 src/mesa/drivers/dri/i965/brw_oa.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_oa.py 
b/src/mesa/drivers/dri/i965/brw_oa.py
index 576ea6687f..7931c825f0 100644
--- a/src/mesa/drivers/dri/i965/brw_oa.py
+++ b/src/mesa/drivers/dri/i965/brw_oa.py
@@ -260,7 +260,7 @@ def output_counter_read(set, counter, counter_vars):
 
 c("static " + ret_type)
 read_sym = "{0}__{1}__{2}__read".format(set.get('chipset').lower(), 
set.get('underscore_name'), counter.get('underscore_name'))
-c(read_sym + "(struct brw_context *brw,\n")
+c(read_sym + "(MAYBE_UNUSED struct brw_context *brw,\n")
 c_indent(len(read_sym) + 1)
 c("const struct brw_perf_query_info *query,\n")
 c("uint64_t *accumulator)\n")

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Mesa (master): i965: Silence unused parameter warnings

[Ian Romanick]

Module: Mesa
Branch: master
Commit: c8a03ab453b5a162c1268aa9f45e4aa6bfa24c6f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c8a03ab453b5a162c1268aa9f45e4aa6bfa24c6f

Author: Ian Romanick 
Date:   Mon Feb 12 10:52:49 2018 -0800

i965: Silence unused parameter warnings

Reduces my build from 7119 warnings to 7005 warnings by silencing 114
instances of

In file included from 
../../SOURCE/master/src/mesa/drivers/dri/i965/brw_context.h:46:0,
 from 
../../SOURCE/master/src/mesa/drivers/dri/i965/intel_pixel_read.c:38:
../../SOURCE/master/src/mesa/drivers/dri/i965/brw_bufmgr.h: In function 
‘brw_bo_unmap’:
../../SOURCE/master/src/mesa/drivers/dri/i965/brw_bufmgr.h:258:47: warning: 
unused parameter ‘bo’ [-Wunused-parameter]
 static inline int brw_bo_unmap(struct brw_bo *bo) { return 0; }
   ^~

Signed-off-by: Ian Romanick 
Reviewed-by: Samuel Iglesias Gonsálvez 

---

 src/mesa/drivers/dri/i965/brw_bufmgr.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 0f2badd006..f33b6b5a3b 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -252,7 +252,7 @@ MUST_CHECK void *brw_bo_map(struct brw_context *brw, struct 
brw_bo *bo, unsigned
  * Reduces the refcount on the userspace mapping of the buffer
  * object.
  */
-static inline int brw_bo_unmap(struct brw_bo *bo) { return 0; }
+static inline int brw_bo_unmap(UNUSED struct brw_bo *bo) { return 0; }
 
 /** Write data into an object. */
 int brw_bo_subdata(struct brw_bo *bo, uint64_t offset,

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Mesa (master): i965: Silence unused parameter warnings in blorp

[Ian Romanick]

Module: Mesa
Branch: master
Commit: f726695ccee6c13be7e5fd01226a53c5028dd7b7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f726695ccee6c13be7e5fd01226a53c5028dd7b7

Author: Ian Romanick 
Date:   Fri Feb 16 19:00:21 2018 -0800

i965: Silence unused parameter warnings in blorp

Reduces my build from 2023 warnings to 1960 warnings by silencing 63
instances of things like

In file included from 
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:33:0:
../../SOURCE/master/src/intel/blorp/blorp_genX_exec.h: In function 
‘blorp_emit_cc_viewport’:
../../SOURCE/master/src/intel/blorp/blorp_genX_exec.h:500:51: warning: unused 
parameter ‘params’ [-Wunused-parameter]
const struct blorp_params *params)
   ^~
../../SOURCE/master/src/intel/blorp/blorp_genX_exec.h: In function 
‘blorp_emit_sampler_state’:
../../SOURCE/master/src/intel/blorp/blorp_genX_exec.h:524:53: warning: unused 
parameter ‘params’ [-Wunused-parameter]
  const struct blorp_params *params)
 ^~
In file included from 
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:36:0:
../../SOURCE/master/src/mesa/drivers/dri/i965/gen4_blorp_exec.h: In function 
‘blorp_emit_vs_state’:
../../SOURCE/master/src/mesa/drivers/dri/i965/gen4_blorp_exec.h:50:48: warning: 
unused parameter ‘params’ [-Wunused-parameter]
 const struct blorp_params *params)
^~
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c: In function 
‘blorp_flush_range’:
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:197:39: 
warning: unused parameter ‘batch’ [-Wunused-parameter]
 blorp_flush_range(struct blorp_batch *batch, void *start, size_t size)
   ^
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:197:52: 
warning: unused parameter ‘start’ [-Wunused-parameter]
 blorp_flush_range(struct blorp_batch *batch, void *start, size_t size)
^
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:197:66: 
warning: unused parameter ‘size’ [-Wunused-parameter]
 blorp_flush_range(struct blorp_batch *batch, void *start, size_t size)
  ^~~~

Signed-off-by: Ian Romanick 
Reviewed-by: Samuel Iglesias Gonsálvez 

---

 src/intel/blorp/blorp_genX_exec.h   | 12 +---
 src/mesa/drivers/dri/i965/gen4_blorp_exec.h | 14 ++
 src/mesa/drivers/dri/i965/genX_blorp_exec.c |  6 --
 3 files changed, 15 insertions(+), 17 deletions(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index cc408ca71c..6dd92d236a 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -529,8 +529,7 @@ blorp_emit_vertex_elements(struct blorp_batch *batch,
 
 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
 static uint32_t
-blorp_emit_cc_viewport(struct blorp_batch *batch,
-   const struct blorp_params *params)
+blorp_emit_cc_viewport(struct blorp_batch *batch)
 {
uint32_t cc_vp_offset;
blorp_emit_dynamic(batch, GENX(CC_VIEWPORT), vp, 32, _vp_offset) {
@@ -553,8 +552,7 @@ blorp_emit_cc_viewport(struct blorp_batch *batch,
 }
 
 static uint32_t
-blorp_emit_sampler_state(struct blorp_batch *batch,
- const struct blorp_params *params)
+blorp_emit_sampler_state(struct blorp_batch *batch)
 {
uint32_t offset;
blorp_emit_dynamic(batch, GENX(SAMPLER_STATE), sampler, 32, ) {
@@ -1013,7 +1011,7 @@ blorp_emit_blend_state(struct blorp_batch *batch,
 
 static uint32_t
 blorp_emit_color_calc_state(struct blorp_batch *batch,
-const struct blorp_params *params)
+MAYBE_UNUSED const struct blorp_params *params)
 {
uint32_t offset;
blorp_emit_dynamic(batch, GENX(COLOR_CALC_STATE), cc, 64, ) {
@@ -1204,7 +1202,7 @@ blorp_emit_pipeline(struct blorp_batch *batch,
blorp_emit(batch, GENX(3DSTATE_CONSTANT_PS), ps);
 
if (params->src.enabled)
-  blorp_emit_sampler_state(batch, params);
+  blorp_emit_sampler_state(batch);
 
blorp_emit_3dstate_multisample(batch, params);
 
@@ -1238,7 +1236,7 @@ blorp_emit_pipeline(struct blorp_batch *batch,
blorp_emit_sf_config(batch, params);
blorp_emit_ps_config(batch, params);
 
-   blorp_emit_cc_viewport(batch, params);
+   blorp_emit_cc_viewport(batch);
 }
 
 / This is the end of the pipeline setup code /
diff --git a/src/mesa/drivers/dri/i965/gen4_blorp_exec.h 
b/src/mesa/drivers/dri/i965/gen4_blorp_exec.h
index 7e5199c56e..e59bc9f2c2 100644
--- a/src/mesa/drivers/dri/i965/gen4_blorp_exec.h
+++ b/src/mesa/drivers/dri/i965/gen4_blorp_exec.h
@@ 

Mesa (master): genxml: Silence unused parameter warnings in generated pack code

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 492a472b28b0a73c50a87427585cf95520588d5d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=492a472b28b0a73c50a87427585cf95520588d5d

Author: Ian Romanick 
Date:   Fri Feb 16 19:09:13 2018 -0800

genxml: Silence unused parameter warnings in generated pack code

Reduces my build from 1960 warnings to 1808 warnings by silencing 152
instances of things like

In file included from ../../SOURCE/master/src/intel/genxml/genX_pack.h:32:0,
 from 
../../SOURCE/master/src/intel/isl/isl_emit_depth_stencil.c:36:
src/intel/genxml/gen4_pack.h: In function ‘__gen_uint’:
src/intel/genxml/gen4_pack.h:58:49: warning: unused parameter ‘end’ 
[-Wunused-parameter]
 __gen_uint(uint64_t v, uint32_t start, uint32_t end)
 ^~~
src/intel/genxml/gen4_pack.h: In function ‘__gen_offset’:
src/intel/genxml/gen4_pack.h:94:35: warning: unused parameter ‘start’ 
[-Wunused-parameter]
 __gen_offset(uint64_t v, uint32_t start, uint32_t end)
   ^
src/intel/genxml/gen4_pack.h:94:51: warning: unused parameter ‘end’ 
[-Wunused-parameter]
 __gen_offset(uint64_t v, uint32_t start, uint32_t end)
   ^~~
src/intel/genxml/gen4_pack.h: In function ‘__gen_ufixed’:
src/intel/genxml/gen4_pack.h:133:48: warning: unused parameter ‘end’ 
[-Wunused-parameter]
 __gen_ufixed(float v, uint32_t start, uint32_t end, uint32_t fract_bits)
^~~

Signed-off-by: Ian Romanick 
Reviewed-by: Samuel Iglesias Gonsálvez 

---

 src/intel/genxml/gen_pack_header.py | 14 +++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/src/intel/genxml/gen_pack_header.py 
b/src/intel/genxml/gen_pack_header.py
index e6cea8646f..7dcada86fa 100644
--- a/src/intel/genxml/gen_pack_header.py
+++ b/src/intel/genxml/gen_pack_header.py
@@ -57,6 +57,12 @@ pack_header = """%(license)s
 #ifndef __gen_field_functions
 #define __gen_field_functions
 
+#ifdef NDEBUG
+#define NDEBUG_UNUSED __attribute__((unused))
+#else
+#define NDEBUG_UNUSED
+#endif
+
 union __gen_value {
float f;
uint32_t dw;
@@ -69,7 +75,7 @@ __gen_mbo(uint32_t start, uint32_t end)
 }
 
 static inline uint64_t
-__gen_uint(uint64_t v, uint32_t start, uint32_t end)
+__gen_uint(uint64_t v, uint32_t start, NDEBUG_UNUSED uint32_t end)
 {
__gen_validate_value(v);
 
@@ -105,7 +111,7 @@ __gen_sint(int64_t v, uint32_t start, uint32_t end)
 }
 
 static inline uint64_t
-__gen_offset(uint64_t v, uint32_t start, uint32_t end)
+__gen_offset(uint64_t v, NDEBUG_UNUSED uint32_t start, NDEBUG_UNUSED uint32_t 
end)
 {
__gen_validate_value(v);
 #ifndef NDEBUG
@@ -144,7 +150,7 @@ __gen_sfixed(float v, uint32_t start, uint32_t end, 
uint32_t fract_bits)
 }
 
 static inline uint64_t
-__gen_ufixed(float v, uint32_t start, uint32_t end, uint32_t fract_bits)
+__gen_ufixed(float v, uint32_t start, NDEBUG_UNUSED uint32_t end, uint32_t 
fract_bits)
 {
__gen_validate_value(v);
 
@@ -169,6 +175,8 @@ __gen_ufixed(float v, uint32_t start, uint32_t end, 
uint32_t fract_bits)
 #error #define __gen_combine_address before including this file
 #endif
 
+#undef NDEBUG_UNUSED
+
 #endif
 
 """

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Mesa (master): i965: Silence unused parameter warnings in genX_state_upload

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 1049b57bf262a6afb2e2ab73062376258b33a442
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1049b57bf262a6afb2e2ab73062376258b33a442

Author: Ian Romanick 
Date:   Wed Feb 21 16:16:53 2018 -0800

i965: Silence unused parameter warnings in genX_state_upload

Reduces my build from 1772 warnings to 1717 warnings by silencing 55
instances of things like

../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function 
‘gen4_emit_vertex_buffer_state’:
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:313:41: 
warning: unused parameter ‘end_offset’ [-Wunused-parameter]
unsigned end_offset,
 ^~
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function 
‘gen4_emit_sampler_state_pointers_xs’:
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4689:58: 
warning: unused parameter ‘brw’ [-Wunused-parameter]
 genX(emit_sampler_state_pointers_xs)(struct brw_context *brw,
  ^~~
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4690:62: 
warning: unused parameter ‘stage_state’ [-Wunused-parameter]
  struct brw_stage_state *stage_state)
  ^~~
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function 
‘gen4_upload_default_color’:
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4730:40: 
warning: unused parameter ‘format’ [-Wunused-parameter]
mesa_format format, GLenum base_format,
^~
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function 
‘translate_wrap_mode’:
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4906:41: 
warning: unused parameter ‘brw’ [-Wunused-parameter]
 translate_wrap_mode(struct brw_context *brw, GLenum wrap, bool using_nearest)
 ^~~
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function 
‘gen4_update_sampler_state’:
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4972:37: 
warning: unused parameter ‘batch_offset_for_sampler_state’ [-Wunused-parameter]
uint32_t batch_offset_for_sampler_state)
 ^~

Signed-off-by: Ian Romanick 
Reviewed-by: Samuel Iglesias Gonsálvez 

---

 src/mesa/drivers/dri/i965/genX_state_upload.c | 34 +++
 1 file changed, 14 insertions(+), 20 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index d43f0ed2ad..001589a8df 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -158,7 +158,7 @@ KSP(struct brw_context *brw, uint32_t offset)
 }
 #else
 static uint32_t
-KSP(struct brw_context *brw, uint32_t offset)
+KSP(UNUSED struct brw_context *brw, uint32_t offset)
 {
return offset;
 }
@@ -330,9 +330,9 @@ genX(emit_vertex_buffer_state)(struct brw_context *brw,
unsigned buffer_nr,
struct brw_bo *bo,
unsigned start_offset,
-   unsigned end_offset,
+   MAYBE_UNUSED unsigned end_offset,
unsigned stride,
-   unsigned step_rate)
+   MAYBE_UNUSED unsigned step_rate)
 {
struct GENX(VERTEX_BUFFER_STATE) buf_state = {
   .VertexBufferIndex = buffer_nr,
@@ -4732,8 +4732,8 @@ genX(emit_mi_report_perf_count)(struct brw_context *brw,
  * Emit a 3DSTATE_SAMPLER_STATE_POINTERS_{VS,HS,GS,DS,PS} packet.
  */
 static void
-genX(emit_sampler_state_pointers_xs)(struct brw_context *brw,
- struct brw_stage_state *stage_state)
+genX(emit_sampler_state_pointers_xs)(MAYBE_UNUSED struct brw_context *brw,
+ MAYBE_UNUSED struct brw_stage_state 
*stage_state)
 {
 #if GEN_GEN >= 7
static const uint16_t packet_headers[] = {
@@ -4773,7 +4773,7 @@ has_component(mesa_format format, int i)
 static void
 genX(upload_default_color)(struct brw_context *brw,
const struct gl_sampler_object *sampler,
-   mesa_format format, GLenum base_format,
+   MAYBE_UNUSED mesa_format format, GLenum base_format,
bool is_integer_format, bool is_stencil_sampling,
uint32_t *sdc_offset)
 {
@@ -4949,7 +4949,7 @@ genX(upload_default_color)(struct brw_context *brw,
 }
 
 static uint32_t

Mesa (master): i965: Mark upload buffers with MAP_ASYNC and MAP_PERSISTENT.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: b04cf529f2e7bab6be22410d4be293aa5e650b03
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b04cf529f2e7bab6be22410d4be293aa5e650b03

Author: Kenneth Graunke 
Date:   Mon Feb 26 23:41:33 2018 -0800

i965: Mark upload buffers with MAP_ASYNC and MAP_PERSISTENT.

This should have no practical impact.  For the default uploader, we
don't really care, but for others, we may want to append more data
as the GPU is reading existing data, which means we need async and
persistent flags.

Reviewed-by: Chris Wilson 

---

 src/mesa/drivers/dri/i965/intel_upload.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_upload.c 
b/src/mesa/drivers/dri/i965/intel_upload.c
index 53dff55687..e4297bf22b 100644
--- a/src/mesa/drivers/dri/i965/intel_upload.c
+++ b/src/mesa/drivers/dri/i965/intel_upload.c
@@ -87,7 +87,9 @@ brw_upload_space(struct brw_uploader *upload,
if (!upload->bo) {
   upload->bo = brw_bo_alloc(upload->bufmgr, "streamed data",
 MAX2(upload->default_size, size), 4096);
-  upload->map = brw_bo_map(NULL, upload->bo, MAP_READ | MAP_WRITE);
+  upload->map = brw_bo_map(NULL, upload->bo,
+   MAP_READ | MAP_WRITE |
+   MAP_PERSISTENT | MAP_ASYNC);
}
 
upload->next_offset = offset + size;

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Mesa (master): i965: Generalize intel_upload.c to support multiple uploaders.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: eb99bf8abe367aaf01ccf50347b510d8cfb87688
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb99bf8abe367aaf01ccf50347b510d8cfb87688

Author: Kenneth Graunke 
Date:   Mon Feb 26 23:17:35 2018 -0800

i965: Generalize intel_upload.c to support multiple uploaders.

I'd like to reuse the upload logic for a new program cache, but the
buffers will need to have a different lifetime than the default
uploader, and also some address space restrictions.  So, we can't
use a single uploader for both situations - we'll need two of them.

This creates a public 'uploader' structure, and adjusts the interface
to take an uploader rather than always using brw->upload.  It should
have no functional change at the moment.

Reviewed-by: Chris Wilson 

---

 src/mesa/drivers/dri/i965/brw_context.c  |  2 +
 src/mesa/drivers/dri/i965/brw_context.h  | 14 ++--
 src/mesa/drivers/dri/i965/brw_curbe.c|  4 +-
 src/mesa/drivers/dri/i965/brw_draw_upload.c  | 30 
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 +--
 src/mesa/drivers/dri/i965/gen6_constant_state.c  | 10 +--
 src/mesa/drivers/dri/i965/intel_batchbuffer.c|  2 +-
 src/mesa/drivers/dri/i965/intel_buffer_objects.h | 21 ++---
 src/mesa/drivers/dri/i965/intel_upload.c | 97 
 9 files changed, 101 insertions(+), 91 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 8ab9063d21..fca5c8e307 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1018,6 +1018,8 @@ brwCreateContext(gl_api api,
 
}
 
+   brw_upload_init(>upload, brw->bufmgr, 65536);
+
brw_init_state(brw);
 
intelInitExtensions(ctx);
diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 050b656e3d..d6e3c7807f 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -718,6 +718,14 @@ struct brw_perf_query_info
uint32_t n_b_counter_regs;
 };
 
+struct brw_uploader {
+   struct brw_bufmgr *bufmgr;
+   struct brw_bo *bo;
+   void *map;
+   uint32_t next_offset;
+   unsigned default_size;
+};
+
 /**
  * brw_context is derived from gl_context.
  */
@@ -786,11 +794,7 @@ struct brw_context
 
struct intel_batchbuffer batch;
 
-   struct {
-  struct brw_bo *bo;
-  void *map;
-  uint32_t next_offset;
-   } upload;
+   struct brw_uploader upload;
 
/**
 * Set if rendering has occurred to the drawable's front buffer.
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c 
b/src/mesa/drivers/dri/i965/brw_curbe.c
index c747110e31..e4a2bd9c89 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -214,8 +214,8 @@ brw_upload_constant_buffer(struct brw_context *brw)
   goto emit;
}
 
-   buf = intel_upload_space(brw, bufsz, 64,
->curbe.curbe_bo, >curbe.curbe_offset);
+   buf = brw_upload_space(>upload, bufsz, 64,
+  >curbe.curbe_bo, >curbe.curbe_offset);
 
STATIC_ASSERT(sizeof(gl_constant_value) == sizeof(float));
 
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c 
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 9b81999ea0..c058064403 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -412,10 +412,10 @@ copy_array_to_vbo_array(struct brw_context *brw,
 * to replicate it out.
 */
if (src_stride == 0) {
-  intel_upload_data(brw, element->glarray->Ptr,
-element->glarray->_ElementSize,
-element->glarray->_ElementSize,
-   >bo, >offset);
+  brw_upload_data(>upload, element->glarray->Ptr,
+  element->glarray->_ElementSize,
+  element->glarray->_ElementSize,
+  >bo, >offset);
 
   buffer->stride = 0;
   buffer->size = element->glarray->_ElementSize;
@@ -425,8 +425,8 @@ copy_array_to_vbo_array(struct brw_context *brw,
const unsigned char *src = element->glarray->Ptr + min * src_stride;
int count = max - min + 1;
GLuint size = count * dst_stride;
-   uint8_t *dst = intel_upload_space(brw, size, dst_stride,
- >bo, >offset);
+   uint8_t *dst = brw_upload_space(>upload, size, dst_stride,
+   >bo, >offset);
 
/* The GL 4.5 spec says:
 *  "If any enabled array’s buffer binding is zero when DrawArrays or
@@ -699,15 +699,17 @@ brw_prepare_shader_draw_parameters(struct brw_context 
*brw)
/* For non-indirect draws, upload gl_BaseVertex. */
if ((vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance) &&
brw->draw.draw_params_bo == NULL) {
-  intel_upload_data(brw, >draw.params, sizeof(brw->draw.params), 

Mesa (master): intel: Drop program size pointer from vec4/fs assembly getters.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 9fa95359df54f8de8219731e55d89abe816a43e8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9fa95359df54f8de8219731e55d89abe816a43e8

Author: Kenneth Graunke 
Date:   Mon Feb 26 16:34:55 2018 -0800

intel: Drop program size pointer from vec4/fs assembly getters.

These days, we're just passing a pointer to a prog_data field, which
we already have access to.  We can just use it directly.

(In the past, it was a pointer to a separate value.)

Reviewed-by: Iago Toral Quiroga 

---

 src/intel/compiler/brw_fs.cpp  | 4 ++--
 src/intel/compiler/brw_fs.h| 2 +-
 src/intel/compiler/brw_fs_generator.cpp| 4 ++--
 src/intel/compiler/brw_shader.cpp  | 5 ++---
 src/intel/compiler/brw_vec4.cpp| 5 ++---
 src/intel/compiler/brw_vec4.h  | 3 +--
 src/intel/compiler/brw_vec4_generator.cpp  | 5 ++---
 src/intel/compiler/brw_vec4_gs_visitor.cpp | 9 +++--
 src/intel/compiler/brw_vec4_tcs.cpp| 5 ++---
 9 files changed, 17 insertions(+), 25 deletions(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index b1e1d98f6e..fc4cfbfb0b 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -6958,7 +6958,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void 
*log_data,
   prog_data->reg_blocks_0 = brw_register_blocks(simd16_grf_used);
}
 
-   return g.get_assembly(_data->base.program_size);
+   return g.get_assembly();
 }
 
 fs_reg *
@@ -7181,7 +7181,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void 
*log_data,
 
   g.generate_code(cfg, prog_data->simd_size);
 
-  ret = g.get_assembly(_data->base.program_size);
+  ret = g.get_assembly();
}
 
delete v8;
diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index 38e9991df7..b0799a0f5e 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -395,7 +395,7 @@ public:
 
void enable_debug(const char *shader_name);
int generate_code(const cfg_t *cfg, int dispatch_width);
-   const unsigned *get_assembly(unsigned int *assembly_size);
+   const unsigned *get_assembly();
 
 private:
void fire_fb_write(fs_inst *inst,
diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index 60944a97d4..df34099713 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -2318,7 +2318,7 @@ fs_generator::generate_code(const cfg_t *cfg, int 
dispatch_width)
 }
 
 const unsigned *
-fs_generator::get_assembly(unsigned int *assembly_size)
+fs_generator::get_assembly()
 {
-   return brw_get_program(p, assembly_size);
+   return brw_get_program(p, _data->program_size);
 }
diff --git a/src/intel/compiler/brw_shader.cpp 
b/src/intel/compiler/brw_shader.cpp
index 0e713819d9..abfad4e54c 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -1270,7 +1270,7 @@ brw_compile_tes(const struct brw_compiler *compiler,
 
   g.generate_code(v.cfg, 8);
 
-  assembly = g.get_assembly(_data->base.base.program_size);
+  assembly = g.get_assembly();
} else {
   brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
  nir, mem_ctx, shader_time_index);
@@ -1284,8 +1284,7 @@ brw_compile_tes(const struct brw_compiler *compiler,
 v.dump_instructions();
 
   assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
-_data->base, v.cfg,
-
_data->base.base.program_size);
+_data->base, v.cfg);
}
 
return assembly;
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 82052b9bad..ac6b997b66 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -2883,7 +2883,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void 
*log_data,
  g.enable_debug(debug_name);
   }
   g.generate_code(v.cfg, 8);
-  assembly = g.get_assembly(_data->base.base.program_size);
+  assembly = g.get_assembly();
}
 
if (!assembly) {
@@ -2899,8 +2899,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void 
*log_data,
   }
 
   assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx,
-shader, _data->base, v.cfg,
-
_data->base.base.program_size);
+shader, _data->base, v.cfg);
}
 
return assembly;
diff --git a/src/intel/compiler/brw_vec4.h b/src/intel/compiler/brw_vec4.h
index 2e93ee2946..39ce51c7dc 100644
--- a/src/intel/compiler/brw_vec4.h
+++ b/src/intel/compiler/brw_vec4.h
@@ -45,8 +45,7 @@ brw_vec4_generate_assembly(const struct brw_compiler 
*compiler,
  

Mesa (master): intel/compiler: Memory fence commit must always be enabled for gen10+

[Francisco Jerez]

Module: Mesa
Branch: master
Commit: 56dc9f9f49638e0769d6bc696ff7f5dafccec9fc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=56dc9f9f49638e0769d6bc696ff7f5dafccec9fc

Author: Anuj Phogat 
Date:   Tue Feb  6 17:09:09 2018 -0800

intel/compiler: Memory fence commit must always be enabled for gen10+

Commit bit in the message descriptor (Bit 13) must be always set
to true in CNL+ for memory fence messages. It also fixes a piglit
GPU hang on cnl+ in simulation environment.
Piglit test: arb_shader_image_load_store-shader-mem-barrier
See HSD ES # 1404612949

Signed-off-by: Anuj Phogat 
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Francisco Jerez 

---

 src/intel/compiler/brw_eu_emit.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 44abede16b..f8102e014e 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -3287,7 +3287,9 @@ brw_memory_fence(struct brw_codegen *p,
  struct brw_reg dst)
 {
const struct gen_device_info *devinfo = p->devinfo;
-   const bool commit_enable = devinfo->gen == 7 && !devinfo->is_haswell;
+   const bool commit_enable =
+  devinfo->gen >= 10 || /* HSD ES # 1404612949 */
+  (devinfo->gen == 7 && !devinfo->is_haswell);
struct brw_inst *insn;
 
brw_push_insn_state(p);

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Mesa (master): intel/fs: Handle surface opcode sample masks via predication.

[Francisco Jerez]

Module: Mesa
Branch: master
Commit: c063e88909e630bb4605037eb0fc072f40f8c2a2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c063e88909e630bb4605037eb0fc072f40f8c2a2

Author: Francisco Jerez 
Date:   Tue Dec 12 12:05:04 2017 -0800

intel/fs: Handle surface opcode sample masks via predication.

The main motivation is to enable HDC surface opcodes on ICL which no
longer allows the sample mask to be provided in a message header, but
this is enabled all the way back to IVB when possible because it
decreases the instruction count of some shaders using HDC messages
significantly, e.g. one of the SynMark2 CSDof compute shaders
decreases instruction count by about 40% due to the removal of header
setup boilerplate which in turn makes a number of send message
payloads more easily CSE-able.  Shader-db results on SKL:

 total instructions in shared programs: 15325319 -> 15314384 (-0.07%)
 instructions in affected programs: 311532 -> 300597 (-3.51%)
 helped: 491
 HURT: 1

Shader-db results on BDW where the optimization needs to be disabled
in some cases due to hardware restrictions:

 total instructions in shared programs: 15604794 -> 15598028 (-0.04%)
 instructions in affected programs: 220863 -> 214097 (-3.06%)
 helped: 351
 HURT: 0

The FPS of SynMark2 CSDof improves by 5.09% ±0.36% (n=10) on my SKL
laptop with this change.  According to Eero this improves performance
of the same test by 9% on BYT and by 7-8% on BXT J4205 and on SKL GT2
desktop.

Reviewed-by: Kenneth Graunke 
Tested-By: Eero Tamminen 

---

 src/intel/compiler/brw_fs.cpp | 43 ++-
 1 file changed, 42 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index c255a3b23b..b1e1d98f6e 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -4460,6 +4460,8 @@ static void
 lower_surface_logical_send(const fs_builder , fs_inst *inst, opcode op,
const fs_reg _mask)
 {
+   const gen_device_info *devinfo = bld.shader->devinfo;
+
/* Get the logical send arguments. */
const fs_reg  = inst->src[0];
const fs_reg  = inst->src[1];
@@ -4470,7 +4472,20 @@ lower_surface_logical_send(const fs_builder , 
fs_inst *inst, opcode op,
/* Calculate the total number of components of the payload. */
const unsigned addr_sz = inst->components_read(0);
const unsigned src_sz = inst->components_read(1);
-   const unsigned header_sz = (sample_mask.file == BAD_FILE ? 0 : 1);
+   /* From the BDW PRM Volume 7, page 147:
+*
+*  "For the Data Cache Data Port*, the header must be present for the
+*   following message types: [...] Typed read/write/atomics"
+*
+* Earlier generations have a similar wording.  Because of this restriction
+* we don't attempt to implement sample masks via predication for such
+* messages prior to Gen9, since we have to provide a header anyway.  On
+* Gen11+ the header has been removed so we can only use predication.
+*/
+   const unsigned header_sz = devinfo->gen < 9 &&
+  (op == SHADER_OPCODE_TYPED_SURFACE_READ ||
+   op == SHADER_OPCODE_TYPED_SURFACE_WRITE ||
+   op == SHADER_OPCODE_TYPED_ATOMIC) ? 1 : 0;
const unsigned sz = header_sz + addr_sz + src_sz;
 
/* Allocate space for the payload. */
@@ -4490,6 +4505,32 @@ lower_surface_logical_send(const fs_builder , 
fs_inst *inst, opcode op,
 
bld.LOAD_PAYLOAD(payload, components, sz, header_sz);
 
+   /* Predicate the instruction on the sample mask if no header is
+* provided.
+*/
+   if (!header_sz && sample_mask.file != BAD_FILE &&
+   sample_mask.file != IMM) {
+  const fs_builder ubld = bld.group(1, 0).exec_all();
+  if (inst->predicate) {
+ assert(inst->predicate == BRW_PREDICATE_NORMAL);
+ assert(!inst->predicate_inverse);
+ assert(inst->flag_subreg < 2);
+ /* Combine the sample mask with the existing predicate by using a
+  * vertical predication mode.
+  */
+ inst->predicate = BRW_PREDICATE_ALIGN1_ALLV;
+ ubld.MOV(retype(brw_flag_subreg(inst->flag_subreg + 2),
+ sample_mask.type),
+  sample_mask);
+  } else {
+ inst->flag_subreg = 2;
+ inst->predicate = BRW_PREDICATE_NORMAL;
+ inst->predicate_inverse = false;
+ ubld.MOV(retype(brw_flag_subreg(inst->flag_subreg), sample_mask.type),
+  sample_mask);
+  }
+   }
+
/* Update the original instruction. */
inst->opcode = op;
inst->mlen = header_sz + (addr_sz + src_sz) * inst->exec_size / 8;

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Mesa (master): intel/ir: Allow representing additional flag subregisters in the IR.

[Francisco Jerez]

Module: Mesa
Branch: master
Commit: cc0fc8b8ac608b036d260007a689eeeb8e815031
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc0fc8b8ac608b036d260007a689eeeb8e815031

Author: Francisco Jerez 
Date:   Tue Dec 12 12:05:02 2017 -0800

intel/ir: Allow representing additional flag subregisters in the IR.

This allows representing conditional mods and predicates on f1.0-f1.1
at the IR level by adding an extra bit to the flag_subreg
backend_instruction field.

Reviewed-by: Jordan Justen 
Reviewed-by: Kenneth Graunke 

---

 src/intel/compiler/brw_fs.cpp| 12 +++-
 src/intel/compiler/brw_fs_generator.cpp  |  4 ++--
 src/intel/compiler/brw_reg.h |  7 +++
 src/intel/compiler/brw_schedule_instructions.cpp |  2 +-
 src/intel/compiler/brw_shader.h  |  4 ++--
 src/intel/compiler/brw_vec4.cpp  |  7 ---
 src/intel/compiler/brw_vec4_generator.cpp|  2 +-
 7 files changed, 24 insertions(+), 14 deletions(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 0d7988dae4..16b6a06c69 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -5488,9 +5488,10 @@ fs_visitor::dump_instruction(backend_instruction 
*be_inst, FILE *file)
fs_inst *inst = (fs_inst *)be_inst;
 
if (inst->predicate) {
-  fprintf(file, "(%cf0.%d) ",
- inst->predicate_inverse ? '-' : '+',
- inst->flag_subreg);
+  fprintf(file, "(%cf%d.%d) ",
+  inst->predicate_inverse ? '-' : '+',
+  inst->flag_subreg / 2,
+  inst->flag_subreg % 2);
}
 
fprintf(file, "%s", brw_instruction_name(devinfo, inst->opcode));
@@ -5502,7 +5503,8 @@ fs_visitor::dump_instruction(backend_instruction 
*be_inst, FILE *file)
   (devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
 inst->opcode != BRW_OPCODE_IF &&
 inst->opcode != BRW_OPCODE_WHILE))) {
- fprintf(file, ".f0.%d", inst->flag_subreg);
+ fprintf(file, ".f%d.%d", inst->flag_subreg / 2,
+ inst->flag_subreg % 2);
   }
}
fprintf(file, "(%d) ", inst->exec_size);
@@ -5888,7 +5890,7 @@ fs_visitor::calculate_register_pressure()
 bool
 fs_visitor::opt_drop_redundant_mov_to_flags()
 {
-   bool flag_mov_found[2] = {false};
+   bool flag_mov_found[4] = {false};
bool progress = false;
 
/* Instructions removed by this pass can only be added if this were true */
diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index a5a821a13b..557b098c20 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1508,7 +1508,7 @@ 
fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
 void
 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
 {
-   struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
+   struct brw_reg flags = brw_flag_subreg(inst->flag_subreg);
struct brw_reg dispatch_mask;
 
if (devinfo->gen >= 6)
@@ -1764,7 +1764,7 @@ fs_generator::generate_code(const cfg_t *cfg, int 
dispatch_width)
   brw_set_default_access_mode(p, BRW_ALIGN_1);
   brw_set_default_predicate_control(p, inst->predicate);
   brw_set_default_predicate_inverse(p, inst->predicate_inverse);
-  brw_set_default_flag_reg(p, 0, inst->flag_subreg);
+  brw_set_default_flag_reg(p, inst->flag_subreg / 2, inst->flag_subreg % 
2);
   brw_set_default_saturate(p, inst->saturate);
   brw_set_default_mask_control(p, inst->force_writemask_all);
   brw_set_default_acc_write_control(p, inst->writes_accumulator);
diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h
index 17d5b97bf3..c41408104f 100644
--- a/src/intel/compiler/brw_reg.h
+++ b/src/intel/compiler/brw_reg.h
@@ -842,6 +842,13 @@ brw_flag_reg(int reg, int subreg)
   BRW_ARF_FLAG + reg, subreg);
 }
 
+static inline struct brw_reg
+brw_flag_subreg(unsigned subreg)
+{
+   return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
+  BRW_ARF_FLAG + subreg / 2, subreg % 2);
+}
+
 /**
  * Return the mask register present in Gen4-5, or the related register present
  * in Gen7.5 and later hardware referred to as "channel enable" register in
diff --git a/src/intel/compiler/brw_schedule_instructions.cpp 
b/src/intel/compiler/brw_schedule_instructions.cpp
index 692f712532..0e793de4dd 100644
--- a/src/intel/compiler/brw_schedule_instructions.cpp
+++ b/src/intel/compiler/brw_schedule_instructions.cpp
@@ -974,7 +974,7 @@ fs_instruction_scheduler::calculate_deps()
 */
schedule_node *last_grf_write[grf_count * 16];
schedule_node *last_mrf_write[BRW_MAX_MRF(v->devinfo->gen)];
-   schedule_node *last_conditional_mod[4] = {};
+   schedule_node *last_conditional_mod[8] = {};

Mesa (master): intel/ir: Allow arbitrary scratch flag registers for SHADER_OPCODE_FIND_LIVE_CHANNEL.

[Francisco Jerez]

Module: Mesa
Branch: master
Commit: 6edb332b44b2570abac8fea2123050ea0f84e1e6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6edb332b44b2570abac8fea2123050ea0f84e1e6

Author: Francisco Jerez 
Date:   Thu Feb 22 12:49:01 2018 -0800

intel/ir: Allow arbitrary scratch flag registers for 
SHADER_OPCODE_FIND_LIVE_CHANNEL.

This shouldn't cause any functional change at this point, it changes
SHADER_OPCODE_FIND_LIVE_CHANNEL to use the flag register specified at
the IR level instead of the hard-coded f1.0, now that it can be
represented in backend_instruction::flag_subreg.  This will be
necessary for scheduling to behave correctly once more things start
making use of f1.0.

Reviewed-by: Jordan Justen 
Reviewed-by: Kenneth Graunke 

---

 src/intel/compiler/brw_eu_emit.c| 5 +++--
 src/intel/compiler/brw_fs.cpp   | 3 ++-
 src/intel/compiler/brw_fs_builder.h | 2 +-
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index a96fe43556..14b1c592b6 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -3399,7 +3399,9 @@ brw_find_live_channel(struct brw_codegen *p, struct 
brw_reg dst,
   */
  inst = brw_FBL(p, vec1(dst), exec_mask);
   } else {
- const struct brw_reg flag = brw_flag_reg(1, 0);
+ const struct brw_reg flag = brw_flag_reg(
+brw_inst_flag_reg_nr(devinfo, p->current),
+brw_inst_flag_subreg_nr(devinfo, p->current));
 
  brw_set_default_exec_size(p, BRW_EXECUTE_1);
  brw_MOV(p, retype(flag, BRW_REGISTER_TYPE_UD), brw_imm_ud(0));
@@ -3418,7 +3420,6 @@ brw_find_live_channel(struct brw_codegen *p, struct 
brw_reg dst,
 brw_inst_set_mask_control(devinfo, inst, BRW_MASK_ENABLE);
 brw_inst_set_group(devinfo, inst, lower_size * i + 8 * 
qtr_control);
 brw_inst_set_cond_modifier(devinfo, inst, BRW_CONDITIONAL_Z);
-brw_inst_set_flag_reg_nr(devinfo, inst, 1);
 brw_inst_set_exec_size(devinfo, inst, cvt(lower_size) - 1);
  }
 
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 16b6a06c69..c255a3b23b 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -931,7 +931,8 @@ fs_inst::flags_written() const
if ((conditional_mod && (opcode != BRW_OPCODE_SEL &&
 opcode != BRW_OPCODE_IF &&
 opcode != BRW_OPCODE_WHILE)) ||
-   opcode == FS_OPCODE_MOV_DISPATCH_TO_FLAGS) {
+   opcode == FS_OPCODE_MOV_DISPATCH_TO_FLAGS ||
+   opcode == SHADER_OPCODE_FIND_LIVE_CHANNEL) {
   return flag_mask(this);
} else {
   return flag_mask(dst, size_written);
diff --git a/src/intel/compiler/brw_fs_builder.h 
b/src/intel/compiler/brw_fs_builder.h
index 874272b7af..b157e33c39 100644
--- a/src/intel/compiler/brw_fs_builder.h
+++ b/src/intel/compiler/brw_fs_builder.h
@@ -406,7 +406,7 @@ namespace brw {
  const dst_reg chan_index = vgrf(BRW_REGISTER_TYPE_UD);
  const dst_reg dst = vgrf(src.type);
 
- ubld.emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, chan_index);
+ ubld.emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, chan_index)->flag_subreg = 
2;
  ubld.emit(SHADER_OPCODE_BROADCAST, dst, src, component(chan_index, 
0));
 
  return src_reg(component(dst, 0));

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Mesa (master): intel/l3: Don't allocate SLM partition on ICL+.

[Francisco Jerez]

Module: Mesa
Branch: master
Commit: 9ec3362e0ba293f20d08493753edeb29d13baadf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ec3362e0ba293f20d08493753edeb29d13baadf

Author: Francisco Jerez 
Date:   Tue Dec 12 12:05:00 2017 -0800

intel/l3: Don't allocate SLM partition on ICL+.

SLM has a chunk of special-purpose memory separate from L3 on ICL+, we
shouldn't allocate a partition for it on L3 anymore.

Reviewed-by: Jordan Justen 
Reviewed-by: Kenneth Graunke 

---

 src/intel/common/gen_l3_config.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index aff13c06ec..7d58ad8d7c 100644
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -232,7 +232,7 @@ gen_get_default_l3_weights(const struct gen_device_info 
*devinfo,
 {
struct gen_l3_weights w = {{ 0 }};
 
-   w.w[GEN_L3P_SLM] = needs_slm;
+   w.w[GEN_L3P_SLM] = devinfo->gen < 11 && needs_slm;
w.w[GEN_L3P_URB] = 1.0;
 
if (devinfo->gen >= 8) {

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Mesa (master): Revert "i965/fs: Predicate byte scattered writes if needed"

[Francisco Jerez]

Module: Mesa
Branch: master
Commit: 4b4838b1ae46a0ce9fed88f275cc01167302cf24
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4b4838b1ae46a0ce9fed88f275cc01167302cf24

Author: Francisco Jerez 
Date:   Sat Feb 24 16:05:21 2018 -0800

Revert "i965/fs: Predicate byte scattered writes if needed"

This reverts commit a4031bdfa927fb4c3c5d0bdadc70634f3c1a5eac.  It's
redundant with the sample mask predication done at this point by the
common logical send lowering infrastructure, and rather buggy because
it wasn't applying the correct sample mask in shaders using discard,
since the dispatch mask returned by FS_OPCODE_MOV_DISPATCH_TO_FLAGS
doesn't reflect samples discarded by the shader, so it could have led
to data corruption in fragment shader invocations that execute discard
based on a non-dynamically uniform condition.

Reviewed-by: Kenneth Graunke 

---

 src/intel/compiler/brw_fs_nir.cpp | 15 +--
 1 file changed, 1 insertion(+), 14 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index 47247875e8..554d61d71a 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -4207,25 +4207,12 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
nir_intrinsic_instr *instr
  * to rely on byte scattered in order to write 16-bit elements.
  * The byte_scattered_write message needs that every written 16-bit
  * type to be aligned 32-bits (stride=2).
- * Additionally, while on Untyped Surface messages the
- * bits of the execution mask are ANDed with the corresponding
- * bits of the Pixel/Sample Mask, that is not the case for byte
- * scattered writes. That is needed to avoid ssbo stores writing
- * on helper invocations. So when that can affect, we load the
- * sample mask, and predicate the send message.
  */
-brw_predicate pred = BRW_PREDICATE_NONE;
-
-if (stage == MESA_SHADER_FRAGMENT) {
-   bld.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS);
-   pred = BRW_PREDICATE_NORMAL;
-}
-
 emit_byte_scattered_write(bld, surf_index, offset_reg,
   write_src,
   1 /* dims */, 1,
   bit_size,
-  pred);
+  BRW_PREDICATE_NONE);
  } else {
 assert(num_components * type_size <= 16);
 assert((num_components * type_size) % 4 == 0);

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Mesa (master): intel/eu: Plumb header present bit to codegen helpers for HDC messages.

[Francisco Jerez]

Module: Mesa
Branch: master
Commit: e7c9adca5726a8c96de20ae7c5f21a30061db392
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7c9adca5726a8c96de20ae7c5f21a30061db392

Author: Francisco Jerez 
Date:   Tue Dec 12 12:05:03 2017 -0800

intel/eu: Plumb header present bit to codegen helpers for HDC messages.

This makes sure that the header-present bit of the message descriptor
is in sync with the IR instruction fields, which gives the optimizer
more control to avoid the overhead of setting up a message header when
it's possible to do so.

Reviewed-by: Jordan Justen 
Reviewed-by: Kenneth Graunke 

---

 src/intel/compiler/brw_eu.h   | 18 --
 src/intel/compiler/brw_eu_emit.c  | 30 ++
 src/intel/compiler/brw_fs_generator.cpp   | 20 ++--
 src/intel/compiler/brw_vec4_generator.cpp | 11 ++-
 4 files changed, 50 insertions(+), 29 deletions(-)

diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 2d0f56f793..a5f28d8fc6 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -444,7 +444,8 @@ brw_untyped_atomic(struct brw_codegen *p,
struct brw_reg surface,
unsigned atomic_op,
unsigned msg_length,
-   bool response_expected);
+   bool response_expected,
+   bool header_present);
 
 void
 brw_untyped_surface_read(struct brw_codegen *p,
@@ -459,7 +460,8 @@ brw_untyped_surface_write(struct brw_codegen *p,
   struct brw_reg payload,
   struct brw_reg surface,
   unsigned msg_length,
-  unsigned num_channels);
+  unsigned num_channels,
+  bool header_present);
 
 void
 brw_typed_atomic(struct brw_codegen *p,
@@ -468,7 +470,8 @@ brw_typed_atomic(struct brw_codegen *p,
  struct brw_reg surface,
  unsigned atomic_op,
  unsigned msg_length,
- bool response_expected);
+ bool response_expected,
+ bool header_present);
 
 void
 brw_typed_surface_read(struct brw_codegen *p,
@@ -476,14 +479,16 @@ brw_typed_surface_read(struct brw_codegen *p,
struct brw_reg payload,
struct brw_reg surface,
unsigned msg_length,
-   unsigned num_channels);
+   unsigned num_channels,
+   bool header_present);
 
 void
 brw_typed_surface_write(struct brw_codegen *p,
 struct brw_reg payload,
 struct brw_reg surface,
 unsigned msg_length,
-unsigned num_channels);
+unsigned num_channels,
+bool header_present);
 
 void
 brw_byte_scattered_read(struct brw_codegen *p,
@@ -498,7 +503,8 @@ brw_byte_scattered_write(struct brw_codegen *p,
  struct brw_reg payload,
  struct brw_reg surface,
  unsigned msg_length,
- unsigned bit_size);
+ unsigned bit_size,
+ bool header_present);
 
 void
 brw_memory_fence(struct brw_codegen *p,
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 14b1c592b6..44abede16b 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -2883,7 +2883,8 @@ brw_untyped_atomic(struct brw_codegen *p,
struct brw_reg surface,
unsigned atomic_op,
unsigned msg_length,
-   bool response_expected)
+   bool response_expected,
+   bool header_present)
 {
const struct gen_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
@@ -2901,7 +2902,7 @@ brw_untyped_atomic(struct brw_codegen *p,
   p, sfid, brw_writemask(dst, mask), payload, surface, msg_length,
   brw_surface_payload_size(p, response_expected,
devinfo->gen >= 8 || devinfo->is_haswell, true),
-  align1);
+  header_present);
 
brw_set_dp_untyped_atomic_message(
   p, insn, atomic_op, response_expected);
@@ -2984,7 +2985,8 @@ brw_untyped_surface_write(struct brw_codegen *p,
   struct brw_reg payload,
   struct brw_reg surface,
   unsigned msg_length,
-  unsigned num_channels)
+  unsigned num_channels,
+  bool header_present)
 {
const struct gen_device_info *devinfo = p->devinfo;
const unsigned sfid = 

Mesa (master): svga: let svga_update_state_retry() return a bool

[Brian Paul]

Module: Mesa
Branch: master
Commit: 0a7deaa0d6d14fcc21cad08d9acae688ed7c9fcb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a7deaa0d6d14fcc21cad08d9acae688ed7c9fcb

Author: Brian Paul 
Date:   Thu Feb 22 09:32:33 2018 -0700

svga: let svga_update_state_retry() return a bool

This will allow minor simplifications elsewhere.

Reviewed-by: Charmaine Lee 
Reviewed-by: Neha Bhende 

---

 src/gallium/drivers/svga/svga_state.c | 11 ---
 src/gallium/drivers/svga/svga_state.h |  4 +---
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_state.c 
b/src/gallium/drivers/svga/svga_state.c
index 9ca6a18e0f..dad78389a2 100644
--- a/src/gallium/drivers/svga/svga_state.c
+++ b/src/gallium/drivers/svga/svga_state.c
@@ -237,19 +237,24 @@ done:
 }
 
 
-void
+/**
+ * Update state.  If the first attempt fails, flush the command buffer
+ * and retry.
+ * \return  true if success, false if second attempt fails.
+ */
+bool
 svga_update_state_retry(struct svga_context *svga, unsigned max_level)
 {
enum pipe_error ret;
 
ret = svga_update_state( svga, max_level );
 
-   if (ret == PIPE_ERROR_OUT_OF_MEMORY) {
+   if (ret != PIPE_OK) {
   svga_context_flush(svga, NULL);
   ret = svga_update_state( svga, max_level );
}
 
-   assert( ret == PIPE_OK );
+   return ret == PIPE_OK;
 }
 
 
diff --git a/src/gallium/drivers/svga/svga_state.h 
b/src/gallium/drivers/svga/svga_state.h
index 04b20e161f..d75617860e 100644
--- a/src/gallium/drivers/svga/svga_state.h
+++ b/src/gallium/drivers/svga/svga_state.h
@@ -91,9 +91,7 @@ extern struct svga_tracked_state svga_update_swtnl_vdecl;
 enum pipe_error svga_update_state( struct svga_context *svga,
unsigned level );
 
-void svga_update_state_retry( struct svga_context *svga,
-  unsigned level );
-
+bool svga_update_state_retry(struct svga_context *svga, unsigned level);
 
 enum pipe_error svga_emit_initial_state( struct svga_context *svga );
 

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Mesa (master): svga: check svga_have_vgpu10() in svga_delete_blend_state()

[Brian Paul]

Module: Mesa
Branch: master
Commit: b871a77316f301ae0262fb38036e3583c2a464c8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b871a77316f301ae0262fb38036e3583c2a464c8

Author: Brian Paul 
Date:   Thu Feb 22 13:22:11 2018 -0700

svga: check svga_have_vgpu10() in svga_delete_blend_state()

We were calling SVGA3D_vgpu10_DestroyBlendState() when vgpu10 was not
enabled (bs->id==0 by default), resulting in lots of device errors.

Reviewed-by: Neha Bhende

---

 src/gallium/drivers/svga/svga_pipe_blend.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/svga/svga_pipe_blend.c 
b/src/gallium/drivers/svga/svga_pipe_blend.c
index a29fbd3ac2..04855fa7c9 100644
--- a/src/gallium/drivers/svga/svga_pipe_blend.c
+++ b/src/gallium/drivers/svga/svga_pipe_blend.c
@@ -361,7 +361,7 @@ static void svga_delete_blend_state(struct pipe_context 
*pipe,
struct svga_blend_state *bs =
   (struct svga_blend_state *) blend;
 
-   if (bs->id != SVGA3D_INVALID_ID) {
+   if (svga_have_vgpu10(svga) && bs->id != SVGA3D_INVALID_ID) {
   enum pipe_error ret;
 
   ret = SVGA3D_vgpu10_DestroyBlendState(svga->swc, bs->id);

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Mesa (master): svga: fix blending regression

[Brian Paul]

Module: Mesa
Branch: master
Commit: dc79b8840248ccc1860ae740f16f0f5309191445
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc79b8840248ccc1860ae740f16f0f5309191445

Author: Brian Paul 
Date:   Wed Feb 21 21:00:38 2018 -0700

svga: fix blending regression

The earlier Mesa commit 3d06c8afb5 ("st/mesa: don't translate blend
state when it's disabled for a colorbuffer") subtly changed the
details of gallium's per-RT blend state.

In particular, when pipe_rt_blend_state[i].blend_enabled is true,
we have to get the src/dst blend terms from pipe_rt_blend_state[i],
not [0] as before.

We now have to scan the blend targets to find the first one that's
enabled (if any).  We have to use the index of that target for getting
the src/dst blend terms.  And note that we have to set identical blend
terms for all targets.

This fixes the Piglit fbo-drawbuffers2-blend test.  VMware bug 2063493.

Reviewed-by: Charmaine Lee 

---

 src/gallium/drivers/svga/svga_pipe_blend.c | 35 --
 1 file changed, 24 insertions(+), 11 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_pipe_blend.c 
b/src/gallium/drivers/svga/svga_pipe_blend.c
index 04855fa7c9..6bb9d94369 100644
--- a/src/gallium/drivers/svga/svga_pipe_blend.c
+++ b/src/gallium/drivers/svga/svga_pipe_blend.c
@@ -148,6 +148,17 @@ svga_create_blend_state(struct pipe_context *pipe,
if (!blend)
   return NULL;
 
+   /* Find index of first target with blending enabled.  -1 means blending
+* is not enabled at all.
+*/
+   int first_enabled = -1;
+   for (i = 0; i < PIPE_MAX_COLOR_BUFS; i++) {
+  if (templ->rt[i].blend_enable) {
+ first_enabled = i;
+ break;
+  }
+   }
+
/* Fill in the per-rendertarget blend state.  We currently only
 * support independent blend enable and colormask per render target.
 */
@@ -260,24 +271,26 @@ svga_create_blend_state(struct pipe_context *pipe,
  }
   }
   else {
- /* Note: the vgpu10 device does not yet support independent
-  * blend terms per render target.  Target[0] always specifies the
-  * blending terms.
+ /* Note: the vgpu10 device does not yet support independent blend
+  * terms per render target.  When blending is enabled, the blend
+  * terms must match for all targets.
   */
- if (templ->independent_blend_enable || templ->rt[0].blend_enable) {
-/* always use the 0th target's blending terms for now */
+ if (first_enabled >= 0) {
+/* use first enabled target's blending terms */
+const struct pipe_rt_blend_state *rt = >rt[first_enabled];
+
 blend->rt[i].srcblend =
-   svga_translate_blend_factor(svga, templ->rt[0].rgb_src_factor);
+   svga_translate_blend_factor(svga, rt->rgb_src_factor);
 blend->rt[i].dstblend =
-   svga_translate_blend_factor(svga, templ->rt[0].rgb_dst_factor);
+   svga_translate_blend_factor(svga, rt->rgb_dst_factor);
 blend->rt[i].blendeq =
-   svga_translate_blend_func(templ->rt[0].rgb_func);
+   svga_translate_blend_func(rt->rgb_func);
 blend->rt[i].srcblend_alpha =
-   svga_translate_blend_factor(svga, 
templ->rt[0].alpha_src_factor);
+   svga_translate_blend_factor(svga, rt->alpha_src_factor);
 blend->rt[i].dstblend_alpha =
-   svga_translate_blend_factor(svga, 
templ->rt[0].alpha_dst_factor);
+   svga_translate_blend_factor(svga, rt->alpha_dst_factor);
 blend->rt[i].blendeq_alpha =
-   svga_translate_blend_func(templ->rt[0].alpha_func);
+   svga_translate_blend_func(rt->alpha_func);
 
 if (blend->rt[i].srcblend_alpha != blend->rt[i].srcblend ||
 blend->rt[i].dstblend_alpha != blend->rt[i].dstblend ||

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Mesa (master): svga: add SVGA_NEW_PRESCALE to the tracked dirty mask for gs

[Brian Paul]

Module: Mesa
Branch: master
Commit: af8877af3b441947e94599a2af3e0fc50b912611
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=af8877af3b441947e94599a2af3e0fc50b912611

Author: Charmaine Lee 
Date:   Tue Feb 27 04:09:58 2018 -0800

svga: add SVGA_NEW_PRESCALE to the tracked dirty mask for gs

Since geometry shader also consumes prescale constants, the
geometry shader constant buffer will need to be updated when prescale
factor is changed.

Reviewed-by: Brian Paul 

---

 src/gallium/drivers/svga/svga_state_constants.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/svga/svga_state_constants.c 
b/src/gallium/drivers/svga/svga_state_constants.c
index 2a61e8e3d0..2c749c9338 100644
--- a/src/gallium/drivers/svga/svga_state_constants.c
+++ b/src/gallium/drivers/svga/svga_state_constants.c
@@ -810,7 +810,8 @@ emit_gs_consts(struct svga_context *svga, unsigned dirty)
 struct svga_tracked_state svga_hw_gs_constants =
 {
"hw gs params",
-   (SVGA_NEW_GS_CONST_BUFFER |
+   (SVGA_NEW_PRESCALE |
+SVGA_NEW_GS_CONST_BUFFER |
 SVGA_NEW_RAST |
 SVGA_NEW_GS_VARIANT),
emit_gs_consts

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Mesa (master): svga: if svga_update_state() fails, skip the draw call

[Brian Paul]

Module: Mesa
Branch: master
Commit: 72df3a7a3957a13c4a667ffb2295ced7b91e5620
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=72df3a7a3957a13c4a667ffb2295ced7b91e5620

Author: Brian Paul 
Date:   Wed Feb 21 13:57:39 2018 -0700

svga: if svga_update_state() fails, skip the draw call

If svga_update_state() fails, we flush the command buffer and retry.
If it fails again, it likely means we were unable to translate a shader
for some reason (uses too many resources, for example).  In that case,
let's just skip the draw call.  The alternative, just disabling the
shader stage in question, would certainly lead to bad rendering anyway,
and probably device errors.

Fixes failed assertion running Piglit glsl-1.50/execution/
variable-indexing/gs-output-array-vec4-index-wr.shader_test since it
uses too many GS output registers (though the test still fails).
VMware bug 2063492.

v2: also call pipe_debug_message() so apps or apitrace can be notified
when this issue occurs.
v3: use svga_update_state_retry().

Reviewed-by: Charmaine Lee 
Reviewed-by: Neha Bhende 

---

 src/gallium/drivers/svga/svga_pipe_draw.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_pipe_draw.c 
b/src/gallium/drivers/svga/svga_pipe_draw.c
index c73c406e69..ace1d2cb6f 100644
--- a/src/gallium/drivers/svga/svga_pipe_draw.c
+++ b/src/gallium/drivers/svga/svga_pipe_draw.c
@@ -203,11 +203,11 @@ svga_draw_vbo(struct pipe_context *pipe, const struct 
pipe_draw_info *info)
   ret = svga_swtnl_draw_vbo(svga, info, indexbuf, index_offset);
}
else {
-  ret = svga_update_state(svga, SVGA_STATE_HW_DRAW);
-  if (ret != PIPE_OK) {
- svga_context_flush(svga, NULL);
- ret = svga_update_state(svga, SVGA_STATE_HW_DRAW);
- assert(ret == PIPE_OK);
+  if (!svga_update_state_retry(svga, SVGA_STATE_HW_DRAW)) {
+ static const char *msg = "State update failed, skipping draw call";
+ debug_printf("%s\n", msg);
+ pipe_debug_message(>debug.callback, INFO, "%s", msg);
+ goto done;
   }
 
   svga_hwtnl_set_fillmode(svga->hwtnl, svga->curr.rast->hw_fillmode);

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Mesa (master): svga: s/unsigned/boolean/ for a few local vars

[Brian Paul]

Module: Mesa
Branch: master
Commit: 35c5cf895920a24062af73d108d20110c2057305
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=35c5cf895920a24062af73d108d20110c2057305

Author: Brian Paul 
Date:   Thu Feb 22 14:43:41 2018 -0700

svga: s/unsigned/boolean/ for a few local vars

Reviewed-by: Charmaine Lee 

---

 src/gallium/drivers/svga/svga_tgsi_vgpu10.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c 
b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
index 6b8337ccfd..b9b3d4fb3f 100644
--- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
+++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
@@ -856,9 +856,9 @@ emit_dst_register(struct svga_shader_emitter_v10 *emit,
const enum tgsi_semantic sem_name = emit->info.output_semantic_name[index];
const unsigned sem_index = emit->info.output_semantic_index[index];
unsigned writemask = reg->Register.WriteMask;
-   const unsigned indirect = reg->Register.Indirect;
+   const boolean indirect = reg->Register.Indirect;
const unsigned tempArrayId = get_temp_array_id(emit, file, index);
-   const unsigned index2d = reg->Register.Dimension;
+   const boolean index2d = reg->Register.Dimension;
VGPU10OperandToken0 operand0;
 
if (file == TGSI_FILE_OUTPUT) {
@@ -971,15 +971,15 @@ emit_src_register(struct svga_shader_emitter_v10 *emit,
 {
enum tgsi_file_type file = reg->Register.File;
unsigned index = reg->Register.Index;
-   const unsigned indirect = reg->Register.Indirect;
+   const boolean indirect = reg->Register.Indirect;
const unsigned tempArrayId = get_temp_array_id(emit, file, index);
-   const unsigned index2d = reg->Register.Dimension;
+   const boolean index2d = reg->Register.Dimension;
const unsigned swizzleX = reg->Register.SwizzleX;
const unsigned swizzleY = reg->Register.SwizzleY;
const unsigned swizzleZ = reg->Register.SwizzleZ;
const unsigned swizzleW = reg->Register.SwizzleW;
-   const unsigned absolute = reg->Register.Absolute;
-   const unsigned negate = reg->Register.Negate;
+   const boolean absolute = reg->Register.Absolute;
+   const boolean negate = reg->Register.Negate;
bool is_prim_id = FALSE;
 
VGPU10OperandToken0 operand0;

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Mesa (master): meson: install vulkan_intel.h header

[Dylan Baker]

Module: Mesa
Branch: master
Commit: e23192022a2cde122a6ccc70e5495fda009bee12
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e23192022a2cde122a6ccc70e5495fda009bee12

Author: Dylan Baker 
Date:   Fri Mar  2 10:28:11 2018 -0800

meson: install vulkan_intel.h header

Fixes: d1992255bb29054fa51763376d125183a9f602f3
   ("meson: Add build Intel "anv" vulkan driver")
Signed-off-by: Dylan Baker 
Reviewed-by: Emil Velikov 

---

 include/meson.build | 4 
 1 file changed, 4 insertions(+)

diff --git a/include/meson.build b/include/meson.build
index 28ffb33215..b4555eabbf 100644
--- a/include/meson.build
+++ b/include/meson.build
@@ -106,3 +106,7 @@ if with_gallium_opencl and not with_opencl_icd
 subdir: 'CL'
   )
 endif
+
+if with_intel_vk
+  install_headers('vulkan/vulkan_intel.h', subdir : 'vulkan')
+endif

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Mesa (master): st/omx_bellagio: add picture profile and entry point

[Leo Liu]

Module: Mesa
Branch: master
Commit: 1ad89fa138180fff233a92fad3588f13d01df303
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1ad89fa138180fff233a92fad3588f13d01df303

Author: Boyuan Zhang 
Date:   Fri Mar  2 11:11:01 2018 -0500

st/omx_bellagio: add picture profile and entry point

Profile and entry point were missing in the picture structure.
Therefore, add them back.

Signed-off-by: Boyuan Zhang 
Reviewed-by: Leo Liu 
Reviewed-by: Christian König 

---

 src/gallium/state_trackers/omx_bellagio/vid_enc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/state_trackers/omx_bellagio/vid_enc.c 
b/src/gallium/state_trackers/omx_bellagio/vid_enc.c
index 1a4fb62d40..162ec1f65a 100644
--- a/src/gallium/state_trackers/omx_bellagio/vid_enc.c
+++ b/src/gallium/state_trackers/omx_bellagio/vid_enc.c
@@ -1098,6 +1098,8 @@ static void enc_HandleTask(omx_base_PortType *port, 
struct encode_task *task,
 
picture.picture_type = picture_type;
picture.pic_order_cnt = task->pic_order_cnt;
+   picture.base.profile = 
enc_TranslateOMXProfileToPipe(priv->profile_level.eProfile);
+   picture.base.entry_point = PIPE_VIDEO_ENTRYPOINT_ENCODE;
if (priv->restricted_b_frames && picture_type == 
PIPE_H264_ENC_PICTURE_TYPE_B)
   picture.not_referenced = true;
enc_ControlPicture(port, );

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Mesa (master): radeonsi: fix radeon create encoder return

[Leo Liu]

Module: Mesa
Branch: master
Commit: 6a62e455f2a703125127161f4c39b98947e8a0f3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a62e455f2a703125127161f4c39b98947e8a0f3

Author: Boyuan Zhang 
Date:   Tue Feb 27 17:29:44 2018 -0500

radeonsi: fix radeon create encoder return

Previous patch missed a "return" when trying to modify the create encoder
function, which made the whole logic fail. Therefore, add the return back.

Fixes: b38b208ff8886e799d6a2 "radeonsi:create uvd hevc enc entry"

Signed-off-by: Boyuan Zhang 
Reviewed-by: Alex Deucher 
Reviewed-by: Eric Engestrom 

---

 src/gallium/drivers/radeonsi/si_uvd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_uvd.c 
b/src/gallium/drivers/radeonsi/si_uvd.c
index 3906bbdfb8..b6cb4cb69e 100644
--- a/src/gallium/drivers/radeonsi/si_uvd.c
+++ b/src/gallium/drivers/radeonsi/si_uvd.c
@@ -150,7 +150,7 @@ struct pipe_video_codec *si_uvd_create_decoder(struct 
pipe_context *context,
 
if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
if (vcn) {
-   radeon_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);
+   return radeon_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);
} else {
if (u_reduce_video_profile(templ->profile) == 
PIPE_VIDEO_FORMAT_HEVC)
return radeon_uvd_create_encoder(context, 
templ, ctx->b.ws, si_vce_get_buffer);

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Mesa (master): loader: Add support for platform and host1x busses

[Thierry Reding]

Module: Mesa
Branch: master
Commit: f9bc48d41d99f2cd4d603561b35fa5c6aedaf169
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9bc48d41d99f2cd4d603561b35fa5c6aedaf169

Author: Thierry Reding 
Date:   Wed Dec 21 14:15:06 2016 +0100

loader: Add support for platform and host1x busses

ARM SoCs usually have their DRM/KMS devices on the platform bus, so add
support for this bus in order to allow use of the DRI_PRIME environment
variable with those devices.

While at it, also support the host1x bus, which is effectively the same
but uses an additional layer in the bus hierarchy.

Note that it isn't enough to support the bus that has the rendering GPU
because the loader code will also try to construct an ID path tag for a
scanout-only device if it is the default that is being opened.

The ID path tag for a device can be obtained by running udevadm info on
the device node, as shown in this example on NVIDIA Tegra:

$ udevadm info /dev/dri/card0 | grep ID_PATH_TAG
E: ID_PATH_TAG=platform-5000_host1x

The corresponding OF_FULLNAME property, from which the ID_PATH_TAG is
constructed, can be found in the sysfs "uevent" attribute for the card0
device's parent:

$ grep OF_FULLNAME /sys/devices/platform/5000.host1x/drm/uevent
OF_FULLNAME=/host1x@5000

Similarily, /dev/dri/card1 corresponds to the GPU:

$ udevadm info /dev/dri/card1 | grep ID_PATH_TAG
E: ID_PATH_TAG=platform-5700_gpu

and:

$ grep OF_FULLNAME /sys/devices/platform/5700.gpu/uevent
OF_FULLNAME=/gpu@5700

Changes in v2:
- avoid confusing pre-increment in strdup()
- add examples of tags to commit message

Reviewed-by: Eric Engestrom 
Reviewed-by: Emil Velikov 
Signed-off-by: Thierry Reding 

---

 src/loader/loader.c | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/src/loader/loader.c b/src/loader/loader.c
index 92b4c5204b..43275484cc 100644
--- a/src/loader/loader.c
+++ b/src/loader/loader.c
@@ -120,6 +120,33 @@ static char *drm_construct_id_path_tag(drmDevicePtr device)
device->businfo.pci->func) < 0) {
  return NULL;
   }
+   } else if (device->bustype == DRM_BUS_PLATFORM ||
+  device->bustype == DRM_BUS_HOST1X) {
+  char *fullname, *name, *address;
+
+  if (device->bustype == DRM_BUS_PLATFORM)
+ fullname = device->businfo.platform->fullname;
+  else
+ fullname = device->businfo.host1x->fullname;
+
+  name = strrchr(fullname, '/');
+  if (!name)
+ name = strdup(fullname);
+  else
+ name = strdup(name + 1);
+
+  address = strchr(name, '@');
+  if (address) {
+ *address++ = '\0';
+
+ if (asprintf(, "platform-%s_%s", address, name) < 0)
+tag = NULL;
+  } else {
+ if (asprintf(, "platform-%s", name) < 0)
+tag = NULL;
+  }
+
+  free(name);
}
return tag;
 }

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Mesa (master): disk cache: Link with -latomic if necessary

[Thierry Reding]

Module: Mesa
Branch: master
Commit: 498faea103aa7966b435f21d8ff5e36172389b1e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=498faea103aa7966b435f21d8ff5e36172389b1e

Author: Thierry Reding 
Date:   Fri Feb 23 14:13:27 2018 +0100

disk cache: Link with -latomic if necessary

The disk cache implementation uses 64-bit atomic operations. For some
architectures, such as 32-bit ARM, GCC will not be able to translate
these operations into atomic, lock-free instructions and will instead
rely on the external atomics library to provide these operations.

Check at configuration time whether or not linking against libatomic
is necessary and if so, create a dependency that can be used while
linking the mesautil library.

This is the meson equivalent of 2ef7f23820a6 ("configure: check if
-latomic is needed for __atomic_*").

For some background information on this, see:

https://gcc.gnu.org/wiki/Atomic/GCCMM

Changes in v2:
- clarify meaning of lock-free in commit message
- fix build if -latomic is not necessary

Acked-by: Matt Turner 
Reviewed-by: Dylan Baker 
Signed-off-by: Thierry Reding 

---

 meson.build  | 17 +
 src/util/meson.build |  2 +-
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/meson.build b/meson.build
index e9928a3793..bb6a835084 100644
--- a/meson.build
+++ b/meson.build
@@ -790,9 +790,26 @@ else
 endif
 
 # Check for GCC style atomics
+dep_atomic = declare_dependency()
+
 if cc.compiles('int main() { int n; return __atomic_load_n(, 
__ATOMIC_ACQUIRE); }',
name : 'GCC atomic builtins')
   pre_args += '-DUSE_GCC_ATOMIC_BUILTINS'
+
+  # Not all atomic calls can be turned into lock-free instructions, in which
+  # GCC will make calls into the libatomic library. Check whether we need to
+  # link with -latomic.
+  #
+  # This can happen for 64-bit atomic operations on 32-bit architectures such
+  # as ARM.
+  if not cc.links('''#include 
+ int main() {
+   uint64_t n;
+   return (int)__atomic_load_n(, __ATOMIC_ACQUIRE);
+ }''',
+  name : 'GCC atomic builtins required -latomic')
+dep_atomic = cc.find_library('atomic')
+  endif
 endif
 if not cc.links('''#include 
uint64_t v;
diff --git a/src/util/meson.build b/src/util/meson.build
index b23dba3a98..eece1cefef 100644
--- a/src/util/meson.build
+++ b/src/util/meson.build
@@ -102,7 +102,7 @@ libmesa_util = static_library(
   'mesa_util',
   [files_mesa_util, format_srgb],
   include_directories : inc_common,
-  dependencies : [dep_zlib, dep_clock, dep_thread],
+  dependencies : [dep_zlib, dep_clock, dep_thread, dep_atomic],
   c_args : [c_msvc_compat_args, c_vis_args],
   build_by_default : false
 )

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Mesa (master): radv: do not set pending_reset_query in BeginCommandBuffer()

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: c133a3411bbf47c2ba7d9cdae7e35a64fe276068
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c133a3411bbf47c2ba7d9cdae7e35a64fe276068

Author: Samuel Pitoiset 
Date:   Thu Mar  1 10:53:49 2018 +0100

radv: do not set pending_reset_query in BeginCommandBuffer()

This is just useless for two reasons:
1) flush_bits is not set accordingly, so nothing will be flushed
   in BeginQuery().
2) we always flush caches in EndCommandBuffer(), so if a reset
   is done in a previous command buffer we are safe.

Cc: "18.0" 
Signed-off-by: Samuel Pitoiset 
Reviewed-by: Alex Smith 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/amd/vulkan/radv_cmd_buffer.c | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index cfdc531acd..2b41baea3d 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1930,13 +1930,6 @@ VkResult radv_BeginCommandBuffer(
 
cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
 
-   /* Force cache flushes before starting a new query in case the
-* corresponding pool has been resetted from a different command
-* buffer. This is because we have to flush caches between reset and
-* begin if the compute shader path has been used.
-*/
-   cmd_buffer->pending_reset_query = true;
-
return result;
 }
 

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