Mesa (master): intel/genxml: recognize 0x, 0o and 0b when setting default value

[Lionel Landwerlin]

Module: Mesa
Branch: master
Commit: 9d1ff2261ccec49994c8162c20969b693b29639a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d1ff2261ccec49994c8162c20969b693b29639a

Author: Caio Marcelo de Oliveira Filho 
Date:   Wed May  2 14:48:57 2018 -0700

intel/genxml: recognize 0x, 0o and 0b when setting default value

Remove the need of converting values that are documented in
hexadecimal. This patch would allow writing



instead of



Reviewed-by: Lionel Landwerlin 

---

 src/intel/genxml/gen_pack_header.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/intel/genxml/gen_pack_header.py 
b/src/intel/genxml/gen_pack_header.py
index 8989f625d3..6a4c8033a7 100644
--- a/src/intel/genxml/gen_pack_header.py
+++ b/src/intel/genxml/gen_pack_header.py
@@ -241,7 +241,8 @@ class Field(object):
 self.prefix = None
 
 if "default" in attrs:
-self.default = int(attrs["default"])
+# Base 0 recognizes 0x, 0o, 0b prefixes in addition to decimal 
ints.
+self.default = int(attrs["default"], base=0)
 else:
 self.default = None
 

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Mesa (master): mesa: Silence an unused parameter warning

[Ian Romanick]

Module: Mesa
Branch: master
Commit: d350276b037b70b8d63023ad4f1411b8692a4b45
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d350276b037b70b8d63023ad4f1411b8692a4b45

Author: Ian Romanick 
Date:   Mon May 22 15:21:00 2017 -0700

mesa: Silence an unused parameter warning

main/framebuffer.c: In function ‘update_color_draw_buffers’:
main/framebuffer.c:629:46: warning: unused parameter ‘ctx’ [-Wunused-parameter]
 update_color_draw_buffers(struct gl_context *ctx, struct gl_framebuffer *fb)
  ^~~

Signed-off-by: Ian Romanick 
Reviewed-by: Lionel Landwerlin 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/main/framebuffer.c | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
index 4ea18f6858..8e751b453b 100644
--- a/src/mesa/main/framebuffer.c
+++ b/src/mesa/main/framebuffer.c
@@ -549,7 +549,7 @@ _mesa_update_framebuffer_visual(struct gl_context *ctx,
  * writing colors.
  */
 static void
-update_color_draw_buffers(struct gl_context *ctx, struct gl_framebuffer *fb)
+update_color_draw_buffers(struct gl_framebuffer *fb)
 {
GLuint output;
 
@@ -573,9 +573,8 @@ update_color_draw_buffers(struct gl_context *ctx, struct 
gl_framebuffer *fb)
  * Unlike the DrawBuffer, we can only read from one (or zero) color buffers.
  */
 static void
-update_color_read_buffer(struct gl_context *ctx, struct gl_framebuffer *fb)
+update_color_read_buffer(struct gl_framebuffer *fb)
 {
-   (void) ctx;
if (fb->_ColorReadBufferIndex == BUFFER_NONE ||
fb->DeletePending ||
fb->Width == 0 ||
@@ -638,8 +637,8 @@ update_framebuffer(struct gl_context *ctx, struct 
gl_framebuffer *fb)
 * read-state if this FB is bound as ctx->DrawBuffer), but no
 * harm.
 */
-   update_color_draw_buffers(ctx, fb);
-   update_color_read_buffer(ctx, fb);
+   update_color_draw_buffers(fb);
+   update_color_read_buffer(fb);
 
compute_depth_max(fb);
 }

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Mesa (master): mesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV)

[Ian Romanick]

Module: Mesa
Branch: master
Commit: f2db3be6200410ffd269f8789f3c97292ce03b0f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2db3be6200410ffd269f8789f3c97292ce03b0f

Author: Ian Romanick 
Date:   Fri Jun 16 18:48:22 2017 -0700

mesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV)

Found by inspection, so I made a piglit test too.

Signed-off-by: Ian Romanick 
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Kenneth Graunke 

---

 src/mesa/main/fog.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/main/fog.c b/src/mesa/main/fog.c
index c051aadded..0decf762a9 100644
--- a/src/mesa/main/fog.c
+++ b/src/mesa/main/fog.c
@@ -62,6 +62,7 @@ _mesa_Fogiv(GLenum pname, const GLint *params )
   case GL_FOG_END:
   case GL_FOG_INDEX:
   case GL_FOG_COORDINATE_SOURCE_EXT:
+  case GL_FOG_DISTANCE_MODE_NV:
 p[0] = (GLfloat) *params;
 break;
   case GL_FOG_COLOR:

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Mesa (master): i965: Enable NV_fog_distance

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 9d0bf720ed83fc4faf4682131057fc2a0b6e5938
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d0bf720ed83fc4faf4682131057fc2a0b6e5938

Author: Ian Romanick 
Date:   Fri Jun 16 19:15:56 2017 -0700

i965: Enable NV_fog_distance

With the previous fixes in place, it appears to just work.

Signed-off-by: Ian Romanick 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 73a6c73f53..e1e19217bc 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -122,6 +122,7 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.ATI_texture_env_combine3 = true;
ctx->Extensions.MESA_pack_invert = true;
ctx->Extensions.NV_conditional_render = true;
+   ctx->Extensions.NV_fog_distance = true;
ctx->Extensions.NV_primitive_restart = true;
ctx->Extensions.NV_texture_barrier = true;
ctx->Extensions.NV_texture_env_combine4 = true;

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Mesa (master): r200: Enable NV_fog_distance

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 9a10a2fd5fc11ee08e8fa049f59fd129885cd332
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a10a2fd5fc11ee08e8fa049f59fd129885cd332

Author: Ian Romanick 
Date:   Sat Jun 17 18:56:13 2017 -0700

r200: Enable NV_fog_distance

With the previous fixes in place, it appears to just work.

Signed-off-by: Ian Romanick 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/r200/r200_context.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/r200/r200_context.c 
b/src/mesa/drivers/dri/r200/r200_context.c
index 4524f06d10..9417dfc8a7 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -353,6 +353,7 @@ GLboolean r200CreateContext( gl_api api,
ctx->Extensions.EXT_texture_filter_anisotropic = true;
ctx->Extensions.EXT_texture_mirror_clamp = true;
ctx->Extensions.MESA_pack_invert = true;
+   ctx->Extensions.NV_fog_distance = true;
ctx->Extensions.NV_texture_rectangle = true;
ctx->Extensions.OES_EGL_image = true;
 

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Mesa (master): ffvertex: Don't try to read output registers in fog calculation

[Ian Romanick]

Module: Mesa
Branch: master
Commit: df80ffa4aaf18433d8e3e97b7cb86426a1e8654b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=df80ffa4aaf18433d8e3e97b7cb86426a1e8654b

Author: Ian Romanick 
Date:   Fri Jun 16 19:02:48 2017 -0700

ffvertex: Don't try to read output registers in fog calculation

Gallium drivers use _mesa_remove_output_reads() via st_program to lower
output reads away.  It seems better to just generate the right thing in
the first place.

Signed-off-by: Ian Romanick 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/main/ffvertex_prog.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/mesa/main/ffvertex_prog.c b/src/mesa/main/ffvertex_prog.c
index 1c755592bd..dfb494bd8c 100644
--- a/src/mesa/main/ffvertex_prog.c
+++ b/src/mesa/main/ffvertex_prog.c
@@ -1297,12 +1297,14 @@ static void build_fog( struct tnl_program *p )
struct ureg input;
 
switch (p->state->fog_distance_mode) {
-   case FDM_EYE_RADIAL: /* Z = sqrt(Xe*Xe + Ye*Ye + Ze*Ze) */
+   case FDM_EYE_RADIAL: { /* Z = sqrt(Xe*Xe + Ye*Ye + Ze*Ze) */
+  struct ureg tmp = get_temp(p);
   input = get_eye_position(p);
-  emit_op2(p, OPCODE_DP3, fog, WRITEMASK_X, input, input);
-  emit_op1(p, OPCODE_RSQ, fog, WRITEMASK_X, fog);
-  emit_op1(p, OPCODE_RCP, fog, WRITEMASK_X, fog);
+  emit_op2(p, OPCODE_DP3, tmp, WRITEMASK_X, input, input);
+  emit_op1(p, OPCODE_RSQ, tmp, WRITEMASK_X, tmp);
+  emit_op1(p, OPCODE_RCP, fog, WRITEMASK_X, tmp);
   break;
+   }
case FDM_EYE_PLANE: /* Z = Ze */
   input = get_eye_position_z(p);
   emit_op1(p, OPCODE_MOV, fog, WRITEMASK_X, input);

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Mesa: tag mesa-18.1.0-rc3: mesa-18.1.0-rc3

[Dylan Baker]

Module: Mesa
Branch: refs/tags/mesa-18.1.0-rc3
Tag:ced69d14bd27a00be5fe386441b7f46c20abd087
URL:
http://cgit.freedesktop.org/mesa/mesa/tag/?id=ced69d14bd27a00be5fe386441b7f46c20abd087

Tagger: Dylan Baker 
Date:   Fri May  4 11:07:39 2018 -0700

mesa-18.1.0-rc3
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Mesa (18.1): bump version to 18.1.0-rc3

[Dylan Baker]

Module: Mesa
Branch: 18.1
Commit: ea1d5faa96e4a6b05e757aea8b88cc01f34b008f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea1d5faa96e4a6b05e757aea8b88cc01f34b008f

Author: Dylan Baker 
Date:   Fri May  4 10:57:29 2018 -0700

bump version to 18.1.0-rc3

---

 VERSION | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/VERSION b/VERSION
index 4ef6d23b54..5b3a4a1f0b 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-18.1.0-rc2
+18.1.0-rc3

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Mesa (master): mesa/main/readpix: Correct handling of packed floating point values

[Ian Romanick]

Module: Mesa
Branch: master
Commit: e695a35f40b085d524ccc9cc910dd49e1a864485
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e695a35f40b085d524ccc9cc910dd49e1a864485

Author: Gert Wollny 
Date:   Fri Apr 27 18:04:01 2018 +0200

mesa/main/readpix: Correct handling of packed floating point values

Make sure that clamping in the pixel transfer operations is enabled/disabled
for packed floating point values just like it is done for single normal and
half precision floating point values.

This fixes a series of CTS tests with virgl that use r11f_g11f_b10f
buffers as target, and where virglrenderer reads these surfaces back
using the format GL_UNSIGNED_INT_10F_11F_11F_REV.

Signed-off-by: Gert Wollny 
Reviewed-by: Gurchetan Singh 
Reviewed-by: Ian Romanick 

---

 src/mesa/main/readpix.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c
index a4eea3043d..c5fc66988b 100644
--- a/src/mesa/main/readpix.c
+++ b/src/mesa/main/readpix.c
@@ -106,7 +106,8 @@ _mesa_get_readpixels_transfer_ops(const struct gl_context 
*ctx,
   /* For blit-based ReadPixels packing, the clamping is done automatically
* unless the type is float. */
   if (_mesa_get_clamp_read_color(ctx, ctx->ReadBuffer) &&
-  (type == GL_FLOAT || type == GL_HALF_FLOAT)) {
+  (type == GL_FLOAT || type == GL_HALF_FLOAT ||
+   type == GL_UNSIGNED_INT_10F_11F_11F_REV)) {
  transferOps |= IMAGE_CLAMP_BIT;
   }
}
@@ -114,7 +115,8 @@ _mesa_get_readpixels_transfer_ops(const struct gl_context 
*ctx,
   /* For CPU-based ReadPixels packing, the clamping must always be done
* for non-float types, */
   if (_mesa_get_clamp_read_color(ctx, ctx->ReadBuffer) ||
-  (type != GL_FLOAT && type != GL_HALF_FLOAT)) {
+  (type != GL_FLOAT && type != GL_HALF_FLOAT &&
+   type != GL_UNSIGNED_INT_10F_11F_11F_REV)) {
  transferOps |= IMAGE_CLAMP_BIT;
   }
}

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Mesa (master): util/set: add a set_clear function

[Scott D Phillips]

Module: Mesa
Branch: master
Commit: 5c075b085585b1629022d40ce7af9448c7d0e906
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c075b085585b1629022d40ce7af9448c7d0e906

Author: Scott D Phillips 
Date:   Wed May  2 09:01:02 2018 -0700

util/set: add a set_clear function

Clear a set back to the state of having zero entries.

Reviewed-by: Kenneth Graunke 
Reviewed-by: Jason Ekstrand 

---

 src/util/set.c | 23 +++
 src/util/set.h |  3 +++
 2 files changed, 26 insertions(+)

diff --git a/src/util/set.c b/src/util/set.c
index d71f771807..2c9b09319f 100644
--- a/src/util/set.c
+++ b/src/util/set.c
@@ -156,6 +156,29 @@ _mesa_set_destroy(struct set *ht, void 
(*delete_function)(struct set_entry *entr
 }
 
 /**
+ * Clears all values from the given set.
+ *
+ * If delete_function is passed, it gets called on each entry present before
+ * the set is cleared.
+ */
+void
+_mesa_set_clear(struct set *set, void (*delete_function)(struct set_entry 
*entry))
+{
+   struct set_entry *entry;
+
+   if (!set)
+  return;
+
+   set_foreach (set, entry) {
+  if (delete_function)
+ delete_function(entry);
+  entry->key = deleted_key;
+   }
+
+   set->entries = set->deleted_entries = 0;
+}
+
+/**
  * Finds a set entry with the given key and hash of that key.
  *
  * Returns NULL if no entry is found.
diff --git a/src/util/set.h b/src/util/set.h
index 9acd2c28c9..06e79e1586 100644
--- a/src/util/set.h
+++ b/src/util/set.h
@@ -61,6 +61,9 @@ _mesa_set_create(void *mem_ctx,
 void
 _mesa_set_destroy(struct set *set,
   void (*delete_function)(struct set_entry *entry));
+void
+_mesa_set_clear(struct set *set,
+void (*delete_function)(struct set_entry *entry));
 
 struct set_entry *
 _mesa_set_add(struct set *set, const void *key);

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Mesa (18.1): st/omx/enc: fix blit setup for YUV LoadImage

[Dylan Baker]

Module: Mesa
Branch: 18.1
Commit: 7a1f220b26d21390493073713a509ac53a36f896
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a1f220b26d21390493073713a509ac53a36f896

Author: Leo Liu 
Date:   Fri Apr 27 08:32:41 2018 -0400

st/omx/enc: fix blit setup for YUV LoadImage

The blit here involves scaling since it's copying from I8 format to R8G8 format.
Half of source will be filtered out with PIPE_TEX_FILTER_NEAREST instruction, it
looks that GPU always uses the second half as source. Currently we use "1" as
the start point of x for R, then causing 1 source pixel of U component shift to
right. So "-1" should be the start point for U component.

Cc: 18.0 18.1 
Reviewed-by: Marek Olšák 
(cherry picked from commit 1c5f4f4e17f74d823d9e38c678e40e9f49e2c053)

---

 src/gallium/state_trackers/omx/vid_enc_common.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/gallium/state_trackers/omx/vid_enc_common.c 
b/src/gallium/state_trackers/omx/vid_enc_common.c
index 874dd3a1c8..2aa739da22 100644
--- a/src/gallium/state_trackers/omx/vid_enc_common.c
+++ b/src/gallium/state_trackers/omx/vid_enc_common.c
@@ -353,7 +353,7 @@ OMX_ERRORTYPE enc_LoadImage_common(vid_enc_PrivateType * 
priv, OMX_VIDEO_PORTDEF
   blit.src.resource = inp->resource;
   blit.src.format = inp->resource->format;
 
-  blit.src.box.x = 0;
+  blit.src.box.x = -1;
   blit.src.box.y = def->nFrameHeight;
   blit.src.box.width = def->nFrameWidth;
   blit.src.box.height = def->nFrameHeight / 2 ;
@@ -367,11 +367,11 @@ OMX_ERRORTYPE enc_LoadImage_common(vid_enc_PrivateType * 
priv, OMX_VIDEO_PORTDEF
   blit.dst.box.depth = 1;
   blit.filter = PIPE_TEX_FILTER_NEAREST;
 
-  blit.mask = PIPE_MASK_G;
+  blit.mask = PIPE_MASK_R;
   priv->s_pipe->blit(priv->s_pipe, );
 
-  blit.src.box.x = 1;
-  blit.mask = PIPE_MASK_R;
+  blit.src.box.x = 0;
+  blit.mask = PIPE_MASK_G;
   priv->s_pipe->blit(priv->s_pipe, );
   priv->s_pipe->flush(priv->s_pipe, NULL, 0);
 

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Mesa (18.1): radv: compute the number of subpass attachments correctly

[Dylan Baker]

Module: Mesa
Branch: 18.1
Commit: 4cf3a2b06469ecc0815d66a62026bbe3f6889f8f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4cf3a2b06469ecc0815d66a62026bbe3f6889f8f

Author: Samuel Pitoiset 
Date:   Fri Apr 27 10:53:13 2018 +0200

radv: compute the number of subpass attachments correctly

Only count color attachments twice if resolves are used, also
account for the depth stencil attachment if present.

Cc: 18.0 18.1 
Reviewed-by: Bas Nieuwenhuizen 
Signed-off-by: Samuel Pitoiset 
(cherry picked from commit d8db5986cee83078e46895d695d698db87507019)

---

 src/amd/vulkan/radv_pass.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_pass.c b/src/amd/vulkan/radv_pass.c
index d059af54f9..a7d54d7d61 100644
--- a/src/amd/vulkan/radv_pass.c
+++ b/src/amd/vulkan/radv_pass.c
@@ -87,8 +87,8 @@ VkResult radv_CreateRenderPass(
subpass_attachment_count +=
desc->inputAttachmentCount +
desc->colorAttachmentCount +
-   /* Count colorAttachmentCount again for 
resolve_attachments */
-   desc->colorAttachmentCount;
+   (desc->pResolveAttachments ? desc->colorAttachmentCount 
: 0) +
+   (desc->pDepthStencilAttachment != NULL);
}
 
if (subpass_attachment_count) {

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Mesa (18.1): egl/x11: Send invalidate to driver on copy_region path in swap_buffer

[Dylan Baker]

Module: Mesa
Branch: 18.1
Commit: cd1435aa9dfcf4ffac67bde1c0454d671127df64
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd1435aa9dfcf4ffac67bde1c0454d671127df64

Author: Deepak Rawat 
Date:   Tue Apr 24 11:50:59 2018 -0700

egl/x11: Send invalidate to driver on copy_region path in swap_buffer

Similar to swap_available path send invalidate to the driver because
egl/X11 is not watching for for server's invalidate events. The
dri2_copy_region path is trigerred when server supports DRI2 version
minor 1.

Tested with piglit egl tests for regression.

V2: Move invalidate from dri2_copy_region to swap_buffer common.

Cc: 
Signed-off-by: Deepak Rawat 
Signed-off-by: Thomas Hellstrom 
Acked-by: Michel Dänzer 
(cherry picked from commit 9a21c96126d6a13e7b472ec622c517c0d0285ba8)

---

 src/egl/drivers/dri2/platform_x11.c | 23 +--
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_x11.c 
b/src/egl/drivers/dri2/platform_x11.c
index 6c287b4d06..60330b33df 100644
--- a/src/egl/drivers/dri2/platform_x11.c
+++ b/src/egl/drivers/dri2/platform_x11.c
@@ -864,19 +864,22 @@ dri2_x11_swap_buffers_msc(_EGLDriver *drv, _EGLDisplay 
*disp, _EGLSurface *draw,
if (draw->Type == EGL_PIXMAP_BIT || draw->Type == EGL_PBUFFER_BIT)
   return 0;
 
-   if (draw->SwapBehavior == EGL_BUFFER_PRESERVED || !dri2_dpy->swap_available)
-  return dri2_copy_region(drv, disp, draw, dri2_surf->region) ? 0 : -1;
-
-   dri2_flush_drawable_for_swapbuffers(disp, draw);
+   if (draw->SwapBehavior == EGL_BUFFER_PRESERVED || 
!dri2_dpy->swap_available) {
+  swap_count = dri2_copy_region(drv, disp, draw, dri2_surf->region) ? 0 : 
-1;
+   } else {
+  dri2_flush_drawable_for_swapbuffers(disp, draw);
 
-   cookie = xcb_dri2_swap_buffers_unchecked(dri2_dpy->conn, 
dri2_surf->drawable,
-  msc_hi, msc_lo, divisor_hi, divisor_lo, remainder_hi, 
remainder_lo);
+  cookie = xcb_dri2_swap_buffers_unchecked(dri2_dpy->conn,
+   dri2_surf->drawable, msc_hi,
+   msc_lo, divisor_hi, divisor_lo,
+   remainder_hi, remainder_lo);
 
-   reply = xcb_dri2_swap_buffers_reply(dri2_dpy->conn, cookie, NULL);
+  reply = xcb_dri2_swap_buffers_reply(dri2_dpy->conn, cookie, NULL);
 
-   if (reply) {
-  swap_count = (((int64_t)reply->swap_hi) << 32) | reply->swap_lo;
-  free(reply);
+  if (reply) {
+ swap_count = (((int64_t)reply->swap_hi) << 32) | reply->swap_lo;
+ free(reply);
+  }
}
 
/* Since we aren't watching for the server's invalidate events like we're

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Mesa (18.1): radv: Allow vkEnumerateInstanceVersion ProcAddr without instance.

[Dylan Baker]

Module: Mesa
Branch: 18.1
Commit: e334caa4be6f70d887cb99c53b49a0737e3ecdde
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e334caa4be6f70d887cb99c53b49a0737e3ecdde

Author: Bas Nieuwenhuizen 
Date:   Tue May  1 18:02:45 2018 +0200

radv: Allow vkEnumerateInstanceVersion ProcAddr without instance.

Apparently the somewhere between 1.1.70 and 1.1.73 the loader started
depending on this. The loader then creates a 1.0 instance, which gets
into funny situation because we have a 1.1 device.

No idea how to do line wrapping in Mako though, my random guesses
did not work.

CC: 18.1 
Reviewed-by: Jason Ekstrand 
(cherry picked from commit 9267ff9883f749dd1708c573c0df4b46687ff973)

---

 src/amd/vulkan/radv_entrypoints_gen.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_entrypoints_gen.py 
b/src/amd/vulkan/radv_entrypoints_gen.py
index 8eb18e64b6..892491e6c3 100644
--- a/src/amd/vulkan/radv_entrypoints_gen.py
+++ b/src/amd/vulkan/radv_entrypoints_gen.py
@@ -205,7 +205,7 @@ radv_entrypoint_is_enabled(int index, uint32_t core_version,
% if not e.device_command:
   if (device) return false;
% endif
-   % if e.name == 'vkCreateInstance' or e.name == 
'vkEnumerateInstanceExtensionProperties' or e.name == 
'vkEnumerateInstanceLayerProperties':
+   % if e.name == 'vkCreateInstance' or e.name == 
'vkEnumerateInstanceExtensionProperties' or e.name == 
'vkEnumerateInstanceLayerProperties' or e.name == 'vkEnumerateInstanceVersion':
   return !device;
% elif e.core_version:
   return instance && ${e.core_version.c_vk_version()} <= core_version;

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Mesa (18.1): spirv: Apply OriginUpperLeft to FragCoord

[Dylan Baker]

Module: Mesa
Branch: 18.1
Commit: d90d4e61e2310a7a6fdd6cbd82c9f72d5d8e03af
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d90d4e61e2310a7a6fdd6cbd82c9f72d5d8e03af

Author: Neil Roberts 
Date:   Wed May  2 18:10:00 2018 +0200

spirv: Apply OriginUpperLeft to FragCoord

This behaviour was changed in 1e5b09f42f694687ac. The commit message
for that says it is just a “tidy up” so my assumption is that the
behaviour change was a mistake. It’s a little hard to decipher looking
at the diff, but the previous code before that patch was:

  if (builtin == SpvBuiltInFragCoord || builtin == SpvBuiltInSamplePosition)
 nir_var->data.origin_upper_left = b->origin_upper_left;

  if (builtin == SpvBuiltInFragCoord)
 nir_var->data.pixel_center_integer = b->pixel_center_integer;

After the patch the code was:

  case SpvBuiltInSamplePosition:
 nir_var->data.origin_upper_left = b->origin_upper_left;
 /* fallthrough */
  case SpvBuiltInFragCoord:
 nir_var->data.pixel_center_integer = b->pixel_center_integer;
 break;

Before the patch origin_upper_left affected both builtins and
pixel_center_integer only affected FragCoord. After the patch
origin_upper_left only affects SamplePosition and pixel_center_integer
affects both variables.

This patch tries to restore the previous behaviour by changing the
code to:

  case SpvBuiltInFragCoord:
 nir_var->data.pixel_center_integer = b->pixel_center_integer;
 /* fallthrough */
  case SpvBuiltInSamplePosition:
 nir_var->data.origin_upper_left = b->origin_upper_left;
 break;

This change will be important for ARB_gl_spirv which is meant to
support OriginLowerLeft.

Reviewed-by: Jason Ekstrand 
Reviewed-by: Anuj Phogat 
Fixes: 1e5b09f42f694687ac "spirv: Tidy some repeated if checks..."
(cherry picked from commit e17d0ccbbddac455e4c47f5adc2333a531fedd3e)

---

 src/compiler/spirv/vtn_variables.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index 9679ff6526..fd8ab7f247 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1419,11 +1419,11 @@ apply_var_decoration(struct vtn_builder *b, 
nir_variable *nir_var,
   case SpvBuiltInTessLevelInner:
  nir_var->data.compact = true;
  break;
-  case SpvBuiltInSamplePosition:
- nir_var->data.origin_upper_left = b->origin_upper_left;
- /* fallthrough */
   case SpvBuiltInFragCoord:
  nir_var->data.pixel_center_integer = b->pixel_center_integer;
+ /* fallthrough */
+  case SpvBuiltInSamplePosition:
+ nir_var->data.origin_upper_left = b->origin_upper_left;
  break;
   default:
  break;

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Mesa (18.1): anv: Allow lookup of vkEnumerateInstanceVersion without an instance

[Dylan Baker]

Module: Mesa
Branch: 18.1
Commit: c760bbff200c3bc4b64a1c2bdd7db1d067733c58
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c760bbff200c3bc4b64a1c2bdd7db1d067733c58

Author: Jason Ekstrand 
Date:   Tue May  1 09:59:24 2018 -0700

anv: Allow lookup of vkEnumerateInstanceVersion without an instance

Fixes: cbab2d1da5edfe9df27a010adf8b1aa9dbee473b
Reviewed-by: Bas Nieuwenhuizen 
(cherry picked from commit d216ffc604573e514904a05691a47dfe5971e8ca)

---

 src/intel/vulkan/anv_device.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 7522b7865c..f8a3fc560a 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1179,6 +1179,7 @@ PFN_vkVoidFunction anv_GetInstanceProcAddr(
 
LOOKUP_ANV_ENTRYPOINT(EnumerateInstanceExtensionProperties);
LOOKUP_ANV_ENTRYPOINT(EnumerateInstanceLayerProperties);
+   LOOKUP_ANV_ENTRYPOINT(EnumerateInstanceVersion);
LOOKUP_ANV_ENTRYPOINT(CreateInstance);
 
 #undef LOOKUP_ANV_ENTRYPOINT

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Mesa (18.1): i965/tex_image: Avoid the ASTC LDR workaround on gen9lp

[Dylan Baker]

Module: Mesa
Branch: 18.1
Commit: b3f3d605c84747d00562ec2cb4cd2d8cb98482d8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3f3d605c84747d00562ec2cb4cd2d8cb98482d8

Author: Nanley Chery 
Date:   Sat Feb 24 01:26:20 2018 -0800

i965/tex_image: Avoid the ASTC LDR workaround on gen9lp

Both the internal documentation and the results of testing this in the
CI suggest that this is unnecessary. Add the fixes tag because this
reduces an internal benchmark's startup time by about 17 seconds
(reported by Eero).

Fixes: 710b1d2e665 "i965/tex_image: Flush certain subnormal ASTC channel values"
Tested-by: Eero Tamminen 
Acked-by: Kenneth Graunke 
(cherry picked from commit 3e56e4642fb5875b3f5c4eb34798ba9f3d827705)

---

 src/mesa/drivers/dri/i965/intel_tex_image.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c 
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index e25bc9a0c0..a0408b304d 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -927,7 +927,7 @@ intelCompressedTexSubImage(struct gl_context *ctx, GLuint 
dims,
 !_mesa_is_srgb_format(gl_format);
struct brw_context *brw = (struct brw_context*) ctx;
const struct gen_device_info *devinfo = >screen->devinfo;
-   if (devinfo->gen == 9 && is_linear_astc)
+   if (devinfo->gen == 9 && !gen_device_info_is_9lp(devinfo) && is_linear_astc)
   flush_astc_denorms(ctx, dims, texImage,
  xoffset, yoffset, zoffset,
  width, height, depth);

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Mesa (18.1): radv: Don't check the incoming apiVersion on CreateInstance.

[Dylan Baker]

Module: Mesa
Branch: 18.1
Commit: 57aebd4283afa2117103922a907bfd26395e7e64
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=57aebd4283afa2117103922a907bfd26395e7e64

Author: Bas Nieuwenhuizen 
Date:   Tue May  1 22:44:42 2018 +0200

radv: Don't check the incoming apiVersion on CreateInstance.

This fixes

dEQP-VK.api.device_init.create_instance_invalid_api_version

CC: 18.1 
Reviewed-by: Samuel Pitoiset 
(cherry picked from commit 467c562a292b4424f24381932b90bcb9869c3d73)

---

 src/amd/vulkan/radv_device.c | 9 -
 1 file changed, 9 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index d88d5f0642..a3a46332b0 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -463,15 +463,6 @@ VkResult radv_CreateInstance(
client_version = VK_MAKE_VERSION(1, 0, 0);
}
 
-   if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
-   client_version > VK_MAKE_VERSION(1, 1, 0xfff)) {
-   return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
-"Client requested version %d.%d.%d",
-VK_VERSION_MAJOR(client_version),
-VK_VERSION_MINOR(client_version),
-VK_VERSION_PATCH(client_version));
-   }
-
instance = vk_zalloc2(_alloc, pAllocator, sizeof(*instance), 8,
  VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
if (!instance)

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Mesa (18.1): radv/winsys: fix leaking resources from bo's imported by fd

[Dylan Baker]

Module: Mesa
Branch: 18.1
Commit: 2fe5a43995d9901d6fc5d73bfe2b1d70d44601bb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2fe5a43995d9901d6fc5d73bfe2b1d70d44601bb

Author: Andres Rodriguez 
Date:   Mon Apr 30 18:05:49 2018 -0400

radv/winsys: fix leaking resources from bo's imported by fd

A bo's ref_count was not being initialized when imported from an fd.
Therefore, we would fail to free the resource during VkFreeMemory().

This patch fixes applications like hifi VR in threaded mode, which
perform frequent imports/releases of IPC shared memory.

Signed-off-by: Andres Rodriguez 
Reviewed-by: Bas Nieuwenhuizen 
CC: 18.0 18.1 
(cherry picked from commit f56e22e49673e8234a7fe0c241b4c3eae4752f34)

---

 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
index e2060651e4..8ed3e53e2d 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
@@ -501,6 +501,7 @@ radv_amdgpu_winsys_bo_from_fd(struct radeon_winsys *_ws,
bo->size = result.alloc_size;
bo->is_shared = true;
bo->ws = ws;
+   bo->ref_count = 1;
radv_amdgpu_add_buffer_to_global_list(bo);
return (struct radeon_winsys_bo *)bo;
 error_va_map:

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Mesa (18.1): intel/compiler: fix 16-bit int brw_negate_immediate and brw_abs_immediate

[Dylan Baker]

Module: Mesa
Branch: 18.1
Commit: 1e5c3fa29b82633a1818f7f107e2384ab9ab03e2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e5c3fa29b82633a1818f7f107e2384ab9ab03e2

Author: Jose Maria Casanova Crespo 
Date:   Thu May  3 01:44:11 2018 +0200

intel/compiler: fix 16-bit int brw_negate_immediate and brw_abs_immediate

From Intel Skylake PRM, vol 07, "Immediate" section (page 768):

"For a word, unsigned word, or half-float immediate data,
software must replicate the same 16-bit immediate value to both
the lower word and the high word of the 32-bit immediate field
in a GEN instruction."

This fixes the int16/uint16 negate and abs immediates that weren't
taking into account the replication in lower and upper words.

v2: Integer cases are different to Float cases. (Jason Ekstrand)
Included reference to PRM (Jose Maria Casanova)
v3: Make explicit uint32_t casting for left shift (Jason Ekstrand)
Split half float implementation. (Jason Ekstrand)
Fix brw_abs_immediate (Jose Maria Casanova)

Cc: "18.0 18.1" 
Reviewed-by: Jason Ekstrand 
(cherry picked from commit 2a76f03c90037a8966eeb7e47d86c11a6ada9312)

---

 src/intel/compiler/brw_shader.cpp | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/intel/compiler/brw_shader.cpp 
b/src/intel/compiler/brw_shader.cpp
index 9cdf9fcb23..284c2e8233 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -580,9 +580,11 @@ brw_negate_immediate(enum brw_reg_type type, struct 
brw_reg *reg)
   reg->d = -reg->d;
   return true;
case BRW_REGISTER_TYPE_W:
-   case BRW_REGISTER_TYPE_UW:
-  reg->d = -(int16_t)reg->ud;
+   case BRW_REGISTER_TYPE_UW: {
+  uint16_t value = -(int16_t)reg->ud;
+  reg->ud = value | (uint32_t)value << 16;
   return true;
+   }
case BRW_REGISTER_TYPE_F:
   reg->f = -reg->f;
   return true;
@@ -618,9 +620,11 @@ brw_abs_immediate(enum brw_reg_type type, struct brw_reg 
*reg)
case BRW_REGISTER_TYPE_D:
   reg->d = abs(reg->d);
   return true;
-   case BRW_REGISTER_TYPE_W:
-  reg->d = abs((int16_t)reg->ud);
+   case BRW_REGISTER_TYPE_W: {
+  uint16_t value = abs((int16_t)reg->ud);
+  reg->ud = value | (uint32_t)value << 16;
   return true;
+   }
case BRW_REGISTER_TYPE_F:
   reg->f = fabsf(reg->f);
   return true;

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Mesa (18.1): radv: fix multisample image copies

[Dylan Baker]

Module: Mesa
Branch: 18.1
Commit: 63953cc0fbd89598477cadd784bf1931de109658
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=63953cc0fbd89598477cadd784bf1931de109658

Author: Matthew Nicholls 
Date:   Wed May  2 14:03:52 2018 +0200

radv: fix multisample image copies

Previously before fb077b0728, the LOD parameter was being used in place of the
sample index, which would only copy the first sample to all samples in the
destination image. After that multisample image copies wouldn't copy anything
from my observations.

This fixes some copy_and_blit CTS tests.

v3.1: - set lod to 0 for nir_txf_ms (Samuel)
v2: - use GLSL_SAMPLER_DIM_MS instead of 2D (Samuel)
- updated commit description (Samuel)

Fix this properly by copying each sample in a separate radv_CmdDraw and using a
pipeline with the correct rasterizationSamples for the destination image.

Cc: 18.0 18.1 
Reviewed-by: Bas Nieuwenhuizen 
(cherry picked from commit 97d57ef9174111bfe1fa6f85e022af5a3cf2f1ce)

---

 src/amd/vulkan/radv_meta_blit2d.c | 288 +-
 src/amd/vulkan/radv_private.h |  18 +--
 2 files changed, 196 insertions(+), 110 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_blit2d.c 
b/src/amd/vulkan/radv_meta_blit2d.c
index e163056257..4a718c639d 100644
--- a/src/amd/vulkan/radv_meta_blit2d.c
+++ b/src/amd/vulkan/radv_meta_blit2d.c
@@ -100,7 +100,8 @@ blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
 struct radv_meta_blit2d_buffer *src_buf,
 struct blit2d_src_temps *tmp,
 enum blit2d_src_type src_type, VkFormat depth_format,
-VkImageAspectFlagBits aspects)
+VkImageAspectFlagBits aspects,
+uint32_t log2_samples)
 {
struct radv_device *device = cmd_buffer->device;
 
@@ -108,7 +109,7 @@ blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
create_bview(cmd_buffer, src_buf, >bview, depth_format);
 
radv_meta_push_descriptor_set(cmd_buffer, 
VK_PIPELINE_BIND_POINT_GRAPHICS,
- 
device->meta_state.blit2d.p_layouts[src_type],
+ 
device->meta_state.blit2d[log2_samples].p_layouts[src_type],
  0, /* set */
  1, /* descriptorWriteCount */
  (VkWriteDescriptorSet[]) {
@@ -123,7 +124,7 @@ blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
  });
 
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
- 
device->meta_state.blit2d.p_layouts[src_type],
+ 
device->meta_state.blit2d[log2_samples].p_layouts[src_type],
  VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4,
  _buf->pitch);
} else {
@@ -131,12 +132,12 @@ blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
 
if (src_type == BLIT2D_SRC_TYPE_IMAGE_3D)

radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
- 
device->meta_state.blit2d.p_layouts[src_type],
+ 
device->meta_state.blit2d[log2_samples].p_layouts[src_type],
  VK_SHADER_STAGE_FRAGMENT_BIT, 16, 
4,
  _img->layer);
 
radv_meta_push_descriptor_set(cmd_buffer, 
VK_PIPELINE_BIND_POINT_GRAPHICS,
- 
device->meta_state.blit2d.p_layouts[src_type],
+ 
device->meta_state.blit2d[log2_samples].p_layouts[src_type],
  0, /* set */
  1, /* descriptorWriteCount */
  (VkWriteDescriptorSet[]) {
@@ -190,10 +191,11 @@ blit2d_bind_dst(struct radv_cmd_buffer *cmd_buffer,
 
 static void
 bind_pipeline(struct radv_cmd_buffer *cmd_buffer,
-  enum blit2d_src_type src_type, unsigned fs_key)
+  enum blit2d_src_type src_type, unsigned fs_key,
+  uint32_t log2_samples)
 {
VkPipeline pipeline =
-   
cmd_buffer->device->meta_state.blit2d.pipelines[src_type][fs_key];
+   
cmd_buffer->device->meta_state.blit2d[log2_samples].pipelines[src_type][fs_key];
 
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
@@ -201,10 +203,11 @@ bind_pipeline(struct radv_cmd_buffer *cmd_buffer,
 
 static void
 bind_depth_pipeline(struct radv_cmd_buffer *cmd_buffer,
-   enum 

Mesa (18.1): intel/compiler: fix brw_imm_w for negative 16-bit integers

[Dylan Baker]

Module: Mesa
Branch: 18.1
Commit: 0d15a443fae48210ba16e7a3b664619ca5f89519
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d15a443fae48210ba16e7a3b664619ca5f89519

Author: Jose Maria Casanova Crespo 
Date:   Thu May  3 01:38:47 2018 +0200

intel/compiler: fix brw_imm_w for negative 16-bit integers

16-bit immediates need to replicate the 16-bit immediate value
in both words of the 32-bit value. This needs to be careful
to avoid sign-extension, which the previous implementation was
not handling properly.

For example, with the previous implementation, storing the value
-3 would generate imm.d = 0xfffd due to signed integer sign
extension, which is not correct. Instead, we should cast to
uint16_t, which gives us the correct result: imm.ud = 0xfffdfffd.

We only had a couple of cases hitting this path in the driver
until now, one with value -1, which would work since all bits are
one in this case, and another with value -2 in brw_clip_tri(),
which would hit the aforementioned issue (this case only affects
gen4 although we are not aware of whether this was causing an
actual bug somewhere).

v2: Make explicit uint32_t casting for left shift (Jason Ekstrand)

Reviewed-by: Jason Ekstrand 

Cc: "18.0 18.1" 
(cherry picked from commit f0e6dacee529661393964725bed561c45405bae4)

---

 src/intel/compiler/brw_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h
index dff9b970b2..ac12ab3d2d 100644
--- a/src/intel/compiler/brw_reg.h
+++ b/src/intel/compiler/brw_reg.h
@@ -705,7 +705,7 @@ static inline struct brw_reg
 brw_imm_w(int16_t w)
 {
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W);
-   imm.d = w | (w << 16);
+   imm.ud = (uint16_t)w | (uint32_t)(uint16_t)w << 16;
return imm;
 }
 

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Mesa (master): egl: add EGL_BAD_MATCH error case for surfaceless and android

[Tapani Pälli]

Module: Mesa
Branch: master
Commit: affe63b1da25dc7038499b6884523384684d70a8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=affe63b1da25dc7038499b6884523384684d70a8

Author: Tapani Pälli 
Date:   Fri May  4 08:28:50 2018 +0300

egl: add EGL_BAD_MATCH error case for surfaceless and android

Just like is done for other backends when suitable config is not
found (added in fd4eba4929).

Signed-off-by: Tapani Pälli 
Reviewed-by: Juan A. Suarez 

---

 src/egl/drivers/dri2/platform_android.c | 4 +++-
 src/egl/drivers/dri2/platform_surfaceless.c | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index 7f1a496ea2..1d6ed92bd6 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -337,8 +337,10 @@ droid_create_surface(_EGLDriver *drv, _EGLDisplay *disp, 
EGLint type,
 
config = dri2_get_dri_config(dri2_conf, type,
 dri2_surf->base.GLColorspace);
-   if (!config)
+   if (!config) {
+  _eglError(EGL_BAD_MATCH, "Unsupported surfacetype/colorspace 
configuration");
   goto cleanup_surface;
+   }
 
if (dri2_dpy->image_driver)
   createNewDrawable = dri2_dpy->image_driver->createNewDrawable;
diff --git a/src/egl/drivers/dri2/platform_surfaceless.c 
b/src/egl/drivers/dri2/platform_surfaceless.c
index 70b302c0ce..a0348a5e95 100644
--- a/src/egl/drivers/dri2/platform_surfaceless.c
+++ b/src/egl/drivers/dri2/platform_surfaceless.c
@@ -130,8 +130,10 @@ dri2_surfaceless_create_surface(_EGLDriver *drv, 
_EGLDisplay *disp, EGLint type,
config = dri2_get_dri_config(dri2_conf, type,
 dri2_surf->base.GLColorspace);
 
-   if (!config)
+   if (!config) {
+  _eglError(EGL_BAD_MATCH, "Unsupported surfacetype/colorspace 
configuration");
   goto cleanup_surface;
+   }
 
dri2_surf->dri_drawable =
   dri2_dpy->image_driver->createNewDrawable(dri2_dpy->dri_screen, config,

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Mesa (master): amd/common: use llvm.amdgcn.wqm for explicit derivatives

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: c0acb596f45624e2bc9ba7285e20bc744a532dbe
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0acb596f45624e2bc9ba7285e20bc744a532dbe

Author: Nicolai Hähnle 
Date:   Tue May  1 11:06:18 2018 +0200

amd/common: use llvm.amdgcn.wqm for explicit derivatives

To comply with an upcoming change in LLVM, see
https://reviews.llvm.org/D46051

Reviewed-by: Bas Nieuwenhuizen 

---

 src/amd/common/ac_llvm_build.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index f21a5d2623..c9b2e36b63 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -1248,6 +1248,13 @@ ac_build_ddxy(struct ac_llvm_context *ctx,
tl = LLVMBuildBitCast(ctx->builder, tl, ctx->f32, "");
trbl = LLVMBuildBitCast(ctx->builder, trbl, ctx->f32, "");
result = LLVMBuildFSub(ctx->builder, trbl, tl, "");
+
+   if (HAVE_LLVM >= 0x0700) {
+   result = ac_build_intrinsic(ctx,
+   "llvm.amdgcn.wqm.f32", ctx->f32,
+   , 1, 0);
+   }
+
return result;
 }
 

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