Mesa (master): nv50/ir/ra: fix SpillCodeInserter::offsetSlot usage
Module: Mesa
Branch: master
Commit: 1f4bfb8797d2f851f5e113f85bcbff519977fd99
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f4bfb8797d2f851f5e113f85bcbff519977fd99
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Wed Feb 19 04:00:34 2014 +0100
nv50/ir/ra: fix SpillCodeInserter::offsetSlot usage
We were turning non-memory spill slots into NULL.
Cc: 10.1 mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index dd3beb7..1ace9f5 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
@@ -284,7 +284,7 @@ public:
bool run(const std::listValuePair);
Symbol *assignSlot(const Interval, const unsigned int size);
- Symbol *offsetSlot(Symbol *, const LValue *);
+ Value *offsetSlot(Value *, const LValue *);
inline int32_t getStackSize() const { return stackSize; }
private:
@@ -1468,12 +1468,12 @@ SpillCodeInserter::assignSlot(const Interval livei,
const unsigned int size)
return slot.sym;
}
-Symbol *
-SpillCodeInserter::offsetSlot(Symbol *base, const LValue *lval)
+Value *
+SpillCodeInserter::offsetSlot(Value *base, const LValue *lval)
{
- if (!base || !lval-compound || (lval-compMask 0x1))
+ if (!lval-compound || (lval-compMask 0x1))
return base;
- Symbol *slot = cloneShallow(func, base);
+ Value *slot = cloneShallow(func, base);
slot-reg.data.offset += (ffs(lval-compMask) - 1) * lval-reg.size;
slot-reg.size = lval-reg.size;
@@ -1486,7 +1486,7 @@ SpillCodeInserter::spill(Instruction *defi, Value *slot,
LValue *lval)
{
const DataType ty = typeOfSize(lval-reg.size);
- slot = offsetSlot(slot-asSym(), lval);
+ slot = offsetSlot(slot, lval);
Instruction *st;
if (slot-reg.file == FILE_MEMORY_LOCAL) {
@@ -1507,7 +1507,7 @@ SpillCodeInserter::unspill(Instruction *usei, LValue
*lval, Value *slot)
{
const DataType ty = typeOfSize(lval-reg.size);
- slot = offsetSlot(slot-asSym(), lval);
+ slot = offsetSlot(slot, lval);
lval = cloneShallow(func, lval);
Instruction *ld;
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Mesa (master): nv50/ir/ra: some register spilling fixes
Module: Mesa
Branch: master
Commit: 2e9ee44797fcce10e2f11ecb8520655f1e30280a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e9ee44797fcce10e2f11ecb8520655f1e30280a
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Sat Feb 8 19:32:54 2014 +0100
nv50/ir/ra: some register spilling fixes
Cc: 10.1 mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 39 +---
1 file changed, 34 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index bbf9838..dd3beb7 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
@@ -284,6 +284,7 @@ public:
bool run(const std::listValuePair);
Symbol *assignSlot(const Interval, const unsigned int size);
+ Symbol *offsetSlot(Symbol *, const LValue *);
inline int32_t getStackSize() const { return stackSize; }
private:
@@ -774,6 +775,7 @@ GCRA::RIG_Node::init(const RegisterSet regs, LValue *lval)
weight = std::numeric_limitsfloat::infinity();
degree = 0;
degreeLimit = regs.getFileSize(f, lval-reg.size);
+ degreeLimit -= relDegree[1][colors] - 1;
livei.insert(lval-livei);
}
@@ -1466,10 +1468,25 @@ SpillCodeInserter::assignSlot(const Interval livei,
const unsigned int size)
return slot.sym;
}
+Symbol *
+SpillCodeInserter::offsetSlot(Symbol *base, const LValue *lval)
+{
+ if (!base || !lval-compound || (lval-compMask 0x1))
+ return base;
+ Symbol *slot = cloneShallow(func, base);
+
+ slot-reg.data.offset += (ffs(lval-compMask) - 1) * lval-reg.size;
+ slot-reg.size = lval-reg.size;
+
+ return slot;
+}
+
void
SpillCodeInserter::spill(Instruction *defi, Value *slot, LValue *lval)
{
- const DataType ty = typeOfSize(slot-reg.size);
+ const DataType ty = typeOfSize(lval-reg.size);
+
+ slot = offsetSlot(slot-asSym(), lval);
Instruction *st;
if (slot-reg.file == FILE_MEMORY_LOCAL) {
@@ -1488,8 +1505,9 @@ SpillCodeInserter::spill(Instruction *defi, Value *slot,
LValue *lval)
LValue *
SpillCodeInserter::unspill(Instruction *usei, LValue *lval, Value *slot)
{
- const DataType ty = typeOfSize(slot-reg.size);
+ const DataType ty = typeOfSize(lval-reg.size);
+ slot = offsetSlot(slot-asSym(), lval);
lval = cloneShallow(func, lval);
Instruction *ld;
@@ -1506,6 +1524,16 @@ SpillCodeInserter::unspill(Instruction *usei, LValue
*lval, Value *slot)
return lval;
}
+
+// For each value that is to be spilled, go through all its definitions.
+// A value can have multiple definitions if it has been coalesced before.
+// For each definition, first go through all its uses and insert an unspill
+// instruction before it, then replace the use with the temporary register.
+// Unspill can be either a load from memory or simply a move to another
+// register file.
+// For Pseudo instructions (like PHI, SPLIT, MERGE) we can erase the use
+// if we have spilled to a memory location, or simply with the new register.
+// No load or conversion instruction should be needed.
bool
SpillCodeInserter::run(const std::listValuePair lst)
{
@@ -1524,12 +1552,13 @@ SpillCodeInserter::run(const std::listValuePair lst)
LValue *dval = (*d)-get()-asLValue();
Instruction *defi = (*d)-getInsn();
- // handle uses first or they'll contain the spill stores
+ // Unspill at each use *before* inserting spill instructions,
+ // we don't want to have the spill instructions in the use list here.
while (!dval-uses.empty()) {
ValueRef *u = dval-uses.front();
Instruction *usei = u-getInsn();
assert(usei);
-if (usei-op == OP_PHI) {
+if (usei-isPseudo()) {
tmp = (slot-reg.file == FILE_MEMORY_LOCAL) ? NULL : slot;
last = NULL;
} else
@@ -1541,7 +1570,7 @@ SpillCodeInserter::run(const std::listValuePair lst)
}
assert(defi);
- if (defi-op == OP_PHI) {
+ if (defi-isPseudo()) {
d = lval-defs.erase(d);
--d;
if (slot-reg.file == FILE_MEMORY_LOCAL)
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Mesa (master): nvc0: create the SW object
Module: Mesa
Branch: master
Commit: dd2229d4c68ed78a50104637aef904f8ab6d7dd3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd2229d4c68ed78a50104637aef904f8ab6d7dd3
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Fri Feb 7 22:51:27 2014 +0100
nvc0: create the SW object
It's required for being able to use software methods now.
---
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c |9 +
src/gallium/drivers/nouveau/nvc0/nvc0_screen.h |1 +
2 files changed, 10 insertions(+)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 752d72b..6bf0a3a 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -361,6 +361,7 @@ nvc0_screen_destroy(struct pipe_screen *pscreen)
nouveau_object_del(screen-eng2d);
nouveau_object_del(screen-m2mf);
nouveau_object_del(screen-compute);
+ nouveau_object_del(screen-nvsw);
nouveau_screen_fini(screen-base);
@@ -597,6 +598,14 @@ nvc0_screen_create(struct nouveau_device *dev)
screen-base.fence.emit = nvc0_screen_fence_emit;
screen-base.fence.update = nvc0_screen_fence_update;
+
+ ret = nouveau_object_new(chan,
+(dev-chipset 0xe0) ? 0x1f906e : 0x906e, 0x906e,
+NULL, 0, screen-nvsw);
+ if (ret)
+ FAIL_SCREEN_INIT(Error creating SW object: %d\n, ret);
+
+
switch (dev-chipset ~0xf) {
case 0x100:
case 0xf0:
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
index 27a0c5f..c58add5 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
@@ -76,6 +76,7 @@ struct nvc0_screen {
struct nouveau_object *eng2d;
struct nouveau_object *m2mf;
struct nouveau_object *compute;
+ struct nouveau_object *nvsw;
};
static INLINE struct nvc0_screen *
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Mesa (master): nvc0/ir/emit: hardcode vertex output stream to 0 for now
Module: Mesa
Branch: master
Commit: b7233acf782a39c7e5643cb303022360664b6046
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7233acf782a39c7e5643cb303022360664b6046
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Fri Feb 7 22:39:44 2014 +0100
nvc0/ir/emit: hardcode vertex output stream to 0 for now
---
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp |9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index 96a4af4..f15ca1b 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -1488,8 +1488,13 @@ CodeEmitterNVC0::emitOUT(const Instruction *i)
// vertex stream
if (i-src(1).getFile() == FILE_IMMEDIATE) {
- code[1] |= 0xc000;
- code[0] |= SDATA(i-src(1)).u32 26;
+ // Using immediate encoding here triggers an invalid opcode error
+ // or random results when error reporting is disabled.
+ // TODO: figure this out when we get multiple vertex streams
+ assert(SDATA(i-src(1)).u32 == 0);
+ srcId(NULL, 26);
+ // code[1] |= 0xc000;
+ // code[0] |= SDATA(i-src(1)).u32 26;
} else {
srcId(i-src(1), 26);
}
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Mesa (master): nvc0: handle TGSI_SEMANTIC_LAYER
Module: Mesa
Branch: master
Commit: 882e98e5e6e63787d0eac572c461605e69fc1589
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=882e98e5e6e63787d0eac572c461605e69fc1589
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Fri Feb 7 23:04:43 2014 +0100
nvc0: handle TGSI_SEMANTIC_LAYER
Cc: 10.1 mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h|1 -
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp |2 +-
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp |2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_program.c |2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c|2 +-
5 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index 752bad3..f2f4ead 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -71,7 +71,6 @@ struct nv50_ir_varying
#define NV50_SEMANTIC_CLIPDISTANCE (TGSI_SEMANTIC_COUNT + 0)
#define NV50_SEMANTIC_VIEWPORTINDEX (TGSI_SEMANTIC_COUNT + 4)
-#define NV50_SEMANTIC_LAYER (TGSI_SEMANTIC_COUNT + 5)
#define NV50_SEMANTIC_INVOCATIONID (TGSI_SEMANTIC_COUNT + 6)
#define NV50_SEMANTIC_TESSFACTOR(TGSI_SEMANTIC_COUNT + 7)
#define NV50_SEMANTIC_TESSCOORD (TGSI_SEMANTIC_COUNT + 8)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index d7c06a4..78a6c83 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -861,8 +861,8 @@ int Source::inferSysValDirection(unsigned sn) const
case TGSI_SEMANTIC_INSTANCEID:
case TGSI_SEMANTIC_VERTEXID:
return 1;
-#if 0
case TGSI_SEMANTIC_LAYER:
+#if 0
case TGSI_SEMANTIC_VIEWPORTINDEX:
return 0;
#endif
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
index 636ef9e..de07646 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
@@ -532,7 +532,7 @@ recordLocation(uint16_t *locs, uint8_t *masks,
case TGSI_SEMANTIC_INSTANCEID: locs[SV_INSTANCE_ID] = addr; break;
case TGSI_SEMANTIC_VERTEXID: locs[SV_VERTEX_ID] = addr; break;
case TGSI_SEMANTIC_PRIMID: locs[SV_PRIMITIVE_ID] = addr; break;
- case NV50_SEMANTIC_LAYER: locs[SV_LAYER] = addr; break;
+ case TGSI_SEMANTIC_LAYER: locs[SV_LAYER] = addr; break;
case NV50_SEMANTIC_VIEWPORTINDEX: locs[SV_VIEWPORT_INDEX] = addr; break;
default:
break;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index 71deb34..1e7f7d2 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -64,7 +64,7 @@ nvc0_shader_output_address(unsigned sn, unsigned si, unsigned
ubase)
switch (sn) {
case NV50_SEMANTIC_TESSFACTOR:return 0x000 + si * 0x4;
case TGSI_SEMANTIC_PRIMID:return 0x060;
- case NV50_SEMANTIC_LAYER: return 0x064;
+ case TGSI_SEMANTIC_LAYER: return 0x064;
case NV50_SEMANTIC_VIEWPORTINDEX: return 0x068;
case TGSI_SEMANTIC_PSIZE: return 0x06c;
case TGSI_SEMANTIC_POSITION: return 0x070;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
index b820ef2..a52fed0 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
@@ -190,7 +190,7 @@ nvc0_gmtyprog_validate(struct nvc0_context *nvc0)
/* we allow GPs with no code for specifying stream output state only */
if (gp gp-code_size) {
- const boolean gp_selects_layer = gp-hdr[13] (1 9);
+ const boolean gp_selects_layer = !!(gp-hdr[13] (1 9));
BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
PUSH_DATA (push, 0x41);
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Mesa (master): Move nv30, nv50 and nvc0 to nouveau.
Module: Mesa
Branch: master
Commit: 5eb7ff1175a644ffe3b0f1a75cb235400355f9fb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5eb7ff1175a644ffe3b0f1a75cb235400355f9fb
Author: Johannes Obermayr johannesoberm...@gmx.de
Date: Tue Aug 20 20:14:00 2013 +0200
Move nv30, nv50 and nvc0 to nouveau.
It is planned to ship openSUSE 13.1 with -shared libs.
nouveau.la, nv30.la, nv50.la and nvc0.la are currently LIBADDs in all nouveau
related targets.
This change makes it possible to easily build one shared libnouveau.so which is
then LIBADDed.
Also dlopen will be faster for one library instead of three and build time on
-jX will be reduced.
Whitespace fixes were requested by 'git am'.
Signed-off-by: Johannes Obermayr johannesoberm...@gmx.de
Acked-by: Christoph Bumiller christoph.bumil...@speed.at
Acked-by: Ian Romanick ian.d.roman...@intel.com
---
configure.ac |5 +-
src/gallium/Android.mk |5 +-
src/gallium/drivers/Makefile.am|2 +-
src/gallium/drivers/nouveau/Android.mk |8 ++-
src/gallium/drivers/nouveau/Makefile.am| 14 ++-
src/gallium/drivers/nouveau/Makefile.sources | 91
.../drivers/{nv50 = nouveau}/codegen/nv50_ir.cpp |8 +-
.../drivers/{nv50 = nouveau}/codegen/nv50_ir.h|8 +-
.../{nv50 = nouveau}/codegen/nv50_ir_bb.cpp |2 +-
.../codegen/nv50_ir_build_util.cpp |4 +-
.../{nv50 = nouveau}/codegen/nv50_ir_build_util.h |0
.../{nv50 = nouveau}/codegen/nv50_ir_driver.h |0
.../codegen/nv50_ir_emit_gk110.cpp |2 +-
.../codegen/nv50_ir_emit_nv50.cpp |4 +-
.../codegen/nv50_ir_emit_nvc0.cpp |2 +-
.../codegen/nv50_ir_from_tgsi.cpp | 12 ++--
.../{nv50 = nouveau}/codegen/nv50_ir_graph.cpp|4 +-
.../{nv50 = nouveau}/codegen/nv50_ir_graph.h |2 +-
.../{nv50 = nouveau}/codegen/nv50_ir_inlines.h|0
.../codegen/nv50_ir_lowering_nv50.cpp |6 +-
.../codegen/nv50_ir_lowering_nvc0.cpp |6 +-
.../{nv50 = nouveau}/codegen/nv50_ir_peephole.cpp |6 +-
.../{nv50 = nouveau}/codegen/nv50_ir_print.cpp|4 +-
.../{nv50 = nouveau}/codegen/nv50_ir_ra.cpp |4 +-
.../{nv50 = nouveau}/codegen/nv50_ir_ssa.cpp |6 +-
.../{nv50 = nouveau}/codegen/nv50_ir_target.cpp |6 +-
.../{nv50 = nouveau}/codegen/nv50_ir_target.h |2 +-
.../codegen/nv50_ir_target_nv50.cpp|2 +-
.../codegen/nv50_ir_target_nv50.h |2 +-
.../codegen/nv50_ir_target_nvc0.cpp|2 +-
.../codegen/nv50_ir_target_nvc0.h |2 +-
.../{nv50 = nouveau}/codegen/nv50_ir_util.cpp |2 +-
.../{nv50 = nouveau}/codegen/nv50_ir_util.h |2 +-
.../{nvc0 = nouveau}/codegen/target_lib_nvc0.asm |0
.../codegen/target_lib_nvc0.asm.h |1 -
.../{nvc0 = nouveau}/codegen/target_lib_nve4.asm |0
.../codegen/target_lib_nve4.asm.h |1 -
.../codegen/target_lib_nvf0.asm.h |0
src/gallium/drivers/nouveau/nouveau_mm.c |1 -
src/gallium/drivers/nouveau/nouveau_screen.c |4 +-
src/gallium/drivers/nouveau/nouveau_video.c|2 +-
.../drivers/{ = nouveau}/nv30/nv01_2d.xml.h |0
.../drivers/{ = nouveau}/nv30/nv30-40_3d.xml.h|0
.../drivers/{ = nouveau}/nv30/nv30_clear.c| 10 +-
.../drivers/{ = nouveau}/nv30/nv30_context.c | 12 ++--
.../drivers/{ = nouveau}/nv30/nv30_context.h |6 +-
src/gallium/drivers/{ = nouveau}/nv30/nv30_draw.c |8 +-
.../drivers/{ = nouveau}/nv30/nv30_format.c |6 +-
.../drivers/{ = nouveau}/nv30/nv30_format.h |0
.../drivers/{ = nouveau}/nv30/nv30_fragprog.c |8 +-
.../drivers/{ = nouveau}/nv30/nv30_fragtex.c |8 +-
.../drivers/{ = nouveau}/nv30/nv30_miptree.c | 10 +-
src/gallium/drivers/{ = nouveau}/nv30/nv30_push.c |8 +-
.../drivers/{ = nouveau}/nv30/nv30_query.c|8 +-
.../drivers/{ = nouveau}/nv30/nv30_resource.c |8 +-
.../drivers/{ = nouveau}/nv30/nv30_resource.h |2 +-
.../drivers/{ = nouveau}/nv30/nv30_screen.c | 18 ++--
.../drivers/{ = nouveau}/nv30/nv30_screen.h | 10 +-
.../drivers/{ = nouveau}/nv30/nv30_state.c| 10 +-
.../drivers/{ = nouveau}/nv30/nv30_state.h|0
.../{ = nouveau}/nv30/nv30_state_validate.c |8 +-
.../drivers/{ = nouveau}/nv30/nv30_texture.c |8 +-
.../drivers/{ = nouveau}/nv30/nv30_transfer.c | 12 ++--
.../drivers/{ = nouveau}/nv30/nv30_transfer.h |0
src/gallium/drivers/{ = nouveau}/nv30/nv30_vbo.c | 10 +-
.../drivers/{ = nouveau}/nv30/nv30_vertprog.c |8 +-
.../drivers/{ = nouveau}/nv30/nv30_vertprog.h |2 +-
.../drivers/{ = nouveau}/nv30
Mesa (master): nv30: fix inconsistent setting of push-user_priv
Module: Mesa Branch: master Commit: 85f7df81a91b1825bf25adf3d4febcbb5e0a0d7e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=85f7df81a91b1825bf25adf3d4febcbb5e0a0d7e Author: Ilia Mirkin imir...@alum.mit.edu Date: Wed Sep 4 02:06:05 2013 -0400 nv30: fix inconsistent setting of push-user_priv It's set to nv30-bufctx everywhere else. Signed-off-by: Ilia Mirkin imir...@alum.mit.edu Cc: 9.2 mesa-sta...@lists.freedesktop.org --- src/gallium/drivers/nv30/nv30_context.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/gallium/drivers/nv30/nv30_context.c b/src/gallium/drivers/nv30/nv30_context.c index e872c02..acef493 100644 --- a/src/gallium/drivers/nv30/nv30_context.c +++ b/src/gallium/drivers/nv30/nv30_context.c @@ -208,7 +208,7 @@ nv30_context_create(struct pipe_screen *pscreen, void *priv) /*XXX: *cough* per-context pushbufs */ push = screen-base.pushbuf; nv30-base.pushbuf = push; - nv30-base.pushbuf-user_priv = push-user_priv; /* hack at validate time */ + nv30-base.pushbuf-user_priv = nv30-bufctx; /* hack at validate time */ nv30-base.pushbuf-rsvd_kick = 16; /* hack in screen before first space */ nv30-base.pushbuf-kick_notify = nv30_context_kick_notify; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nv30: find first unused texcoord rather than bailing if first is used
Module: Mesa Branch: master Commit: 3282697621241e646247b85327c50747416a766b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3282697621241e646247b85327c50747416a766b Author: Ilia Mirkin imir...@alum.mit.edu Date: Sun Sep 1 12:38:52 2013 -0400 nv30: find first unused texcoord rather than bailing if first is used This fixes shaders produced by supertuxkart. Cc: 9.2 mesa-sta...@lists.freedesktop.org Signed-off-by: Ilia Mirkin imir...@alum.mit.edu --- src/gallium/drivers/nv30/nvfx_fragprog.c |3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nv30/nvfx_fragprog.c b/src/gallium/drivers/nv30/nvfx_fragprog.c index 1231862..a734330 100644 --- a/src/gallium/drivers/nv30/nvfx_fragprog.c +++ b/src/gallium/drivers/nv30/nvfx_fragprog.c @@ -976,9 +976,8 @@ nvfx_fragprog_assign_generic(struct nv30_context *nvfx, struct nvfx_fpc *fpc, fpc-r_input[idx] = nvfx_reg(NVFXSR_INPUT, hw); return TRUE; } - return FALSE; } - return TRUE; + return FALSE; default: return TRUE; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nouveau: initialise the nouveau_transfer maps
Module: Mesa Branch: master Commit: dc10251d086576a007c77b7ca7854f5fe8c7e134 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc10251d086576a007c77b7ca7854f5fe8c7e134 Author: Emil Velikov emil.l.veli...@gmail.com Date: Fri Aug 9 19:51:02 2013 +0100 nouveau: initialise the nouveau_transfer maps Cc: 9.2 and 9.1 mesa-sta...@lists.freedesktop.org Signed-off-by: Emil Velikov emil.l.veli...@gmail.com --- src/gallium/drivers/nouveau/nouveau_buffer.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/gallium/drivers/nouveau/nouveau_buffer.c b/src/gallium/drivers/nouveau/nouveau_buffer.c index 02bc6f0..3e04049 100644 --- a/src/gallium/drivers/nouveau/nouveau_buffer.c +++ b/src/gallium/drivers/nouveau/nouveau_buffer.c @@ -289,6 +289,7 @@ nouveau_buffer_cache(struct nouveau_context *nv, struct nv04_resource *buf) tx.base.box.x = 0; tx.base.box.width = buf-base.width0; tx.bo = NULL; + tx.map = NULL; if (!buf-data) if (!nouveau_buffer_malloc(buf)) @@ -690,6 +691,7 @@ nouveau_buffer_migrate(struct nouveau_context *nv, tx.base.box.x = 0; tx.base.box.width = buf-base.width0; tx.bo = NULL; + tx.map = NULL; if (!nouveau_transfer_staging(nv, tx, FALSE)) return FALSE; nouveau_transfer_write(nv, tx, 0, tx.base.box.width); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nvc0: fix blitctx memory leak
Module: Mesa
Branch: master
Commit: 2a7762bdb62faa1d54c445fcec7733cf6f690ac5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a7762bdb62faa1d54c445fcec7733cf6f690ac5
Author: Joakim Sindholt opensou...@zhasha.com
Date: Sun May 12 16:17:00 2013 +0200
nvc0: fix blitctx memory leak
Cc: 9.2 and 9.1 mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/nvc0/nvc0_context.c |1 +
src/gallium/drivers/nvc0/nvc0_context.h |1 +
src/gallium/drivers/nvc0/nvc0_surface.c |7 +++
3 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_context.c
b/src/gallium/drivers/nvc0/nvc0_context.c
index bf0c204..f7cfe59 100644
--- a/src/gallium/drivers/nvc0/nvc0_context.c
+++ b/src/gallium/drivers/nvc0/nvc0_context.c
@@ -111,6 +111,7 @@ nvc0_destroy(struct pipe_context *pipe)
nouveau_pushbuf_kick(nvc0-base.pushbuf, nvc0-base.pushbuf-channel);
nvc0_context_unreference_resources(nvc0);
+ nvc0_blitctx_destroy(nvc0);
#ifdef NVC0_WITH_DRAW_MODULE
draw_destroy(nvc0-draw);
diff --git a/src/gallium/drivers/nvc0/nvc0_context.h
b/src/gallium/drivers/nvc0/nvc0_context.h
index 2c84cdf..a175f0a 100644
--- a/src/gallium/drivers/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nvc0/nvc0_context.h
@@ -96,6 +96,7 @@
struct nvc0_blitctx;
boolean nvc0_blitctx_create(struct nvc0_context *);
+void nvc0_blitctx_destroy(struct nvc0_context *);
struct nvc0_context {
struct nouveau_context base;
diff --git a/src/gallium/drivers/nvc0/nvc0_surface.c
b/src/gallium/drivers/nvc0/nvc0_surface.c
index c8d26f5..606a2b5 100644
--- a/src/gallium/drivers/nvc0/nvc0_surface.c
+++ b/src/gallium/drivers/nvc0/nvc0_surface.c
@@ -1247,6 +1247,13 @@ nvc0_blitctx_create(struct nvc0_context *nvc0)
}
void
+nvc0_blitctx_destroy(struct nvc0_context *nvc0)
+{
+ if (nvc0-blit)
+ FREE(nvc0-blit);
+}
+
+void
nvc0_init_surface_functions(struct nvc0_context *nvc0)
{
struct pipe_context *pipe = nvc0-base.pipe;
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Mesa (master): nvc0/ir: add f32 long immediate cannot saturate
Module: Mesa
Branch: master
Commit: 53992060564bd66f167342e0864cee9406147b04
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=53992060564bd66f167342e0864cee9406147b04
Author: Christoph Bumiller christoph.bumil...@speed.at
Date: Sun Jun 30 15:23:15 2013 +0200
nvc0/ir: add f32 long immediate cannot saturate
Cc: 9.2 mesa-sta...@lists.freedesktop.org
---
.../drivers/nvc0/codegen/nv50_ir_target_nvc0.cpp | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/nvc0/codegen/nv50_ir_target_nvc0.cpp
b/src/gallium/drivers/nvc0/codegen/nv50_ir_target_nvc0.cpp
index 2dd7fd2..4ee1a67 100644
--- a/src/gallium/drivers/nvc0/codegen/nv50_ir_target_nvc0.cpp
+++ b/src/gallium/drivers/nvc0/codegen/nv50_ir_target_nvc0.cpp
@@ -337,6 +337,11 @@ TargetNVC0::insnCanLoad(const Instruction *i, int s,
// (except if we implement more constraints)
if (ld-getSrc(0)-asImm()-reg.data.u32 0xfff)
return false;
+ } else
+ if (i-op == OP_ADD i-sType == TYPE_F32) {
+ // add f32 LIMM cannot saturate
+ if (i-saturate (reg.data.u32 0xfff))
+return false;
}
}
@@ -431,6 +436,13 @@ TargetNVC0::isSatSupported(const Instruction *insn) const
if (insn-dType == TYPE_U32)
return (insn-op == OP_ADD) || (insn-op == OP_MAD);
+ // add f32 LIMM cannot saturate
+ if (insn-op == OP_ADD insn-sType == TYPE_F32) {
+ if (insn-getSrc(1)-asImm()
+ insn-getSrc(1)-reg.data.u32 0xfff)
+ return false;
+ }
+
return insn-dType == TYPE_F32;
}
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Mesa (master): nvc0/ir: fix use after free in texture barrier insertion pass
Module: Mesa
Branch: master
Commit: 7086636358b611a2bb124253e1fe870107e1cecb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7086636358b611a2bb124253e1fe870107e1cecb
Author: Tiziano Bacocco tizb...@gmail.com
Date: Tue Jul 30 22:04:49 2013 +0200
nvc0/ir: fix use after free in texture barrier insertion pass
Fixes crash with Amnesia: The Dark Descent.
Cc: 9.2 and 9.1 mesa-sta...@lists.freedesktop.org
---
.../drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
b/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
index 251e49b..1832e1a 100644
--- a/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
@@ -443,6 +443,7 @@ NVC0LegalizePostRA::insertTextureBarriers(Function *fn)
if (i-op == OP_TEXBAR) {
if (i-subOp = max) {
delete_Instruction(prog, i);
+ i = NULL;
} else {
max = i-subOp;
if (prev prev-op == OP_TEXBAR prev-subOp = max) {
@@ -454,7 +455,7 @@ NVC0LegalizePostRA::insertTextureBarriers(Function *fn)
if (isTextureOp(i-op)) {
max++;
}
- if (!i-isNop())
+ if (i !i-isNop())
prev = i;
}
}
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Mesa (master): nvc0: delete compute object on screen destruction
Module: Mesa Branch: master Commit: 7fe159ba7442b4558d4d06ad8c236ae565f5e5d8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7fe159ba7442b4558d4d06ad8c236ae565f5e5d8 Author: Christoph Bumiller christoph.bumil...@speed.at Date: Sun May 12 16:42:45 2013 +0200 nvc0: delete compute object on screen destruction Cc: 9.2 mesa-sta...@lists.freedesktop.org --- src/gallium/drivers/nvc0/nvc0_screen.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/gallium/drivers/nvc0/nvc0_screen.c b/src/gallium/drivers/nvc0/nvc0_screen.c index 93a2902..1de07ff 100644 --- a/src/gallium/drivers/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nvc0/nvc0_screen.c @@ -361,6 +361,7 @@ nvc0_screen_destroy(struct pipe_screen *pscreen) nouveau_object_del(screen-eng3d); nouveau_object_del(screen-eng2d); nouveau_object_del(screen-m2mf); + nouveau_object_del(screen-compute); nouveau_screen_fini(screen-base); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nvc0: don't use bufctx in nvc0_cb_push
Module: Mesa
Branch: master
Commit: 1048d89907b3a11e695b2c44d1966fb4e61b1b77
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1048d89907b3a11e695b2c44d1966fb4e61b1b77
Author: Christoph Bumiller christoph.bumil...@speed.at
Date: Mon Jun 17 18:47:21 2013 +0200
nvc0: don't use bufctx in nvc0_cb_push
Too many calls into libdrm when a single one is enough.
---
src/gallium/drivers/nvc0/nvc0_transfer.c | 10 +++---
1 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_transfer.c
b/src/gallium/drivers/nvc0/nvc0_transfer.c
index 3f87662..a0333a3 100644
--- a/src/gallium/drivers/nvc0/nvc0_transfer.c
+++ b/src/gallium/drivers/nvc0/nvc0_transfer.c
@@ -505,13 +505,13 @@ nvc0_miptree_transfer_unmap(struct pipe_context *pctx,
FREE(tx);
}
+/* This happens rather often with DTD9/st. */
void
nvc0_cb_push(struct nouveau_context *nv,
struct nouveau_bo *bo, unsigned domain,
unsigned base, unsigned size,
unsigned offset, unsigned words, const uint32_t *data)
{
- struct nouveau_bufctx *bctx = nvc0_context(nv-pipe)-bufctx;
struct nouveau_pushbuf *push = nv-pushbuf;
NOUVEAU_DRV_STAT(nv-screen, constbuf_upload_count, 1);
@@ -520,10 +520,6 @@ nvc0_cb_push(struct nouveau_context *nv,
assert(!(offset 3));
size = align(size, 0x100);
- nouveau_bufctx_refn(bctx, 0, bo, NOUVEAU_BO_WR | domain);
- nouveau_pushbuf_bufctx(push, bctx);
- nouveau_pushbuf_validate(push);
-
BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
PUSH_DATA (push, size);
PUSH_DATAh(push, bo-offset + base);
@@ -534,6 +530,8 @@ nvc0_cb_push(struct nouveau_context *nv,
nr = MIN2(nr, words);
nr = MIN2(nr, NV04_PFIFO_MAX_PACKET_LEN - 1);
+ PUSH_SPACE(push, nr + 2);
+ PUSH_REFN (push, bo, NOUVEAU_BO_WR | domain);
BEGIN_1IC0(push, NVC0_3D(CB_POS), nr + 1);
PUSH_DATA (push, offset);
PUSH_DATAp(push, data, nr);
@@ -542,8 +540,6 @@ nvc0_cb_push(struct nouveau_context *nv,
data += nr;
offset += nr * 4;
}
-
- nouveau_bufctx_reset(bctx, 0);
}
void
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Mesa (master): nvc0: clear the flushed flag
Module: Mesa
Branch: master
Commit: 528a48ee8da91d79614a877edf8583d063db6c36
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=528a48ee8da91d79614a877edf8583d063db6c36
Author: Christoph Bumiller christoph.bumil...@speed.at
Date: Tue Jun 18 10:59:45 2013 +0200
nvc0: clear the flushed flag
---
src/gallium/drivers/nvc0/nvc0_state_validate.c |9 -
1 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_state_validate.c
b/src/gallium/drivers/nvc0/nvc0_state_validate.c
index 1e14723..4b50b43 100644
--- a/src/gallium/drivers/nvc0/nvc0_state_validate.c
+++ b/src/gallium/drivers/nvc0/nvc0_state_validate.c
@@ -566,11 +566,10 @@ nvc0_state_validate(struct nvc0_context *nvc0, uint32_t
mask, unsigned words)
nouveau_pushbuf_bufctx(nvc0-base.pushbuf, nvc0-bufctx_3d);
ret = nouveau_pushbuf_validate(nvc0-base.pushbuf);
- if (unlikely(ret))
- return FALSE;
- if (unlikely(nvc0-state.flushed))
+ if (unlikely(nvc0-state.flushed)) {
+ nvc0-state.flushed = FALSE;
nvc0_bufctx_fence(nvc0, nvc0-bufctx_3d, TRUE);
-
- return TRUE;
+ }
+ return !ret;
}
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Mesa (master): nvc0: add more MP counters for nve4
Module: Mesa Branch: master Commit: 981b5891016580a72c2d6a457c6e8ef2dd5a9c95 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=981b5891016580a72c2d6a457c6e8ef2dd5a9c95 Author: Samuel Pitoiset samuel.pitoi...@gmail.com Date: Thu Jul 25 10:35:34 2013 +0200 nvc0: add more MP counters for nve4 --- src/gallium/drivers/nvc0/nvc0_query.c | 20 src/gallium/drivers/nvc0/nvc0_screen.h | 25 ++--- src/gallium/drivers/nvc0/nve4_compute.xml.h | 16 +--- 3 files changed, 47 insertions(+), 14 deletions(-) diff --git a/src/gallium/drivers/nvc0/nvc0_query.c b/src/gallium/drivers/nvc0/nvc0_query.c index 75c515a..d2c423b 100644 --- a/src/gallium/drivers/nvc0/nvc0_query.c +++ b/src/gallium/drivers/nvc0/nvc0_query.c @@ -774,6 +774,16 @@ static const char *nve4_pm_query_names[] = active_warps, active_cycles, inst_issued, + atom_count, + gred_count, + shared_load_replay, + shared_store_replay, + local_load_transactions, + local_store_transactions, + l1_shared_load_transactions, + l1_shared_store_transactions, + global_ld_mem_divergence_replays, + global_st_mem_divergence_replays, /* metrics, i.e. functions of the MP counters */ metric-ipc, /* inst_executed, clock */ metric-ipac, /* inst_executed, active_cycles */ @@ -871,6 +881,16 @@ static const struct nve4_mp_pm_query_cfg nve4_mp_pm_queries[] = _Q1A(BRANCH_DIVERGENT, 0x0001, B6, BRANCH, 0x0010, 1, 1), _Q1B(ACTIVE_WARPS, 0x003f, B6, WARP, 0x31483104, 2, 1), _Q1B(ACTIVE_CYCLES, 0x0001, B6, WARP, 0x, 1, 1), + _Q1A(ATOM_COUNT, 0x0001, B6, BRANCH, 0x, 1, 1), + _Q1A(GRED_COUNT, 0x0001, B6, BRANCH, 0x0008, 1, 1), + _Q1B(LD_SHARED_REPLAY, 0x0001, B6, REPLAY, 0x0008, 1, 1), + _Q1B(ST_SHARED_REPLAY, 0x0001, B6, REPLAY, 0x000c, 1, 1), + _Q1B(LD_LOCAL_TRANSACTIONS, 0x0001, B6, TRANSACTION, 0x, 1, 1), + _Q1B(ST_LOCAL_TRANSACTIONS, 0x0001, B6, TRANSACTION, 0x0004, 1, 1), + _Q1B(L1_LD_SHARED_TRANSACTIONS, 0x0001, B6, TRANSACTION, 0x0008, 1, 1), + _Q1B(L1_ST_SHARED_TRANSACTIONS, 0x0001, B6, TRANSACTION, 0x000c, 1, 1), + _Q1B(GLD_MEM_DIV_REPLAY, 0x0001, B6, REPLAY, 0x0010, 1, 1), + _Q1B(GST_MEM_DIV_REPLAY, 0x0001, B6, REPLAY, 0x0014, 1, 1), _M2AB(IPC, 0x3, B6, EXEC, 0x398, 0x, LOGOP, WARP, 0x0, DIV_SUM_M0, 10, 1), _M2AB(IPAC, 0x3, B6, EXEC, 0x398, 0x1, B6, WARP, 0x0, AVG_DIV_MM, 10, 1), _M2A(IPEC, 0x3, B6, EXEC, 0x398, 0xe, LOGOP, EXEC, 0x398, AVG_DIV_MM, 10, 1), diff --git a/src/gallium/drivers/nvc0/nvc0_screen.h b/src/gallium/drivers/nvc0/nvc0_screen.h index 826014e..ed43696 100644 --- a/src/gallium/drivers/nvc0/nvc0_screen.h +++ b/src/gallium/drivers/nvc0/nvc0_screen.h @@ -87,7 +87,7 @@ nvc0_screen(struct pipe_screen *screen) /* Performance counter queries: */ -#define NVE4_PM_QUERY_COUNT 39 +#define NVE4_PM_QUERY_COUNT 49 #define NVE4_PM_QUERY(i)(PIPE_QUERY_DRIVER_SPECIFIC + (i)) #define NVE4_PM_QUERY_LAST NVE4_PM_QUERY(NVE4_PM_QUERY_COUNT - 1) #define NVE4_PM_QUERY_PROF_TRIGGER_00 @@ -123,12 +123,23 @@ nvc0_screen(struct pipe_screen *screen) #define NVE4_PM_QUERY_ACTIVE_WARPS 30 #define NVE4_PM_QUERY_ACTIVE_CYCLES 31 #define NVE4_PM_QUERY_INST_ISSUED 32 -#define NVE4_PM_QUERY_METRIC_IPC33 -#define NVE4_PM_QUERY_METRIC_IPAC 34 -#define NVE4_PM_QUERY_METRIC_IPEC 35 -#define NVE4_PM_QUERY_METRIC_MP_OCCUPANCY 36 -#define NVE4_PM_QUERY_METRIC_MP_EFFICIENCY 37 -#define NVE4_PM_QUERY_METRIC_INST_REPLAY_OHEAD 38 +#define NVE4_PM_QUERY_ATOM_COUNT33 +#define NVE4_PM_QUERY_GRED_COUNT34 +#define NVE4_PM_QUERY_LD_SHARED_REPLAY 35 +#define NVE4_PM_QUERY_ST_SHARED_REPLAY 36 +#define NVE4_PM_QUERY_LD_LOCAL_TRANSACTIONS 37 +#define NVE4_PM_QUERY_ST_LOCAL_TRANSACTIONS 38 +#define NVE4_PM_QUERY_L1_LD_SHARED_TRANSACTIONS 39 +#define NVE4_PM_QUERY_L1_ST_SHARED_TRANSACTIONS 40 +#define NVE4_PM_QUERY_GLD_MEM_DIV_REPLAY41 +#define NVE4_PM_QUERY_GST_MEM_DIV_REPLAY42 +#define NVE4_PM_QUERY_METRIC_IPC43 +#define NVE4_PM_QUERY_METRIC_IPAC 44 +#define NVE4_PM_QUERY_METRIC_IPEC 45 +#define NVE4_PM_QUERY_METRIC_MP_OCCUPANCY 46 +#define NVE4_PM_QUERY_METRIC_MP_EFFICIENCY 47 +#define NVE4_PM_QUERY_METRIC_INST_REPLAY_OHEAD 48 + /* #define NVE4_PM_QUERY_GR_IDLE 50 #define NVE4_PM_QUERY_BSP_IDLE 51 diff --git a/src/gallium/drivers/nvc0/nve4_compute.xml.h b/src/gallium/drivers/nvc0/nve4_compute.xml.h index 96527cc..e971fc1 100644 --- a/src/gallium/drivers/nvc0/nve4_compute.xml.h +++ b/src/gallium/drivers/nvc0/nve4_compute.xml.h @@ -8,13 +8,13 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this
Mesa (master): nv50: handle pure integer vertex attributes
Module: Mesa
Branch: master
Commit: 07c8f7a6f8dfe724c1ae92ec45dd04532b6fd453
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=07c8f7a6f8dfe724c1ae92ec45dd04532b6fd453
Author: Emil Velikov emil.l.veli...@gmail.com
Date: Fri Jun 21 18:04:55 2013 +0100
nv50: handle pure integer vertex attributes
And as a side effect fix a crash in the following piglit test:
general/attribs GL3
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
Cc: 9.2 and 9.1 mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/nv30/nv30_vbo.c |4 +++-
src/gallium/drivers/nv50/nv50_vbo.c | 12 +++-
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nv30/nv30_vbo.c
b/src/gallium/drivers/nv30/nv30_vbo.c
index 9033fa5..9f00c02 100644
--- a/src/gallium/drivers/nv30/nv30_vbo.c
+++ b/src/gallium/drivers/nv30/nv30_vbo.c
@@ -40,13 +40,15 @@ nv30_emit_vtxattr(struct nv30_context *nv30, struct
pipe_vertex_buffer *vb,
const unsigned nc = util_format_get_nr_components(ve-src_format);
struct nouveau_pushbuf *push = nv30-base.pushbuf;
struct nv04_resource *res = nv04_resource(vb-buffer);
+ const struct util_format_description *desc =
+ util_format_description(ve-src_format);
const void *data;
float v[4];
data = nouveau_resource_map_offset(nv30-base, res, vb-buffer_offset +
ve-src_offset, NOUVEAU_BO_RD);
- util_format_read_4f(ve-src_format, v, 0, data, 0, 0, 0, 1, 1);
+ desc-unpack_rgba_float(v, 0, data, 0, 1, 1);
switch (nc) {
case 4:
diff --git a/src/gallium/drivers/nv50/nv50_vbo.c
b/src/gallium/drivers/nv50/nv50_vbo.c
index db4e0cd..ca46f6c 100644
--- a/src/gallium/drivers/nv50/nv50_vbo.c
+++ b/src/gallium/drivers/nv50/nv50_vbo.c
@@ -140,10 +140,20 @@ nv50_emit_vtxattr(struct nv50_context *nv50, struct
pipe_vertex_buffer *vb,
const void *data = (const uint8_t *)vb-user_buffer + ve-src_offset;
float v[4];
const unsigned nc = util_format_get_nr_components(ve-src_format);
+ const struct util_format_description *desc =
+ util_format_description(ve-src_format);
assert(vb-user_buffer);
- util_format_read_4f(ve-src_format, v, 0, data, 0, 0, 0, 1, 1);
+ if (desc-channel[0].pure_integer) {
+ if (desc-channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
+ desc-unpack_rgba_sint((int32_t *)v, 0, data, 0, 1, 1);
+ } else {
+ desc-unpack_rgba_uint((uint32_t *)v, 0, data, 0, 1, 1);
+ }
+ } else {
+ desc-unpack_rgba_float(v, 0, data, 0, 1, 1);
+ }
switch (nc) {
case 4:
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Mesa (master): nvc0: implement MP performance counters for nvc0:nvd9
Module: Mesa
Branch: master
Commit: 31caddb8d95348502f3bdfe8b619515b801b3bf4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=31caddb8d95348502f3bdfe8b619515b801b3bf4
Author: Samuel Pitoiset samuel.pitoi...@gmail.com
Date: Thu Jul 25 10:35:36 2013 +0200
nvc0: implement MP performance counters for nvc0:nvd9
---
src/gallium/drivers/nvc0/nvc0_query.c | 428 +---
src/gallium/drivers/nvc0/nvc0_screen.h | 35 +++
2 files changed, 370 insertions(+), 93 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_query.c
b/src/gallium/drivers/nvc0/nvc0_query.c
index d2c423b..a9a0bbc 100644
--- a/src/gallium/drivers/nvc0/nvc0_query.c
+++ b/src/gallium/drivers/nvc0/nvc0_query.c
@@ -27,6 +27,7 @@
#include nvc0_context.h
#include nouveau/nv_object.xml.h
#include nve4_compute.xml.h
+#include nvc0_compute.xml.h
#define NVC0_QUERY_STATE_READY 0
#define NVC0_QUERY_STATE_ACTIVE 1
@@ -55,9 +56,9 @@ struct nvc0_query {
#define NVC0_QUERY_ALLOC_SPACE 256
-static void nve4_mp_pm_query_begin(struct nvc0_context *, struct nvc0_query *);
-static void nve4_mp_pm_query_end(struct nvc0_context *, struct nvc0_query *);
-static boolean nve4_mp_pm_query_result(struct nvc0_context *,
+static void nvc0_mp_pm_query_begin(struct nvc0_context *, struct nvc0_query *);
+static void nvc0_mp_pm_query_end(struct nvc0_context *, struct nvc0_query *);
+static boolean nvc0_mp_pm_query_result(struct nvc0_context *,
struct nvc0_query *, void *, boolean);
static INLINE struct nvc0_query *
@@ -155,20 +156,18 @@ nvc0_query_create(struct pipe_context *pipe, unsigned
type)
break;
} else
#endif
- if (nvc0-screen-base.class_3d = NVE4_3D_CLASS
- nvc0-screen-base.device-drm_version = 0x01000101) {
- if (type = NVE4_PM_QUERY(0)
- type = NVE4_PM_QUERY_LAST) {
+ if (nvc0-screen-base.device-drm_version = 0x01000101) {
+ if (type = NVE4_PM_QUERY(0) type = NVE4_PM_QUERY_LAST) {
/* for each MP:
* [00] = WS0.C0
* [04] = WS0.C1
* [08] = WS0.C2
* [0c] = WS0.C3
- * [10] = WS0.C0
+ * [10] = WS1.C0
* [14] = WS1.C1
* [18] = WS1.C2
* [1c] = WS1.C3
- * [20] = WS1.C0
+ * [20] = WS2.C0
* [24] = WS2.C1
* [28] = WS2.C2
* [2c] = WS2.C3
@@ -187,6 +186,21 @@ nvc0_query_create(struct pipe_context *pipe, unsigned type)
*/
space = (4 * 4 + 4 + 4) * nvc0-screen-mp_count *
sizeof(uint32_t);
break;
+ } else
+ if (type = NVC0_PM_QUERY(0) type = NVC0_PM_QUERY_LAST) {
+/* for each MP:
+ * [00] = MP.C0
+ * [04] = MP.C1
+ * [08] = MP.C2
+ * [0c] = MP.C3
+ * [10] = MP.C4
+ * [14] = MP.C5
+ * [18] = MP.C6
+ * [1c] = MP.C7
+ * [20] = MP.sequence
+ */
+space = (8 + 1) * nvc0-screen-mp_count * sizeof(uint32_t);
+break;
}
}
debug_printf(invalid query type: %u\n, type);
@@ -310,8 +324,9 @@ nvc0_query_begin(struct pipe_context *pipe, struct
pipe_query *pq)
q-u.value = 0;
} else
#endif
- if (q-type = NVE4_PM_QUERY(0) q-type = NVE4_PM_QUERY_LAST) {
- nve4_mp_pm_query_begin(nvc0, q);
+ if ((q-type = NVE4_PM_QUERY(0) q-type = NVE4_PM_QUERY_LAST) ||
+ (q-type = NVC0_PM_QUERY(0) q-type = NVC0_PM_QUERY_LAST)) {
+ nvc0_mp_pm_query_begin(nvc0, q);
}
break;
}
@@ -389,8 +404,10 @@ nvc0_query_end(struct pipe_context *pipe, struct
pipe_query *pq)
return;
} else
#endif
- if (q-type = NVE4_PM_QUERY(0) q-type = NVE4_PM_QUERY_LAST)
- nve4_mp_pm_query_end(nvc0, q);
+ if ((q-type = NVE4_PM_QUERY(0) q-type = NVE4_PM_QUERY_LAST) ||
+ (q-type = NVC0_PM_QUERY(0) q-type = NVC0_PM_QUERY_LAST)) {
+ nvc0_mp_pm_query_end(nvc0, q);
+ }
break;
}
if (q-is64bit)
@@ -428,8 +445,9 @@ nvc0_query_result(struct pipe_context *pipe, struct
pipe_query *pq,
return TRUE;
} else
#endif
- if (q-type = NVE4_PM_QUERY(0) q-type = NVE4_PM_QUERY_LAST) {
- return nve4_mp_pm_query_result(nvc0, q, result, wait);
+ if ((q-type = NVE4_PM_QUERY(0) q-type = NVE4_PM_QUERY_LAST) ||
+ (q-type = NVC0_PM_QUERY(0) q-type = NVC0_PM_QUERY_LAST)) {
+ return nvc0_mp_pm_query_result(nvc0, q, result, wait);
}
if (q-state != NVC0_QUERY_STATE_READY)
@@ -649,7 +667,7 @@ static const char *nvc0_drv_stat_names[] =
#endif /* NOUVEAU_ENABLE_DRIVER_STATISTICS */
-/* === PERFORMANCE MONITORING COUNTERS === */
+/* === PERFORMANCE MONITORING COUNTERS for NVE4+ === */
/* Code to read out MP counters: They are accessible via mmio, too, but let's
* just avoid mapping
Mesa (master): nvc0: don' t access array out of bounds on unexpected sample count
Module: Mesa Branch: master Commit: 2daf974cfe701f5955b96b51478ca545c4a5082c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2daf974cfe701f5955b96b51478ca545c4a5082c Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Tue Aug 6 22:20:25 2013 +0200 nvc0: don't access array out of bounds on unexpected sample count --- src/gallium/drivers/nvc0/nvc0_context.c |3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nvc0/nvc0_context.c b/src/gallium/drivers/nvc0/nvc0_context.c index 69e1970..5da491f 100644 --- a/src/gallium/drivers/nvc0/nvc0_context.c +++ b/src/gallium/drivers/nvc0/nvc0_context.c @@ -394,8 +394,7 @@ nvc0_context_get_sample_position(struct pipe_context *pipe, case 8: ptr = ms8; break; default: assert(0); - ptr = ms1; - break; + return; /* bad sample count - undefined locations */ } xy[0] = ptr[sample_index][0] * 0.0625f; xy[1] = ptr[sample_index][1] * 0.0625f; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nvc0: properly align NVE4_COMPUTE_MP_TEMP_SIZE
Module: Mesa Branch: master Commit: ef6d5ee9f34bce89c8bb8ff001be4c70a2a5421d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef6d5ee9f34bce89c8bb8ff001be4c70a2a5421d Author: Samuel Pitoiset samuel.pitoi...@gmail.com Date: Thu Jul 25 10:35:33 2013 +0200 nvc0: properly align NVE4_COMPUTE_MP_TEMP_SIZE MP_TEMP_SIZE must be aligned to 0x8000, while TEMP_SIZE on NVE4_3D must be aligned to 0x2, so perform both alignments to be sure we allocate enough space (actually the bo will most likely use 128 KiB pages and not aligning to that would be a waste anyway). Cc: 9.2 mesa-sta...@lists.freedesktop.org --- src/gallium/drivers/nvc0/nvc0_screen.c |1 + src/gallium/drivers/nvc0/nve4_compute.c |4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nvc0/nvc0_screen.c b/src/gallium/drivers/nvc0/nvc0_screen.c index 201d12f..171a302 100644 --- a/src/gallium/drivers/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nvc0/nvc0_screen.c @@ -512,6 +512,7 @@ nvc0_screen_resize_tls_area(struct nvc0_screen *screen, } size *= (screen-base.device-chipset = 0xe0) ? 64 : 48; /* max warps */ + size = align(size, 0x8000); size *= screen-mp_count; size = align(size, 1 17); diff --git a/src/gallium/drivers/nvc0/nve4_compute.c b/src/gallium/drivers/nvc0/nve4_compute.c index 258564b..abadd60 100644 --- a/src/gallium/drivers/nvc0/nve4_compute.c +++ b/src/gallium/drivers/nvc0/nve4_compute.c @@ -78,11 +78,11 @@ nve4_screen_compute_setup(struct nvc0_screen *screen, */ BEGIN_NVC0(push, NVE4_COMPUTE(MP_TEMP_SIZE_HIGH(0)), 3); PUSH_DATAh(push, screen-tls-size / screen-mp_count); - PUSH_DATA (push, screen-tls-size / screen-mp_count); + PUSH_DATA (push, (screen-tls-size / screen-mp_count) ~0x7fff); PUSH_DATA (push, 0xff); BEGIN_NVC0(push, NVE4_COMPUTE(MP_TEMP_SIZE_HIGH(1)), 3); PUSH_DATAh(push, screen-tls-size / screen-mp_count); - PUSH_DATA (push, screen-tls-size / screen-mp_count); + PUSH_DATA (push, (screen-tls-size / screen-mp_count) ~0x7fff); PUSH_DATA (push, 0xff); /* Unified address space ? Who needs that ? Certainly not OpenCL. ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (9.1): nv50,nvc0: s/uint16/uint32 for constant buffer offset
Module: Mesa
Branch: 9.1
Commit: 5f420477f089ef04f9126bdee869084fc8fc9e41
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f420477f089ef04f9126bdee869084fc8fc9e41
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Wed Jul 24 20:41:31 2013 +0200
nv50,nvc0: s/uint16/uint32 for constant buffer offset
Looks like a thinko, Hey, constant buffers can be at most 64 KiB
in size, offset can't be larger. But it can, of course.
I think piglit lacks a test for UBO and BindBufferRange that
tests if it actually works.
---
src/gallium/drivers/nv50/nv50_stateobj.h |2 +-
src/gallium/drivers/nvc0/nvc0_stateobj.h |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_stateobj.h
b/src/gallium/drivers/nv50/nv50_stateobj.h
index f75608c..37b9967 100644
--- a/src/gallium/drivers/nv50/nv50_stateobj.h
+++ b/src/gallium/drivers/nv50/nv50_stateobj.h
@@ -40,7 +40,7 @@ struct nv50_constbuf {
const uint8_t *data;
} u;
uint32_t size; /* max 65536 */
- uint16_t offset;
+ uint32_t offset;
boolean user; /* should only be TRUE if u.data is valid and non-NULL */
};
diff --git a/src/gallium/drivers/nvc0/nvc0_stateobj.h
b/src/gallium/drivers/nvc0/nvc0_stateobj.h
index edab60b..80c3342 100644
--- a/src/gallium/drivers/nvc0/nvc0_stateobj.h
+++ b/src/gallium/drivers/nvc0/nvc0_stateobj.h
@@ -38,7 +38,7 @@ struct nvc0_constbuf {
const void *data;
} u;
uint32_t size;
- uint16_t offset;
+ uint32_t offset;
boolean user; /* should only be TRUE if u.data is valid and non-NULL */
};
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Mesa (9.2): nv50,nvc0: s/uint16/uint32 for constant buffer offset
Module: Mesa
Branch: 9.2
Commit: 9b8ad643629fad1724e01c8fbb3289e43d42e1c1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b8ad643629fad1724e01c8fbb3289e43d42e1c1
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Wed Jul 24 20:41:31 2013 +0200
nv50,nvc0: s/uint16/uint32 for constant buffer offset
Looks like a thinko, Hey, constant buffers can be at most 64 KiB
in size, offset can't be larger. But it can, of course.
I think piglit lacks a test for UBO and BindBufferRange that
tests if it actually works.
---
src/gallium/drivers/nv50/nv50_stateobj.h |2 +-
src/gallium/drivers/nvc0/nvc0_stateobj.h |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_stateobj.h
b/src/gallium/drivers/nv50/nv50_stateobj.h
index f75608c..37b9967 100644
--- a/src/gallium/drivers/nv50/nv50_stateobj.h
+++ b/src/gallium/drivers/nv50/nv50_stateobj.h
@@ -40,7 +40,7 @@ struct nv50_constbuf {
const uint8_t *data;
} u;
uint32_t size; /* max 65536 */
- uint16_t offset;
+ uint32_t offset;
boolean user; /* should only be TRUE if u.data is valid and non-NULL */
};
diff --git a/src/gallium/drivers/nvc0/nvc0_stateobj.h
b/src/gallium/drivers/nvc0/nvc0_stateobj.h
index edab60b..80c3342 100644
--- a/src/gallium/drivers/nvc0/nvc0_stateobj.h
+++ b/src/gallium/drivers/nvc0/nvc0_stateobj.h
@@ -38,7 +38,7 @@ struct nvc0_constbuf {
const void *data;
} u;
uint32_t size;
- uint16_t offset;
+ uint32_t offset;
boolean user; /* should only be TRUE if u.data is valid and non-NULL */
};
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Mesa (master): nv50,nvc0: s/uint16/uint32 for constant buffer offset
Module: Mesa
Branch: master
Commit: 5c37039797938e43a7dfb6c7d39a1f0bb4f32df3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c37039797938e43a7dfb6c7d39a1f0bb4f32df3
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Wed Jul 24 20:41:31 2013 +0200
nv50,nvc0: s/uint16/uint32 for constant buffer offset
Looks like a thinko, Hey, constant buffers can be at most 64 KiB
in size, offset can't be larger. But it can, of course.
I think piglit lacks a test for UBO and BindBufferRange that
tests if it actually works.
---
src/gallium/drivers/nv50/nv50_stateobj.h |2 +-
src/gallium/drivers/nvc0/nvc0_stateobj.h |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_stateobj.h
b/src/gallium/drivers/nv50/nv50_stateobj.h
index f75608c..37b9967 100644
--- a/src/gallium/drivers/nv50/nv50_stateobj.h
+++ b/src/gallium/drivers/nv50/nv50_stateobj.h
@@ -40,7 +40,7 @@ struct nv50_constbuf {
const uint8_t *data;
} u;
uint32_t size; /* max 65536 */
- uint16_t offset;
+ uint32_t offset;
boolean user; /* should only be TRUE if u.data is valid and non-NULL */
};
diff --git a/src/gallium/drivers/nvc0/nvc0_stateobj.h
b/src/gallium/drivers/nvc0/nvc0_stateobj.h
index edab60b..80c3342 100644
--- a/src/gallium/drivers/nvc0/nvc0_stateobj.h
+++ b/src/gallium/drivers/nvc0/nvc0_stateobj.h
@@ -38,7 +38,7 @@ struct nvc0_constbuf {
const void *data;
} u;
uint32_t size;
- uint16_t offset;
+ uint32_t offset;
boolean user; /* should only be TRUE if u.data is valid and non-NULL */
};
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Mesa (master): nv50: avoid crash on updating RASTERIZE_ENABLE state
Module: Mesa
Branch: master
Commit: 7f7b05d6b324c15b6573dfe1e90d4d5cf416a59b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f7b05d6b324c15b6573dfe1e90d4d5cf416a59b
Author: Emil Velikov emil.l.veli...@gmail.com
Date: Wed Jun 19 00:02:24 2013 +0200
nv50: avoid crash on updating RASTERIZE_ENABLE state
When doing blit using the 3D engine, the rasterizer cso may be NULL.
Ported from nvc0 commit 8aa8b0539.
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
src/gallium/drivers/nv50/nv50_surface.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_surface.c
b/src/gallium/drivers/nv50/nv50_surface.c
index d6066f2..30dab0b 100644
--- a/src/gallium/drivers/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nv50/nv50_surface.c
@@ -458,6 +458,7 @@ struct nv50_blitctx
enum pipe_texture_target target;
struct {
struct pipe_framebuffer_state fb;
+ struct nv50_rasterizer_stateobj *rast;
struct nv50_program *vp;
struct nv50_program *gp;
struct nv50_program *fp;
@@ -467,6 +468,7 @@ struct nv50_blitctx
struct nv50_tsc_entry *sampler[2];
uint32_t dirty;
} saved;
+ struct nv50_rasterizer_stateobj rast;
};
static void
@@ -836,10 +838,14 @@ nv50_blitctx_pre_blit(struct nv50_blitctx *ctx)
ctx-saved.fb.cbufs[0] = nv50-framebuffer.cbufs[0];
ctx-saved.fb.zsbuf = nv50-framebuffer.zsbuf;
+ ctx-saved.rast = nv50-rast;
+
ctx-saved.vp = nv50-vertprog;
ctx-saved.gp = nv50-gmtyprog;
ctx-saved.fp = nv50-fragprog;
+ nv50-rast = ctx-rast;
+
nv50-vertprog = blitter-vp;
nv50-gmtyprog = NULL;
nv50-fragprog = ctx-fp;
@@ -884,6 +890,8 @@ nv50_blitctx_post_blit(struct nv50_blitctx *blit)
nv50-framebuffer.cbufs[0] = blit-saved.fb.cbufs[0];
nv50-framebuffer.zsbuf = blit-saved.fb.zsbuf;
+ nv50-rast = blit-saved.rast;
+
nv50-vertprog = blit-saved.vp;
nv50-gmtyprog = blit-saved.gp;
nv50-fragprog = blit-saved.fp;
@@ -1328,6 +1336,8 @@ nv50_blitctx_create(struct nv50_context *nv50)
nv50-blit-nv50 = nv50;
+ nv50-blit-rast.pipe.half_pixel_center = 1;
+
return TRUE;
}
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Mesa (master): nv50: set BORDER_COLOR_SRGB in sampler objects
Module: Mesa
Branch: master
Commit: 246ff8f887e10a2828fb43104a06ba6f2505b74d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=246ff8f887e10a2828fb43104a06ba6f2505b74d
Author: Christoph Bumiller christoph.bumil...@speed.at
Date: Sat Apr 13 15:04:55 2013 +0200
nv50: set BORDER_COLOR_SRGB in sampler objects
---
src/gallium/drivers/nv50/nv50_state.c | 30 +-
src/gallium/drivers/nv50/nv50_texture.xml.h | 24 ++---
2 files changed, 35 insertions(+), 19 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_state.c
b/src/gallium/drivers/nv50/nv50_state.c
index 819b0a2..cbde4b1 100644
--- a/src/gallium/drivers/nv50/nv50_state.c
+++ b/src/gallium/drivers/nv50/nv50_state.c
@@ -24,6 +24,7 @@
#include util/u_helpers.h
#include util/u_inlines.h
#include util/u_transfer.h
+#include util/u_format_srgb.h
#include tgsi/tgsi_parse.h
@@ -456,7 +457,7 @@ void *
nv50_sampler_state_create(struct pipe_context *pipe,
const struct pipe_sampler_state *cso)
{
- struct nv50_tsc_entry *so = CALLOC_STRUCT(nv50_tsc_entry);
+ struct nv50_tsc_entry *so = MALLOC_STRUCT(nv50_tsc_entry);
float f[2];
so-id = -1;
@@ -466,20 +467,13 @@ nv50_sampler_state_create(struct pipe_context *pipe,
(nv50_tsc_wrap_mode(cso-wrap_t) 3) |
(nv50_tsc_wrap_mode(cso-wrap_r) 6));
- if (nouveau_screen(pipe-screen)-class_3d = NVE4_3D_CLASS) {
- if (cso-seamless_cube_map)
- so-tsc[1] |= NVE4_TSC_1_CUBE_SEAMLESS;
- if (!cso-normalized_coords)
- so-tsc[1] |= NVE4_TSC_1_FORCE_NONNORMALIZED_COORDS;
- }
-
switch (cso-mag_img_filter) {
case PIPE_TEX_FILTER_LINEAR:
- so-tsc[1] |= NV50_TSC_1_MAGF_LINEAR;
+ so-tsc[1] = NV50_TSC_1_MAGF_LINEAR;
break;
case PIPE_TEX_FILTER_NEAREST:
default:
- so-tsc[1] |= NV50_TSC_1_MAGF_NEAREST;
+ so-tsc[1] = NV50_TSC_1_MAGF_NEAREST;
break;
}
@@ -506,6 +500,13 @@ nv50_sampler_state_create(struct pipe_context *pipe,
break;
}
+ if (nouveau_screen(pipe-screen)-class_3d = NVE4_3D_CLASS) {
+ if (cso-seamless_cube_map)
+ so-tsc[1] |= NVE4_TSC_1_CUBE_SEAMLESS;
+ if (!cso-normalized_coords)
+ so-tsc[1] |= NVE4_TSC_1_FORCE_NONNORMALIZED_COORDS;
+ }
+
if (cso-max_anisotropy = 16)
so-tsc[0] |= (7 20);
else
@@ -532,9 +533,16 @@ nv50_sampler_state_create(struct pipe_context *pipe,
f[0] = CLAMP(cso-min_lod, 0.0f, 15.0f);
f[1] = CLAMP(cso-max_lod, 0.0f, 15.0f);
- so-tsc[2] |=
+ so-tsc[2] =
(((int)(f[1] * 256.0f) 0xfff) 12) | ((int)(f[0] * 256.0f) 0xfff);
+ so-tsc[2] |=
+ util_format_linear_float_to_srgb_8unorm(cso-border_color.f[0]) 24;
+ so-tsc[3] =
+ util_format_linear_float_to_srgb_8unorm(cso-border_color.f[1]) 12;
+ so-tsc[3] |=
+ util_format_linear_float_to_srgb_8unorm(cso-border_color.f[2]) 20;
+
so-tsc[4] = fui(cso-border_color.f[0]);
so-tsc[5] = fui(cso-border_color.f[1]);
so-tsc[6] = fui(cso-border_color.f[2]);
diff --git a/src/gallium/drivers/nv50/nv50_texture.xml.h
b/src/gallium/drivers/nv50/nv50_texture.xml.h
index 63daf9e..31eab9b 100644
--- a/src/gallium/drivers/nv50/nv50_texture.xml.h
+++ b/src/gallium/drivers/nv50/nv50_texture.xml.h
@@ -1,5 +1,5 @@
-#ifndef RNNDB_NV50_TEXTURE_XML
-#define RNNDB_NV50_TEXTURE_XML
+#ifndef NV50_TEXTURE_XML
+#define NV50_TEXTURE_XML
/* Autogenerated file, DO NOT EDIT manually!
@@ -8,12 +8,12 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- rnndb/nv50_texture.xml ( 8180 bytes, from 2012-07-31 11:07:50)
-- ./rnndb/copyright.xml ( 6452 bytes, from 2011-07-10 21:35:25)
-- ./rnndb/nvchipsets.xml ( 3736 bytes, from 2012-07-31 11:01:16)
-- ./rnndb/nv50_defs.xml ( 5468 bytes, from 2011-07-10 21:35:25)
+- rnndb/nv50_texture.xml ( 8648 bytes, from 2013-04-13 12:49:11)
+- rnndb/copyright.xml( 6452 bytes, from 2011-08-11 18:25:12)
+- rnndb/nvchipsets.xml ( 3954 bytes, from 2013-03-26 01:26:43)
+- rnndb/nv50_defs.xml( 16652 bytes, from 2013-04-04 10:57:15)
-Copyright (C) 2006-2012 by the following authors:
+Copyright (C) 2006-2013 by the following authors:
- Artur Huillet arthur.huil...@free.fr (ahuillet)
- Ben Skeggs (darktama, darktama_)
- B. R. koala...@users.sourceforge.net (koala_br)
@@ -277,6 +277,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
#define NV50_TSC_2_MIN_LOD__SHIFT 0
#define NV50_TSC_2_MAX_LOD__MASK 0x00fff000
#define NV50_TSC_2_MAX_LOD__SHIFT 12
+#define NV50_TSC_2_BORDER_COLOR_SRGB_RED__MASK 0xff00
+#define NV50_TSC_2_BORDER_COLOR_SRGB_RED__SHIFT24
+
+#define NV50_TSC_3 0x000c
+#define
Mesa (master): nv50: fix 4th component of Lx_SINT/UINT formats
Module: Mesa Branch: master Commit: 2d5d054752fc7885d1dd4fedfd90888e66bd8d34 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d5d054752fc7885d1dd4fedfd90888e66bd8d34 Author: Christoph Bumiller christoph.bumil...@speed.at Date: Fri Apr 12 19:11:30 2013 +0200 nv50: fix 4th component of Lx_SINT/UINT formats --- src/gallium/drivers/nv50/nv50_formats.c | 12 ++-- 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/nv50/nv50_formats.c b/src/gallium/drivers/nv50/nv50_formats.c index 35623aa..66d9bbf 100644 --- a/src/gallium/drivers/nv50/nv50_formats.c +++ b/src/gallium/drivers/nv50/nv50_formats.c @@ -207,16 +207,16 @@ const struct nv50_format nv50_format_table[PIPE_FORMAT_COUNT] = F3B(L8_UNORM, R8_UNORM, C0, C0, C0, xx, UNORM, 8, TB), F3B(L8_SRGB, R8_UNORM, C0, C0, C0, xx, UNORM, 8, TB), F3B(L8_SNORM, R8_SNORM, C0, C0, C0, xx, SNORM, 8, TC), - F3B(L8_SINT, R8_SINT, C0, C0, C0, xx, SINT, 8, TR), - F3B(L8_UINT, R8_UINT, C0, C0, C0, xx, UINT, 8, TR), + I3B(L8_SINT, R8_SINT, C0, C0, C0, xx, SINT, 8, TR), + I3B(L8_UINT, R8_UINT, C0, C0, C0, xx, UINT, 8, TR), F3B(L16_UNORM, R16_UNORM, C0, C0, C0, xx, UNORM, 16, TC), F3B(L16_SNORM, R16_SNORM, C0, C0, C0, xx, SNORM, 16, TC), F3B(L16_FLOAT, R16_FLOAT, C0, C0, C0, xx, FLOAT, 16, TB), - F3B(L16_SINT, R16_SINT, C0, C0, C0, xx, SINT, 16, TR), - F3B(L16_UINT, R16_UINT, C0, C0, C0, xx, UINT, 16, TR), + I3B(L16_SINT, R16_SINT, C0, C0, C0, xx, SINT, 16, TR), + I3B(L16_UINT, R16_UINT, C0, C0, C0, xx, UINT, 16, TR), F3B(L32_FLOAT, R32_FLOAT, C0, C0, C0, xx, FLOAT, 32, TB), - F3B(L32_SINT, R32_SINT, C0, C0, C0, xx, SINT, 32, TR), - F3B(L32_UINT, R32_UINT, C0, C0, C0, xx, UINT, 32, TR), + I3B(L32_SINT, R32_SINT, C0, C0, C0, xx, SINT, 32, TR), + I3B(L32_UINT, R32_UINT, C0, C0, C0, xx, UINT, 32, TR), C4B(I8_UNORM, R8_UNORM, C0, C0, C0, C0, UNORM, 8, TR), C4B(I8_SNORM, R8_SNORM, C0, C0, C0, C0, SNORM, 8, TR), ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): st/mesa: optionally apply texture swizzle to border color v2
Module: Mesa
Branch: master
Commit: 729abfd0f53c27ba58da95882bef985945933c65
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=729abfd0f53c27ba58da95882bef985945933c65
Author: Christoph Bumiller christoph.bumil...@speed.at
Date: Fri Apr 12 13:42:01 2013 +0200
st/mesa: optionally apply texture swizzle to border color v2
This is the only sane solution for nv50 and nvc0 (really, trust me),
but since on other hardware the border colour is tightly coupled with
texture state they'd have to undo the swizzle, so I've added a cap.
The dependency of update_sampler on the texture updates was
introduced to avoid doing the apply_depthmode to the swizzle twice.
v2: Moved swizzling helper to u_format.c, extended the CAP to
provide more accurate information.
---
src/gallium/auxiliary/util/u_format.c| 34 ++
src/gallium/auxiliary/util/u_format.h| 12
src/gallium/docs/source/cso/sampler.rst |6 ++-
src/gallium/docs/source/screen.rst | 11 +++
src/gallium/drivers/freedreno/freedreno_screen.c |1 +
src/gallium/drivers/i915/i915_screen.c |1 +
src/gallium/drivers/llvmpipe/lp_screen.c |2 +
src/gallium/drivers/nv30/nv30_screen.c |1 +
src/gallium/drivers/nv50/nv50_screen.c |2 +
src/gallium/drivers/nvc0/nvc0_screen.c |2 +
src/gallium/drivers/r300/r300_screen.c |1 +
src/gallium/drivers/r600/r600_pipe.c |3 ++
src/gallium/drivers/radeonsi/radeonsi_pipe.c |1 +
src/gallium/drivers/softpipe/sp_screen.c |2 +
src/gallium/drivers/svga/svga_screen.c |2 +
src/gallium/include/pipe/p_defines.h |7 -
src/mesa/state_tracker/st_atom.c |2 +-
src/mesa/state_tracker/st_atom_sampler.c | 27 +++--
src/mesa/state_tracker/st_context.c |4 ++
src/mesa/state_tracker/st_context.h |1 +
20 files changed, 115 insertions(+), 7 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_format.c
b/src/gallium/auxiliary/util/u_format.c
index 1845637..9bdc2ea 100644
--- a/src/gallium/auxiliary/util/u_format.c
+++ b/src/gallium/auxiliary/util/u_format.c
@@ -632,6 +632,40 @@ void util_format_compose_swizzles(const unsigned char
swz1[4],
}
}
+void util_format_apply_color_swizzle(union pipe_color_union *dst,
+ const union pipe_color_union *src,
+ const unsigned char swz[4],
+ const boolean is_integer)
+{
+ unsigned c;
+
+ if (is_integer) {
+ for (c = 0; c 4; ++c) {
+ switch (swz[c]) {
+ case PIPE_SWIZZLE_RED: dst-ui[c] = src-ui[0]; break;
+ case PIPE_SWIZZLE_GREEN: dst-ui[c] = src-ui[1]; break;
+ case PIPE_SWIZZLE_BLUE: dst-ui[c] = src-ui[2]; break;
+ case PIPE_SWIZZLE_ALPHA: dst-ui[c] = src-ui[3]; break;
+ default:
+dst-ui[c] = (swz[c] == PIPE_SWIZZLE_ONE) ? 1 : 0;
+break;
+ }
+ }
+ } else {
+ for (c = 0; c 4; ++c) {
+ switch (swz[c]) {
+ case PIPE_SWIZZLE_RED: dst-f[c] = src-f[0]; break;
+ case PIPE_SWIZZLE_GREEN: dst-f[c] = src-f[1]; break;
+ case PIPE_SWIZZLE_BLUE: dst-f[c] = src-f[2]; break;
+ case PIPE_SWIZZLE_ALPHA: dst-f[c] = src-f[3]; break;
+ default:
+dst-f[c] = (swz[c] == PIPE_SWIZZLE_ONE) ? 1.0f : 0.0f;
+break;
+ }
+ }
+ }
+}
+
void util_format_swizzle_4f(float *dst, const float *src,
const unsigned char swz[4])
{
diff --git a/src/gallium/auxiliary/util/u_format.h
b/src/gallium/auxiliary/util/u_format.h
index ed942fb..e4b9c36 100644
--- a/src/gallium/auxiliary/util/u_format.h
+++ b/src/gallium/auxiliary/util/u_format.h
@@ -33,6 +33,9 @@
#include pipe/p_format.h
#include util/u_debug.h
+union pipe_color_union;
+
+
#ifdef __cplusplus
extern C {
#endif
@@ -1117,6 +1120,15 @@ void util_format_compose_swizzles(const unsigned char
swz1[4],
const unsigned char swz2[4],
unsigned char dst[4]);
+/* Apply the swizzle provided in \param swz (which is one of PIPE_SWIZZLE_x)
+ * to \param src and store the result in \param dst.
+ * \param is_integer determines the value written for PIPE_SWIZZLE_ONE.
+ */
+void util_format_apply_color_swizzle(union pipe_color_union *dst,
+ const union pipe_color_union *src,
+ const unsigned char swz[4],
+ const boolean is_integer);
+
void util_format_swizzle_4f(float *dst, const float *src,
const unsigned char swz[4]);
diff --git a/src/gallium/docs/source/cso/sampler.rst
b/src/gallium/docs/source/cso/sampler.rst
index 26ffc18..9959793
Mesa (master): nv50: add remaining RGBX formats
Module: Mesa Branch: master Commit: 78eaaff696b34ebd4b13466c1eb75295e88eeb53 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=78eaaff696b34ebd4b13466c1eb75295e88eeb53 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Thu Apr 18 20:55:32 2013 +0200 nv50: add remaining RGBX formats Not all are supported as render targets. The state tracker fallback of using RGBA instead of RGBX currently fails for blending, we could work around this by clearing their alpha to 1 and modifying the color mask to disable writing alpha. --- src/gallium/drivers/nv50/nv50_formats.c | 16 1 files changed, 12 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/nv50/nv50_formats.c b/src/gallium/drivers/nv50/nv50_formats.c index 66d9bbf..1ec41f9 100644 --- a/src/gallium/drivers/nv50/nv50_formats.c +++ b/src/gallium/drivers/nv50/nv50_formats.c @@ -176,6 +176,7 @@ const struct nv50_format nv50_format_table[PIPE_FORMAT_COUNT] = C4A(R8G8B8A8_UNORM, RGBA8_UNORM, C0, C1, C2, C3, UNORM, 8_8_8_8, IBV, 0), F3A(R8G8B8X8_UNORM, RGBX8_UNORM, C0, C1, C2, xx, UNORM, 8_8_8_8, TB), C4A(R8G8B8A8_SRGB, RGBA8_SRGB, C0, C1, C2, C3, UNORM, 8_8_8_8, TB, 0), + F3B(R8G8B8X8_SRGB, RGBX8_SRGB, C0, C1, C2, xx, UNORM, 8_8_8_8, TB), ZXB(Z16_UNORM, Z16_UNORM, C0, C0, C0, xx, UNORM, Z16, TZ), ZXB(Z32_FLOAT, Z32_FLOAT, C0, C0, C0, xx, FLOAT, Z32, TZ), @@ -279,14 +280,15 @@ const struct nv50_format nv50_format_table[PIPE_FORMAT_COUNT] = C4A(R32G32B32A32_FLOAT, RGBA32_FLOAT, C0, C1, C2, C3, FLOAT, 32_32_32_32, IBV, 0), - F3B(R32G32B32X32_FLOAT, RGBX32_FLOAT, C0, C1, C2, xx, FLOAT, 32_32_32_32, - TB), C4A(R32G32B32A32_UNORM, NONE, C0, C1, C2, C3, UNORM, 32_32_32_32, TV, 0), C4A(R32G32B32A32_SNORM, NONE, C0, C1, C2, C3, SNORM, 32_32_32_32, TV, 0), C4A(R32G32B32A32_SINT, RGBA32_SINT, C0, C1, C2, C3, SINT, 32_32_32_32, IRV, 0), C4A(R32G32B32A32_UINT, RGBA32_UINT, C0, C1, C2, C3, UINT, 32_32_32_32, IRV, 0), + F3B(R32G32B32X32_FLOAT, RGBX32_FLOAT, C0, C1, C2, xx, FLOAT, 32_32_32_32, TB), + I3B(R32G32B32X32_SINT, RGBX32_SINT, C0, C1, C2, xx, SINT, 32_32_32_32, TR), + I3B(R32G32B32X32_UINT, RGBX32_UINT, C0, C1, C2, xx, UINT, 32_32_32_32, TR), F2A(R32G32_FLOAT, RG32_FLOAT, C0, C1, xx, xx, FLOAT, 32_32, IBV), F2A(R32G32_UNORM, NONE, C0, C1, xx, xx, UNORM, 32_32, TV), @@ -302,8 +304,6 @@ const struct nv50_format nv50_format_table[PIPE_FORMAT_COUNT] = C4A(R16G16B16A16_FLOAT, RGBA16_FLOAT, C0, C1, C2, C3, FLOAT, 16_16_16_16, IBV, 0), - F3B(R16G16B16X16_FLOAT, RGBX16_FLOAT, C0, C1, C2, xx, FLOAT, 16_16_16_16, - TB), C4A(R16G16B16A16_UNORM, RGBA16_UNORM, C0, C1, C2, C3, UNORM, 16_16_16_16, ICV, 0), C4A(R16G16B16A16_SNORM, RGBA16_SNORM, C0, C1, C2, C3, SNORM, 16_16_16_16, @@ -312,6 +312,11 @@ const struct nv50_format nv50_format_table[PIPE_FORMAT_COUNT] = IRV, 0), C4A(R16G16B16A16_UINT, RGBA16_UINT, C0, C1, C2, C3, UINT, 16_16_16_16, IRV, 0), + F3B(R16G16B16X16_FLOAT, RGBX16_FLOAT, C0, C1, C2, xx, FLOAT, 16_16_16_16, TB), + F3B(R16G16B16X16_UNORM, RGBA16_UNORM, C0, C1, C2, xx, UNORM, 16_16_16_16, T), + F3B(R16G16B16X16_SNORM, RGBA16_SNORM, C0, C1, C2, xx, SNORM, 16_16_16_16, T), + I3B(R16G16B16X16_SINT, RGBA16_SINT, C0, C1, C2, xx, SINT, 16_16_16_16, T), + I3B(R16G16B16X16_UINT, RGBA16_UINT, C0, C1, C2, xx, UINT, 16_16_16_16, T), F2A(R16G16_FLOAT, RG16_FLOAT, C0, C1, xx, xx, FLOAT, 16_16, IBV), F2A(R16G16_UNORM, RG16_UNORM, C0, C1, xx, xx, UNORM, 16_16, ICV), @@ -328,6 +333,9 @@ const struct nv50_format nv50_format_table[PIPE_FORMAT_COUNT] = C4A(R8G8B8A8_SNORM, RGBA8_SNORM, C0, C1, C2, C3, SNORM, 8_8_8_8, ICV, 0), C4A(R8G8B8A8_SINT, RGBA8_SINT, C0, C1, C2, C3, SINT, 8_8_8_8, IRV, 0), C4A(R8G8B8A8_UINT, RGBA8_UINT, C0, C1, C2, C3, UINT, 8_8_8_8, IRV, 0), + F3B(R8G8B8X8_SNORM, RGBA8_SNORM, C0, C1, C2, xx, SNORM, 8_8_8_8, T), + I3B(R8G8B8X8_SINT, RGBA8_SINT, C0, C1, C2, xx, SINT, 8_8_8_8, T), + I3B(R8G8B8X8_UINT, RGBA8_UINT, C0, C1, C2, xx, UINT, 8_8_8_8, T), F2A(R8G8_UNORM, RG8_UNORM, C0, C1, xx, xx, UNORM, 8_8, IBV), F2A(R8G8_SNORM, RG8_SNORM, C0, C1, xx, xx, SNORM, 8_8, ICV), ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nv50,nvc0: add RGBX16/32_FLOAT formats
Module: Mesa Branch: master Commit: 69804c2ab89d2b3633f90ee9d7a4688a33e1800b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=69804c2ab89d2b3633f90ee9d7a4688a33e1800b Author: Christoph Bumiller christoph.bumil...@speed.at Date: Mon Apr 8 13:47:26 2013 +0200 nv50,nvc0: add RGBX16/32_FLOAT formats --- src/gallium/drivers/nv50/nv50_formats.c |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/gallium/drivers/nv50/nv50_formats.c b/src/gallium/drivers/nv50/nv50_formats.c index 2f29ad8..35623aa 100644 --- a/src/gallium/drivers/nv50/nv50_formats.c +++ b/src/gallium/drivers/nv50/nv50_formats.c @@ -279,6 +279,8 @@ const struct nv50_format nv50_format_table[PIPE_FORMAT_COUNT] = C4A(R32G32B32A32_FLOAT, RGBA32_FLOAT, C0, C1, C2, C3, FLOAT, 32_32_32_32, IBV, 0), + F3B(R32G32B32X32_FLOAT, RGBX32_FLOAT, C0, C1, C2, xx, FLOAT, 32_32_32_32, + TB), C4A(R32G32B32A32_UNORM, NONE, C0, C1, C2, C3, UNORM, 32_32_32_32, TV, 0), C4A(R32G32B32A32_SNORM, NONE, C0, C1, C2, C3, SNORM, 32_32_32_32, TV, 0), C4A(R32G32B32A32_SINT, RGBA32_SINT, C0, C1, C2, C3, SINT, 32_32_32_32, @@ -300,6 +302,8 @@ const struct nv50_format nv50_format_table[PIPE_FORMAT_COUNT] = C4A(R16G16B16A16_FLOAT, RGBA16_FLOAT, C0, C1, C2, C3, FLOAT, 16_16_16_16, IBV, 0), + F3B(R16G16B16X16_FLOAT, RGBX16_FLOAT, C0, C1, C2, xx, FLOAT, 16_16_16_16, + TB), C4A(R16G16B16A16_UNORM, RGBA16_UNORM, C0, C1, C2, C3, UNORM, 16_16_16_16, ICV, 0), C4A(R16G16B16A16_SNORM, RGBA16_SNORM, C0, C1, C2, C3, SNORM, 16_16_16_16, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nvc0: fix 2D engine MS2 resolve
Module: Mesa
Branch: master
Commit: 2b62ba7cb0e69cae721545e8775193f87955dec8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b62ba7cb0e69cae721545e8775193f87955dec8
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Sat Apr 6 14:15:54 2013 +0200
nvc0: fix 2D engine MS2 resolve
---
src/gallium/drivers/nvc0/nvc0_surface.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_surface.c
b/src/gallium/drivers/nvc0/nvc0_surface.c
index 3abf717..4e8bb36 100644
--- a/src/gallium/drivers/nvc0/nvc0_surface.c
+++ b/src/gallium/drivers/nvc0/nvc0_surface.c
@@ -1038,8 +1038,8 @@ nvc0_blit_eng2d(struct nvc0_context *nvc0, const struct
pipe_blit_info *info)
if (src-base.base.nr_samples dst-base.base.nr_samples) {
/* center src coorinates for proper MS resolve filtering */
- srcx += (int64_t)src-ms_x 32;
- srcy += (int64_t)src-ms_y 32;
+ srcx += (int64_t)(src-ms_x + 0) 32;
+ srcy += (int64_t)(src-ms_y + 1) 31;
}
dstx = info-dst.box.x dst-ms_x;
___
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mesa-commit@lists.freedesktop.org
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Mesa (master): nvc0: patch up TEX cases with 5 or 6 sources on nve4
Module: Mesa
Branch: master
Commit: 71c1c8a9b89ca1ecca1857c53cd8c648c9c9a871
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=71c1c8a9b89ca1ecca1857c53cd8c648c9c9a871
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Sat Apr 6 17:40:02 2013 +0200
nvc0: patch up TEX cases with 5 or 6 sources on nve4
Hackishly fixes alignment requirement of 2nd tuple for now.
---
.../drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp | 20 +++-
1 files changed, 19 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
b/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
index 5f0f2e7..c459d60 100644
--- a/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
@@ -728,13 +728,31 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
if (i-tex.useOffsets) {
uint32_t value = 0;
int n, c;
- int s = i-srcCount(0xff);
+ int s = i-srcCount(0xff, true);
+ if (i-srcExists(s)) // move potential predicate out of the way
+ i-moveSources(s, 1);
for (n = 0; n i-tex.useOffsets; ++n)
for (c = 0; c 3; ++c)
value |= (i-tex.offset[n][c] 0xf) (n * 12 + c * 4);
i-setSrc(s, bld.loadImm(NULL, value));
}
+ if (prog-getTarget()-getChipset() = NVISA_GK104_CHIPSET) {
+ //
+ // If TEX requires more than 4 sources, the 2nd register tuple must be
+ // aligned to 4, even if it consists of just a single 4-byte register.
+ //
+ // XXX HACK: We insert 0 sources to avoid the 5 or 6 regs case.
+ //
+ int s = i-srcCount(0xff, true);
+ if (s 4 s 7) {
+ if (i-srcExists(s)) // move potential predicate out of the way
+i-moveSources(s, 7 - s);
+ while (s 7)
+i-setSrc(s++, bld.loadImm(NULL, 0));
+ }
+ }
+
return true;
}
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Mesa (master): nvc0: implement multisample textures
Module: Mesa
Branch: master
Commit: 4da54c91d24da891c56957f29274e7821c8254f6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4da54c91d24da891c56957f29274e7821c8254f6
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Sat Apr 6 14:52:05 2013 +0200
nvc0: implement multisample textures
---
src/gallium/drivers/nv50/codegen/nv50_ir.h |2 +
.../drivers/nv50/codegen/nv50_ir_from_tgsi.cpp | 26 +---
src/gallium/drivers/nv50/nv50_resource.h |1 +
src/gallium/drivers/nv50/nv50_surface.c|1 +
.../drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp |5 +-
src/gallium/drivers/nvc0/nvc0_context.c| 46
src/gallium/drivers/nvc0/nvc0_miptree.c|2 +
src/gallium/drivers/nvc0/nvc0_screen.c |2 +-
src/gallium/drivers/nvc0/nvc0_surface.c|1 +
src/gallium/drivers/nvc0/nvc0_tex.c| 36 +---
10 files changed, 97 insertions(+), 25 deletions(-)
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir.h
b/src/gallium/drivers/nv50/codegen/nv50_ir.h
index 236673c..ae365af 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir.h
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir.h
@@ -824,6 +824,8 @@ public:
int isArray() const { return descTable[target].array ? 1 : 0; }
int isCube() const { return descTable[target].cube ? 1 : 0; }
int isShadow() const { return descTable[target].shadow ? 1 : 0; }
+ int isMS() const {
+return target == TEX_TARGET_2D_MS || target == TEX_TARGET_2D_MS_ARRAY;
}
Target operator=(TexTarget targ)
{
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
b/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
index b546429..6897691 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
@@ -358,11 +358,13 @@ static nv50_ir::TexTarget translateTexture(uint tex)
switch (tex) {
NV50_IR_TEX_TARG_CASE(1D, 1D);
NV50_IR_TEX_TARG_CASE(2D, 2D);
+ NV50_IR_TEX_TARG_CASE(2D_MSAA, 2D_MS);
NV50_IR_TEX_TARG_CASE(3D, 3D);
NV50_IR_TEX_TARG_CASE(CUBE, CUBE);
NV50_IR_TEX_TARG_CASE(RECT, RECT);
NV50_IR_TEX_TARG_CASE(1D_ARRAY, 1D_ARRAY);
NV50_IR_TEX_TARG_CASE(2D_ARRAY, 2D_ARRAY);
+ NV50_IR_TEX_TARG_CASE(2D_ARRAY_MSAA, 2D_MS_ARRAY);
NV50_IR_TEX_TARG_CASE(CUBE_ARRAY, CUBE_ARRAY);
NV50_IR_TEX_TARG_CASE(SHADOW1D, 1D_SHADOW);
NV50_IR_TEX_TARG_CASE(SHADOW2D, 2D_SHADOW);
@@ -581,6 +583,8 @@ static nv50_ir::operation translateOpcode(uint opcode)
NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX);
NV50_IR_OPCODE_CASE(SAMPLE_D, TXD);
NV50_IR_OPCODE_CASE(SAMPLE_L, TXL);
+ NV50_IR_OPCODE_CASE(SAMPLE_I, TXF);
+ NV50_IR_OPCODE_CASE(SAMPLE_I_MS, TXF);
NV50_IR_OPCODE_CASE(GATHER4, TXG);
NV50_IR_OPCODE_CASE(SVIEWINFO, TXQ);
@@ -1134,7 +1138,7 @@ private:
// R,S,L,C,Dx,Dy encode TGSI sources for respective values (0xSf for auto)
void setTexRS(TexInstruction *, unsigned int s, int R, int S);
void handleTEX(Value *dst0[4], int R, int S, int L, int C, int Dx, int Dy);
- void handleTXF(Value *dst0[4], int R);
+ void handleTXF(Value *dst0[4], int R, int L_M);
void handleTXQ(Value *dst0[4], enum TexQuery);
void handleLIT(Value *dst0[4]);
void handleUserClipPlanes();
@@ -1689,25 +1693,29 @@ Converter::handleTEX(Value *dst[4], int R, int S, int
L, int C, int Dx, int Dy)
bb-insertTail(texi);
}
-// 1st source: xyz = coordinates, w = lod
+// 1st source: xyz = coordinates, w = lod/sample
// 2nd source: offset
void
-Converter::handleTXF(Value *dst[4], int R)
+Converter::handleTXF(Value *dst[4], int R, int L_M)
{
TexInstruction *texi = new_TexInstruction(func, tgsi.getOP());
+ int ms;
unsigned int c, d, s;
texi-tex.target = tgsi.getTexture(code, R);
+ ms = texi-tex.target.isMS() ? 1 : 0;
+ texi-tex.levelZero = ms; /* MS textures don't have mip-maps */
+
for (c = 0, d = 0; c 4; ++c) {
if (dst[c]) {
texi-setDef(d++, dst[c]);
texi-tex.mask |= 1 c;
}
}
- for (c = 0; c texi-tex.target.getArgCount(); ++c)
+ for (c = 0; c (texi-tex.target.getArgCount() - ms); ++c)
texi-setSrc(c, fetchSrc(0, c));
- texi-setSrc(c++, fetchSrc(0, 3)); // lod
+ texi-setSrc(c++, fetchSrc(L_M 4, L_M 3)); // lod or ms
setTexRS(texi, c, R, -1);
@@ -2392,7 +2400,13 @@ Converter::handleInstruction(const struct
tgsi_full_instruction *insn)
handleTEX(dst0, 1, 2, 0x30, 0x30, 0x30, 0x40);
break;
case TGSI_OPCODE_TXF:
- handleTXF(dst0, 1);
+ handleTXF(dst0, 1, 0x03);
+ break;
+ case TGSI_OPCODE_SAMPLE_I:
+ handleTXF(dst0, 1, 0x03);
+ break;
+ case TGSI_OPCODE_SAMPLE_I_MS:
+ handleTXF(dst0, 1, 0x20);
break;
case TGSI_OPCODE_TXQ:
case TGSI_OPCODE_SVIEWINFO:
diff --git a/src/gallium/drivers/nv50/nv50_resource.h
b/src/gallium
Mesa (master): nv50/codegen: do not emitATOM() if the subOp is unknown
Module: Mesa Branch: master Commit: 249f3d73cf5e9d22c592a619830a2f40912e6197 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=249f3d73cf5e9d22c592a619830a2f40912e6197 Author: Emil Velikov emil.l.veli...@gmail.com Date: Fri Apr 12 00:22:30 2013 +0100 nv50/codegen: do not emitATOM() if the subOp is unknown For debug build we'll hit the assert, for release we are going to emit random data as subOp is used uninitilised. Spotted by gcc codegen/nv50_ir_emit_nv50.cpp: In member function 'void nv50_ir::CodeEmitterNV50::emitATOM(const nv50_ir::Instruction*)': codegen/nv50_ir_emit_nv50.cpp:1554:12: warning: 'subOp' may be used uninitialized in this function [-Wmaybe-uninitialized] uint8_t subOp; ^ Signed-off-by: Emil Velikov emil.l.veli...@gmail.com --- .../drivers/nv50/codegen/nv50_ir_emit_nv50.cpp |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_emit_nv50.cpp b/src/gallium/drivers/nv50/codegen/nv50_ir_emit_nv50.cpp index 2638ef1..bc5a833 100644 --- a/src/gallium/drivers/nv50/codegen/nv50_ir_emit_nv50.cpp +++ b/src/gallium/drivers/nv50/codegen/nv50_ir_emit_nv50.cpp @@ -1565,7 +1565,7 @@ CodeEmitterNV50::emitATOM(const Instruction *i) case NV50_IR_SUBOP_ATOM_EXCH: subOp = 0x1; break; default: assert(!invalid subop); - break; + return; } code[0] = 0xd001; code[1] = 0xe0c0 | (subOp 2); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nvc0: compile nve4_cache_split_name() only in debug build
Module: Mesa
Branch: master
Commit: e28c266682fe8ac1c6ba27a90802974c05c35dde
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e28c266682fe8ac1c6ba27a90802974c05c35dde
Author: Emil Velikov emil.l.veli...@gmail.com
Date: Fri Apr 12 00:22:31 2013 +0100
nvc0: compile nve4_cache_split_name() only in debug build
As otherwise it is unused - pointed out by gcc
nve4_compute.c:586:20: warning: 'nve4_cache_split_name' defined but not used
[-Wunused-function]
static const char *nve4_cache_split_name(unsigned value)
^
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
src/gallium/drivers/nvc0/nve4_compute.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nve4_compute.c
b/src/gallium/drivers/nvc0/nve4_compute.c
index d7aa61e..2550530 100644
--- a/src/gallium/drivers/nvc0/nve4_compute.c
+++ b/src/gallium/drivers/nvc0/nve4_compute.c
@@ -583,6 +583,7 @@ nve4_compute_validate_textures(struct nvc0_context *nvc0)
}
+#ifdef DEBUG
static const char *nve4_cache_split_name(unsigned value)
{
switch (value) {
@@ -594,7 +595,6 @@ static const char *nve4_cache_split_name(unsigned value)
}
}
-#ifdef DEBUG
static void
nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *desc)
{
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Mesa (master): nvc0: bail out early during nve4_compute_setup()
Module: Mesa Branch: master Commit: 48bcb94dc375af17ceee14693c7cb3fdbb7e2151 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=48bcb94dc375af17ceee14693c7cb3fdbb7e2151 Author: Emil Velikov emil.l.veli...@gmail.com Date: Fri Apr 12 00:22:32 2013 +0100 nvc0: bail out early during nve4_compute_setup() Exit gracefully rather than trying to create a random object, whenever the chipset is unknown Signed-off-by: Emil Velikov emil.l.veli...@gmail.com --- src/gallium/drivers/nvc0/nve4_compute.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/gallium/drivers/nvc0/nve4_compute.c b/src/gallium/drivers/nvc0/nve4_compute.c index 2550530..7ea61e8 100644 --- a/src/gallium/drivers/nvc0/nve4_compute.c +++ b/src/gallium/drivers/nvc0/nve4_compute.c @@ -51,7 +51,7 @@ nve4_screen_compute_setup(struct nvc0_screen *screen, break; default: NOUVEAU_ERR(unsupported chipset: NV%02x\n, dev-chipset); - break; + return -1; } ret = nouveau_object_new(chan, 0xbeef00c0, obj_class, NULL, 0, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nvc0: set ret variable if launch desc allocation failed
Module: Mesa
Branch: master
Commit: ac1118d53c0b22db8dcd6fcdcd2d1a245037dbc1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac1118d53c0b22db8dcd6fcdcd2d1a245037dbc1
Author: Emil Velikov emil.l.veli...@gmail.com
Date: Fri Apr 12 00:22:33 2013 +0100
nvc0: set ret variable if launch desc allocation failed
Pointed out by gcc
nve4_compute.c: In function 'nve4_launch_grid':
nve4_compute.c:511:7: warning: 'ret' may be used uninitialized in
this function [-Wmaybe-uninitialized]
if (ret)
^
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
Edit by Christoph Bumiller:
Set it to -1 to indicate failure and only when it's actually required.
---
src/gallium/drivers/nvc0/nve4_compute.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nve4_compute.c
b/src/gallium/drivers/nvc0/nve4_compute.c
index 7ea61e8..106fb7a 100644
--- a/src/gallium/drivers/nvc0/nve4_compute.c
+++ b/src/gallium/drivers/nvc0/nve4_compute.c
@@ -469,8 +469,10 @@ nve4_launch_grid(struct pipe_context *pipe,
int ret;
desc = nve4_compute_alloc_launch_desc(nvc0-base, desc_bo, desc_gpuaddr);
- if (!desc)
+ if (!desc) {
+ ret = -1;
goto out;
+ }
BCTX_REFN_bo(nvc0-bufctx_cp, CP_DESC, NOUVEAU_BO_GART | NOUVEAU_BO_RD,
desc_bo);
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Mesa (master): gallium: add PIPE_CAP_QUERY_PIPELINE_STATISTICS
Module: Mesa Branch: master Commit: f35e96d973d57d314620509b2350ebb2bd3b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f35e96d973d57d314620509b2350ebb2bd3b Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Fri Mar 29 13:02:49 2013 +0100 gallium: add PIPE_CAP_QUERY_PIPELINE_STATISTICS Reviewed-by: Marek Olšák mar...@gmail.com --- src/gallium/docs/source/screen.rst |2 ++ src/gallium/drivers/freedreno/freedreno_screen.c |1 + src/gallium/drivers/i915/i915_screen.c |1 + src/gallium/drivers/llvmpipe/lp_screen.c |2 ++ src/gallium/drivers/nv30/nv30_screen.c |1 + src/gallium/drivers/nv50/nv50_screen.c |2 ++ src/gallium/drivers/nvc0/nvc0_screen.c |1 + src/gallium/drivers/r300/r300_screen.c |1 + src/gallium/drivers/r600/r600_pipe.c |1 + src/gallium/drivers/radeonsi/radeonsi_pipe.c |1 + src/gallium/drivers/softpipe/sp_screen.c |2 ++ src/gallium/include/pipe/p_defines.h |3 ++- 12 files changed, 17 insertions(+), 1 deletions(-) diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst index 8c7e86e..c1a3c0b 100644 --- a/src/gallium/docs/source/screen.rst +++ b/src/gallium/docs/source/screen.rst @@ -149,6 +149,8 @@ The integer capabilities: to use a blit to implement a texture transfer which needs format conversions and swizzling in state trackers. Generally, all hardware drivers with dedicated memory should return 1 and all software rasterizers should return 0. +* ``PIPE_CAP_QUERY_PIPELINE_STATISTICS``: Whether PIPE_QUERY_PIPELINE_STATISTICS + is supported. .. _pipe_capf: diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 79eef5e..283d07f 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -199,6 +199,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_VERTEX_COLOR_CLAMPED: case PIPE_CAP_USER_VERTEX_BUFFERS: case PIPE_CAP_USER_INDEX_BUFFERS: + case PIPE_CAP_QUERY_PIPELINE_STATISTICS: return 0; /* Stream output. */ diff --git a/src/gallium/drivers/i915/i915_screen.c b/src/gallium/drivers/i915/i915_screen.c index 13aa91c..54b2154 100644 --- a/src/gallium/drivers/i915/i915_screen.c +++ b/src/gallium/drivers/i915/i915_screen.c @@ -210,6 +210,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap) case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: case PIPE_CAP_START_INSTANCE: case PIPE_CAP_QUERY_TIMESTAMP: + case PIPE_CAP_QUERY_PIPELINE_STATISTICS: case PIPE_CAP_TEXTURE_MULTISAMPLE: case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: return 0; diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c index e8c6ab1..6700887 100644 --- a/src/gallium/drivers/llvmpipe/lp_screen.c +++ b/src/gallium/drivers/llvmpipe/lp_screen.c @@ -130,6 +130,8 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param) return 0; case PIPE_CAP_QUERY_TIMESTAMP: return 1; + case PIPE_CAP_QUERY_PIPELINE_STATISTICS: + return 0; case PIPE_CAP_TEXTURE_MIRROR_CLAMP: return 1; case PIPE_CAP_TEXTURE_SHADOW_MAP: diff --git a/src/gallium/drivers/nv30/nv30_screen.c b/src/gallium/drivers/nv30/nv30_screen.c index 4084869..e33710e 100644 --- a/src/gallium/drivers/nv30/nv30_screen.c +++ b/src/gallium/drivers/nv30/nv30_screen.c @@ -122,6 +122,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: + case PIPE_CAP_QUERY_PIPELINE_STATISTICS: return 0; case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: diff --git a/src/gallium/drivers/nv50/nv50_screen.c b/src/gallium/drivers/nv50/nv50_screen.c index 0a20ae3..53eeeb6 100644 --- a/src/gallium/drivers/nv50/nv50_screen.c +++ b/src/gallium/drivers/nv50/nv50_screen.c @@ -189,6 +189,8 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 0; case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: return 1; + case PIPE_CAP_QUERY_PIPELINE_STATISTICS: + return 0; default: NOUVEAU_ERR(unknown PIPE_CAP %d\n, param); return 0; diff --git a/src/gallium/drivers/nvc0/nvc0_screen.c b/src/gallium/drivers/nvc0/nvc0_screen.c index 5b9385a..3a32539 100644 --- a/src/gallium/drivers/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nvc0/nvc0_screen.c @@ -136,6 +136,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_QUERY_TIME_ELAPSED: case PIPE_CAP_OCCLUSION_QUERY: case
Mesa (master): gallium/docs: fix definition of PIPE_QUERY_SO_STATISTICS
Module: Mesa Branch: master Commit: c620aad71c2fe147dd2435c27053b435801a5237 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c620aad71c2fe147dd2435c27053b435801a5237 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Fri Mar 29 14:30:49 2013 +0100 gallium/docs: fix definition of PIPE_QUERY_SO_STATISTICS Reviewed-by: Marek Olšák mar...@gmail.com --- src/gallium/docs/source/context.rst |8 +--- 1 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/gallium/docs/source/context.rst b/src/gallium/docs/source/context.rst index 9e57930..2cc1848 100644 --- a/src/gallium/docs/source/context.rst +++ b/src/gallium/docs/source/context.rst @@ -335,15 +335,17 @@ The result is a 64-bit integer specifying the timer resolution in Hz, followed by a boolean value indicating whether the timer has incremented. ``PIPE_QUERY_PRIMITIVES_GENERATED`` returns a 64-bit integer indicating -the number of primitives processed by the pipeline. +the number of primitives processed by the pipeline (regardless of whether +stream output is active or not). ``PIPE_QUERY_PRIMITIVES_EMITTED`` returns a 64-bit integer indicating the number of primitives written to stream output buffers. ``PIPE_QUERY_SO_STATISTICS`` returns 2 64-bit integers corresponding to -the results of +the result of ``PIPE_QUERY_PRIMITIVES_EMITTED`` and -``PIPE_QUERY_PRIMITIVES_GENERATED``, in this order. +the number of primitives that would have been written to stream output buffers +if they had infinite space available (primitives_storage_needed), in this order. ``PIPE_QUERY_SO_OVERFLOW_PREDICATE`` returns a boolean value indicating whether the stream output targets have overflowed as a result of the ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): gallium/hud: add support for PIPE_QUERY_PIPELINE_STATISTICS
Module: Mesa
Branch: master
Commit: 3d2790cead7eb744341e8b1708b7a6d03524768d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d2790cead7eb744341e8b1708b7a6d03524768d
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Fri Mar 29 13:56:35 2013 +0100
gallium/hud: add support for PIPE_QUERY_PIPELINE_STATISTICS
Also, renamed pixels-rendered to samples-passed because the
occlusion counter increments even if colour and depth writes are
disabled, or (on some implementations) for killed fragments that
passed the depth test when PS early_fragment_tests is set.
---
src/gallium/auxiliary/hud/hud_context.c | 45 +++--
src/gallium/auxiliary/hud/hud_cpu.c |6 ++-
src/gallium/auxiliary/hud/hud_driver_query.c |9 +++--
src/gallium/auxiliary/hud/hud_private.h |1 +
4 files changed, 52 insertions(+), 9 deletions(-)
diff --git a/src/gallium/auxiliary/hud/hud_context.c
b/src/gallium/auxiliary/hud/hud_context.c
index 9b7b63f..5511f8e 100644
--- a/src/gallium/auxiliary/hud/hud_context.c
+++ b/src/gallium/auxiliary/hud/hud_context.c
@@ -90,6 +90,10 @@ struct hud_context {
unsigned max_num_vertices;
unsigned num_vertices;
} text, bg, whitelines;
+
+ struct {
+ boolean query_pipeline_statistics;
+ } cap;
};
@@ -719,15 +723,45 @@ hud_parse_env_var(struct hud_context *hud, const char
*env)
else if (sscanf(name, cpu%u%s, i, s) == 1) {
hud_cpu_graph_install(pane, i);
}
- else if (strcmp(name, pixels-rendered) == 0
+ else if (strcmp(name, samples-passed) == 0
has_occlusion_query(hud-pipe-screen)) {
- hud_pipe_query_install(pane, hud-pipe, pixels-rendered,
-PIPE_QUERY_OCCLUSION_COUNTER, 0, FALSE);
+ hud_pipe_query_install(pane, hud-pipe, samples-passed,
+PIPE_QUERY_OCCLUSION_COUNTER, 0, 0, FALSE);
}
else if (strcmp(name, primitives-generated) == 0
has_streamout(hud-pipe-screen)) {
hud_pipe_query_install(pane, hud-pipe, primitives-generated,
-PIPE_QUERY_PRIMITIVES_GENERATED, 0, FALSE);
+PIPE_QUERY_PRIMITIVES_GENERATED, 0, 0, FALSE);
+ }
+ else if (strncmp(name, pipeline-statistics-, 20) == 0) {
+ if (hud-cap.query_pipeline_statistics) {
+static const char *pipeline_statistics_names[] =
+{
+ ia-vertices,
+ ia-primitives,
+ vs-invocations,
+ gs-invocations,
+ gs-primitives,
+ clipper-invocations,
+ clipper-primitives-generated,
+ ps-invocations,
+ hs-invocations,
+ ds-invocations,
+ cs-invocations
+};
+for (i = 0; i Elements(pipeline_statistics_names); ++i)
+ if (strcmp(name[20], pipeline_statistics_names[i]) == 0)
+ break;
+if (i Elements(pipeline_statistics_names))
+ hud_pipe_query_install(pane, hud-pipe, name[20],
+ PIPE_QUERY_PIPELINE_STATISTICS, i,
+ 0, FALSE);
+else
+ fprintf(stderr, gallium_hud: invalid pipeline-statistics-*\n);
+ } else {
+fprintf(stderr, gallium_hud: PIPE_QUERY_PIPELINE_STATISTICS
+not supported by the driver\n);
+ }
}
else {
if (!hud_driver_query_install(pane, hud-pipe, name)){
@@ -990,6 +1024,9 @@ hud_create(struct pipe_context *pipe, struct cso_context
*cso)
LIST_INITHEAD(hud-pane_list);
+ hud-cap.query_pipeline_statistics =
+ pipe-screen-get_param(pipe-screen,
PIPE_CAP_QUERY_PIPELINE_STATISTICS);
+
hud_parse_env_var(hud, env);
return hud;
}
diff --git a/src/gallium/auxiliary/hud/hud_cpu.c
b/src/gallium/auxiliary/hud/hud_cpu.c
index dfd9f68..ce98115 100644
--- a/src/gallium/auxiliary/hud/hud_cpu.c
+++ b/src/gallium/auxiliary/hud/hud_cpu.c
@@ -32,6 +32,7 @@
#include os/os_time.h
#include util/u_memory.h
#include stdio.h
+#include inttypes.h
static boolean
get_cpu_stats(unsigned cpu_index, uint64_t *busy_time, uint64_t *total_time)
@@ -55,8 +56,9 @@ get_cpu_stats(unsigned cpu_index, uint64_t *busy_time,
uint64_t *total_time)
int i, num;
num = sscanf(line,
- %s %llu %llu %llu %llu %llu %llu %llu %llu %llu
- %llu %llu %llu,
+ %s %PRIu64 %PRIu64 %PRIu64 %PRIu64 %PRIu64
+ %PRIu64 %PRIu64 %PRIu64 %PRIu64 %PRIu64
+ %PRIu64 %PRIu64,
cpuname, v[0], v[1], v[2], v[3], v[4], v[5],
v[6], v[7], v[8], v[9], v[10], v[11]);
if (num 5) {
diff --git a/src/gallium/auxiliary/hud/hud_driver_query.c
b/src/gallium/auxiliary/hud
Mesa (master): nvc0: use fence to check state of queries that don' t write sequence
Module: Mesa
Branch: master
Commit: 6bca4e7085b5ce76ae065f40df39f6e3481d7475
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6bca4e7085b5ce76ae065f40df39f6e3481d7475
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Fri Mar 29 13:50:44 2013 +0100
nvc0: use fence to check state of queries that don't write sequence
This still isn't optimal, since the fence will signal a bit late,
but better than checking on the bo, which may never be ready if it
is shared (which is likely).
---
src/gallium/drivers/nvc0/nvc0_query.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_query.c
b/src/gallium/drivers/nvc0/nvc0_query.c
index 5c4431e..cd0dacd 100644
--- a/src/gallium/drivers/nvc0/nvc0_query.c
+++ b/src/gallium/drivers/nvc0/nvc0_query.c
@@ -46,6 +46,7 @@ struct nvc0_query {
boolean is64bit;
uint8_t rotate;
int nesting; /* only used for occlusion queries */
+ struct nouveau_fence *fence;
struct nouveau_mm_allocation *mm;
};
@@ -98,6 +99,7 @@ static void
nvc0_query_destroy(struct pipe_context *pipe, struct pipe_query *pq)
{
nvc0_query_allocate(nvc0_context(pipe), nvc0_query(pq), 0);
+ nouveau_fence_ref(NULL, nvc0_query(pq)-fence);
FREE(nvc0_query(pq));
}
@@ -337,13 +339,15 @@ nvc0_query_end(struct pipe_context *pipe, struct
pipe_query *pq)
nve4_mp_pm_query_end(nvc0, q);
break;
}
+ if (q-is64bit)
+ nouveau_fence_ref(nvc0-screen-base.fence.current, q-fence);
}
static INLINE void
nvc0_query_update(struct nouveau_client *cli, struct nvc0_query *q)
{
if (q-is64bit) {
- if (!nouveau_bo_map(q-bo, NOUVEAU_BO_RD | NOUVEAU_BO_NOBLOCK, cli))
+ if (nouveau_fence_signalled(q-fence))
q-state = NVC0_QUERY_STATE_READY;
} else {
if (q-data[0] == q-sequence)
___
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Mesa (master): nvc0: use correct hw query for PRIMITIVES_GENERATED
Module: Mesa Branch: master Commit: ea12fc3f6c154ac32573f6c0039af21676ad1c18 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea12fc3f6c154ac32573f6c0039af21676ad1c18 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Fri Mar 29 15:11:16 2013 +0100 nvc0: use correct hw query for PRIMITIVES_GENERATED It was the same as SO_STATISTICS[1] before. --- src/gallium/drivers/nvc0/nvc0_query.c | 11 +++ 1 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/nvc0/nvc0_query.c b/src/gallium/drivers/nvc0/nvc0_query.c index cd0dacd..2c8fcfa 100644 --- a/src/gallium/drivers/nvc0/nvc0_query.c +++ b/src/gallium/drivers/nvc0/nvc0_query.c @@ -129,12 +129,15 @@ nvc0_query_create(struct pipe_context *pipe, unsigned type) q-is64bit = TRUE; space = 64; break; + case PIPE_QUERY_PRIMITIVES_GENERATED: + case PIPE_QUERY_PRIMITIVES_EMITTED: + q-is64bit = TRUE; + space = 32; + break; case PIPE_QUERY_TIME_ELAPSED: case PIPE_QUERY_TIMESTAMP: case PIPE_QUERY_TIMESTAMP_DISJOINT: case PIPE_QUERY_GPU_FINISHED: - case PIPE_QUERY_PRIMITIVES_GENERATED: - case PIPE_QUERY_PRIMITIVES_EMITTED: space = 32; break; case NVC0_QUERY_TFB_BUFFER_OFFSET: @@ -234,7 +237,7 @@ nvc0_query_begin(struct pipe_context *pipe, struct pipe_query *pq) } break; case PIPE_QUERY_PRIMITIVES_GENERATED: - nvc0_query_get(push, q, 0x10, 0x06805002 | (q-index 5)); + nvc0_query_get(push, q, 0x10, 0x09005002 | (q-index 5)); break; case PIPE_QUERY_PRIMITIVES_EMITTED: nvc0_query_get(push, q, 0x10, 0x05805002 | (q-index 5)); @@ -295,7 +298,7 @@ nvc0_query_end(struct pipe_context *pipe, struct pipe_query *pq) } break; case PIPE_QUERY_PRIMITIVES_GENERATED: - nvc0_query_get(push, q, 0, 0x06805002 | (q-index 5)); + nvc0_query_get(push, q, 0, 0x09005002 | (q-index 5)); break; case PIPE_QUERY_PRIMITIVES_EMITTED: nvc0_query_get(push, q, 0, 0x05805002 | (q-index 5)); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nvc0: disable compressed storage type 0xdb for now
Module: Mesa
Branch: master
Commit: 7628cc247feecfb31aff97f47f039ebe476f0ca8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7628cc247feecfb31aff97f47f039ebe476f0ca8
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Sun Mar 31 20:10:23 2013 +0200
nvc0: disable compressed storage type 0xdb for now
Single-sample color compression doesn't seem that useful anyway.
---
src/gallium/drivers/nvc0/nvc0_miptree.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_miptree.c
b/src/gallium/drivers/nvc0/nvc0_miptree.c
index 1136804..412cca4 100644
--- a/src/gallium/drivers/nvc0/nvc0_miptree.c
+++ b/src/gallium/drivers/nvc0/nvc0_miptree.c
@@ -101,9 +101,11 @@ nvc0_mt_choose_storage_type(struct nv50_miptree *mt,
boolean compressed)
}
break;
case 32:
- if (compressed) {
+ if (compressed ms) {
switch (ms) {
+ /* This one makes things blurry:
case 0: tile_flags = 0xdb; break;
+ */
case 1: tile_flags = 0xdd; break;
case 2: tile_flags = 0xdf; break;
case 3: tile_flags = 0xe4; break;
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Mesa (master): nvc0: add some driver statistics queries
Module: Mesa
Branch: master
Commit: 198f514aa6f08bc43a3002519843b0fe94f340bd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=198f514aa6f08bc43a3002519843b0fe94f340bd
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Fri Mar 29 16:30:58 2013 +0100
nvc0: add some driver statistics queries
---
src/gallium/drivers/nouveau/nouveau_buffer.c | 30 ++
src/gallium/drivers/nouveau/nouveau_fence.c|2 +
src/gallium/drivers/nouveau/nouveau_screen.h | 55 ++
src/gallium/drivers/nv50/nv50_miptree.c|4 +
src/gallium/drivers/nvc0/nvc0_context.c|4 +
src/gallium/drivers/nvc0/nvc0_miptree.c|4 +
src/gallium/drivers/nvc0/nvc0_query.c | 134
src/gallium/drivers/nvc0/nvc0_screen.h | 46 -
src/gallium/drivers/nvc0/nvc0_state_validate.c |2 +
src/gallium/drivers/nvc0/nvc0_surface.c|4 +
src/gallium/drivers/nvc0/nvc0_tex.c|1 +
src/gallium/drivers/nvc0/nvc0_transfer.c |6 +
src/gallium/drivers/nvc0/nvc0_vbo.c| 10 ++
src/gallium/drivers/nvc0/nvc0_vbo_translate.c |2 +
14 files changed, 279 insertions(+), 25 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nouveau_buffer.c
b/src/gallium/drivers/nouveau/nouveau_buffer.c
index e3cbaf6..5c9a44e 100644
--- a/src/gallium/drivers/nouveau/nouveau_buffer.c
+++ b/src/gallium/drivers/nouveau/nouveau_buffer.c
@@ -51,12 +51,14 @@ nouveau_buffer_allocate(struct nouveau_screen *screen,
buf-bo, buf-offset);
if (!buf-bo)
return nouveau_buffer_allocate(screen, buf, NOUVEAU_BO_GART);
+ NOUVEAU_DRV_STAT(screen, buf_obj_current_bytes_vid, buf-base.width0);
} else
if (domain == NOUVEAU_BO_GART) {
buf-mm = nouveau_mm_allocate(screen-mm_GART, size,
buf-bo, buf-offset);
if (!buf-bo)
return FALSE;
+ NOUVEAU_DRV_STAT(screen, buf_obj_current_bytes_sys, buf-base.width0);
} else {
assert(domain == 0);
if (!nouveau_buffer_malloc(buf))
@@ -85,6 +87,11 @@ nouveau_buffer_release_gpu_storage(struct nv04_resource *buf)
if (buf-mm)
release_allocation(buf-mm, buf-fence);
+ if (buf-domain == NOUVEAU_BO_VRAM)
+ NOUVEAU_DRV_STAT_RES(buf, buf_obj_current_bytes_vid,
-(uint64_t)buf-base.width0);
+ if (buf-domain == NOUVEAU_BO_GART)
+ NOUVEAU_DRV_STAT_RES(buf, buf_obj_current_bytes_sys,
-(uint64_t)buf-base.width0);
+
buf-domain = 0;
}
@@ -117,6 +124,8 @@ nouveau_buffer_destroy(struct pipe_screen *pscreen,
nouveau_fence_ref(NULL, res-fence_wr);
FREE(res);
+
+ NOUVEAU_DRV_STAT(nouveau_screen(pscreen), buf_obj_current_count, -1);
}
static uint8_t *
@@ -153,6 +162,8 @@ nouveau_transfer_read(struct nouveau_context *nv, struct
nouveau_transfer *tx)
const unsigned base = tx-base.box.x;
const unsigned size = tx-base.box.width;
+ NOUVEAU_DRV_STAT(nv-screen, buf_read_bytes_staging_vid, size);
+
nv-copy_data(nv, tx-bo, tx-offset, NOUVEAU_BO_GART,
buf-bo, buf-offset + base, buf-domain, size);
@@ -179,6 +190,11 @@ nouveau_transfer_write(struct nouveau_context *nv, struct
nouveau_transfer *tx,
else
buf-status |= NOUVEAU_BUFFER_STATUS_DIRTY;
+ if (buf-domain == NOUVEAU_BO_VRAM)
+ NOUVEAU_DRV_STAT(nv-screen, buf_write_bytes_staging_vid, size);
+ if (buf-domain == NOUVEAU_BO_GART)
+ NOUVEAU_DRV_STAT(nv-screen, buf_write_bytes_staging_sys, size);
+
if (tx-bo)
nv-copy_data(nv, buf-bo, buf-offset + base, buf-domain,
tx-bo, tx-offset + offset, NOUVEAU_BO_GART, size);
@@ -197,11 +213,15 @@ nouveau_buffer_sync(struct nv04_resource *buf, unsigned
rw)
if (rw == PIPE_TRANSFER_READ) {
if (!buf-fence_wr)
return TRUE;
+ NOUVEAU_DRV_STAT_RES(buf, buf_non_kernel_fence_sync_count,
+ !nouveau_fence_signalled(buf-fence_wr));
if (!nouveau_fence_wait(buf-fence_wr))
return FALSE;
} else {
if (!buf-fence)
return TRUE;
+ NOUVEAU_DRV_STAT_RES(buf, buf_non_kernel_fence_sync_count,
+ !nouveau_fence_signalled(buf-fence));
if (!nouveau_fence_wait(buf-fence))
return FALSE;
@@ -320,6 +340,11 @@ nouveau_buffer_transfer_map(struct pipe_context *pipe,
nouveau_buffer_transfer_init(tx, resource, box, usage);
*ptransfer = tx-base;
+ if (usage PIPE_TRANSFER_READ)
+ NOUVEAU_DRV_STAT(nv-screen, buf_transfers_rd, 1);
+ if (usage PIPE_TRANSFER_WRITE)
+ NOUVEAU_DRV_STAT(nv-screen, buf_transfers_wr, 1);
+
if (buf-domain == NOUVEAU_BO_VRAM) {
if (usage NOUVEAU_TRANSFER_DISCARD) {
if (usage PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE)
@@ -427,6 +452,9 @@ nouveau_buffer_transfer_unmap(struct pipe_context *pipe,
}
}
+ if (!tx-bo (tx-base.usage PIPE_TRANSFER_WRITE
Mesa (master): nvc0: add some metrics to driver specific queries
Module: Mesa
Branch: master
Commit: 7bac075f25b803039fa8629028e15c5184cc8aad
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7bac075f25b803039fa8629028e15c5184cc8aad
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Mon Apr 1 17:25:40 2013 +0200
nvc0: add some metrics to driver specific queries
---
src/gallium/drivers/nvc0/nvc0_query.c | 209 +++-
src/gallium/drivers/nvc0/nvc0_screen.h |9 +-
2 files changed, 160 insertions(+), 58 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_query.c
b/src/gallium/drivers/nvc0/nvc0_query.c
index 52fff45..0fe8ae0 100644
--- a/src/gallium/drivers/nvc0/nvc0_query.c
+++ b/src/gallium/drivers/nvc0/nvc0_query.c
@@ -701,7 +701,14 @@ static const char *nve4_pm_query_names[] =
branch,
divergent_branch,
active_warps,
- active_cycles
+ active_cycles,
+ /* metrics, i.e. functions of the MP counters */
+ metric-ipc, /* inst_executed, clock */
+ metric-ipac, /* inst_executed, active_cycles */
+ metric-ipec, /* inst_executed, (bool)inst_executed */
+ metric-achieved_occupancy,/* active_warps, active_cycles */
+ metric-sm_efficiency, /* active_cycles, clock */
+ metric-inst_replay_overhead /* inst_issued, inst_executed */
};
/* For simplicity, we will allocate as many group slots as we allocate counter
@@ -715,59 +722,94 @@ struct nve4_mp_counter_cfg
uint32_t func: 16; /* mask or 4-bit logic op (depending on mode) */
uint32_t mode: 4; /* LOGOP,B6,LOGOP_B6(_PULSE) */
uint32_t pad : 3;
- uint32_t sig_dom : 1; /* if 0, MP_PM_A, if 1, MP_PM_B */
+ uint32_t sig_dom : 1; /* if 0, MP_PM_A (per warp-sched), if 1, MP_PM_B */
uint32_t sig_sel : 8; /* signal group */
uint32_t src_sel : 32; /* signal selection for up to 5 sources */
};
+#define NVE4_COUNTER_OPn_SUM0
+#define NVE4_COUNTER_OPn_OR 1
+#define NVE4_COUNTER_OPn_AND2
+#define NVE4_COUNTER_OP2_REL_SUM_MM 3 /* (sum(ctr0) - sum(ctr1)) /
sum(ctr0) */
+#define NVE4_COUNTER_OP2_DIV_SUM_M0 4 /* sum(ctr0) / ctr1 of MP[0]) */
+#define NVE4_COUNTER_OP2_AVG_DIV_MM 5 /* avg(ctr0 / ctr1) */
+#define NVE4_COUNTER_OP2_AVG_DIV_M0 6 /* avg(ctr0) / ctr1 of MP[0]) */
+
struct nve4_mp_pm_query_cfg
{
struct nve4_mp_counter_cfg ctr[4];
uint8_t num_counters;
- uint8_t op; /* PIPE_LOGICOP_CLEAR(for ADD),OR,AND */
+ uint8_t op;
+ uint8_t norm[2]; /* normalization num,denom */
};
-#define _Q1A(n, f, m, g, s) [NVE4_PM_QUERY_##n] = { { { f,
NVE4_COMPUTE_MP_PM_FUNC_MODE_##m, 0, 0, NVE4_COMPUTE_MP_PM_A_SIGSEL_##g, s },
{}, {}, {} }, 1, PIPE_LOGICOP_CLEAR }
-#define _Q1B(n, f, m, g, s) [NVE4_PM_QUERY_##n] = { { { f,
NVE4_COMPUTE_MP_PM_FUNC_MODE_##m, 0, 1, NVE4_COMPUTE_MP_PM_B_SIGSEL_##g, s },
{}, {}, {} }, 1, PIPE_LOGICOP_CLEAR }
-
+#define _Q1A(n, f, m, g, s, nu, dn) [NVE4_PM_QUERY_##n] = { { { f,
NVE4_COMPUTE_MP_PM_FUNC_MODE_##m, 0, 0, NVE4_COMPUTE_MP_PM_A_SIGSEL_##g, s },
{}, {}, {} }, 1, NVE4_COUNTER_OPn_SUM, { nu, dn } }
+#define _Q1B(n, f, m, g, s, nu, dn) [NVE4_PM_QUERY_##n] = { { { f,
NVE4_COMPUTE_MP_PM_FUNC_MODE_##m, 0, 1, NVE4_COMPUTE_MP_PM_B_SIGSEL_##g, s },
{}, {}, {} }, 1, NVE4_COUNTER_OPn_SUM, { nu, dn } }
+#define _M2A(n, f0, m0, g0, s0, f1, m1, g1, s1, o, nu, dn)
[NVE4_PM_QUERY_METRIC_##n] = { { \
+ { f0, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m0, 0, 0,
NVE4_COMPUTE_MP_PM_A_SIGSEL_##g0, s0 }, \
+ { f1, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m1, 0, 0,
NVE4_COMPUTE_MP_PM_A_SIGSEL_##g1, s1 }, \
+ {}, {}, }, 2, NVE4_COUNTER_OP2_##o, { nu, dn } }
+#define _M2B(n, f0, m0, g0, s0, f1, m1, g1, s1, o, nu, dn)
[NVE4_PM_QUERY_METRIC_##n] = { { \
+ { f0, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m0, 0, 1,
NVE4_COMPUTE_MP_PM_B_SIGSEL_##g0, s0 }, \
+ { f1, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m1, 0, 1,
NVE4_COMPUTE_MP_PM_B_SIGSEL_##g1, s1 }, \
+ {}, {}, }, 2, NVE4_COUNTER_OP2_##o, { nu, dn } }
+#define _M2AB(n, f0, m0, g0, s0, f1, m1, g1, s1, o, nu, dn)
[NVE4_PM_QUERY_METRIC_##n] = { { \
+ { f0, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m0, 0, 0,
NVE4_COMPUTE_MP_PM_A_SIGSEL_##g0, s0 }, \
+ { f1, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m1, 0, 1,
NVE4_COMPUTE_MP_PM_B_SIGSEL_##g1, s1 }, \
+ {}, {}, }, 2, NVE4_COUNTER_OP2_##o, { nu, dn } }
+
+/* NOTES:
+ * active_warps: bit 0 alternates btw 0 and 1 for odd nr of warps
+ * inst_executed etc.: we only count a single warp scheduler
+ * metric-ipXc: we simply multiply by 4 to account for the 4 warp schedulers;
+ * this is inaccurate !
+ */
static const struct nve4_mp_pm_query_cfg nve4_mp_pm_queries[] =
{
- _Q1A(PROF_TRIGGER_0, 0x0001, B6, USER, 0x),
- _Q1A(PROF_TRIGGER_1, 0x0001, B6, USER, 0x0004),
- _Q1A(PROF_TRIGGER_2, 0x0001, B6, USER, 0x0008),
- _Q1A(PROF_TRIGGER_3, 0x0001, B6, USER, 0x000c),
- _Q1A(PROF_TRIGGER_4, 0x0001, B6, USER, 0x0010),
- _Q1A(PROF_TRIGGER_5, 0x0001, B6, USER, 0x0014),
- _Q1A
Mesa (master): nvc0: read PM counters for each warp scheduler separately
Module: Mesa
Branch: master
Commit: fb0334adb3c9d20016c15e5706a6dfe1fc70ba88
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb0334adb3c9d20016c15e5706a6dfe1fc70ba88
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Tue Apr 2 18:24:45 2013 +0200
nvc0: read PM counters for each warp scheduler separately
---
src/gallium/drivers/nvc0/nvc0_query.c | 184 ++-
src/gallium/drivers/nvc0/nvc0_screen.h | 15 ++--
2 files changed, 138 insertions(+), 61 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_query.c
b/src/gallium/drivers/nvc0/nvc0_query.c
index 0fe8ae0..35d5d46 100644
--- a/src/gallium/drivers/nvc0/nvc0_query.c
+++ b/src/gallium/drivers/nvc0/nvc0_query.c
@@ -159,8 +159,33 @@ nvc0_query_create(struct pipe_context *pipe, unsigned type)
nvc0-screen-base.device-drm_version = 0x01000101) {
if (type = NVE4_PM_QUERY(0)
type = NVE4_PM_QUERY_LAST) {
-/* 8 counters per MP + clock */
-space = 12 * nvc0-screen-mp_count * sizeof(uint32_t);
+/* for each MP:
+ * [00] = WS0.C0
+ * [04] = WS0.C1
+ * [08] = WS0.C2
+ * [0c] = WS0.C3
+ * [10] = WS0.C0
+ * [14] = WS1.C1
+ * [18] = WS1.C2
+ * [1c] = WS1.C3
+ * [20] = WS1.C0
+ * [24] = WS2.C1
+ * [28] = WS2.C2
+ * [2c] = WS2.C3
+ * [30] = WS3.C0
+ * [34] = WS3.C1
+ * [38] = WS3.C2
+ * [3c] = WS3.C3
+ * [40] = MP.C4
+ * [44] = MP.C5
+ * [48] = MP.C6
+ * [4c] = MP.C7
+ * [50] = WS0.sequence
+ * [54] = WS1.sequence
+ * [58] = WS2.sequence
+ * [5c] = WS3.sequence
+ */
+space = (4 * 4 + 4 + 4) * nvc0-screen-mp_count *
sizeof(uint32_t);
break;
}
}
@@ -634,36 +659,82 @@ static const char *nvc0_drv_stat_names[] =
*/
static const uint64_t nve4_read_mp_pm_counters_code[] =
{
- 0x2042004270420047ULL, /* sched */
- 0x280040001de4ULL, /* mov b32 $r0 c0[0] (04) */
- 0x2c000c009c04ULL, /* mov b32 $r2 $physid (20) */
- 0x2800400010005de4ULL, /* mov b32 $r1 c0[4] (04) */
- 0x2c008400dc04ULL, /* mov b32 $r3 $tidx (27) */
- 0x7000c01050209c03ULL, /* ext u32 $r2 $r2 0x0414 (04) */
- 0x2c0010011c04ULL, /* mov b32 $r4 $pm0 (20) */
- 0x190efc33dc03ULL, /* set $p1 eq u32 $r3 0 (04) */
- 0x2280428042804277ULL, /* sched */
- 0x2c0014015c04ULL, /* mov b32 $r5 $pm1 (27) */
- 0x1000c0209c02ULL, /* mul $r2 u32 $r2 u32 48 (04) */
- 0x2c0018019c04ULL, /* mov b32 $r6 $pm2 (28) */
- 0x480108001c03ULL, /* add b32 ($r0 $c) $r0 $r2 (04) */
- 0x2c001c01dc04ULL, /* mov b32 $r7 $pm3 (28) */
- 0x08105c42ULL, /* add b32 $r1 $r1 0 $c (04) */
- 0x2c0140009c04ULL, /* mov b32 $r2 $clock (28) */
- 0x2042804200420047ULL, /* sched */
- 0x940107c5ULL, /* $p1 st b128 wt g[$r0d] $r4q (04) */
- 0x2c0020011c04ULL, /* mov b32 $r4 $pm4 (20) */
- 0x2c0024015c04ULL, /* mov b32 $r5 $pm5 (04) */
- 0x2c0028019c04ULL, /* mov b32 $r6 $pm6 (20) */
- 0x2c002c01dc04ULL, /* mov b32 $r7 $pm7 (04) */
- 0x2c014400dc04ULL, /* mov b32 $r3 $clockhi (28) */
- 0x9400400107c5ULL, /* $p1 st b128 wt g[$r0d+16] $r4q (04) */
- 0x22e042804207ULL, /* sched */
- 0x2800400020011de4ULL, /* mov b32 $r4 c0[8] (20) */
- 0x2c000c015c04ULL, /* mov b32 $r5 $physid (04) */
- 0x9400800087a5ULL, /* $p1 st b64 wt g[$r0d+32] $r2d (28) */
- 0x9400a00107a5ULL, /* $p1 st b64 wt g[$r0d+40] $r4d (04) */
- 0x80001de7ULL /* exit (2e) */
+ /* sched 0x20 0x20 0x20 0x20 0x20 0x20 0x20
+* mov b32 $r8 $tidx
+* mov b32 $r12 $physid
+* mov b32 $r0 $pm0
+* mov b32 $r1 $pm1
+* mov b32 $r2 $pm2
+* mov b32 $r3 $pm3
+* mov b32 $r4 $pm4
+* sched 0x20 0x20 0x23 0x04 0x20 0x04 0x2b
+* mov b32 $r5 $pm5
+* mov b32 $r6 $pm6
+* mov b32 $r7 $pm7
+* set $p0 0x1 eq u32 $r8 0x0
+* mov b32 $r10 c0[0x0]
+* ext u32 $r8 $r12 0x414
+* mov b32 $r11 c0[0x4]
+* sched 0x04 0x2e 0x04 0x20 0x20 0x28 0x04
+* ext u32 $r9 $r12 0x208
+* (not $p0) exit
+* set $p1 0x1 eq u32 $r9 0x0
+* mul $r8 u32 $r8 u32 96
+* mul $r12 u32 $r9 u32 16
+* mul $r13 u32 $r9 u32 4
+* add b32 $r9 $r8 $r13
+* sched 0x28 0x04 0x2c 0x04 0x2c 0x04 0x2c
+* add b32 $r8 $r8 $r12
+* mov b32 $r12 $r10
+* add b32 $r10 $c $r10 $r8
+* mov b32 $r13 $r11
+* add b32 $r11 $r11 0x0 $c
+* add b32 $r12 $c $r12 $r9
+* st b128 wt g[$r10d] $r0q
+* sched 0x4 0x2c 0x20 0x04 0x2e 0x00 0x00
+* mov b32 $r0 c0[0x8]
+* add b32 $r13 $r13 0x0 $c
+* $p1 st b128 wt g[$r12d+0x40] $r4q
+* st b32 wt g[$r12d+0x50] $r0
+* exit */
+ 0x2202020202020207ULL,
+ 0x2c0084021c04ULL
Mesa (master): nvc0: demagic some of the NVE4_COMPUTE_UPLOAD methods
Module: Mesa
Branch: master
Commit: 3ed4bbd76904983ca4b19a58afd2187f497b4ab0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ed4bbd76904983ca4b19a58afd2187f497b4ab0
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Mon Apr 1 21:46:24 2013 +0200
nvc0: demagic some of the NVE4_COMPUTE_UPLOAD methods
It's actually the same as P2MF.
---
src/gallium/drivers/nvc0/nve4_compute.c | 58 +++---
src/gallium/drivers/nvc0/nve4_compute.h |4 -
src/gallium/drivers/nvc0/nve4_compute.xml.h | 116 +++
3 files changed, 129 insertions(+), 49 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nve4_compute.c
b/src/gallium/drivers/nvc0/nve4_compute.c
index 89da7d5..d7aa61e 100644
--- a/src/gallium/drivers/nvc0/nve4_compute.c
+++ b/src/gallium/drivers/nvc0/nve4_compute.c
@@ -129,14 +129,14 @@ nve4_screen_compute_setup(struct nvc0_screen *screen,
IMMED_NVC0(push, SUBC_COMPUTE(0x02c4), 1);
/* MS sample coordinate offsets: these do not work with _ALT modes ! */
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
PUSH_DATAh(push, screen-parm-offset + NVE4_CP_INPUT_MS_OFFSETS);
PUSH_DATA (push, screen-parm-offset + NVE4_CP_INPUT_MS_OFFSETS);
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
PUSH_DATA (push, 64);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_UNK0184_UNKVAL);
+ PUSH_DATA (push, 1);
BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 17);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
+ PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 1));
PUSH_DATA (push, 0); /* 0 */
PUSH_DATA (push, 0);
PUSH_DATA (push, 1); /* 1 */
@@ -155,14 +155,14 @@ nve4_screen_compute_setup(struct nvc0_screen *screen,
PUSH_DATA (push, 1);
#ifdef DEBUG
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
PUSH_DATAh(push, screen-parm-offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
PUSH_DATA (push, screen-parm-offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
PUSH_DATA (push, 28);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_UNK0184_UNKVAL);
+ PUSH_DATA (push, 1);
BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 8);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
+ PUSH_DATA (push, 1);
PUSH_DATA (push, screen-parm-offset + NVE4_CP_PARAM_TRAP_INFO);
PUSH_DATAh(push, screen-parm-offset + NVE4_CP_PARAM_TRAP_INFO);
PUSH_DATA (push, screen-tls-offset);
@@ -199,14 +199,14 @@ nve4_compute_validate_surfaces(struct nvc0_context *nvc0)
* NVE4's surface load/store instructions receive all the information
* directly instead of via binding points, so we have to supply them.
*/
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
PUSH_DATAh(push, screen-parm-offset + NVE4_CP_INPUT_SUF(i));
PUSH_DATA (push, screen-parm-offset + NVE4_CP_INPUT_SUF(i));
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
PUSH_DATA (push, 64);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_UNK0184_UNKVAL);
+ PUSH_DATA (push, 1);
BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 17);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
+ PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 1));
nve4_set_surface_info(push, nvc0-surfaces[t][i], screen);
@@ -279,14 +279,14 @@ nve4_compute_set_tex_handles(struct nvc0_context *nvc0)
address = nvc0-screen-parm-offset + NVE4_CP_INPUT_TEX(i);
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
PUSH_DATAh(push, address);
PUSH_DATA (push, address);
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
PUSH_DATA (push, n * 4);
PUSH_DATA (push, 0x1);
BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + n);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
+ PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 1));
PUSH_DATAp(push, nvc0-tex_handles[s][i], n);
BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
@@ -365,24 +365,24 @@ nve4_compute_upload_input(struct nvc0_context *nvc0,
const void *input,
struct nvc0_program *cp = nvc0-compprog;
if (cp-parm_size) {
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
PUSH_DATAh(push, screen-parm-offset);
PUSH_DATA (push, screen-parm-offset);
- BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
+ BEGIN_NVC0(push, NVE4_COMPUTE
Mesa (master): nouveau: accelerate buffer copies in resource_copy_region
Module: Mesa
Branch: master
Commit: 2a8145d36b0f04d0f26c1628222a8b5c4830f435
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a8145d36b0f04d0f26c1628222a8b5c4830f435
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Sat Mar 30 15:55:20 2013 +0100
nouveau: accelerate buffer copies in resource_copy_region
---
src/gallium/drivers/nouveau/nouveau_buffer.c | 34 ++
src/gallium/drivers/nouveau/nouveau_buffer.h |7 +++--
src/gallium/drivers/nv30/nv30_miptree.c |5 ++-
src/gallium/drivers/nv50/nv50_surface.c |6 ++--
src/gallium/drivers/nvc0/nvc0_surface.c |6 ++--
5 files changed, 47 insertions(+), 11 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nouveau_buffer.c
b/src/gallium/drivers/nouveau/nouveau_buffer.c
index 5c9a44e..02bc6f0 100644
--- a/src/gallium/drivers/nouveau/nouveau_buffer.c
+++ b/src/gallium/drivers/nouveau/nouveau_buffer.c
@@ -2,6 +2,7 @@
#include util/u_inlines.h
#include util/u_memory.h
#include util/u_math.h
+#include util/u_surface.h
#include nouveau_screen.h
#include nouveau_context.h
@@ -460,6 +461,39 @@ nouveau_buffer_transfer_unmap(struct pipe_context *pipe,
}
+void
+nouveau_copy_buffer(struct nouveau_context *nv,
+struct nv04_resource *dst, unsigned dstx,
+struct nv04_resource *src, unsigned srcx, unsigned size)
+{
+ assert(dst-base.target == PIPE_BUFFER src-base.target == PIPE_BUFFER);
+
+ if (likely(dst-domain) likely(src-domain)) {
+ nv-copy_data(nv,
+dst-bo, dst-offset + dstx, dst-domain,
+src-bo, src-offset + srcx, src-domain, size);
+
+ dst-status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
+ nouveau_fence_ref(nv-screen-fence.current, dst-fence);
+ nouveau_fence_ref(nv-screen-fence.current, dst-fence_wr);
+
+ src-status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
+ nouveau_fence_ref(nv-screen-fence.current, src-fence);
+ } else {
+ struct pipe_box src_box;
+ src_box.x = srcx;
+ src_box.y = 0;
+ src_box.z = 0;
+ src_box.width = size;
+ src_box.height = 1;
+ src_box.depth = 1;
+ util_resource_copy_region(nv-pipe,
+dst-base, 0, dstx, 0, 0,
+src-base, 0, src_box);
+ }
+}
+
+
void *
nouveau_resource_map_offset(struct nouveau_context *nv,
struct nv04_resource *res, uint32_t offset,
diff --git a/src/gallium/drivers/nouveau/nouveau_buffer.h
b/src/gallium/drivers/nouveau/nouveau_buffer.h
index aafc842..fd7a3f1 100644
--- a/src/gallium/drivers/nouveau/nouveau_buffer.h
+++ b/src/gallium/drivers/nouveau/nouveau_buffer.h
@@ -49,9 +49,10 @@ struct nv04_resource {
void
nouveau_buffer_release_gpu_storage(struct nv04_resource *);
-boolean
-nouveau_buffer_download(struct nouveau_context *, struct nv04_resource *,
-unsigned start, unsigned size);
+void
+nouveau_copy_buffer(struct nouveau_context *,
+struct nv04_resource *dst, unsigned dst_pos,
+struct nv04_resource *src, unsigned src_pos, unsigned
size);
boolean
nouveau_buffer_migrate(struct nouveau_context *,
diff --git a/src/gallium/drivers/nv30/nv30_miptree.c
b/src/gallium/drivers/nv30/nv30_miptree.c
index d4dcacb..f536287 100644
--- a/src/gallium/drivers/nv30/nv30_miptree.c
+++ b/src/gallium/drivers/nv30/nv30_miptree.c
@@ -130,8 +130,9 @@ nv30_resource_copy_region(struct pipe_context *pipe,
struct nv30_rect src, dst;
if (dstres-target == PIPE_BUFFER srcres-target == PIPE_BUFFER) {
- util_resource_copy_region(pipe, dstres, dst_level, dstx, dsty, dstz,
- srcres, src_level, src_box);
+ nouveau_copy_buffer(nv30-base,
+ nv04_resource(dstres), dstx,
+ nv04_resource(srcres), src_box-x, src_box-width);
return;
}
diff --git a/src/gallium/drivers/nv50/nv50_surface.c
b/src/gallium/drivers/nv50/nv50_surface.c
index b29a736..51e702c 100644
--- a/src/gallium/drivers/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nv50/nv50_surface.c
@@ -200,10 +200,10 @@ nv50_resource_copy_region(struct pipe_context *pipe,
boolean m2mf;
unsigned dst_layer = dstz, src_layer = src_box-z;
- /* Fallback for buffers. */
if (dst-target == PIPE_BUFFER src-target == PIPE_BUFFER) {
- util_resource_copy_region(pipe, dst, dst_level, dstx, dsty, dstz,
-src, src_level, src_box);
+ nouveau_copy_buffer(nv50-base,
+ nv04_resource(dst), dstx,
+ nv04_resource(src), src_box-x, src_box-width);
return;
}
diff --git a/src/gallium/drivers/nvc0/nvc0_surface.c
b/src/gallium/drivers/nvc0/nvc0_surface.c
index 95f3ff4..de71127 100644
--- a/src/gallium/drivers/nvc0/nvc0_surface.c
+++ b/src/gallium/drivers/nvc0/nvc0_surface.c
@@ -201,10 +201,10
Mesa (master): st/mesa: fix bitmap,drawpix, drawtex for PIPE_CAP_TGSI_TEXCOORD
Module: Mesa
Branch: master
Commit: e45c969fe5890472d0a49bf2f7d561f3d315be2a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e45c969fe5890472d0a49bf2f7d561f3d315be2a
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Sat Mar 30 14:57:21 2013 +0100
st/mesa: fix bitmap,drawpix,drawtex for PIPE_CAP_TGSI_TEXCOORD
NOTE: Changed the semantic index for the drawtex coordinate to
be the texture unit index instead of always 0.
Not sure if this is correct but since the value seems to depend
on the unit it would make sense to use different varying slots.
---
src/mesa/state_tracker/st_cb_bitmap.c |1 +
src/mesa/state_tracker/st_cb_drawpixels.c |5 -
src/mesa/state_tracker/st_cb_drawtex.c|4 +++-
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_bitmap.c
b/src/mesa/state_tracker/st_cb_bitmap.c
index bae9ff8..0513814 100644
--- a/src/mesa/state_tracker/st_cb_bitmap.c
+++ b/src/mesa/state_tracker/st_cb_bitmap.c
@@ -766,6 +766,7 @@ st_Bitmap(struct gl_context *ctx, GLint x, GLint y,
/* create pass-through vertex shader now */
const uint semantic_names[] = { TGSI_SEMANTIC_POSITION,
TGSI_SEMANTIC_COLOR,
+st-needs_texcoord_semantic ? TGSI_SEMANTIC_TEXCOORD :
TGSI_SEMANTIC_GENERIC };
const uint semantic_indexes[] = { 0, 0, 0 };
st-bitmap.vs = util_make_vertex_passthrough_shader(st-pipe, 3,
diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c
b/src/mesa/state_tracker/st_cb_drawpixels.c
index f0baa34..b25b776 100644
--- a/src/mesa/state_tracker/st_cb_drawpixels.c
+++ b/src/mesa/state_tracker/st_cb_drawpixels.c
@@ -294,6 +294,9 @@ static void *
make_passthrough_vertex_shader(struct st_context *st,
GLboolean passColor)
{
+ const unsigned texcoord_semantic = st-needs_texcoord_semantic ?
+ TGSI_SEMANTIC_TEXCOORD : TGSI_SEMANTIC_GENERIC;
+
if (!st-drawpix.vert_shaders[passColor]) {
struct ureg_program *ureg = ureg_create( TGSI_PROCESSOR_VERTEX );
@@ -307,7 +310,7 @@ make_passthrough_vertex_shader(struct st_context *st,
/* MOV result.texcoord0, vertex.attr[1]; */
ureg_MOV(ureg,
- ureg_DECL_output( ureg, TGSI_SEMANTIC_GENERIC, 0 ),
+ ureg_DECL_output( ureg, texcoord_semantic, 0 ),
ureg_DECL_vs_input( ureg, 1 ));
if (passColor) {
diff --git a/src/mesa/state_tracker/st_cb_drawtex.c
b/src/mesa/state_tracker/st_cb_drawtex.c
index a8806c9..c4efce0 100644
--- a/src/mesa/state_tracker/st_cb_drawtex.c
+++ b/src/mesa/state_tracker/st_cb_drawtex.c
@@ -209,7 +209,9 @@ st_DrawTex(struct gl_context *ctx, GLfloat x, GLfloat y,
GLfloat z,
SET_ATTRIB(2, attr, s1, t1, 0.0f, 1.0f); /* upper right */
SET_ATTRIB(3, attr, s0, t1, 0.0f, 1.0f); /* upper left */
-semantic_names[attr] = TGSI_SEMANTIC_GENERIC;
+semantic_names[attr] = st-needs_texcoord_semantic ?
+ TGSI_SEMANTIC_TEXCOORD : TGSI_SEMANTIC_GENERIC;
+/* XXX: should this use semantic index i instead of 0 ? */
semantic_indexes[attr] = 0;
attr++;
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Mesa (master): nv50, nvc0: disable DEPTH_RANGE_NEAR/FAR clipping during blit
Module: Mesa Branch: master Commit: 6417d56c1921c311a7b59001e0d37822a0ed1a65 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6417d56c1921c311a7b59001e0d37822a0ed1a65 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Sun Mar 31 22:10:02 2013 +0200 nv50,nvc0: disable DEPTH_RANGE_NEAR/FAR clipping during blit We send position.z == 0, DEPTH_RANGE may be some arbitrary range not including 0 (for exmaple in piglit's hiz tests). --- src/gallium/drivers/nv50/nv50_surface.c |2 ++ src/gallium/drivers/nvc0/nvc0_3d.xml.h |2 +- src/gallium/drivers/nvc0/nvc0_surface.c |2 ++ 3 files changed, 5 insertions(+), 1 deletions(-) diff --git a/src/gallium/drivers/nv50/nv50_surface.c b/src/gallium/drivers/nv50/nv50_surface.c index 51e702c..d482477 100644 --- a/src/gallium/drivers/nv50/nv50_surface.c +++ b/src/gallium/drivers/nv50/nv50_surface.c @@ -976,6 +976,8 @@ nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info) BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1); PUSH_DATA (push, 0); + BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1); + PUSH_DATA (push, 0x1); /* Draw a large triangle in screen coordinates covering the whole * render target, with scissors defining the destination region. diff --git a/src/gallium/drivers/nvc0/nvc0_3d.xml.h b/src/gallium/drivers/nvc0/nvc0_3d.xml.h index 44f96a2..d3f719d 100644 --- a/src/gallium/drivers/nvc0/nvc0_3d.xml.h +++ b/src/gallium/drivers/nvc0/nvc0_3d.xml.h @@ -1041,7 +1041,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_VIEWPORT_TRANSFORM_EN 0x192c #define NVC0_3D_VIEW_VOLUME_CLIP_CTRL 0x193c -#define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK0 0x0001 +#define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_RANGE_0_1 0x0001 #define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1__MASK 0x0006 #define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1__SHIFT 1 #define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK0 0x diff --git a/src/gallium/drivers/nvc0/nvc0_surface.c b/src/gallium/drivers/nvc0/nvc0_surface.c index de71127..2af7fcd 100644 --- a/src/gallium/drivers/nvc0/nvc0_surface.c +++ b/src/gallium/drivers/nvc0/nvc0_surface.c @@ -869,6 +869,8 @@ nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info) z += 0.5f * dz; IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 0); + IMMED_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 0x2 | + NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_RANGE_0_1); BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(0)), 2); PUSH_DATA (push, nvc0-framebuffer.width 16); PUSH_DATA (push, nvc0-framebuffer.height 16); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nvc0: fix for 2d engine R source formats writing RRR1 and not R001
Module: Mesa
Branch: master
Commit: d801545964f8183bb17ed913b7c19482dad43b6c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d801545964f8183bb17ed913b7c19482dad43b6c
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Sat Mar 30 21:28:30 2013 +0100
nvc0: fix for 2d engine R source formats writing RRR1 and not R001
---
src/gallium/drivers/nv50/nv50_blit.h| 40 ++
src/gallium/drivers/nv50/nv50_surface.c | 71
src/gallium/drivers/nvc0/nvc0_surface.c | 89 +--
3 files changed, 148 insertions(+), 52 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_blit.h
b/src/gallium/drivers/nv50/nv50_blit.h
index d409f21..bdd6a63 100644
--- a/src/gallium/drivers/nv50/nv50_blit.h
+++ b/src/gallium/drivers/nv50/nv50_blit.h
@@ -180,4 +180,44 @@ nv50_blit_eng2d_get_mask(const struct pipe_blit_info *info)
return mask;
}
+#if NOUVEAU_DRIVER == 0xc0
+# define nv50_format_table nvc0_format_table
+#endif
+
+/* return TRUE for formats that can be converted among each other by NVC0_2D */
+static INLINE boolean
+nv50_2d_dst_format_faithful(enum pipe_format format)
+{
+ const uint64_t mask =
+ NV50_ENG2D_SUPPORTED_FORMATS
+ ~NV50_ENG2D_NOCONVERT_FORMATS;
+ uint8_t id = nv50_format_table[format].rt;
+ return (id = 0xc0) (mask (1ULL (id - 0xc0)));
+}
+static INLINE boolean
+nv50_2d_src_format_faithful(enum pipe_format format)
+{
+ const uint64_t mask =
+ NV50_ENG2D_SUPPORTED_FORMATS
+~(NV50_ENG2D_LUMINANCE_FORMATS | NV50_ENG2D_INTENSITY_FORMATS);
+ uint8_t id = nv50_format_table[format].rt;
+ return (id = 0xc0) (mask (1ULL (id - 0xc0)));
+}
+
+static INLINE boolean
+nv50_2d_format_supported(enum pipe_format format)
+{
+ uint8_t id = nv50_format_table[format].rt;
+ return (id = 0xc0)
+ (NV50_ENG2D_SUPPORTED_FORMATS (1ULL (id - 0xc0)));
+}
+
+static INLINE boolean
+nv50_2d_dst_format_ops_supported(enum pipe_format format)
+{
+ uint8_t id = nv50_format_table[format].rt;
+ return (id = 0xc0)
+ (NV50_ENG2D_OPERATION_FORMATS (1ULL (id - 0xc0)));
+}
+
#endif /* __NV50_BLIT_H__ */
diff --git a/src/gallium/drivers/nv50/nv50_surface.c
b/src/gallium/drivers/nv50/nv50_surface.c
index d482477..5d0b313 100644
--- a/src/gallium/drivers/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nv50/nv50_surface.c
@@ -35,25 +35,22 @@
#include nv50_context.h
#include nv50_resource.h
-#include nv50_blit.h
#include nv50_defs.xml.h
#include nv50_texture.xml.h
+/* these are used in nv50_blit.h */
#define NV50_ENG2D_SUPPORTED_FORMATS 0xff0843e080608409ULL
+#define NV50_ENG2D_NOCONVERT_FORMATS 0x00084020ULL
+#define NV50_ENG2D_LUMINANCE_FORMATS 0x00084020ULL
+#define NV50_ENG2D_INTENSITY_FORMATS 0xULL
+#define NV50_ENG2D_OPERATION_FORMATS 0x060001c000608000ULL
-/* return TRUE for formats that can be converted among each other by NV50_2D */
-static INLINE boolean
-nv50_2d_format_faithful(enum pipe_format format)
-{
- uint8_t id = nv50_format_table[format].rt;
-
- return (id = 0xc0)
- (NV50_ENG2D_SUPPORTED_FORMATS (1ULL (id - 0xc0)));
-}
+#define NOUVEAU_DRIVER 0x50
+#include nv50_blit.h
static INLINE uint8_t
-nv50_2d_format(enum pipe_format format)
+nv50_2d_format(enum pipe_format format, boolean dst, boolean dst_src_equal)
{
uint8_t id = nv50_format_table[format].rt;
@@ -62,6 +59,7 @@ nv50_2d_format(enum pipe_format format)
*/
if ((id = 0xc0) (NV50_ENG2D_SUPPORTED_FORMATS (1ULL (id - 0xc0
return id;
+ assert(dst_src_equal);
switch (util_format_get_blocksize(format)) {
case 1:
@@ -78,7 +76,7 @@ nv50_2d_format(enum pipe_format format)
static int
nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
struct nv50_miptree *mt, unsigned level, unsigned layer,
-enum pipe_format pformat)
+enum pipe_format pformat, boolean dst_src_pformat_equal)
{
struct nouveau_bo *bo = mt-base.bo;
uint32_t width, height, depth;
@@ -86,7 +84,7 @@ nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
uint32_t offset = mt-level[level].offset;
- format = nv50_2d_format(pformat);
+ format = nv50_2d_format(pformat, dst, dst_src_pformat_equal);
if (!format) {
NOUVEAU_ERR(invalid/unsupported surface format: %s\n,
util_format_name(pformat));
@@ -155,15 +153,16 @@ nv50_2d_texture_do_copy(struct nouveau_pushbuf *push,
const enum pipe_format dfmt = dst-base.base.format;
const enum pipe_format sfmt = src-base.base.format;
int ret;
+ boolean eqfmt = dfmt == sfmt;
if (!PUSH_SPACE(push, 2 * 16 + 32))
return PIPE_ERROR;
- ret = nv50_2d_texture_set(push, 1, dst, dst_level, dz, dfmt);
+ ret = nv50_2d_texture_set(push, 1, dst, dst_level, dz, dfmt, eqfmt);
if (ret)
return ret;
- ret = nv50_2d_texture_set
Mesa (master): nv50: account for pesky prefetch in size calculation of linear textures
Module: Mesa
Branch: master
Commit: ba9b0b682f51222752ac56e7a0615f9bbb686089
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba9b0b682f51222752ac56e7a0615f9bbb686089
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Wed Apr 3 00:18:29 2013 +0200
nv50: account for pesky prefetch in size calculation of linear textures
---
src/gallium/drivers/nv50/nv50_miptree.c |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_miptree.c
b/src/gallium/drivers/nv50/nv50_miptree.c
index 5c839a8..ed0f8c2 100644
--- a/src/gallium/drivers/nv50/nv50_miptree.c
+++ b/src/gallium/drivers/nv50/nv50_miptree.c
@@ -217,6 +217,7 @@ nv50_miptree_init_layout_linear(struct nv50_miptree *mt)
{
struct pipe_resource *pt = mt-base.base;
const unsigned blocksize = util_format_get_blocksize(pt-format);
+ unsigned h = pt-height0;
if (util_format_is_depth_or_stencil(pt-format))
return FALSE;
@@ -228,7 +229,11 @@ nv50_miptree_init_layout_linear(struct nv50_miptree *mt)
mt-level[0].pitch = align(pt-width0 * blocksize, 64);
- mt-total_size = mt-level[0].pitch * pt-height0;
+ /* Account for very generous prefetch (allocate size as if tiled). */
+ h = MAX2(h, 8);
+ h = util_next_power_of_two(h);
+
+ mt-total_size = mt-level[0].pitch * h;
return TRUE;
}
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Mesa (master): nvc0: honour scaled coordiantes setting for linear textures
Module: Mesa
Branch: master
Commit: f0a0d59f0fdceb756838ad6dad012852ba48362e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0a0d59f0fdceb756838ad6dad012852ba48362e
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Tue Apr 2 16:24:06 2013 +0200
nvc0: honour scaled coordiantes setting for linear textures
---
src/gallium/drivers/nvc0/nvc0_tex.c | 11 +--
1 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_tex.c
b/src/gallium/drivers/nvc0/nvc0_tex.c
index b0e02fc..ffd2854 100644
--- a/src/gallium/drivers/nvc0/nvc0_tex.c
+++ b/src/gallium/drivers/nvc0/nvc0_tex.c
@@ -61,7 +61,7 @@ nvc0_create_sampler_view(struct pipe_context *pipe,
{
uint32_t flags = 0;
- if (res-target == PIPE_TEXTURE_RECT)
+ if (res-target == PIPE_TEXTURE_RECT || res-target == PIPE_BUFFER)
flags |= NV50_TEXVIEW_SCALED_COORDS;
return nvc0_create_texture_view(pipe, res, templ, flags, res-target);
@@ -122,9 +122,13 @@ nvc0_create_texture_view(struct pipe_context *pipe,
if (desc-colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
tic[2] |= NV50_TIC_2_COLORSPACE_SRGB;
+ if (!(flags NV50_TEXVIEW_SCALED_COORDS))
+ tic[2] |= NV50_TIC_2_NORMALIZED_COORDS;
+
/* check for linear storage type */
if (unlikely(!nouveau_bo_memtype(nv04_resource(texture)-bo))) {
if (texture-target == PIPE_BUFFER) {
+ assert(!(tic[2] NV50_TIC_2_NORMALIZED_COORDS));
address +=
view-pipe.u.buf.first_element * desc-block.bits / 8;
tic[2] |= NV50_TIC_2_LINEAR | NV50_TIC_2_TARGET_BUFFER;
@@ -135,8 +139,6 @@ nvc0_create_texture_view(struct pipe_context *pipe,
} else {
/* must be 2D texture without mip maps */
tic[2] |= NV50_TIC_2_LINEAR | NV50_TIC_2_TARGET_RECT;
- if (texture-target != PIPE_TEXTURE_RECT)
-tic[2] |= NV50_TIC_2_NORMALIZED_COORDS;
tic[3] = mt-level[0].pitch;
tic[4] = mt-base.base.width0;
tic[5] = (1 16) | mt-base.base.height0;
@@ -148,9 +150,6 @@ nvc0_create_texture_view(struct pipe_context *pipe,
return view-pipe;
}
- if (!(flags NV50_TEXVIEW_SCALED_COORDS))
- tic[2] |= NV50_TIC_2_NORMALIZED_COORDS;
-
tic[2] |=
((mt-level[0].tile_mode 0x0f0) (22 - 4)) |
((mt-level[0].tile_mode 0xf00) (25 - 8));
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Mesa (master): nvc0: place staging textures in GART and map them directly
Module: Mesa
Branch: master
Commit: 8e1dd58a7e76834c1fb6d117b6ea5755e05cfb77
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e1dd58a7e76834c1fb6d117b6ea5755e05cfb77
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Wed Apr 3 00:18:55 2013 +0200
nvc0: place staging textures in GART and map them directly
---
src/gallium/drivers/nv50/nv50_miptree.c |6 ++--
src/gallium/drivers/nv50/nv50_resource.h |2 +-
src/gallium/drivers/nvc0/nvc0_2d.xml.h |2 +-
src/gallium/drivers/nvc0/nvc0_miptree.c | 25 ---
src/gallium/drivers/nvc0/nvc0_screen.c |2 +
src/gallium/drivers/nvc0/nvc0_surface.c |3 +-
src/gallium/drivers/nvc0/nvc0_transfer.c | 47 ++
7 files changed, 76 insertions(+), 11 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_miptree.c
b/src/gallium/drivers/nv50/nv50_miptree.c
index ed0f8c2..fe48188 100644
--- a/src/gallium/drivers/nv50/nv50_miptree.c
+++ b/src/gallium/drivers/nv50/nv50_miptree.c
@@ -213,7 +213,7 @@ nv50_miptree_init_ms_mode(struct nv50_miptree *mt)
}
boolean
-nv50_miptree_init_layout_linear(struct nv50_miptree *mt)
+nv50_miptree_init_layout_linear(struct nv50_miptree *mt, unsigned pitch_align)
{
struct pipe_resource *pt = mt-base.base;
const unsigned blocksize = util_format_get_blocksize(pt-format);
@@ -227,7 +227,7 @@ nv50_miptree_init_layout_linear(struct nv50_miptree *mt)
if (mt-ms_x | mt-ms_y)
return FALSE;
- mt-level[0].pitch = align(pt-width0 * blocksize, 64);
+ mt-level[0].pitch = align(pt-width0 * blocksize, pitch_align);
/* Account for very generous prefetch (allocate size as if tiled). */
h = MAX2(h, 8);
@@ -314,7 +314,7 @@ nv50_miptree_create(struct pipe_screen *pscreen,
if (bo_config.nv50.memtype != 0) {
nv50_miptree_init_layout_tiled(mt);
} else
- if (!nv50_miptree_init_layout_linear(mt)) {
+ if (!nv50_miptree_init_layout_linear(mt, 64)) {
FREE(mt);
return NULL;
}
diff --git a/src/gallium/drivers/nv50/nv50_resource.h
b/src/gallium/drivers/nv50/nv50_resource.h
index a2bc980..469d812 100644
--- a/src/gallium/drivers/nv50/nv50_resource.h
+++ b/src/gallium/drivers/nv50/nv50_resource.h
@@ -67,7 +67,7 @@ nv50_miptree(struct pipe_resource *pt)
/* Internal functions:
*/
boolean
-nv50_miptree_init_layout_linear(struct nv50_miptree *mt);
+nv50_miptree_init_layout_linear(struct nv50_miptree *mt, unsigned pitch_align);
struct pipe_resource *
nv50_miptree_create(struct pipe_screen *pscreen,
diff --git a/src/gallium/drivers/nvc0/nvc0_2d.xml.h
b/src/gallium/drivers/nvc0/nvc0_2d.xml.h
index 93dba34..9a488c1 100644
--- a/src/gallium/drivers/nvc0/nvc0_2d.xml.h
+++ b/src/gallium/drivers/nvc0/nvc0_2d.xml.h
@@ -122,7 +122,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
#define NVC0_2D_UNK258 0x0258
-#define NVC0_2D_UNK260 0x0260
+#define NVC0_2D_SINGLE_GPC 0x0260
#define NVC0_2D_COND_ADDRESS_HIGH 0x0264
diff --git a/src/gallium/drivers/nvc0/nvc0_miptree.c
b/src/gallium/drivers/nvc0/nvc0_miptree.c
index 9fcd788..2913363 100644
--- a/src/gallium/drivers/nvc0/nvc0_miptree.c
+++ b/src/gallium/drivers/nvc0/nvc0_miptree.c
@@ -158,9 +158,6 @@ nvc0_miptree_init_ms_mode(struct nv50_miptree *mt)
return TRUE;
}
-boolean
-nv50_miptree_init_layout_linear(struct nv50_miptree *);
-
static void
nvc0_miptree_init_layout_video(struct nv50_miptree *mt)
{
@@ -260,6 +257,21 @@ nvc0_miptree_create(struct pipe_screen *pscreen,
pipe_reference_init(pt-reference, 1);
pt-screen = pscreen;
+ if (pt-usage == PIPE_USAGE_STAGING) {
+ switch (pt-target) {
+ case PIPE_TEXTURE_1D:
+ case PIPE_TEXTURE_2D:
+ case PIPE_TEXTURE_RECT:
+ if (pt-last_level == 0
+ !util_format_is_depth_or_stencil(pt-format)
+ pt-nr_samples = 1)
+pt-flags |= NOUVEAU_RESOURCE_FLAG_LINEAR;
+ break;
+ default:
+ break;
+ }
+ }
+
bo_config.nvc0.memtype = nvc0_mt_choose_storage_type(mt, compressed);
if (!nvc0_miptree_init_ms_mode(mt)) {
@@ -273,13 +285,16 @@ nvc0_miptree_create(struct pipe_screen *pscreen,
if (likely(bo_config.nvc0.memtype)) {
nvc0_miptree_init_layout_tiled(mt);
} else
- if (!nv50_miptree_init_layout_linear(mt)) {
+ if (!nv50_miptree_init_layout_linear(mt, 128)) {
FREE(mt);
return NULL;
}
bo_config.nvc0.tile_mode = mt-level[0].tile_mode;
- mt-base.domain = NOUVEAU_BO_VRAM;
+ if (!bo_config.nvc0.memtype pt-usage == PIPE_USAGE_STAGING)
+ mt-base.domain = NOUVEAU_BO_GART;
+ else
+ mt-base.domain = NOUVEAU_BO_VRAM;
bo_flags = mt-base.domain | NOUVEAU_BO_NOSNOOP;
diff --git a/src/gallium/drivers/nvc0/nvc0_screen.c
b/src/gallium/drivers/nvc0/nvc0_screen.c
index 3a32539..a46fb38
Mesa (master): nvc0: fix 128 bit compressed storage type selection
Module: Mesa
Branch: master
Commit: 4de70bf43c5715711b1d287590470df16e6cf837
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4de70bf43c5715711b1d287590470df16e6cf837
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Wed Apr 3 01:17:46 2013 +0200
nvc0: fix 128 bit compressed storage type selection
---
src/gallium/drivers/nvc0/nvc0_miptree.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_miptree.c
b/src/gallium/drivers/nvc0/nvc0_miptree.c
index 2913363..3d50735 100644
--- a/src/gallium/drivers/nvc0/nvc0_miptree.c
+++ b/src/gallium/drivers/nvc0/nvc0_miptree.c
@@ -82,7 +82,7 @@ nvc0_mt_choose_storage_type(struct nv50_miptree *mt, boolean
compressed)
switch (util_format_get_blocksizebits(mt-base.base.format)) {
case 128:
if (compressed)
-tile_flags = 0xf4 + ms;
+tile_flags = 0xf4 + ms * 2;
else
tile_flags = 0xfe;
break;
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Mesa (master): nv50,nvc0: remove MS resolve formats hack
Module: Mesa
Branch: master
Commit: 80eef069f032af921554ba0e03062d84488d3f6c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=80eef069f032af921554ba0e03062d84488d3f6c
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Wed Apr 3 13:19:15 2013 +0200
nv50,nvc0: remove MS resolve formats hack
Mesa now allows BlitFramebuffer resolve between RGBA and BGRA.
---
src/gallium/drivers/nv50/nv50_screen.c |5 -
src/gallium/drivers/nvc0/nvc0_screen.c | 10 --
2 files changed, 0 insertions(+), 15 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_screen.c
b/src/gallium/drivers/nv50/nv50_screen.c
index 53eeeb6..55081be 100644
--- a/src/gallium/drivers/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nv50/nv50_screen.c
@@ -65,11 +65,6 @@ nv50_screen_is_format_supported(struct pipe_screen *pscreen,
if (nv50_screen(pscreen)-tesla-oclass NVA0_3D_CLASS)
return FALSE;
break;
- case PIPE_FORMAT_R8G8B8A8_UNORM:
- case PIPE_FORMAT_R8G8B8X8_UNORM:
- /* HACK: GL requires equal formats for MS resolve and window is BGRA */
- if (bindings PIPE_BIND_RENDER_TARGET)
- return FALSE;
default:
break;
}
diff --git a/src/gallium/drivers/nvc0/nvc0_screen.c
b/src/gallium/drivers/nvc0/nvc0_screen.c
index a46fb38..f2dd65b 100644
--- a/src/gallium/drivers/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nvc0/nvc0_screen.c
@@ -51,16 +51,6 @@ nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
if (!util_format_is_supported(format, bindings))
return FALSE;
- switch (format) {
- case PIPE_FORMAT_R8G8B8A8_UNORM:
- case PIPE_FORMAT_R8G8B8X8_UNORM:
- /* HACK: GL requires equal formats for MS resolve and window is BGRA */
- if (bindings PIPE_BIND_RENDER_TARGET)
- return FALSE;
- default:
- break;
- }
-
if ((bindings PIPE_BIND_SAMPLER_VIEW) (target != PIPE_BUFFER))
if (util_format_get_blocksizebits(format) == 3 * 32)
return FALSE;
___
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Mesa (master): nv50: fix 3D render target setup
Module: Mesa
Branch: master
Commit: 090e73fc4642dfedb9ac46259572135229c8199e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=090e73fc4642dfedb9ac46259572135229c8199e
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Mon Mar 25 19:41:18 2013 +0100
nv50: fix 3D render target setup
---
src/gallium/drivers/nv50/nv50_state_validate.c | 12 ++--
1 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_state_validate.c
b/src/gallium/drivers/nv50/nv50_state_validate.c
index a95e96d..f5e7b36 100644
--- a/src/gallium/drivers/nv50/nv50_state_validate.c
+++ b/src/gallium/drivers/nv50/nv50_state_validate.c
@@ -9,6 +9,7 @@ nv50_validate_fb(struct nv50_context *nv50)
struct pipe_framebuffer_state *fb = nv50-framebuffer;
unsigned i;
unsigned ms_mode = NV50_3D_MULTISAMPLE_MODE_MS1;
+ uint32_t array_size = 0x, array_mode = 0;
nouveau_bufctx_reset(nv50-bufctx_3d, NV50_BIND_FB);
@@ -23,6 +24,13 @@ nv50_validate_fb(struct nv50_context *nv50)
struct nv50_surface *sf = nv50_surface(fb-cbufs[i]);
struct nouveau_bo *bo = mt-base.bo;
+ array_size = MIN2(array_size, sf-depth);
+ if (mt-layout_3d)
+ array_mode = NV50_3D_RT_ARRAY_MODE_MODE_3D; /* 1 16 */
+
+ /* can't mix 3D with ARRAY or have RTs of different depth/array_size */
+ assert(mt-layout_3d || !array_mode || array_size == 1);
+
BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(i)), 5);
PUSH_DATAh(push, bo-offset + sf-offset);
PUSH_DATA (push, bo-offset + sf-offset);
@@ -34,7 +42,7 @@ nv50_validate_fb(struct nv50_context *nv50)
PUSH_DATA (push, sf-width);
PUSH_DATA (push, sf-height);
BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
- PUSH_DATA (push, sf-depth);
+ PUSH_DATA (push, array_mode | array_size);
} else {
PUSH_DATA (push, 0);
PUSH_DATA (push, 0);
@@ -63,7 +71,7 @@ nv50_validate_fb(struct nv50_context *nv50)
struct nv50_miptree *mt = nv50_miptree(fb-zsbuf-texture);
struct nv50_surface *sf = nv50_surface(fb-zsbuf);
struct nouveau_bo *bo = mt-base.bo;
- int unk = mt-base.base.target == PIPE_TEXTURE_2D;
+ int unk = mt-base.base.target == PIPE_TEXTURE_3D || sf-depth == 1;
BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
PUSH_DATAh(push, bo-offset + sf-offset);
___
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Mesa (master): nvc0: use NOUVEAU_GETPARAM_GRAPH_UNITS to get MP count
Module: Mesa
Branch: master
Commit: 25722e3454fb179933514f3a1b76e0f4662875bd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=25722e3454fb179933514f3a1b76e0f4662875bd
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Wed Mar 27 23:38:29 2013 +0100
nvc0: use NOUVEAU_GETPARAM_GRAPH_UNITS to get MP count
---
src/gallium/drivers/nvc0/nvc0_screen.c | 63 +--
src/gallium/drivers/nvc0/nvc0_screen.h |5 ++-
src/gallium/drivers/nvc0/nve4_compute.c | 12 +++---
src/gallium/drivers/nvc0/nve4_compute.xml.h | 22 ++
4 files changed, 73 insertions(+), 29 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_screen.c
b/src/gallium/drivers/nvc0/nvc0_screen.c
index b6cf2ca..b5b4ef1 100644
--- a/src/gallium/drivers/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nvc0/nvc0_screen.c
@@ -32,6 +32,10 @@
#include nvc0_graph_macros.h
+#ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
+# define NOUVEAU_GETPARAM_GRAPH_UNITS 13
+#endif
+
static boolean
nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
enum pipe_format format,
@@ -494,6 +498,35 @@ nvc0_screen_init_compute(struct nvc0_screen *screen)
}
}
+boolean
+nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
+uint32_t lpos, uint32_t lneg, uint32_t cstack)
+{
+ struct nouveau_bo *bo = NULL;
+ int ret;
+ uint64_t size = (lpos + lneg) * 32 + cstack;
+
+ if (size = (1 20)) {
+ NOUVEAU_ERR(requested TLS size too large: 0x%PRIx64\n, size);
+ return FALSE;
+ }
+
+ size *= (screen-base.device-chipset = 0xe0) ? 64 : 48; /* max warps */
+ size *= screen-mp_count;
+
+ size = align(size, 1 17);
+
+ ret = nouveau_bo_new(screen-base.device, NOUVEAU_BO_VRAM, 1 17, size,
+NULL, bo);
+ if (ret) {
+ NOUVEAU_ERR(failed to allocate TLS area, size: 0x%PRIx64\n, size);
+ return FALSE;
+ }
+ nouveau_bo_ref(NULL, screen-tls);
+ screen-tls = bo;
+ return TRUE;
+}
+
#define FAIL_SCREEN_INIT(str, err)\
do { \
NOUVEAU_ERR(str, err); \
@@ -508,6 +541,7 @@ nvc0_screen_create(struct nouveau_device *dev)
struct pipe_screen *pscreen;
struct nouveau_object *chan;
struct nouveau_pushbuf *push;
+ uint64_t value;
uint32_t obj_class;
int ret;
unsigned i;
@@ -733,18 +767,21 @@ nvc0_screen_create(struct nouveau_device *dev)
PUSH_DATAh(push, screen-uniform_bo-offset + (5 16) + (6 9));
PUSH_DATA (push, screen-uniform_bo-offset + (5 16) + (6 9));
- /* max MPs * max warps per MP (TODO: ask kernel) */
- if (screen-eng3d-oclass = NVE4_3D_CLASS)
- screen-tls_size = 8 * 64 * 32;
- else
- screen-tls_size = 16 * 48 * 32;
- screen-tls_size *= NVC0_CAP_MAX_PROGRAM_TEMPS * 16;
- screen-tls_size = align(screen-tls_size, 1 17);
+ if (dev-drm_version = 0x01000101) {
+ ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, value);
+ if (ret) {
+ NOUVEAU_ERR(NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n);
+ goto fail;
+ }
+ } else {
+ if (dev-chipset = 0xe0 dev-chipset 0xf0)
+ value = (8 8) | 4;
+ else
+ value = (16 8) | 4;
+ }
+ screen-mp_count = value 8;
- ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 17,
-screen-tls_size, NULL, screen-tls);
- if (ret)
- goto fail;
+ nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
PUSH_DATAh(push, screen-text-offset);
@@ -752,8 +789,8 @@ nvc0_screen_create(struct nouveau_device *dev)
BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
PUSH_DATAh(push, screen-tls-offset);
PUSH_DATA (push, screen-tls-offset);
- PUSH_DATA (push, screen-tls_size 32);
- PUSH_DATA (push, screen-tls_size);
+ PUSH_DATA (push, screen-tls-size 32);
+ PUSH_DATA (push, screen-tls-size);
BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
PUSH_DATA (push, 0);
BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
diff --git a/src/gallium/drivers/nvc0/nvc0_screen.h
b/src/gallium/drivers/nvc0/nvc0_screen.h
index 16f0feb..13dc83e 100644
--- a/src/gallium/drivers/nvc0/nvc0_screen.h
+++ b/src/gallium/drivers/nvc0/nvc0_screen.h
@@ -38,7 +38,7 @@ struct nvc0_screen {
struct nouveau_bo *txc; /* TIC (offset 0) and TSC (65536) */
struct nouveau_bo *poly_cache;
- uint64_t tls_size;
+ uint16_t mp_count;
struct nouveau_heap *text_heap;
struct nouveau_heap *lib_code; /* allocated from text_heap */
@@ -86,6 +86,9 @@ int nvc0_screen_tsc_alloc(struct nvc0_screen *, void *);
int nve4_screen_compute_setup(struct nvc0_screen *, struct nouveau_pushbuf *);
+boolean nvc0_screen_resize_tls_area(struct nvc0_screen *, uint32_t lpos,
+uint32_t lneg, uint32_t cstack);
+
static INLINE void
nvc0_resource_fence
Mesa (master): nv50,nvc0: fix 3d blits, restore viewport after blit
Module: Mesa
Branch: master
Commit: 443b247878edd6a67adc073b0c36e2941436b9a0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=443b247878edd6a67adc073b0c36e2941436b9a0
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Fri Mar 22 13:49:40 2013 +0100
nv50,nvc0: fix 3d blits, restore viewport after blit
---
src/gallium/drivers/nv50/nv50_surface.c |8 -
src/gallium/drivers/nvc0/nvc0_surface.c | 42 +++---
2 files changed, 32 insertions(+), 18 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_surface.c
b/src/gallium/drivers/nv50/nv50_surface.c
index 117d3d1..b29a736 100644
--- a/src/gallium/drivers/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nv50/nv50_surface.c
@@ -935,7 +935,7 @@ nv50_blit_3d(struct nv50_context *nv50, const struct
pipe_blit_info *info)
nv50_blit_select_fp(blit, info);
nv50_blitctx_pre_blit(blit);
- nv50_blit_set_dst(blit, dst, info-dst.level, 0, info-dst.format);
+ nv50_blit_set_dst(blit, dst, info-dst.level, -1, info-dst.format);
nv50_blit_set_src(blit, src, info-src.level, -1, info-src.format,
blit-filter);
@@ -1223,10 +1223,14 @@ nv50_blit(struct pipe_context *pipe, const struct
pipe_blit_info *info)
debug_printf(blit: cannot filter array or cube textures in z
direction);
}
- if (!eng3d info-dst.format != info-src.format)
+ if (!eng3d info-dst.format != info-src.format) {
if (!nv50_2d_format_faithful(info-dst.format) ||
!nv50_2d_format_faithful(info-src.format))
eng3d = TRUE;
+ if (info-dst.format == PIPE_FORMAT_R8_UNORM ||
+ info-dst.format == PIPE_FORMAT_R16_UNORM)
+ eng3d = TRUE;
+ }
if (info-src.resource-nr_samples == 8
info-dst.resource-nr_samples = 1)
diff --git a/src/gallium/drivers/nvc0/nvc0_surface.c
b/src/gallium/drivers/nvc0/nvc0_surface.c
index cd4e3a7..8ed9223 100644
--- a/src/gallium/drivers/nvc0/nvc0_surface.c
+++ b/src/gallium/drivers/nvc0/nvc0_surface.c
@@ -492,19 +492,19 @@ nvc0_blitter_make_vp(struct nvc0_blitter *blit)
{
static const uint32_t code_nvc0[] =
{
- 0xfff01c66, 0x0680, /* vfetch b128 { $r0 $r1 $r2 $r3 } a[0x80] */
- 0xfff11c26, 0x0690, /* vfetch b96 { $r4 $r5 $r6 } a[0x90]*/
- 0x03f01c66, 0x0a7e0070, /* export b128 o[0x70] { $r0 $r1 $r2 $r3 } */
- 0x13f01c26, 0x0a7e0080, /* export b96 o[0x80] { $r4 $r5 $r6 } */
+ 0xfff11c26, 0x0680, /* vfetch b64 $r4:$r5 a[0x80] */
+ 0xfff01c46, 0x0690, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
+ 0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
+ 0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
0x1de7, 0x8000, /* exit */
};
static const uint32_t code_nve4[] =
{
0x0007, 0x2000, /* sched */
- 0xfff01c66, 0x0680, /* vfetch b128 { $r0 $r1 $r2 $r3 } a[0x80] */
- 0xfff11c46, 0x0690, /* vfetch b96 { $r4 $r5 $r6 } a[0x90]*/
- 0x03f01c66, 0x0a7e0070, /* export b128 o[0x70] { $r0 $r1 $r2 $r3 } */
- 0x13f01c46, 0x0a7e0080, /* export b96 o[0x80] { $r4 $r5 $r6 } */
+ 0xfff11c26, 0x0680, /* vfetch b64 $r4:$r5 a[0x80] */
+ 0xfff01c46, 0x0690, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
+ 0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
+ 0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
0x1de7, 0x8000, /* exit */
};
@@ -517,13 +517,13 @@ nvc0_blitter_make_vp(struct nvc0_blitter *blit)
blit-vp.code = (uint32_t *)code_nvc0; /* const_cast */
blit-vp.code_size = sizeof(code_nvc0);
}
- blit-vp.num_gprs = 7;
+ blit-vp.num_gprs = 6;
blit-vp.vp.edgeflag = PIPE_MAX_ATTRIBS;
blit-vp.hdr[0] = 0x00020461; /* vertprog magic */
blit-vp.hdr[4] = 0x000ff000; /* no outputs read */
- blit-vp.hdr[6] = 0x003f; /* a[0x80], a[0x90] */
- blit-vp.hdr[13] = 0x0003f000; /* o[0x70], o[0x80] */
+ blit-vp.hdr[6] = 0x0073; /* a[0x80].xy, a[0x90].xyz */
+ blit-vp.hdr[13] = 0x00073000; /* o[0x70].xy, o[0x80].xyz */
}
static void
@@ -828,7 +828,7 @@ nvc0_blit_3d(struct nvc0_context *nvc0, const struct
pipe_blit_info *info)
nvc0_blit_select_fp(blit, info);
nvc0_blitctx_pre_blit(blit);
- nvc0_blit_set_dst(blit, dst, info-dst.level, 0, info-dst.format);
+ nvc0_blit_set_dst(blit, dst, info-dst.level, -1, info-dst.format);
nvc0_blit_set_src(blit, src, info-src.level, -1, info-src.format,
blit-filter);
@@ -933,11 +933,14 @@ nvc0_blit_3d(struct nvc0_context *nvc0, const struct
pipe_blit_info *info)
if (info-dst.box.z + info-dst.box.depth - 1)
IMMED_NVC0(push, NVC0_3D(LAYER), 0);
- /* re-enable normally constant state */
+ nvc0_blitctx_post_blit(blit);
- IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
+ /* restore viewport */
- nvc0_blitctx_post_blit(blit);
+ BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(0)), 2);
+ PUSH_DATA (push, nvc0
Mesa (master): nvc0: enable compression when supported
Module: Mesa
Branch: master
Commit: 480359bcf644c496c5318e89fe7ad60d95772acd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=480359bcf644c496c5318e89fe7ad60d95772acd
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Thu Mar 21 19:26:01 2013 +0100
nvc0: enable compression when supported
---
src/gallium/drivers/nvc0/nvc0_3d.xml.h |6 ++
src/gallium/drivers/nvc0/nvc0_miptree.c |5 ++---
src/gallium/drivers/nvc0/nvc0_screen.c |5 +
3 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_3d.xml.h
b/src/gallium/drivers/nvc0/nvc0_3d.xml.h
index 1cf1f96..44f96a2 100644
--- a/src/gallium/drivers/nvc0/nvc0_3d.xml.h
+++ b/src/gallium/drivers/nvc0/nvc0_3d.xml.h
@@ -1139,6 +1139,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
#define NVC0_3D_LOGIC_OP_NAND 0x150e
#define NVC0_3D_LOGIC_OP_SET 0x150f
+#define NVC0_3D_ZETA_COMP_ENABLE 0x19cc
+
#define NVC0_3D_CLEAR_BUFFERS 0x19d0
#define NVC0_3D_CLEAR_BUFFERS_Z
0x0001
#define NVC0_3D_CLEAR_BUFFERS_S
0x0002
@@ -1153,6 +1155,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
#define NVC0_3D_CLIPID_FILL0x19d4
+#define NVC0_3D_RT_COMP_ENABLE(i0)(0x19e0 +
0x4*(i0))
+#define NVC0_3D_RT_COMP_ENABLE__ESIZE 0x0004
+#define NVC0_3D_RT_COMP_ENABLE__LEN0x0008
+
#define NVC0_3D_COLOR_MASK(i0)(0x1a00 +
0x4*(i0))
#define NVC0_3D_COLOR_MASK__ESIZE 0x0004
#define NVC0_3D_COLOR_MASK__LEN
0x0008
diff --git a/src/gallium/drivers/nvc0/nvc0_miptree.c
b/src/gallium/drivers/nvc0/nvc0_miptree.c
index 8c4d724..1136804 100644
--- a/src/gallium/drivers/nvc0/nvc0_miptree.c
+++ b/src/gallium/drivers/nvc0/nvc0_miptree.c
@@ -41,8 +41,6 @@ nvc0_mt_choose_storage_type(struct nv50_miptree *mt, boolean
compressed)
uint32_t tile_flags;
- compressed = FALSE; /* not yet supported */
-
if (unlikely(mt-base.base.bind PIPE_BIND_CURSOR))
return 0;
if (unlikely(mt-base.base.flags NOUVEAU_RESOURCE_FLAG_LINEAR))
@@ -247,6 +245,7 @@ nvc0_miptree_create(struct pipe_screen *pscreen,
struct nouveau_device *dev = nouveau_screen(pscreen)-device;
struct nv50_miptree *mt = CALLOC_STRUCT(nv50_miptree);
struct pipe_resource *pt = mt-base.base;
+ boolean compressed = dev-drm_version = 0x01000101;
int ret;
union nouveau_bo_config bo_config;
uint32_t bo_flags;
@@ -259,7 +258,7 @@ nvc0_miptree_create(struct pipe_screen *pscreen,
pipe_reference_init(pt-reference, 1);
pt-screen = pscreen;
- bo_config.nvc0.memtype = nvc0_mt_choose_storage_type(mt, TRUE);
+ bo_config.nvc0.memtype = nvc0_mt_choose_storage_type(mt, compressed);
if (!nvc0_miptree_init_ms_mode(mt)) {
FREE(mt);
diff --git a/src/gallium/drivers/nvc0/nvc0_screen.c
b/src/gallium/drivers/nvc0/nvc0_screen.c
index b5b4ef1..bf353c4 100644
--- a/src/gallium/drivers/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nvc0/nvc0_screen.c
@@ -677,6 +677,11 @@ nvc0_screen_create(struct nouveau_device *dev)
PUSH_DATA (push, 0x17);
}
+ IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev-drm_version = 0x01000101);
+ BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
+ for (i = 0; i 8; ++i)
+ PUSH_DATA(push, dev-drm_version = 0x01000101);
+
BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
PUSH_DATA (push, 1);
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Mesa (master): nvc0: implement MP performance counters
Module: Mesa
Branch: master
Commit: ee624ced364bfd2f896809874ef3a808a11c5ecf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee624ced364bfd2f896809874ef3a808a11c5ecf
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Wed Mar 27 23:39:06 2013 +0100
nvc0: implement MP performance counters
There's more, but this only adds (most) of the counters that are
handled directly by the shader processors.
The other counter domains are not handled on the multiprocessor and
there are no FIFO object methods for configuring them.
Instead, they have to be programmed by the kernel via PCOUNTER, and
the interface for this isn't in place yet.
---
src/gallium/drivers/nvc0/nvc0_context.h |3 +-
src/gallium/drivers/nvc0/nvc0_program.c |6 +-
src/gallium/drivers/nvc0/nvc0_query.c | 393 ++-
src/gallium/drivers/nvc0/nvc0_screen.c |6 +
src/gallium/drivers/nvc0/nvc0_screen.h | 71 +
src/gallium/drivers/nvc0/nvc0_winsys.h |2 +
src/gallium/drivers/nvc0/nve4_compute.c | 11 +-
src/gallium/drivers/nvc0/nve4_compute.xml.h | 70 +
8 files changed, 556 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_context.h
b/src/gallium/drivers/nvc0/nvc0_context.h
index d9aa378..799d9b9 100644
--- a/src/gallium/drivers/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nvc0/nvc0_context.h
@@ -84,7 +84,8 @@
#define NVC0_BIND_CP_GLOBAL 49
#define NVC0_BIND_CP_DESC50
#define NVC0_BIND_CP_SCREEN 51
-#define NVC0_BIND_CP_COUNT 52
+#define NVC0_BIND_CP_QUERY 52
+#define NVC0_BIND_CP_COUNT 53
/* bufctx for other operations */
#define NVC0_BIND_2D0
diff --git a/src/gallium/drivers/nvc0/nvc0_program.c
b/src/gallium/drivers/nvc0/nvc0_program.c
index 22dfaf9..15f683c 100644
--- a/src/gallium/drivers/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nvc0/nvc0_program.c
@@ -777,8 +777,8 @@ nvc0_program_destroy(struct nvc0_context *nvc0, struct
nvc0_program *prog)
if (prog-mem)
nouveau_heap_free(prog-mem);
-
- FREE(prog-code);
+ if (prog-code)
+ FREE(prog-code); /* may be 0 for hardcoded shaders */
FREE(prog-immd_data);
FREE(prog-relocs);
if (prog-type == PIPE_SHADER_COMPUTE prog-cp.syms)
@@ -807,5 +807,5 @@ nvc0_program_symbol_offset(const struct nvc0_program *prog,
uint32_t label)
for (i = 0; i prog-cp.num_syms; ++i)
if (syms[i].label == label)
return prog-code_base + base + syms[i].offset;
- return ~0;
+ return prog-code_base; /* no symbols or symbol not found */
}
diff --git a/src/gallium/drivers/nvc0/nvc0_query.c
b/src/gallium/drivers/nvc0/nvc0_query.c
index d329148..5c4431e 100644
--- a/src/gallium/drivers/nvc0/nvc0_query.c
+++ b/src/gallium/drivers/nvc0/nvc0_query.c
@@ -26,6 +26,7 @@
#include nvc0_context.h
#include nouveau/nv_object.xml.h
+#include nve4_compute.xml.h
#define NVC0_QUERY_STATE_READY 0
#define NVC0_QUERY_STATE_ACTIVE 1
@@ -36,6 +37,7 @@ struct nvc0_query {
uint32_t *data;
uint16_t type;
uint16_t index;
+ int8_t ctr[4];
uint32_t sequence;
struct nouveau_bo *bo;
uint32_t base;
@@ -49,6 +51,11 @@ struct nvc0_query {
#define NVC0_QUERY_ALLOC_SPACE 256
+static void nve4_mp_pm_query_begin(struct nvc0_context *, struct nvc0_query *);
+static void nve4_mp_pm_query_end(struct nvc0_context *, struct nvc0_query *);
+static boolean nve4_mp_pm_query_result(struct nvc0_context *,
+ struct nvc0_query *, void *, boolean);
+
static INLINE struct nvc0_query *
nvc0_query(struct pipe_query *pipe)
{
@@ -132,6 +139,16 @@ nvc0_query_create(struct pipe_context *pipe, unsigned type)
space = 16;
break;
default:
+ if (nvc0-screen-base.class_3d = NVE4_3D_CLASS
+ nvc0-screen-base.device-drm_version = 0x01000101) {
+ if (type = NVE4_PM_QUERY(0)
+ type = NVE4_PM_QUERY_MAX) {
+/* 8 counters per MP + clock */
+space = 12 * nvc0-screen-mp_count * sizeof(uint32_t);
+break;
+ }
+ }
+ debug_printf(invalid query type: %u\n, type);
FREE(q);
return NULL;
}
@@ -244,6 +261,8 @@ nvc0_query_begin(struct pipe_context *pipe, struct
pipe_query *pq)
nvc0_query_get(push, q, 0xc0 + 0x90, 0x0e809002); /* TEP, LAUNCHES */
break;
default:
+ if (q-type = NVE4_PM_QUERY(0) q-type = NVE4_PM_QUERY_MAX)
+ nve4_mp_pm_query_begin(nvc0, q);
break;
}
q-state = NVC0_QUERY_STATE_ACTIVE;
@@ -314,7 +333,8 @@ nvc0_query_end(struct pipe_context *pipe, struct pipe_query
*pq)
nvc0_query_get(push, q, 0x00, 0x0d005002 | (q-index 5));
break;
default:
- assert(0);
+ if (q-type = NVE4_PM_QUERY(0) q-type = NVE4_PM_QUERY_MAX)
+ nve4_mp_pm_query_end(nvc0, q);
break;
}
}
@@ -343,6 +363,9 @@ nvc0_query_result(struct pipe_context *pipe, struct
pipe_query *pq
Mesa (master): nvc0: fix max varying count, move CLIPVERTEX, FOG out of the way
Module: Mesa
Branch: master
Commit: 529dbbfcf7a674f2d82eed5e88ce92615721d5f2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=529dbbfcf7a674f2d82eed5e88ce92615721d5f2
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Fri Mar 15 23:39:01 2013 +0100
nvc0: fix max varying count, move CLIPVERTEX,FOG out of the way
The card spews an error if I use all 128 generic slots.
Apparently the real limit isn't just dictated by the address space
layout.
---
.../drivers/nv50/codegen/nv50_ir_from_tgsi.cpp | 23 +++
src/gallium/drivers/nvc0/nvc0_program.c| 13 +++
src/gallium/drivers/nvc0/nvc0_screen.c | 12 -
3 files changed, 36 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
b/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
index 613187c..b546429 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
@@ -1009,7 +1009,9 @@ bool Source::scanInstruction(const struct
tgsi_full_instruction *inst)
else
info-out[dst.getIndex(0)].mask |= dst.getMask();
- if (info-out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PSIZE)
+ if (info-out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PSIZE ||
+ info-out[dst.getIndex(0)].sn == TGSI_SEMANTIC_PRIMID ||
+ info-out[dst.getIndex(0)].sn == TGSI_SEMANTIC_FOG)
info-out[dst.getIndex(0)].mask = 1;
if (isEdgeFlagPassthrough(insn))
@@ -1040,14 +1042,25 @@ bool Source::scanInstruction(const struct
tgsi_full_instruction *inst)
for (unsigned i = 0; i info-numInputs; ++i)
info-in[i].mask = 0xf;
} else {
+ const int i = src.getIndex(0);
for (unsigned c = 0; c 4; ++c) {
if (!(mask (1 c)))
continue;
int k = src.getSwizzle(c);
-int i = src.getIndex(0);
-if (info-in[i].sn != TGSI_SEMANTIC_FOG || k == TGSI_SWIZZLE_X)
- if (k = TGSI_SWIZZLE_W)
- info-in[i].mask |= 1 k;
+if (k = TGSI_SWIZZLE_W)
+ info-in[i].mask |= 1 k;
+ }
+ switch (info-in[i].sn) {
+ case TGSI_SEMANTIC_PSIZE:
+ case TGSI_SEMANTIC_PRIMID:
+ case TGSI_SEMANTIC_FOG:
+info-in[i].mask = 0x1;
+break;
+ case TGSI_SEMANTIC_PCOORD:
+info-in[i].mask = 0x3;
+break;
+ default:
+break;
}
}
}
diff --git a/src/gallium/drivers/nvc0/nvc0_program.c
b/src/gallium/drivers/nvc0/nvc0_program.c
index 2f1b417..22dfaf9 100644
--- a/src/gallium/drivers/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nvc0/nvc0_program.c
@@ -27,6 +27,9 @@
#include nv50/codegen/nv50_ir_driver.h
#include nve4_compute.h
+/* NOTE: Using a[0x270] in FP may cause an error even if we're using less than
+ * 124 scalar varying values.
+ */
static uint32_t
nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
{
@@ -36,12 +39,12 @@ nvc0_shader_input_address(unsigned sn, unsigned si,
unsigned ubase)
case TGSI_SEMANTIC_PSIZE:return 0x06c;
case TGSI_SEMANTIC_POSITION: return 0x070;
case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
- case TGSI_SEMANTIC_FOG: return 0x270;
+ case TGSI_SEMANTIC_FOG: return 0x2e8;
case TGSI_SEMANTIC_COLOR:return 0x280 + si * 0x10;
case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
case NV50_SEMANTIC_CLIPDISTANCE: return 0x2c0 + si * 0x4;
case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
- case TGSI_SEMANTIC_CLIPVERTEX: return 0x260;
+ case TGSI_SEMANTIC_CLIPVERTEX: return 0x270;
case TGSI_SEMANTIC_PCOORD: return 0x2e0;
case NV50_SEMANTIC_TESSCOORD:return 0x2f0;
case TGSI_SEMANTIC_INSTANCEID: return 0x2f8;
@@ -66,12 +69,12 @@ nvc0_shader_output_address(unsigned sn, unsigned si,
unsigned ubase)
case TGSI_SEMANTIC_PSIZE: return 0x06c;
case TGSI_SEMANTIC_POSITION: return 0x070;
case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
- case TGSI_SEMANTIC_FOG: return 0x270;
+ case TGSI_SEMANTIC_FOG: return 0x2e8;
case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
case TGSI_SEMANTIC_BCOLOR:return 0x2a0 + si * 0x10;
case NV50_SEMANTIC_CLIPDISTANCE: return 0x2c0 + si * 0x4;
case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
- case TGSI_SEMANTIC_CLIPVERTEX:return 0x260;
+ case TGSI_SEMANTIC_CLIPVERTEX:return 0x270;
case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
case TGSI_SEMANTIC_EDGEFLAG: return ~0;
default:
@@ -440,7 +443,7 @@ nvc0_fp_gen_header(struct nvc0_program *fp, struct
nv50_ir_prog_info *info)
} else
if (info-in[i].slot[0] = (0x2c0 / 4)
info
Mesa (master): 54 new commits
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8aa8b0539eda00b9bafacb69774b26975db66ae4 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Mon Mar 11 20:53:25 2013 +0100 nvc0: avoid crash on updating RASTERIZE_ENABLE state When doing a blit with the 3D engine, the rasterizer or zsa cso may be NULL. URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4d28aff48fb8e93e2faf2ed042663f7c32c5af7b Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Fri Mar 1 16:45:47 2013 +0100 gallium/tests: check format in compute tests, make selectable URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2dded78ea9209a11897e178d5f585f66262ce1e Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Sat Mar 9 17:17:14 2013 +0100 nvc0: add MP trap handler for nve4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae59a7d35d2b6f23634617dc91e1baf85c9d6d81 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Sat Mar 9 12:11:38 2013 +0100 nvc0: they removed the NTID,NCTAID,GRIDID registers on nve4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e066f2f62f6043d43385bcdce4e7fa07ffa3ecbe Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Sat Feb 23 19:40:23 2013 +0100 nvc0: implement compute support for nve4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=75f1f852b00ad0d766684d01695322b93a2acd55 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Mon Mar 11 17:34:43 2013 +0100 nvc0/ir: try to fix CAS (CompareAndSwap) URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=18fdfbdc32f204d6728c1ad57a693b1a6ad0aec9 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Mon Mar 11 17:34:05 2013 +0100 nv50/ir: add CCTL (cache control) op URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9db7e09cb4db2bbd11edf40c77d3becad649fc53 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Mon Mar 11 17:32:52 2013 +0100 nvc0/ir/emit: fix emission of large address offsets URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=175c185941944fbfde20c08d79e83041c26a7cd5 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Fri Mar 8 22:40:30 2013 +0100 nvc0: add SHADER/COMPUTE_RESOURCE bind flags to format table URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=19ea0bd5217fc486dcd2de756872e1ce4e3064b7 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Sat Mar 2 18:27:56 2013 +0100 nouveau: align PIPE_BIND_SHADER,COMPUTE_RESOURCEs to 256 bytes URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=47f2179844bd21f8112367ef8ed0acead7160f10 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Fri Mar 1 21:37:37 2013 +0100 nv50,nvc0: copy writable flag on surface creation URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a91d3a2a4c4e7851fdb46465224213ce1874c9b Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Sat Mar 2 21:00:26 2013 +0100 nv50/ir: add support for different sampler and resource index on nve4 And remove non-working code for indirect sampler/resource selection. Will be added back later. Includes code from nv50/ir/tgsi: Resource indirect indexing by Francisco Jerez (when mixing the R and S handles we can only specify them via a register, i.e. indirectly, unless we upload all the used handle combinations to c[] space, which we don't for now). URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=99e4eba669f13a0dc80880f4f91e2338377c1667 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Sat Mar 2 14:59:06 2013 +0100 nv50/ir: implement splitting of 64 bit ops after RA URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac9f19e485a15b2c58680d5c884597f60d6f1b1b Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Thu Feb 28 22:08:36 2013 +0100 nvc0/ir: skip back edges when determining latest sched value URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f07c46a4f425d1075e79ad1bba424f6921e37cc8 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Thu Feb 28 19:07:24 2013 +0100 nvc0/ir: use large issue delay after RET, too URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b23ec3f8ba1230679d0188e5bf00270bf238b826 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Thu Feb 28 19:00:02 2013 +0100 nv50/ir: fix size adjustment for sched info for multiple functions URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d39169cb6dd25f92e62254aa3920c2add2b3ca25 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Wed Feb 27 21:02:29 2013 +0100 nv50/ir: print function inputs and outputs URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b4faa2b1717225a0c7b08a227436091d5fdceaf Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Wed Feb 27 15:32:35 2013 +0100 nv50/ir/ssa: add
Mesa (master): mesa: implement GL_ARB_texture_buffer_range
Module: Mesa
Branch: master
Commit: 785a8c3bebac838b675ac891aaadff4efcb504d8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=785a8c3bebac838b675ac891aaadff4efcb504d8
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Fri Jan 25 14:54:05 2013 +0100
mesa: implement GL_ARB_texture_buffer_range
v2: Record texObj.BufferSize as -1 in TexBuffer(non-Range) instead
of the buffer's current size so we know we always have to use the
full size of the buffer object (i.e. even if it changes without the
user calling TexBuffer again) for the texture.
Clarify invalid offset alignment error message.
v3: Use extra GL_CORE-only section in get_hash_params.py for
TEXTURE_BUFFER_OFFSET_ALIGNMENT.
v4: Remove unnecessary check for profile in _mesa_TexBufferRange.
Add check for extension enable in get_tex_level_parameter_buffer.
v5: Fix position in gl_API.xml.
Add comment about meaning of BufferSize == -1.
v6: Add back checks for core profile and add a note about it.
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mapi/glapi/gen/ARB_texture_buffer_range.xml | 22 ++
src/mapi/glapi/gen/Makefile.am |1 +
src/mapi/glapi/gen/gl_API.xml |4 +
src/mesa/main/context.c |1 +
src/mesa/main/extensions.c |1 +
src/mesa/main/get.c |1 +
src/mesa/main/get_hash_params.py|6 ++
src/mesa/main/mtypes.h |6 ++
src/mesa/main/teximage.c| 89 ++-
src/mesa/main/teximage.h|4 +
src/mesa/main/texparam.c| 12 +++
11 files changed, 130 insertions(+), 17 deletions(-)
diff --git a/src/mapi/glapi/gen/ARB_texture_buffer_range.xml
b/src/mapi/glapi/gen/ARB_texture_buffer_range.xml
new file mode 100644
index 000..2176c08
--- /dev/null
+++ b/src/mapi/glapi/gen/ARB_texture_buffer_range.xml
@@ -0,0 +1,22 @@
+?xml version=1.0?
+!DOCTYPE OpenGLAPI SYSTEM gl_API.dtd
+
+OpenGLAPI
+
+category name=GL_ARB_texture_buffer_range number=139
+
+enum name=TEXTURE_BUFFER_OFFSET value=0x919D/
+enum name=TEXTURE_BUFFER_SIZEvalue=0x919E/
+enum name=TEXTURE_BUFFER_OFFSET_ALIGNMENTvalue=0x919F/
+
+function name=TexBufferRange offset=assign
+param name=target type=GLenum/
+param name=internalformat type=GLenum/
+param name=buffer type=GLuint/
+param name=offset type=GLintptr/
+param name=size type=GLsizeiptr/
+/function
+
+/category
+
+/OpenGLAPI
diff --git a/src/mapi/glapi/gen/Makefile.am b/src/mapi/glapi/gen/Makefile.am
index f869d28..4d51bbc 100644
--- a/src/mapi/glapi/gen/Makefile.am
+++ b/src/mapi/glapi/gen/Makefile.am
@@ -108,6 +108,7 @@ API_XML = \
ARB_seamless_cube_map.xml \
ARB_sync.xml \
ARB_texture_buffer_object.xml \
+ ARB_texture_buffer_range.xml \
ARB_texture_compression_rgtc.xml \
ARB_texture_float.xml \
ARB_texture_rg.xml \
diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
index 404ccea..4cbd724 100644
--- a/src/mapi/glapi/gen/gl_API.xml
+++ b/src/mapi/glapi/gen/gl_API.xml
@@ -8316,6 +8316,10 @@
xi:include href=ARB_invalidate_subdata.xml
xmlns:xi=http://www.w3.org/2001/XInclude/
+!-- ARB extensions #133...#138 --
+
+xi:include href=ARB_texture_buffer_range.xml
xmlns:xi=http://www.w3.org/2001/XInclude/
+
!-- Non-ARB extensions sorted by extension number. --
category name=GL_EXT_blend_color number=2
diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index 531b811..e5ed97f 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -564,6 +564,7 @@ _mesa_init_constants(struct gl_context *ctx)
ctx-Const.MaxTextureMaxAnisotropy = MAX_TEXTURE_MAX_ANISOTROPY;
ctx-Const.MaxTextureLodBias = MAX_TEXTURE_LOD_BIAS;
ctx-Const.MaxTextureBufferSize = 65536;
+ ctx-Const.TextureBufferOffsetAlignment = 1;
ctx-Const.MaxArrayLockSize = MAX_ARRAY_LOCK_SIZE;
ctx-Const.SubPixelBits = SUB_PIXEL_BITS;
ctx-Const.MinPointSize = MIN_POINT_SIZE;
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index 7a8195a..c9638a1 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
@@ -131,6 +131,7 @@ static const struct extension extension_table[] = {
{ GL_ARB_texture_border_clamp,
o(ARB_texture_border_clamp),GLL,2000 },
{ GL_ARB_texture_buffer_object,
o(ARB_texture_buffer_object), GLC,2008 },
{ GL_ARB_texture_buffer_object_rgb32,
o(ARB_texture_buffer_object_rgb32), GLC,2009 },
+ { GL_ARB_texture_buffer_range,
o(ARB_texture_buffer_range),GLC,2012 },
{ GL_ARB_texture_compression
Mesa (master): gallium: add PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
Module: Mesa
Branch: master
Commit: 0fcd2c5e2fa06339de8af80ff8d35e479d61ccf5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0fcd2c5e2fa06339de8af80ff8d35e479d61ccf5
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Sun Dec 16 17:23:15 2012 +0100
gallium: add PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
Reviewed-by: Brian Paul bri...@vmware.com
---
src/gallium/docs/source/screen.rst |3 +++
src/gallium/include/pipe/p_defines.h |3 ++-
2 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/src/gallium/docs/source/screen.rst
b/src/gallium/docs/source/screen.rst
index 7a17f69..68d1a35 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -134,6 +134,9 @@ The integer capabilities:
expected for a pointer returned by transfer_map if the resource is
PIPE_BUFFER. In other words, the pointer returned by transfer_map is
always aligned to this value.
+* ``PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT``: Describes the required
+ alignment for pipe_sampler_view::u.buf.first_element, in bytes.
+ If a driver does not support first/last_element, it should return 0.
.. _pipe_capf:
diff --git a/src/gallium/include/pipe/p_defines.h
b/src/gallium/include/pipe/p_defines.h
index bd08ac0..d0db5e4 100644
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium/include/pipe/p_defines.h
@@ -497,7 +497,8 @@ enum pipe_cap {
PIPE_CAP_TEXTURE_MULTISAMPLE = 74,
PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT = 75,
PIPE_CAP_CUBE_MAP_ARRAY = 76,
- PIPE_CAP_TEXTURE_BUFFER_OBJECTS = 77
+ PIPE_CAP_TEXTURE_BUFFER_OBJECTS = 77,
+ PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT = 78
};
/**
___
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mesa-commit@lists.freedesktop.org
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Mesa (master): st/mesa: add support for GL_ARB_texture_buffer_range
Module: Mesa
Branch: master
Commit: a901d54f67be0a9ec5a33195036eb6dfc54b501c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a901d54f67be0a9ec5a33195036eb6dfc54b501c
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Sat Dec 22 13:46:27 2012 +0100
st/mesa: add support for GL_ARB_texture_buffer_range
v2: Update to handle BufferSize being -1 and return a NULL sampler
view if the specified range would cause out of bounds access.
Reviewed-by: Brian Paul bri...@vmware.com
Acked-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/state_tracker/st_atom_texture.c | 22 +-
src/mesa/state_tracker/st_extensions.c |7 +++
2 files changed, 28 insertions(+), 1 deletions(-)
diff --git a/src/mesa/state_tracker/st_atom_texture.c
b/src/mesa/state_tracker/st_atom_texture.c
index dba1d82..4b43b2a 100644
--- a/src/mesa/state_tracker/st_atom_texture.c
+++ b/src/mesa/state_tracker/st_atom_texture.c
@@ -152,7 +152,27 @@ st_create_texture_sampler_view_from_stobj(struct
pipe_context *pipe,
u_sampler_view_default_template(templ,
stObj-pt,
format);
- templ.u.tex.first_level = stObj-base.BaseLevel;
+
+ if (stObj-pt-target == PIPE_BUFFER) {
+ unsigned base, size;
+ unsigned f, n;
+ const struct util_format_description *desc
+ = util_format_description(templ.format);
+
+ base = stObj-base.BufferOffset;
+ if (base = stObj-pt-width0)
+ return NULL;
+ size = MIN2(stObj-pt-width0 - base, (unsigned)stObj-base.BufferSize);
+
+ f = ((base * 8) / desc-block.bits) * desc-block.width;
+ n = ((size * 8) / desc-block.bits) * desc-block.width;
+ if (!n)
+ return NULL;
+ templ.u.buf.first_element = f;
+ templ.u.buf.last_element = f + (n - 1);
+ } else {
+ templ.u.tex.first_level = stObj-base.BaseLevel;
+ }
if (swizzle != SWIZZLE_NOOP) {
templ.swizzle_r = GET_SWZ(swizzle, 0);
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index 34c0d7b..214588f 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -685,6 +685,13 @@ void st_init_extensions(struct st_context *st)
}
if (screen-get_param(screen, PIPE_CAP_TEXTURE_BUFFER_OBJECTS)) {
ctx-Extensions.ARB_texture_buffer_object = GL_TRUE;
+
+ ctx-Const.TextureBufferOffsetAlignment =
+ screen-get_param(screen, PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT);
+
+ if (ctx-Const.TextureBufferOffsetAlignment)
+ ctx-Extensions.ARB_texture_buffer_range = GL_TRUE;
+
init_format_extensions(st, tbo_rgb32, Elements(tbo_rgb32),
PIPE_BUFFER, PIPE_BIND_SAMPLER_VIEW);
}
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Mesa (master): nv50,nvc0: fix/enable texture buffer objects
Module: Mesa Branch: master Commit: 4bdf5454a5b0846d56c610b4e7e595fbedcf4c22 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4bdf5454a5b0846d56c610b4e7e595fbedcf4c22 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Sat Jan 12 14:59:43 2013 +0100 nv50,nvc0: fix/enable texture buffer objects --- docs/GL3.txt|2 +- src/gallium/drivers/nv50/nv50_formats.c | 10 +++-- src/gallium/drivers/nv50/nv50_screen.c |6 ++- src/gallium/drivers/nv50/nv50_tex.c | 50 +-- src/gallium/drivers/nv50/nv50_texture.xml.h |1 + src/gallium/drivers/nvc0/nvc0_screen.c |8 - 6 files changed, 43 insertions(+), 34 deletions(-) diff --git a/docs/GL3.txt b/docs/GL3.txt index 21c37c0..88621e3 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -149,7 +149,7 @@ ARB_robust_buffer_access_behaviornot started ARB_shader_image_sizenot started ARB_shader_storage_buffer_object not started ARB_stencil_texturingnot started -ARB_texture_buffer_range not started +ARB_texture_buffer_range DONE (nv50, nvc0) ARB_texture_query_levels not started ARB_texture_storage_multisample not started ARB_texture_view not started diff --git a/src/gallium/drivers/nv50/nv50_formats.c b/src/gallium/drivers/nv50/nv50_formats.c index 41757d2..658f1c4 100644 --- a/src/gallium/drivers/nv50/nv50_formats.c +++ b/src/gallium/drivers/nv50/nv50_formats.c @@ -54,9 +54,11 @@ #if NOUVEAU_DRIVER == 0xc0 # define U_TC U_TB # define U_TCV U_TBV +# define U_tV U_TV #else # define U_TC U_TR # define U_TCV U_TRV +# define U_tV U_V #endif #define NV50_SURFACE_FORMAT_NONE 0 @@ -65,7 +67,7 @@ /* for vertex buffers: */ #define NV50_TIC_0_FMT_8_8_8NV50_TIC_0_FMT_8_8_8_8 #define NV50_TIC_0_FMT_16_16_16 NV50_TIC_0_FMT_16_16_16_16 -#define NV50_TIC_0_FMT_32_32_32 NV50_TIC_0_FMT_32_32_32_32 +#define NV50_TIC_0_FMT_32_32_32 NVC0_TIC_0_FMT_32_32_32 #if NOUVEAU_DRIVER == 0xc0 # define NVXX_3D_VAF_SIZE(s) NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_##s @@ -344,11 +346,11 @@ const struct nv50_format nv50_format_table[PIPE_FORMAT_COUNT] = C4A(R32G32B32A32_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 32_32_32_32, V, 0), C4A(R32G32B32A32_USCALED, NONE, C0, C1, C2, C3, USCALED, 32_32_32_32, V, 0), - F3A(R32G32B32_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, V), + F3A(R32G32B32_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, tV), F3A(R32G32B32_UNORM, NONE, C0, C1, C2, xx, UNORM, 32_32_32, V), F3A(R32G32B32_SNORM, NONE, C0, C1, C2, xx, SNORM, 32_32_32, V), - I3A(R32G32B32_SINT, NONE, C0, C1, C2, xx, SINT, 32_32_32, V), - I3A(R32G32B32_UINT, NONE, C0, C1, C2, xx, UINT, 32_32_32, V), + I3A(R32G32B32_SINT, NONE, C0, C1, C2, xx, SINT, 32_32_32, tV), + I3A(R32G32B32_UINT, NONE, C0, C1, C2, xx, UINT, 32_32_32, tV), F3A(R32G32B32_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 32_32_32, V), F3A(R32G32B32_USCALED, NONE, C0, C1, C2, xx, USCALED, 32_32_32, V), F2A(R32G32_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 32_32, V), diff --git a/src/gallium/drivers/nv50/nv50_screen.c b/src/gallium/drivers/nv50/nv50_screen.c index b1a9c4d..be74350 100644 --- a/src/gallium/drivers/nv50/nv50_screen.c +++ b/src/gallium/drivers/nv50/nv50_screen.c @@ -108,6 +108,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_NPOT_TEXTURES: case PIPE_CAP_ANISOTROPIC_FILTER: case PIPE_CAP_SCALED_RESOLVE: + case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: return 1; case PIPE_CAP_SEAMLESS_CUBE_MAP: return nv50_screen(pscreen)-tesla-oclass = NVA0_3D_CLASS; @@ -125,7 +126,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_SM3: return 1; case PIPE_CAP_GLSL_FEATURE_LEVEL: - return 130; + return 140; case PIPE_CAP_MAX_RENDER_TARGETS: return 8; case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: @@ -176,13 +177,14 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 1; case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: return 256; + case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: + return 1; /* 256 for binding as RT, but that's not possible in GL */ case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: return NOUVEAU_MIN_BUFFER_MAP_ALIGN; case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_TEXTURE_MULTISAMPLE: - case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: return 0; default: NOUVEAU_ERR(unknown PIPE_CAP %d\n, param); diff --git a/src/gallium/drivers/nv50/nv50_tex.c b/src/gallium/drivers/nv50
Mesa (master): nouveau: don't try to use push_data if it's not implemented
Module: Mesa
Branch: master
Commit: e058f2ac97eebbe86fc77ef607ce1cfdcab2cc19
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e058f2ac97eebbe86fc77ef607ce1cfdcab2cc19
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Fri Jan 25 19:37:40 2013 +0100
nouveau: don't try to use push_data if it's not implemented
---
src/gallium/drivers/nouveau/nouveau_buffer.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nouveau_buffer.c
b/src/gallium/drivers/nouveau/nouveau_buffer.c
index fd5..0c3d43b 100644
--- a/src/gallium/drivers/nouveau/nouveau_buffer.c
+++ b/src/gallium/drivers/nouveau/nouveau_buffer.c
@@ -124,6 +124,9 @@ nouveau_transfer_staging(struct nouveau_context *nv,
const unsigned adj = tx-base.box.x NOUVEAU_MIN_BUFFER_MAP_ALIGN_MASK;
const unsigned size = align(tx-base.box.width, 4) + adj;
+ if (!nv-push_data)
+ permit_pb = FALSE;
+
if ((size = NOUVEAU_TRANSFER_PUSHBUF_THRESHOLD) permit_pb) {
tx-map = align_malloc(size, NOUVEAU_MIN_BUFFER_MAP_ALIGN);
if (tx-map)
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Mesa (master): nv50/ir: fix a couple of warnings
Module: Mesa
Branch: master
Commit: b0863c26d43a9ed135c8db980fb0bc9bca35548c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0863c26d43a9ed135c8db980fb0bc9bca35548c
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Sat Jan 12 17:37:34 2013 +0100
nv50/ir: fix a couple of warnings
---
.../drivers/nv50/codegen/nv50_ir_from_tgsi.cpp |4 +++-
src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp| 11 ++-
src/gallium/drivers/nv50/codegen/nv50_ir_target.h |2 ++
3 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
b/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
index cf483d0..5078eb4 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
@@ -722,7 +722,9 @@ bool Source::scanSource()
if (info-io.genUserClip 0) {
info-io.clipDistanceMask = (1 info-io.genUserClip) - 1;
- for (unsigned int n = 0; n ((info-io.genUserClip + 3) / 4); ++n) {
+ const unsigned int nOut = (info-io.genUserClip + 3) / 4;
+
+ for (unsigned int n = 0; n nOut; ++n) {
unsigned int i = info-numOutputs++;
info-out[i].id = i;
info-out[i].sn = TGSI_SEMANTIC_CLIPDIST;
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp
b/src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp
index 714837e..9947c04 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp
@@ -263,7 +263,7 @@ public:
bool run(const std::listValuePair);
- Symbol *assignSlot(const Interval, unsigned int size);
+ Symbol *assignSlot(const Interval, const unsigned int size);
inline int32_t getStackSize() const { return stackSize; }
private:
@@ -1384,7 +1384,7 @@ GCRA::cleanup(const bool success)
}
Symbol *
-SpillCodeInserter::assignSlot(const Interval livei, unsigned int size)
+SpillCodeInserter::assignSlot(const Interval livei, const unsigned int size)
{
SpillSlot slot;
int32_t offsetBase = stackSize;
@@ -1397,21 +1397,22 @@ SpillCodeInserter::assignSlot(const Interval livei,
unsigned int size)
slot.sym = NULL;
for (offset = offsetBase; offset stackSize; offset += size) {
+ const int32_t entryEnd = offset + size;
while (it != slots.end() it-offset offset)
++it;
if (it == slots.end()) // no slots left
break;
std::listSpillSlot::iterator bgn = it;
- while (it != slots.end() it-offset (offset + size)) {
+ while (it != slots.end() it-offset entryEnd) {
it-occup.print();
if (it-occup.overlaps(livei))
break;
++it;
}
- if (it == slots.end() || it-offset = (offset + size)) {
+ if (it == slots.end() || it-offset = entryEnd) {
// fits
- for (; bgn != slots.end() bgn-offset (offset + size); ++bgn) {
+ for (; bgn != slots.end() bgn-offset entryEnd; ++bgn) {
bgn-occup.insert(livei);
if (bgn-size() == size)
slot.sym = bgn-sym;
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_target.h
b/src/gallium/drivers/nv50/codegen/nv50_ir_target.h
index c60ee02..757f4f9 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_target.h
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_target.h
@@ -62,6 +62,7 @@ class CodeEmitter
{
public:
CodeEmitter(const Target *);
+ virtual ~CodeEmitter();
// returns whether the instruction was encodable and written
virtual bool emitInstruction(Instruction *) = 0;
@@ -117,6 +118,7 @@ class Target
{
public:
Target(bool j, bool s) : joinAnterior(j), hasSWSched(s) { }
+ virtual ~Target();
static Target *create(uint32_t chipset);
static void destroy(Target *);
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Mesa (master): nouveau: fix undefined behaviour when testing sample_count
Module: Mesa
Branch: master
Commit: 7d2d450ea6d8082db14cd3f86c6c25442bf771c5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7d2d450ea6d8082db14cd3f86c6c25442bf771c5
Author: Christoph Bumiller christoph.bumil...@speed.at
Date: Sat Jan 19 20:53:22 2013 +0100
nouveau: fix undefined behaviour when testing sample_count
NOTE: This is a candidate for the 9.0 branch.
---
src/gallium/drivers/nv30/nv30_screen.c |2 ++
src/gallium/drivers/nv50/nv50_screen.c |2 ++
src/gallium/drivers/nvc0/nvc0_screen.c |2 ++
3 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/nv30/nv30_screen.c
b/src/gallium/drivers/nv30/nv30_screen.c
index 06f7c42..f3faf8a 100644
--- a/src/gallium/drivers/nv30/nv30_screen.c
+++ b/src/gallium/drivers/nv30/nv30_screen.c
@@ -244,6 +244,8 @@ nv30_screen_is_format_supported(struct pipe_screen *pscreen,
unsigned sample_count,
unsigned bindings)
{
+ if (sample_count 4)
+ return FALSE;
if (!(0x0017 (1 sample_count)))
return FALSE;
diff --git a/src/gallium/drivers/nv50/nv50_screen.c
b/src/gallium/drivers/nv50/nv50_screen.c
index 1155c93..b1a9c4d 100644
--- a/src/gallium/drivers/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nv50/nv50_screen.c
@@ -50,6 +50,8 @@ nv50_screen_is_format_supported(struct pipe_screen *pscreen,
unsigned sample_count,
unsigned bindings)
{
+ if (sample_count 8)
+ return FALSE;
if (!(0x117 (1 sample_count))) /* 0, 1, 2, 4 or 8 */
return FALSE;
if (sample_count == 8 util_format_get_blocksizebits(format) = 128)
diff --git a/src/gallium/drivers/nvc0/nvc0_screen.c
b/src/gallium/drivers/nvc0/nvc0_screen.c
index de0513b..46bb797 100644
--- a/src/gallium/drivers/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nvc0/nvc0_screen.c
@@ -39,6 +39,8 @@ nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
unsigned sample_count,
unsigned bindings)
{
+ if (sample_count 8)
+ return FALSE;
if (!(0x117 (1 sample_count))) /* 0, 1, 2, 4 or 8 */
return FALSE;
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Mesa (9.0): nvc0: add missing call to map edge flag in push_vbo
Module: Mesa Branch: 9.0 Commit: ddf1e620e9ba64feaac4686c4596a4f21c2efeeb URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ddf1e620e9ba64feaac4686c4596a4f21c2efeeb Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Mon Jan 7 20:18:06 2013 +0100 nvc0: add missing call to map edge flag in push_vbo Note: this is a candidate for the 9.0 stable branch. --- src/gallium/drivers/nvc0/nvc0_vbo_translate.c |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/src/gallium/drivers/nvc0/nvc0_vbo_translate.c b/src/gallium/drivers/nvc0/nvc0_vbo_translate.c index 42d9e05..033a5d0 100644 --- a/src/gallium/drivers/nvc0/nvc0_vbo_translate.c +++ b/src/gallium/drivers/nvc0/nvc0_vbo_translate.c @@ -439,6 +439,9 @@ nvc0_push_vbo(struct nvc0_context *nvc0, const struct pipe_draw_info *info) nvc0_vertex_configure_translate(nvc0, info-index_bias); + if (unlikely(ctx.edgeflag.enabled)) + nvc0_push_map_edgeflag(ctx, nvc0, info-index_bias); + ctx.prim_restart = info-primitive_restart; ctx.restart_index = info-restart_index; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (9.0): nv50/ir: wrap assertion using typeid in #ifndef NDEBUG
Module: Mesa
Branch: 9.0
Commit: b3cd93d933e985123eabe18dd4fd14bf33fa6968
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3cd93d933e985123eabe18dd4fd14bf33fa6968
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Mon Jan 7 15:50:19 2013 +0100
nv50/ir: wrap assertion using typeid in #ifndef NDEBUG
Note: this is a candidate for the 9.0 stable branch.
---
src/gallium/drivers/nv50/codegen/nv50_ir.cpp |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir.cpp
b/src/gallium/drivers/nv50/codegen/nv50_ir.cpp
index 335e9e0..146dbbb 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir.cpp
@@ -715,7 +715,9 @@ Instruction::clone(ClonePolicyFunction pol, Instruction
*i) const
{
if (!i)
i = new_Instruction(pol.context(), op, dType);
+#ifndef NDEBUG // non-conformant assert, so this is required
assert(typeid(*i) == typeid(*this));
+#endif
pol.setInstruction(this, i);
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Mesa (9.0): nouveau: fix undefined behaviour when testing sample_count
Module: Mesa
Branch: 9.0
Commit: 3703e9920c2a4d1a022871624bd0d7bd16073867
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3703e9920c2a4d1a022871624bd0d7bd16073867
Author: Christoph Bumiller christoph.bumil...@speed.at
Date: Sat Jan 19 20:53:22 2013 +0100
nouveau: fix undefined behaviour when testing sample_count
NOTE: This is a candidate for the 9.0 branch.
---
src/gallium/drivers/nv30/nv30_screen.c |2 ++
src/gallium/drivers/nv50/nv50_screen.c |2 ++
src/gallium/drivers/nvc0/nvc0_screen.c |2 ++
3 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/nv30/nv30_screen.c
b/src/gallium/drivers/nv30/nv30_screen.c
index 1752d10..9d104f1 100644
--- a/src/gallium/drivers/nv30/nv30_screen.c
+++ b/src/gallium/drivers/nv30/nv30_screen.c
@@ -241,6 +241,8 @@ nv30_screen_is_format_supported(struct pipe_screen *pscreen,
unsigned sample_count,
unsigned bindings)
{
+ if (sample_count 4)
+ return FALSE;
if (!(0x0017 (1 sample_count)))
return FALSE;
diff --git a/src/gallium/drivers/nv50/nv50_screen.c
b/src/gallium/drivers/nv50/nv50_screen.c
index 982948e..06b0f37 100644
--- a/src/gallium/drivers/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nv50/nv50_screen.c
@@ -50,6 +50,8 @@ nv50_screen_is_format_supported(struct pipe_screen *pscreen,
unsigned sample_count,
unsigned bindings)
{
+ if (sample_count 8)
+ return FALSE;
if (!(0x117 (1 sample_count))) /* 0, 1, 2, 4 or 8 */
return FALSE;
if (sample_count == 8 util_format_get_blocksizebits(format) = 128)
diff --git a/src/gallium/drivers/nvc0/nvc0_screen.c
b/src/gallium/drivers/nvc0/nvc0_screen.c
index 8bb9ff6..3a78aad 100644
--- a/src/gallium/drivers/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nvc0/nvc0_screen.c
@@ -39,6 +39,8 @@ nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
unsigned sample_count,
unsigned bindings)
{
+ if (sample_count 8)
+ return FALSE;
if (!(0x117 (1 sample_count))) /* 0, 1, 2, 4 or 8 */
return FALSE;
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Mesa (master): nv50/ir: add definitions of Target and CodeEmitter dtors
Module: Mesa
Branch: master
Commit: e264b8ef4138fb874bcf3f82cfd7468ee27768da
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e264b8ef4138fb874bcf3f82cfd7468ee27768da
Author: Christoph Bumiller christoph.bumil...@speed.at
Date: Sat Jan 19 22:08:01 2013 +0100
nv50/ir: add definitions of Target and CodeEmitter dtors
I really did build test, my compiler just doesn't seem to care.
---
src/gallium/drivers/nv50/codegen/nv50_ir_target.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_target.h
b/src/gallium/drivers/nv50/codegen/nv50_ir_target.h
index 757f4f9..304dda4 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_target.h
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_target.h
@@ -62,7 +62,7 @@ class CodeEmitter
{
public:
CodeEmitter(const Target *);
- virtual ~CodeEmitter();
+ virtual ~CodeEmitter() { }
// returns whether the instruction was encodable and written
virtual bool emitInstruction(Instruction *) = 0;
@@ -118,7 +118,7 @@ class Target
{
public:
Target(bool j, bool s) : joinAnterior(j), hasSWSched(s) { }
- virtual ~Target();
+ virtual ~Target() { }
static Target *create(uint32_t chipset);
static void destroy(Target *);
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Mesa (master): nv50/nvc0: Build codegen in nv50.
Module: Mesa
Branch: master
Commit: 6bca283ad5ebdd85e268c6757842b3c808c6b73d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6bca283ad5ebdd85e268c6757842b3c808c6b73d
Author: Johannes Obermayr johannesoberm...@gmx.de
Date: Sat Jan 12 12:55:08 2013 +0100
nv50/nvc0: Build codegen in nv50.
This is required to make libnv50 independent of libnvc0.
---
src/gallium/drivers/nv50/Makefile.sources | 12 +++-
src/gallium/drivers/nv50/nv50_miptree.c| 32 ++-
src/gallium/drivers/nv50/nv50_resource.h |3 +-
src/gallium/drivers/nvc0/Makefile.sources |6
.../drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp |2 +-
src/gallium/drivers/nvc0/nvc0_miptree.c| 26 +---
6 files changed, 45 insertions(+), 36 deletions(-)
diff --git a/src/gallium/drivers/nv50/Makefile.sources
b/src/gallium/drivers/nv50/Makefile.sources
index c112e82..1092570 100644
--- a/src/gallium/drivers/nv50/Makefile.sources
+++ b/src/gallium/drivers/nv50/Makefile.sources
@@ -15,7 +15,7 @@ C_SOURCES := \
nv50_push.c \
nv50_query.c
-CPP_SOURCES := \
+CODEGEN_NV50_SOURCES := \
codegen/nv50_ir.cpp \
codegen/nv50_ir_bb.cpp \
codegen/nv50_ir_build_util.cpp \
@@ -30,3 +30,13 @@ CPP_SOURCES := \
codegen/nv50_ir_target.cpp \
codegen/nv50_ir_target_nv50.cpp \
codegen/nv50_ir_util.cpp
+
+CODEGEN_NVC0_SOURCES := \
+ $(top_srcdir)/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_gk110.cpp \
+ $(top_srcdir)/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp \
+
$(top_srcdir)/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp \
+ $(top_srcdir)/src/gallium/drivers/nvc0/codegen/nv50_ir_target_nvc0.cpp
+
+CPP_SOURCES := \
+ $(CODEGEN_NV50_SOURCES) \
+ $(CODEGEN_NVC0_SOURCES)
diff --git a/src/gallium/drivers/nv50/nv50_miptree.c
b/src/gallium/drivers/nv50/nv50_miptree.c
index fc9d7f3..7883edb 100644
--- a/src/gallium/drivers/nv50/nv50_miptree.c
+++ b/src/gallium/drivers/nv50/nv50_miptree.c
@@ -28,10 +28,38 @@
#include nv50_context.h
#include nv50_resource.h
-static INLINE uint32_t
+uint32_t
+nv50_tex_choose_tile_dims_helper(unsigned nx, unsigned ny, unsigned nz)
+{
+ uint32_t tile_mode = 0x000;
+
+ if (ny 64) tile_mode = 0x040; /* height 128 tiles */
+ else
+ if (ny 32) tile_mode = 0x030; /* height 64 tiles */
+ else
+ if (ny 16) tile_mode = 0x020; /* height 32 tiles */
+ else
+ if (ny 8) tile_mode = 0x010; /* height 16 tiles */
+
+ if (nz == 1)
+ return tile_mode;
+ else
+ if (tile_mode 0x020)
+ tile_mode = 0x020;
+
+ if (nz 16 tile_mode 0x020)
+ return tile_mode | 0x500; /* depth 32 tiles */
+ if (nz 8) return tile_mode | 0x400; /* depth 16 tiles */
+ if (nz 4) return tile_mode | 0x300; /* depth 8 tiles */
+ if (nz 2) return tile_mode | 0x200; /* depth 4 tiles */
+
+ return tile_mode | 0x100;
+}
+
+static uint32_t
nv50_tex_choose_tile_dims(unsigned nx, unsigned ny, unsigned nz)
{
- return nvc0_tex_choose_tile_dims(nx, ny * 2, nz);
+ return nv50_tex_choose_tile_dims_helper(nx, ny * 2, nz);
}
static uint32_t
diff --git a/src/gallium/drivers/nv50/nv50_resource.h
b/src/gallium/drivers/nv50/nv50_resource.h
index 4808955..a2bc980 100644
--- a/src/gallium/drivers/nv50/nv50_resource.h
+++ b/src/gallium/drivers/nv50/nv50_resource.h
@@ -32,8 +32,7 @@ nv50_screen_init_resource_functions(struct pipe_screen
*pscreen);
#endif /* __NVC0_RESOURCE_H__ */
uint32_t
-nvc0_tex_choose_tile_dims(unsigned nx, unsigned ny, unsigned nz);
-
+nv50_tex_choose_tile_dims_helper(unsigned nx, unsigned ny, unsigned nz);
struct nv50_miptree_level {
uint32_t offset;
diff --git a/src/gallium/drivers/nvc0/Makefile.sources
b/src/gallium/drivers/nvc0/Makefile.sources
index 82504bf..d0e213b 100644
--- a/src/gallium/drivers/nvc0/Makefile.sources
+++ b/src/gallium/drivers/nvc0/Makefile.sources
@@ -14,9 +14,3 @@ C_SOURCES := \
nvc0_program.c \
nvc0_shader_state.c \
nvc0_query.c
-
-CPP_SOURCES := \
- codegen/nv50_ir_emit_gk110.cpp \
- codegen/nv50_ir_emit_nvc0.cpp \
- codegen/nv50_ir_lowering_nvc0.cpp \
- codegen/nv50_ir_target_nvc0.cpp
diff --git a/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
b/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
index 749ace5..c5a7772 100644
--- a/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
@@ -1096,7 +1096,7 @@ NVC0LoweringPass::visit(Instruction *i)
break;
default:
break;
- }
+ }
return true;
}
diff --git a/src/gallium/drivers/nvc0/nvc0_miptree.c
b/src/gallium/drivers/nvc0/nvc0_miptree.c
index b63f196..dd415d0 100644
--- a/src/gallium/drivers/nvc0/nvc0_miptree.c
+++ b/src/gallium/drivers/nvc0/nvc0_miptree.c
@@ -28,32 +28,10 @@
#include nvc0_context.h
#include nvc0_resource.h
Mesa (master): nouveau: improve buffer transfers
Module: Mesa
Branch: master
Commit: 48a45ec24ae74c00d1487552e94d9f824a428f58
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=48a45ec24ae74c00d1487552e94d9f824a428f58
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Tue Jan 8 16:13:11 2013 +0100
nouveau: improve buffer transfers
Save double memcpy on uploads to VRAM in most cases.
Properly handle FLUSH_EXPLICIT.
Reallocate on DISCARD_WHOLE_RESOURCE to avoid sync.
---
src/gallium/drivers/nouveau/nouveau_buffer.c | 399 +
src/gallium/drivers/nouveau/nouveau_buffer.h |3 +
src/gallium/drivers/nouveau/nouveau_context.h | 23 ++
src/gallium/drivers/nouveau/nouveau_screen.h |4 +-
src/gallium/drivers/nouveau/nouveau_winsys.h |3 +
src/gallium/drivers/nv30/nv30_context.c | 78 +-
src/gallium/drivers/nv50/nv50_context.c | 82 +
src/gallium/drivers/nv50/nv50_screen.c|2 +-
src/gallium/drivers/nv50/nv50_screen.h|3 +-
src/gallium/drivers/nvc0/nvc0_context.c | 86 ++
src/gallium/drivers/nvc0/nvc0_screen.c|2 +-
src/gallium/drivers/nvc0/nvc0_screen.h|3 +-
12 files changed, 551 insertions(+), 137 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nouveau_buffer.c
b/src/gallium/drivers/nouveau/nouveau_buffer.c
index 0ecd53a..fd5 100644
--- a/src/gallium/drivers/nouveau/nouveau_buffer.c
+++ b/src/gallium/drivers/nouveau/nouveau_buffer.c
@@ -10,8 +10,15 @@
#include nouveau_buffer.h
#include nouveau_mm.h
+#define NOUVEAU_TRANSFER_PUSHBUF_THRESHOLD 192
+
struct nouveau_transfer {
struct pipe_transfer base;
+
+ uint8_t *map;
+ struct nouveau_bo *bo;
+ struct nouveau_mm_allocation *mm;
+ uint32_t offset;
};
static INLINE struct nouveau_transfer *
@@ -21,6 +28,14 @@ nouveau_transfer(struct pipe_transfer *transfer)
}
static INLINE boolean
+nouveau_buffer_malloc(struct nv04_resource *buf)
+{
+ if (!buf-data)
+ buf-data = align_malloc(buf-base.width0, NOUVEAU_MIN_BUFFER_MAP_ALIGN);
+ return !!buf-data;
+}
+
+static INLINE boolean
nouveau_buffer_allocate(struct nouveau_screen *screen,
struct nv04_resource *buf, unsigned domain)
{
@@ -40,13 +55,10 @@ nouveau_buffer_allocate(struct nouveau_screen *screen,
buf-bo, buf-offset);
if (!buf-bo)
return FALSE;
- }
- if (domain != NOUVEAU_BO_GART) {
- if (!buf-data) {
- buf-data = align_malloc(buf-base.width0, 64);
- if (!buf-data)
-return FALSE;
- }
+ } else {
+ assert(domain == 0);
+ if (!nouveau_buffer_malloc(buf))
+ return FALSE;
}
buf-domain = domain;
if (buf-bo)
@@ -80,6 +92,11 @@ nouveau_buffer_reallocate(struct nouveau_screen *screen,
{
nouveau_buffer_release_gpu_storage(buf);
+ nouveau_fence_ref(NULL, buf-fence);
+ nouveau_fence_ref(NULL, buf-fence_wr);
+
+ buf-status = NOUVEAU_BUFFER_STATUS_REALLOC_MASK;
+
return nouveau_buffer_allocate(screen, buf, domain);
}
@@ -100,73 +117,75 @@ nouveau_buffer_destroy(struct pipe_screen *pscreen,
FREE(res);
}
-/* Maybe just migrate to GART right away if we actually need to do this. */
-boolean
-nouveau_buffer_download(struct nouveau_context *nv, struct nv04_resource *buf,
-unsigned start, unsigned size)
+static uint8_t *
+nouveau_transfer_staging(struct nouveau_context *nv,
+ struct nouveau_transfer *tx, boolean permit_pb)
{
- struct nouveau_mm_allocation *mm;
- struct nouveau_bo *bounce = NULL;
- uint32_t offset;
+ const unsigned adj = tx-base.box.x NOUVEAU_MIN_BUFFER_MAP_ALIGN_MASK;
+ const unsigned size = align(tx-base.box.width, 4) + adj;
- assert(buf-domain == NOUVEAU_BO_VRAM);
+ if ((size = NOUVEAU_TRANSFER_PUSHBUF_THRESHOLD) permit_pb) {
+ tx-map = align_malloc(size, NOUVEAU_MIN_BUFFER_MAP_ALIGN);
+ if (tx-map)
+ tx-map += adj;
+ } else {
+ tx-mm =
+ nouveau_mm_allocate(nv-screen-mm_GART, size, tx-bo, tx-offset);
+ if (tx-bo) {
+ tx-offset += adj;
+ if (!nouveau_bo_map(tx-bo, 0, NULL))
+tx-map = (uint8_t *)tx-bo-map + tx-offset;
+ }
+ }
+ return tx-map;
+}
- mm = nouveau_mm_allocate(nv-screen-mm_GART, size, bounce, offset);
- if (!bounce)
- return FALSE;
+/* Maybe just migrate to GART right away if we actually need to do this. */
+static boolean
+nouveau_transfer_read(struct nouveau_context *nv, struct nouveau_transfer *tx)
+{
+ struct nv04_resource *buf = nv04_resource(tx-base.resource);
+ const unsigned base = tx-base.box.x;
+ const unsigned size = tx-base.box.width;
- nv-copy_data(nv, bounce, offset, NOUVEAU_BO_GART,
- buf-bo, buf-offset + start, NOUVEAU_BO_VRAM, size);
+ nv-copy_data(nv, tx-bo, tx-offset, NOUVEAU_BO_GART,
+ buf-bo, buf-offset + base, buf-domain, size);
- if (nouveau_bo_map(bounce
Mesa (master): nouveau: increase max order of suballocated buffers by 1
Module: Mesa
Branch: master
Commit: 39fe03e2de655aee9939cb51d08cac8aa491bb6e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=39fe03e2de655aee9939cb51d08cac8aa491bb6e
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Tue Jan 8 12:35:25 2013 +0100
nouveau: increase max order of suballocated buffers by 1
This is really a hack to make TF2 (considerably, up to 20 - 70 fps
at low res) faster.
---
src/gallium/drivers/nouveau/nouveau_mm.c | 11 +--
1 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nouveau_mm.c
b/src/gallium/drivers/nouveau/nouveau_mm.c
index 6045af6..439c0fb 100644
--- a/src/gallium/drivers/nouveau/nouveau_mm.c
+++ b/src/gallium/drivers/nouveau/nouveau_mm.c
@@ -9,8 +9,15 @@
#include nouveau_screen.h
#include nouveau_mm.h
+/* TODO: Higher orders can waste a lot of space for npot size buffers, should
+ * add an extra cache for such buffer objects.
+ *
+ * HACK: Max order == 21 to accommodate TF2's 1.5 MiB, frequently reallocated
+ * vertex buffer (VM flush (?) decreases performance dramatically).
+ */
+
#define MM_MIN_ORDER 7 /* = 6 to not violate ARB_map_buffer_alignment */
-#define MM_MAX_ORDER 20
+#define MM_MAX_ORDER 21
#define MM_NUM_BUCKETS (MM_MAX_ORDER - MM_MIN_ORDER + 1)
@@ -102,7 +109,7 @@ mm_default_slab_size(unsigned chunk_order)
{
static const int8_t slab_order[MM_MAX_ORDER - MM_MIN_ORDER + 1] =
{
- 12, 12, 13, 14, 14, 17, 17, 17, 17, 19, 19, 20, 21, 22
+ 12, 12, 13, 14, 14, 17, 17, 17, 17, 19, 19, 20, 21, 22, 22
};
assert(chunk_order = MM_MAX_ORDER chunk_order = MM_MIN_ORDER);
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Mesa (master): nvc0: fix out of bounds writes for unaligned sizes in push_data
Module: Mesa Branch: master Commit: 076f4ced8b7bbf2074cf932e653b1da6db2e2380 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=076f4ced8b7bbf2074cf932e653b1da6db2e2380 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Tue Jan 8 13:46:24 2013 +0100 nvc0: fix out of bounds writes for unaligned sizes in push_data --- src/gallium/drivers/nvc0/nvc0_transfer.c |6 -- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nvc0/nvc0_transfer.c b/src/gallium/drivers/nvc0/nvc0_transfer.c index 66753c9..16467ce 100644 --- a/src/gallium/drivers/nvc0/nvc0_transfer.c +++ b/src/gallium/drivers/nvc0/nvc0_transfer.c @@ -201,7 +201,7 @@ nvc0_m2mf_push_linear(struct nouveau_context *nv, PUSH_DATAh(push, dst-offset + offset); PUSH_DATA (push, dst-offset + offset); BEGIN_NVC0(push, NVC0_M2MF(LINE_LENGTH_IN), 2); - PUSH_DATA (push, nr * 4); + PUSH_DATA (push, MIN2(size, nr * 4)); PUSH_DATA (push, 1); BEGIN_NVC0(push, NVC0_M2MF(EXEC), 1); PUSH_DATA (push, 0x100111); @@ -213,6 +213,7 @@ nvc0_m2mf_push_linear(struct nouveau_context *nv, count -= nr; src += nr; offset += nr * 4; + size -= nr * 4; } nouveau_bufctx_reset(nvc0-bufctx, 0); @@ -246,7 +247,7 @@ nve4_p2mf_push_linear(struct nouveau_context *nv, PUSH_DATAh(push, dst-offset + offset); PUSH_DATA (push, dst-offset + offset); BEGIN_NVC0(push, NVE4_P2MF(LINE_LENGTH_IN), 2); - PUSH_DATA (push, nr * 4); + PUSH_DATA (push, MIN2(size, nr * 4)); PUSH_DATA (push, 1); /* must not be interrupted (trap on QUERY fence, 0x50 works however) */ BEGIN_1IC0(push, NVE4_P2MF(EXEC), nr + 1); @@ -256,6 +257,7 @@ nve4_p2mf_push_linear(struct nouveau_context *nv, count -= nr; src += nr; offset += nr * 4; + size -= nr * 4; } nouveau_bufctx_reset(nvc0-bufctx, 0); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nv50/ir: wrap assertion using typeid in #ifndef NDEBUG
Module: Mesa
Branch: master
Commit: be75a9373a6d0f9e2ef35ac376a541e60d72d306
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=be75a9373a6d0f9e2ef35ac376a541e60d72d306
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Mon Jan 7 15:50:19 2013 +0100
nv50/ir: wrap assertion using typeid in #ifndef NDEBUG
Note: this is a candidate for the 9.0 stable branch.
---
src/gallium/drivers/nv50/codegen/nv50_ir.cpp |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir.cpp
b/src/gallium/drivers/nv50/codegen/nv50_ir.cpp
index 335e9e0..146dbbb 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir.cpp
@@ -715,7 +715,9 @@ Instruction::clone(ClonePolicyFunction pol, Instruction
*i) const
{
if (!i)
i = new_Instruction(pol.context(), op, dType);
+#ifndef NDEBUG // non-conformant assert, so this is required
assert(typeid(*i) == typeid(*this));
+#endif
pol.setInstruction(this, i);
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Mesa (master): nvc0: add missing call to map edge flag in push_vbo
Module: Mesa Branch: master Commit: 41e105d5beb78c42993a602cc58d0f990739b088 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=41e105d5beb78c42993a602cc58d0f990739b088 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Mon Jan 7 20:18:06 2013 +0100 nvc0: add missing call to map edge flag in push_vbo Note: this is a candidate for the 9.0 stable branch. --- src/gallium/drivers/nvc0/nvc0_vbo_translate.c |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/src/gallium/drivers/nvc0/nvc0_vbo_translate.c b/src/gallium/drivers/nvc0/nvc0_vbo_translate.c index 42d9e05..033a5d0 100644 --- a/src/gallium/drivers/nvc0/nvc0_vbo_translate.c +++ b/src/gallium/drivers/nvc0/nvc0_vbo_translate.c @@ -439,6 +439,9 @@ nvc0_push_vbo(struct nvc0_context *nvc0, const struct pipe_draw_info *info) nvc0_vertex_configure_translate(nvc0, info-index_bias); + if (unlikely(ctx.edgeflag.enabled)) + nvc0_push_map_edgeflag(ctx, nvc0, info-index_bias); + ctx.prim_restart = info-primitive_restart; ctx.restart_index = info-restart_index; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nvc0: use correct resource target to select blit shader
Module: Mesa Branch: master Commit: b9c8a98e216f4613dc0a40e26d08f2c1cb760e76 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9c8a98e216f4613dc0a40e26d08f2c1cb760e76 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Mon Jan 7 22:12:28 2013 +0100 nvc0: use correct resource target to select blit shader --- src/gallium/drivers/nvc0/nvc0_surface.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nvc0/nvc0_surface.c b/src/gallium/drivers/nvc0/nvc0_surface.c index 2f81cf5..591f67c 100644 --- a/src/gallium/drivers/nvc0/nvc0_surface.c +++ b/src/gallium/drivers/nvc0/nvc0_surface.c @@ -544,7 +544,7 @@ nvc0_blit_select_fp(struct nvc0_blitctx *ctx, const struct pipe_blit_info *info) struct nvc0_blitter *blitter = ctx-nvc0-screen-blitter; const enum pipe_texture_target ptarg = - nv50_blit_reinterpret_pipe_texture_target(info-dst.resource-target); + nv50_blit_reinterpret_pipe_texture_target(info-src.resource-target); const unsigned targ = nv50_blit_texture_type(ptarg); const unsigned mode = ctx-mode; @@ -553,7 +553,7 @@ nvc0_blit_select_fp(struct nvc0_blitctx *ctx, const struct pipe_blit_info *info) pipe_mutex_lock(blitter-mutex); if (!blitter-fp[targ][mode]) blitter-fp[targ][mode] = -nv50_blitter_make_fp(ctx-nvc0-base.pipe, mode, targ); +nv50_blitter_make_fp(ctx-nvc0-base.pipe, mode, ptarg); pipe_mutex_unlock(blitter-mutex); } ctx-fp = blitter-fp[targ][mode]; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nvc0: catch too high GENERIC indices to prevent GRAPH traps
Module: Mesa
Branch: master
Commit: 18f3f7b95898e7db20cdb24181bc24f91cc24fe6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=18f3f7b95898e7db20cdb24181bc24f91cc24fe6
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Mon Jan 7 15:46:31 2013 +0100
nvc0: catch too high GENERIC indices to prevent GRAPH traps
---
src/gallium/drivers/nvc0/nvc0_program.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_program.c
b/src/gallium/drivers/nvc0/nvc0_program.c
index 8bcb206..39393a1 100644
--- a/src/gallium/drivers/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nvc0/nvc0_program.c
@@ -43,8 +43,14 @@ nvc0_mesa_varying_hack(struct nv50_ir_varying *var)
for (c = 0; c 4; ++c)
var-slot[c] = (0x2e0 + c * 0x4) / 4;
else
+ if (var-si = 39)
for (c = 0; c 4; ++c) /* move down user varyings (first has index 8) */
var-slot[c] -= 0x80 / 4;
+ else {
+ NOUVEAU_ERR(too many varyings / invalid location: %u !\n, var-si);
+ for (c = 0; c 4; ++c)
+ var-slot[c] = (0x270 + c * 0x4) / 4; /* catch invalid indices */
+ }
}
static uint32_t
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Mesa (master): nvc0/ir: allow neg, abs modifiers on OP_SET with integer result
Module: Mesa Branch: master Commit: 1f079f9e5879ed9e5f2a951bca305a43e5dc9d1d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f079f9e5879ed9e5f2a951bca305a43e5dc9d1d Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Sat Dec 8 19:46:14 2012 +0100 nvc0/ir: allow neg,abs modifiers on OP_SET with integer result --- .../drivers/nvc0/codegen/nv50_ir_target_nvc0.cpp |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/gallium/drivers/nvc0/codegen/nv50_ir_target_nvc0.cpp b/src/gallium/drivers/nvc0/codegen/nv50_ir_target_nvc0.cpp index e3db4b2..cdc7c0a 100644 --- a/src/gallium/drivers/nvc0/codegen/nv50_ir_target_nvc0.cpp +++ b/src/gallium/drivers/nvc0/codegen/nv50_ir_target_nvc0.cpp @@ -481,6 +481,10 @@ TargetNVC0::isModSupported(const Instruction *insn, int s, Modifier mod) const case OP_OR: case OP_XOR: break; + case OP_SET: + if (insn-sType != TYPE_F32) +return false; + break; case OP_ADD: if (mod.abs()) return false; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nvc0/ir/emit: fix check for flags register use in logic ops
Module: Mesa
Branch: master
Commit: 7c6584b9968ff1af0798d0a783142052b43c1dc0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c6584b9968ff1af0798d0a783142052b43c1dc0
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Sat Dec 8 15:06:43 2012 +0100
nvc0/ir/emit: fix check for flags register use in logic ops
---
.../drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
b/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
index 92496a3..ab4fb94 100644
--- a/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
@@ -647,17 +647,17 @@ CodeEmitterNVC0::emitLogicOp(const Instruction *i,
uint8_t subOp)
if (isLIMM(i-src(1), TYPE_U32)) {
emitForm_A(i, HEX64(3800, 0002));
- if (i-srcExists(2))
+ if (i-flagsDef = 0)
code[1] |= 1 26;
} else {
emitForm_A(i, HEX64(6800, 0003));
- if (i-srcExists(2))
+ if (i-flagsDef = 0)
code[1] |= 1 16;
}
code[0] |= subOp 6;
- if (i-srcExists(2)) // carry
+ if (i-flagsSrc = 0) // carry
code[0] |= 1 5;
if (i-src(0).mod Modifier(NV50_IR_MOD_NOT)) code[0] |= 1 9;
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Mesa (master): st/mesa: set PIPE_BIND_SAMPLER_VIEW for TBOs in st_bufferobj_data
Module: Mesa Branch: master Commit: 5e98cefb5a088b71ed3cb8e5cd826deed7d28b37 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e98cefb5a088b71ed3cb8e5cd826deed7d28b37 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Sat Dec 8 16:02:54 2012 +0100 st/mesa: set PIPE_BIND_SAMPLER_VIEW for TBOs in st_bufferobj_data --- src/mesa/state_tracker/st_cb_bufferobjects.c |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/src/mesa/state_tracker/st_cb_bufferobjects.c b/src/mesa/state_tracker/st_cb_bufferobjects.c index 7d1c05a..cf291c1 100644 --- a/src/mesa/state_tracker/st_cb_bufferobjects.c +++ b/src/mesa/state_tracker/st_cb_bufferobjects.c @@ -195,6 +195,9 @@ st_bufferobj_data(struct gl_context *ctx, case GL_ELEMENT_ARRAY_BUFFER_ARB: bind = PIPE_BIND_INDEX_BUFFER; break; + case GL_TEXTURE_BUFFER: + bind = PIPE_BIND_SAMPLER_VIEW; + break; case GL_TRANSFORM_FEEDBACK_BUFFER: bind = PIPE_BIND_STREAM_OUTPUT; break; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nv50,nvc0: add support for cube map arrays
Module: Mesa
Branch: master
Commit: f7599b2c32185535b4c215de0ba0454129fa523f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7599b2c32185535b4c215de0ba0454129fa523f
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Fri Dec 7 22:47:40 2012 +0100
nv50,nvc0: add support for cube map arrays
NOTE: nv50 support not enabled, someone with nva3/8 please fix.
---
src/gallium/drivers/nv50/codegen/nv50_ir.h |3 +-
.../drivers/nv50/codegen/nv50_ir_build_util.cpp|1 +
.../drivers/nv50/codegen/nv50_ir_emit_nv50.cpp | 17 +
.../drivers/nv50/codegen/nv50_ir_from_tgsi.cpp | 27 +-
src/gallium/drivers/nv50/codegen/nv50_ir_inlines.h |4 +-
.../drivers/nv50/codegen/nv50_ir_lowering_nv50.cpp | 39 ++--
src/gallium/drivers/nv50/codegen/nv50_ir_print.cpp |2 +-
.../drivers/nv50/codegen/nv50_ir_target.cpp|4 +-
src/gallium/drivers/nv50/nv50_blit.h |1 +
src/gallium/drivers/nv50/nv50_screen.c |5 +++
src/gallium/drivers/nv50/nv50_surface.c|1 +
src/gallium/drivers/nv50/nv50_tex.c|9 +++--
.../drivers/nvc0/codegen/nv50_ir_emit_gk110.cpp|1 -
.../drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp |1 -
src/gallium/drivers/nvc0/nvc0_screen.c |1 +
src/gallium/drivers/nvc0/nvc0_tex.c|9 +++--
16 files changed, 88 insertions(+), 37 deletions(-)
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir.h
b/src/gallium/drivers/nv50/codegen/nv50_ir.h
index 0b47c32..b951b9d 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir.h
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir.h
@@ -124,7 +124,7 @@ enum operation
OP_DFDY,
OP_RDSV, // read system value
OP_WRSV, // write system value
- OP_PIXLD,
+ OP_TEXPREP, // turn cube map array into 2d array coordinates, TODO: move
OP_QUADOP,
OP_QUADON,
OP_QUADPOP,
@@ -750,6 +750,7 @@ public:
Target operator=(TexTarget targ)
{
assert(targ TEX_TARGET_COUNT);
+ target = targ;
return *this;
}
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_build_util.cpp
b/src/gallium/drivers/nv50/codegen/nv50_ir_build_util.cpp
index f713e63..322d6b9 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_build_util.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_build_util.cpp
@@ -254,6 +254,7 @@ BuildUtil::mkTex(operation op, TexTarget targ, uint8_t tic,
uint8_t tsc,
tex-setTexture(targ, tic, tsc);
+ insert(tex);
return tex;
}
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_emit_nv50.cpp
b/src/gallium/drivers/nv50/codegen/nv50_ir_emit_nv50.cpp
index 90ec9d0..2ba87f3 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_emit_nv50.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_emit_nv50.cpp
@@ -116,6 +116,7 @@ private:
void emitTEX(const TexInstruction *);
void emitTXQ(const TexInstruction *);
+ void emitTEXPREP(const TexInstruction *);
void emitQUADOP(const Instruction *, uint8_t lane, uint8_t quOp);
@@ -1430,6 +1431,19 @@ CodeEmitterNV50::emitTXQ(const TexInstruction *i)
}
void
+CodeEmitterNV50::emitTEXPREP(const TexInstruction *i)
+{
+ code[0] = 0xf801 | (3 22) | (i-tex.s 17) | (i-tex.r 9);
+ code[1] = 0x6001;
+
+ code[0] |= (i-tex.mask 0x3) 25;
+ code[1] |= (i-tex.mask 0xc) 12;
+ defId(i-def(0), 2);
+
+ emitFlagsRd(i);
+}
+
+void
CodeEmitterNV50::emitPRERETEmu(const FlowInstruction *i)
{
uint32_t pos = i-target.bb-binPos + 8; // +8 to skip an op */
@@ -1652,6 +1666,9 @@ CodeEmitterNV50::emitInstruction(Instruction *insn)
case OP_TXQ:
emitTXQ(insn-asTex());
break;
+ case OP_TEXPREP:
+ emitTEXPREP(insn-asTex());
+ break;
case OP_EMIT:
case OP_RESTART:
emitOUT(insn);
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
b/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
index e73c804..cf483d0 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
@@ -237,6 +237,10 @@ unsigned int Instruction::srcMask(unsigned int s) const
return 0x1;
case TGSI_OPCODE_LIT:
return 0xb;
+ case TGSI_OPCODE_TEX2:
+ case TGSI_OPCODE_TXB2:
+ case TGSI_OPCODE_TXL2:
+ return (s == 0) ? 0xf : 0x3;
case TGSI_OPCODE_TEX:
case TGSI_OPCODE_TXB:
case TGSI_OPCODE_TXD:
@@ -264,6 +268,12 @@ unsigned int Instruction::srcMask(unsigned int s) const
case TGSI_TEXTURE_RECT:
mask = 0xb;
break;
+ case TGSI_TEXTURE_CUBE_ARRAY:
+ case TGSI_TEXTURE_SHADOW2D_ARRAY:
+ case TGSI_TEXTURE_SHADOWCUBE:
+ case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
+ mask |= 0x8;
+ break;
default:
break;
}
@@ -343,12 +353,14 @@ static nv50_ir::TexTarget translateTexture(uint tex)
NV50_IR_TEX_TARG_CASE(RECT, RECT
Mesa (master): nv50,nvc0: fix shader eviction
Module: Mesa
Branch: master
Commit: cfa752cd332ff1cfac403001f3833476ba6d978d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cfa752cd332ff1cfac403001f3833476ba6d978d
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Fri Dec 7 22:43:10 2012 +0100
nv50,nvc0: fix shader eviction
---
src/gallium/drivers/nv50/nv50_program.c |5 +
src/gallium/drivers/nvc0/nvc0_program.c | 16 ++--
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_program.c
b/src/gallium/drivers/nv50/nv50_program.c
index 0d292f7..10810bf 100644
--- a/src/gallium/drivers/nv50/nv50_program.c
+++ b/src/gallium/drivers/nv50/nv50_program.c
@@ -396,6 +396,11 @@ nv50_program_upload_code(struct nv50_context *nv50, struct
nv50_program *prog)
nouveau_heap_free(evict-mem);
}
debug_printf(WARNING: out of code space, evicting all shaders.\n);
+ ret = nouveau_heap_alloc(heap, size, prog, prog-mem);
+ if (ret) {
+ NOUVEAU_ERR(shader too large (0x%x) to fit in code space ?\n, size);
+ return FALSE;
+ }
}
prog-code_base = prog-mem-start;
diff --git a/src/gallium/drivers/nvc0/nvc0_program.c
b/src/gallium/drivers/nvc0/nvc0_program.c
index 9655e18..8bcb206 100644
--- a/src/gallium/drivers/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nvc0/nvc0_program.c
@@ -670,8 +670,20 @@ nvc0_program_upload_code(struct nvc0_context *nvc0, struct
nvc0_program *prog)
ret = nouveau_heap_alloc(screen-text_heap, size, prog, prog-mem);
if (ret) {
- NOUVEAU_ERR(out of code space\n);
- return FALSE;
+ struct nouveau_heap *heap = screen-text_heap;
+ struct nouveau_heap *iter;
+ for (iter = heap; iter iter-next != heap; iter = iter-next) {
+ struct nvc0_program *evict = iter-priv;
+ if (evict)
+nouveau_heap_free(evict-mem);
+ }
+ debug_printf(WARNING: out of code space, evicting all shaders.\n);
+ ret = nouveau_heap_alloc(heap, size, prog, prog-mem);
+ if (ret) {
+ NOUVEAU_ERR(shader too large (0x%x) to fit in code space ?\n, size);
+ return FALSE;
+ }
+ IMMED_NVC0(nvc0-base.pushbuf, NVC0_3D(SERIALIZE), 0);
}
prog-code_base = prog-mem-start;
prog-immd_base = align(prog-mem-start + prog-immd_base, 0x100);
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Mesa (master): nv50,nvc0: expose ARB_map_buffer_alignment
Module: Mesa
Branch: master
Commit: d8988f048fd963eeddf33c682d64ebdfaa2de9ae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8988f048fd963eeddf33c682d64ebdfaa2de9ae
Author: Lucas Stach d...@lynxeye.de
Date: Wed Oct 31 16:31:12 2012 +0100
nv50,nvc0: expose ARB_map_buffer_alignment
All HW buffers (also suballocated ones) are already aligned.
Just make sure that also the initial sysram buffers have proper
alignment.
---
src/gallium/drivers/nouveau/nouveau_buffer.c |6 +++---
src/gallium/drivers/nouveau/nouveau_mm.c |2 +-
src/gallium/drivers/nv50/nv50_screen.c |3 ++-
src/gallium/drivers/nvc0/nvc0_screen.c |3 ++-
4 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nouveau_buffer.c
b/src/gallium/drivers/nouveau/nouveau_buffer.c
index fb929d6..0ecd53a 100644
--- a/src/gallium/drivers/nouveau/nouveau_buffer.c
+++ b/src/gallium/drivers/nouveau/nouveau_buffer.c
@@ -43,7 +43,7 @@ nouveau_buffer_allocate(struct nouveau_screen *screen,
}
if (domain != NOUVEAU_BO_GART) {
if (!buf-data) {
- buf-data = MALLOC(buf-base.width0);
+ buf-data = align_malloc(buf-base.width0, 64);
if (!buf-data)
return FALSE;
}
@@ -92,7 +92,7 @@ nouveau_buffer_destroy(struct pipe_screen *pscreen,
nouveau_buffer_release_gpu_storage(res);
if (res-data !(res-status NOUVEAU_BUFFER_STATUS_USER_MEMORY))
- FREE(res-data);
+ align_free(res-data);
nouveau_fence_ref(NULL, res-fence);
nouveau_fence_ref(NULL, res-fence_wr);
@@ -457,7 +457,7 @@ nouveau_buffer_migrate(struct nouveau_context *nv,
if (ret)
return ret;
memcpy((uint8_t *)buf-bo-map + buf-offset, buf-data, size);
- FREE(buf-data);
+ align_free(buf-data);
} else
if (old_domain != 0 new_domain != 0) {
struct nouveau_mm_allocation *mm = buf-mm;
diff --git a/src/gallium/drivers/nouveau/nouveau_mm.c
b/src/gallium/drivers/nouveau/nouveau_mm.c
index 4207084..6045af6 100644
--- a/src/gallium/drivers/nouveau/nouveau_mm.c
+++ b/src/gallium/drivers/nouveau/nouveau_mm.c
@@ -9,7 +9,7 @@
#include nouveau_screen.h
#include nouveau_mm.h
-#define MM_MIN_ORDER 7
+#define MM_MIN_ORDER 7 /* = 6 to not violate ARB_map_buffer_alignment */
#define MM_MAX_ORDER 20
#define MM_NUM_BUCKETS (MM_MAX_ORDER - MM_MIN_ORDER + 1)
diff --git a/src/gallium/drivers/nv50/nv50_screen.c
b/src/gallium/drivers/nv50/nv50_screen.c
index 9461af9..d0a0295 100644
--- a/src/gallium/drivers/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nv50/nv50_screen.c
@@ -170,11 +170,12 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
return 1;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return 256;
+ case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
+ return 64;
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_TEXTURE_MULTISAMPLE:
- case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
return 0;
default:
NOUVEAU_ERR(unknown PIPE_CAP %d\n, param);
diff --git a/src/gallium/drivers/nvc0/nvc0_screen.c
b/src/gallium/drivers/nvc0/nvc0_screen.c
index 0e0b666..3bf2191 100644
--- a/src/gallium/drivers/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nvc0/nvc0_screen.c
@@ -148,11 +148,12 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
return 1;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return 256;
+ case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
+ return 64;
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_TEXTURE_MULTISAMPLE:
- case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
return 0;
default:
NOUVEAU_ERR(unknown PIPE_CAP %d\n, param);
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Mesa (master): nv50,nvc0: fix 2d engine stencil-only copies
Module: Mesa Branch: master Commit: 351d3c59f2a1153047d45fcdb23cc487f231683d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=351d3c59f2a1153047d45fcdb23cc487f231683d Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Thu Oct 25 14:11:17 2012 +0200 nv50,nvc0: fix 2d engine stencil-only copies --- src/gallium/drivers/nv50/nv50_2d.xml.h | 59 +- src/gallium/drivers/nv50/nv50_surface.c |4 ++- src/gallium/drivers/nvc0/nvc0_2d.xml.h |4 +- src/gallium/drivers/nvc0/nvc0_surface.c |3 +- 4 files changed, 48 insertions(+), 22 deletions(-) diff --git a/src/gallium/drivers/nv50/nv50_2d.xml.h b/src/gallium/drivers/nv50/nv50_2d.xml.h index bc9bcf7..dfbef2c 100644 --- a/src/gallium/drivers/nv50/nv50_2d.xml.h +++ b/src/gallium/drivers/nv50/nv50_2d.xml.h @@ -1,5 +1,5 @@ -#ifndef NV50_2D_XML -#define NV50_2D_XML +#ifndef RNNDB_NV50_2D_XML +#define RNNDB_NV50_2D_XML /* Autogenerated file, DO NOT EDIT manually! @@ -8,14 +8,14 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- nv50_2d.xml( 9799 bytes, from 2010-12-28 17:17:11) -- copyright.xml ( 6452 bytes, from 2010-12-15 23:45:18) -- nv_object.xml ( 11898 bytes, from 2010-12-28 17:17:11) -- nvchipsets.xml ( 3074 bytes, from 2010-12-15 23:45:18) -- nv_defs.xml( 4437 bytes, from 2010-12-15 23:45:18) -- nv50_defs.xml ( 4487 bytes, from 2010-12-15 23:45:18) - -Copyright (C) 2006-2010 by the following authors: +- rnndb/nv50_2d.xml ( 3 bytes, from 2011-07-09 13:43:58) +- ./rnndb/copyright.xml ( 6452 bytes, from 2011-07-09 13:43:58) +- ./rnndb/nv_object.xml ( 12912 bytes, from 2012-07-12 09:41:09) +- ./rnndb/nvchipsets.xml ( 3736 bytes, from 2012-07-12 09:41:09) +- ./rnndb/nv_defs.xml( 4437 bytes, from 2011-07-09 13:43:58) +- ./rnndb/nv50_defs.xml ( 5468 bytes, from 2011-07-09 13:43:58) + +Copyright (C) 2006-2011 by the following authors: - Artur Huillet arthur.huil...@free.fr (ahuillet) - Ben Skeggs (darktama, darktama_) - B. R. koala...@users.sourceforge.net (koala_br) @@ -106,6 +106,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50_2D_UNK228 0x0228 +#define NVC0_2D_UNK228 0x0228 + #define NV50_2D_SRC_FORMAT 0x0230 #define NV50_2D_SRC_LINEAR 0x0234 @@ -116,6 +118,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50_2D_SRC_LAYER 0x0240 +#define NVC0_2D_UNK0240 0x0240 + #define NV50_2D_SRC_PITCH 0x0244 #define NV50_2D_SRC_PITCH__MAX 0x0004 @@ -170,23 +174,33 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50_2D_ROP0x02a0 #define NV50_2D_BETA1 0x02a4 +#define NV50_2D_BETA1_BETA1__MASK 0x7f80 +#define NV50_2D_BETA1_BETA1__SHIFT 23 #define NV50_2D_BETA4 0x02a8 +#define NV50_2D_BETA4_B__MASK 0x00ff +#define NV50_2D_BETA4_B__SHIFT 0 +#define NV50_2D_BETA4_G__MASK 0xff00 +#define NV50_2D_BETA4_G__SHIFT 8 +#define NV50_2D_BETA4_R__MASK 0x00ff +#define NV50_2D_BETA4_R__SHIFT 16 +#define NV50_2D_BETA4_A__MASK 0xff00 +#define NV50_2D_BETA4_A__SHIFT 24 #define NV50_2D_OPERATION 0x02ac #define NV50_2D_OPERATION_SRCCOPY_AND 0x #define NV50_2D_OPERATION_ROP_AND 0x0001 -#define NV50_2D_OPERATION_BLEND_AND0x0002 +#define NV50_2D_OPERATION_BLEND 0x0002 #define NV50_2D_OPERATION_SRCCOPY 0x0003 -#define NV50_2D_OPERATION_UNK4 0x0004 +#define NV50_2D_OPERATION_ROP 0x0004 #define NV50_2D_OPERATION_SRCCOPY_PREMULT 0x0005 #define NV50_2D_OPERATION_BLEND_PREMULT 0x0006 -#define NV50_2D_UNK2B0 0x02b0 -#define NV50_2D_UNK2B0_UNK0__MASK 0x003f -#define NV50_2D_UNK2B0_UNK0__SHIFT 0 -#define
Mesa (master): nv50/ir: restore use of long immediate encodings
Module: Mesa
Branch: master
Commit: 9ae7d8bb799a8c5008c7c4824d414ca856e13ba5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ae7d8bb799a8c5008c7c4824d414ca856e13ba5
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Thu Oct 25 14:32:29 2012 +0200
nv50/ir: restore use of long immediate encodings
NOTE: This is a candidate for the 9.0 branch.
---
.../drivers/nv50/codegen/nv50_ir_emit_nv50.cpp |3 +++
.../drivers/nv50/codegen/nv50_ir_target_nv50.cpp |6 ++
2 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_emit_nv50.cpp
b/src/gallium/drivers/nv50/codegen/nv50_ir_emit_nv50.cpp
index bc4657c..90ec9d0 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_emit_nv50.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_emit_nv50.cpp
@@ -1284,6 +1284,9 @@ CodeEmitterNV50::emitLogicOp(const Instruction *i)
assert(i-op == OP_AND);
break;
}
+ if (i-src(0).mod Modifier(NV50_IR_MOD_NOT))
+ code[0] |= 1 22;
+
emitForm_IMM(i);
} else {
switch (i-op) {
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_target_nv50.cpp
b/src/gallium/drivers/nv50/codegen/nv50_ir_target_nv50.cpp
index 8b11c6a..6b4175e 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_target_nv50.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_target_nv50.cpp
@@ -323,6 +323,12 @@ TargetNV50::insnCanLoad(const Instruction *i, int s,
ldSize = typeSizeof(ld-dType);
}
+ if (sf == FILE_IMMEDIATE)
+ return true;
+
+
+ // Check if memory access is encodable:
+
if (ldSize 4 sf == FILE_SHADER_INPUT) // no 4-byte aligned a[] access
return false;
if (ld-getSrc(0)-reg.data.offset (int32_t)(127 * ldSize))
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Mesa (master): nv50/ir/tgsi: fix srcMask for TXP with SHADOW1D
Module: Mesa Branch: master Commit: d310e29302fb409c0c23442c2b1d1a6c044dd6f0 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d310e29302fb409c0c23442c2b1d1a6c044dd6f0 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Wed Oct 24 20:33:02 2012 +0200 nv50/ir/tgsi: fix srcMask for TXP with SHADOW1D --- .../drivers/nv50/codegen/nv50_ir_from_tgsi.cpp |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp index 071674b..e73c804 100644 --- a/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp +++ b/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp @@ -257,7 +257,7 @@ unsigned int Instruction::srcMask(unsigned int s) const mask = 0x9; break; case TGSI_TEXTURE_SHADOW1D: - mask = 0x5; + mask = 0xd; break; case TGSI_TEXTURE_1D_ARRAY: case TGSI_TEXTURE_2D: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nv50,nvc0: implement blit
Module: Mesa Branch: master Commit: 36ea744f58e5b436c45ed857bd92bbb472e641d5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=36ea744f58e5b436c45ed857bd92bbb472e641d5 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Wed Sep 26 23:06:40 2012 +0200 nv50,nvc0: implement blit --- src/gallium/drivers/nv50/nv50_blit.h | 182 ++ src/gallium/drivers/nv50/nv50_context.c |5 + src/gallium/drivers/nv50/nv50_context.h | 15 + src/gallium/drivers/nv50/nv50_query.c|3 + src/gallium/drivers/nv50/nv50_resource.h |5 + src/gallium/drivers/nv50/nv50_screen.c |5 +- src/gallium/drivers/nv50/nv50_screen.h |7 +- src/gallium/drivers/nv50/nv50_surface.c | 919 -- src/gallium/drivers/nv50/nv50_tex.c | 29 +- src/gallium/drivers/nvc0/nvc0_context.c |5 + src/gallium/drivers/nvc0/nvc0_context.h | 16 + src/gallium/drivers/nvc0/nvc0_query.c|3 + src/gallium/drivers/nvc0/nvc0_screen.c |5 +- src/gallium/drivers/nvc0/nvc0_screen.h |7 +- src/gallium/drivers/nvc0/nvc0_surface.c | 884 - src/gallium/drivers/nvc0/nvc0_tex.c | 23 +- 16 files changed, 1398 insertions(+), 715 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=36ea744f58e5b436c45ed857bd92bbb472e641d5 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nv50,nvc0: fix 3d engine blit for nvc0
Module: Mesa Branch: master Commit: 2149ce41ed6b10f7bff65d7b3f23fd03b89753e3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2149ce41ed6b10f7bff65d7b3f23fd03b89753e3 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Sun Sep 30 22:59:34 2012 +0200 nv50,nvc0: fix 3d engine blit for nvc0 --- src/gallium/drivers/nv50/nv50_surface.c |4 +++- src/gallium/drivers/nvc0/nvc0_surface.c |9 ++--- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/nv50/nv50_surface.c b/src/gallium/drivers/nv50/nv50_surface.c index e64a2ba..f315a23 100644 --- a/src/gallium/drivers/nv50/nv50_surface.c +++ b/src/gallium/drivers/nv50/nv50_surface.c @@ -483,6 +483,7 @@ nv50_blitter_make_vp(struct nv50_blitter *blit) blit-vp.out[1].hw = 2; blit-vp.out[1].mask = 0x7; blit-vp.out[1].sn = TGSI_SEMANTIC_GENERIC; + blit-vp.out[1].si = 8; blit-vp.vp.attrs[0] = 0x73; blit-vp.vp.psiz = 0x40; blit-vp.vp.edgeflag = 0x40; @@ -524,8 +525,9 @@ nv50_blitter_make_fp(struct pipe_context *pipe, return NULL; out = ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 0); + /* NOTE: use GENERIC[8] so we don't use the TEXCOORD slots on nvc0 */ tc = ureg_DECL_fs_input( - ureg, TGSI_SEMANTIC_GENERIC, 0, TGSI_INTERPOLATE_LINEAR); + ureg, TGSI_SEMANTIC_GENERIC, 8, TGSI_INTERPOLATE_LINEAR); data = ureg_DECL_temporary(ureg); diff --git a/src/gallium/drivers/nvc0/nvc0_surface.c b/src/gallium/drivers/nvc0/nvc0_surface.c index dcf0085..4f79020 100644 --- a/src/gallium/drivers/nvc0/nvc0_surface.c +++ b/src/gallium/drivers/nvc0/nvc0_surface.c @@ -618,7 +618,7 @@ nvc0_blit_set_src(struct nvc0_blitctx *ctx, (res-target == PIPE_TEXTURE_3D ? res-depth0 : res-array_size) - 1; } - flags = NV50_TEXVIEW_SCALED_COORDS; + flags = res-last_level ? 0 : NV50_TEXVIEW_SCALED_COORDS; if (filter res-nr_samples == 8) flags |= NV50_TEXVIEW_FILTER_MSAA8; @@ -826,8 +826,8 @@ nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info) x0 = (float)info-src.box.x - x_range * (float)info-dst.box.x; y0 = (float)info-src.box.y - y_range * (float)info-dst.box.y; - x1 = info-src.box.x + 16384.0f * x_range; - y1 = info-src.box.y + 16384.0f * y_range; + x1 = x0 + 16384.0f * x_range; + y1 = y0 + 16384.0f * y_range; x0 *= (float)(1 nv50_miptree(src)-ms_x); x1 *= (float)(1 nv50_miptree(src)-ms_x); @@ -851,6 +851,9 @@ nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info) z += 0.5f * dz; IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 0); + BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(0)), 2); + PUSH_DATA (push, nvc0-framebuffer.width 16); + PUSH_DATA (push, nvc0-framebuffer.height 16); /* Draw a large triangle in screen coordinates covering the whole * render target, with scissors defining the destination region. ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nvc0: make sure handles for unbound textures/ samplers are uploaded on nve4
Module: Mesa
Branch: master
Commit: c321b1bef15e2807de3f6225c4abcbf48969997a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c321b1bef15e2807de3f6225c4abcbf48969997a
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Wed Jul 11 20:52:58 2012 +0200
nvc0: make sure handles for unbound textures/samplers are uploaded on nve4
---
src/gallium/drivers/nvc0/nvc0_context.c |2 ++
src/gallium/drivers/nvc0/nvc0_tex.c |8 ++--
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_context.c
b/src/gallium/drivers/nvc0/nvc0_context.c
index ee131d2..2c032ab 100644
--- a/src/gallium/drivers/nvc0/nvc0_context.c
+++ b/src/gallium/drivers/nvc0/nvc0_context.c
@@ -194,6 +194,8 @@ nvc0_create(struct pipe_screen *pscreen, void *priv)
nvc0-base.scratch.bo_size = 2 20;
+ memset(nvc0-tex_handles, ~0, sizeof(nvc0-tex_handles));
+
return pipe;
out_err:
diff --git a/src/gallium/drivers/nvc0/nvc0_tex.c
b/src/gallium/drivers/nvc0/nvc0_tex.c
index 0930212..b52918e 100644
--- a/src/gallium/drivers/nvc0/nvc0_tex.c
+++ b/src/gallium/drivers/nvc0/nvc0_tex.c
@@ -338,8 +338,10 @@ nve4_validate_tic(struct nvc0_context *nvc0, unsigned s)
if (dirty)
BCTX_REFN(nvc0-bufctx_3d, TEX(s, i), res, RD);
}
- for (; i nvc0-state.num_textures[s]; ++i)
+ for (; i nvc0-state.num_textures[s]; ++i) {
nvc0-tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
+ nvc0-textures_dirty[s] |= 1 i;
+ }
nvc0-state.num_textures[s] = nvc0-num_textures[s];
@@ -446,8 +448,10 @@ nve4_validate_tsc(struct nvc0_context *nvc0, int s)
nvc0-tex_handles[s][i] = ~NVE4_TSC_ENTRY_INVALID;
nvc0-tex_handles[s][i] |= tsc-id 20;
}
- for (; i nvc0-state.num_samplers[s]; ++i)
+ for (; i nvc0-state.num_samplers[s]; ++i) {
nvc0-tex_handles[s][i] |= NVE4_TSC_ENTRY_INVALID;
+ nvc0-samplers_dirty[s] |= 1 i;
+ }
nvc0-state.num_samplers[s] = nvc0-num_samplers[s];
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Mesa (master): nv50/ir/ra: Fix register interference tracking.
Module: Mesa
Branch: master
Commit: 374925bec9c3c613ef0c6855d0ddf7e081b446d8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=374925bec9c3c613ef0c6855d0ddf7e081b446d8
Author: Jay Cornwall j...@jcornwall.me
Date: Sat Sep 22 11:15:11 2012 -0500
nv50/ir/ra: Fix register interference tracking.
See fdo bug 55224.
---
src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp
b/src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp
index 1399876..714837e 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp
@@ -43,7 +43,7 @@ public:
bool assign(int32_t reg, DataFile f, unsigned int size);
void release(DataFile f, int32_t reg, unsigned int size);
- bool occupy(DataFile f, int32_t reg, unsigned int size);
+ bool occupy(DataFile f, int32_t reg, unsigned int size, bool noTest =
false);
bool occupy(const Value *);
void occupyMask(DataFile f, int32_t reg, uint8_t mask);
@@ -167,9 +167,9 @@ RegisterSet::occupyMask(DataFile f, int32_t reg, uint8_t
mask)
}
bool
-RegisterSet::occupy(DataFile f, int32_t reg, unsigned int size)
+RegisterSet::occupy(DataFile f, int32_t reg, unsigned int size, bool noTest)
{
- if (bits[f].testRange(reg, size))
+ if (!noTest bits[f].testRange(reg, size))
return false;
bits[f].setRange(reg, size);
@@ -1235,7 +1235,7 @@ GCRA::checkInterference(const RIG_Node *node,
Graph::EdgeIterator ei)
INFO_DBG(prog-dbgFlags, REG_ALLOC,
(%%%i) X (%%%i): $r%i + %u\n,
vA-id, vB-id, intf-reg, intf-colors);
- regs.occupy(node-f, intf-reg, intf-colors);
+ regs.occupy(node-f, intf-reg, intf-colors, true);
}
}
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Mesa (master): nvc0/ir: add initial code to support GK110 ISA encoding
Module: Mesa
Branch: master
Commit: 3433471e8b46dd9dd042a00f88ef9ad011a94aac
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3433471e8b46dd9dd042a00f88ef9ad011a94aac
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Sat Sep 1 17:26:24 2012 +0200
nvc0/ir: add initial code to support GK110 ISA encoding
---
src/gallium/drivers/nv50/codegen/nv50_ir_driver.h |5 +
src/gallium/drivers/nv50/codegen/nv50_ir_inlines.h | 25 +
src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp|1 +
.../drivers/nv50/codegen/nv50_ir_target.cpp|1 +
src/gallium/drivers/nvc0/Makefile.sources |1 +
.../drivers/nvc0/codegen/nv50_ir_emit_gk110.cpp| 1628
.../drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp | 23 +-
.../drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp | 10 +-
.../drivers/nvc0/codegen/nv50_ir_target_nvc0.cpp |4 +-
.../drivers/nvc0/codegen/nv50_ir_target_nvc0.h |6 +-
10 files changed, 1691 insertions(+), 13 deletions(-)
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_driver.h
b/src/gallium/drivers/nv50/codegen/nv50_ir_driver.h
index 9632986..446befa 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_driver.h
@@ -93,6 +93,11 @@ struct nv50_ir_prog_symbol
uint32_t offset;
};
+#define NVISA_GF100_CHIPSET_C0 0xc0
+#define NVISA_GF100_CHIPSET_D0 0xd0
+#define NVISA_GK104_CHIPSET0xe0
+#define NVISA_GK110_CHIPSET0xf0
+
struct nv50_ir_prog_info
{
uint16_t target; /* chipset (0x50, 0x84, 0xc0, ...) */
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_inlines.h
b/src/gallium/drivers/nv50/codegen/nv50_ir_inlines.h
index ab4c98f..55a3332 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_inlines.h
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_inlines.h
@@ -73,6 +73,31 @@ static inline unsigned int typeSizeof(DataType ty)
}
}
+static inline unsigned int typeSizeofLog2(DataType ty)
+{
+ switch (ty) {
+ case TYPE_F16:
+ case TYPE_U16:
+ case TYPE_S16:
+ return 1;
+ case TYPE_F32:
+ case TYPE_U32:
+ case TYPE_S32:
+ return 2;
+ case TYPE_F64:
+ case TYPE_U64:
+ case TYPE_S64:
+ return 3;
+ case TYPE_B96:
+ case TYPE_B128:
+ return 4;
+ case TYPE_U8:
+ case TYPE_S8:
+ default:
+ return 0;
+ }
+}
+
static inline DataType typeOfSize(unsigned int size,
bool flt = false, bool sgn = false)
{
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp
b/src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp
index 726331e..1399876 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp
@@ -1907,6 +1907,7 @@ RegAlloc::InsertConstraintsPass::visit(BasicBlock *bb)
texConstraintNVC0(tex);
break;
case 0xe0:
+ case NVISA_GK110_CHIPSET:
texConstraintNVE0(tex);
break;
default:
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_target.cpp
b/src/gallium/drivers/nv50/codegen/nv50_ir_target.cpp
index f718912..707c9e8 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_target.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_target.cpp
@@ -121,6 +121,7 @@ Target *Target::create(unsigned int chipset)
case 0xc0:
case 0xd0:
case 0xe0:
+ case NVISA_GK110_CHIPSET:
return getTargetNVC0(chipset);
case 0x50:
case 0x80:
diff --git a/src/gallium/drivers/nvc0/Makefile.sources
b/src/gallium/drivers/nvc0/Makefile.sources
index d74ecf3..82504bf 100644
--- a/src/gallium/drivers/nvc0/Makefile.sources
+++ b/src/gallium/drivers/nvc0/Makefile.sources
@@ -16,6 +16,7 @@ C_SOURCES := \
nvc0_query.c
CPP_SOURCES := \
+ codegen/nv50_ir_emit_gk110.cpp \
codegen/nv50_ir_emit_nvc0.cpp \
codegen/nv50_ir_lowering_nvc0.cpp \
codegen/nv50_ir_target_nvc0.cpp
diff --git a/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_gk110.cpp
b/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_gk110.cpp
new file mode 100644
index 000..6c229fd
--- /dev/null
+++ b/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_gk110.cpp
@@ -0,0 +1,1628 @@
+/*
+ * Copyright 2012 Christoph Bumiller
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
Mesa (master): nv50/ir/emit: don' t forget saturation bit on f32 add immediate
Module: Mesa
Branch: master
Commit: f3a7be740dd9658097c2518a3bc6ec4ec197ad70
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f3a7be740dd9658097c2518a3bc6ec4ec197ad70
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Sat Aug 18 17:30:50 2012 +0200
nv50/ir/emit: don't forget saturation bit on f32 add immediate
Solved by Maxim Levitsky on IRC.
---
.../drivers/nv50/codegen/nv50_ir_emit_nv50.cpp |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_emit_nv50.cpp
b/src/gallium/drivers/nv50/codegen/nv50_ir_emit_nv50.cpp
index 3ea89ae..bc4657c 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_emit_nv50.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_emit_nv50.cpp
@@ -893,6 +893,8 @@ CodeEmitterNV50::emitFADD(const Instruction *i)
emitForm_IMM(i);
code[0] |= neg0 15;
code[0] |= neg1 22;
+ if (i-saturate)
+ code[0] |= 1 8;
} else
if (i-encSize == 8) {
code[1] = 0;
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Mesa (master): nv50/ir/tgsi: handle DP2 in tgsi Instruction srcMask
Module: Mesa Branch: master Commit: c51f8e2790e9f1aed51133ca0e33dac236fba4a0 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c51f8e2790e9f1aed51133ca0e33dac236fba4a0 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Sat Aug 18 17:34:44 2012 +0200 nv50/ir/tgsi: handle DP2 in tgsi Instruction srcMask Solved by Tiziano Bacocco on IRC. --- .../drivers/nv50/codegen/nv50_ir_from_tgsi.cpp |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp index 16f191d..071674b 100644 --- a/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp +++ b/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp @@ -214,6 +214,8 @@ unsigned int Instruction::srcMask(unsigned int s) const case TGSI_OPCODE_COS: case TGSI_OPCODE_SIN: return (mask 0x8) | ((mask 0x7) ? 0x1 : 0x0); + case TGSI_OPCODE_DP2: + return 0x3; case TGSI_OPCODE_DP3: return 0x7; case TGSI_OPCODE_DP4: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nv50: fix resource_resolve shader start offsets
Module: Mesa
Branch: master
Commit: cd3d85b63daf59a0574fe99dc516e043a1c9c329
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd3d85b63daf59a0574fe99dc516e043a1c9c329
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Mon Jul 23 13:04:34 2012 +0200
nv50: fix resource_resolve shader start offsets
---
src/gallium/drivers/nv50/nv50_surface.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_surface.c
b/src/gallium/drivers/nv50/nv50_surface.c
index 15c88d5..0872f8d 100644
--- a/src/gallium/drivers/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nv50/nv50_surface.c
@@ -637,14 +637,14 @@ nv50_blitctx_get_color_mask_and_fp(struct nv50_blitctx
*blit,
switch (format) {
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- blit-fp_offset = 160;
+ blit-fp_offset = 0xb0;
if (mask PIPE_MASK_Z)
blit-color_mask |= 0x0111;
if (mask PIPE_MASK_S)
blit-color_mask |= 0x1000;
break;
case PIPE_FORMAT_S8_UINT_Z24_UNORM:
- blit-fp_offset = 24;
+ blit-fp_offset = 0x18;
if (mask PIPE_MASK_Z)
blit-color_mask |= 0x1110;
if (mask PIPE_MASK_S)
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Mesa (master): gallium: specify resource_resolve destination via a pipe_surface
Module: Mesa
Branch: master
Commit: 5d5af7d359e0060fa00b90a8f04900b96f9058b0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d5af7d359e0060fa00b90a8f04900b96f9058b0
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Wed Jul 25 13:47:58 2012 +0200
gallium: specify resource_resolve destination via a pipe_surface
The format member of pipe_surface may differ from that of the
pipe_resource, which is used to communicate, for instance, whether
sRGB encode should be enabled in the resolve operation or not.
Fixes resolve to sRGB surfaces in mesa/st when GL_FRAMEBUFFER_SRGB
is disabled.
Reviewed-by: Brian Paul bri...@vmware.com
---
src/gallium/drivers/nv30/nv30_miptree.c |5 +++-
src/gallium/drivers/nv50/nv50_surface.c | 32 --
src/gallium/drivers/nvc0/nvc0_surface.c | 32 --
src/gallium/drivers/r300/r300_render.c |7 +-
src/gallium/include/pipe/p_state.h |6 +---
src/mesa/state_tracker/st_cb_blit.c | 15 +
6 files changed, 39 insertions(+), 58 deletions(-)
diff --git a/src/gallium/drivers/nv30/nv30_miptree.c
b/src/gallium/drivers/nv30/nv30_miptree.c
index 7e67729..cd6a814 100644
--- a/src/gallium/drivers/nv30/nv30_miptree.c
+++ b/src/gallium/drivers/nv30/nv30_miptree.c
@@ -153,7 +153,10 @@ nv30_resource_resolve(struct pipe_context *pipe,
define_rect(info-src.res, 0, 0, info-src.x0, info-src.y0,
info-src.x1 - info-src.x0, info-src.y1 - info-src.y0, src);
- define_rect(info-dst.res, info-dst.level, 0, info-dst.x0, info-dst.y0,
+ define_rect(info-dst.surface-texture,
+ info-dst.surface-u.tex.level,
+ info-dst.surface-u.tex.first_layer,
+ info-dst.x0, info-dst.y0,
info-dst.x1 - info-dst.x0, info-dst.y1 - info-dst.y0, dst);
nv30_transfer_rect(nv30, BILINEAR, src, dst);
diff --git a/src/gallium/drivers/nv50/nv50_surface.c
b/src/gallium/drivers/nv50/nv50_surface.c
index 0872f8d..ed5223b 100644
--- a/src/gallium/drivers/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nv50/nv50_surface.c
@@ -436,6 +436,7 @@ struct nv50_blitctx
unsigned num_samplers[3];
struct pipe_sampler_view *texture[2];
struct nv50_tsc_entry *sampler[2];
+ enum pipe_format format;
unsigned dirty;
} saved;
struct nv50_program vp;
@@ -661,26 +662,19 @@ nv50_blitctx_get_color_mask_and_fp(struct nv50_blitctx
*blit,
}
static void
-nv50_blit_set_dst(struct nv50_context *nv50,
- struct pipe_resource *res, unsigned level, unsigned layer)
+nv50_blit_set_dst(struct nv50_context *nv50, struct pipe_surface *surf,
+ struct nv50_blitctx *blit)
{
- struct pipe_context *pipe = nv50-base.pipe;
- struct pipe_surface templ;
+ blit-saved.format = surf-format;
- if (util_format_is_depth_or_stencil(res-format))
- templ.format = nv50_blit_zeta_to_colour_format(res-format);
- else
- templ.format = res-format;
-
- templ.usage = PIPE_USAGE_STREAM;
- templ.u.tex.level = level;
- templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
+ if (util_format_is_depth_or_stencil(surf-format))
+ surf-format = nv50_blit_zeta_to_colour_format(surf-format);
- nv50-framebuffer.cbufs[0] = nv50_miptree_surface_new(pipe, res, templ);
+ nv50-framebuffer.cbufs[0] = surf;
nv50-framebuffer.nr_cbufs = 1;
nv50-framebuffer.zsbuf = NULL;
- nv50-framebuffer.width = nv50-framebuffer.cbufs[0]-width;
- nv50-framebuffer.height = nv50-framebuffer.cbufs[0]-height;
+ nv50-framebuffer.width = surf-width;
+ nv50-framebuffer.height = surf-height;
}
static INLINE void
@@ -822,7 +816,7 @@ nv50_blitctx_post_blit(struct nv50_context *nv50, struct
nv50_blitctx *blit)
{
int s;
- pipe_surface_reference(nv50-framebuffer.cbufs[0], NULL);
+ nv50-framebuffer.cbufs[0]-format = blit-saved.format;
nv50-framebuffer.width = blit-saved.fb.width;
nv50-framebuffer.height = blit-saved.fb.height;
@@ -862,7 +856,7 @@ nv50_resource_resolve(struct pipe_context *pipe,
struct nv50_blitctx *blit = screen-blitctx;
struct nouveau_pushbuf *push = nv50-base.pushbuf;
struct pipe_resource *src = info-src.res;
- struct pipe_resource *dst = info-dst.res;
+ struct pipe_resource *dst = info-dst.surface-texture;
float x0, x1, y0, y1, z;
float x_range, y_range;
@@ -872,8 +866,8 @@ nv50_resource_resolve(struct pipe_context *pipe,
nv50_blitctx_pre_blit(blit, nv50);
- nv50_blit_set_dst(nv50, dst, info-dst.level, info-dst.layer);
- nv50_blit_set_src(nv50, src, 0, info-src.layer);
+ nv50_blit_set_dst(nv50, info-dst.surface, blit);
+ nv50_blit_set_src(nv50, src, 0, info-src.layer);
nv50_blitctx_prepare_state(blit);
diff --git a/src/gallium/drivers/nvc0/nvc0_surface.c
b/src/gallium/drivers/nvc0/nvc0_surface.c
index 607b02e..6773f96 100644
--- a/src/gallium/drivers/nvc0/nvc0_surface.c
+++ b/src/gallium/drivers
Mesa (master): nv50: fix depth/stencil multisample memory storage types
Module: Mesa
Branch: master
Commit: acd66ec03346d37c593b5ba13e4c94ae11eef50d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=acd66ec03346d37c593b5ba13e4c94ae11eef50d
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Wed Jul 25 16:16:11 2012 +0200
nv50: fix depth/stencil multisample memory storage types
Leftover from libdrm_nouveau v2 interface change.
---
src/gallium/drivers/nv50/nv50_miptree.c | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_miptree.c
b/src/gallium/drivers/nv50/nv50_miptree.c
index 5ba8cf8..7b8dfb8 100644
--- a/src/gallium/drivers/nv50/nv50_miptree.c
+++ b/src/gallium/drivers/nv50/nv50_miptree.c
@@ -37,7 +37,7 @@ nv50_tex_choose_tile_dims(unsigned nx, unsigned ny, unsigned
nz)
static uint32_t
nv50_mt_choose_storage_type(struct nv50_miptree *mt, boolean compressed)
{
- const unsigned ms = util_logbase2(mt-base.base.nr_samples);
+ const unsigned ms = mt-ms_x + mt-ms_y;
uint32_t tile_flags;
@@ -48,20 +48,20 @@ nv50_mt_choose_storage_type(struct nv50_miptree *mt,
boolean compressed)
switch (mt-base.base.format) {
case PIPE_FORMAT_Z16_UNORM:
- tile_flags = 0x6c + (ms 8);
+ tile_flags = 0x6c + ms;
break;
case PIPE_FORMAT_S8_UINT_Z24_UNORM:
- tile_flags = 0x18 + (ms 8);
+ tile_flags = 0x18 + ms;
break;
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- tile_flags = 0x128 + (ms 8);
+ tile_flags = 0x128 + ms;
break;
case PIPE_FORMAT_Z32_FLOAT:
- tile_flags = 0x40 + (ms 8);
+ tile_flags = 0x40 + ms;
break;
case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
- tile_flags = 0x60 + (ms 8);
+ tile_flags = 0x60 + ms;
break;
default:
switch (util_format_get_blocksizebits(mt-base.base.format)) {
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