Mesa (master): nir: Add lowering for find_lsb.
Module: Mesa
Branch: master
Commit: 6a0db5f08ffac7d43a5b937982262f357a21f95b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a0db5f08ffac7d43a5b937982262f357a21f95b
Author: Eric Anholt
Date: Fri May 4 14:02:55 2018 -0700
nir: Add lowering for find_lsb.
There is a fairly simple relation to turn this into ufind_msb.
Reviewed-by: Matt Turner
Reviewed-by: Ian Romanick
---
src/compiler/nir/nir.h| 2 ++
src/compiler/nir/nir_opt_algebraic.py | 4
2 files changed, 6 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 9fca61f007..b9426f8eb4 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1915,6 +1915,8 @@ typedef struct nir_shader_compiler_options {
bool lower_bfm;
/** Lowers ifind_msb to compare and ufind_msb */
bool lower_ifind_msb;
+ /** Lowers find_lsb to ufind_msb and logic ops */
+ bool lower_find_lsb;
bool lower_uadd_carry;
bool lower_usub_borrow;
/** lowers fneg and ineg to fsub and isub. */
diff --git a/src/compiler/nir/nir_opt_algebraic.py
b/src/compiler/nir/nir_opt_algebraic.py
index f6685977f3..db907df854 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -559,6 +559,10 @@ optimizations = [
('ufind_msb', ('bcsel', ('ilt', 'value', 0), ('inot', 'value'), 'value')),
'options->lower_ifind_msb'),
+ (('find_lsb', 'value'),
+('ufind_msb', ('iand', 'value', ('ineg', 'value'))),
+'options->lower_find_lsb'),
+
(('extract_i8', a, 'b@32'),
('ishr', ('ishl', a, ('imul', ('isub', 3, b), 8)), 24),
'options->lower_extract_byte'),
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Mesa (master): nir: Add lowering for bitfieldInsert without using bfi.
Module: Mesa
Branch: master
Commit: 74618ccbcab6d785152c2840525d5bef08ed0696
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=74618ccbcab6d785152c2840525d5bef08ed0696
Author: Eric Anholt
Date: Wed May 2 14:13:23 2018 -0700
nir: Add lowering for bitfieldInsert without using bfi.
If you don't have HW to do bfi, then lowering bitfieldInsert to bfi makes
things harder than keeping the "bits" argument around.
This still uses bfm, but I've added the obvious lowering of bfm if you
need it.
Reviewed-by: Matt Turner
Reviewed-by: Ian Romanick
---
src/compiler/nir/nir.h| 5 +
src/compiler/nir/nir_opt_algebraic.py | 14 ++
2 files changed, 19 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 5a1f79515a..6c0276fcc7 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1904,7 +1904,12 @@ typedef struct nir_shader_compiler_options {
bool lower_fmod32;
bool lower_fmod64;
bool lower_bitfield_extract;
+ /** Lowers bitfield_insert to bfi/bfm */
bool lower_bitfield_insert;
+ /** Lowers bitfield_insert to bfm, compares, and shifts. */
+ bool lower_bitfield_insert_to_shifts;
+ /** Lowers bfm to shifts and subtracts. */
+ bool lower_bfm;
bool lower_uadd_carry;
bool lower_usub_borrow;
/** lowers fneg and ineg to fsub and isub. */
diff --git a/src/compiler/nir/nir_opt_algebraic.py
b/src/compiler/nir/nir_opt_algebraic.py
index fdfb0250b0..878d13ded5 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -515,6 +515,20 @@ optimizations = [
('bfi', ('bfm', 'bits', 'offset'), 'insert', 'base')),
'options->lower_bitfield_insert'),
+ # Alternative lowering that doesn't rely on bfi.
+ (('bitfield_insert', 'base', 'insert', 'offset', 'bits'),
+('bcsel', ('ilt', 31, 'bits'),
+ 'insert',
+ ('ior',
+ ('iand', 'base', ('inot', ('bfm', 'bits', 'offset'))),
+ ('iand', ('ishl', 'insert', 'offset'), ('bfm', 'bits', 'offset',
+'options->lower_bitfield_insert_to_shifts'),
+
+ # bfm lowering -- note that the NIR opcode is undefined if either arg is 32.
+ (('bfm', 'bits', 'offset'),
+('ishl', ('isub', ('ishl', 1, 'bits'), 1), 'offset'),
+'options->lower_bfm'),
+
(('ibitfield_extract', 'value', 'offset', 'bits'),
('bcsel', ('ilt', 31, 'bits'), 'value',
('ibfe', 'value', 'offset', 'bits')),
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Mesa (master): nir: Look into uniform structs for samplers when counting num_textures.
Module: Mesa
Branch: master
Commit: 833c4046007f22ce1da0e1c2b89e8f1892f8d38e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=833c4046007f22ce1da0e1c2b89e8f1892f8d38e
Author: Eric Anholt
Date: Fri Mar 30 16:04:34 2018 -0700
nir: Look into uniform structs for samplers when counting num_textures.
mesa/st decides whether to update samplers after a program change based on
whether num_textures is nonzero. By not counting samplers in a uniform
struct, we would segfault in
KHR-GLES3.shaders.struct.uniform.sampler_vertex if it was run in the same
context after a non-vertex-shader-uniform testcase (as is the case during
a full conformance run).
v2: Implement using two separate pure functions instead of updating
pointers.
Reviewed-by: Jason Ekstrand
---
src/compiler/nir/nir_gather_info.c | 56 ++
1 file changed, 44 insertions(+), 12 deletions(-)
diff --git a/src/compiler/nir/nir_gather_info.c
b/src/compiler/nir/nir_gather_info.c
index dba9f199ec..3534b6949e 100644
--- a/src/compiler/nir/nir_gather_info.c
+++ b/src/compiler/nir/nir_gather_info.c
@@ -352,24 +352,56 @@ gather_info_block(nir_block *block, nir_shader *shader)
}
}
+static unsigned
+glsl_type_get_sampler_count(const struct glsl_type *type)
+{
+ if (glsl_type_is_array(type)) {
+ return (glsl_get_aoa_size(type) *
+ glsl_type_get_sampler_count(glsl_without_array(type)));
+ }
+
+ if (glsl_type_is_struct(type)) {
+ unsigned count = 0;
+ for (int i = 0; i < glsl_get_length(type); i++)
+ count += glsl_type_get_sampler_count(glsl_get_struct_field(type, i));
+ return count;
+ }
+
+ if (glsl_type_is_sampler(type))
+ return 1;
+
+ return 0;
+}
+
+static unsigned
+glsl_type_get_image_count(const struct glsl_type *type)
+{
+ if (glsl_type_is_array(type)) {
+ return (glsl_get_aoa_size(type) *
+ glsl_type_get_image_count(glsl_without_array(type)));
+ }
+
+ if (glsl_type_is_struct(type)) {
+ unsigned count = 0;
+ for (int i = 0; i < glsl_get_length(type); i++)
+ count += glsl_type_get_image_count(glsl_get_struct_field(type, i));
+ return count;
+ }
+
+ if (glsl_type_is_image(type))
+ return 1;
+
+ return 0;
+}
+
void
nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint)
{
shader->info.num_textures = 0;
shader->info.num_images = 0;
nir_foreach_variable(var, >uniforms) {
- const struct glsl_type *type = var->type;
- unsigned count = 1;
- if (glsl_type_is_array(type)) {
- count = glsl_get_aoa_size(type);
- type = glsl_without_array(type);
- }
-
- if (glsl_type_is_image(type)) {
- shader->info.num_images += count;
- } else if (glsl_type_is_sampler(type)) {
- shader->info.num_textures += count;
- }
+ shader->info.num_textures += glsl_type_get_sampler_count(var->type);
+ shader->info.num_images += glsl_type_get_image_count(var->type);
}
shader->info.inputs_read = 0;
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Mesa (master): nir: Add lowering from ibitfield_extract/ubitfield_extract to shifts.
Module: Mesa
Branch: master
Commit: af88acf4c4e2e14161872752fb9fb4683f9c8845
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=af88acf4c4e2e14161872752fb9fb4683f9c8845
Author: Eric Anholt
Date: Wed May 2 13:02:21 2018 -0700
nir: Add lowering from ibitfield_extract/ubitfield_extract to shifts.
V3D doesn't have opcodes for ibfe/ubfe, so we need to lower similarly to
glsl/lower_instructions.cpp.
Reviewed-by: Matt Turner
Reviewed-by: Ian Romanick
---
src/compiler/nir/nir.h| 3 +++
src/compiler/nir/nir_opt_algebraic.py | 16
2 files changed, 19 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 6c0276fcc7..519c019887 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1903,7 +1903,10 @@ typedef struct nir_shader_compiler_options {
bool lower_fsqrt;
bool lower_fmod32;
bool lower_fmod64;
+ /** Lowers ibitfield_extract/ubitfield_extract to ibfe/ubfe. */
bool lower_bitfield_extract;
+ /** Lowers ibitfield_extract/ubitfield_extract to bfm, compares, shifts. */
+ bool lower_bitfield_extract_to_shifts;
/** Lowers bitfield_insert to bfi/bfm */
bool lower_bitfield_insert;
/** Lowers bitfield_insert to bfm, compares, and shifts. */
diff --git a/src/compiler/nir/nir_opt_algebraic.py
b/src/compiler/nir/nir_opt_algebraic.py
index 878d13ded5..eaa8b14164 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -539,6 +539,22 @@ optimizations = [
('ubfe', 'value', 'offset', 'bits')),
'options->lower_bitfield_extract'),
+ (('ibitfield_extract', 'value', 'offset', 'bits'),
+('bcsel', ('ieq', 0, 'bits'),
+ 0,
+ ('ishr',
+ ('ishl', 'value', ('isub', ('isub', 32, 'bits'), 'offset')),
+ ('isub', 32, 'bits'))),
+'options->lower_bitfield_extract_to_shifts'),
+
+ (('ubitfield_extract', 'value', 'offset', 'bits'),
+('iand',
+ ('ushr', 'value', 'offset'),
+ ('bcsel', ('ieq', 'bits', 32),
+ 0x,
+ ('bfm', 'bits', 0))),
+'options->lower_bitfield_extract_to_shifts'),
+
(('extract_i8', a, 'b@32'),
('ishr', ('ishl', a, ('imul', ('isub', 3, b), 8)), 24),
'options->lower_extract_byte'),
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Mesa (master): nir: Add lowering for nir_op_bit_count.
Module: Mesa
Branch: master
Commit: 73953b071365ca64db353023fff78a06b20503a3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=73953b071365ca64db353023fff78a06b20503a3
Author: Eric Anholt
Date: Tue May 8 13:04:37 2018 -0700
nir: Add lowering for nir_op_bit_count.
This is basically the same as the GLSL lowering path.
v2: Fix typo in the link
Reviewed-by: Matt Turner
Reviewed-by: Ian Romanick
---
src/compiler/nir/nir.h | 2 ++
src/compiler/nir/nir_lower_alu.c | 36
2 files changed, 38 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 06154aa990..bb477742dc 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1913,6 +1913,8 @@ typedef struct nir_shader_compiler_options {
bool lower_bitfield_insert_to_shifts;
/** Lowers bitfield_reverse to shifts. */
bool lower_bitfield_reverse;
+ /** Lowers bit_count to shifts. */
+ bool lower_bit_count;
/** Lowers bfm to shifts and subtracts. */
bool lower_bfm;
/** Lowers ifind_msb to compare and ufind_msb */
diff --git a/src/compiler/nir/nir_lower_alu.c b/src/compiler/nir/nir_lower_alu.c
index ff977f0169..8d1a1d3746 100644
--- a/src/compiler/nir/nir_lower_alu.c
+++ b/src/compiler/nir/nir_lower_alu.c
@@ -94,6 +94,42 @@ lower_alu_instr(nir_alu_instr *instr, nir_builder *b)
}
break;
+ case nir_op_bit_count:
+ if (b->shader->options->lower_bit_count) {
+ /* For more details, see:
+ *
+ *
http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
+ */
+ nir_ssa_def *c1 = nir_imm_int(b, 1);
+ nir_ssa_def *c2 = nir_imm_int(b, 2);
+ nir_ssa_def *c4 = nir_imm_int(b, 4);
+ nir_ssa_def *c24 = nir_imm_int(b, 24);
+ nir_ssa_def *c = nir_imm_int(b, 0x);
+ nir_ssa_def *c = nir_imm_int(b, 0x);
+ nir_ssa_def *c0f0f0f0f = nir_imm_int(b, 0x0f0f0f0f);
+ nir_ssa_def *c01010101 = nir_imm_int(b, 0x01010101);
+
+ lowered = nir_ssa_for_alu_src(b, instr, 0);
+
+ lowered = nir_isub(b, lowered,
+nir_iand(b, nir_ushr(b, lowered, c1), c));
+
+ lowered = nir_iadd(b,
+nir_iand(b, lowered, c),
+nir_iand(b, nir_ushr(b, lowered, c2), c));
+
+ lowered = nir_ushr(b,
+nir_imul(b,
+ nir_iand(b,
+ nir_iadd(b,
+ lowered,
+ nir_ushr(b, lowered,
c4)),
+ c0f0f0f0f),
+ c01010101),
+c24);
+ }
+ break;
+
case nir_op_imul_high:
case nir_op_umul_high:
if (b->shader->options->lower_mul_high) {
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Mesa (master): nir: Add lowering for ifind_msb to ufind_msb.
Module: Mesa
Branch: master
Commit: d4c7c3c225b7c34669498c15c2d3186cf6a4647e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4c7c3c225b7c34669498c15c2d3186cf6a4647e
Author: Eric Anholt
Date: Fri May 4 13:33:47 2018 -0700
nir: Add lowering for ifind_msb to ufind_msb.
ufind_msb is easily expressed in terms of clz, and we can reduce ifind_msb
to that.
Reviewed-by: Matt Turner
Reviewed-by: Ian Romanick
---
src/compiler/nir/nir.h| 2 ++
src/compiler/nir/nir_opt_algebraic.py | 4
2 files changed, 6 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 519c019887..9fca61f007 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1913,6 +1913,8 @@ typedef struct nir_shader_compiler_options {
bool lower_bitfield_insert_to_shifts;
/** Lowers bfm to shifts and subtracts. */
bool lower_bfm;
+ /** Lowers ifind_msb to compare and ufind_msb */
+ bool lower_ifind_msb;
bool lower_uadd_carry;
bool lower_usub_borrow;
/** lowers fneg and ineg to fsub and isub. */
diff --git a/src/compiler/nir/nir_opt_algebraic.py
b/src/compiler/nir/nir_opt_algebraic.py
index eaa8b14164..f6685977f3 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -555,6 +555,10 @@ optimizations = [
('bfm', 'bits', 0))),
'options->lower_bitfield_extract_to_shifts'),
+ (('ifind_msb', 'value'),
+('ufind_msb', ('bcsel', ('ilt', 'value', 0), ('inot', 'value'), 'value')),
+'options->lower_ifind_msb'),
+
(('extract_i8', a, 'b@32'),
('ishr', ('ishl', a, ('imul', ('isub', 3, b), 8)), 24),
'options->lower_extract_byte'),
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Mesa (master): v3d: Enable the new NIR bitfield operation lowering paths.
Module: Mesa
Branch: master
Commit: 9d5860310d57db9b3aabf0c0e562130fb8dcce99
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d5860310d57db9b3aabf0c0e562130fb8dcce99
Author: Eric Anholt
Date: Wed May 2 14:17:07 2018 -0700
v3d: Enable the new NIR bitfield operation lowering paths.
These together get the GLSL 3.00 unorm/snorm pack functions and
MESA_shader_integer operations working.
v2: Fix commit message typo.
Reviewed-by: Matt Turner
Reviewed-by: Ian Romanick
---
src/broadcom/compiler/nir_to_vir.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/src/broadcom/compiler/nir_to_vir.c
b/src/broadcom/compiler/nir_to_vir.c
index ec8f22321f..0f7e47689d 100644
--- a/src/broadcom/compiler/nir_to_vir.c
+++ b/src/broadcom/compiler/nir_to_vir.c
@@ -755,6 +755,10 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
result = vir_NOT(c, src[0]);
break;
+case nir_op_ufind_msb:
+result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
+break;
+
case nir_op_imul:
result = vir_UMUL(c, src[0], src[1]);
break;
@@ -853,6 +857,13 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
result = vir_FDY(c, src[0]);
break;
+case nir_op_uadd_carry:
+vir_PF(c, vir_ADD(c, src[0], src[1]), V3D_QPU_PF_PUSHC);
+result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
+vir_uniform_ui(c, ~0),
+vir_uniform_ui(c, 0)));
+break;
+
default:
fprintf(stderr, "unknown NIR ALU inst: ");
nir_print_instr(>instr, stderr);
@@ -1894,8 +1905,11 @@ const nir_shader_compiler_options v3d_nir_options = {
.lower_all_io_to_temps = true,
.lower_extract_byte = true,
.lower_extract_word = true,
-.lower_bitfield_insert = true,
-.lower_bitfield_extract = true,
+.lower_bfm = true,
+.lower_bitfield_insert_to_shifts = true,
+.lower_bitfield_extract_to_shifts = true,
+.lower_bitfield_reverse = true,
+.lower_bit_count = true,
.lower_pack_unorm_2x16 = true,
.lower_pack_snorm_2x16 = true,
.lower_pack_unorm_4x8 = true,
@@ -1903,12 +1917,15 @@ const nir_shader_compiler_options v3d_nir_options = {
.lower_unpack_unorm_4x8 = true,
.lower_unpack_snorm_4x8 = true,
.lower_fdiv = true,
+.lower_find_lsb = true,
.lower_ffma = true,
.lower_flrp32 = true,
.lower_fpow = true,
.lower_fsat = true,
.lower_fsqrt = true,
+.lower_ifind_msb = true,
.lower_ldexp = true,
+.lower_mul_high = true,
.native_integers = true,
};
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Mesa (master): nir: Add an ALU lowering pass for mul_high.
Module: Mesa
Branch: master
Commit: 6e1597c2d9f5e14ffaf1c326985ee3203f995044
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e1597c2d9f5e14ffaf1c326985ee3203f995044
Author: Eric Anholt
Date: Tue May 8 11:24:40 2018 -0700
nir: Add an ALU lowering pass for mul_high.
This is based on the glsl/lower_instructions.cpp implementation, but
should be much more readable.
Reviewed-by: Matt Turner
Reviewed-by: Ian Romanick
---
src/compiler/Makefile.sources | 1 +
src/compiler/nir/meson.build | 1 +
src/compiler/nir/nir.h| 3 +
src/compiler/nir/nir_lower_alu.c | 165 ++
src/mesa/state_tracker/st_glsl_to_nir.cpp | 1 +
5 files changed, 171 insertions(+)
diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index 3daa2c5133..d629c2b8ec 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -214,6 +214,7 @@ NIR_FILES = \
nir/nir_loop_analyze.c \
nir/nir_loop_analyze.h \
nir/nir_lower_alpha_test.c \
+ nir/nir_lower_alu.c \
nir/nir_lower_alu_to_scalar.c \
nir/nir_lower_atomics_to_ssbo.c \
nir/nir_lower_bitmap.c \
diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
index 3fec363691..598c68aff9 100644
--- a/src/compiler/nir/meson.build
+++ b/src/compiler/nir/meson.build
@@ -104,6 +104,7 @@ files_libnir = files(
'nir_liveness.c',
'nir_loop_analyze.c',
'nir_loop_analyze.h',
+ 'nir_lower_alu.c',
'nir_lower_alu_to_scalar.c',
'nir_lower_alpha_test.c',
'nir_lower_atomics_to_ssbo.c',
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index b9426f8eb4..7d01eb23bc 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1919,6 +1919,8 @@ typedef struct nir_shader_compiler_options {
bool lower_find_lsb;
bool lower_uadd_carry;
bool lower_usub_borrow;
+ /** Lowers imul_high/umul_high to 16-bit multiplies and carry operations. */
+ bool lower_mul_high;
/** lowers fneg and ineg to fsub and isub. */
bool lower_negate;
/** lowers fsub and isub to fadd+fneg and iadd+ineg. */
@@ -2628,6 +2630,7 @@ bool nir_move_vec_src_uses_to_dest(nir_shader *shader);
bool nir_lower_vec_to_movs(nir_shader *shader);
void nir_lower_alpha_test(nir_shader *shader, enum compare_func func,
bool alpha_to_one);
+bool nir_lower_alu(nir_shader *shader);
bool nir_lower_alu_to_scalar(nir_shader *shader);
bool nir_lower_load_const_to_scalar(nir_shader *shader);
bool nir_lower_read_invocation_to_scalar(nir_shader *shader);
diff --git a/src/compiler/nir/nir_lower_alu.c b/src/compiler/nir/nir_lower_alu.c
new file mode 100644
index 00..28ecaf6bad
--- /dev/null
+++ b/src/compiler/nir/nir_lower_alu.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright © 2010 Intel Corporation
+ * Copyright © 2018 Broadcom
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "nir.h"
+#include "nir_builder.h"
+
+/** nir_lower_alu.c
+ *
+ * NIR's home for miscellaneous ALU operation lowering implementations.
+ *
+ * Most NIR ALU lowering occurs in nir_opt_algebraic.py, since it's generally
+ * easy to write them there. However, if terms appear multiple times in the
+ * lowered code, it can get very verbose and cause a lot of work for CSE, so
+ * it may end up being easier to write out in C code.
+ *
+ * The shader must be in SSA for this pass.
+ */
+
+#define LOWER_MUL_HIGH (1 << 0)
+
+static bool
+lower_alu_instr(nir_alu_instr *instr, nir_builder *b)
+{
+ nir_ssa_def *lowered = NULL;
+
+ assert(instr->dest.dest.is_ssa);
+
+ b->cursor = nir_before_instr(>instr);
+ b->exact = instr->exact;
+
+ switch (instr->op) {
+ case nir_op_imul_high:
+ case nir_op_umul_high:
+ if (b->shader->options->lower_mul_high) {
Mesa (master): v3d: Work around GFXH-1461/GFXH-1689 by using CLEAR_TILE_BUFFERS.
Module: Mesa
Branch: master
Commit: f69473a712147c27fefbe83b9beacb251969fd92
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f69473a712147c27fefbe83b9beacb251969fd92
Author: Eric Anholt
Date: Wed May 2 11:45:07 2018 -0700
v3d: Work around GFXH-1461/GFXH-1689 by using CLEAR_TILE_BUFFERS.
This doesn't seem to have done anything to my test results. However,
given that we've still got a class of GPU hangs, following the workarounds
that the closed driver does so that we get the same command sequences
seems like a good idea.
---
src/gallium/drivers/v3d/v3dx_rcl.c | 27 +--
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/v3d/v3dx_rcl.c
b/src/gallium/drivers/v3d/v3dx_rcl.c
index 5be29aca1f..766f7909c1 100644
--- a/src/gallium/drivers/v3d/v3dx_rcl.c
+++ b/src/gallium/drivers/v3d/v3dx_rcl.c
@@ -130,10 +130,7 @@ store_general(struct v3d_job *job,
store.address = cl_address(rsc->bo, surf->offset);
#if V3D_VERSION >= 40
-store.clear_buffer_being_stored =
-((job->cleared & pipe_bit) &&
- (general_color_clear ||
- !(pipe_bit & PIPE_CLEAR_COLOR_BUFFERS)));
+store.clear_buffer_being_stored = false;
if (separate_stencil)
store.output_image_format = V3D_OUTPUT_IMAGE_FORMAT_S8;
@@ -269,6 +266,7 @@ v3d_rcl_emit_loads(struct v3d_job *job, struct v3d_cl *cl)
static void
v3d_rcl_emit_stores(struct v3d_job *job, struct v3d_cl *cl)
{
+#if V3D_VERSION < 40
MAYBE_UNUSED bool needs_color_clear = job->cleared &
PIPE_CLEAR_COLOR_BUFFERS;
MAYBE_UNUSED bool needs_z_clear = job->cleared & PIPE_CLEAR_DEPTH;
MAYBE_UNUSED bool needs_s_clear = job->cleared & PIPE_CLEAR_STENCIL;
@@ -290,6 +288,9 @@ v3d_rcl_emit_stores(struct v3d_job *job, struct v3d_cl *cl)
bool general_color_clear = (needs_color_clear &&
(job->cleared & PIPE_CLEAR_COLOR_BUFFERS)
==
(job->resolve & PIPE_CLEAR_COLOR_BUFFERS));
+#else
+bool general_color_clear = false;
+#endif
uint32_t stores_pending = job->resolve;
@@ -342,8 +343,8 @@ v3d_rcl_emit_stores(struct v3d_job *job, struct v3d_cl *cl)
}
}
-if (stores_pending) {
#if V3D_VERSION < 40
+if (stores_pending) {
cl_emit(cl,
STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED, store) {
store.disable_color_buffer_write =
@@ -362,23 +363,29 @@ v3d_rcl_emit_stores(struct v3d_job *job, struct v3d_cl
*cl)
store.disable_stencil_buffer_clear_on_write =
!needs_s_clear;
};
-#else /* V3D_VERSION >= 40 */
-unreachable("All color buffers should have been stored.");
-#endif /* V3D_VERSION >= 40 */
} else if (needs_color_clear && !general_color_clear) {
/* If we didn't do our color clears in the general packet,
* then emit a packet to clear all the TLB color buffers now.
*/
-#if V3D_VERSION < 40
cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
store.buffer_to_store = NONE;
}
+}
#else /* V3D_VERSION >= 40 */
+assert(!stores_pending);
+
+/* GFXH-1461/GFXH-1689: The per-buffer store command's clear
+ * buffer bit is broken for depth/stencil. In addition, the
+ * clear packet's Z/S bit is broken, but the RTs bit ends up
+ * clearing Z/S.
+ */
+if (job->cleared) {
cl_emit(cl, CLEAR_TILE_BUFFERS, clear) {
+clear.clear_z_stencil_buffer = true;
clear.clear_all_render_targets = true;
}
-#endif /* V3D_VERSION >= 40 */
}
+#endif /* V3D_VERSION >= 40 */
}
static void
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Mesa (master): nir: Add lowering for nir_op_bitfield_reverse.
Module: Mesa
Branch: master
Commit: 7afa26d4e39c73502ad75b95605197eb52c8d099
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7afa26d4e39c73502ad75b95605197eb52c8d099
Author: Eric Anholt
Date: Tue May 8 12:47:48 2018 -0700
nir: Add lowering for nir_op_bitfield_reverse.
This is basically the same as the GLSL lowering path.
Reviewed-by: Matt Turner
Reviewed-by: Ian Romanick
---
src/compiler/nir/nir.h | 2 ++
src/compiler/nir/nir_lower_alu.c | 47 +++-
2 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 7d01eb23bc..06154aa990 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1911,6 +1911,8 @@ typedef struct nir_shader_compiler_options {
bool lower_bitfield_insert;
/** Lowers bitfield_insert to bfm, compares, and shifts. */
bool lower_bitfield_insert_to_shifts;
+ /** Lowers bitfield_reverse to shifts. */
+ bool lower_bitfield_reverse;
/** Lowers bfm to shifts and subtracts. */
bool lower_bfm;
/** Lowers ifind_msb to compare and ufind_msb */
diff --git a/src/compiler/nir/nir_lower_alu.c b/src/compiler/nir/nir_lower_alu.c
index 28ecaf6bad..ff977f0169 100644
--- a/src/compiler/nir/nir_lower_alu.c
+++ b/src/compiler/nir/nir_lower_alu.c
@@ -50,6 +50,50 @@ lower_alu_instr(nir_alu_instr *instr, nir_builder *b)
b->exact = instr->exact;
switch (instr->op) {
+ case nir_op_bitfield_reverse:
+ if (b->shader->options->lower_bitfield_reverse) {
+ /* For more details, see:
+ *
+ * http://graphics.stanford.edu/~seander/bithacks.html#ReverseParallel
+ */
+ nir_ssa_def *c1 = nir_imm_int(b, 1);
+ nir_ssa_def *c2 = nir_imm_int(b, 2);
+ nir_ssa_def *c4 = nir_imm_int(b, 4);
+ nir_ssa_def *c8 = nir_imm_int(b, 8);
+ nir_ssa_def *c16 = nir_imm_int(b, 16);
+ nir_ssa_def *c = nir_imm_int(b, 0x);
+ nir_ssa_def *c = nir_imm_int(b, 0x);
+ nir_ssa_def *c0f0f0f0f = nir_imm_int(b, 0x0f0f0f0f);
+ nir_ssa_def *c00ff00ff = nir_imm_int(b, 0x00ff00ff);
+
+ lowered = nir_ssa_for_alu_src(b, instr, 0);
+
+ /* Swap odd and even bits. */
+ lowered = nir_ior(b,
+ nir_iand(b, nir_ushr(b, lowered, c1), c),
+ nir_ishl(b, nir_iand(b, lowered, c), c1));
+
+ /* Swap consecutive pairs. */
+ lowered = nir_ior(b,
+ nir_iand(b, nir_ushr(b, lowered, c2), c),
+ nir_ishl(b, nir_iand(b, lowered, c), c2));
+
+ /* Swap nibbles. */
+ lowered = nir_ior(b,
+ nir_iand(b, nir_ushr(b, lowered, c4), c0f0f0f0f),
+ nir_ishl(b, nir_iand(b, lowered, c0f0f0f0f), c4));
+
+ /* Swap bytes. */
+ lowered = nir_ior(b,
+ nir_iand(b, nir_ushr(b, lowered, c8), c00ff00ff),
+ nir_ishl(b, nir_iand(b, lowered, c00ff00ff), c8));
+
+ lowered = nir_ior(b,
+ nir_ushr(b, lowered, c16),
+ nir_ishl(b, lowered, c16));
+ }
+ break;
+
case nir_op_imul_high:
case nir_op_umul_high:
if (b->shader->options->lower_mul_high) {
@@ -136,7 +180,8 @@ nir_lower_alu(nir_shader *shader)
{
bool progress = false;
- if (!shader->options->lower_mul_high)
+ if (!shader->options->lower_bitfield_reverse &&
+ !shader->options->lower_mul_high)
return false;
nir_foreach_function(function, shader) {
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Mesa (master): v3d: Be more explicit about include directory from our generated code.
Module: Mesa Branch: master Commit: 2b1b2cbf619f9b3d578dabb0956bd5a248b6a89c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b1b2cbf619f9b3d578dabb0956bd5a248b6a89c Author: Eric Anholt Date: Tue Jun 5 08:50:55 2018 -0700 v3d: Be more explicit about include directory from our generated code. You'd need src/broadcom/cle/ in the -I previously, for srcdir != builddir. nir was fine at that, but automake didn't have it. Bugzilla: https://github.com/anholt/mesa/issues/104 --- src/broadcom/cle/gen_pack_header.py | 2 +- src/gallium/drivers/v3d/Makefile.am | 2 ++ src/gallium/drivers/vc4/Makefile.am | 3 ++- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/broadcom/cle/gen_pack_header.py b/src/broadcom/cle/gen_pack_header.py index e5762762b2..310e0a7c7a 100644 --- a/src/broadcom/cle/gen_pack_header.py +++ b/src/broadcom/cle/gen_pack_header.py @@ -43,7 +43,7 @@ pack_header = """%(license)s #ifndef %(guard)s #define %(guard)s -#include "v3d_packet_helpers.h" +#include "cle/v3d_packet_helpers.h" """ diff --git a/src/gallium/drivers/v3d/Makefile.am b/src/gallium/drivers/v3d/Makefile.am index ff0334a239..5b4ed5df2b 100644 --- a/src/gallium/drivers/v3d/Makefile.am +++ b/src/gallium/drivers/v3d/Makefile.am @@ -25,7 +25,9 @@ include $(top_srcdir)/src/gallium/Automake.inc AM_CFLAGS = \ -I$(top_builddir)/src/compiler/nir \ -I$(top_srcdir)/include/drm-uapi \ + -I$(top_srcdir)/src/broadcom \ -I$(top_builddir)/src/broadcom \ + -I$(top_builddir)/src \ $(LIBDRM_CFLAGS) \ $(V3D_SIMULATOR_CFLAGS) \ $(GALLIUM_DRIVER_CFLAGS) \ diff --git a/src/gallium/drivers/vc4/Makefile.am b/src/gallium/drivers/vc4/Makefile.am index d65bf20e26..4c7dd843da 100644 --- a/src/gallium/drivers/vc4/Makefile.am +++ b/src/gallium/drivers/vc4/Makefile.am @@ -30,7 +30,8 @@ AM_CFLAGS = \ -I$(top_builddir)/src/compiler/nir \ -I$(top_srcdir)/include/drm-uapi \ -I$(top_builddir)/src \ - -I$(top_srcdir)/src/broadcom/cle \ + -I$(top_srcdir)/src/broadcom \ + -I$(top_builddir)/src/broadcom \ $(LIBDRM_CFLAGS) \ $(GALLIUM_DRIVER_CFLAGS) \ $(SIM_CFLAGS) \ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): v3d: Fix automake linking error.
Module: Mesa Branch: master Commit: d511bba2f92566c512c86c5f51bd756834cbd444 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d511bba2f92566c512c86c5f51bd756834cbd444 Author: Vinson Lee Date: Tue May 22 00:17:45 2018 + v3d: Fix automake linking error. CXXLDgallium_dri.la ../../../../src/broadcom/.libs/libbroadcom.a(clif_dump.o): In function `clif_dump_packet': src/broadcom/clif/clif_dump.c:87: undefined reference to `v3d33_clif_dump_packet' src/broadcom/clif/clif_dump.c:85: undefined reference to `v3d41_clif_dump_packet' ../../../../src/broadcom/.libs/libbroadcom.a(clif_dump.o): In function `clif_process_worklist': src/broadcom/clif/clif_dump.c:140: undefined reference to `v3d41_clif_dump_gl_shader_state_record' src/broadcom/clif/clif_dump.c:144: undefined reference to `v3d33_clif_dump_gl_shader_state_record' Signed-off-by: Vinson Lee Reviewed-by: Eric Anholt --- src/gallium/drivers/v3d/Automake.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/v3d/Automake.inc b/src/gallium/drivers/v3d/Automake.inc index 7cf8ae7cd8..91ae826b30 100644 --- a/src/gallium/drivers/v3d/Automake.inc +++ b/src/gallium/drivers/v3d/Automake.inc @@ -5,7 +5,9 @@ TARGET_CPPFLAGS += -DGALLIUM_V3D TARGET_LIB_DEPS += \ $(top_builddir)/src/gallium/winsys/v3d/drm/libv3ddrm.la \ $(top_builddir)/src/gallium/drivers/v3d/libv3d.la \ - $(top_builddir)/src/broadcom/libbroadcom.la + $(top_builddir)/src/broadcom/libbroadcom.la \ + $(top_builddir)/src/broadcom/libbroadcom_v33.la \ + $(top_builddir)/src/broadcom/libbroadcom_v41.la if !HAVE_GALLIUM_VC4 TARGET_LIB_DEPS += $(top_builddir)/src/broadcom/cle/libbroadcom_cle.la ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): v3d: Include v3d_drm.h path.
Module: Mesa
Branch: master
Commit: 85f61197df49c3384f9f6c8cf0e642249e42e8fd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=85f61197df49c3384f9f6c8cf0e642249e42e8fd
Author: Vinson Lee <v...@freedesktop.org>
Date: Thu May 17 22:39:50 2018 +
v3d: Include v3d_drm.h path.
Fix build error.
CC v3d_blit.lo
In file included from v3d_blit.c:27:0:
v3d_context.h:39:10: fatal error: v3d_drm.h: No such file or directory
#include "v3d_drm.h"
^~~
Fixes: 8a793d42f1cc ("v3d: Switch the vc5 driver to using the finalized V3D
UABI.")
Signed-off-by: Vinson Lee <v...@freedesktop.org>
Reviewed-by: Eric Anholt <e...@anholt.net>
---
src/gallium/drivers/v3d/Makefile.am | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/v3d/Makefile.am
b/src/gallium/drivers/v3d/Makefile.am
index 2b4c364c24..ff0334a239 100644
--- a/src/gallium/drivers/v3d/Makefile.am
+++ b/src/gallium/drivers/v3d/Makefile.am
@@ -24,6 +24,7 @@ include $(top_srcdir)/src/gallium/Automake.inc
AM_CFLAGS = \
-I$(top_builddir)/src/compiler/nir \
+ -I$(top_srcdir)/include/drm-uapi \
-I$(top_builddir)/src/broadcom \
$(LIBDRM_CFLAGS) \
$(V3D_SIMULATOR_CFLAGS) \
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Mesa (master): broadcom/vc4: Drop libdrm_vc4 requirement
Module: Mesa Branch: master Commit: 1ec01a911b7b4dc63c47fb16288b6d9962aeb60f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1ec01a911b7b4dc63c47fb16288b6d9962aeb60f Author: Stefan Schake <stsch...@gmail.com> Date: Wed Apr 25 00:00:55 2018 +0200 broadcom/vc4: Drop libdrm_vc4 requirement This was missed in the move back to the local uapi copy. libdrm_vc4 only seems to consist of headers that also exist in the Mesa tree. Signed-off-by: Stefan Schake <stsch...@gmail.com> Reviewed-by: Eric Anholt <e...@anholt.net> --- configure.ac | 1 - 1 file changed, 1 deletion(-) diff --git a/configure.ac b/configure.ac index 30980151ee..681696e789 100644 --- a/configure.ac +++ b/configure.ac @@ -2727,7 +2727,6 @@ if test -n "$with_gallium_drivers"; then ;; xvc4) HAVE_GALLIUM_VC4=yes -require_libdrm "vc4" PKG_CHECK_MODULES([SIMPENROSE], [simpenrose], [USE_VC4_SIMULATOR=yes; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): broadcom/vc4: Native fence fd support
Module: Mesa
Branch: master
Commit: b0acc3a5628c6c6dd669cbb7cff2d974b175605e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0acc3a5628c6c6dd669cbb7cff2d974b175605e
Author: Stefan Schake <stsch...@gmail.com>
Date: Wed Apr 25 00:01:00 2018 +0200
broadcom/vc4: Native fence fd support
With the syncobj support in place, lets use it to implement the
EGL_ANDROID_native_fence_sync extension. This mostly follows previous
implementations in freedreno and etnaviv.
v2: Drop the flags (Eric)
Handle in_fence_fd already in job_submit (Eric)
Drop extra vc4_fence_context_init (Eric)
Dup fds with CLOEXEC (Eric)
Mention exact extension name (Eric)
Signed-off-by: Stefan Schake <stsch...@gmail.com>
Reviewed-by: Eric Anholt <e...@anholt.net>
---
src/gallium/drivers/vc4/vc4_context.c | 21 ++-
src/gallium/drivers/vc4/vc4_context.h | 5 +++
src/gallium/drivers/vc4/vc4_fence.c | 70 +--
src/gallium/drivers/vc4/vc4_job.c | 12 +-
src/gallium/drivers/vc4/vc4_screen.c | 6 ++-
src/gallium/drivers/vc4/vc4_screen.h | 4 +-
6 files changed, 107 insertions(+), 11 deletions(-)
diff --git a/src/gallium/drivers/vc4/vc4_context.c
b/src/gallium/drivers/vc4/vc4_context.c
index 0deb3ef85e..9ff39c2655 100644
--- a/src/gallium/drivers/vc4/vc4_context.c
+++ b/src/gallium/drivers/vc4/vc4_context.c
@@ -59,8 +59,17 @@ vc4_pipe_flush(struct pipe_context *pctx, struct
pipe_fence_handle **fence,
if (fence) {
struct pipe_screen *screen = pctx->screen;
+int fd = -1;
+
+if (flags & PIPE_FLUSH_FENCE_FD) {
+/* The vc4_fence takes ownership of the returned fd. */
+drmSyncobjExportSyncFile(vc4->fd, vc4->job_syncobj,
+ );
+}
+
struct vc4_fence *f = vc4_fence_create(vc4->screen,
- vc4->last_emit_seqno);
+ vc4->last_emit_seqno,
+ fd);
screen->fence_reference(screen, fence, NULL);
*fence = (struct pipe_fence_handle *)f;
}
@@ -124,8 +133,12 @@ vc4_context_destroy(struct pipe_context *pctx)
vc4_program_fini(pctx);
-if (vc4->screen->has_syncobj)
+if (vc4->screen->has_syncobj) {
drmSyncobjDestroy(vc4->fd, vc4->job_syncobj);
+drmSyncobjDestroy(vc4->fd, vc4->in_syncobj);
+}
+if (vc4->in_fence_fd >= 0)
+close(vc4->in_fence_fd);
ralloc_free(vc4);
}
@@ -167,6 +180,10 @@ vc4_context_create(struct pipe_screen *pscreen, void
*priv, unsigned flags)
if (err)
goto fail;
+err = vc4_fence_context_init(vc4);
+if (err)
+goto fail;
+
slab_create_child(>transfer_pool, >transfer_pool);
vc4->uploader = u_upload_create_default(>base);
diff --git a/src/gallium/drivers/vc4/vc4_context.h
b/src/gallium/drivers/vc4/vc4_context.h
index d094957bb5..ce8bcffac0 100644
--- a/src/gallium/drivers/vc4/vc4_context.h
+++ b/src/gallium/drivers/vc4/vc4_context.h
@@ -411,6 +411,10 @@ struct vc4_context {
/** Handle of syncobj containing the last submitted job fence. */
uint32_t job_syncobj;
+
+int in_fence_fd;
+/** Handle of the syncobj that holds in_fence_fd for submission. */
+uint32_t in_syncobj;
};
struct vc4_rasterizer_state {
@@ -506,6 +510,7 @@ void vc4_write_uniforms(struct vc4_context *vc4,
void vc4_flush(struct pipe_context *pctx);
int vc4_job_init(struct vc4_context *vc4);
+int vc4_fence_context_init(struct vc4_context *vc4);
struct vc4_job *vc4_get_job(struct vc4_context *vc4,
struct pipe_surface *cbuf,
struct pipe_surface *zsbuf);
diff --git a/src/gallium/drivers/vc4/vc4_fence.c
b/src/gallium/drivers/vc4/vc4_fence.c
index f61e7c6a5e..7071425595 100644
--- a/src/gallium/drivers/vc4/vc4_fence.c
+++ b/src/gallium/drivers/vc4/vc4_fence.c
@@ -34,26 +34,39 @@
* fired off as our fence marker.
*/
+#include
+#include
+
#include "util/u_inlines.h"
#include "vc4_screen.h"
+#include "vc4_context.h"
#include "vc4_bufmgr.h"
struct vc4_fence {
struct pipe_reference reference;
uint64_t seqno;
+int fd;
};
+static inline struct vc4_fence *
+vc4_fence(struct pipe_fence_handle *pfence)
+{
+return (struct vc4_fence *)pfence;
+}
+
static void
vc4_fence_reference(struct pipe_screen *pscreen,
struct pipe_fence_handle **pp,
struct pipe_fence_handle *pf)
{
struct vc4_fence **p = (struct vc4_fence **)pp;
-
Mesa (master): drm-uapi: Update vc4 header with syncobj submit support
Module: Mesa
Branch: master
Commit: 580d1f4c607bc6cd5bf24f9d303a502d6d9dcaec
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=580d1f4c607bc6cd5bf24f9d303a502d6d9dcaec
Author: Stefan Schake <stsch...@gmail.com>
Date: Wed Apr 25 00:00:56 2018 +0200
drm-uapi: Update vc4 header with syncobj submit support
v2: Synchronized with kernel v2
v3: Update for the finalized kernel ABI (pad2 field)
Signed-off-by: Stefan Schake <stsch...@gmail.com>
Reviewed-by: Eric Anholt <e...@anholt.net>
---
include/drm-uapi/vc4_drm.h | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/include/drm-uapi/vc4_drm.h b/include/drm-uapi/vc4_drm.h
index 4117117b42..31f50de39a 100644
--- a/include/drm-uapi/vc4_drm.h
+++ b/include/drm-uapi/vc4_drm.h
@@ -183,10 +183,17 @@ struct drm_vc4_submit_cl {
/* ID of the perfmon to attach to this job. 0 means no perfmon. */
__u32 perfmonid;
- /* Unused field to align this struct on 64 bits. Must be set to 0.
-* If one ever needs to add an u32 field to this struct, this field
-* can be used.
+ /* Syncobj handle to wait on. If set, processing of this render job
+* will not start until the syncobj is signaled. 0 means ignore.
*/
+ __u32 in_sync;
+
+ /* Syncobj handle to export fence to. If set, the fence in the syncobj
+* will be replaced with a fence that signals upon completion of this
+* render job. 0 means ignore.
+*/
+ __u32 out_sync;
+
__u32 pad2;
};
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Mesa (master): broadcom/vc4: Store job fence in syncobj
Module: Mesa
Branch: master
Commit: 44036c354d800dda08d3688b042130039f3d592a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=44036c354d800dda08d3688b042130039f3d592a
Author: Stefan Schake <stsch...@gmail.com>
Date: Wed Apr 25 00:00:59 2018 +0200
broadcom/vc4: Store job fence in syncobj
This gives us access to the fence created for the render job.
v2: Drop flag (Eric)
Signed-off-by: Stefan Schake <stsch...@gmail.com>
Reviewed-by: Eric Anholt <e...@anholt.net>
---
src/gallium/drivers/vc4/vc4_context.c | 10 --
src/gallium/drivers/vc4/vc4_context.h | 5 -
src/gallium/drivers/vc4/vc4_job.c | 24 +++-
3 files changed, 35 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/vc4/vc4_context.c
b/src/gallium/drivers/vc4/vc4_context.c
index c1e041d1ef..0deb3ef85e 100644
--- a/src/gallium/drivers/vc4/vc4_context.c
+++ b/src/gallium/drivers/vc4/vc4_context.c
@@ -124,6 +124,9 @@ vc4_context_destroy(struct pipe_context *pctx)
vc4_program_fini(pctx);
+if (vc4->screen->has_syncobj)
+drmSyncobjDestroy(vc4->fd, vc4->job_syncobj);
+
ralloc_free(vc4);
}
@@ -132,6 +135,7 @@ vc4_context_create(struct pipe_screen *pscreen, void *priv,
unsigned flags)
{
struct vc4_screen *screen = vc4_screen(pscreen);
struct vc4_context *vc4;
+int err;
/* Prevent dumping of the shaders built during context setup. */
uint32_t saved_shaderdb_flag = vc4_debug & VC4_DEBUG_SHADERDB;
@@ -157,10 +161,12 @@ vc4_context_create(struct pipe_screen *pscreen, void
*priv, unsigned flags)
vc4_query_init(pctx);
vc4_resource_context_init(pctx);
-vc4_job_init(vc4);
-
vc4->fd = screen->fd;
+err = vc4_job_init(vc4);
+if (err)
+goto fail;
+
slab_create_child(>transfer_pool, >transfer_pool);
vc4->uploader = u_upload_create_default(>base);
diff --git a/src/gallium/drivers/vc4/vc4_context.h
b/src/gallium/drivers/vc4/vc4_context.h
index 16bebeec40..d094957bb5 100644
--- a/src/gallium/drivers/vc4/vc4_context.h
+++ b/src/gallium/drivers/vc4/vc4_context.h
@@ -408,6 +408,9 @@ struct vc4_context {
struct vc4_hwperfmon *perfmon;
/** @} */
+
+/** Handle of syncobj containing the last submitted job fence. */
+uint32_t job_syncobj;
};
struct vc4_rasterizer_state {
@@ -502,7 +505,7 @@ void vc4_write_uniforms(struct vc4_context *vc4,
struct vc4_texture_stateobj *texstate);
void vc4_flush(struct pipe_context *pctx);
-void vc4_job_init(struct vc4_context *vc4);
+int vc4_job_init(struct vc4_context *vc4);
struct vc4_job *vc4_get_job(struct vc4_context *vc4,
struct pipe_surface *cbuf,
struct pipe_surface *zsbuf);
diff --git a/src/gallium/drivers/vc4/vc4_job.c
b/src/gallium/drivers/vc4/vc4_job.c
index 41c274ca1b..3b0ba8b69c 100644
--- a/src/gallium/drivers/vc4/vc4_job.c
+++ b/src/gallium/drivers/vc4/vc4_job.c
@@ -477,6 +477,9 @@ vc4_job_submit(struct vc4_context *vc4, struct vc4_job *job)
}
submit.flags |= job->flags;
+if (vc4->screen->has_syncobj)
+submit.out_sync = vc4->job_syncobj;
+
if (!(vc4_debug & VC4_DEBUG_NORAST)) {
int ret;
@@ -530,7 +533,7 @@ vc4_job_hash(const void *key)
return _mesa_hash_data(key, sizeof(struct vc4_job_key));
}
-void
+int
vc4_job_init(struct vc4_context *vc4)
{
vc4->jobs = _mesa_hash_table_create(vc4,
@@ -539,5 +542,24 @@ vc4_job_init(struct vc4_context *vc4)
vc4->write_jobs = _mesa_hash_table_create(vc4,
_mesa_hash_pointer,
_mesa_key_pointer_equal);
+
+if (vc4->screen->has_syncobj) {
+/* Create the syncobj as signaled since with no job executed
+ * there is nothing to wait on.
+ */
+int ret = drmSyncobjCreate(vc4->fd,
+ DRM_SYNCOBJ_CREATE_SIGNALED,
+ >job_syncobj);
+if (ret) {
+/* If the screen indicated syncobj support, we should
+ * be able to create a signaled syncobj.
+ * At this point it is too late to pretend the screen
+ * has no syncobj support.
+ */
+return ret;
+}
+}
+
+return 0;
}
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Mesa (master): broadcom/vc4: Bump libdrm requirement
Module: Mesa Branch: master Commit: 4fc0ebdff55419965919e4d6bf3c7f7f2759f7aa URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4fc0ebdff55419965919e4d6bf3c7f7f2759f7aa Author: Stefan Schake <stsch...@gmail.com> Date: Wed Apr 25 00:00:57 2018 +0200 broadcom/vc4: Bump libdrm requirement Require a version of libdrm with syncobj support. v2: Don't require a libdrm_vc4, just bump core libdrm if vc4 enabled (by anholt) Signed-off-by: Stefan Schake <stsch...@gmail.com> Reviewed-by: Eric Anholt <e...@anholt.net> --- configure.ac | 2 ++ meson.build | 6 ++ 2 files changed, 8 insertions(+) diff --git a/configure.ac b/configure.ac index 681696e789..401025bf2e 100644 --- a/configure.ac +++ b/configure.ac @@ -80,6 +80,7 @@ LIBDRM_NVVIEUX_REQUIRED=2.4.66 LIBDRM_NOUVEAU_REQUIRED=2.4.66 LIBDRM_FREEDRENO_REQUIRED=2.4.92 LIBDRM_ETNAVIV_REQUIRED=2.4.89 +LIBDRM_VC4_REQUIRED=2.4.89 dnl Versions for external dependencies DRI2PROTO_REQUIRED=2.8 @@ -2727,6 +2728,7 @@ if test -n "$with_gallium_drivers"; then ;; xvc4) HAVE_GALLIUM_VC4=yes +PKG_CHECK_MODULES([VC4], [libdrm >= $LIBDRM_VC4_REQUIRED]) PKG_CHECK_MODULES([SIMPENROSE], [simpenrose], [USE_VC4_SIMULATOR=yes; diff --git a/meson.build b/meson.build index b8ebda9cdc..0f88ddfe8e 100644 --- a/meson.build +++ b/meson.build @@ -1055,6 +1055,12 @@ _libdrm_checks = [ ['freedreno', with_gallium_freedreno], ] +# VC4 only needs core libdrm support of this version, not a libdrm_vc4 +# library. +if with_gallium_vc4 + _drm_ver = '2.4.89' +endif + # Loop over the enables versions and get the highest libdrm requirement for all # active drivers. foreach d : _libdrm_checks ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): broadcom/vc4: Detect syncobj support
Module: Mesa
Branch: master
Commit: 9ed05e2520f77a11f73d21bccfe149b2b800082c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ed05e2520f77a11f73d21bccfe149b2b800082c
Author: Stefan Schake <stsch...@gmail.com>
Date: Wed Apr 25 00:00:58 2018 +0200
broadcom/vc4: Detect syncobj support
We need to know if the kernel supports syncobj submission since otherwise
all the DRM syncobj calls fail.
v2: Use drmGetCap to detect syncobj support (Eric)
Signed-off-by: Stefan Schake <stsch...@gmail.com>
Reviewed-by: Eric Anholt <e...@anholt.net>
---
src/gallium/drivers/vc4/vc4_screen.c | 6 ++
src/gallium/drivers/vc4/vc4_screen.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/src/gallium/drivers/vc4/vc4_screen.c
b/src/gallium/drivers/vc4/vc4_screen.c
index 81c8049325..5476b8cf10 100644
--- a/src/gallium/drivers/vc4/vc4_screen.c
+++ b/src/gallium/drivers/vc4/vc4_screen.c
@@ -659,7 +659,9 @@ struct pipe_screen *
vc4_screen_create(int fd, struct renderonly *ro)
{
struct vc4_screen *screen = rzalloc(NULL, struct vc4_screen);
+uint64_t syncobj_cap = 0;
struct pipe_screen *pscreen;
+int err;
pscreen = >base;
@@ -695,6 +697,10 @@ vc4_screen_create(int fd, struct renderonly *ro)
screen->has_perfmon_ioctl =
vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_PERFMON);
+err = drmGetCap(fd, DRM_CAP_SYNCOBJ, _cap);
+if (err == 0 && syncobj_cap)
+screen->has_syncobj = true;
+
if (!vc4_get_chip_info(screen))
goto fail;
diff --git a/src/gallium/drivers/vc4/vc4_screen.h
b/src/gallium/drivers/vc4/vc4_screen.h
index 0b884423ba..438e90a1a2 100644
--- a/src/gallium/drivers/vc4/vc4_screen.h
+++ b/src/gallium/drivers/vc4/vc4_screen.h
@@ -98,6 +98,7 @@ struct vc4_screen {
bool has_madvise;
bool has_tiling_ioctl;
bool has_perfmon_ioctl;
+bool has_syncobj;
struct vc4_simulator_file *sim_file;
};
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Mesa (master): v3d: Add support for glSampleMask / glSampleCoverage.
Module: Mesa
Branch: master
Commit: 97894b1267923dee25ea5263e547ac8822ef7095
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=97894b1267923dee25ea5263e547ac8822ef7095
Author: Eric Anholt <e...@anholt.net>
Date: Tue May 8 14:28:33 2018 -0700
v3d: Add support for glSampleMask / glSampleCoverage.
---
src/broadcom/cle/v3d_packet_v41.xml| 5 +
src/broadcom/cle/v3d_packet_v42.xml| 5 +
src/gallium/drivers/v3d/v3d_context.h | 2 +-
src/gallium/drivers/v3d/v3d_program.c | 2 +-
src/gallium/drivers/v3d/v3d_uniforms.c | 2 +-
src/gallium/drivers/v3d/v3dx_emit.c| 23 ++-
src/gallium/drivers/v3d/v3dx_state.c | 2 +-
7 files changed, 36 insertions(+), 5 deletions(-)
diff --git a/src/broadcom/cle/v3d_packet_v41.xml
b/src/broadcom/cle/v3d_packet_v41.xml
index 1fb5d5d284..c516561407 100644
--- a/src/broadcom/cle/v3d_packet_v41.xml
+++ b/src/broadcom/cle/v3d_packet_v41.xml
@@ -475,6 +475,11 @@
+
+
+
+
+
diff --git a/src/broadcom/cle/v3d_packet_v42.xml
b/src/broadcom/cle/v3d_packet_v42.xml
index a562d662ff..fb4425968c 100644
--- a/src/broadcom/cle/v3d_packet_v42.xml
+++ b/src/broadcom/cle/v3d_packet_v42.xml
@@ -476,6 +476,11 @@
+
+
+
+
+
diff --git a/src/gallium/drivers/v3d/v3d_context.h
b/src/gallium/drivers/v3d/v3d_context.h
index d110ed5022..47945f9649 100644
--- a/src/gallium/drivers/v3d/v3d_context.h
+++ b/src/gallium/drivers/v3d/v3d_context.h
@@ -61,7 +61,7 @@ void v3d_job_add_bo(struct v3d_job *job, struct v3d_bo *bo);
#define VC5_DIRTY_BLEND_COLOR (1 << 7)
#define VC5_DIRTY_STENCIL_REF (1 << 8)
-#define VC5_DIRTY_SAMPLE_MASK (1 << 9)
+#define VC5_DIRTY_SAMPLE_STATE (1 << 9)
#define VC5_DIRTY_FRAMEBUFFER (1 << 10)
#define VC5_DIRTY_STIPPLE (1 << 11)
#define VC5_DIRTY_VIEWPORT (1 << 12)
diff --git a/src/gallium/drivers/v3d/v3d_program.c
b/src/gallium/drivers/v3d/v3d_program.c
index 63e6fda547..036f7c6e67 100644
--- a/src/gallium/drivers/v3d/v3d_program.c
+++ b/src/gallium/drivers/v3d/v3d_program.c
@@ -399,7 +399,7 @@ v3d_update_compiled_fs(struct v3d_context *v3d, uint8_t
prim_mode)
VC5_DIRTY_FRAMEBUFFER |
VC5_DIRTY_ZSA |
VC5_DIRTY_RASTERIZER |
-VC5_DIRTY_SAMPLE_MASK |
+VC5_DIRTY_SAMPLE_STATE |
VC5_DIRTY_FRAGTEX |
VC5_DIRTY_UNCOMPILED_FS))) {
return;
diff --git a/src/gallium/drivers/v3d/v3d_uniforms.c
b/src/gallium/drivers/v3d/v3d_uniforms.c
index 9dd128ab41..ad46c69121 100644
--- a/src/gallium/drivers/v3d/v3d_uniforms.c
+++ b/src/gallium/drivers/v3d/v3d_uniforms.c
@@ -475,7 +475,7 @@ v3d_set_shader_uniform_dirty_flags(struct
v3d_compiled_shader *shader)
break;
case QUNIFORM_SAMPLE_MASK:
-dirty |= VC5_DIRTY_SAMPLE_MASK;
+dirty |= VC5_DIRTY_SAMPLE_STATE;
break;
default:
diff --git a/src/gallium/drivers/v3d/v3dx_emit.c
b/src/gallium/drivers/v3d/v3dx_emit.c
index 8a65478a16..161ce51b2f 100644
--- a/src/gallium/drivers/v3d/v3dx_emit.c
+++ b/src/gallium/drivers/v3d/v3dx_emit.c
@@ -387,8 +387,17 @@ v3dX(emit_state)(struct pipe_context *pctx)
config.enable_depth_offset =
v3d->rasterizer->base.offset_tri;
+/* V3D follows GL behavior where the sample mask only
+ * applies when MSAA is enabled. Gallium has sample
+ * mask apply anyway, and the MSAA blit shaders will
+ * set sample mask without explicitly setting
+ * rasterizer oversample. Just force it on here,
+ * since the blit shaders are the only way to have
+ * !multisample && samplemask != 0xf.
+ */
config.rasterizer_oversample_mode =
-v3d->rasterizer->base.multisample;
+v3d->rasterizer->base.multisample ||
+v3d->sample_mask != 0xf;
config.direct3d_provoking_vertex =
v3d->rasterizer->base.flatshade_first;
@@ -719,4 +728,16 @@ v3dX(emit_state)(struct pipe_context *pctx)
}
}
}
+
+#if V3D_VERSION >= 40
+if (v3d->dirty & VC5_DIRTY_SAMPLE_STATE) {
+cl_emit(>bcl, SAMPLE_STATE, state) {
+/* Note: SampleCoverage was handled at the
+ * state_tracker level by converting to sa
Mesa (master): v3d: Enable NaN propagation in the VS and CS as well.
Module: Mesa Branch: master Commit: 9bbc3f8cf1f116aa17ebcd399c0d3a8fb07b5266 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9bbc3f8cf1f116aa17ebcd399c0d3a8fb07b5266 Author: Eric Anholt <e...@anholt.net> Date: Tue May 8 13:22:57 2018 -0700 v3d: Enable NaN propagation in the VS and CS as well. Fixes piglit vs-isnan-*.shader_test at the expense of gl-1.0-spot-light. --- src/broadcom/cle/v3d_packet_v33.xml | 4 +++- src/broadcom/cle/v3d_packet_v41.xml | 4 +++- src/broadcom/cle/v3d_packet_v42.xml | 4 +++- src/gallium/drivers/v3d/v3dx_draw.c | 4 +++- 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/src/broadcom/cle/v3d_packet_v33.xml b/src/broadcom/cle/v3d_packet_v33.xml index aac9fbfd28..22d43cc802 100644 --- a/src/broadcom/cle/v3d_packet_v33.xml +++ b/src/broadcom/cle/v3d_packet_v33.xml @@ -702,15 +702,17 @@ - + + + diff --git a/src/broadcom/cle/v3d_packet_v41.xml b/src/broadcom/cle/v3d_packet_v41.xml index 5f6d643195..1fb5d5d284 100644 --- a/src/broadcom/cle/v3d_packet_v41.xml +++ b/src/broadcom/cle/v3d_packet_v41.xml @@ -781,17 +781,19 @@ - + + + diff --git a/src/broadcom/cle/v3d_packet_v42.xml b/src/broadcom/cle/v3d_packet_v42.xml index f180e5eec5..a562d662ff 100644 --- a/src/broadcom/cle/v3d_packet_v42.xml +++ b/src/broadcom/cle/v3d_packet_v42.xml @@ -782,17 +782,19 @@ - + + + diff --git a/src/gallium/drivers/v3d/v3dx_draw.c b/src/gallium/drivers/v3d/v3dx_draw.c index 28b35165c7..4d872b30ec 100644 --- a/src/gallium/drivers/v3d/v3dx_draw.c +++ b/src/gallium/drivers/v3d/v3dx_draw.c @@ -183,7 +183,9 @@ v3d_emit_gl_shader_state(struct v3d_context *v3d, shader.number_of_varyings_in_fragment_shader = v3d->prog.fs->prog_data.base->num_inputs; -shader.propagate_nans = true; +shader.coordinate_shader_propagate_nans = true; +shader.vertex_shader_propagate_nans = true; +shader.fragment_shader_propagate_nans = true; shader.coordinate_shader_code_address = cl_address(v3d->prog.cs->bo, 0); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): v3d: Fix wiring filters to NEAREST for 32-bit texture returns.
Module: Mesa
Branch: master
Commit: b2e7c32703fde3944b227927a0f8094da521ae39
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b2e7c32703fde3944b227927a0f8094da521ae39
Author: Eric Anholt <e...@anholt.net>
Date: Tue May 1 17:22:09 2018 -0700
v3d: Fix wiring filters to NEAREST for 32-bit texture returns.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104626
---
src/gallium/drivers/v3d/v3dx_emit.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/v3d/v3dx_emit.c
b/src/gallium/drivers/v3d/v3dx_emit.c
index a52ddfe6b1..8a65478a16 100644
--- a/src/gallium/drivers/v3d/v3dx_emit.c
+++ b/src/gallium/drivers/v3d/v3dx_emit.c
@@ -209,7 +209,7 @@ emit_one_texture(struct v3d_context *v3d, struct
v3d_texture_stateobj *stage_tex
if (return_size == 32) {
min_mip_filter = PIPE_TEX_MIPFILTER_NEAREST;
-mag_img_filter = PIPE_TEX_FILTER_NEAREST;
+min_img_filter = PIPE_TEX_FILTER_NEAREST;
mag_img_filter = PIPE_TEX_FILTER_NEAREST;
}
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Mesa (master): v3d: Switch the vc5 driver to using the finalized V3D UABI.
Module: Mesa
Branch: master
Commit: 8a793d42f1ccef2c87053a1d9a130b49cfb2b84f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a793d42f1ccef2c87053a1d9a130b49cfb2b84f
Author: Eric Anholt <e...@anholt.net>
Date: Tue May 1 12:00:56 2018 -0700
v3d: Switch the vc5 driver to using the finalized V3D UABI.
In the process of merging to the kernel, I renamed the driver to the
general product line's name (since we have both vc5 and vc6 supported
already). Since the ABI is finalized, move the header to include/drm-uapi.
---
Makefile.am| 1 +
.../vc5/vc5_drm.h => include/drm-uapi/v3d_drm.h| 75 +++---
src/gallium/drivers/vc5/Makefile.sources | 1 -
src/gallium/drivers/vc5/v3dx_context.h | 4 +-
src/gallium/drivers/vc5/v3dx_simulator.c | 18 +++---
src/gallium/drivers/vc5/vc5_bufmgr.c | 16 ++---
src/gallium/drivers/vc5/vc5_context.h | 8 +--
src/gallium/drivers/vc5/vc5_job.c | 2 +-
src/gallium/drivers/vc5/vc5_screen.c | 13 ++--
src/gallium/drivers/vc5/vc5_simulator.c| 20 +++---
10 files changed, 79 insertions(+), 79 deletions(-)
diff --git a/Makefile.am b/Makefile.am
index 86d7e7f910..9e27db046e 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -77,6 +77,7 @@ noinst_HEADERS = \
include/drm-uapi/drm_mode.h \
include/drm-uapi/i915_drm.h \
include/drm-uapi/tegra_drm.h \
+ include/drm-uapi/v3d_drm.h \
include/drm-uapi/vc4_drm.h \
include/D3D9 \
include/GL/wglext.h \
diff --git a/src/gallium/drivers/vc5/vc5_drm.h b/include/drm-uapi/v3d_drm.h
similarity index 68%
rename from src/gallium/drivers/vc5/vc5_drm.h
rename to include/drm-uapi/v3d_drm.h
index 184863d206..7b66277836 100644
--- a/src/gallium/drivers/vc5/vc5_drm.h
+++ b/include/drm-uapi/v3d_drm.h
@@ -1,5 +1,5 @@
/*
- * Copyright © 2014-2017 Broadcom
+ * Copyright © 2014-2018 Broadcom
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -21,8 +21,8 @@
* IN THE SOFTWARE.
*/
-#ifndef _VC5_DRM_H_
-#define _VC5_DRM_H_
+#ifndef _V3D_DRM_H_
+#define _V3D_DRM_H_
#include "drm.h"
@@ -30,28 +30,28 @@
extern "C" {
#endif
-#define DRM_VC5_SUBMIT_CL 0x00
-#define DRM_VC5_WAIT_BO 0x01
-#define DRM_VC5_CREATE_BO 0x02
-#define DRM_VC5_MMAP_BO 0x03
-#define DRM_VC5_GET_PARAM 0x04
-#define DRM_VC5_GET_BO_OFFSET 0x05
+#define DRM_V3D_SUBMIT_CL 0x00
+#define DRM_V3D_WAIT_BO 0x01
+#define DRM_V3D_CREATE_BO 0x02
+#define DRM_V3D_MMAP_BO 0x03
+#define DRM_V3D_GET_PARAM 0x04
+#define DRM_V3D_GET_BO_OFFSET 0x05
-#define DRM_IOCTL_VC5_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE +
DRM_VC5_SUBMIT_CL, struct drm_vc5_submit_cl)
-#define DRM_IOCTL_VC5_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE +
DRM_VC5_WAIT_BO, struct drm_vc5_wait_bo)
-#define DRM_IOCTL_VC5_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE +
DRM_VC5_CREATE_BO, struct drm_vc5_create_bo)
-#define DRM_IOCTL_VC5_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE +
DRM_VC5_MMAP_BO, struct drm_vc5_mmap_bo)
-#define DRM_IOCTL_VC5_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE +
DRM_VC5_GET_PARAM, struct drm_vc5_get_param)
-#define DRM_IOCTL_VC5_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE +
DRM_VC5_GET_BO_OFFSET, struct drm_vc5_get_bo_offset)
+#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE +
DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
+#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE +
DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
+#define DRM_IOCTL_V3D_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE +
DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
+#define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE +
DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
+#define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE +
DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
+#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE +
DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
/**
- * struct drm_vc5_submit_cl - ioctl argument for submitting commands to the 3D
+ * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
* engine.
*
* This asks the kernel to have the GPU execute an optional binner
* command list, and a render command list.
*/
-struct drm_vc5_submit_cl {
+struct drm_v3d_submit_cl {
/* Pointer to the binner command list.
*
* This is the first set of commands executed, which runs the
@@ -101,29 +101,32 @@ struct drm_vc5_submit
Mesa (master): v3d: Rename the vc5_dri.so driver to v3d_dri.so.
Module: Mesa Branch: master Commit: c4c488a2aeb24c0f468664c0cacd0d0a4e46 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c4c488a2aeb24c0f468664c0cacd0d0a4e46 Author: Eric Anholt <e...@anholt.net> Date: Fri Aug 25 15:34:22 2017 -0700 v3d: Rename the vc5_dri.so driver to v3d_dri.so. This allows the driver to load against the merged kernel DRM driver. In the process, rename most of the build system variables and gallium plumbing functions. --- configure.ac | 18 +++--- meson.build| 6 ++--- meson_options.txt | 2 +- src/broadcom/Makefile.vc5.am | 6 ++--- src/broadcom/meson.build | 10 src/gallium/Makefile.am| 4 ++-- .../auxiliary/pipe-loader/pipe_loader_drm.c| 8 +++ src/gallium/auxiliary/target-helpers/drm_helper.h | 10 .../auxiliary/target-helpers/drm_helper_public.h | 4 ++-- src/gallium/drivers/vc5/Automake.inc | 10 src/gallium/drivers/vc5/Makefile.am| 28 +++--- src/gallium/drivers/vc5/Makefile.sources | 2 +- src/gallium/drivers/vc5/meson.build| 22 - src/gallium/drivers/vc5/v3dx_simulator.c | 4 ++-- src/gallium/drivers/vc5/vc5_bufmgr.c | 2 +- src/gallium/drivers/vc5/vc5_context.h | 2 +- src/gallium/drivers/vc5/vc5_job.c | 2 +- src/gallium/drivers/vc5/vc5_screen.c | 4 ++-- src/gallium/drivers/vc5/vc5_screen.h | 2 +- src/gallium/drivers/vc5/vc5_simulator.c| 4 ++-- src/gallium/drivers/vc5/vc5_simulator_wrapper.cpp | 4 ++-- src/gallium/meson.build| 4 ++-- src/gallium/targets/dri/meson.build| 4 ++-- src/gallium/targets/dri/target.c | 8 +++ src/gallium/winsys/vc5/drm/Android.mk | 2 +- src/gallium/winsys/vc5/drm/Makefile.am | 4 ++-- src/gallium/winsys/vc5/drm/meson.build | 4 ++-- src/gallium/winsys/vc5/drm/vc5_drm_public.h| 2 +- src/gallium/winsys/vc5/drm/vc5_drm_winsys.c| 4 ++-- 29 files changed, 93 insertions(+), 93 deletions(-) diff --git a/configure.ac b/configure.ac index 5f5e76040d..81ce001e3c 100644 --- a/configure.ac +++ b/configure.ac @@ -1372,7 +1372,7 @@ GALLIUM_DRIVERS_DEFAULT="r300,r600,svga,swrast" AC_ARG_WITH([gallium-drivers], [AS_HELP_STRING([--with-gallium-drivers@<:@=DIRS...@:>@], [comma delimited Gallium drivers list, e.g. - "i915,nouveau,r300,r600,radeonsi,freedreno,pl111,svga,swrast,swr,tegra,vc4,vc5,virgl,etnaviv,imx" + "i915,nouveau,r300,r600,radeonsi,freedreno,pl111,svga,swrast,swr,tegra,v3d,vc4,virgl,etnaviv,imx" @<:@default=r300,r600,svga,swrast@:>@])], [with_gallium_drivers="$withval"], [with_gallium_drivers="$GALLIUM_DRIVERS_DEFAULT"]) @@ -2734,12 +2734,12 @@ if test -n "$with_gallium_drivers"; then DEFINES="$DEFINES -DUSE_VC4_SIMULATOR"], [USE_VC4_SIMULATOR=no]) ;; -xvc5) -HAVE_GALLIUM_VC5=yes +xv3d) +HAVE_GALLIUM_V3D=yes -PKG_CHECK_MODULES([VC5_SIMULATOR], [v3dv3], - [USE_VC5_SIMULATOR=yes; - DEFINES="$DEFINES -DUSE_VC5_SIMULATOR"], +PKG_CHECK_MODULES([V3D_SIMULATOR], [v3dv3], + [USE_V3D_SIMULATOR=yes; + DEFINES="$DEFINES -DUSE_V3D_SIMULATOR"], [AC_MSG_ERROR([vc5 requires the simulator])]) ;; xpl111) @@ -2892,8 +2892,8 @@ AM_CONDITIONAL(HAVE_GALLIUM_SWR, test "x$HAVE_GALLIUM_SWR" = xyes) AM_CONDITIONAL(HAVE_GALLIUM_SWRAST, test "x$HAVE_GALLIUM_SOFTPIPE" = xyes -o \ "x$HAVE_GALLIUM_LLVMPIPE" = xyes -o \ "x$HAVE_GALLIUM_SWR" = xyes) +AM_CONDITIONAL(HAVE_GALLIUM_V3D, test "x$HAVE_GALLIUM_V3D" = xyes) AM_CONDITIONAL(HAVE_GALLIUM_VC4, test "x$HAVE_GALLIUM_VC4" = xyes) -AM_CONDITIONAL(HAVE_GALLIUM_VC5, test "x$HAVE_GALLIUM_VC5" = xyes) AM_CONDITIONAL(HAVE_GALLIUM_VIRGL, test "x$HAVE_GALLIUM_VIRGL" = xyes) AM_CONDITIONAL(HAVE_GALLIUM_STATIC_TARGETS, test "x$enable_shared_pipe_drivers" = xno) @@ -2921,7 +2921,7 @@ AM_CONDITIONAL(HAVE_AMD_DRIVERS, test "x$HAVE_GALLIUM_RADEONSI" = xyes -o \ "x$HAVE_RADEON_VULKAN" = xyes) AM_CONDITIONAL(HAVE_BROADCOM_DRIVERS, test "x$HAVE_GALLIUM_V
Mesa (master): v3d: Enable the driver by default.
Module: Mesa
Branch: master
Commit: 795488d2bf4c7b500634d6928e96c4533e515cfe
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=795488d2bf4c7b500634d6928e96c4533e515cfe
Author: Eric Anholt <e...@anholt.net>
Date: Tue May 1 12:20:11 2018 -0700
v3d: Enable the driver by default.
Now that we have a stabilized ABI and a fairly conformant driver, turn it
on.
---
configure.ac| 2 +-
src/gallium/drivers/v3d/meson.build | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/configure.ac b/configure.ac
index a73471b7b4..30980151ee 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2740,7 +2740,7 @@ if test -n "$with_gallium_drivers"; then
PKG_CHECK_MODULES([V3D_SIMULATOR], [v3dv3],
[USE_V3D_SIMULATOR=yes;
DEFINES="$DEFINES -DUSE_V3D_SIMULATOR"],
- [AC_MSG_ERROR([vc5 requires the simulator])])
+ [USE_V3D_SIMULATOR=no])
;;
xpl111)
HAVE_GALLIUM_PL111=yes
diff --git a/src/gallium/drivers/v3d/meson.build
b/src/gallium/drivers/v3d/meson.build
index 38021515ed..18e68a6269 100644
--- a/src/gallium/drivers/v3d/meson.build
+++ b/src/gallium/drivers/v3d/meson.build
@@ -53,7 +53,7 @@ files_per_version = files(
)
v3dv3_c_args = []
-dep_v3dv3 = dependency('v3dv3')
+dep_v3dv3 = dependency('v3dv3', required: false)
if dep_v3dv3.found()
v3dv3_c_args = '-DUSE_V3D_SIMULATOR'
endif
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Mesa (master): v3d: Rename driver functions from vc5 to v3d.
Module: Mesa Branch: master Commit: 01ae6a91896e9cce7a817445db0b11825f9f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=01ae6a91896e9cce7a817445db0b11825f9f Author: Eric Anholt <e...@anholt.net> Date: Tue May 1 12:39:31 2018 -0700 v3d: Rename driver functions from vc5 to v3d. This is the final step of the driver rename. --- src/gallium/drivers/v3d/v3d_blit.c | 96 - src/gallium/drivers/v3d/v3d_bufmgr.c| 158 +++--- src/gallium/drivers/v3d/v3d_bufmgr.h| 50 ++--- src/gallium/drivers/v3d/v3d_cl.c| 24 +-- src/gallium/drivers/v3d/v3d_cl.h| 98 - src/gallium/drivers/v3d/v3d_context.c | 112 +- src/gallium/drivers/v3d/v3d_context.h | 210 +- src/gallium/drivers/v3d/v3d_fence.c | 38 ++-- src/gallium/drivers/v3d/v3d_format_table.h | 2 +- src/gallium/drivers/v3d/v3d_formats.c | 34 +-- src/gallium/drivers/v3d/v3d_job.c | 188 - src/gallium/drivers/v3d/v3d_program.c | 264 +++ src/gallium/drivers/v3d/v3d_query.c | 84 src/gallium/drivers/v3d/v3d_resource.c | 220 +-- src/gallium/drivers/v3d/v3d_resource.h | 48 ++--- src/gallium/drivers/v3d/v3d_screen.c| 72 +++ src/gallium/drivers/v3d/v3d_screen.h| 22 +- src/gallium/drivers/v3d/v3d_simulator.c | 162 +++--- src/gallium/drivers/v3d/v3d_tiling.c| 102 - src/gallium/drivers/v3d/v3d_tiling.h| 18 +- src/gallium/drivers/v3d/v3d_uniforms.c | 114 +- src/gallium/drivers/v3d/v3dx_context.h | 8 +- src/gallium/drivers/v3d/v3dx_draw.c | 264 +++ src/gallium/drivers/v3d/v3dx_emit.c | 258 +++ src/gallium/drivers/v3d/v3dx_format_table.c | 4 +- src/gallium/drivers/v3d/v3dx_job.c | 4 +- src/gallium/drivers/v3d/v3dx_rcl.c | 74 +++ src/gallium/drivers/v3d/v3dx_simulator.c| 22 +- src/gallium/drivers/v3d/v3dx_state.c| 316 ++-- 29 files changed, 1533 insertions(+), 1533 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=01ae6a91896e9cce7a817445db0b11825f9f ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): v3d: Rename the driver files from "vc5" to "v3d".
Module: Mesa
Branch: master
Commit: 8c47ebbd232704ab048eab2572e2b2a44f38957a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c47ebbd232704ab048eab2572e2b2a44f38957a
Author: Eric Anholt <e...@anholt.net>
Date: Tue May 1 12:24:48 2018 -0700
v3d: Rename the driver files from "vc5" to "v3d".
---
configure.ac | 4 +-
src/broadcom/Makefile.am | 2 +-
src/broadcom/{Makefile.vc5.am => Makefile.v3d.am} | 0
src/gallium/Makefile.am| 2 +-
src/gallium/auxiliary/target-helpers/drm_helper.h | 2 +-
src/gallium/drivers/{vc5 => v3d}/.editorconfig | 0
src/gallium/drivers/{vc5 => v3d}/Automake.inc | 4 +-
src/gallium/drivers/{vc5 => v3d}/Makefile.am | 0
src/gallium/drivers/v3d/Makefile.sources | 36
src/gallium/drivers/{vc5 => v3d}/meson.build | 50 +++---
.../drivers/{vc5/vc5_blit.c => v3d/v3d_blit.c} | 2 +-
.../drivers/{vc5/vc5_bufmgr.c => v3d/v3d_bufmgr.c} | 4 +-
.../drivers/{vc5/vc5_bufmgr.h => v3d/v3d_bufmgr.h} | 2 +-
src/gallium/drivers/{vc5/vc5_cl.c => v3d/v3d_cl.c} | 2 +-
src/gallium/drivers/{vc5/vc5_cl.h => v3d/v3d_cl.h} | 0
.../{vc5/vc5_context.c => v3d/v3d_context.c} | 6 +--
.../{vc5/vc5_context.h => v3d/v3d_context.h} | 8 ++--
.../drivers/{vc5/vc5_fence.c => v3d/v3d_fence.c} | 4 +-
.../vc5_format_table.h => v3d/v3d_format_table.h} | 0
.../{vc5/vc5_formats.c => v3d/v3d_formats.c} | 4 +-
.../drivers/{vc5/vc5_job.c => v3d/v3d_job.c} | 2 +-
.../{vc5/vc5_program.c => v3d/v3d_program.c} | 2 +-
.../drivers/{vc5/vc5_query.c => v3d/v3d_query.c} | 2 +-
.../{vc5/vc5_resource.c => v3d/v3d_resource.c} | 8 ++--
.../{vc5/vc5_resource.h => v3d/v3d_resource.h} | 2 +-
.../drivers/{vc5/vc5_screen.c => v3d/v3d_screen.c} | 6 +--
.../drivers/{vc5/vc5_screen.h => v3d/v3d_screen.h} | 0
.../{vc5/vc5_simulator.c => v3d/v3d_simulator.c} | 6 +--
.../v3d_simulator_wrapper.cpp} | 4 +-
.../v3d_simulator_wrapper.h} | 0
.../drivers/{vc5/vc5_tiling.c => v3d/v3d_tiling.c} | 6 +--
.../drivers/{vc5/vc5_tiling.h => v3d/v3d_tiling.h} | 0
.../{vc5/vc5_uniforms.c => v3d/v3d_uniforms.c} | 2 +-
src/gallium/drivers/{vc5 => v3d}/v3dx_context.h| 2 +-
.../drivers/{vc5/vc5_draw.c => v3d/v3dx_draw.c}| 6 +--
.../drivers/{vc5/vc5_emit.c => v3d/v3dx_emit.c}| 2 +-
.../drivers/{vc5 => v3d}/v3dx_format_table.c | 4 +-
src/gallium/drivers/{vc5 => v3d}/v3dx_job.c| 2 +-
.../drivers/{vc5/vc5_rcl.c => v3d/v3dx_rcl.c} | 4 +-
src/gallium/drivers/{vc5 => v3d}/v3dx_simulator.c | 6 +--
.../drivers/{vc5/vc5_state.c => v3d/v3dx_state.c} | 4 +-
src/gallium/drivers/vc5/Makefile.sources | 36
src/gallium/meson.build| 4 +-
src/gallium/targets/dri/Makefile.am| 2 +-
src/gallium/winsys/{vc5 => v3d}/drm/Android.mk | 0
src/gallium/winsys/{vc5 => v3d}/drm/Makefile.am| 0
src/gallium/winsys/v3d/drm/Makefile.sources| 3 ++
src/gallium/winsys/{vc5 => v3d}/drm/meson.build| 2 +-
.../vc5_drm_public.h => v3d/drm/v3d_drm_public.h} | 0
.../vc5_drm_winsys.c => v3d/drm/v3d_drm_winsys.c} | 4 +-
src/gallium/winsys/vc5/drm/Makefile.sources| 3 --
51 files changed, 128 insertions(+), 128 deletions(-)
diff --git a/configure.ac b/configure.ac
index 81ce001e3c..a73471b7b4 100644
--- a/configure.ac
+++ b/configure.ac
@@ -3037,8 +3037,8 @@ AC_CONFIG_FILES([Makefile
src/gallium/drivers/tegra/Makefile
src/gallium/drivers/etnaviv/Makefile
src/gallium/drivers/imx/Makefile
+ src/gallium/drivers/v3d/Makefile
src/gallium/drivers/vc4/Makefile
- src/gallium/drivers/vc5/Makefile
src/gallium/drivers/virgl/Makefile
src/gallium/state_trackers/clover/Makefile
src/gallium/state_trackers/dri/Makefile
@@ -3085,8 +3085,8 @@ AC_CONFIG_FILES([Makefile
src/gallium/winsys/sw/wrapper/Makefile
src/gallium/winsys/sw/xlib/Makefile
src/gallium/winsys/tegra/drm/Makefile
+ src/gallium/winsys/v3d/drm/Makefile
src/gallium/winsys/vc4/drm/Makefile
- src/gallium/winsys/vc5/drm/Makefile
src/gallium/winsys/virgl/drm/Makefile
src/gallium/winsys/virgl/vtest/Makefile
src/gbm/Makefile
diff --git a/src/broadcom/Makefile.am b/src/broadcom/Makefile.am
index 49267de73b..4faa772154 100644
--- a/src/broadcom/Makefile.am
+++ b/src/broadcom/Makefile.am
@@ -60,6 +60,6 @@ PYTHON_GEN = $(AM_V_GEN)$(PYTHON2) $(PYTHON_F
Mesa (master): freedreno: Fix ir3_cmdline.c build.
Module: Mesa
Branch: master
Commit: 800be7f2777350f97b43d77b0e6bfc1df2b756a1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=800be7f2777350f97b43d77b0e6bfc1df2b756a1
Author: Eric Anholt <e...@anholt.net>
Date: Tue May 1 13:07:21 2018 -0700
freedreno: Fix ir3_cmdline.c build.
Fixes: 6487e7a30c9e ("nir: move GL specific passes to src/compiler/glsl")
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
Reviewed-by: Rob Clark <robdcl...@gmail.com>
---
src/gallium/drivers/freedreno/ir3/ir3_cmdline.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
index 5631216ebd..55809d527a 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
@@ -46,6 +46,7 @@
#include "compiler/glsl/standalone.h"
#include "compiler/glsl/glsl_to_nir.h"
+#include "compiler/glsl/gl_nir.h"
#include "compiler/nir_types.h"
#include "compiler/spirv/nir_spirv.h"
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Mesa (master): broadcom/vc5: Add validation that we don't violate GFXH-1633 requirements.
Module: Mesa
Branch: master
Commit: 77b4f30bae4100b2a80e961b89359e1fd1beed9d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=77b4f30bae4100b2a80e961b89359e1fd1beed9d
Author: Eric Anholt <e...@anholt.net>
Date: Wed Apr 25 16:24:15 2018 -0700
broadcom/vc5: Add validation that we don't violate GFXH-1633 requirements.
We don't use ldunifa yet, but we will eventually for UBOs.
---
src/broadcom/compiler/qpu_validate.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/broadcom/compiler/qpu_validate.c
b/src/broadcom/compiler/qpu_validate.c
index b459d81b44..fb2ed123ab 100644
--- a/src/broadcom/compiler/qpu_validate.c
+++ b/src/broadcom/compiler/qpu_validate.c
@@ -124,6 +124,19 @@ qpu_validate_inst(struct v3d_qpu_validate_state *state,
struct qinst *qinst)
fail_instr(state, "LDUNIF after a LDVARY");
}
+/* GFXH-1633 */
+bool last_reads_ldunif = (state->last && (state->last->sig.ldunif ||
+ state->last->sig.ldunifrf));
+bool last_reads_ldunifa = (state->last && (state->last->sig.ldunifa ||
+
state->last->sig.ldunifarf));
+bool reads_ldunif = inst->sig.ldunif || inst->sig.ldunifrf;
+bool reads_ldunifa = inst->sig.ldunifa || inst->sig.ldunifarf;
+if ((last_reads_ldunif && reads_ldunifa) ||
+(last_reads_ldunifa && reads_ldunif)) {
+fail_instr(state,
+ "LDUNIF and LDUNIFA can't be next to each other");
+}
+
int tmu_writes = 0;
int sfu_writes = 0;
int vpm_writes = 0;
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Mesa (master): broadcom/vc5: Add support for centroid varyings.
Module: Mesa
Branch: master
Commit: 76ee9edcb4f5be8699cfb9a6c4aa231c4e7d4183
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=76ee9edcb4f5be8699cfb9a6c4aa231c4e7d4183
Author: Eric Anholt <e...@anholt.net>
Date: Thu Apr 26 09:24:32 2018 -0700
broadcom/vc5: Add support for centroid varyings.
It would be nice to share the flags packet emit logic with flat shade
flags, but I couldn't come up with a good way while still using our pack
macros. We need to refactor this to shader record setup at compile time,
anyway.
Fixes ext_framebuffer_multisample-interpolation * centroid-*
---
src/broadcom/compiler/nir_to_vir.c| 33 +
src/broadcom/compiler/v3d_compiler.h | 7 +++
src/broadcom/compiler/vir.c | 4
src/gallium/drivers/vc5/vc5_context.h | 1 +
src/gallium/drivers/vc5/vc5_draw.c| 3 +++
src/gallium/drivers/vc5/vc5_emit.c| 39 +++
src/gallium/drivers/vc5/vc5_program.c | 14 +
7 files changed, 97 insertions(+), 4 deletions(-)
diff --git a/src/broadcom/compiler/nir_to_vir.c
b/src/broadcom/compiler/nir_to_vir.c
index d6c2d1902b..ec8f22321f 100644
--- a/src/broadcom/compiler/nir_to_vir.c
+++ b/src/broadcom/compiler/nir_to_vir.c
@@ -436,6 +436,7 @@ emit_fragment_varying(struct v3d_compile *c, nir_variable
*var,
/* FALLTHROUGH */
case INTERP_MODE_SMOOTH:
if (var->data.centroid) {
+BITSET_SET(c->centroid_flags, i);
return vir_FADD(c, vir_FMUL(c, vary,
c->payload_w_centroid),
r5);
} else {
@@ -1985,6 +1986,36 @@ vir_emit_last_thrsw(struct v3d_compile *c)
c->last_thrsw->is_last_thrsw = true;
}
+/* There's a flag in the shader for "centroid W used in addition to center W",
+ * so we need to walk the program after VIR optimization to see if both are
+ * used.
+ */
+static void
+vir_check_payload_w(struct v3d_compile *c)
+{
+if (c->s->info.stage != MESA_SHADER_FRAGMENT)
+return;
+
+bool any_centroid = false;
+for (int i = 0; i < ARRAY_SIZE(c->centroid_flags); i++) {
+if (c->centroid_flags[i])
+any_centroid = true;
+}
+if (!any_centroid)
+return;
+
+vir_for_each_inst_inorder(inst, c) {
+for (int i = 0; i < vir_get_nsrc(inst); i++) {
+if (inst->src[i].file == QFILE_REG &&
+inst->src[i].index == 0) {
+c->uses_centroid_and_center_w = true;
+return;
+}
+}
+}
+
+}
+
void
v3d_nir_to_vir(struct v3d_compile *c)
{
@@ -2024,6 +2055,8 @@ v3d_nir_to_vir(struct v3d_compile *c)
vir_optimize(c);
vir_lower_uniforms(c);
+vir_check_payload_w(c);
+
/* XXX: vir_schedule_instructions(c); */
if (V3D_DEBUG & (V3D_DEBUG_VIR |
diff --git a/src/broadcom/compiler/v3d_compiler.h
b/src/broadcom/compiler/v3d_compiler.h
index e89ea7be21..4dba23c067 100644
--- a/src/broadcom/compiler/v3d_compiler.h
+++ b/src/broadcom/compiler/v3d_compiler.h
@@ -478,6 +478,10 @@ struct v3d_compile {
*/
uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
+uint32_t centroid_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
+
+bool uses_centroid_and_center_w;
+
struct v3d_ubo_range *ubo_ranges;
bool *ubo_range_used;
uint32_t ubo_ranges_array_size;
@@ -657,8 +661,11 @@ struct v3d_fs_prog_data {
*/
uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
+uint32_t centroid_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
+
bool writes_z;
bool discard;
+bool uses_centroid_and_center_w;
};
/* Special nir_load_input intrinsic index for loading the current TLB
diff --git a/src/broadcom/compiler/vir.c b/src/broadcom/compiler/vir.c
index 93990ee806..0de5335d12 100644
--- a/src/broadcom/compiler/vir.c
+++ b/src/broadcom/compiler/vir.c
@@ -758,6 +758,9 @@ v3d_set_fs_prog_data_inputs(struct v3d_compile *c,
for (int i = 0; i < V3D_MAX_FS_INPUTS; i++) {
if (BITSET_TEST(c->flat_shade_flags, i))
prog_data->flat_shade_flags[i / 24] |= 1 << (i % 24);
+
+if (BITSET_TEST(c->centroid_flags, i))
+prog_data->centroid_flags[i / 24] |= 1 << (i % 24);
}
}
@@ -838,6 +841,7 @@ uint64_t *v3d_compile_fs(const struct v3d_compiler
*compiler,
prog_data->writes_z = (c->s->info.outputs_written &
(1 << FRAG_RESULT_DEPTH));
prog_data->discard = c->s->info.fs.uses_disc
Mesa (master): broadcom/vc5: Add validation that we don't violate GFXH-1625 requirements.
Module: Mesa
Branch: master
Commit: 089c32eefd2f9afcbfc87349beacbdf9d005cfac
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=089c32eefd2f9afcbfc87349beacbdf9d005cfac
Author: Eric Anholt <e...@anholt.net>
Date: Wed Apr 25 16:16:27 2018 -0700
broadcom/vc5: Add validation that we don't violate GFXH-1625 requirements.
We don't use TMUWT yet, but we will once we do SSBOs.
---
src/broadcom/compiler/qpu_validate.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/broadcom/compiler/qpu_validate.c
b/src/broadcom/compiler/qpu_validate.c
index 492f2e64d0..b459d81b44 100644
--- a/src/broadcom/compiler/qpu_validate.c
+++ b/src/broadcom/compiler/qpu_validate.c
@@ -247,6 +247,11 @@ qpu_validate_inst(struct v3d_qpu_validate_state *state,
struct qinst *qinst)
if (v3d_qpu_sig_writes_address(devinfo, >sig))
fail_instr(state, "RF write after THREND");
+
+/* GFXH-1625: No TMUWT in the last instruction */
+if (state->last_thrsw_ip - state->ip == 2 &&
+inst->alu.add.op == V3D_QPU_A_TMUWT)
+fail_instr(state, "TMUWT in last instruction");
}
if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH) {
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Mesa (master): broadcom/vc5: Add an assert about GFXH-1559.
Module: Mesa Branch: master Commit: e2f33178010a9612d8d89bf128e3a01a69e1dd82 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2f33178010a9612d8d89bf128e3a01a69e1dd82 Author: Eric Anholt <e...@anholt.net> Date: Wed Apr 25 16:30:20 2018 -0700 broadcom/vc5: Add an assert about GFXH-1559. Our TF outputs always start at 6 or 7 currently, so we don't hit the broken 8 case. Let's make sure that doesn't change somehow. --- src/gallium/drivers/vc5/vc5_program.c | 9 + 1 file changed, 9 insertions(+) diff --git a/src/gallium/drivers/vc5/vc5_program.c b/src/gallium/drivers/vc5/vc5_program.c index 6beb3359f2..d885cdf297 100644 --- a/src/gallium/drivers/vc5/vc5_program.c +++ b/src/gallium/drivers/vc5/vc5_program.c @@ -125,6 +125,10 @@ vc5_set_transform_feedback_outputs(struct vc5_uncompiled_shader *so, .output_buffer_to_write_to = buffer, }; +/* GFXH-1559 */ +assert(unpacked.first_shaded_vertex_value_to_output != 8 || + so->num_tf_specs != 0); + assert(so->num_tf_specs != ARRAY_SIZE(so->tf_specs)); V3D33_TRANSFORM_FEEDBACK_OUTPUT_DATA_SPEC_pack(NULL, (void *)>tf_specs[so->num_tf_specs], @@ -136,6 +140,11 @@ vc5_set_transform_feedback_outputs(struct vc5_uncompiled_shader *so, * though. */ unpacked.first_shaded_vertex_value_to_output++; + +/* GFXH-1559 */ +assert(unpacked.first_shaded_vertex_value_to_output != 8 || + so->num_tf_specs != 0); + V3D33_TRANSFORM_FEEDBACK_OUTPUT_DATA_SPEC_pack(NULL, (void *)>tf_specs_psiz[so->num_tf_specs], ); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): st: Choose a 2101010 format for GL_RGB/GL_RGBA with a 2_10_10_10 type.
Module: Mesa
Branch: master
Commit: 8adf813f83b9f54e3c9958cc7c7a485e6e2e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8adf813f83b9f54e3c9958cc7c7a485e6e2e
Author: Eric Anholt <e...@anholt.net>
Date: Wed Apr 25 11:40:40 2018 -0700
st: Choose a 2101010 format for GL_RGB/GL_RGBA with a 2_10_10_10 type.
GLES's GL_EXT_texture_type_2_10_10_10_REV allows uploading this type to an
unsized internalformat, and it should be non-color-renderable.
fbobject.c's implementation of the check for color-renderable is checks
that the texture has a 2101010 mesa format, so make sure that we have
chosen a 2101010 format so that check can do what it meant to.
Fixes KHR-GLES3.packed_pixels.pbo_rectangle.rgb on vc5.
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
---
src/mesa/state_tracker/st_format.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/mesa/state_tracker/st_format.c
b/src/mesa/state_tracker/st_format.c
index 3db3c7e967..418f534202 100644
--- a/src/mesa/state_tracker/st_format.c
+++ b/src/mesa/state_tracker/st_format.c
@@ -2138,6 +2138,19 @@ st_choose_format(struct st_context *st, GLenum
internalFormat,
goto success;
}
+ /* For an unsized GL_RGB but a 2_10_10_10 type, try to pick one of the
+* 2_10_10_10 formats. This is important for
+* GL_EXT_texture_type_2_10_10_10_EXT support, which says that these
+* formats are not color-renderable. Mesa's check for making those
+* non-color-renderable is based on our chosen format being 2101010.
+*/
+ if (type == GL_UNSIGNED_INT_2_10_10_10_REV) {
+ if (internalFormat == GL_RGB)
+ internalFormat = GL_RGB10;
+ else if (internalFormat == GL_RGBA)
+ internalFormat = GL_RGB10_A2;
+ }
+
/* search table for internalFormat */
for (i = 0; i < ARRAY_SIZE(format_map); i++) {
const struct format_mapping *mapping = _map[i];
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Mesa (master): broadcom/vc5: Add QPU validation for register writes after thrend.
Module: Mesa
Branch: master
Commit: dc4cb04ee516c5e17181cf04d932dcc2da533388
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc4cb04ee516c5e17181cf04d932dcc2da533388
Author: Eric Anholt <e...@anholt.net>
Date: Wed Apr 25 13:51:47 2018 -0700
broadcom/vc5: Add QPU validation for register writes after thrend.
The next shader gets to start writing the register file during these
slots, so make sure we don't stomp over them.
The only case of hitting this that I could imagine would be dead writes.
---
src/broadcom/compiler/qpu_validate.c | 34 +++---
1 file changed, 31 insertions(+), 3 deletions(-)
diff --git a/src/broadcom/compiler/qpu_validate.c
b/src/broadcom/compiler/qpu_validate.c
index 4ef587c1d5..492f2e64d0 100644
--- a/src/broadcom/compiler/qpu_validate.c
+++ b/src/broadcom/compiler/qpu_validate.c
@@ -41,7 +41,15 @@ struct v3d_qpu_validate_state {
int last_sfu_write;
int last_branch_ip;
int last_thrsw_ip;
+
+/* Set when we've found the last-THRSW signal, or if we were started
+ * in single-segment mode.
+ */
bool last_thrsw_found;
+
+/* Set when we've found the THRSW after the last THRSW */
+bool thrend_found;
+
int thrsw_count;
};
@@ -204,6 +212,9 @@ qpu_validate_inst(struct v3d_qpu_validate_state *state,
struct qinst *qinst)
if (in_branch_delay_slots(state))
fail_instr(state, "THRSW in a branch delay slot.");
+if (state->last_thrsw_found)
+state->thrend_found = true;
+
if (state->last_thrsw_ip == state->ip - 1) {
/* If it's the second THRSW in a row, then it's just a
* last-thrsw signal.
@@ -221,6 +232,23 @@ qpu_validate_inst(struct v3d_qpu_validate_state *state,
struct qinst *qinst)
}
}
+if (state->thrend_found &&
+state->last_thrsw_ip - state->ip <= 2 &&
+inst->type == V3D_QPU_INSTR_TYPE_ALU) {
+if ((inst->alu.add.op != V3D_QPU_A_NOP &&
+ !inst->alu.add.magic_write)) {
+fail_instr(state, "RF write after THREND");
+}
+
+if ((inst->alu.mul.op != V3D_QPU_M_NOP &&
+ !inst->alu.mul.magic_write)) {
+fail_instr(state, "RF write after THREND");
+}
+
+if (v3d_qpu_sig_writes_address(devinfo, >sig))
+fail_instr(state, "RF write after THREND");
+}
+
if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH) {
if (in_branch_delay_slots(state))
fail_instr(state, "branch in a branch delay slot.");
@@ -262,6 +290,8 @@ qpu_validate(struct v3d_compile *c)
.last_thrsw_ip = -10,
.last_branch_ip = -10,
.ip = 0,
+
+.last_thrsw_found = !c->last_thrsw,
};
vir_for_each_block(block, c) {
@@ -273,8 +303,6 @@ qpu_validate(struct v3d_compile *c)
"thread switch found without last-THRSW in
program");
}
-if (state.thrsw_count == 0 ||
-(state.last_thrsw_found && state.thrsw_count == 1)) {
+if (!state.thrend_found)
fail_instr(, "No program-end THRSW found");
-}
}
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Mesa (master): broadcom/vc5: Implement GFXH-1742 workaround (emit 2 dummy stores on 4.x).
Module: Mesa
Branch: master
Commit: 57ceb95c842215880b7cb416fbdb9545276cfc05
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=57ceb95c842215880b7cb416fbdb9545276cfc05
Author: Eric Anholt <e...@anholt.net>
Date: Wed Apr 25 14:18:52 2018 -0700
broadcom/vc5: Implement GFXH-1742 workaround (emit 2 dummy stores on 4.x).
This should fix help with intermittent GPU hangs in tests switching
formats while rendering small frames. Unfortunately, it didn't help with
the tests I'm having troubles with.
---
src/gallium/drivers/vc5/vc5_rcl.c | 35 +++
1 file changed, 27 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_rcl.c
b/src/gallium/drivers/vc5/vc5_rcl.c
index 7f804aa27a..7d32d9ad0e 100644
--- a/src/gallium/drivers/vc5/vc5_rcl.c
+++ b/src/gallium/drivers/vc5/vc5_rcl.c
@@ -715,20 +715,39 @@ v3dX(emit_rcl)(struct vc5_job *job)
coords.tile_row_number = 0;
}
+/* Emit an initial clear of the tile buffers. This is necessary for
+ * any buffers that should be cleared (since clearing normally happens
+ * at the *end* of the generic tile list), but it's also nice to clear
+ * everything so the first tile doesn't inherit any contents from some
+ * previous frame.
+ *
+ * Also, implement the GFXH-1742 workaround. There's a race in the HW
+ * between the RCL updating the TLB's internal type/size and the
+ * spawning of the QPU instances using the TLB's current internal
+ * type/size. To make sure the QPUs get the right state,, we need 1
+ * dummy store in between internal type/size changes on V3D 3.x, and 2
+ * dummy stores on 4.x.
+ */
#if V3D_VERSION < 40
cl_emit(>rcl, STORE_TILE_BUFFER_GENERAL, store) {
store.buffer_to_store = NONE;
}
#else
-cl_emit(>rcl, END_OF_LOADS, end);
-cl_emit(>rcl, STORE_TILE_BUFFER_GENERAL, store) {
-store.buffer_to_store = NONE;
-}
-cl_emit(>rcl, CLEAR_TILE_BUFFERS, clear) {
-clear.clear_z_stencil_buffer = true;
-clear.clear_all_render_targets = true;
+for (int i = 0; i < 2; i++) {
+if (i > 0)
+cl_emit(>rcl, TILE_COORDINATES, coords);
+cl_emit(>rcl, END_OF_LOADS, end);
+cl_emit(>rcl, STORE_TILE_BUFFER_GENERAL, store) {
+store.buffer_to_store = NONE;
+}
+if (i == 0) {
+cl_emit(>rcl, CLEAR_TILE_BUFFERS, clear) {
+clear.clear_z_stencil_buffer = true;
+clear.clear_all_render_targets = true;
+}
+}
+cl_emit(>rcl, END_OF_TILE_MARKER, end);
}
-cl_emit(>rcl, END_OF_TILE_MARKER, end);
#endif
cl_emit(>rcl, FLUSH_VCD_CACHE, flush);
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Mesa (master): gallium/util: Fix incorrect refcounting of separate stencil.
Module: Mesa
Branch: master
Commit: 069c409f434ab215940aad2092d5d236b410a7b9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=069c409f434ab215940aad2092d5d236b410a7b9
Author: Eric Anholt <e...@anholt.net>
Date: Wed Apr 25 09:47:40 2018 -0700
gallium/util: Fix incorrect refcounting of separate stencil.
The driver may have a reference on the separate stencil buffer for some
reason (like an unflushed job using it), so we can't directly free the
resource and should instead just decrement the refcount that we own.
Fixes double-free in KHR-GLES3.packed_depth_stencil.blit.depth32f_stencil8
on vc5.
Fixes: e94eb5e6000e ("gallium/util: add u_transfer_helper")
Reviewed-by: Rob Clark <robdcl...@gmail.com>
---
src/gallium/auxiliary/util/u_transfer_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_transfer_helper.c
b/src/gallium/auxiliary/util/u_transfer_helper.c
index dd31049920..3b085fd99f 100644
--- a/src/gallium/auxiliary/util/u_transfer_helper.c
+++ b/src/gallium/auxiliary/util/u_transfer_helper.c
@@ -138,8 +138,7 @@ u_transfer_helper_resource_destroy(struct pipe_screen
*pscreen,
if (helper->vtbl->get_stencil) {
struct pipe_resource *stencil = helper->vtbl->get_stencil(prsc);
- if (stencil)
- helper->vtbl->resource_destroy(pscreen, stencil);
+ pipe_resource_reference(, NULL);
}
helper->vtbl->resource_destroy(pscreen, prsc);
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Mesa (master): broadcom/vc5: Fix tile load/store of MSAA surfaces on 4.x.
Module: Mesa Branch: master Commit: 5710532e9e5b44e40c5ed65b2dcffe66f6803d01 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5710532e9e5b44e40c5ed65b2dcffe66f6803d01 Author: Eric Anholt <e...@anholt.net> Date: Tue Apr 24 13:22:41 2018 -0700 broadcom/vc5: Fix tile load/store of MSAA surfaces on 4.x. For single-sample we have to always program SAMPLE_0, but for multisample we want to store all the samples. --- src/broadcom/cle/v3d_packet_v41.xml | 4 ++-- src/broadcom/cle/v3d_packet_v42.xml | 4 ++-- src/gallium/drivers/vc5/vc5_rcl.c | 12 +++- 3 files changed, 15 insertions(+), 5 deletions(-) diff --git a/src/broadcom/cle/v3d_packet_v41.xml b/src/broadcom/cle/v3d_packet_v41.xml index 32934d71cd..5f6d643195 100644 --- a/src/broadcom/cle/v3d_packet_v41.xml +++ b/src/broadcom/cle/v3d_packet_v41.xml @@ -277,7 +277,7 @@ - + @@ -311,7 +311,7 @@ - + diff --git a/src/broadcom/cle/v3d_packet_v42.xml b/src/broadcom/cle/v3d_packet_v42.xml index db128b5451..f180e5eec5 100644 --- a/src/broadcom/cle/v3d_packet_v42.xml +++ b/src/broadcom/cle/v3d_packet_v42.xml @@ -278,7 +278,7 @@ - + @@ -312,7 +312,7 @@ - + diff --git a/src/gallium/drivers/vc5/vc5_rcl.c b/src/gallium/drivers/vc5/vc5_rcl.c index 2b1309bc1a..3289227513 100644 --- a/src/gallium/drivers/vc5/vc5_rcl.c +++ b/src/gallium/drivers/vc5/vc5_rcl.c @@ -85,7 +85,11 @@ load_general(struct vc5_cl *cl, struct pipe_surface *psurf, int buffer, load.height_in_ub_or_stride = slice->stride; } -/* XXX: MSAA */ +if (psurf->texture->nr_samples > 1) +load.decimate_mode = V3D_DECIMATE_MODE_ALL_SAMPLES; +else +load.decimate_mode = V3D_DECIMATE_MODE_SAMPLE_0; + #else /* V3D_VERSION < 40 */ /* Can't do raw ZSTENCIL loads -- need to load/store them to * separate buffers for Z and stencil. @@ -147,6 +151,12 @@ store_general(struct vc5_job *job, >slices[psurf->u.tex.level]; store.height_in_ub_or_stride = slice->stride; } + +if (psurf->texture->nr_samples > 1) +store.decimate_mode = V3D_DECIMATE_MODE_ALL_SAMPLES; +else +store.decimate_mode = V3D_DECIMATE_MODE_SAMPLE_0; + #else /* V3D_VERSION < 40 */ /* Can't do raw ZSTENCIL stores -- need to load/store them to * separate buffers for Z and stencil. ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): broadcom/vc5: Remove leftover vc4 MSAA lowering setup in the FS key.
Module: Mesa
Branch: master
Commit: 503716fa8623f2f59a909adac0bd629c71661119
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=503716fa8623f2f59a909adac0bd629c71661119
Author: Eric Anholt <e...@anholt.net>
Date: Tue Apr 24 15:23:27 2018 -0700
broadcom/vc5: Remove leftover vc4 MSAA lowering setup in the FS key.
---
src/broadcom/compiler/v3d_compiler.h | 17 +
src/gallium/drivers/vc5/vc5_program.c | 5 +
2 files changed, 6 insertions(+), 16 deletions(-)
diff --git a/src/broadcom/compiler/v3d_compiler.h
b/src/broadcom/compiler/v3d_compiler.h
index 207e29733a..e89ea7be21 100644
--- a/src/broadcom/compiler/v3d_compiler.h
+++ b/src/broadcom/compiler/v3d_compiler.h
@@ -302,18 +302,11 @@ struct v3d_key {
uint8_t swizzle[4];
uint8_t return_size;
uint8_t return_channels;
-union {
-struct {
-unsigned compare_mode:1;
-unsigned compare_func:3;
-bool clamp_s:1;
-bool clamp_t:1;
-bool clamp_r:1;
-};
-struct {
-uint16_t msaa_width, msaa_height;
-};
-};
+unsigned compare_mode:1;
+unsigned compare_func:3;
+bool clamp_s:1;
+bool clamp_t:1;
+bool clamp_r:1;
} tex[V3D_MAX_TEXTURE_SAMPLERS];
uint8_t ucp_enables;
};
diff --git a/src/gallium/drivers/vc5/vc5_program.c
b/src/gallium/drivers/vc5/vc5_program.c
index 7bad80a168..6beb3359f2 100644
--- a/src/gallium/drivers/vc5/vc5_program.c
+++ b/src/gallium/drivers/vc5/vc5_program.c
@@ -363,10 +363,7 @@ vc5_setup_shared_key(struct vc5_context *vc5, struct
v3d_key *key,
key->tex[i].swizzle[3] = PIPE_SWIZZLE_W;
}
-if (sampler->texture->nr_samples > 1) {
-key->tex[i].msaa_width = sampler->texture->width0;
-key->tex[i].msaa_height = sampler->texture->height0;
-} else if (sampler){
+if (sampler) {
key->tex[i].compare_mode = sampler_state->compare_mode;
key->tex[i].compare_func = sampler_state->compare_func;
key->tex[i].clamp_s =
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Mesa (master): broadcom/vc5: Fix cpp of MSAA surfaces on 4.x.
Module: Mesa
Branch: master
Commit: 9f3f4284c0397615bfe50ba4e50aaffe5dc64e84
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f3f4284c0397615bfe50ba4e50aaffe5dc64e84
Author: Eric Anholt <e...@anholt.net>
Date: Tue Apr 24 14:56:23 2018 -0700
broadcom/vc5: Fix cpp of MSAA surfaces on 4.x.
The internal-type-bpp path is for surfaces that get stored in the raw TLB
format. For 4.x, we're storing MSAA as just 2x width/height at the
original format.
---
src/gallium/drivers/vc5/vc5_resource.c | 6 --
src/gallium/drivers/vc5/vc5_state.c| 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_resource.c
b/src/gallium/drivers/vc5/vc5_resource.c
index eb5fa4e908..3c2ed27077 100644
--- a/src/gallium/drivers/vc5/vc5_resource.c
+++ b/src/gallium/drivers/vc5/vc5_resource.c
@@ -566,9 +566,11 @@ vc5_resource_setup(struct pipe_screen *pscreen,
prsc->screen = pscreen;
if (prsc->nr_samples <= 1 ||
+screen->devinfo.ver >= 40 ||
util_format_is_depth_or_stencil(prsc->format)) {
-rsc->cpp = util_format_get_blocksize(prsc->format) *
-MAX2(prsc->nr_samples, 1);
+rsc->cpp = util_format_get_blocksize(prsc->format);
+if (screen->devinfo.ver < 40 && prsc->nr_samples > 1)
+rsc->cpp *= prsc->nr_samples;
} else {
assert(vc5_rt_format_supported(>devinfo,
prsc->format));
uint32_t output_image_format =
diff --git a/src/gallium/drivers/vc5/vc5_state.c
b/src/gallium/drivers/vc5/vc5_state.c
index 350bd6a4ed..42ae64157c 100644
--- a/src/gallium/drivers/vc5/vc5_state.c
+++ b/src/gallium/drivers/vc5/vc5_state.c
@@ -752,7 +752,7 @@ vc5_create_sampler_view(struct pipe_context *pctx, struct
pipe_resource *prsc,
#endif
tex.array_stride_64_byte_aligned = rsc->cube_map_stride / 64;
-if (prsc->nr_samples > 1) {
+if (prsc->nr_samples > 1 && V3D_VERSION < 40) {
/* Using texture views to reinterpret formats on our
* MSAA textures won't work, because we don't lay out
* the bits in memory as it's expected -- for example,
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Mesa (master): broadcom/vc5: Fix reloads of separate stencil buffers.
Module: Mesa
Branch: master
Commit: 0d4ce00d700631cce26c62b865b4013ef45572e7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d4ce00d700631cce26c62b865b4013ef45572e7
Author: Eric Anholt <e...@anholt.net>
Date: Tue Apr 24 17:50:50 2018 -0700
broadcom/vc5: Fix reloads of separate stencil buffers.
Like for stores, we need to emit a separate load_general packet.
---
src/gallium/drivers/vc5/vc5_rcl.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_rcl.c
b/src/gallium/drivers/vc5/vc5_rcl.c
index 3289227513..7f804aa27a 100644
--- a/src/gallium/drivers/vc5/vc5_rcl.c
+++ b/src/gallium/drivers/vc5/vc5_rcl.c
@@ -226,10 +226,22 @@ vc5_rcl_emit_loads(struct vc5_job *job, struct vc5_cl *cl)
if ((loads_pending & PIPE_CLEAR_DEPTHSTENCIL) &&
(V3D_VERSION >= 40 ||
(job->zsbuf && job->zsbuf->texture->nr_samples > 1))) {
-load_general(cl, job->zsbuf,
- zs_buffer_from_pipe_bits(loads_pending),
- PIPE_CLEAR_DEPTHSTENCIL,
- _pending);
+struct vc5_resource *rsc = vc5_resource(job->zsbuf->texture);
+
+if (rsc->separate_stencil &&
+(loads_pending & PIPE_CLEAR_STENCIL)) {
+load_general(cl, job->zsbuf,
+ STENCIL,
+ PIPE_CLEAR_STENCIL,
+ _pending);
+}
+
+if (loads_pending & PIPE_CLEAR_DEPTHSTENCIL) {
+load_general(cl, job->zsbuf,
+ zs_buffer_from_pipe_bits(loads_pending),
+ loads_pending & PIPE_CLEAR_DEPTHSTENCIL,
+ _pending);
+}
}
#if V3D_VERSION < 40
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Mesa (master): broadcom/vc5: Implement stencil blits using RGBA.
Module: Mesa
Branch: master
Commit: ac207acb97cdfa203c686806ba3a41269e1bf35d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac207acb97cdfa203c686806ba3a41269e1bf35d
Author: Eric Anholt <e...@anholt.net>
Date: Tue Apr 24 11:11:40 2018 -0700
broadcom/vc5: Implement stencil blits using RGBA.
Fixes piglit fbo-depthstencil blit default_fb
---
src/gallium/drivers/vc5/vc5_blit.c | 76 +
src/gallium/drivers/vc5/vc5_state.c | 9 -
2 files changed, 83 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_blit.c
b/src/gallium/drivers/vc5/vc5_blit.c
index 64811416e5..66f530723f 100644
--- a/src/gallium/drivers/vc5/vc5_blit.c
+++ b/src/gallium/drivers/vc5/vc5_blit.c
@@ -209,6 +209,77 @@ vc5_render_blit(struct pipe_context *ctx, struct
pipe_blit_info *info)
return true;
}
+/* Implement stencil blits by reinterpreting the stencil data as an RGBA
+ * or R8 texture.
+ */
+static void
+vc5_stencil_blit(struct pipe_context *ctx, const struct pipe_blit_info *info)
+{
+struct vc5_context *vc5 = vc5_context(ctx);
+struct vc5_resource *src = vc5_resource(info->src.resource);
+struct vc5_resource *dst = vc5_resource(info->dst.resource);
+enum pipe_format src_format, dst_format;
+
+if (src->separate_stencil) {
+src = src->separate_stencil;
+src_format = PIPE_FORMAT_R8_UNORM;
+} else {
+src_format = PIPE_FORMAT_RGBA_UNORM;
+}
+
+if (dst->separate_stencil) {
+dst = dst->separate_stencil;
+dst_format = PIPE_FORMAT_R8_UNORM;
+} else {
+dst_format = PIPE_FORMAT_RGBA_UNORM;
+}
+
+/* Initialize the surface. */
+struct pipe_surface dst_tmpl = {
+.u.tex = {
+.level = info->dst.level,
+.first_layer = info->dst.box.z,
+.last_layer = info->dst.box.z,
+},
+.format = dst_format,
+};
+struct pipe_surface *dst_surf =
+ctx->create_surface(ctx, >base, _tmpl);
+
+/* Initialize the sampler view. */
+struct pipe_sampler_view src_tmpl = {
+.target = src->base.target,
+.format = src_format,
+.u.tex = {
+.first_level = info->src.level,
+.last_level = info->src.level,
+.first_layer = 0,
+.last_layer = (PIPE_TEXTURE_3D ?
+ u_minify(src->base.depth0,
+info->src.level) - 1 :
+ src->base.array_size - 1),
+},
+.swizzle_r = PIPE_SWIZZLE_X,
+.swizzle_g = PIPE_SWIZZLE_Y,
+.swizzle_b = PIPE_SWIZZLE_Z,
+.swizzle_a = PIPE_SWIZZLE_W,
+};
+struct pipe_sampler_view *src_view =
+ctx->create_sampler_view(ctx, >base, _tmpl);
+
+vc5_blitter_save(vc5);
+util_blitter_blit_generic(vc5->blitter, dst_surf, >dst.box,
+ src_view, >src.box,
+ src->base.width0, src->base.height0,
+ PIPE_MASK_R,
+ PIPE_TEX_FILTER_NEAREST,
+ info->scissor_enable ? >scissor : NULL,
+ info->alpha_blend);
+
+pipe_surface_reference(_surf, NULL);
+pipe_sampler_view_reference(_view, NULL);
+}
+
/* Optimal hardware path for blitting pixels.
* Scaling, format conversion, up- and downsampling (resolve) are allowed.
*/
@@ -217,6 +288,11 @@ vc5_blit(struct pipe_context *pctx, const struct
pipe_blit_info *blit_info)
{
struct pipe_blit_info info = *blit_info;
+if (info.mask & PIPE_MASK_S) {
+vc5_stencil_blit(pctx, blit_info);
+info.mask &= ~PIPE_MASK_S;
+}
+
#if 0
if (vc5_tile_blit(pctx, blit_info))
return;
diff --git a/src/gallium/drivers/vc5/vc5_state.c
b/src/gallium/drivers/vc5/vc5_state.c
index ba2d748ba9..350bd6a4ed 100644
--- a/src/gallium/drivers/vc5/vc5_state.c
+++ b/src/gallium/drivers/vc5/vc5_state.c
@@ -760,9 +760,14 @@ vc5_create_sampler_view(struct pipe_context *pctx, struct
pipe_resource *prsc,
* ARB_texture_view spec, but in HW we lay them out as
* 32bpp RGBA8 and 64bpp RGBA16F. Just assert for now
* to catch failures.
+ *
+ * We explicitly allow remapping S8Z24 to RGBA for
+ * vc5_blit.c's stencil bli
Mesa (master): broadcom/vc5: Set up internal_format for imported resources.
Module: Mesa Branch: master Commit: 3d21fc193efc3ccca1e442d4f9409cd93eb04282 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d21fc193efc3ccca1e442d4f9409cd93eb04282 Author: Eric Anholt <e...@anholt.net> Date: Thu Apr 12 16:29:19 2018 -0700 broadcom/vc5: Set up internal_format for imported resources. Without this, we'd assertion fail in u_transfer_helper when mapping an imported resource. --- src/gallium/drivers/vc5/vc5_resource.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/gallium/drivers/vc5/vc5_resource.c b/src/gallium/drivers/vc5/vc5_resource.c index 9c714b4183..eb5fa4e908 100644 --- a/src/gallium/drivers/vc5/vc5_resource.c +++ b/src/gallium/drivers/vc5/vc5_resource.c @@ -731,6 +731,8 @@ vc5_resource_from_handle(struct pipe_screen *pscreen, if (!rsc->bo) goto fail; +rsc->internal_format = prsc->format; + vc5_setup_slices(rsc); vc5_debug_resource_layout(rsc, "import"); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): broadcom/vc5: Treat imports of DRM_FORMAT_MOD_INVALID BOs as linear.
Module: Mesa
Branch: master
Commit: 3cdd055ed24d97ff79221ac427102a58b9b28d6c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3cdd055ed24d97ff79221ac427102a58b9b28d6c
Author: Eric Anholt <e...@anholt.net>
Date: Thu Apr 12 13:46:24 2018 -0700
broadcom/vc5: Treat imports of DRM_FORMAT_MOD_INVALID BOs as linear.
We don't have any kernel metadata about BO tiling, so this probably is all
we should do for the moment.
---
src/gallium/drivers/vc5/vc5_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/vc5/vc5_resource.c
b/src/gallium/drivers/vc5/vc5_resource.c
index c8c99cf487..9c714b4183 100644
--- a/src/gallium/drivers/vc5/vc5_resource.c
+++ b/src/gallium/drivers/vc5/vc5_resource.c
@@ -694,6 +694,7 @@ vc5_resource_from_handle(struct pipe_screen *pscreen,
switch (whandle->modifier) {
case DRM_FORMAT_MOD_LINEAR:
+case DRM_FORMAT_MOD_INVALID:
rsc->tiled = false;
break;
/* XXX: UIF */
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Mesa (master): broadcom/vc5: Don't allocate simulator BOs at offset 0.
Module: Mesa Branch: master Commit: 482f2e24b59086bcc1515663167744c707d1c82c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=482f2e24b59086bcc1515663167744c707d1c82c Author: Eric Anholt <e...@anholt.net> Date: Thu Apr 12 15:19:42 2018 -0700 broadcom/vc5: Don't allocate simulator BOs at offset 0. The kernel won't return us BOs at offset 0 (because things like OQs wouldn't work there), so we shouldn't in the simulator either. --- src/gallium/drivers/vc5/vc5_simulator.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/vc5/vc5_simulator.c b/src/gallium/drivers/vc5/vc5_simulator.c index ee4ffb28c0..5fbcad346a 100644 --- a/src/gallium/drivers/vc5/vc5_simulator.c +++ b/src/gallium/drivers/vc5/vc5_simulator.c @@ -594,7 +594,11 @@ vc5_simulator_init_global(const struct v3d_device_info *devinfo) v3d_hw_get_mem(sim_state.v3d, _state.mem_size, _state.mem); -sim_state.heap = u_mmInit(0, sim_state.mem_size); +/* Allocate from anywhere from 4096 up. We don't allocate at 0, + * because for OQs and some other addresses in the HW, 0 means + * disabled. + */ +sim_state.heap = u_mmInit(4096, sim_state.mem_size - 4096); /* Make a block of 0xd0 at address 0 to make sure we don't screw up * and land there. ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): broadcom/vc5: Assert that created BOs have offset != 0.
Module: Mesa Branch: master Commit: f08f477a93e783361d2942133da18504c2851469 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f08f477a93e783361d2942133da18504c2851469 Author: Eric Anholt <e...@anholt.net> Date: Thu Apr 12 15:20:17 2018 -0700 broadcom/vc5: Assert that created BOs have offset != 0. The kernel shouldn't return a bo at NULL, and the HW special-cases NULL address values for things like OQs. --- src/gallium/drivers/vc5/vc5_bufmgr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/vc5/vc5_bufmgr.c b/src/gallium/drivers/vc5/vc5_bufmgr.c index 1b91fbbdae..ef6995e4de 100644 --- a/src/gallium/drivers/vc5/vc5_bufmgr.c +++ b/src/gallium/drivers/vc5/vc5_bufmgr.c @@ -366,6 +366,7 @@ vc5_bo_open_handle(struct vc5_screen *screen, return NULL; } bo->offset = get.offset; +assert(bo->offset != 0); util_hash_table_set(screen->bo_handles, (void *)(uintptr_t)handle, bo); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): broadcom/vc5: Add sim support for the GET_BO_OFFSET ioctl.
Module: Mesa
Branch: master
Commit: 82cdb801fda294465aadcdd5dde426a1fa02ffd2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=82cdb801fda294465aadcdd5dde426a1fa02ffd2
Author: Eric Anholt <e...@anholt.net>
Date: Thu Apr 12 13:47:52 2018 -0700
broadcom/vc5: Add sim support for the GET_BO_OFFSET ioctl.
Otherwise we'd crash immediately upon importing a BO through EGL
interfaces.
---
src/gallium/drivers/vc5/vc5_bufmgr.c| 13 +++--
src/gallium/drivers/vc5/vc5_simulator.c | 14 ++
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_bufmgr.c
b/src/gallium/drivers/vc5/vc5_bufmgr.c
index 7a9c04a268..1b91fbbdae 100644
--- a/src/gallium/drivers/vc5/vc5_bufmgr.c
+++ b/src/gallium/drivers/vc5/vc5_bufmgr.c
@@ -348,6 +348,12 @@ vc5_bo_open_handle(struct vc5_screen *screen,
bo->name = "winsys";
bo->private = false;
+#ifdef USE_VC5_SIMULATOR
+vc5_simulator_open_from_handle(screen->fd, winsys_stride,
+ bo->handle, bo->size);
+bo->map = malloc(bo->size);
+#endif
+
struct drm_vc5_get_bo_offset get = {
.handle = handle,
};
@@ -355,17 +361,12 @@ vc5_bo_open_handle(struct vc5_screen *screen,
if (ret) {
fprintf(stderr, "Failed to get BO offset: %s\n",
strerror(errno));
+free(bo->map);
free(bo);
return NULL;
}
bo->offset = get.offset;
-#ifdef USE_VC5_SIMULATOR
-vc5_simulator_open_from_handle(screen->fd, winsys_stride,
- bo->handle, bo->size);
-bo->map = malloc(bo->size);
-#endif
-
util_hash_table_set(screen->bo_handles, (void *)(uintptr_t)handle, bo);
done:
diff --git a/src/gallium/drivers/vc5/vc5_simulator.c
b/src/gallium/drivers/vc5/vc5_simulator.c
index d677293f3e..ee4ffb28c0 100644
--- a/src/gallium/drivers/vc5/vc5_simulator.c
+++ b/src/gallium/drivers/vc5/vc5_simulator.c
@@ -511,6 +511,18 @@ vc5_simulator_mmap_bo_ioctl(int fd, struct drm_vc5_mmap_bo
*args)
}
static int
+vc5_simulator_get_bo_offset_ioctl(int fd, struct drm_vc5_get_bo_offset *args)
+{
+struct vc5_simulator_file *file = vc5_get_simulator_file_for_fd(fd);
+struct vc5_simulator_bo *sim_bo = vc5_get_simulator_bo(file,
+ args->handle);
+
+args->offset = sim_bo->block->ofs;
+
+return 0;
+}
+
+static int
vc5_simulator_gem_close_ioctl(int fd, struct drm_gem_close *args)
{
/* Free the simulator's internal tracking. */
@@ -541,6 +553,8 @@ vc5_simulator_ioctl(int fd, unsigned long request, void
*args)
return vc5_simulator_create_bo_ioctl(fd, args);
case DRM_IOCTL_VC5_MMAP_BO:
return vc5_simulator_mmap_bo_ioctl(fd, args);
+case DRM_IOCTL_VC5_GET_BO_OFFSET:
+return vc5_simulator_get_bo_offset_ioctl(fd, args);
case DRM_IOCTL_VC5_WAIT_BO:
/* We do all of the vc5 rendering synchronously, so we just
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Mesa (master): broadcom/vc5: Update the UABI for in/out syncobjs
Module: Mesa
Branch: master
Commit: b225cdceccb225329298763baa302a9332288b18
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b225cdceccb225329298763baa302a9332288b18
Author: Eric Anholt <e...@anholt.net>
Date: Wed Apr 4 09:59:18 2018 -0700
broadcom/vc5: Update the UABI for in/out syncobjs
This is the ABI I'm hoping to stabilize for merging the driver. seqnos
are eliminated, which allows for the GPU scheduler to task-switch between
DRM fds even after submission to the kernel. In/out sync objects are
introduced, to allow the Android fencing extension (not yet implemented,
but should be trivial), and to also allow the driver to tell the kernel to
not start a bin until a previous render is complete.
---
src/gallium/drivers/vc5/v3dx_simulator.c | 2 +-
src/gallium/drivers/vc5/vc5_bufmgr.c | 38
src/gallium/drivers/vc5/vc5_context.c| 10 --
src/gallium/drivers/vc5/vc5_context.h| 6 ++--
src/gallium/drivers/vc5/vc5_drm.h| 61 +---
src/gallium/drivers/vc5/vc5_fence.c | 23
src/gallium/drivers/vc5/vc5_job.c| 1 +
src/gallium/drivers/vc5/vc5_screen.h | 3 --
src/gallium/drivers/vc5/vc5_simulator.c | 1 -
9 files changed, 55 insertions(+), 90 deletions(-)
diff --git a/src/gallium/drivers/vc5/v3dx_simulator.c
b/src/gallium/drivers/vc5/v3dx_simulator.c
index aed4aab204..90fafaee1e 100644
--- a/src/gallium/drivers/vc5/v3dx_simulator.c
+++ b/src/gallium/drivers/vc5/v3dx_simulator.c
@@ -103,7 +103,7 @@ v3dX(simulator_get_param_ioctl)(struct v3d_hw *v3d,
struct drm_vc5_get_param *args)
{
static const uint32_t reg_map[] = {
-[DRM_VC5_PARAM_V3D_HUB_UIFCFG] = V3D_HUB_CTL_UIFCFG,
+[DRM_VC5_PARAM_V3D_UIFCFG] = V3D_HUB_CTL_UIFCFG,
[DRM_VC5_PARAM_V3D_HUB_IDENT1] = V3D_HUB_CTL_IDENT1,
[DRM_VC5_PARAM_V3D_HUB_IDENT2] = V3D_HUB_CTL_IDENT2,
[DRM_VC5_PARAM_V3D_HUB_IDENT3] = V3D_HUB_CTL_IDENT3,
diff --git a/src/gallium/drivers/vc5/vc5_bufmgr.c
b/src/gallium/drivers/vc5/vc5_bufmgr.c
index bced512ae0..7a9c04a268 100644
--- a/src/gallium/drivers/vc5/vc5_bufmgr.c
+++ b/src/gallium/drivers/vc5/vc5_bufmgr.c
@@ -451,44 +451,6 @@ vc5_bo_flink(struct vc5_bo *bo, uint32_t *name)
return true;
}
-static int vc5_wait_seqno_ioctl(int fd, uint64_t seqno, uint64_t timeout_ns)
-{
-struct drm_vc5_wait_seqno wait = {
-.seqno = seqno,
-.timeout_ns = timeout_ns,
-};
-int ret = vc5_ioctl(fd, DRM_IOCTL_VC5_WAIT_SEQNO, );
-if (ret == -1)
-return -errno;
-else
-return 0;
-
-}
-
-bool
-vc5_wait_seqno(struct vc5_screen *screen, uint64_t seqno, uint64_t timeout_ns,
- const char *reason)
-{
-if (unlikely(V3D_DEBUG & V3D_DEBUG_PERF) && timeout_ns && reason) {
-if (vc5_wait_seqno_ioctl(screen->fd, seqno, 0) == -ETIME) {
-fprintf(stderr, "Blocking on seqno %lld for %s\n",
-(long long)seqno, reason);
-}
-}
-
-int ret = vc5_wait_seqno_ioctl(screen->fd, seqno, timeout_ns);
-if (ret) {
-if (ret != -ETIME) {
-fprintf(stderr, "wait failed: %d\n", ret);
-abort();
-}
-
-return false;
-}
-
-return true;
-}
-
static int vc5_wait_bo_ioctl(int fd, uint32_t handle, uint64_t timeout_ns)
{
struct drm_vc5_wait_bo wait = {
diff --git a/src/gallium/drivers/vc5/vc5_context.c
b/src/gallium/drivers/vc5/vc5_context.c
index 9403f8ffdd..b6d1234879 100644
--- a/src/gallium/drivers/vc5/vc5_context.c
+++ b/src/gallium/drivers/vc5/vc5_context.c
@@ -60,8 +60,7 @@ vc5_pipe_flush(struct pipe_context *pctx, struct
pipe_fence_handle **fence,
if (fence) {
struct pipe_screen *screen = pctx->screen;
-struct vc5_fence *f = vc5_fence_create(vc5->screen,
- vc5->last_emit_seqno);
+struct vc5_fence *f = vc5_fence_create(vc5);
screen->fence_reference(screen, fence, NULL);
*fence = (struct pipe_fence_handle *)f;
}
@@ -128,6 +127,13 @@ vc5_context_create(struct pipe_screen *pscreen, void
*priv, unsigned flags)
vc5->screen = screen;
+int ret = drmSyncobjCreate(screen->fd, DRM_SYNCOBJ_CREATE_SIGNALED,
+ >out_sync);
+if (ret) {
+ralloc_free(vc5);
+return NULL;
+}
+
pctx->screen = pscreen;
pctx->priv = priv;
pctx->destroy = vc5_context_destroy;
diff --git a/src/gallium/drivers/vc5/vc5_context.h
b/src/gallium/drivers/v
Mesa (master): broadcom/vc5: Refactor the implicit coords/stores_pending logic.
Module: Mesa
Branch: master
Commit: b946218c4894bd30d8e31b27afff4ea592d0812b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b946218c4894bd30d8e31b27afff4ea592d0812b
Author: Eric Anholt <e...@anholt.net>
Date: Fri Mar 30 16:43:51 2018 -0700
broadcom/vc5: Refactor the implicit coords/stores_pending logic.
Since I just fixed a bug due to forgetting to do these right, do it once
in the helper func.
---
src/gallium/drivers/vc5/vc5_rcl.c | 36 +---
1 file changed, 13 insertions(+), 23 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_rcl.c
b/src/gallium/drivers/vc5/vc5_rcl.c
index 5ffdfd9ca3..0f9f7fb1b1 100644
--- a/src/gallium/drivers/vc5/vc5_rcl.c
+++ b/src/gallium/drivers/vc5/vc5_rcl.c
@@ -83,7 +83,7 @@ load_general(struct vc5_cl *cl, struct pipe_surface *psurf,
int buffer)
static void
store_general(struct vc5_job *job,
struct vc5_cl *cl, struct pipe_surface *psurf, int buffer,
- int pipe_bit, bool last_store, bool general_color_clear)
+ int pipe_bit, uint32_t *stores_pending, bool general_color_clear)
{
struct vc5_surface *surf = vc5_surface(psurf);
bool separate_stencil = surf->separate_stencil && buffer == STENCIL;
@@ -92,6 +92,9 @@ store_general(struct vc5_job *job,
surf = vc5_surface(psurf);
}
+*stores_pending &= ~pipe_bit;
+bool last_store = !(*stores_pending);
+
struct vc5_resource *rsc = vc5_resource(psurf->texture);
rsc->writes++;
@@ -146,6 +149,11 @@ store_general(struct vc5_job *job,
surf->padded_height_of_output_image_in_uif_blocks;
#endif /* V3D_VERSION < 40 */
}
+
+/* There must be a TILE_COORDINATES_IMPLICIT between each store. */
+if (V3D_VERSION < 40 && !last_store) {
+cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
+}
}
static int
@@ -282,11 +290,8 @@ vc5_rcl_emit_stores(struct vc5_job *job, struct vc5_cl *cl)
continue;
}
-stores_pending &= ~bit;
store_general(job, cl, psurf, RENDER_TARGET_0 + i, bit,
- !stores_pending, general_color_clear);
-if (V3D_VERSION < 40 && stores_pending)
-cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
+ _pending, general_color_clear);
}
if (job->resolve & PIPE_CLEAR_DEPTHSTENCIL && job->zsbuf &&
@@ -294,38 +299,23 @@ vc5_rcl_emit_stores(struct vc5_job *job, struct vc5_cl
*cl)
struct vc5_resource *rsc = vc5_resource(job->zsbuf->texture);
if (rsc->separate_stencil) {
if (job->resolve & PIPE_CLEAR_DEPTH) {
-stores_pending &= ~PIPE_CLEAR_DEPTH;
store_general(job, cl, job->zsbuf, Z,
PIPE_CLEAR_DEPTH,
- !stores_pending,
+ _pending,
general_color_clear);
-if (V3D_VERSION < 40 && stores_pending) {
-cl_emit(cl, TILE_COORDINATES_IMPLICIT,
-coords);
-}
}
if (job->resolve & PIPE_CLEAR_STENCIL) {
-stores_pending &= ~PIPE_CLEAR_STENCIL;
store_general(job, cl, job->zsbuf, STENCIL,
PIPE_CLEAR_STENCIL,
- !stores_pending,
+ _pending,
general_color_clear);
-if (V3D_VERSION < 40 && stores_pending) {
-cl_emit(cl, TILE_COORDINATES_IMPLICIT,
-coords);
-}
}
} else {
-stores_pending &= ~PIPE_CLEAR_DEPTHSTENCIL;
store_general(job, cl, job->zsbuf,
zs_buffer_from_pipe_bits(job->resolve),
job->resolve & PIPE_CLEAR_DEPTHSTENCIL,
- !stores_pending, general_color_clear);
-if (V3D_VERSION < 40 && stores_pending) {
-cl_emit(cl, TILE_COORDINATES_IMPLICIT,
-coords);
-
Mesa (master): broadcom/vc5: Fix a stray '`' in a comment.
Module: Mesa
Branch: master
Commit: 7bc77dbb00a1032f79620751b934929eb0b25c66
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7bc77dbb00a1032f79620751b934929eb0b25c66
Author: Eric Anholt <e...@anholt.net>
Date: Wed Apr 11 16:28:07 2018 -0700
broadcom/vc5: Fix a stray '`' in a comment.
---
src/gallium/drivers/vc5/vc5_job.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/vc5/vc5_job.c
b/src/gallium/drivers/vc5/vc5_job.c
index 12dd75766a..9947fb47ff 100644
--- a/src/gallium/drivers/vc5/vc5_job.c
+++ b/src/gallium/drivers/vc5/vc5_job.c
@@ -394,7 +394,7 @@ vc5_job_submit(struct vc5_context *vc5, struct vc5_job *job)
job->submit.rcl_end = job->rcl.bo->offset + cl_offset(>rcl);
/* On V3D 4.1, the tile alloc/state setup moved to register writes
- * instead of binner pac`kets.
+ * instead of binner packets.
*/
if (screen->devinfo.ver >= 41) {
vc5_job_add_bo(job, job->tile_alloc);
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Mesa (master): broadcom/vc5: Rename read_but_not_cleared to loads_pending.
Module: Mesa
Branch: master
Commit: 6a21a582fba74e3566f7b240702c19cbe2559a06
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a21a582fba74e3566f7b240702c19cbe2559a06
Author: Eric Anholt <e...@anholt.net>
Date: Fri Mar 30 16:53:39 2018 -0700
broadcom/vc5: Rename read_but_not_cleared to loads_pending.
This is a more obvious name for what the variable means, and matches what
it's called for stores.
---
src/gallium/drivers/vc5/vc5_rcl.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_rcl.c
b/src/gallium/drivers/vc5/vc5_rcl.c
index 0f9f7fb1b1..cd43e9d546 100644
--- a/src/gallium/drivers/vc5/vc5_rcl.c
+++ b/src/gallium/drivers/vc5/vc5_rcl.c
@@ -191,11 +191,11 @@ flush_last_load(struct vc5_cl *cl)
static void
vc5_rcl_emit_loads(struct vc5_job *job, struct vc5_cl *cl)
{
-uint32_t read_but_not_cleared = job->resolve & ~job->cleared;
+uint32_t loads_pending = job->resolve & ~job->cleared;
for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
uint32_t bit = PIPE_CLEAR_COLOR0 << i;
-if (!(read_but_not_cleared & bit))
+if (!(loads_pending & bit))
continue;
struct pipe_surface *psurf = job->cbufs[i];
@@ -205,19 +205,19 @@ vc5_rcl_emit_loads(struct vc5_job *job, struct vc5_cl *cl)
}
load_general(cl, psurf, RENDER_TARGET_0 + i);
-read_but_not_cleared &= ~bit;
+loads_pending &= ~bit;
-if (read_but_not_cleared)
+if (loads_pending)
flush_last_load(cl);
}
-if (read_but_not_cleared & PIPE_CLEAR_DEPTHSTENCIL &&
+if (loads_pending & PIPE_CLEAR_DEPTHSTENCIL &&
(V3D_VERSION >= 40 ||
(job->zsbuf && job->zsbuf->texture->nr_samples > 1))) {
load_general(cl, job->zsbuf,
- zs_buffer_from_pipe_bits(read_but_not_cleared));
-read_but_not_cleared &= ~PIPE_CLEAR_DEPTHSTENCIL;
-if (read_but_not_cleared)
+ zs_buffer_from_pipe_bits(loads_pending));
+loads_pending &= ~PIPE_CLEAR_DEPTHSTENCIL;
+if (loads_pending)
cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
}
@@ -225,20 +225,20 @@ vc5_rcl_emit_loads(struct vc5_job *job, struct vc5_cl *cl)
/* The initial reload will be queued until we get the
* tile coordinates.
*/
-if (read_but_not_cleared) {
+if (loads_pending) {
cl_emit(cl, RELOAD_TILE_COLOUR_BUFFER, load) {
load.disable_colour_buffer_load =
-(~read_but_not_cleared &
+(~loads_pending &
PIPE_CLEAR_COLOR_BUFFERS) >>
PIPE_FIRST_COLOR_BUFFER_BIT;
load.enable_z_load =
-read_but_not_cleared & PIPE_CLEAR_DEPTH;
+loads_pending & PIPE_CLEAR_DEPTH;
load.enable_stencil_load =
-read_but_not_cleared & PIPE_CLEAR_STENCIL;
+loads_pending & PIPE_CLEAR_STENCIL;
}
}
#else /* V3D_VERSION >= 40 */
-assert(!read_but_not_cleared);
+assert(!loads_pending);
cl_emit(cl, END_OF_LOADS, end);
#endif
}
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Mesa (master): broadcom/vc5: Fix MSAA depth/stencil size setup.
Module: Mesa
Branch: master
Commit: 7553cbfc9d78f0a4f8816122ce6327bc3899c2b5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7553cbfc9d78f0a4f8816122ce6327bc3899c2b5
Author: Eric Anholt <e...@anholt.net>
Date: Fri Mar 30 16:14:29 2018 -0700
broadcom/vc5: Fix MSAA depth/stencil size setup.
The v3dX(get_internal_type_bpp_for_output_format)() call only handles
color output formats (which overlap in enum numbers with depth output
formats), so for depth we just need to take the normal cpp times the
number of samples.
---
src/gallium/drivers/vc5/vc5_resource.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_resource.c
b/src/gallium/drivers/vc5/vc5_resource.c
index 321a14b904..c8c99cf487 100644
--- a/src/gallium/drivers/vc5/vc5_resource.c
+++ b/src/gallium/drivers/vc5/vc5_resource.c
@@ -565,8 +565,10 @@ vc5_resource_setup(struct pipe_screen *pscreen,
pipe_reference_init(>reference, 1);
prsc->screen = pscreen;
-if (prsc->nr_samples <= 1) {
-rsc->cpp = util_format_get_blocksize(prsc->format);
+if (prsc->nr_samples <= 1 ||
+util_format_is_depth_or_stencil(prsc->format)) {
+rsc->cpp = util_format_get_blocksize(prsc->format) *
+MAX2(prsc->nr_samples, 1);
} else {
assert(vc5_rt_format_supported(>devinfo,
prsc->format));
uint32_t output_image_format =
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Mesa (master): broadcom/vc5: Drop the finished_seqno optimization.
Module: Mesa
Branch: master
Commit: d9c525ed2240ff450f36a5d83c9c2c66087cd2bb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d9c525ed2240ff450f36a5d83c9c2c66087cd2bb
Author: Eric Anholt <e...@anholt.net>
Date: Wed Apr 4 09:58:23 2018 -0700
broadcom/vc5: Drop the finished_seqno optimization.
With the DRM scheduler changes, I'm about to remove all seqnos from the
UABI.
---
src/gallium/drivers/vc5/vc5_bufmgr.c | 4
src/gallium/drivers/vc5/vc5_screen.h | 7 ---
2 files changed, 11 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_bufmgr.c
b/src/gallium/drivers/vc5/vc5_bufmgr.c
index 5e068400fd..bced512ae0 100644
--- a/src/gallium/drivers/vc5/vc5_bufmgr.c
+++ b/src/gallium/drivers/vc5/vc5_bufmgr.c
@@ -469,9 +469,6 @@ bool
vc5_wait_seqno(struct vc5_screen *screen, uint64_t seqno, uint64_t timeout_ns,
const char *reason)
{
-if (screen->finished_seqno >= seqno)
-return true;
-
if (unlikely(V3D_DEBUG & V3D_DEBUG_PERF) && timeout_ns && reason) {
if (vc5_wait_seqno_ioctl(screen->fd, seqno, 0) == -ETIME) {
fprintf(stderr, "Blocking on seqno %lld for %s\n",
@@ -489,7 +486,6 @@ vc5_wait_seqno(struct vc5_screen *screen, uint64_t seqno,
uint64_t timeout_ns,
return false;
}
-screen->finished_seqno = seqno;
return true;
}
diff --git a/src/gallium/drivers/vc5/vc5_screen.h
b/src/gallium/drivers/vc5/vc5_screen.h
index 710396de99..05a770ba2a 100644
--- a/src/gallium/drivers/vc5/vc5_screen.h
+++ b/src/gallium/drivers/vc5/vc5_screen.h
@@ -61,13 +61,6 @@ struct vc5_screen {
const char *name;
-/** The last seqno we've completed a wait for.
- *
- * This lets us slightly optimize our waits by skipping wait syscalls
- * if we know the job's already done.
- */
-uint64_t finished_seqno;
-
struct slab_parent_pool transfer_pool;
struct vc5_bo_cache {
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Mesa (master): broadcom/vc5: Drop the throttling code.
Module: Mesa
Branch: master
Commit: aedfd8ede4c2e0ecad0a3796796b2f0610482ced
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aedfd8ede4c2e0ecad0a3796796b2f0610482ced
Author: Eric Anholt <e...@anholt.net>
Date: Wed Apr 4 09:57:51 2018 -0700
broadcom/vc5: Drop the throttling code.
Since I'll be using the DRM scheduler, we won't run into the problem of a
runaway client starving other clients of GPU time.
---
src/gallium/drivers/vc5/vc5_job.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_job.c
b/src/gallium/drivers/vc5/vc5_job.c
index 0d0405bf66..3f70539a1f 100644
--- a/src/gallium/drivers/vc5/vc5_job.c
+++ b/src/gallium/drivers/vc5/vc5_job.c
@@ -422,15 +422,6 @@ vc5_job_submit(struct vc5_context *vc5, struct vc5_job
*job)
}
}
-if (vc5->last_emit_seqno - vc5->screen->finished_seqno > 5) {
-if (!vc5_wait_seqno(vc5->screen,
-vc5->last_emit_seqno - 5,
-PIPE_TIMEOUT_INFINITE,
-"job throttling")) {
-fprintf(stderr, "Job throttling failed\n");
-}
-}
-
done:
vc5_job_free(vc5, job);
}
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Mesa (master): broadcom/vc5: Emit missing TILE_COORDINATES_IMPLICIT in separate z/s stores.
Module: Mesa
Branch: master
Commit: ec60559f97dc13d85fb197e2dd99827e12fff371
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec60559f97dc13d85fb197e2dd99827e12fff371
Author: Eric Anholt <e...@anholt.net>
Date: Fri Mar 30 16:39:14 2018 -0700
broadcom/vc5: Emit missing TILE_COORDINATES_IMPLICIT in separate z/s stores.
Fixes a simulator assertion failure in
KHR-GLES3.packed_depth_stencil.blit.depth32f_stencil8
---
src/gallium/drivers/vc5/vc5_rcl.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_rcl.c
b/src/gallium/drivers/vc5/vc5_rcl.c
index 83593a86d2..5ffdfd9ca3 100644
--- a/src/gallium/drivers/vc5/vc5_rcl.c
+++ b/src/gallium/drivers/vc5/vc5_rcl.c
@@ -291,31 +291,42 @@ vc5_rcl_emit_stores(struct vc5_job *job, struct vc5_cl
*cl)
if (job->resolve & PIPE_CLEAR_DEPTHSTENCIL && job->zsbuf &&
!(V3D_VERSION < 40 && job->zsbuf->texture->nr_samples <= 1)) {
-stores_pending &= ~PIPE_CLEAR_DEPTHSTENCIL;
-
struct vc5_resource *rsc = vc5_resource(job->zsbuf->texture);
if (rsc->separate_stencil) {
if (job->resolve & PIPE_CLEAR_DEPTH) {
+stores_pending &= ~PIPE_CLEAR_DEPTH;
store_general(job, cl, job->zsbuf, Z,
PIPE_CLEAR_DEPTH,
!stores_pending,
general_color_clear);
+if (V3D_VERSION < 40 && stores_pending) {
+cl_emit(cl, TILE_COORDINATES_IMPLICIT,
+coords);
+}
}
+
if (job->resolve & PIPE_CLEAR_STENCIL) {
+stores_pending &= ~PIPE_CLEAR_STENCIL;
store_general(job, cl, job->zsbuf, STENCIL,
PIPE_CLEAR_STENCIL,
!stores_pending,
general_color_clear);
+if (V3D_VERSION < 40 && stores_pending) {
+cl_emit(cl, TILE_COORDINATES_IMPLICIT,
+coords);
+}
}
} else {
+stores_pending &= ~PIPE_CLEAR_DEPTHSTENCIL;
store_general(job, cl, job->zsbuf,
zs_buffer_from_pipe_bits(job->resolve),
job->resolve & PIPE_CLEAR_DEPTHSTENCIL,
!stores_pending, general_color_clear);
+if (V3D_VERSION < 40 && stores_pending) {
+cl_emit(cl, TILE_COORDINATES_IMPLICIT,
+coords);
+}
}
-
-if (V3D_VERSION < 40 && stores_pending)
-cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
}
if (stores_pending) {
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Mesa (master): broadcom/vc5: Add checks that we don't try to do raw Z+S load/stores.
Module: Mesa
Branch: master
Commit: 8f2999120de83845b1c0098170356819c5a6e439
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f2999120de83845b1c0098170356819c5a6e439
Author: Eric Anholt <e...@anholt.net>
Date: Fri Mar 30 16:31:07 2018 -0700
broadcom/vc5: Add checks that we don't try to do raw Z+S load/stores.
This was dying in the simulator on
GTF-GLES3.gtf.GL3Tests.packed_depth_stencil.packed_depth_stencil_blit.
We'll need to do basically the same thing as Z32F/S8 does in the MSAA
Z24S8 case.
---
src/gallium/drivers/vc5/vc5_rcl.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/gallium/drivers/vc5/vc5_rcl.c
b/src/gallium/drivers/vc5/vc5_rcl.c
index 8ff1515f88..83593a86d2 100644
--- a/src/gallium/drivers/vc5/vc5_rcl.c
+++ b/src/gallium/drivers/vc5/vc5_rcl.c
@@ -69,6 +69,10 @@ load_general(struct vc5_cl *cl, struct pipe_surface *psurf,
int buffer)
/* XXX: MSAA */
#else /* V3D_VERSION < 40 */
+/* Can't do raw ZSTENCIL loads -- need to load/store them to
+ * separate buffers for Z and stencil.
+ */
+assert(buffer != ZSTENCIL);
load.raw_mode = true;
load.padded_height_of_output_image_in_uif_blocks =
surf->padded_height_of_output_image_in_uif_blocks;
@@ -119,6 +123,10 @@ store_general(struct vc5_job *job,
store.height_in_ub_or_stride = slice->stride;
}
#else /* V3D_VERSION < 40 */
+/* Can't do raw ZSTENCIL stores -- need to load/store them to
+ * separate buffers for Z and stencil.
+ */
+assert(buffer != ZSTENCIL);
store.raw_mode = true;
if (!last_store) {
store.disable_colour_buffers_clear_on_write = true;
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Mesa (master): broadcom/vc5: Move flush_last_load into load_general, like for stores.
Module: Mesa
Branch: master
Commit: dd9c476165bd4d76c5aec8f7320b7ed9d961ac7c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd9c476165bd4d76c5aec8f7320b7ed9d961ac7c
Author: Eric Anholt <e...@anholt.net>
Date: Fri Mar 30 16:50:23 2018 -0700
broadcom/vc5: Move flush_last_load into load_general, like for stores.
This should avoid mistakes with not flushing as we change the series of
loads. Already, it fixes a hopefully unreachable case where we were
emitting just the TILE_COORDINATES and not the dummy store that needs to
go with it.
---
src/gallium/drivers/vc5/vc5_rcl.c | 57 ---
1 file changed, 29 insertions(+), 28 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_rcl.c
b/src/gallium/drivers/vc5/vc5_rcl.c
index cd43e9d546..2b1309bc1a 100644
--- a/src/gallium/drivers/vc5/vc5_rcl.c
+++ b/src/gallium/drivers/vc5/vc5_rcl.c
@@ -34,8 +34,26 @@
#define PIPE_FIRST_COLOR_BUFFER_BIT (ffs(PIPE_CLEAR_COLOR0) - 1)
+/* The HW queues up the load until the tile coordinates show up, but can only
+ * track one at a time. If we need to do more than one load, then we need to
+ * flush out the previous load by emitting the tile coordinates and doing a
+ * dummy store.
+ */
+static void
+flush_last_load(struct vc5_cl *cl)
+{
+if (V3D_VERSION >= 40)
+return;
+
+cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
+cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
+store.buffer_to_store = NONE;
+}
+}
+
static void
-load_general(struct vc5_cl *cl, struct pipe_surface *psurf, int buffer)
+load_general(struct vc5_cl *cl, struct pipe_surface *psurf, int buffer,
+ uint32_t pipe_bit, uint32_t *loads_pending)
{
struct vc5_surface *surf = vc5_surface(psurf);
bool separate_stencil = surf->separate_stencil && buffer == STENCIL;
@@ -78,6 +96,10 @@ load_general(struct vc5_cl *cl, struct pipe_surface *psurf,
int buffer)
surf->padded_height_of_output_image_in_uif_blocks;
#endif /* V3D_VERSION < 40 */
}
+
+*loads_pending &= ~pipe_bit;
+if (*loads_pending)
+flush_last_load(cl);
}
static void
@@ -171,23 +193,6 @@ zs_buffer_from_pipe_bits(int pipe_clear_bits)
}
}
-/* The HW queues up the load until the tile coordinates show up, but can only
- * track one at a time. If we need to do more than one load, then we need to
- * flush out the previous load by emitting the tile coordinates and doing a
- * dummy store.
- */
-static void
-flush_last_load(struct vc5_cl *cl)
-{
-if (V3D_VERSION >= 40)
-return;
-
-cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
-cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
-store.buffer_to_store = NONE;
-}
-}
-
static void
vc5_rcl_emit_loads(struct vc5_job *job, struct vc5_cl *cl)
{
@@ -204,21 +209,17 @@ vc5_rcl_emit_loads(struct vc5_job *job, struct vc5_cl *cl)
continue;
}
-load_general(cl, psurf, RENDER_TARGET_0 + i);
-loads_pending &= ~bit;
-
-if (loads_pending)
-flush_last_load(cl);
+load_general(cl, psurf, RENDER_TARGET_0 + i,
+ bit, _pending);
}
-if (loads_pending & PIPE_CLEAR_DEPTHSTENCIL &&
+if ((loads_pending & PIPE_CLEAR_DEPTHSTENCIL) &&
(V3D_VERSION >= 40 ||
(job->zsbuf && job->zsbuf->texture->nr_samples > 1))) {
load_general(cl, job->zsbuf,
- zs_buffer_from_pipe_bits(loads_pending));
-loads_pending &= ~PIPE_CLEAR_DEPTHSTENCIL;
-if (loads_pending)
-cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
+ zs_buffer_from_pipe_bits(loads_pending),
+ PIPE_CLEAR_DEPTHSTENCIL,
+ _pending);
}
#if V3D_VERSION < 40
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Mesa (master): broadcom/vc5: Stop trying to swizzle around RGBA4 clear color.
Module: Mesa
Branch: master
Commit: 123ee3762722e2703459cc9b966b8cbf64a63769
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=123ee3762722e2703459cc9b966b8cbf64a63769
Author: Eric Anholt <e...@anholt.net>
Date: Tue Mar 27 21:52:35 2018 -0700
broadcom/vc5: Stop trying to swizzle around RGBA4 clear color.
We always want A in the A slot in the tile buffer, and any other swapping
should happen elsewhere.
Fixes RGBA4-using cases in fbo-clear-formats and
GTF-GLES3.gtf.GL3Tests.color_buffer_float.color_buffer_float_clamp_fixed.
---
src/gallium/drivers/vc5/vc5_draw.c | 14 ++
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_draw.c
b/src/gallium/drivers/vc5/vc5_draw.c
index 25f4883be2..841c991d20 100644
--- a/src/gallium/drivers/vc5/vc5_draw.c
+++ b/src/gallium/drivers/vc5/vc5_draw.c
@@ -627,18 +627,8 @@ vc5_clear(struct pipe_context *pctx, unsigned buffers,
switch (surf->internal_type) {
case V3D_INTERNAL_TYPE_8:
-if (surf->format == PIPE_FORMAT_B4G4R4A4_UNORM ||
-surf->format == PIPE_FORMAT_B4G4R4A4_UNORM) {
-/* Our actual hardware layout is ABGR, but
- * we apply a swizzle when texturing to flip
- * things back around.
- */
-util_pack_color(color->f,
PIPE_FORMAT_A8R8G8B8_UNORM,
-);
-} else {
-util_pack_color(color->f,
PIPE_FORMAT_R8G8B8A8_UNORM,
-);
-}
+util_pack_color(color->f, PIPE_FORMAT_R8G8B8A8_UNORM,
+);
memcpy(job->clear_color[i], uc.ui, internal_size);
break;
case V3D_INTERNAL_TYPE_8I:
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Mesa (master): broadcom/vc4: Fix out-of-tree build with automake.
Module: Mesa Branch: master Commit: 1dae92f150b4a4f1d8f847a562353629aa3c6ca5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1dae92f150b4a4f1d8f847a562353629aa3c6ca5 Author: Aaron Watry <awa...@gmail.com> Date: Tue Mar 27 20:26:18 2018 -0500 broadcom/vc4: Fix out-of-tree build with automake. Signed-off-by: Aaron Watry <awa...@gmail.com> Reviewed-by: Eric Anholt <e...@anholt.net> --- src/broadcom/Makefile.am | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/broadcom/Makefile.am b/src/broadcom/Makefile.am index 35ed703a09..49267de73b 100644 --- a/src/broadcom/Makefile.am +++ b/src/broadcom/Makefile.am @@ -24,7 +24,9 @@ AM_CPPFLAGS = \ -I$(top_srcdir)/include \ -I$(top_builddir)/src \ -I$(top_srcdir)/src \ + -I$(top_builddir)/src/compiler/nir \ -I$(top_srcdir)/src/broadcom/ \ + -I$(top_srcdir)/src/broadcom/cle \ -I$(top_srcdir)/src/broadcom/include \ -I$(top_srcdir)/src/gallium/auxiliary \ -I$(top_srcdir)/src/gallium/include \ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): broadcom/vc5: Start using nir_opt_move_load_ubo().
Module: Mesa Branch: master Commit: 81f82ecc56c3ac6f40389977e316381928391755 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=81f82ecc56c3ac6f40389977e316381928391755 Author: Eric Anholt <e...@anholt.net> Date: Wed Mar 28 11:19:35 2018 -0700 broadcom/vc5: Start using nir_opt_move_load_ubo(). In the absence of a general NIR or VIR-level scheduler, this at least avoids spilling in GTF-GLES3.gtf.GL3Tests.uniform_buffer_object.uniform_buffer_object_storage_layouts --- src/broadcom/compiler/nir_to_vir.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/broadcom/compiler/nir_to_vir.c b/src/broadcom/compiler/nir_to_vir.c index 893dfa160a..5171000178 100644 --- a/src/broadcom/compiler/nir_to_vir.c +++ b/src/broadcom/compiler/nir_to_vir.c @@ -1202,6 +1202,8 @@ v3d_optimize_nir(struct nir_shader *s) NIR_PASS(progress, s, nir_opt_constant_folding); NIR_PASS(progress, s, nir_opt_undef); } while (progress); + +NIR_PASS(progress, s, nir_opt_move_load_ubo); } static int ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): st: Don't try to finalize the texture in st_render_texture().
Module: Mesa
Branch: master
Commit: 0349c79bdc2c04b3d64d144159f3268ad74e2b7c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0349c79bdc2c04b3d64d144159f3268ad74e2b7c
Author: Eric Anholt <e...@anholt.net>
Date: Tue Mar 27 15:39:49 2018 -0700
st: Don't try to finalize the texture in st_render_texture().
We can't necessarily finalize the texture at this point if we're rendering
to a texture image whose format is different from the baselevel's format.
This was introduced as a fix for fbo-incomplete-texture-03 in
de414f491526610bb260c73805c81ba413388e20, but the later fix for vmware on
that testcase in 95d5c48f68b598cfa6db25f44aac52b3e11403cc made it
unnecessary.
Fixes assertion failures in util_resource_copy_region() in
KHR-GLES3.copy_tex_image_conversions.forbidden.* when trying to finalize
an R8 texture image to the RG8 texture object's pt.
Reviewed-by: Brian Paul <bri...@vmware.com>
---
src/mesa/state_tracker/st_cb_fbo.c | 4
1 file changed, 4 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_fbo.c
b/src/mesa/state_tracker/st_cb_fbo.c
index 02ae8e1380..f859133e39 100644
--- a/src/mesa/state_tracker/st_cb_fbo.c
+++ b/src/mesa/state_tracker/st_cb_fbo.c
@@ -509,14 +509,10 @@ st_render_texture(struct gl_context *ctx,
struct gl_renderbuffer_attachment *att)
{
struct st_context *st = st_context(ctx);
- struct pipe_context *pipe = st->pipe;
struct gl_renderbuffer *rb = att->Renderbuffer;
struct st_renderbuffer *strb = st_renderbuffer(rb);
struct pipe_resource *pt;
- if (!st_finalize_texture(ctx, pipe, att->Texture, att->CubeMapFace))
- return;
-
pt = get_teximage_resource(att->Texture,
att->CubeMapFace,
att->TextureLevel);
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Mesa (master): broadcom/vc5: Work around scissor w/h==0 bug same as rasterizer discard.
Module: Mesa
Branch: master
Commit: 2f4c4e10c268a8b9a013b422d85439c5933d8075
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f4c4e10c268a8b9a013b422d85439c5933d8075
Author: Eric Anholt <e...@anholt.net>
Date: Tue Mar 27 21:30:42 2018 -0700
broadcom/vc5: Work around scissor w/h==0 bug same as rasterizer discard.
The 7268 HW apparently lets some rendering through in this case. Fixes
GTF-GLES2.gtf.GL2FixedTests.scissor.scissor
---
src/gallium/drivers/vc5/vc5_emit.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_emit.c
b/src/gallium/drivers/vc5/vc5_emit.c
index deb46228da..0d11d7e1ad 100644
--- a/src/gallium/drivers/vc5/vc5_emit.c
+++ b/src/gallium/drivers/vc5/vc5_emit.c
@@ -308,6 +308,7 @@ v3dX(emit_state)(struct pipe_context *pctx)
{
struct vc5_context *vc5 = vc5_context(pctx);
struct vc5_job *job = vc5->job;
+bool rasterizer_discard = vc5->rasterizer->base.rasterizer_discard;
if (vc5->dirty & (VC5_DIRTY_SCISSOR | VC5_DIRTY_VIEWPORT |
VC5_DIRTY_RASTERIZER)) {
@@ -344,6 +345,18 @@ v3dX(emit_state)(struct pipe_context *pctx)
clip.clip_window_bottom_pixel_coordinate = miny;
clip.clip_window_width_in_pixels = maxx - minx;
clip.clip_window_height_in_pixels = maxy - miny;
+
+#if V3D_VERSION < 41
+/* The HW won't entirely clip out when scissor w/h is
+ * 0. Just treat it the same as rasterizer discard.
+ */
+if (clip.clip_window_width_in_pixels == 0 ||
+clip.clip_window_height_in_pixels == 0) {
+rasterizer_discard = true;
+clip.clip_window_width_in_pixels = 1;
+clip.clip_window_height_in_pixels = 1;
+}
+#endif
}
job->draw_min_x = MIN2(job->draw_min_x, minx);
@@ -358,11 +371,11 @@ v3dX(emit_state)(struct pipe_context *pctx)
VC5_DIRTY_COMPILED_FS)) {
cl_emit(>bcl, CONFIGURATION_BITS, config) {
config.enable_forward_facing_primitive =
-!vc5->rasterizer->base.rasterizer_discard &&
+!rasterizer_discard &&
!(vc5->rasterizer->base.cull_face &
PIPE_FACE_FRONT);
config.enable_reverse_facing_primitive =
-!vc5->rasterizer->base.rasterizer_discard &&
+!rasterizer_discard &&
!(vc5->rasterizer->base.cull_face &
PIPE_FACE_BACK);
/* This seems backwards, but it's what gets the
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Mesa (master): broadcom/vc5: Fix setup of integer surface clear values.
Module: Mesa Branch: master Commit: 1fe4c748f743d003fc9052f4a7d0925ab8c5919e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1fe4c748f743d003fc9052f4a7d0925ab8c5919e Author: Eric Anholt <e...@anholt.net> Date: Tue Mar 27 22:02:17 2018 -0700 broadcom/vc5: Fix setup of integer surface clear values. I'm disappointed that the compiler didn't warn me about use of uninitialized uc in these paths. Just use the incoming clear color instead of the packing temporary if we're doing our own packing. Fixes GTF-GLES3.gtf.GL3Tests.color_buffer_float.color_buffer_float_clamp_* --- src/gallium/drivers/vc5/vc5_draw.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/gallium/drivers/vc5/vc5_draw.c b/src/gallium/drivers/vc5/vc5_draw.c index 841c991d20..ff14d1c135 100644 --- a/src/gallium/drivers/vc5/vc5_draw.c +++ b/src/gallium/drivers/vc5/vc5_draw.c @@ -633,10 +633,10 @@ vc5_clear(struct pipe_context *pctx, unsigned buffers, break; case V3D_INTERNAL_TYPE_8I: case V3D_INTERNAL_TYPE_8UI: -job->clear_color[i][0] = ((uc.ui[0] & 0xff) | - (uc.ui[1] & 0xff) << 8 | - (uc.ui[2] & 0xff) << 16 | - (uc.ui[3] & 0xff) << 24); +job->clear_color[i][0] = ((color->ui[0] & 0xff) | + (color->ui[1] & 0xff) << 8 | + (color->ui[2] & 0xff) << 16 | + (color->ui[3] & 0xff) << 24); break; case V3D_INTERNAL_TYPE_16F: util_pack_color(color->f, PIPE_FORMAT_R16G16B16A16_FLOAT, @@ -645,10 +645,10 @@ vc5_clear(struct pipe_context *pctx, unsigned buffers, break; case V3D_INTERNAL_TYPE_16I: case V3D_INTERNAL_TYPE_16UI: -job->clear_color[i][0] = ((uc.ui[0] & 0x) | - uc.ui[1] << 16); -job->clear_color[i][1] = ((uc.ui[2] & 0x) | - uc.ui[3] << 16); +job->clear_color[i][0] = ((color->ui[0] & 0x) | + color->ui[1] << 16); +job->clear_color[i][1] = ((color->ui[2] & 0x) | + color->ui[3] << 16); break; case V3D_INTERNAL_TYPE_32F: case V3D_INTERNAL_TYPE_32I: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): broadcom/vc5: Fix padding of NPOT miplevels >= 2.
Module: Mesa Branch: master Commit: a691fa4a1be3730f0cfc9566944bd23adb03966d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a691fa4a1be3730f0cfc9566944bd23adb03966d Author: Eric Anholt <e...@anholt.net> Date: Tue Mar 27 16:29:10 2018 -0700 broadcom/vc5: Fix padding of NPOT miplevels >= 2. The power-of-two padded size that gets minified is based on level 1's dimensions, not level 0's, which starts to differ at a width of 9. Fixes all failures on texelFetch fs sampler2D 1x1x1-64x64x1 --- src/gallium/drivers/vc5/vc5_resource.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/vc5/vc5_resource.c b/src/gallium/drivers/vc5/vc5_resource.c index 1f0ddb1a29..321a14b904 100644 --- a/src/gallium/drivers/vc5/vc5_resource.c +++ b/src/gallium/drivers/vc5/vc5_resource.c @@ -390,9 +390,14 @@ vc5_setup_slices(struct vc5_resource *rsc) uint32_t width = prsc->width0; uint32_t height = prsc->height0; uint32_t depth = prsc->depth0; -uint32_t pot_width = util_next_power_of_two(width); -uint32_t pot_height = util_next_power_of_two(height); -uint32_t pot_depth = util_next_power_of_two(depth); +/* Note that power-of-two padding is based on level 1. These are not + * equivalent to just util_next_power_of_two(dimension), because at a + * level 0 dimension of 9, the level 1 power-of-two padded value is 4, + * not 8. + */ +uint32_t pot_width = 2 * util_next_power_of_two(u_minify(width, 1)); +uint32_t pot_height = 2 * util_next_power_of_two(u_minify(height, 1)); +uint32_t pot_depth = 2 * util_next_power_of_two(u_minify(depth, 1)); uint32_t offset = 0; uint32_t utile_w = vc5_utile_width(rsc->cpp); uint32_t utile_h = vc5_utile_height(rsc->cpp); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): broadcom/vc5: Fix RG16I/UI texture sampling.
Module: Mesa
Branch: master
Commit: 9f1b4f620464f76c82bcf4b36514f895c59f5c17
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f1b4f620464f76c82bcf4b36514f895c59f5c17
Author: Eric Anholt <e...@anholt.net>
Date: Tue Mar 27 14:26:17 2018 -0700
broadcom/vc5: Fix RG16I/UI texture sampling.
How many times did I look at this table without noticing the missing 'G'
in the texture column?
Fixes KHR-GLES3.copy_tex_image_conversions.required.* on 7268.
---
src/gallium/drivers/vc5/v3dx_format_table.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/vc5/v3dx_format_table.c
b/src/gallium/drivers/vc5/v3dx_format_table.c
index 4aaf0ecd3d..cc356fc381 100644
--- a/src/gallium/drivers/vc5/v3dx_format_table.c
+++ b/src/gallium/drivers/vc5/v3dx_format_table.c
@@ -120,8 +120,8 @@ static const struct vc5_format format_table[] = {
FORMAT(R16_SINT, R16I, R16I,SWIZ_X001, 16, 0),
FORMAT(R16_UINT, R16UI,R16UI, SWIZ_X001, 16, 0),
-FORMAT(R16G16_SINT, RG16I,R16I,SWIZ_XY01, 16, 0),
-FORMAT(R16G16_UINT, RG16UI, R16UI, SWIZ_XY01, 16, 0),
+FORMAT(R16G16_SINT, RG16I,RG16I, SWIZ_XY01, 16, 0),
+FORMAT(R16G16_UINT, RG16UI, RG16UI, SWIZ_XY01, 16, 0),
FORMAT(R16G16B16A16_SINT, RGBA16I, RGBA16I, SWIZ_XYZW, 16, 0),
FORMAT(R16G16B16A16_UINT, RGBA16UI, RGBA16UI,SWIZ_XYZW, 16, 0),
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Mesa (master): broadcom/vc5: Disable transform feedback on V3D 4.x at the end of the job.
Module: Mesa
Branch: master
Commit: ef2cf9cc3c1a4bc96fcc46eb623768a400c3d68d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef2cf9cc3c1a4bc96fcc46eb623768a400c3d68d
Author: Eric Anholt <e...@anholt.net>
Date: Fri Mar 23 15:28:40 2018 -0700
broadcom/vc5: Disable transform feedback on V3D 4.x at the end of the job.
The next job from this client will turn it back on unless TF gets
disabled, but we don't want the state to leak from this client to another
(which causes GPU hangs).
---
src/gallium/drivers/vc5/v3dx_job.c| 21 +++--
src/gallium/drivers/vc5/vc5_context.h | 6 ++
src/gallium/drivers/vc5/vc5_emit.c| 7 ---
3 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/vc5/v3dx_job.c
b/src/gallium/drivers/vc5/v3dx_job.c
index d4b0adfea0..ca3831c75b 100644
--- a/src/gallium/drivers/vc5/v3dx_job.c
+++ b/src/gallium/drivers/vc5/v3dx_job.c
@@ -33,8 +33,12 @@
void v3dX(bcl_epilogue)(struct vc5_context *vc5, struct vc5_job *job)
{
vc5_cl_ensure_space_with_branch(>bcl,
-7 +
-
cl_packet_length(OCCLUSION_QUERY_COUNTER));
+
cl_packet_length(OCCLUSION_QUERY_COUNTER) +
+#if V3D_VERSION >= 41
+
cl_packet_length(TRANSFORM_FEEDBACK_SPECS) +
+#endif
+
cl_packet_length(INCREMENT_SEMAPHORE) +
+
cl_packet_length(FLUSH_ALL_STATE));
if (job->oq_enabled) {
/* Disable the OQ at the end of the CL, so that the
@@ -44,6 +48,19 @@ void v3dX(bcl_epilogue)(struct vc5_context *vc5, struct
vc5_job *job)
cl_emit(>bcl, OCCLUSION_QUERY_COUNTER, counter);
}
+/* Disable TF at the end of the CL, so that the next job to be
+ * run doesn't start out trying to write TF primitives. On
+ * V3D 3.x, it's only the TF primitive mode that triggers TF
+ * writes.
+ */
+#if V3D_VERSION >= 41
+if (job->tf_enabled) {
+cl_emit(>bcl, TRANSFORM_FEEDBACK_SPECS, tfe) {
+tfe.enable = false;
+};
+}
+#endif /* V3D_VERSION >= 41 */
+
/* Increment the semaphore indicating that binning is done and
* unblocking the render thread. Note that this doesn't act
* until the FLUSH completes.
diff --git a/src/gallium/drivers/vc5/vc5_context.h
b/src/gallium/drivers/vc5/vc5_context.h
index 7272e045c4..f6ed91c27a 100644
--- a/src/gallium/drivers/vc5/vc5_context.h
+++ b/src/gallium/drivers/vc5/vc5_context.h
@@ -294,6 +294,12 @@ struct vc5_job {
*/
bool oq_enabled;
+/**
+ * Set when a packet enabling TF on all further primitives has been
+ * emitted.
+ */
+bool tf_enabled;
+
bool uses_early_z;
/**
diff --git a/src/gallium/drivers/vc5/vc5_emit.c
b/src/gallium/drivers/vc5/vc5_emit.c
index 061d6e7c9d..a98fd037d0 100644
--- a/src/gallium/drivers/vc5/vc5_emit.c
+++ b/src/gallium/drivers/vc5/vc5_emit.c
@@ -585,12 +585,13 @@ v3dX(emit_state)(struct pipe_context *pctx)
vc5->prog.bind_vs->tf_specs);
#if V3D_VERSION >= 40
+job->tf_enabled = (vc5->prog.bind_vs->num_tf_specs !=
0 &&
+ vc5->active_queries);
+
cl_emit(>bcl, TRANSFORM_FEEDBACK_SPECS, tfe) {
tfe.number_of_16_bit_output_data_specs_following =
vc5->prog.bind_vs->num_tf_specs;
-tfe.enable =
-(vc5->prog.bind_vs->num_tf_specs != 0
&&
- vc5->active_queries);
+tfe.enable = job->tf_enabled;
};
#else /* V3D_VERSION < 40 */
cl_emit(>bcl, TRANSFORM_FEEDBACK_ENABLE, tfe) {
___
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Mesa (master): broadcom/vc5: Move the BCL epilogue code to a per-version compile.
Module: Mesa
Branch: master
Commit: 1fa820cef861b0f2efd001cfb3c4adecf2fa549b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1fa820cef861b0f2efd001cfb3c4adecf2fa549b
Author: Eric Anholt <e...@anholt.net>
Date: Fri Mar 23 15:19:05 2018 -0700
broadcom/vc5: Move the BCL epilogue code to a per-version compile.
I need to do some new packets for transform feedback on 4.1.
---
src/gallium/drivers/vc5/Makefile.sources | 1 +
src/gallium/drivers/vc5/meson.build | 1 +
src/gallium/drivers/vc5/v3dx_context.h | 2 ++
src/gallium/drivers/vc5/v3dx_job.c | 59
src/gallium/drivers/vc5/vc5_job.c| 28 +++
5 files changed, 67 insertions(+), 24 deletions(-)
diff --git a/src/gallium/drivers/vc5/Makefile.sources
b/src/gallium/drivers/vc5/Makefile.sources
index 0259ecc99b..c1e4e0b023 100644
--- a/src/gallium/drivers/vc5/Makefile.sources
+++ b/src/gallium/drivers/vc5/Makefile.sources
@@ -28,6 +28,7 @@ C_SOURCES := \
VC5_PER_VERSION_SOURCES = \
v3dx_context.h \
v3dx_format_table.c \
+ v3dx_job.c \
v3dx_simulator.c \
vc5_draw.c \
vc5_emit.c \
diff --git a/src/gallium/drivers/vc5/meson.build
b/src/gallium/drivers/vc5/meson.build
index 005bf2f9b8..4f20c2697e 100644
--- a/src/gallium/drivers/vc5/meson.build
+++ b/src/gallium/drivers/vc5/meson.build
@@ -44,6 +44,7 @@ files_libvc5 = files(
files_per_version = files(
'v3dx_format_table.c',
+ 'v3dx_job.c',
'v3dx_simulator.c',
'vc5_draw.c',
'vc5_emit.c',
diff --git a/src/gallium/drivers/vc5/v3dx_context.h
b/src/gallium/drivers/vc5/v3dx_context.h
index addc7433b3..f9edd1c636 100644
--- a/src/gallium/drivers/vc5/v3dx_context.h
+++ b/src/gallium/drivers/vc5/v3dx_context.h
@@ -34,6 +34,8 @@ void v3dX(emit_rcl)(struct vc5_job *job);
void v3dX(draw_init)(struct pipe_context *pctx);
void v3dX(state_init)(struct pipe_context *pctx);
+void v3dX(bcl_epilogue)(struct vc5_context *vc5, struct vc5_job *job);
+
void v3dX(simulator_init_regs)(struct v3d_hw *v3d);
int v3dX(simulator_get_param_ioctl)(struct v3d_hw *v3d,
struct drm_vc5_get_param *args);
diff --git a/src/gallium/drivers/vc5/v3dx_job.c
b/src/gallium/drivers/vc5/v3dx_job.c
new file mode 100644
index 00..d4b0adfea0
--- /dev/null
+++ b/src/gallium/drivers/vc5/v3dx_job.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright © 2014-2017 Broadcom
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+/** @file v3dx_job.c
+ *
+ * V3D version-specific functions for submitting VC5 render jobs to the
+ * kernel.
+ */
+
+#include "vc5_context.h"
+#include "broadcom/cle/v3dx_pack.h"
+
+void v3dX(bcl_epilogue)(struct vc5_context *vc5, struct vc5_job *job)
+{
+vc5_cl_ensure_space_with_branch(>bcl,
+7 +
+
cl_packet_length(OCCLUSION_QUERY_COUNTER));
+
+if (job->oq_enabled) {
+/* Disable the OQ at the end of the CL, so that the
+ * draw calls at the start of the CL don't inherit the
+ * OQ counter.
+ */
+cl_emit(>bcl, OCCLUSION_QUERY_COUNTER, counter);
+}
+
+/* Increment the semaphore indicating that binning is done and
+ * unblocking the render thread. Note that this doesn't act
+ * until the FLUSH completes.
+ */
+cl_emit(>bcl, INCREMENT_SEMAPHORE, incr);
+
+/* The FLUSH_ALL emits any unwritten state changes in each
+ * tile. We can use this to reset any state that needs to be
+ * present at the start of the next tile, as we
Mesa (master): broadcom/vc5: Fix swizzling of RGB10_A2UI render targets.
Module: Mesa
Branch: master
Commit: 0024b77e876017b559b76d816d40a2abbd9a0ea1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0024b77e876017b559b76d816d40a2abbd9a0ea1
Author: Eric Anholt <e...@anholt.net>
Date: Mon Mar 26 12:39:12 2018 -0700
broadcom/vc5: Fix swizzling of RGB10_A2UI render targets.
This is the actual hardware layout, and we were only swizzling R/B back
around in texturing. Fixes part of
KHR-GLES3.copy_tex_image_conversions.required.cubemap_negx_cubemap_negx in
simulation.
---
src/gallium/drivers/vc5/v3dx_format_table.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/vc5/v3dx_format_table.c
b/src/gallium/drivers/vc5/v3dx_format_table.c
index 884f7373a1..4aaf0ecd3d 100644
--- a/src/gallium/drivers/vc5/v3dx_format_table.c
+++ b/src/gallium/drivers/vc5/v3dx_format_table.c
@@ -68,7 +68,7 @@ static const struct vc5_format format_table[] = {
FORMAT(R8G8B8A8_SNORM,NO, RGBA8_SNORM, SWIZ_XYZW, 16, 0),
FORMAT(R8G8B8X8_SNORM,NO, RGBA8_SNORM, SWIZ_XYZ1, 16, 0),
FORMAT(R10G10B10A2_UNORM, RGB10_A2, RGB10_A2,SWIZ_XYZW, 16, 0),
-FORMAT(B10G10R10A2_UINT, RGB10_A2UI, RGB10_A2UI, SWIZ_ZYXW, 16, 0),
+FORMAT(R10G10B10A2_UINT, RGB10_A2UI, RGB10_A2UI, SWIZ_XYZW, 16, 0),
FORMAT(A4B4G4R4_UNORM,ABGR, RGBA4, SWIZ_XYZW, 16, 0),
___
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Mesa (master): st: Allow accelerated CopyTexImage from RGBA to RGB.
Module: Mesa
Branch: master
Commit: d491ad1d364afa60eef5cf7b45f69f7007ab3dfd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d491ad1d364afa60eef5cf7b45f69f7007ab3dfd
Author: Eric Anholt <e...@anholt.net>
Date: Wed Mar 21 11:43:28 2018 -0700
st: Allow accelerated CopyTexImage from RGBA to RGB.
There's nothing to worry about here -- the A channel just gets dropped by
the blit. This avoids a segfault in the fallback path when copying from a
RGBA16_SINT renderbuffer to a RGB16_SINT destination represented by an
RGBA16_SINT texture (the fallback path tries to get/fetch to float
buffers, but the float pack/unpack functions are NULL for SINT/UINT).
Fixes KHR-GLES3.packed_pixels.pbo_rectangle.rgba16i on VC5.
v2: Extract the logic to a helper function and explain what's going on
better.
v3: const-qualify args
Reviewed-by: Brian Paul <bri...@vmware.com>
---
src/mesa/state_tracker/st_cb_texture.c | 32 ++--
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_texture.c
b/src/mesa/state_tracker/st_cb_texture.c
index 6345ead639..3a793a7265 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -2281,6 +2281,31 @@ fallback_copy_texsubimage(struct gl_context *ctx,
pipe->transfer_unmap(pipe, src_trans);
}
+static bool
+st_can_copyteximage_using_blit(const struct gl_texture_image *texImage,
+ const struct gl_renderbuffer *rb)
+{
+ GLenum tex_baseformat = _mesa_get_format_base_format(texImage->TexFormat);
+
+ /* We don't blit to a teximage where the GL base format doesn't match the
+* texture's chosen format, except in the case of a GL_RGB texture
+* represented with GL_RGBA (where the alpha channel is just being
+* dropped).
+*/
+ if (texImage->_BaseFormat != tex_baseformat &&
+ ((texImage->_BaseFormat != GL_RGB || tex_baseformat != GL_RGBA))) {
+ return false;
+ }
+
+ /* We can't blit from a RB where the GL base format doesn't match the RB's
+* chosen format (for example, GL RGB or ALPHA with rb->Format of an RGBA
+* type, because the other channels will be undefined).
+*/
+ if (rb->_BaseFormat != _mesa_get_format_base_format(rb->Format))
+ return false;
+
+ return true;
+}
/**
* Do a CopyTex[Sub]Image1/2/3D() using a hardware (blit) path if possible.
@@ -2324,12 +2349,7 @@ st_CopyTexSubImage(struct gl_context *ctx, GLuint dims,
goto fallback;
}
- /* The base internal format must match the mesa format, so make sure
-* e.g. an RGB internal format is really allocated as RGB and not as RGBA.
-*/
- if (texImage->_BaseFormat !=
- _mesa_get_format_base_format(texImage->TexFormat) ||
- rb->_BaseFormat != _mesa_get_format_base_format(rb->Format)) {
+ if (!st_can_copyteximage_using_blit(texImage, rb)) {
goto fallback;
}
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Mesa (master): broadcom/vc5: Fix EZ disabling and allow using GT/GE direction as well.
Module: Mesa
Branch: master
Commit: 1bf466270d416643e8fcacd6b790e53660303059
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1bf466270d416643e8fcacd6b790e53660303059
Author: Eric Anholt <e...@anholt.net>
Date: Fri Mar 23 16:18:02 2018 -0700
broadcom/vc5: Fix EZ disabling and allow using GT/GE direction as well.
Once we've disabled EZ for some draws, we need to not use EZ on future
draws. Implementing that made implementing the GT/GE direction trivial.
Fixes KHR-GLES3.shaders.fragdepth.compare.no_write on V3D 4.1 simulation.
---
src/gallium/drivers/vc5/vc5_context.h | 20 +--
src/gallium/drivers/vc5/vc5_draw.c| 47 ---
src/gallium/drivers/vc5/vc5_emit.c| 9 ---
src/gallium/drivers/vc5/vc5_rcl.c | 16 +++-
src/gallium/drivers/vc5/vc5_state.c | 40 -
5 files changed, 111 insertions(+), 21 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_context.h
b/src/gallium/drivers/vc5/vc5_context.h
index f6ed91c27a..f61c37ba92 100644
--- a/src/gallium/drivers/vc5/vc5_context.h
+++ b/src/gallium/drivers/vc5/vc5_context.h
@@ -199,6 +199,13 @@ struct vc5_job_key {
struct pipe_surface *zsbuf;
};
+enum vc5_ez_state {
+VC5_EZ_UNDECIDED = 0,
+VC5_EZ_GT_GE,
+VC5_EZ_LT_LE,
+VC5_EZ_DISABLED,
+};
+
/**
* A complete bin/render job.
*
@@ -300,7 +307,16 @@ struct vc5_job {
*/
bool tf_enabled;
-bool uses_early_z;
+/**
+ * Current EZ state for drawing. Updated at the start of draw after
+ * we've decided on the shader being rendered.
+ */
+enum vc5_ez_state ez_state;
+/**
+ * The first EZ state that was used for drawing with a decided EZ
+ * direction (so either UNDECIDED, GT, or LT).
+ */
+enum vc5_ez_state first_ez_state;
/**
* Number of draw calls (not counting full buffer clears) queued in
@@ -429,7 +445,7 @@ struct vc5_rasterizer_state {
struct vc5_depth_stencil_alpha_state {
struct pipe_depth_stencil_alpha_state base;
-bool early_z_enable;
+enum vc5_ez_state ez_state;
/** Uniforms for stencil state.
*
diff --git a/src/gallium/drivers/vc5/vc5_draw.c
b/src/gallium/drivers/vc5/vc5_draw.c
index 7a409c14d4..25f4883be2 100644
--- a/src/gallium/drivers/vc5/vc5_draw.c
+++ b/src/gallium/drivers/vc5/vc5_draw.c
@@ -327,6 +327,49 @@ vc5_tf_statistics_record(struct vc5_context *vc5,
}
static void
+vc5_update_job_ez(struct vc5_context *vc5, struct vc5_job *job)
+{
+switch (vc5->zsa->ez_state) {
+case VC5_EZ_UNDECIDED:
+/* If the Z/S state didn't pick a direction but didn't
+ * disable, then go along with the current EZ state. This
+ * allows EZ optimization for Z func == EQUAL or NEVER.
+ */
+break;
+
+case VC5_EZ_LT_LE:
+case VC5_EZ_GT_GE:
+/* If the Z/S state picked a direction, then it needs to match
+ * the current direction if we've decided on one.
+ */
+if (job->ez_state == VC5_EZ_UNDECIDED)
+job->ez_state = vc5->zsa->ez_state;
+else if (job->ez_state != vc5->zsa->ez_state)
+job->ez_state = VC5_EZ_DISABLED;
+break;
+
+case VC5_EZ_DISABLED:
+/* If the current Z/S state disables EZ because of a bad Z
+ * func or stencil operation, then we can't do any more EZ in
+ * this frame.
+ */
+job->ez_state = VC5_EZ_DISABLED;
+break;
+}
+
+/* If the FS affects the Z of the pixels, then it may update against
+ * the chosen EZ direction (though we could use
+ * ARB_conservative_depth's hints to avoid this)
+ */
+if (vc5->prog.fs->prog_data.fs->writes_z) {
+job->ez_state = VC5_EZ_DISABLED;
+}
+
+if (job->first_ez_state == VC5_EZ_UNDECIDED)
+job->first_ez_state = job->ez_state;
+}
+
+static void
vc5_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
{
struct vc5_context *vc5 = vc5_context(pctx);
@@ -384,6 +427,7 @@ vc5_draw_vbo(struct pipe_context *pctx, const struct
pipe_draw_info *info)
vc5_start_draw(vc5);
vc5_update_compiled_shaders(vc5, info->mode);
+vc5_update_job_ez(vc5, job);
#if V3D_VERSION >= 41
v3d41_emit_state(pctx);
@@ -515,9 +559,6 @@ vc5_draw_vbo(struct pipe_context *pctx, const struct
pipe_draw_info *info)
if (vc5->zsa->base.depth.enabled) {
job->resolve |= PIPE_CLEAR_DEPTH;
rsc->initialized_buffe
Mesa (master): broadcom/vc5: Implement workaround for GFXH-1431.
Module: Mesa
Branch: master
Commit: 494da6c2dd8f0b570693f7611b58be11061224e0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=494da6c2dd8f0b570693f7611b58be11061224e0
Author: Eric Anholt <e...@anholt.net>
Date: Mon Mar 26 10:38:28 2018 -0700
broadcom/vc5: Implement workaround for GFXH-1431.
This should fix some blending errors, but doesn't impact any testcases in
the CTS.
---
src/gallium/drivers/vc5/vc5_emit.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/vc5/vc5_emit.c
b/src/gallium/drivers/vc5/vc5_emit.c
index 71f508c9ee..deb46228da 100644
--- a/src/gallium/drivers/vc5/vc5_emit.c
+++ b/src/gallium/drivers/vc5/vc5_emit.c
@@ -490,7 +490,11 @@ v3dX(emit_state)(struct pipe_context *pctx)
}
}
-if (vc5->dirty & VC5_DIRTY_BLEND_COLOR) {
+/* GFXH-1431: On V3D 3.x, writing BLEND_CONFIG resets the constant
+ * color.
+ */
+if (vc5->dirty & VC5_DIRTY_BLEND_COLOR ||
+(V3D_VERSION < 41 && (vc5->dirty & VC5_DIRTY_BLEND))) {
cl_emit(>bcl, BLEND_CONSTANT_COLOUR, colour) {
colour.red_f16 = (vc5->swap_color_rb ?
vc5->blend_color.hf[2] :
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Mesa (master): broadcom/vc5: Limit each transform feedback data spec to 16 dwords.
Module: Mesa
Branch: master
Commit: 9e62aec9cd4853016b4d03a56b5756111a312d65
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e62aec9cd4853016b4d03a56b5756111a312d65
Author: Eric Anholt <e...@anholt.net>
Date: Wed Mar 21 15:18:34 2018 -0700
broadcom/vc5: Limit each transform feedback data spec to 16 dwords.
The length-1 field only has 4 bits, so we need to generate separate specs
when there's too much TF output per buffer.
Fixes
GTF-GLES3.gtf.GL3Tests.transform_feedback.transform_feedback_builtin_type
and transform_feedback_max_interleaved.
---
src/gallium/drivers/vc5/vc5_context.h | 2 +-
src/gallium/drivers/vc5/vc5_program.c | 43 ---
2 files changed, 31 insertions(+), 14 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_context.h
b/src/gallium/drivers/vc5/vc5_context.h
index 1ab5a6b153..976fba90f8 100644
--- a/src/gallium/drivers/vc5/vc5_context.h
+++ b/src/gallium/drivers/vc5/vc5_context.h
@@ -130,7 +130,7 @@ struct vc5_uncompiled_shader {
struct pipe_shader_state base;
uint32_t num_tf_outputs;
struct v3d_varying_slot *tf_outputs;
-uint16_t tf_specs[PIPE_MAX_SO_BUFFERS];
+uint16_t tf_specs[16];
uint32_t num_tf_specs;
/**
diff --git a/src/gallium/drivers/vc5/vc5_program.c
b/src/gallium/drivers/vc5/vc5_program.c
index 87c21abe8b..a7a089510b 100644
--- a/src/gallium/drivers/vc5/vc5_program.c
+++ b/src/gallium/drivers/vc5/vc5_program.c
@@ -49,6 +49,14 @@ vc5_get_slot_for_driver_location(nir_shader *s, uint32_t
driver_location)
return -1;
}
+/**
+ * Precomputes the TRANSFORM_FEEDBACK_OUTPUT_DATA_SPEC array for the shader.
+ *
+ * A shader can have 16 of these specs, and each one of them can write up to
+ * 16 dwords. Since we allow a total of 64 transform feedback output
+ * components (not 16 vectors), we have to group the writes of multiple
+ * varyings together in a single data spec.
+ */
static void
vc5_set_transform_feedback_outputs(struct vc5_uncompiled_shader *so,
const struct pipe_stream_output_info
*stream_output)
@@ -102,19 +110,28 @@ vc5_set_transform_feedback_outputs(struct
vc5_uncompiled_shader *so,
if (!vpm_size)
continue;
-struct V3D33_TRANSFORM_FEEDBACK_OUTPUT_DATA_SPEC unpacked = {
-/* We need the offset from the coordinate shader's VPM
- * output block, which has the [X, Y, Z, W, Xs, Ys]
- * values at the start. Note that this will need some
- * shifting when PSIZ is also present.
- */
-.first_shaded_vertex_value_to_output = vpm_start + 6,
-
.number_of_consecutive_vertex_values_to_output_as_32_bit_values_minus_1 =
vpm_size - 1,
-.output_buffer_to_write_to = buffer,
-};
-V3D33_TRANSFORM_FEEDBACK_OUTPUT_DATA_SPEC_pack(NULL,
- (void
*)>tf_specs[so->num_tf_specs++],
- );
+uint32_t vpm_start_offset = vpm_start + 6;
+
+while (vpm_size) {
+uint32_t write_size = MIN2(vpm_size, 1 << 4);
+
+struct V3D33_TRANSFORM_FEEDBACK_OUTPUT_DATA_SPEC
unpacked = {
+/* We need the offset from the coordinate
shader's VPM
+ * output block, which has the [X, Y, Z, W,
Xs, Ys]
+ * values at the start.
+ */
+.first_shaded_vertex_value_to_output =
vpm_start_offset,
+
.number_of_consecutive_vertex_values_to_output_as_32_bit_values_minus_1 =
write_size - 1,
+.output_buffer_to_write_to = buffer,
+};
+
+assert(so->num_tf_specs != ARRAY_SIZE(so->tf_specs));
+V3D33_TRANSFORM_FEEDBACK_OUTPUT_DATA_SPEC_pack(NULL,
+ (void
*)>tf_specs[so->num_tf_specs++],
+
);
+vpm_start_offset += write_size;
+vpm_size -= write_size;
+}
}
so->num_tf_outputs = slot_count;
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Mesa (master): broadcom/vc5: Fix transform feedback in the presence of point size.
Module: Mesa
Branch: master
Commit: 33878641305345b9bb76ad5ebf2335ec9c17adfa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=33878641305345b9bb76ad5ebf2335ec9c17adfa
Author: Eric Anholt <e...@anholt.net>
Date: Wed Mar 21 15:07:19 2018 -0700
broadcom/vc5: Fix transform feedback in the presence of point size.
I had this note to myself, and it turns out that a lot of CTS tests use
XFB with points to get data out without using a fragment shader. Keep
track of two sets of precomputed TF specs (point size in VPM prologue or
not), and switch between them when we enable/disable point size.
---
src/gallium/drivers/vc5/vc5_context.h | 1 +
src/gallium/drivers/vc5/vc5_emit.c| 13 ++---
src/gallium/drivers/vc5/vc5_program.c | 13 -
3 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_context.h
b/src/gallium/drivers/vc5/vc5_context.h
index 976fba90f8..7272e045c4 100644
--- a/src/gallium/drivers/vc5/vc5_context.h
+++ b/src/gallium/drivers/vc5/vc5_context.h
@@ -131,6 +131,7 @@ struct vc5_uncompiled_shader {
uint32_t num_tf_outputs;
struct v3d_varying_slot *tf_outputs;
uint16_t tf_specs[16];
+uint16_t tf_specs_psiz[16];
uint32_t num_tf_specs;
/**
diff --git a/src/gallium/drivers/vc5/vc5_emit.c
b/src/gallium/drivers/vc5/vc5_emit.c
index 1db97081df..061d6e7c9d 100644
--- a/src/gallium/drivers/vc5/vc5_emit.c
+++ b/src/gallium/drivers/vc5/vc5_emit.c
@@ -572,10 +572,18 @@ v3dX(emit_state)(struct pipe_context *pctx)
/* Set up the transform feedback data specs (which VPM entries to
* output to which buffers).
*/
-if (vc5->dirty & VC5_DIRTY_STREAMOUT) {
+if (vc5->dirty & (VC5_DIRTY_STREAMOUT |
+ VC5_DIRTY_RASTERIZER |
+ VC5_DIRTY_PRIM_MODE)) {
struct vc5_streamout_stateobj *so = >streamout;
if (so->num_targets) {
+bool psiz_per_vertex = (vc5->prim_mode ==
PIPE_PRIM_POINTS &&
+
vc5->rasterizer->base.point_size_per_vertex);
+uint16_t *tf_specs = (psiz_per_vertex ?
+ vc5->prog.bind_vs->tf_specs_psiz
:
+ vc5->prog.bind_vs->tf_specs);
+
#if V3D_VERSION >= 40
cl_emit(>bcl, TRANSFORM_FEEDBACK_SPECS, tfe) {
tfe.number_of_16_bit_output_data_specs_following =
@@ -593,8 +601,7 @@ v3dX(emit_state)(struct pipe_context *pctx)
};
#endif /* V3D_VERSION < 40 */
for (int i = 0; i < vc5->prog.bind_vs->num_tf_specs;
i++) {
-cl_emit_prepacked(>bcl,
-
>prog.bind_vs->tf_specs[i]);
+cl_emit_prepacked(>bcl, _specs[i]);
}
}
}
diff --git a/src/gallium/drivers/vc5/vc5_program.c
b/src/gallium/drivers/vc5/vc5_program.c
index a7a089510b..7bad80a168 100644
--- a/src/gallium/drivers/vc5/vc5_program.c
+++ b/src/gallium/drivers/vc5/vc5_program.c
@@ -127,8 +127,19 @@ vc5_set_transform_feedback_outputs(struct
vc5_uncompiled_shader *so,
assert(so->num_tf_specs != ARRAY_SIZE(so->tf_specs));
V3D33_TRANSFORM_FEEDBACK_OUTPUT_DATA_SPEC_pack(NULL,
- (void
*)>tf_specs[so->num_tf_specs++],
+ (void
*)>tf_specs[so->num_tf_specs],
);
+
+/* If point size is being written by the shader, then
+ * all the VPM start offsets are shifted up by one.
+ * We won't know that until the variant is compiled,
+ * though.
+ */
+unpacked.first_shaded_vertex_value_to_output++;
+V3D33_TRANSFORM_FEEDBACK_OUTPUT_DATA_SPEC_pack(NULL,
+ (void
*)>tf_specs_psiz[so->num_tf_specs],
+
);
+so->num_tf_specs++;
vpm_start_offset += write_size;
vpm_size -= write_size;
}
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Mesa (master): broadcom/vc5: Fix extraneous register index in QIR dumping of TLBU writes.
Module: Mesa Branch: master Commit: c2b13627d9d7973687350cab243ade65115cff0d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2b13627d9d7973687350cab243ade65115cff0d Author: Eric Anholt <e...@anholt.net> Date: Mon Mar 26 12:18:39 2018 -0700 broadcom/vc5: Fix extraneous register index in QIR dumping of TLBU writes. Just like TLB without a config uniform, we don't have a register index. --- src/broadcom/compiler/vir_dump.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/broadcom/compiler/vir_dump.c b/src/broadcom/compiler/vir_dump.c index 90a3fb0ac6..88b5dc90ac 100644 --- a/src/broadcom/compiler/vir_dump.c +++ b/src/broadcom/compiler/vir_dump.c @@ -71,6 +71,7 @@ vir_print_reg(struct v3d_compile *c, struct qreg reg) break; case QFILE_TLB: +case QFILE_TLBU: fprintf(stderr, "%s", files[reg.file]); break; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): broadcom/vc5: Disable TF on V3D 4.x when drawing with queries disabled.
Module: Mesa
Branch: master
Commit: 262208eb3c2c53a1fd807bc76b12088f6ce2c56d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=262208eb3c2c53a1fd807bc76b12088f6ce2c56d
Author: Eric Anholt <e...@anholt.net>
Date: Fri Mar 23 15:43:50 2018 -0700
broadcom/vc5: Disable TF on V3D 4.x when drawing with queries disabled.
On 3.x, we just don't flag the primitive as needing TF, but those
primitive bits are now allocated to the new primitive types. Now we need
to actually update the enable flag at draw time.
---
src/gallium/drivers/vc5/vc5_emit.c | 7 +++
src/gallium/drivers/vc5/vc5_query.c | 1 +
2 files changed, 8 insertions(+)
diff --git a/src/gallium/drivers/vc5/vc5_emit.c
b/src/gallium/drivers/vc5/vc5_emit.c
index a98fd037d0..d5bf2824d2 100644
--- a/src/gallium/drivers/vc5/vc5_emit.c
+++ b/src/gallium/drivers/vc5/vc5_emit.c
@@ -604,6 +604,13 @@ v3dX(emit_state)(struct pipe_context *pctx)
for (int i = 0; i < vc5->prog.bind_vs->num_tf_specs;
i++) {
cl_emit_prepacked(>bcl, _specs[i]);
}
+} else if (job->tf_enabled) {
+#if V3D_VERSION >= 40
+cl_emit(>bcl, TRANSFORM_FEEDBACK_SPECS, tfe) {
+tfe.enable = false;
+};
+job->tf_enabled = false;
+#endif /* V3D_VERSION >= 40 */
}
}
diff --git a/src/gallium/drivers/vc5/vc5_query.c
b/src/gallium/drivers/vc5/vc5_query.c
index 5ec9be2e35..9aa80cf536 100644
--- a/src/gallium/drivers/vc5/vc5_query.c
+++ b/src/gallium/drivers/vc5/vc5_query.c
@@ -164,6 +164,7 @@ vc5_set_active_query_state(struct pipe_context *pctx,
boolean enable)
vc5->active_queries = enable;
vc5->dirty |= VC5_DIRTY_OQ;
+vc5->dirty |= VC5_DIRTY_STREAMOUT;
}
void
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Mesa (master): broadcom/vc5: Split transform feedback specs update from buffers.
Module: Mesa
Branch: master
Commit: 09ac5ade8f3855e42e4902d7e1acab540f3f1568
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=09ac5ade8f3855e42e4902d7e1acab540f3f1568
Author: Eric Anholt <e...@anholt.net>
Date: Fri Mar 23 15:40:36 2018 -0700
broadcom/vc5: Split transform feedback specs update from buffers.
The specs update will be changing based on additional state flags in the
next commit, and this unindents the buffer update code.
---
src/gallium/drivers/vc5/vc5_emit.c | 59 +-
1 file changed, 32 insertions(+), 27 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_emit.c
b/src/gallium/drivers/vc5/vc5_emit.c
index e5a9e0e03a..1db97081df 100644
--- a/src/gallium/drivers/vc5/vc5_emit.c
+++ b/src/gallium/drivers/vc5/vc5_emit.c
@@ -569,6 +569,9 @@ v3dX(emit_state)(struct pipe_context *pctx)
}
}
+/* Set up the transform feedback data specs (which VPM entries to
+ * output to which buffers).
+ */
if (vc5->dirty & VC5_DIRTY_STREAMOUT) {
struct vc5_streamout_stateobj *so = >streamout;
@@ -593,42 +596,44 @@ v3dX(emit_state)(struct pipe_context *pctx)
cl_emit_prepacked(>bcl,
>prog.bind_vs->tf_specs[i]);
}
+}
+}
-for (int i = 0; i < so->num_targets; i++) {
-const struct pipe_stream_output_target *target
=
-so->targets[i];
-struct vc5_resource *rsc = target ?
-vc5_resource(target->buffer) : NULL;
+/* Set up the trasnform feedback buffers. */
+if (vc5->dirty & VC5_DIRTY_STREAMOUT) {
+struct vc5_streamout_stateobj *so = >streamout;
+for (int i = 0; i < so->num_targets; i++) {
+const struct pipe_stream_output_target *target =
+so->targets[i];
+struct vc5_resource *rsc = target ?
+vc5_resource(target->buffer) : NULL;
#if V3D_VERSION >= 40
-if (!target)
-continue;
+if (!target)
+continue;
-cl_emit(>bcl, TRANSFORM_FEEDBACK_BUFFER,
output) {
-output.buffer_address =
+cl_emit(>bcl, TRANSFORM_FEEDBACK_BUFFER, output) {
+output.buffer_address =
+cl_address(rsc->bo,
+ target->buffer_offset);
+output.buffer_size_in_32_bit_words =
+target->buffer_size >> 2;
+output.buffer_number = i;
+}
+#else /* V3D_VERSION < 40 */
+cl_emit(>bcl, TRANSFORM_FEEDBACK_OUTPUT_ADDRESS,
output) {
+if (target) {
+output.address =
cl_address(rsc->bo,
target->buffer_offset);
-output.buffer_size_in_32_bit_words =
-target->buffer_size >> 2;
-output.buffer_number = i;
}
-#else /* V3D_VERSION < 40 */
-cl_emit(>bcl,
TRANSFORM_FEEDBACK_OUTPUT_ADDRESS, output) {
-if (target) {
-output.address =
-cl_address(rsc->bo,
-
target->buffer_offset);
-}
-};
+};
#endif /* V3D_VERSION < 40 */
-if (target) {
-vc5_job_add_write_resource(vc5->job,
-
target->buffer);
-}
-/* XXX: buffer_size? */
+if (target) {
+vc5_job_add_write_resource(vc5->job,
+ target->buffer);
}
-} else {
-/* XXX? */
+
Mesa (master): gallium/u_vbuf: Protect against overflow with large instance divisors.
Module: Mesa
Branch: master
Commit: 0356db022da819176d9d0eacab63d4c2c852f876
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0356db022da819176d9d0eacab63d4c2c852f876
Author: Eric Anholt <e...@anholt.net>
Date: Tue Mar 20 10:42:12 2018 -0700
gallium/u_vbuf: Protect against overflow with large instance divisors.
GTF-GLES3.gtf.GL3Tests.instanced_arrays.instanced_arrays_divisor uses -1
as a divisor, so we would overflow to count=0 and upload no data,
triggering the assert below. We want to upload 1 element in this case,
fixing the test on VC5.
v2: Use some more obvious logic, and explain why we don't use the normal
round_up().
Reviewed-by: Brian Paul <bri...@vmware.com>
---
src/gallium/auxiliary/util/u_vbuf.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/util/u_vbuf.c
b/src/gallium/auxiliary/util/u_vbuf.c
index 95d7990c6c..8a680d60a6 100644
--- a/src/gallium/auxiliary/util/u_vbuf.c
+++ b/src/gallium/auxiliary/util/u_vbuf.c
@@ -936,7 +936,16 @@ u_vbuf_upload_buffers(struct u_vbuf *mgr,
size = mgr->ve->src_format_size[i];
} else if (instance_div) {
/* Per-instance attrib. */
- unsigned count = (num_instances + instance_div - 1) / instance_div;
+
+ /* Figure out how many instances we'll render given instance_div. We
+ * can't use the typical div_round_up() pattern because the CTS uses
+ * instance_div = ~0 for a test, which overflows div_round_up()'s
+ * addition.
+ */
+ unsigned count = num_instances / instance_div;
+ if (count * instance_div != num_instances)
+count++;
+
first += vb->stride * start_instance;
size = vb->stride * (count - 1) + mgr->ve->src_format_size[i];
} else {
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Mesa (master): broadcom/vc5: Account for InstanceID/VertexID in VPM segment size.
Module: Mesa Branch: master Commit: d7a015cbc6a6c12a87ee7ec725cc399d3712f43c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7a015cbc6a6c12a87ee7ec725cc399d3712f43c Author: Eric Anholt <e...@anholt.net> Date: Thu Mar 22 13:52:11 2018 -0700 broadcom/vc5: Account for InstanceID/VertexID in VPM segment size. Fixes failure in GTF-GLES3.gtf.GL3Tests.draw_instanced.draw_instanced_attrib_size --- src/broadcom/compiler/vir.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src/broadcom/compiler/vir.c b/src/broadcom/compiler/vir.c index ff9405e6c1..93990ee806 100644 --- a/src/broadcom/compiler/vir.c +++ b/src/broadcom/compiler/vir.c @@ -728,15 +728,20 @@ uint64_t *v3d_compile_vs(const struct v3d_compiler *compiler, prog_data->vpm_input_size += c->vattr_sizes[i]; } -/* Input/output segment size are in 8x32-bit multiples. */ -prog_data->vpm_input_size = align(prog_data->vpm_input_size, 8) / 8; -prog_data->vpm_output_size = align(c->num_vpm_writes, 8) / 8; - prog_data->uses_vid = (s->info.system_values_read & (1ull << SYSTEM_VALUE_VERTEX_ID)); prog_data->uses_iid = (s->info.system_values_read & (1ull << SYSTEM_VALUE_INSTANCE_ID)); +if (prog_data->uses_vid) +prog_data->vpm_input_size++; +if (prog_data->uses_iid) +prog_data->vpm_input_size++; + +/* Input/output segment size are in 8x32-bit multiples. */ +prog_data->vpm_input_size = align(prog_data->vpm_input_size, 8) / 8; +prog_data->vpm_output_size = align(c->num_vpm_writes, 8) / 8; + return v3d_return_qpu_insts(c, final_assembly_size); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): broadcom/vc5: Add missing support for 2101010_REV vertex attributes.
Module: Mesa Branch: master Commit: 4f62679be58449f2bd3184b56fdee21e85418234 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f62679be58449f2bd3184b56fdee21e85418234 Author: Eric Anholt <e...@anholt.net> Date: Wed Mar 21 14:44:04 2018 -0700 broadcom/vc5: Add missing support for 2101010_REV vertex attributes. Fixes GTF-GLES3.gtf.GL3Tests.vertex_type_2_10_10_10_rev.vertex_type_2_10_10_10_rev_invalid2, where we hadn't thrown a GL error as needed in the extension-disabled case. We want to be exposing the extension anyway. --- src/gallium/drivers/vc5/vc5_screen.c | 8 1 file changed, 8 insertions(+) diff --git a/src/gallium/drivers/vc5/vc5_screen.c b/src/gallium/drivers/vc5/vc5_screen.c index add5a2f358..2a42bc1b87 100644 --- a/src/gallium/drivers/vc5/vc5_screen.c +++ b/src/gallium/drivers/vc5/vc5_screen.c @@ -481,6 +481,14 @@ vc5_screen_is_format_supported(struct pipe_screen *pscreen, case PIPE_FORMAT_R8G8B8_SSCALED: case PIPE_FORMAT_R8G8_SSCALED: case PIPE_FORMAT_R8_SSCALED: +case PIPE_FORMAT_R10G10B10A2_UNORM: +case PIPE_FORMAT_B10G10R10A2_UNORM: +case PIPE_FORMAT_R10G10B10A2_SNORM: +case PIPE_FORMAT_B10G10R10A2_SNORM: +case PIPE_FORMAT_R10G10B10A2_USCALED: +case PIPE_FORMAT_B10G10R10A2_USCALED: +case PIPE_FORMAT_R10G10B10A2_SSCALED: +case PIPE_FORMAT_B10G10R10A2_SSCALED: break; default: return FALSE; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): broadcom/vc5: Set up a vertex position if the shader doesn't.
Module: Mesa
Branch: master
Commit: ba29b89dc7c7555fc6996fee2d08b9cbcd8b9018
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba29b89dc7c7555fc6996fee2d08b9cbcd8b9018
Author: Eric Anholt <e...@anholt.net>
Date: Wed Mar 21 14:18:08 2018 -0700
broadcom/vc5: Set up a vertex position if the shader doesn't.
Our backend needs some sort of vertex position value to emit the scaled
viewport values and such. Fixes potential segfaults in
KHR-GLES3.copy_tex_image_conversions.required.cubemap_negx_cubemap_negx
---
src/broadcom/compiler/nir_to_vir.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/src/broadcom/compiler/nir_to_vir.c
b/src/broadcom/compiler/nir_to_vir.c
index 75e35067f2..893dfa160a 100644
--- a/src/broadcom/compiler/nir_to_vir.c
+++ b/src/broadcom/compiler/nir_to_vir.c
@@ -1103,9 +1103,31 @@ emit_vpm_write_setup(struct v3d_compile *c)
v3d33_vir_vpm_write_setup(c);
}
+/**
+ * Sets up c->outputs[c->output_position_index] for the vertex shader
+ * epilogue, if an output vertex position wasn't specified in the user's
+ * shader. This may be the case for transform feedback with rasterizer
+ * discard enabled.
+ */
+static void
+setup_default_position(struct v3d_compile *c)
+{
+if (c->output_position_index != -1)
+return;
+
+c->output_position_index = c->outputs_array_size;
+for (int i = 0; i < 4; i++) {
+add_output(c,
+ c->output_position_index + i,
+ VARYING_SLOT_POS, i);
+}
+}
+
static void
emit_vert_end(struct v3d_compile *c)
{
+setup_default_position(c);
+
uint32_t vpm_index = 0;
struct qreg rcp_w = vir_SFU(c, V3D_QPU_WADDR_RECIP,
c->outputs[c->output_position_index + 3]);
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Mesa (master): broadcom/vc5: Allow FBOs with mixed color formats.
Module: Mesa Branch: master Commit: b8387dbc49a87ff7a2b613a29a375b2a2eb88041 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b8387dbc49a87ff7a2b613a29a375b2a2eb88041 Author: Eric Anholt <e...@anholt.net> Date: Thu Mar 22 13:45:17 2018 -0700 broadcom/vc5: Allow FBOs with mixed color formats. This is required by GLES3, fixing GTF-GLES3.gtf.GL3Tests.framebuffer_srgb.framebuffer_srgb_draw --- src/gallium/drivers/vc5/vc5_screen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/vc5/vc5_screen.c b/src/gallium/drivers/vc5/vc5_screen.c index 2a42bc1b87..271c2c878b 100644 --- a/src/gallium/drivers/vc5/vc5_screen.c +++ b/src/gallium/drivers/vc5/vc5_screen.c @@ -143,6 +143,7 @@ vc5_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 0; case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: +case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: return 1; @@ -167,7 +168,6 @@ vc5_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: case PIPE_CAP_CUBE_MAP_ARRAY: case PIPE_CAP_TEXTURE_MIRROR_CLAMP: -case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: case PIPE_CAP_SEAMLESS_CUBE_MAP: case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): broadcom/vc5: Fix up the NIR types of FS outputs generated by NIR-to-TGSI.
Module: Mesa
Branch: master
Commit: baeb6a4b4a275bc418037b718c904180e9e5c690
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=baeb6a4b4a275bc418037b718c904180e9e5c690
Author: Eric Anholt <e...@anholt.net>
Date: Wed Mar 21 12:05:54 2018 -0700
broadcom/vc5: Fix up the NIR types of FS outputs generated by NIR-to-TGSI.
Unfortunately TGSI doesn't record the type of the FS output like GLSL
does, but VC5's TLB writes depend on the output's base type. Just record
the type in the key at variant compile time when we've got a TGSI input
and then fix it up.
Fixes KHR-GLES3.packed_pixels.pbo_rectangle.rgba32i/ui and apparently a
GPU hang that breaks most tests that come after it.
---
src/broadcom/compiler/v3d_compiler.h | 5 +
src/broadcom/compiler/vir.c | 33 +
src/gallium/drivers/vc5/vc5_context.h | 7 +++
src/gallium/drivers/vc5/vc5_program.c | 9 +
4 files changed, 54 insertions(+)
diff --git a/src/broadcom/compiler/v3d_compiler.h
b/src/broadcom/compiler/v3d_compiler.h
index df81f0757e..207e29733a 100644
--- a/src/broadcom/compiler/v3d_compiler.h
+++ b/src/broadcom/compiler/v3d_compiler.h
@@ -336,6 +336,11 @@ struct v3d_fs_key {
uint8_t swap_color_rb;
/* Mask of which render targets need to be written as 32-bit floats */
uint8_t f32_color_rb;
+/* Masks of which render targets need to be written as ints/uints.
+ * Used by gallium to work around lost information in TGSI.
+ */
+uint8_t int_color_rb;
+uint8_t uint_color_rb;
uint8_t alpha_test_func;
uint8_t logicop_func;
uint32_t point_sprite_mask;
diff --git a/src/broadcom/compiler/vir.c b/src/broadcom/compiler/vir.c
index 05f557fbcd..ff9405e6c1 100644
--- a/src/broadcom/compiler/vir.c
+++ b/src/broadcom/compiler/vir.c
@@ -756,6 +756,36 @@ v3d_set_fs_prog_data_inputs(struct v3d_compile *c,
}
}
+static void
+v3d_fixup_fs_output_types(struct v3d_compile *c)
+{
+nir_foreach_variable(var, >s->outputs) {
+uint32_t mask = 0;
+
+switch (var->data.location) {
+case FRAG_RESULT_COLOR:
+mask = ~0;
+break;
+case FRAG_RESULT_DATA0:
+case FRAG_RESULT_DATA1:
+case FRAG_RESULT_DATA2:
+case FRAG_RESULT_DATA3:
+mask = 1 << (var->data.location - FRAG_RESULT_DATA0);
+break;
+}
+
+if (c->fs_key->int_color_rb & mask) {
+var->type =
+glsl_vector_type(GLSL_TYPE_INT,
+
glsl_get_components(var->type));
+} else if (c->fs_key->uint_color_rb & mask) {
+var->type =
+glsl_vector_type(GLSL_TYPE_UINT,
+
glsl_get_components(var->type));
+}
+}
+}
+
uint64_t *v3d_compile_fs(const struct v3d_compiler *compiler,
struct v3d_fs_key *key,
struct v3d_fs_prog_data *prog_data,
@@ -768,6 +798,9 @@ uint64_t *v3d_compile_fs(const struct v3d_compiler
*compiler,
c->fs_key = key;
+if (key->int_color_rb || key->uint_color_rb)
+v3d_fixup_fs_output_types(c);
+
v3d_lower_nir(c);
if (key->light_twoside)
diff --git a/src/gallium/drivers/vc5/vc5_context.h
b/src/gallium/drivers/vc5/vc5_context.h
index 28b2e165a9..1ab5a6b153 100644
--- a/src/gallium/drivers/vc5/vc5_context.h
+++ b/src/gallium/drivers/vc5/vc5_context.h
@@ -132,6 +132,13 @@ struct vc5_uncompiled_shader {
struct v3d_varying_slot *tf_outputs;
uint16_t tf_specs[PIPE_MAX_SO_BUFFERS];
uint32_t num_tf_specs;
+
+/**
+ * Flag for if the NIR in this shader originally came from TGSI. If
+ * so, we need to do some fixups at compile time, due to missing
+ * information in TGSI that exists in NIR.
+ */
+bool was_tgsi;
};
struct vc5_compiled_shader {
diff --git a/src/gallium/drivers/vc5/vc5_program.c
b/src/gallium/drivers/vc5/vc5_program.c
index ae3850a64b..87c21abe8b 100644
--- a/src/gallium/drivers/vc5/vc5_program.c
+++ b/src/gallium/drivers/vc5/vc5_program.c
@@ -170,6 +170,8 @@ vc5_shader_state_create(struct pipe_context *pctx,
fprintf(stderr, "\n");
}
s = tgsi_to_nir(cso->tokens, _nir_options);
+
+so->was_tgsi = true;
}
NIR_PASS_V(s, nir_opt_global_to_local);
@@ -414,6 +416,13 @@ vc5_update_compiled_fs(struct vc5_context *vc5, uint8_t
prim_mode)
desc->channel[0].size == 32) {
k
Mesa (master): broadcom/vc5: Don't skip job submit just because everything is scissored.
Module: Mesa
Branch: master
Commit: 9f0c9c6d18dfb0027bde20647083395e24ce9825
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f0c9c6d18dfb0027bde20647083395e24ce9825
Author: Eric Anholt <e...@anholt.net>
Date: Tue Mar 20 12:52:19 2018 -0700
broadcom/vc5: Don't skip job submit just because everything is scissored.
The coordinate shaders may now have side effects in the form of transform
feedback.
Part of fixing
GTF-GLES3.gtf.GL3Tests.transform_feedback.transform_feedback_misc
---
src/gallium/drivers/vc5/vc5_job.c | 8
src/gallium/drivers/vc5/vc5_rcl.c | 9 +++--
2 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_job.c
b/src/gallium/drivers/vc5/vc5_job.c
index aa56ad6f24..213a978e3c 100644
--- a/src/gallium/drivers/vc5/vc5_job.c
+++ b/src/gallium/drivers/vc5/vc5_job.c
@@ -377,14 +377,6 @@ vc5_job_submit(struct vc5_context *vc5, struct vc5_job
*job)
if (!job->needs_flush)
goto done;
-/* The RCL setup would choke if the draw bounds cause no drawing, so
- * just drop the drawing if that's the case.
- */
-if (job->draw_max_x <= job->draw_min_x ||
-job->draw_max_y <= job->draw_min_y) {
-goto done;
-}
-
if (vc5->screen->devinfo.ver >= 41)
v3d41_emit_rcl(job);
else
diff --git a/src/gallium/drivers/vc5/vc5_rcl.c
b/src/gallium/drivers/vc5/vc5_rcl.c
index 86ea22628d..a5efa32e21 100644
--- a/src/gallium/drivers/vc5/vc5_rcl.c
+++ b/src/gallium/drivers/vc5/vc5_rcl.c
@@ -696,8 +696,13 @@ v3dX(emit_rcl)(struct vc5_job *job)
uint32_t supertile_h_in_pixels = job->tile_height * supertile_h;
uint32_t min_x_supertile = job->draw_min_x / supertile_w_in_pixels;
uint32_t min_y_supertile = job->draw_min_y / supertile_h_in_pixels;
-uint32_t max_x_supertile = (job->draw_max_x - 1) /
supertile_w_in_pixels;
-uint32_t max_y_supertile = (job->draw_max_y - 1) /
supertile_h_in_pixels;
+
+uint32_t max_x_supertile = 0;
+uint32_t max_y_supertile = 0;
+if (job->draw_max_x != 0 && job->draw_max_y != 0) {
+max_x_supertile = (job->draw_max_x - 1) /
supertile_w_in_pixels;
+max_y_supertile = (job->draw_max_y - 1) /
supertile_h_in_pixels;
+}
for (int y = min_y_supertile; y <= max_y_supertile; y++) {
for (int x = min_x_supertile; x <= max_x_supertile; x++) {
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Mesa (master): broadcom/vc5: Clamp the instance divisor to 16 bits.
Module: Mesa
Branch: master
Commit: ba87d85b043bf4beecae1afda22ea42b217df2b8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba87d85b043bf4beecae1afda22ea42b217df2b8
Author: Eric Anholt <e...@anholt.net>
Date: Tue Mar 20 10:00:21 2018 -0700
broadcom/vc5: Clamp the instance divisor to 16 bits.
Fixes debug assert on
GTF-GLES3.gtf.GL3Tests.instanced_arrays.instanced_arrays_divisor
Signed-off-by: Eric Anholt <e...@anholt.net>
---
src/gallium/drivers/vc5/vc5_state.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/vc5/vc5_state.c
b/src/gallium/drivers/vc5/vc5_state.c
index 65dd9a2c42..75cd948e4a 100644
--- a/src/gallium/drivers/vc5/vc5_state.c
+++ b/src/gallium/drivers/vc5/vc5_state.c
@@ -319,7 +319,8 @@ vc5_vertex_state_create(struct pipe_context *pctx, unsigned
num_elements,
attr.normalized_int_type = desc->channel[0].normalized;
attr.read_as_int_uint = desc->channel[0].pure_integer;
-attr.instance_divisor = elem->instance_divisor;
+attr.instance_divisor = MIN2(elem->instance_divisor,
+ 0x);
switch (desc->channel[0].type) {
case UTIL_FORMAT_TYPE_FLOAT:
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Mesa (master): broadcom/vc5: Fix 3D miplevel limit to match other texture targets.
Module: Mesa Branch: master Commit: f735ac6b1ce181015db3dde698c31580b92d4725 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f735ac6b1ce181015db3dde698c31580b92d4725 Author: Eric Anholt <e...@anholt.net> Date: Tue Mar 20 10:48:11 2018 -0700 broadcom/vc5: Fix 3D miplevel limit to match other texture targets. Fixes segfault in GTF-GLES3.gtf.GL3Tests.texture_storage.texture_storage_texture_levels on level 13. --- src/gallium/drivers/vc5/vc5_screen.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/gallium/drivers/vc5/vc5_screen.c b/src/gallium/drivers/vc5/vc5_screen.c index 5f505c9a3d..add5a2f358 100644 --- a/src/gallium/drivers/vc5/vc5_screen.c +++ b/src/gallium/drivers/vc5/vc5_screen.c @@ -271,9 +271,8 @@ vc5_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) /* Texturing. */ case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: -return VC5_MAX_MIP_LEVELS; case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: -return 256; +return VC5_MAX_MIP_LEVELS; case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: return 2048; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): broadcom/vc5: Handle sparsely populated SO target array.
Module: Mesa
Branch: master
Commit: 024e814dee20a58f1d11129ffb2b4497beeacca7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=024e814dee20a58f1d11129ffb2b4497beeacca7
Author: Eric Anholt <e...@anholt.net>
Date: Tue Mar 20 11:09:02 2018 -0700
broadcom/vc5: Handle sparsely populated SO target array.
Fixes
GTF-GLES3.gtf.GL3Tests.transform_feedback.transform_feedback_state_variables
---
src/gallium/drivers/vc5/vc5_emit.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_emit.c
b/src/gallium/drivers/vc5/vc5_emit.c
index ae47fda81f..e5a9e0e03a 100644
--- a/src/gallium/drivers/vc5/vc5_emit.c
+++ b/src/gallium/drivers/vc5/vc5_emit.c
@@ -597,10 +597,13 @@ v3dX(emit_state)(struct pipe_context *pctx)
for (int i = 0; i < so->num_targets; i++) {
const struct pipe_stream_output_target *target
=
so->targets[i];
-struct vc5_resource *rsc =
-vc5_resource(target->buffer);
+struct vc5_resource *rsc = target ?
+vc5_resource(target->buffer) : NULL;
#if V3D_VERSION >= 40
+if (!target)
+continue;
+
cl_emit(>bcl, TRANSFORM_FEEDBACK_BUFFER,
output) {
output.buffer_address =
cl_address(rsc->bo,
@@ -611,13 +614,17 @@ v3dX(emit_state)(struct pipe_context *pctx)
}
#else /* V3D_VERSION < 40 */
cl_emit(>bcl,
TRANSFORM_FEEDBACK_OUTPUT_ADDRESS, output) {
-output.address =
-cl_address(rsc->bo,
-
target->buffer_offset);
+if (target) {
+output.address =
+cl_address(rsc->bo,
+
target->buffer_offset);
+}
};
#endif /* V3D_VERSION < 40 */
-vc5_job_add_write_resource(vc5->job,
- target->buffer);
+if (target) {
+vc5_job_add_write_resource(vc5->job,
+
target->buffer);
+}
/* XXX: buffer_size? */
}
} else {
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Mesa (master): intel/blorp: Fix compiler warning about num_layers.
Module: Mesa
Branch: master
Commit: 4d8b476fa9a01aef94dc2d83e9306ba7c5adbe7f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4d8b476fa9a01aef94dc2d83e9306ba7c5adbe7f
Author: Eric Anholt <e...@anholt.net>
Date: Sat Feb 10 10:29:56 2018 +
intel/blorp: Fix compiler warning about num_layers.
The compiler doesn't notice that the condition for num_layers to be
undefined already defined it above (as our assert checked in a debug
build).
v2: Move the pair of assignments to one outside of the block.
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 72c5d194ef..72578b6ea5 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1426,8 +1426,8 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw,
} else {
level = irb->mt_level;
start_layer = irb->mt_layer;
- num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
}
+ num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
stencil_mask = ctx->Stencil.WriteMask[0] & 0xff;
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Mesa (master): broadcom/vc5: Add a QPU helper for instructions using the TLB.
Module: Mesa
Branch: master
Commit: c3a504f470b8116ebcd892ce1f48125549817467
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c3a504f470b8116ebcd892ce1f48125549817467
Author: Eric Anholt <e...@anholt.net>
Date: Mon Mar 19 11:30:27 2018 -0700
broadcom/vc5: Add a QPU helper for instructions using the TLB.
This will be used for detecting last thread segment in register spilling.
---
src/broadcom/qpu/qpu_instr.c | 22 ++
src/broadcom/qpu/qpu_instr.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/src/broadcom/qpu/qpu_instr.c b/src/broadcom/qpu/qpu_instr.c
index 978d470cc6..213a0826a5 100644
--- a/src/broadcom/qpu/qpu_instr.c
+++ b/src/broadcom/qpu/qpu_instr.c
@@ -569,6 +569,28 @@ v3d_qpu_add_op_writes_vpm(enum v3d_qpu_add_op op)
}
bool
+v3d_qpu_uses_tlb(const struct v3d_qpu_instr *inst)
+{
+if (inst->sig.ldtlb ||
+inst->sig.ldtlbu)
+return true;
+
+if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
+if (inst->alu.add.magic_write &&
+v3d_qpu_magic_waddr_is_tlb(inst->alu.add.waddr)) {
+return true;
+}
+
+if (inst->alu.mul.magic_write &&
+v3d_qpu_magic_waddr_is_tlb(inst->alu.mul.waddr)) {
+return true;
+}
+}
+
+return false;
+}
+
+bool
v3d_qpu_writes_tmu(const struct v3d_qpu_instr *inst)
{
return (inst->type == V3D_QPU_INSTR_TYPE_ALU &&
diff --git a/src/broadcom/qpu/qpu_instr.h b/src/broadcom/qpu/qpu_instr.h
index 9568857f11..e5e9a9a3f1 100644
--- a/src/broadcom/qpu/qpu_instr.h
+++ b/src/broadcom/qpu/qpu_instr.h
@@ -437,6 +437,7 @@ bool v3d_qpu_magic_waddr_is_tmu(enum v3d_qpu_waddr waddr)
ATTRIBUTE_CONST;
bool v3d_qpu_magic_waddr_is_tlb(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
bool v3d_qpu_magic_waddr_is_vpm(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
bool v3d_qpu_magic_waddr_is_tsy(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
+bool v3d_qpu_uses_tlb(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
bool v3d_qpu_writes_tmu(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
bool v3d_qpu_writes_r3(const struct v3d_device_info *devinfo,
const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
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Mesa (master): broadcom/vc5: The ldvpm signal also a case of using the VPM.
Module: Mesa
Branch: master
Commit: 407f21ef1bcbd4054927aa8cc7a9f9252b389a87
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=407f21ef1bcbd4054927aa8cc7a9f9252b389a87
Author: Eric Anholt <e...@anholt.net>
Date: Mon Mar 19 11:05:03 2018 -0700
broadcom/vc5: The ldvpm signal also a case of using the VPM.
The QPU scheduling code calling this function already separately checked
this signal.
---
src/broadcom/qpu/qpu_instr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/broadcom/qpu/qpu_instr.c b/src/broadcom/qpu/qpu_instr.c
index 9603373943..506cf06d55 100644
--- a/src/broadcom/qpu/qpu_instr.c
+++ b/src/broadcom/qpu/qpu_instr.c
@@ -569,6 +569,9 @@ v3d_qpu_writes_tmu(const struct v3d_qpu_instr *inst)
bool
v3d_qpu_uses_vpm(const struct v3d_qpu_instr *inst)
{
+if (inst->sig.ldvpm)
+return true;
+
if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
if (v3d_qpu_add_op_uses_vpm(inst->alu.add.op))
return true;
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Mesa (master): broadcom/vc5: Re-do live variables after removing thrsws.
Module: Mesa
Branch: master
Commit: 55bf2983330dffafce53a2772cac078f4477988e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=55bf2983330dffafce53a2772cac078f4477988e
Author: Eric Anholt <e...@anholt.net>
Date: Fri Feb 23 17:46:35 2018 -0800
broadcom/vc5: Re-do live variables after removing thrsws.
Otherwise our start/ends ips won't line up with the actual instructions.
---
src/broadcom/compiler/nir_to_vir.c | 1 +
src/broadcom/compiler/vir_live_variables.c | 16 +---
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/src/broadcom/compiler/nir_to_vir.c
b/src/broadcom/compiler/nir_to_vir.c
index 595689d244..a8098fc320 100644
--- a/src/broadcom/compiler/nir_to_vir.c
+++ b/src/broadcom/compiler/nir_to_vir.c
@@ -1929,6 +1929,7 @@ vir_remove_thrsw(struct v3d_compile *c)
vir_remove_instruction(c, inst);
}
}
+vir_calculate_live_intervals(c);
c->last_thrsw = NULL;
}
diff --git a/src/broadcom/compiler/vir_live_variables.c
b/src/broadcom/compiler/vir_live_variables.c
index 217b716fd9..20acace1fa 100644
--- a/src/broadcom/compiler/vir_live_variables.c
+++ b/src/broadcom/compiler/vir_live_variables.c
@@ -311,10 +311,20 @@ vir_calculate_live_intervals(struct v3d_compile *c)
{
int bitset_words = BITSET_WORDS(c->num_temps);
-/* If we called this function more than once, then we should be
- * freeing the previous arrays.
+/* We may be called more than once if we've rearranged the program to
+ * try to get register allocation to succeed.
*/
-assert(!c->temp_start);
+if (c->temp_start) {
+ralloc_free(c->temp_start);
+ralloc_free(c->temp_end);
+
+vir_for_each_block(block, c) {
+ralloc_free(block->def);
+ralloc_free(block->use);
+ralloc_free(block->live_in);
+ralloc_free(block->live_out);
+}
+}
c->temp_start = rzalloc_array(c, int, c->num_temps);
c->temp_end = rzalloc_array(c, int, c->num_temps);
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Mesa (master): broadcom/vc5: Move the umul macro to a header.
Module: Mesa
Branch: master
Commit: c81d6817422c83ba990fac19b165d4dedb1150fe
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c81d6817422c83ba990fac19b165d4dedb1150fe
Author: Eric Anholt <e...@anholt.net>
Date: Tue Mar 13 16:23:33 2018 -0700
broadcom/vc5: Move the umul macro to a header.
Anywhere we want to multiply, we probably want this.
---
src/broadcom/compiler/nir_to_vir.c | 9 +
src/broadcom/compiler/v3d_compiler.h | 7 +++
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/broadcom/compiler/nir_to_vir.c
b/src/broadcom/compiler/nir_to_vir.c
index a8098fc320..61486870dc 100644
--- a/src/broadcom/compiler/nir_to_vir.c
+++ b/src/broadcom/compiler/nir_to_vir.c
@@ -256,13 +256,6 @@ vir_SAT(struct v3d_compile *c, struct qreg val)
}
static struct qreg
-ntq_umul(struct v3d_compile *c, struct qreg src0, struct qreg src1)
-{
-vir_MULTOP(c, src0, src1);
-return vir_UMUL24(c, src0, src1);
-}
-
-static struct qreg
ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
{
return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
@@ -765,7 +758,7 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
break;
case nir_op_imul:
-result = ntq_umul(c, src[0], src[1]);
+result = vir_UMUL(c, src[0], src[1]);
break;
case nir_op_seq:
diff --git a/src/broadcom/compiler/v3d_compiler.h
b/src/broadcom/compiler/v3d_compiler.h
index 94cbd0523c..f777cfcd87 100644
--- a/src/broadcom/compiler/v3d_compiler.h
+++ b/src/broadcom/compiler/v3d_compiler.h
@@ -916,6 +916,13 @@ vir_LDTMU(struct v3d_compile *c)
}
}
+static inline struct qreg
+vir_UMUL(struct v3d_compile *c, struct qreg src0, struct qreg src1)
+{
+vir_MULTOP(c, src0, src1);
+return vir_UMUL24(c, src0, src1);
+}
+
/*
static inline struct qreg
vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
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Mesa (master): broadcom/vc5: Add cursors to the compiler infrastructure, like NIR's.
Module: Mesa
Branch: master
Commit: d721348dcdb3658572c5952563d1f4d1ca0321af
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d721348dcdb3658572c5952563d1f4d1ca0321af
Author: Eric Anholt <e...@anholt.net>
Date: Tue Mar 13 15:41:16 2018 -0700
broadcom/vc5: Add cursors to the compiler infrastructure, like NIR's.
This will let me do lowering late in compilation using the same
instruction builder as we use in nir_to_vir.
---
src/broadcom/compiler/nir_to_vir.c | 9 +++-
src/broadcom/compiler/v3d_compiler.h | 43
src/broadcom/compiler/vir.c | 29 ++--
3 files changed, 73 insertions(+), 8 deletions(-)
diff --git a/src/broadcom/compiler/nir_to_vir.c
b/src/broadcom/compiler/nir_to_vir.c
index 61486870dc..c1ba1e3049 100644
--- a/src/broadcom/compiler/nir_to_vir.c
+++ b/src/broadcom/compiler/nir_to_vir.c
@@ -198,14 +198,11 @@ ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int
chan,
if (c->execute.file != QFILE_NULL) {
last_inst->dst.index = qregs[chan].index;
-/* Set the flags to the current exec mask. To insert
- * the flags push, we temporarily remove our SSA
- * instruction.
+/* Set the flags to the current exec mask.
*/
-list_del(_inst->link);
+c->cursor = vir_before_inst(last_inst);
vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
-list_addtail(_inst->link,
- >cur_block->instructions);
+c->cursor = vir_after_inst(last_inst);
vir_set_cond(last_inst, V3D_QPU_COND_IFA);
last_inst->cond_is_exec_mask = true;
diff --git a/src/broadcom/compiler/v3d_compiler.h
b/src/broadcom/compiler/v3d_compiler.h
index f777cfcd87..fdf1b13197 100644
--- a/src/broadcom/compiler/v3d_compiler.h
+++ b/src/broadcom/compiler/v3d_compiler.h
@@ -384,6 +384,48 @@ struct qblock {
/** @} */
};
+/** Which util/list.h add mode we should use when inserting an instruction. */
+enum vir_cursor_mode {
+vir_cursor_add,
+vir_cursor_addtail,
+};
+
+/**
+ * Tracking structure for where new instructions should be inserted. Create
+ * with one of the vir_after_inst()-style helper functions.
+ *
+ * This does not protect against removal of the block or instruction, so we
+ * have an assert in instruction removal to try to catch it.
+ */
+struct vir_cursor {
+enum vir_cursor_mode mode;
+struct list_head *link;
+};
+
+static inline struct vir_cursor
+vir_before_inst(struct qinst *inst)
+{
+return (struct vir_cursor){ vir_cursor_addtail, >link };
+}
+
+static inline struct vir_cursor
+vir_after_inst(struct qinst *inst)
+{
+return (struct vir_cursor){ vir_cursor_add, >link };
+}
+
+static inline struct vir_cursor
+vir_before_block(struct qblock *block)
+{
+return (struct vir_cursor){ vir_cursor_add, >instructions };
+}
+
+static inline struct vir_cursor
+vir_after_block(struct qblock *block)
+{
+return (struct vir_cursor){ vir_cursor_addtail, >instructions };
+}
+
/**
* Compiler state saved across compiler invocations, for any expensive global
* setup.
@@ -500,6 +542,7 @@ struct v3d_compile {
struct qreg undef;
uint32_t num_temps;
+struct vir_cursor cursor;
struct list_head blocks;
int next_block_index;
struct qblock *cur_block;
diff --git a/src/broadcom/compiler/vir.c b/src/broadcom/compiler/vir.c
index 7ea431036e..0b2bbf0e79 100644
--- a/src/broadcom/compiler/vir.c
+++ b/src/broadcom/compiler/vir.c
@@ -418,7 +418,16 @@ vir_branch_inst(enum v3d_qpu_branch_cond cond, struct qreg
src)
static void
vir_emit(struct v3d_compile *c, struct qinst *inst)
{
-list_addtail(>link, >cur_block->instructions);
+switch (c->cursor.mode) {
+case vir_cursor_add:
+list_add(>link, c->cursor.link);
+break;
+case vir_cursor_addtail:
+list_addtail(>link, c->cursor.link);
+break;
+}
+
+c->cursor = vir_after_inst(inst);
}
/* Updates inst to write to a new temporary, emits it, and notes the def. */
@@ -468,6 +477,7 @@ void
vir_set_emit_block(struct v3d_compile *c, struct qblock *block)
{
c->cur_block = block;
+c->cursor = vir_after_block(block);
list_addtail(>link, >blocks);
}
@@ -791,6 +801,8 @@ vir_remove_instruction(struct v3d_compile *c, struct qinst
*qinst)
if (qinst->dst.file == QFILE_TEMP)
c->defs[qinst->dst.index] = NULL;
+assert(>link != c->cursor.link);
+
list_del(>link);
Mesa (master): broadcom/vc5: Add support for register spilling.
Module: Mesa
Branch: master
Commit: facc3c6f58de88ac3707a1b8435b7fc655d13124
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=facc3c6f58de88ac3707a1b8435b7fc655d13124
Author: Eric Anholt <e...@anholt.net>
Date: Tue Mar 13 15:13:00 2018 -0700
broadcom/vc5: Add support for register spilling.
Our register spilling support is nice to have since vc4 couldn't at all,
but we're still very restricted due to needing to not spill during a TMU
operation, or during the last segment of the program (which would be nice
to spill a value of, when there's a long-lived value being passed through
with little modification from the start to the end).
We could do better by emitting unspills for the last-segment values just
before the last thrsw, since the last segment is probably not the maximum
interference area.
Fixes GTF uniform_buffer_object_arrays_of_all_valid_basic_types and 3
others.
---
src/broadcom/compiler/nir_to_vir.c| 11 +-
src/broadcom/compiler/v3d_compiler.h | 24 ++-
src/broadcom/compiler/vir.c | 8 +
src/broadcom/compiler/vir_register_allocate.c | 244 +-
src/gallium/drivers/vc5/vc5_context.h | 3 +
src/gallium/drivers/vc5/vc5_program.c | 15 ++
src/gallium/drivers/vc5/vc5_uniforms.c| 12 ++
7 files changed, 306 insertions(+), 11 deletions(-)
diff --git a/src/broadcom/compiler/nir_to_vir.c
b/src/broadcom/compiler/nir_to_vir.c
index c1ba1e3049..75e35067f2 100644
--- a/src/broadcom/compiler/nir_to_vir.c
+++ b/src/broadcom/compiler/nir_to_vir.c
@@ -1919,12 +1919,11 @@ vir_remove_thrsw(struct v3d_compile *c)
vir_remove_instruction(c, inst);
}
}
-vir_calculate_live_intervals(c);
c->last_thrsw = NULL;
}
-static void
+void
vir_emit_last_thrsw(struct v3d_compile *c)
{
/* On V3D before 4.1, we need a TMU op to be outstanding when thread
@@ -2012,16 +2011,16 @@ v3d_nir_to_vir(struct v3d_compile *c)
fprintf(stderr, "\n");
}
-/* Compute the live ranges so we can figure out interference. */
-vir_calculate_live_intervals(c);
-
/* Attempt to allocate registers for the temporaries. If we fail,
* reduce thread count and try again.
*/
int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
struct qpu_reg *temp_registers;
while (true) {
-temp_registers = v3d_register_allocate(c);
+bool spilled;
+temp_registers = v3d_register_allocate(c, );
+if (spilled)
+continue;
if (temp_registers)
break;
diff --git a/src/broadcom/compiler/v3d_compiler.h
b/src/broadcom/compiler/v3d_compiler.h
index fdf1b13197..84cc4d290a 100644
--- a/src/broadcom/compiler/v3d_compiler.h
+++ b/src/broadcom/compiler/v3d_compiler.h
@@ -248,6 +248,12 @@ enum quniform_contents {
QUNIFORM_ALPHA_REF,
QUNIFORM_SAMPLE_MASK,
+
+/**
+ * Returns the the offset of the scratch buffer for register spilling.
+ */
+QUNIFORM_SPILL_OFFSET,
+QUNIFORM_SPILL_SIZE_PER_THREAD,
};
struct v3d_varying_slot {
@@ -506,6 +512,20 @@ struct v3d_compile {
uint8_t vattr_sizes[V3D_MAX_VS_INPUTS];
uint32_t num_vpm_writes;
+/* Size in bytes of registers that have been spilled. This is how much
+ * space needs to be available in the spill BO per thread per QPU.
+ */
+uint32_t spill_size;
+/* Shader-db stats for register spilling. */
+uint32_t spills, fills;
+/**
+ * Register spilling's per-thread base address, shared between each
+ * spill/fill's addressing calculations.
+ */
+struct qreg spill_base;
+/* Bit vector of which temps may be spilled */
+BITSET_WORD *spillable;
+
/**
* Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
*
@@ -600,6 +620,7 @@ struct v3d_prog_data {
struct v3d_ubo_range *ubo_ranges;
uint32_t num_ubo_ranges;
uint32_t ubo_size;
+uint32_t spill_size;
uint8_t num_inputs;
uint8_t threads;
@@ -697,6 +718,7 @@ void vir_set_unpack(struct qinst *inst, int src,
enum v3d_qpu_input_unpack unpack);
struct qreg vir_get_temp(struct v3d_compile *c);
+void vir_emit_last_thrsw(struct v3d_compile *c);
void vir_calculate_live_intervals(struct v3d_compile *c);
bool vir_has_implicit_uniform(struct qinst *inst);
int vir_get_implicit_uniform_src(struct qinst *inst);
@@ -746,7 +768,7 @@ void v3d40_vir_emit_tex(struct v3d_compile *c,
nir_tex_instr *instr);
void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
void qpu_validate(struct v3d_
Mesa (master): broadcom/vc5: Don't annotate dumps with stale live intervals.
Module: Mesa
Branch: master
Commit: 00910e3057588de3fe9b5dc2ae9263c2e4ba6cc4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=00910e3057588de3fe9b5dc2ae9263c2e4ba6cc4
Author: Eric Anholt <e...@anholt.net>
Date: Wed Mar 14 11:03:23 2018 -0700
broadcom/vc5: Don't annotate dumps with stale live intervals.
As you're debugging register allocation, you may have changed the
intervals and not recomputed yet. Just skip the dump in that case.
---
src/broadcom/compiler/v3d_compiler.h | 1 +
src/broadcom/compiler/vir.c| 3 +++
src/broadcom/compiler/vir_dump.c | 4 ++--
src/broadcom/compiler/vir_live_variables.c | 2 ++
4 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/broadcom/compiler/v3d_compiler.h
b/src/broadcom/compiler/v3d_compiler.h
index 84cc4d290a..df81f0757e 100644
--- a/src/broadcom/compiler/v3d_compiler.h
+++ b/src/broadcom/compiler/v3d_compiler.h
@@ -548,6 +548,7 @@ struct v3d_compile {
/* Live ranges of temps. */
int *temp_start, *temp_end;
+bool live_intervals_valid;
uint32_t *uniform_data;
enum quniform_contents *uniform_contents;
diff --git a/src/broadcom/compiler/vir.c b/src/broadcom/compiler/vir.c
index 0cbdc986d3..05f557fbcd 100644
--- a/src/broadcom/compiler/vir.c
+++ b/src/broadcom/compiler/vir.c
@@ -435,6 +435,7 @@ vir_emit(struct v3d_compile *c, struct qinst *inst)
}
c->cursor = vir_after_inst(inst);
+c->live_intervals_valid = false;
}
/* Updates inst to write to a new temporary, emits it, and notes the def. */
@@ -813,6 +814,8 @@ vir_remove_instruction(struct v3d_compile *c, struct qinst
*qinst)
list_del(>link);
free(qinst);
+
+c->live_intervals_valid = false;
}
struct qreg
diff --git a/src/broadcom/compiler/vir_dump.c b/src/broadcom/compiler/vir_dump.c
index ef860cbb5c..90a3fb0ac6 100644
--- a/src/broadcom/compiler/vir_dump.c
+++ b/src/broadcom/compiler/vir_dump.c
@@ -321,7 +321,7 @@ vir_dump(struct v3d_compile *c)
vir_for_each_block(block, c) {
fprintf(stderr, "BLOCK %d:\n", block->index);
vir_for_each_inst(inst, block) {
-if (c->temp_start) {
+if (c->live_intervals_valid) {
bool first = true;
for (int i = 0; i < c->num_temps; i++) {
@@ -342,7 +342,7 @@ vir_dump(struct v3d_compile *c)
fprintf(stderr, " ");
}
-if (c->temp_end) {
+if (c->live_intervals_valid) {
bool first = true;
for (int i = 0; i < c->num_temps; i++) {
diff --git a/src/broadcom/compiler/vir_live_variables.c
b/src/broadcom/compiler/vir_live_variables.c
index 20acace1fa..019cde1456 100644
--- a/src/broadcom/compiler/vir_live_variables.c
+++ b/src/broadcom/compiler/vir_live_variables.c
@@ -347,4 +347,6 @@ vir_calculate_live_intervals(struct v3d_compile *c)
;
vir_compute_start_end(c, c->num_temps);
+
+c->live_intervals_valid = true;
}
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Mesa (master): broadcom/vc5: Remove redundant last_inst lookup.
Module: Mesa
Branch: master
Commit: 271fc58ba1b9e6a0245c7ab262834705f2e20372
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=271fc58ba1b9e6a0245c7ab262834705f2e20372
Author: Eric Anholt <e...@anholt.net>
Date: Wed Mar 14 14:43:15 2018 -0700
broadcom/vc5: Remove redundant last_inst lookup.
The point was to get the MOV, which the MOV_dest already returned.
---
src/broadcom/compiler/vir.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/broadcom/compiler/vir.c b/src/broadcom/compiler/vir.c
index 0b2bbf0e79..6a315dd482 100644
--- a/src/broadcom/compiler/vir.c
+++ b/src/broadcom/compiler/vir.c
@@ -900,7 +900,6 @@ vir_PF(struct v3d_compile *c, struct qreg src, enum
v3d_qpu_pf pf)
last_inst != c->defs[src.index]) {
/* XXX: Make the MOV be the appropriate type */
last_inst = vir_MOV_dest(c, vir_reg(QFILE_NULL, 0), src);
-last_inst = (struct qinst *)c->cur_block->instructions.prev;
}
vir_set_pf(last_inst, pf);
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Mesa (master): broadcom/vc5: Introduce v3d_qpu_reads_vpm()/v3d_qpu_writes_vpm().
Module: Mesa
Branch: master
Commit: 09c4dd19713b3155bd744f873e91e0328be62978
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=09c4dd19713b3155bd744f873e91e0328be62978
Author: Eric Anholt <e...@anholt.net>
Date: Mon Mar 19 11:03:47 2018 -0700
broadcom/vc5: Introduce v3d_qpu_reads_vpm()/v3d_qpu_writes_vpm().
These helpers will be used in register spilling to determine where to add
a last thrsw if needed, and might help refactor QPU scheduling.
---
src/broadcom/qpu/qpu_instr.c | 35 ---
src/broadcom/qpu/qpu_instr.h | 4 +++-
2 files changed, 35 insertions(+), 4 deletions(-)
diff --git a/src/broadcom/qpu/qpu_instr.c b/src/broadcom/qpu/qpu_instr.c
index 506cf06d55..978d470cc6 100644
--- a/src/broadcom/qpu/qpu_instr.c
+++ b/src/broadcom/qpu/qpu_instr.c
@@ -535,7 +535,7 @@ v3d_qpu_magic_waddr_is_tsy(enum v3d_qpu_waddr waddr)
}
static bool
-v3d_qpu_add_op_uses_vpm(enum v3d_qpu_add_op op)
+v3d_qpu_add_op_reads_vpm(enum v3d_qpu_add_op op)
{
switch (op) {
case V3D_QPU_A_VPMSETUP:
@@ -547,6 +547,18 @@ v3d_qpu_add_op_uses_vpm(enum v3d_qpu_add_op op)
case V3D_QPU_A_LDVPMP:
case V3D_QPU_A_LDVPMG_IN:
case V3D_QPU_A_LDVPMG_OUT:
+return true;
+default:
+return false;
+}
+}
+
+static bool
+v3d_qpu_add_op_writes_vpm(enum v3d_qpu_add_op op)
+{
+switch (op) {
+case V3D_QPU_A_VPMSETUP:
+case V3D_QPU_A_VPMWT:
case V3D_QPU_A_STVPMV:
case V3D_QPU_A_STVPMD:
case V3D_QPU_A_STVPMP:
@@ -567,13 +579,24 @@ v3d_qpu_writes_tmu(const struct v3d_qpu_instr *inst)
}
bool
-v3d_qpu_uses_vpm(const struct v3d_qpu_instr *inst)
+v3d_qpu_reads_vpm(const struct v3d_qpu_instr *inst)
{
if (inst->sig.ldvpm)
return true;
if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
-if (v3d_qpu_add_op_uses_vpm(inst->alu.add.op))
+if (v3d_qpu_add_op_reads_vpm(inst->alu.add.op))
+return true;
+}
+
+return false;
+}
+
+bool
+v3d_qpu_writes_vpm(const struct v3d_qpu_instr *inst)
+{
+if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
+if (v3d_qpu_add_op_writes_vpm(inst->alu.add.op))
return true;
if (inst->alu.add.magic_write &&
@@ -591,6 +614,12 @@ v3d_qpu_uses_vpm(const struct v3d_qpu_instr *inst)
}
bool
+v3d_qpu_uses_vpm(const struct v3d_qpu_instr *inst)
+{
+return v3d_qpu_reads_vpm(inst) || v3d_qpu_writes_vpm(inst);
+}
+
+bool
v3d_qpu_writes_r3(const struct v3d_device_info *devinfo,
const struct v3d_qpu_instr *inst)
{
diff --git a/src/broadcom/qpu/qpu_instr.h b/src/broadcom/qpu/qpu_instr.h
index 39232b0e61..9568857f11 100644
--- a/src/broadcom/qpu/qpu_instr.h
+++ b/src/broadcom/qpu/qpu_instr.h
@@ -445,7 +445,9 @@ bool v3d_qpu_writes_r4(const struct v3d_device_info
*devinfo,
bool v3d_qpu_writes_r5(const struct v3d_device_info *devinfo,
const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
bool v3d_qpu_uses_mux(const struct v3d_qpu_instr *inst, enum v3d_qpu_mux mux);
-bool v3d_qpu_uses_vpm(const struct v3d_qpu_instr *inst);
+bool v3d_qpu_uses_vpm(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
+bool v3d_qpu_reads_vpm(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
+bool v3d_qpu_writes_vpm(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
bool v3d_qpu_sig_writes_address(const struct v3d_device_info *devinfo,
const struct v3d_qpu_sig *sig) ATTRIBUTE_CONST;
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Mesa (master): broadcom/vc5: Extract v3d_qpu_writes_tmu() helper.
Module: Mesa
Branch: master
Commit: 4760040c0980a8921120d517d5e5809f7f0e488c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4760040c0980a8921120d517d5e5809f7f0e488c
Author: Eric Anholt <e...@anholt.net>
Date: Wed Mar 14 15:04:32 2018 -0700
broadcom/vc5: Extract v3d_qpu_writes_tmu() helper.
This will be reused in register spilling.
---
src/broadcom/compiler/qpu_schedule.c | 7 +--
src/broadcom/qpu/qpu_instr.c | 10 ++
src/broadcom/qpu/qpu_instr.h | 1 +
3 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/src/broadcom/compiler/qpu_schedule.c
b/src/broadcom/compiler/qpu_schedule.c
index 3ced2a4949..b404390a79 100644
--- a/src/broadcom/compiler/qpu_schedule.c
+++ b/src/broadcom/compiler/qpu_schedule.c
@@ -588,13 +588,8 @@ get_instruction_priority(const struct v3d_qpu_instr *inst)
next_score++;
/* Schedule texture read setup early to hide their latency better. */
-if (inst->type == V3D_QPU_INSTR_TYPE_ALU &&
-((inst->alu.add.magic_write &&
- v3d_qpu_magic_waddr_is_tmu(inst->alu.add.waddr)) ||
- (inst->alu.mul.magic_write &&
- v3d_qpu_magic_waddr_is_tmu(inst->alu.mul.waddr {
+if (v3d_qpu_writes_tmu(inst))
return next_score;
-}
next_score++;
return baseline_score;
diff --git a/src/broadcom/qpu/qpu_instr.c b/src/broadcom/qpu/qpu_instr.c
index f31c81f8ca..9603373943 100644
--- a/src/broadcom/qpu/qpu_instr.c
+++ b/src/broadcom/qpu/qpu_instr.c
@@ -557,6 +557,16 @@ v3d_qpu_add_op_uses_vpm(enum v3d_qpu_add_op op)
}
bool
+v3d_qpu_writes_tmu(const struct v3d_qpu_instr *inst)
+{
+return (inst->type == V3D_QPU_INSTR_TYPE_ALU &&
+((inst->alu.add.magic_write &&
+ v3d_qpu_magic_waddr_is_tmu(inst->alu.add.waddr)) ||
+ (inst->alu.mul.magic_write &&
+ v3d_qpu_magic_waddr_is_tmu(inst->alu.mul.waddr;
+}
+
+bool
v3d_qpu_uses_vpm(const struct v3d_qpu_instr *inst)
{
if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
diff --git a/src/broadcom/qpu/qpu_instr.h b/src/broadcom/qpu/qpu_instr.h
index 2289e18225..39232b0e61 100644
--- a/src/broadcom/qpu/qpu_instr.h
+++ b/src/broadcom/qpu/qpu_instr.h
@@ -437,6 +437,7 @@ bool v3d_qpu_magic_waddr_is_tmu(enum v3d_qpu_waddr waddr)
ATTRIBUTE_CONST;
bool v3d_qpu_magic_waddr_is_tlb(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
bool v3d_qpu_magic_waddr_is_vpm(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
bool v3d_qpu_magic_waddr_is_tsy(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
+bool v3d_qpu_writes_tmu(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
bool v3d_qpu_writes_r3(const struct v3d_device_info *devinfo,
const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
bool v3d_qpu_writes_r4(const struct v3d_device_info *devinfo,
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Mesa (master): broadcom/vc5: On QPU pack error, dump the instruction and return cleanly.
Module: Mesa
Branch: master
Commit: 34dc64f6274db73851b0f1e5f0440a9785cafd6c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=34dc64f6274db73851b0f1e5f0440a9785cafd6c
Author: Eric Anholt <e...@anholt.net>
Date: Wed Mar 14 14:39:51 2018 -0700
broadcom/vc5: On QPU pack error, dump the instruction and return cleanly.
This is nice for debugging when you've made a bad instruction.
---
src/broadcom/compiler/vir_to_qpu.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/broadcom/compiler/vir_to_qpu.c
b/src/broadcom/compiler/vir_to_qpu.c
index 568a004803..83b1936cbd 100644
--- a/src/broadcom/compiler/vir_to_qpu.c
+++ b/src/broadcom/compiler/vir_to_qpu.c
@@ -388,7 +388,13 @@ v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg
*temp_registers)
vir_for_each_inst_inorder(inst, c) {
bool ok = v3d_qpu_instr_pack(c->devinfo, >qpu,
>qpu_insts[i++]);
-assert(ok); (void) ok;
+if (!ok) {
+fprintf(stderr, "Failed to pack instruction:\n");
+vir_dump_inst(c, inst);
+fprintf(stderr, "\n");
+c->failed = true;
+return;
+}
}
assert(i == c->qpu_inst_count);
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Mesa (master): anv: Silence warning about heap_size.
Module: Mesa Branch: master Commit: 7db1c09d12bac50d66feaf981ff52b319091dd2d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7db1c09d12bac50d66feaf981ff52b319091dd2d Author: Eric Anholt <e...@anholt.net> Date: Sat Feb 10 11:25:48 2018 + anv: Silence warning about heap_size. We only get VK_SUCCESS if it was initialized, but apparently my compiler doesn't track that far. Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> --- src/intel/vulkan/anv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 82b237e76d..4cacba9343 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -110,7 +110,7 @@ anv_physical_device_init_heaps(struct anv_physical_device *device, int fd) device->supports_48bit_addresses = (device->info.gen >= 8) && anv_gem_supports_48b_addresses(fd); - uint64_t heap_size; + uint64_t heap_size = 0; VkResult result = anv_compute_heap_size(fd, _size); if (result != VK_SUCCESS) return result; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv: Silence compiler warnings about uninitialized bind_offset.
Module: Mesa
Branch: master
Commit: 9f89452ea36327b1a7faefd401784599288c1be0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f89452ea36327b1a7faefd401784599288c1be0
Author: Eric Anholt <e...@anholt.net>
Date: Sat Feb 10 11:11:14 2018 +
anv: Silence compiler warnings about uninitialized bind_offset.
This is a legitimate warning: if anv's blorp_alloc_binding_table() throws
an error from anv_cmd_buffer_alloc_blorp_binding_table(), we silently
continue to use this undefined value. The rest of this code doesn't seem
very allocation-error-proof, though, either.
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
src/intel/blorp/blorp_genX_exec.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/blorp/blorp_genX_exec.h
b/src/intel/blorp/blorp_genX_exec.h
index b612709035..992bc9959a 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1388,7 +1388,7 @@ blorp_emit_surface_states(struct blorp_batch *batch,
const struct blorp_params *params)
{
const struct isl_device *isl_dev = batch->blorp->isl_dev;
- uint32_t bind_offset, surface_offsets[2];
+ uint32_t bind_offset = 0, surface_offsets[2];
void *surface_maps[2];
MAYBE_UNUSED bool has_indirect_clear_color = false;
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Mesa (master): i965: Silence compiler warning about promoted_constants.
Module: Mesa
Branch: master
Commit: d25640c3a3b914059abd661f0651d88b4fe408e8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d25640c3a3b914059abd661f0651d88b4fe408e8
Author: Eric Anholt <e...@anholt.net>
Date: Sat Feb 10 11:22:53 2018 +
i965: Silence compiler warning about promoted_constants.
We only have a cfg != NULL if we went through one of the paths that set
it, but my compiler doesn't figure that out.
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Fixes: 6411defdcd6f ("intel/cs: Re-run final NIR optimizations for each SIMD
size")
---
src/intel/compiler/brw_fs.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index f65e5d9d8b..6eea532f56 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -7223,7 +7223,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void
*log_data,
fs_visitor *v8 = NULL, *v16 = NULL, *v32 = NULL;
cfg_t *cfg = NULL;
const char *fail_msg = NULL;
- unsigned promoted_constants;
+ unsigned promoted_constants = 0;
/* Now the main event: Visit the shader IR and generate our CS IR for it.
*/
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