Mesa (master): i965: use BLT to clear buffer if possible on Sandybridge
Module: Mesa
Branch: master
Commit: 266d8eed6927650a55974a293959fe21073030bb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=266d8eed6927650a55974a293959fe21073030bb
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Wed Jan 5 13:32:40 2011 +0800
i965: use BLT to clear buffer if possible on Sandybridge
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=32713
---
src/mesa/drivers/dri/intel/intel_clear.c |6 --
1 files changed, 0 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_clear.c
b/src/mesa/drivers/dri/intel/intel_clear.c
index 8472911..82d29e7 100644
--- a/src/mesa/drivers/dri/intel/intel_clear.c
+++ b/src/mesa/drivers/dri/intel/intel_clear.c
@@ -169,12 +169,6 @@ intelClear(struct gl_context *ctx, GLbitfield mask)
}
}
- if (intel-gen = 6) {
- /* Blits are in a different ringbuffer so we don't use them. */
- tri_mask |= blit_mask;
- blit_mask = 0;
- }
-
/* Anything left, just use tris */
tri_mask |= mask ~blit_mask;
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Mesa (7.10): i965: use BLT to clear buffer if possible on Sandybridge
Module: Mesa
Branch: 7.10
Commit: 4e8f123f14e4a5bbd47c8cf7ec0c02d4ee6efd2d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e8f123f14e4a5bbd47c8cf7ec0c02d4ee6efd2d
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Wed Jan 5 13:32:40 2011 +0800
i965: use BLT to clear buffer if possible on Sandybridge
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=32713
(cherry picked from commit 266d8eed6927650a55974a293959fe21073030bb)
---
src/mesa/drivers/dri/intel/intel_clear.c |6 --
1 files changed, 0 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_clear.c
b/src/mesa/drivers/dri/intel/intel_clear.c
index 8472911..82d29e7 100644
--- a/src/mesa/drivers/dri/intel/intel_clear.c
+++ b/src/mesa/drivers/dri/intel/intel_clear.c
@@ -169,12 +169,6 @@ intelClear(struct gl_context *ctx, GLbitfield mask)
}
}
- if (intel-gen = 6) {
- /* Blits are in a different ringbuffer so we don't use them. */
- tri_mask |= blit_mask;
- blit_mask = 0;
- }
-
/* Anything left, just use tris */
tri_mask |= mask ~blit_mask;
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Mesa (7.10): mesa/meta: fix broken assertion, rename stack depth var
Module: Mesa
Branch: 7.10
Commit: 604009fa77ec00d1366a97edaaece22f3a7b04e2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=604009fa77ec00d1366a97edaaece22f3a7b04e2
Author: Brian Paul bri...@vmware.com
Date: Fri Dec 10 10:02:33 2010 -0700
mesa/meta: fix broken assertion, rename stack depth var
assert(current_save_state MAX_META_OPS_DEPTH) did not compile.
Rename current_save_state to SaveStackDepth to be more consistent with
the style of the other fields.
(cherry picked from commit 2a4df8933eaeb0bd0d6e63fee3d23a47c4b3adb7)
---
src/mesa/drivers/common/meta.c | 12 +++-
1 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index cbc0512..cdb2500 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -272,8 +272,10 @@ struct gen_mipmap_state
*/
struct gl_meta_state
{
- struct save_state Save[MAX_META_OPS_DEPTH];/** state saved during
meta-ops */
- int current_save_state;
+ /** Stack of state saved during meta-ops */
+ struct save_state Save[MAX_META_OPS_DEPTH];
+ /** Save stack depth */
+ GLuint SaveStackDepth;
struct temp_texture TempTex;
@@ -328,9 +330,9 @@ _mesa_meta_begin(struct gl_context *ctx, GLbitfield state)
struct save_state *save;
/* hope MAX_META_OPS_DEPTH is large enough */
- assert(current_save_state MAX_META_OPS_DEPTH);
+ assert(ctx-Meta-SaveStackDepth MAX_META_OPS_DEPTH);
- save = ctx-Meta-Save[ctx-Meta-current_save_state++];
+ save = ctx-Meta-Save[ctx-Meta-SaveStackDepth++];
memset(save, 0, sizeof(*save));
save-SavedState = state;
@@ -581,7 +583,7 @@ _mesa_meta_begin(struct gl_context *ctx, GLbitfield state)
static void
_mesa_meta_end(struct gl_context *ctx)
{
- struct save_state *save = ctx-Meta-Save[--ctx-Meta-current_save_state];
+ struct save_state *save = ctx-Meta-Save[--ctx-Meta-SaveStackDepth];
const GLbitfield state = save-SavedState;
if (state META_ALPHA_TEST) {
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Mesa (7.10): meta: allow nested meta operations
Module: Mesa
Branch: 7.10
Commit: 7e856fd0430a6d4272b60511b9aac06c91c24887
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e856fd0430a6d4272b60511b9aac06c91c24887
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Fri Dec 10 09:31:19 2010 +0800
meta: allow nested meta operations
_mesa_meta_CopyPixels results in nested meta operations on Sandybridge.
Previoulsy the second meta operation overrides all states saved by the
first meta function.
(cherry picked from commit d1196bbc191c4f1b355d432dcb2eeff9790fda34)
---
src/mesa/drivers/common/meta.c | 14 ++
1 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 95accc1..cbc0512 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -266,13 +266,14 @@ struct gen_mipmap_state
GLuint FBO;
};
-
+#define MAX_META_OPS_DEPTH 2
/**
* All per-context meta state.
*/
struct gl_meta_state
{
- struct save_state Save;/** state saved during meta-ops */
+ struct save_state Save[MAX_META_OPS_DEPTH];/** state saved during
meta-ops */
+ int current_save_state;
struct temp_texture TempTex;
@@ -324,8 +325,13 @@ _mesa_meta_free(struct gl_context *ctx)
static void
_mesa_meta_begin(struct gl_context *ctx, GLbitfield state)
{
- struct save_state *save = ctx-Meta-Save;
+ struct save_state *save;
+
+ /* hope MAX_META_OPS_DEPTH is large enough */
+ assert(current_save_state MAX_META_OPS_DEPTH);
+ save = ctx-Meta-Save[ctx-Meta-current_save_state++];
+ memset(save, 0, sizeof(*save));
save-SavedState = state;
if (state META_ALPHA_TEST) {
@@ -575,7 +581,7 @@ _mesa_meta_begin(struct gl_context *ctx, GLbitfield state)
static void
_mesa_meta_end(struct gl_context *ctx)
{
- struct save_state *save = ctx-Meta-Save;
+ struct save_state *save = ctx-Meta-Save[--ctx-Meta-current_save_state];
const GLbitfield state = save-SavedState;
if (state META_ALPHA_TEST) {
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Mesa (7.10): i965: support for two-sided lighting on Sandybridge
Module: Mesa
Branch: 7.10
Commit: 639f595fa0d1872973c7a5f8c8f40185d397ea6f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=639f595fa0d1872973c7a5f8c8f40185d397ea6f
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Fri Dec 10 13:01:44 2010 +0800
i965: support for two-sided lighting on Sandybridge
VS places color attributes together so that SF unit can fetch the right
attribute according to object orientation. This fixes light issue in
mesa demo geartrain, projtex.
(cherry picked from commit e47eacdc53aec6743c42c8d9ab8298f802161733)
---
src/mesa/drivers/dri/i965/brw_defines.h |7 +
src/mesa/drivers/dri/i965/brw_vs.c|3 +-
src/mesa/drivers/dri/i965/brw_vs.h|1 +
src/mesa/drivers/dri/i965/brw_vs_emit.c | 35 +++-
src/mesa/drivers/dri/i965/gen6_sf_state.c | 32 --
5 files changed, 72 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 5c5b825..7f3e498 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1029,6 +1029,13 @@
# define ATTRIBUTE_0_CONST_SOURCE_SHIFT9
# define ATTRIBUTE_0_SWIZZLE_SHIFT 6
# define ATTRIBUTE_0_SOURCE_SHIFT 0
+
+# define ATTRIBUTE_SWIZZLE_INPUTATTR0
+# define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING 1
+# define ATTRIBUTE_SWIZZLE_INPUTATTR_W 2
+# define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING_W 3
+# define ATTRIBUTE_SWIZZLE_SHIFT6
+
/* DW16: Point sprite texture coordinate enables */
/* DW17: Constant interpolation enables */
/* DW18: attr 0-7 wrap shortest enables */
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c
b/src/mesa/drivers/dri/i965/brw_vs.c
index 59f270d..6ae75d2 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -130,6 +130,7 @@ static void brw_upload_vs_prog(struct brw_context *brw)
key.nr_userclip = brw_count_bits(ctx-Transform.ClipPlanesEnabled);
key.copy_edgeflag = (ctx-Polygon.FrontMode != GL_FILL ||
ctx-Polygon.BackMode != GL_FILL);
+ key.two_side_color = (ctx-Light.Enabled ctx-Light.Model.TwoSide);
/* _NEW_POINT */
if (ctx-Point.PointSprite) {
@@ -157,7 +158,7 @@ static void brw_upload_vs_prog(struct brw_context *brw)
*/
const struct brw_tracked_state brw_vs_prog = {
.dirty = {
- .mesa = _NEW_TRANSFORM | _NEW_POLYGON | _NEW_POINT,
+ .mesa = _NEW_TRANSFORM | _NEW_POLYGON | _NEW_POINT | _NEW_LIGHT,
.brw = BRW_NEW_VERTEX_PROGRAM,
.cache = 0
},
diff --git a/src/mesa/drivers/dri/i965/brw_vs.h
b/src/mesa/drivers/dri/i965/brw_vs.h
index 9338a6b..0b88cc1 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.h
+++ b/src/mesa/drivers/dri/i965/brw_vs.h
@@ -44,6 +44,7 @@ struct brw_vs_prog_key {
GLuint nr_userclip:4;
GLuint copy_edgeflag:1;
GLuint point_coord_replace:8;
+ GLuint two_side_color: 1;
};
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c
b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index b7771e6..b5dd58d 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -140,11 +140,13 @@ clear_current_const(struct brw_vs_compile *c)
static void brw_vs_alloc_regs( struct brw_vs_compile *c )
{
struct intel_context *intel = c-func.brw-intel;
- GLuint i, reg = 0, mrf;
+ GLuint i, reg = 0, mrf, j;
int attributes_in_vue;
int first_reladdr_output;
int max_constant;
int constant = 0;
+ int vert_result_reoder[VERT_RESULT_MAX];
+ int bfc = 0;
/* Determine whether to use a real constant buffer or use a block
* of GRF registers for constants. The later is faster but only
@@ -291,7 +293,36 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
mrf = 4;
first_reladdr_output = get_first_reladdr_output(c-vp-program);
- for (i = 0; i VERT_RESULT_MAX; i++) {
+
+ for (i = 0; i VERT_RESULT_MAX; i++)
+ vert_result_reoder[i] = i;
+
+ /* adjust attribute order in VUE for BFC0/BFC1 on Gen6+ */
+ if (intel-gen = 6 c-key.two_side_color) {
+ if ((c-prog_data.outputs_written BITFIELD64_BIT(VERT_RESULT_COL1))
+ (c-prog_data.outputs_written BITFIELD64_BIT(VERT_RESULT_BFC1))) {
+ assert(c-prog_data.outputs_written
BITFIELD64_BIT(VERT_RESULT_COL0));
+ assert(c-prog_data.outputs_written
BITFIELD64_BIT(VERT_RESULT_BFC0));
+ bfc = 2;
+ } else if ((c-prog_data.outputs_written
BITFIELD64_BIT(VERT_RESULT_COL0))
+ (c-prog_data.outputs_written BITFIELD64_BIT(VERT_RESULT_BFC0)))
+ bfc = 1;
+
+ if (bfc) {
+ for (i = 0; i bfc; i++) {
+ vert_result_reoder[VERT_RESULT_COL0 + i * 2 + 0] =
VERT_RESULT_COL0 + i;
+ vert_result_reoder[VERT_RESULT_COL0 + i * 2 + 1] =
Mesa (7.10): i965: fix register region description
Module: Mesa Branch: 7.10 Commit: 8953ac25705f2971913b91e8fac3179c6d033ba5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8953ac25705f2971913b91e8fac3179c6d033ba5 Author: Xiang, Haihao haihao.xi...@intel.com Date: Fri Dec 24 09:24:08 2010 +0800 i965: fix register region description This fixes brw_eu_emit.c:179: validate_reg: Assertion `width == 1' failed. (cherry picked from commit 82493216044b0320219fc631baa7b02381daa0de) --- src/mesa/drivers/dri/i965/brw_vs_emit.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index b5dd58d..656292c 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -1122,7 +1122,7 @@ get_constant(struct brw_vs_compile *c, } /* replicate lower four floats into upper half (to get XYZWXYZW) */ - const_reg = stride(const_reg, 0, 4, 0); + const_reg = stride(const_reg, 0, 4, 1); const_reg.subnr = 0; return const_reg; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (7.10): i965: use align1 access mode for instructions with execSize= 1 in VS
Module: Mesa Branch: 7.10 Commit: 1988cba847386f5e03703137136c4fee08318ba2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1988cba847386f5e03703137136c4fee08318ba2 Author: Xiang, Haihao haihao.xi...@intel.com Date: Fri Dec 24 09:34:50 2010 +0800 i965: use align1 access mode for instructions with execSize=1 in VS All operands must be 16-bytes aligned in aligh16 mode. This fixes l_xxx.c in oglconform. (cherry picked from commit dc987adc9f5f9f851be124985fa6bbcdbfa4a7a5) --- src/mesa/drivers/dri/i965/brw_eu_emit.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index c01e752..ad6eb85 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -1723,6 +1723,7 @@ void brw_dp_READ_4_vs(struct brw_compile *p, /* Setup MRF[1] with location/offset into const buffer */ brw_push_insn_state(p); + brw_set_access_mode(p, BRW_ALIGN_1); brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_set_mask_control(p, BRW_MASK_DISABLE); brw_set_predicate_control(p, BRW_PREDICATE_NONE); @@ -1766,6 +1767,7 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p, /* Setup MRF[1] with offset into const buffer */ brw_push_insn_state(p); + brw_set_access_mode(p, BRW_ALIGN_1); brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_set_mask_control(p, BRW_MASK_DISABLE); brw_set_predicate_control(p, BRW_PREDICATE_NONE); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: fix register region description
Module: Mesa Branch: master Commit: 82493216044b0320219fc631baa7b02381daa0de URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=82493216044b0320219fc631baa7b02381daa0de Author: Xiang, Haihao haihao.xi...@intel.com Date: Fri Dec 24 09:24:08 2010 +0800 i965: fix register region description This fixes brw_eu_emit.c:179: validate_reg: Assertion `width == 1' failed. --- src/mesa/drivers/dri/i965/brw_vs_emit.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 326bb1e..a64188a 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -1136,7 +1136,7 @@ get_constant(struct brw_vs_compile *c, } /* replicate lower four floats into upper half (to get XYZWXYZW) */ - const_reg = stride(const_reg, 0, 4, 0); + const_reg = stride(const_reg, 0, 4, 1); const_reg.subnr = 0; return const_reg; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: use align1 access mode for instructions with execSize= 1 in VS
Module: Mesa Branch: master Commit: dc987adc9f5f9f851be124985fa6bbcdbfa4a7a5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc987adc9f5f9f851be124985fa6bbcdbfa4a7a5 Author: Xiang, Haihao haihao.xi...@intel.com Date: Fri Dec 24 09:34:50 2010 +0800 i965: use align1 access mode for instructions with execSize=1 in VS All operands must be 16-bytes aligned in aligh16 mode. This fixes l_xxx.c in oglconform. --- src/mesa/drivers/dri/i965/brw_eu_emit.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index f8a3044..88131c4 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -1727,6 +1727,7 @@ void brw_dp_READ_4_vs(struct brw_compile *p, /* Setup MRF[1] with location/offset into const buffer */ brw_push_insn_state(p); + brw_set_access_mode(p, BRW_ALIGN_1); brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_set_mask_control(p, BRW_MASK_DISABLE); brw_set_predicate_control(p, BRW_PREDICATE_NONE); @@ -1774,6 +1775,7 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p, /* Setup MRF[1] with offset into const buffer */ brw_push_insn_state(p); + brw_set_access_mode(p, BRW_ALIGN_1); brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_set_mask_control(p, BRW_MASK_DISABLE); brw_set_predicate_control(p, BRW_PREDICATE_NONE); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: support for two-sided lighting on Sandybridge
Module: Mesa
Branch: master
Commit: e47eacdc53aec6743c42c8d9ab8298f802161733
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e47eacdc53aec6743c42c8d9ab8298f802161733
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Fri Dec 10 13:01:44 2010 +0800
i965: support for two-sided lighting on Sandybridge
VS places color attributes together so that SF unit can fetch the right
attribute according to object orientation. This fixes light issue in
mesa demo geartrain, projtex.
---
src/mesa/drivers/dri/i965/brw_defines.h |7 +
src/mesa/drivers/dri/i965/brw_vs.c|3 +-
src/mesa/drivers/dri/i965/brw_vs.h|1 +
src/mesa/drivers/dri/i965/brw_vs_emit.c | 35 +++-
src/mesa/drivers/dri/i965/gen6_sf_state.c | 32 --
5 files changed, 72 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 5c5b825..7f3e498 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1029,6 +1029,13 @@
# define ATTRIBUTE_0_CONST_SOURCE_SHIFT9
# define ATTRIBUTE_0_SWIZZLE_SHIFT 6
# define ATTRIBUTE_0_SOURCE_SHIFT 0
+
+# define ATTRIBUTE_SWIZZLE_INPUTATTR0
+# define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING 1
+# define ATTRIBUTE_SWIZZLE_INPUTATTR_W 2
+# define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING_W 3
+# define ATTRIBUTE_SWIZZLE_SHIFT6
+
/* DW16: Point sprite texture coordinate enables */
/* DW17: Constant interpolation enables */
/* DW18: attr 0-7 wrap shortest enables */
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c
b/src/mesa/drivers/dri/i965/brw_vs.c
index 59f270d..6ae75d2 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -130,6 +130,7 @@ static void brw_upload_vs_prog(struct brw_context *brw)
key.nr_userclip = brw_count_bits(ctx-Transform.ClipPlanesEnabled);
key.copy_edgeflag = (ctx-Polygon.FrontMode != GL_FILL ||
ctx-Polygon.BackMode != GL_FILL);
+ key.two_side_color = (ctx-Light.Enabled ctx-Light.Model.TwoSide);
/* _NEW_POINT */
if (ctx-Point.PointSprite) {
@@ -157,7 +158,7 @@ static void brw_upload_vs_prog(struct brw_context *brw)
*/
const struct brw_tracked_state brw_vs_prog = {
.dirty = {
- .mesa = _NEW_TRANSFORM | _NEW_POLYGON | _NEW_POINT,
+ .mesa = _NEW_TRANSFORM | _NEW_POLYGON | _NEW_POINT | _NEW_LIGHT,
.brw = BRW_NEW_VERTEX_PROGRAM,
.cache = 0
},
diff --git a/src/mesa/drivers/dri/i965/brw_vs.h
b/src/mesa/drivers/dri/i965/brw_vs.h
index 9338a6b..0b88cc1 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.h
+++ b/src/mesa/drivers/dri/i965/brw_vs.h
@@ -44,6 +44,7 @@ struct brw_vs_prog_key {
GLuint nr_userclip:4;
GLuint copy_edgeflag:1;
GLuint point_coord_replace:8;
+ GLuint two_side_color: 1;
};
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c
b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index add5e39..09887da 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -140,11 +140,13 @@ clear_current_const(struct brw_vs_compile *c)
static void brw_vs_alloc_regs( struct brw_vs_compile *c )
{
struct intel_context *intel = c-func.brw-intel;
- GLuint i, reg = 0, mrf;
+ GLuint i, reg = 0, mrf, j;
int attributes_in_vue;
int first_reladdr_output;
int max_constant;
int constant = 0;
+ int vert_result_reoder[VERT_RESULT_MAX];
+ int bfc = 0;
/* Determine whether to use a real constant buffer or use a block
* of GRF registers for constants. The later is faster but only
@@ -291,7 +293,36 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
mrf = 4;
first_reladdr_output = get_first_reladdr_output(c-vp-program);
- for (i = 0; i VERT_RESULT_MAX; i++) {
+
+ for (i = 0; i VERT_RESULT_MAX; i++)
+ vert_result_reoder[i] = i;
+
+ /* adjust attribute order in VUE for BFC0/BFC1 on Gen6+ */
+ if (intel-gen = 6 c-key.two_side_color) {
+ if ((c-prog_data.outputs_written BITFIELD64_BIT(VERT_RESULT_COL1))
+ (c-prog_data.outputs_written BITFIELD64_BIT(VERT_RESULT_BFC1))) {
+ assert(c-prog_data.outputs_written
BITFIELD64_BIT(VERT_RESULT_COL0));
+ assert(c-prog_data.outputs_written
BITFIELD64_BIT(VERT_RESULT_BFC0));
+ bfc = 2;
+ } else if ((c-prog_data.outputs_written
BITFIELD64_BIT(VERT_RESULT_COL0))
+ (c-prog_data.outputs_written BITFIELD64_BIT(VERT_RESULT_BFC0)))
+ bfc = 1;
+
+ if (bfc) {
+ for (i = 0; i bfc; i++) {
+ vert_result_reoder[VERT_RESULT_COL0 + i * 2 + 0] =
VERT_RESULT_COL0 + i;
+ vert_result_reoder[VERT_RESULT_COL0 + i * 2 + 1] =
VERT_RESULT_BFC0 + i;
+ }
+
+ for (i =
Mesa (master): meta: allow nested meta operations
Module: Mesa
Branch: master
Commit: d1196bbc191c4f1b355d432dcb2eeff9790fda34
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1196bbc191c4f1b355d432dcb2eeff9790fda34
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Fri Dec 10 09:31:19 2010 +0800
meta: allow nested meta operations
_mesa_meta_CopyPixels results in nested meta operations on Sandybridge.
Previoulsy the second meta operation overrides all states saved by the
first meta function.
---
src/mesa/drivers/common/meta.c | 14 ++
1 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 95accc1..cbc0512 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -266,13 +266,14 @@ struct gen_mipmap_state
GLuint FBO;
};
-
+#define MAX_META_OPS_DEPTH 2
/**
* All per-context meta state.
*/
struct gl_meta_state
{
- struct save_state Save;/** state saved during meta-ops */
+ struct save_state Save[MAX_META_OPS_DEPTH];/** state saved during
meta-ops */
+ int current_save_state;
struct temp_texture TempTex;
@@ -324,8 +325,13 @@ _mesa_meta_free(struct gl_context *ctx)
static void
_mesa_meta_begin(struct gl_context *ctx, GLbitfield state)
{
- struct save_state *save = ctx-Meta-Save;
+ struct save_state *save;
+
+ /* hope MAX_META_OPS_DEPTH is large enough */
+ assert(current_save_state MAX_META_OPS_DEPTH);
+ save = ctx-Meta-Save[ctx-Meta-current_save_state++];
+ memset(save, 0, sizeof(*save));
save-SavedState = state;
if (state META_ALPHA_TEST) {
@@ -575,7 +581,7 @@ _mesa_meta_begin(struct gl_context *ctx, GLbitfield state)
static void
_mesa_meta_end(struct gl_context *ctx)
{
- struct save_state *save = ctx-Meta-Save;
+ struct save_state *save = ctx-Meta-Save[--ctx-Meta-current_save_state];
const GLbitfield state = save-SavedState;
if (state META_ALPHA_TEST) {
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Mesa (master): i965: set minimum/maximum Point Width on Sandybridge
Module: Mesa Branch: master Commit: 5ff6ed2b975d56e0e9ab363e2dc756ce93c78803 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ff6ed2b975d56e0e9ab363e2dc756ce93c78803 Author: Xiang, Haihao haihao.xi...@intel.com Date: Tue Dec 7 16:30:00 2010 +0800 i965: set minimum/maximum Point Width on Sandybridge It is used for point width on vertex. This fixes mesa demo spriteblast and pointblast. --- src/mesa/drivers/dri/i965/gen6_clip_state.c |4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c b/src/mesa/drivers/dri/i965/gen6_clip_state.c index c65b41e..c7c4eb1 100644 --- a/src/mesa/drivers/dri/i965/gen6_clip_state.c +++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c @@ -64,7 +64,9 @@ upload_clip_state(struct brw_context *brw) userclip GEN6_USER_CLIP_CLIP_DISTANCES_SHIFT | depth_clamp | provoking); - OUT_BATCH(GEN6_CLIP_FORCE_ZERO_RTAINDEX); + OUT_BATCH(U_FIXED(0.125, 3) GEN6_CLIP_MIN_POINT_WIDTH_SHIFT | + U_FIXED(225.875, 3) GEN6_CLIP_MAX_POINT_WIDTH_SHIFT | + GEN6_CLIP_FORCE_ZERO_RTAINDEX); ADVANCE_BATCH(); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: fix for flat shading on Sandybridge
Module: Mesa
Branch: master
Commit: 08be8d64509f60d2cc80112f5b94f43e06e94ff2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=08be8d64509f60d2cc80112f5b94f43e06e94ff2
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Mon Dec 6 09:33:18 2010 +0800
i965: fix for flat shading on Sandybridge
use constant interpolation instead of linear interpolation for
attributes COL0,COL1 if GL_FLAT is used. This fixes mesa demo bounce.
---
src/mesa/drivers/dri/i965/gen6_sf_state.c | 11 +--
1 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 476bf53..4cd2d69 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -69,7 +69,7 @@ upload_sf_state(struct brw_context *brw)
uint32_t num_inputs = brw_count_bits(brw-vs.prog_data-outputs_written);
/* BRW_NEW_FRAGMENT_PROGRAM */
uint32_t num_outputs =
brw_count_bits(brw-fragment_program-Base.InputsRead);
- uint32_t dw1, dw2, dw3, dw4, dw16;
+ uint32_t dw1, dw2, dw3, dw4, dw16, dw17;
int i;
/* _NEW_BUFFER */
GLboolean render_to_fbo = brw-intel.ctx.DrawBuffer-Name != 0;
@@ -92,6 +92,7 @@ upload_sf_state(struct brw_context *brw)
dw3 = 0;
dw4 = 0;
dw16 = 0;
+ dw17 = 0;
/* _NEW_POLYGON */
if ((ctx-Polygon.FrontFace == GL_CCW) ^ render_to_fbo)
@@ -203,6 +204,12 @@ upload_sf_state(struct brw_context *brw)
}
}
+ /* flat shading */
+ if (ctx-Light.ShadeModel == GL_FLAT) {
+ dw17 |= ((brw-fragment_program-Base.InputsRead (FRAG_BIT_COL0 |
FRAG_BIT_COL1))
+((brw-fragment_program-Base.InputsRead FRAG_BIT_WPOS) ? 0
: 1));
+ }
+
BEGIN_BATCH(20);
OUT_BATCH(CMD_3D_SF_STATE 16 | (20 - 2));
OUT_BATCH(dw1);
@@ -233,7 +240,7 @@ upload_sf_state(struct brw_context *brw)
OUT_BATCH(attr_overrides);
}
OUT_BATCH(dw16); /* point sprite texcoord bitmask */
- OUT_BATCH(0); /* constant interp bitmask */
+ OUT_BATCH(dw17); /* constant interp bitmask */
OUT_BATCH(0); /* wrapshortest enables 0-7 */
OUT_BATCH(0); /* wrapshortest enables 8-15 */
ADVANCE_BATCH();
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Mesa (master): i965: add support for polygon mode on Sandybridge.
Module: Mesa
Branch: master
Commit: 32e1e591467d9a28c2ac4d2e17af7be2dc429d43
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=32e1e591467d9a28c2ac4d2e17af7be2dc429d43
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Wed Dec 1 16:59:36 2010 +0800
i965: add support for polygon mode on Sandybridge.
This fixes some mesa demos such as fslight/engine in wireframe mode.
---
src/mesa/drivers/dri/i965/gen6_sf_state.c | 42 +
1 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 471067e..06ac5d4 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -99,6 +99,48 @@ upload_sf_state(struct brw_context *brw)
if (ctx-Polygon.OffsetFill)
dw2 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID;
+ if (ctx-Polygon.OffsetLine)
+ dw2 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME;
+
+ if (ctx-Polygon.OffsetPoint)
+ dw2 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT;
+
+ switch (ctx-Polygon.FrontMode) {
+ case GL_FILL:
+ dw2 |= GEN6_SF_FRONT_SOLID;
+ break;
+
+ case GL_LINE:
+ dw2 |= GEN6_SF_FRONT_WIREFRAME;
+ break;
+
+ case GL_POINT:
+ dw2 |= GEN6_SF_FRONT_POINT;
+ break;
+
+ default:
+ assert(0);
+ break;
+ }
+
+ switch (ctx-Polygon.BackMode) {
+ case GL_FILL:
+ dw2 |= GEN6_SF_BACK_SOLID;
+ break;
+
+ case GL_LINE:
+ dw2 |= GEN6_SF_BACK_WIREFRAME;
+ break;
+
+ case GL_POINT:
+ dw2 |= GEN6_SF_BACK_POINT;
+ break;
+
+ default:
+ assert(0);
+ break;
+ }
+
/* _NEW_SCISSOR */
if (ctx-Scissor.Enabled)
dw3 |= GEN6_SF_SCISSOR_ENABLE;
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Mesa (master): mesa: fix regression from b4bb6680200b5a898583392f4c831c02f41e63f7
Module: Mesa
Branch: master
Commit: 93102b4cd8e620337acf4bd42ba51f954664087e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=93102b4cd8e620337acf4bd42ba51f954664087e
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Tue Nov 23 08:52:23 2010 +0800
mesa: fix regression from b4bb6680200b5a898583392f4c831c02f41e63f7
Pending commands to the previous context aren't flushed since commit b4bb668
Reported-by: Oleksiy Krivoshey oleks...@gmail.com
Signed-off-by: Xiang, Haihao haihao.xi...@intel.com
---
src/mesa/main/context.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index b132030..4ed179a 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -1399,6 +1399,8 @@ _mesa_make_current( struct gl_context *newCtx,
struct gl_framebuffer *drawBuffer,
struct gl_framebuffer *readBuffer )
{
+ GET_CURRENT_CONTEXT(curCtx);
+
if (MESA_VERBOSE VERBOSE_API)
_mesa_debug(newCtx, _mesa_make_current()\n);
@@ -1419,6 +1421,11 @@ _mesa_make_current( struct gl_context *newCtx,
}
}
+ if (curCtx
+ (curCtx-WinSysDrawBuffer || curCtx-WinSysReadBuffer) /* make sure
this context is valid for flushing */
+ curCtx != newCtx)
+ _mesa_flush(curCtx);
+
/* We used to call _glapi_check_multithread() here. Now do it in drivers */
_glapi_set_context((void *) newCtx);
ASSERT(_mesa_get_current_context() == newCtx);
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Mesa (master): i965: validate sf state
Module: Mesa Branch: master Commit: f5539b6991e336aa1cf302dbdb1a29b3e85cff36 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5539b6991e336aa1cf302dbdb1a29b3e85cff36 Author: Xiang, Haihao haihao.xi...@intel.com Date: Thu Aug 20 18:19:36 2009 +0800 i965: validate sf state --- src/mesa/drivers/dri/i965/brw_misc_state.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 85a7706..ea71857 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -172,6 +172,7 @@ static void prepare_psp_urb_cbs(struct brw_context *brw) brw_add_validated_bo(brw, brw-vs.state_bo); brw_add_validated_bo(brw, brw-gs.state_bo); brw_add_validated_bo(brw, brw-clip.state_bo); + brw_add_validated_bo(brw, brw-sf.state_bo); brw_add_validated_bo(brw, brw-wm.state_bo); brw_add_validated_bo(brw, brw-cc.state_bo); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: fix cube map on IGDNG
Module: Mesa
Branch: master
Commit: 1f40ffca634b8d6699c9b5d153c231e79527317a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f40ffca634b8d6699c9b5d153c231e79527317a
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Thu Aug 13 18:42:52 2009 +0800
i965: fix cube map on IGDNG
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 13 -
1 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 7f9b253..1d2e953 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -65,11 +65,6 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
if (mt-compressed) {
mt-pitch = ALIGN(mt-width0, align_w);
- qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 *
align_h) / 4 * mt-pitch * mt-cpp;
- mt-total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) +
11 * align_h) / 4 * 6;
- } else {
- qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 *
align_h) * mt-pitch * mt-cpp;
- mt-total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) +
11 * align_h) * 6;
}
if (mt-first_level != mt-last_level) {
@@ -90,6 +85,14 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
mt-pitch = intel_miptree_pitch_align(intel, mt, tiling, mt-pitch);
+ if (mt-compressed) {
+ qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 *
align_h) / 4 * mt-pitch * mt-cpp;
+ mt-total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) +
11 * align_h) / 4 * 6;
+ } else {
+ qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 *
align_h) * mt-pitch * mt-cpp;
+ mt-total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) +
11 * align_h) * 6;
+ }
+
for (level = mt-first_level; level = mt-last_level; level++) {
GLuint img_height;
GLuint nr_images = 6;
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Mesa (master): i965: Postpone ff_sync message in CLIP kernel on IGDNG
Module: Mesa
Branch: master
Commit: 3e2b6a204966b962c9881e90fe3f0b74cf84d8c4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e2b6a204966b962c9881e90fe3f0b74cf84d8c4
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Thu Jul 30 14:45:11 2009 +0800
i965: Postpone ff_sync message in CLIP kernel on IGDNG
In addition, it guarantees ff_sync message is issued
---
src/mesa/drivers/dri/i965/brw_clip.h |3 ++
src/mesa/drivers/dri/i965/brw_clip_line.c |7 +++-
src/mesa/drivers/dri/i965/brw_clip_point.c|4 +-
src/mesa/drivers/dri/i965/brw_clip_tri.c |8 +++-
src/mesa/drivers/dri/i965/brw_clip_unfilled.c |3 +-
src/mesa/drivers/dri/i965/brw_clip_util.c | 48 ++--
6 files changed, 53 insertions(+), 20 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clip.h
b/src/mesa/drivers/dri/i965/brw_clip.h
index 12e8548..957df44 100644
--- a/src/mesa/drivers/dri/i965/brw_clip.h
+++ b/src/mesa/drivers/dri/i965/brw_clip.h
@@ -100,6 +100,8 @@ struct brw_clip_compile {
struct brw_reg fixed_planes;
struct brw_reg plane_equation;
+
+ struct brw_reg ff_sync;
} reg;
/* 3 different ways of expressing vertex size:
@@ -173,4 +175,5 @@ struct brw_reg get_tmp( struct brw_clip_compile *c );
void brw_clip_project_position(struct brw_clip_compile *c,
struct brw_reg pos );
void brw_clip_ff_sync(struct brw_clip_compile *c);
+void brw_clip_init_ff_sync(struct brw_clip_compile *c);
#endif
diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c
b/src/mesa/drivers/dri/i965/brw_clip_line.c
index 9abd064..048ca62 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_line.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_line.c
@@ -85,6 +85,10 @@ static void brw_clip_line_alloc_regs( struct
brw_clip_compile *c )
i++;
}
+ if (c-need_ff_sync) {
+ c-reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD);
+ i++;
+ }
c-first_tmp = i;
c-last_tmp = i;
@@ -246,8 +250,6 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
brw_ADD(p, c-reg.t, c-reg.t0, c-reg.t1);
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c-reg.t,
brw_imm_f(1.0));
- if (c-need_ff_sync)
- brw_clip_ff_sync(c);
not_culled = brw_IF(p, BRW_EXECUTE_1);
{
brw_clip_interp_vertex(c, newvtx0, vtx0, vtx1, c-reg.t0, GL_FALSE);
@@ -265,6 +267,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
void brw_emit_line_clip( struct brw_clip_compile *c )
{
brw_clip_line_alloc_regs(c);
+ brw_clip_init_ff_sync(c);
if (c-key.do_flat_shading)
brw_clip_copy_colors(c, 0, 1);
diff --git a/src/mesa/drivers/dri/i965/brw_clip_point.c
b/src/mesa/drivers/dri/i965/brw_clip_point.c
index 9738299..8458f61 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_point.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_point.c
@@ -50,7 +50,7 @@ void brw_emit_point_clip( struct brw_clip_compile *c )
/* Send an empty message to kill the thread:
*/
brw_clip_tri_alloc_regs(c, 0);
- if (c-need_ff_sync)
- brw_clip_ff_sync(c);
+ brw_clip_init_ff_sync(c);
+
brw_clip_kill_thread(c);
}
diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c
b/src/mesa/drivers/dri/i965/brw_clip_tri.c
index 4c2d655..0efd772 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_tri.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c
@@ -119,6 +119,11 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
i++;
}
+ if (c-need_ff_sync) {
+ c-reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD);
+ i++;
+ }
+
c-first_tmp = i;
c-last_tmp = i;
@@ -563,6 +568,7 @@ void brw_emit_tri_clip( struct brw_clip_compile *c )
brw_clip_tri_alloc_regs(c, 3 + c-key.nr_userclip + 6);
brw_clip_tri_init_vertices(c);
brw_clip_init_clipmask(c);
+ brw_clip_init_ff_sync(c);
/* if -ve rhw workaround bit is set,
do cliptest */
@@ -589,8 +595,6 @@ void brw_emit_tri_clip( struct brw_clip_compile *c )
else
maybe_do_clip_tri(c);
- if (c-need_ff_sync)
- brw_clip_ff_sync(c);
brw_clip_tri_emit_polygon(c);
/* Send an empty message to kill the thread:
diff --git a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
index 2695038..ad1bfa4 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
@@ -453,6 +453,7 @@ void brw_emit_unfilled_clip( struct brw_clip_compile *c )
brw_clip_tri_alloc_regs(c, 3 + c-key.nr_userclip + 6);
brw_clip_tri_init_vertices(c);
+ brw_clip_init_ff_sync(c);
assert(c-offset[VERT_RESULT_EDGE]);
@@ -496,8 +497,6 @@ void brw_emit_unfilled_clip( struct brw_clip_compile *c )
}
brw_ENDIF(p, do_clip);
- if (c-need_ff_sync)
- brw_clip_ff_sync(c);
emit_unfilled_primitives(c);
brw_clip_kill_thread(c);
}
diff --git
Mesa (master): i965: the offset of any branch/ jump instruction is in unit of 64bits on IGDNG
Module: Mesa
Branch: master
Commit: 868aa160745ed0b3f1a83353ef2f3a8fcb5d235e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=868aa160745ed0b3f1a83353ef2f3a8fcb5d235e
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Wed Jul 15 10:40:16 2009 +0800
i965: the offset of any branch/jump instruction is in unit of 64bits on IGDNG
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 21 +
src/mesa/drivers/dri/i965/brw_wm_glsl.c |9 +++--
2 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index ec634e6..2412014 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -648,6 +648,10 @@ struct brw_instruction *brw_ELSE(struct brw_compile *p,
struct brw_instruction *if_insn)
{
struct brw_instruction *insn;
+ GLuint br = 1;
+
+ if (BRW_IS_IGDNG(p-brw))
+ br = 2;
if (p-single_program_flow) {
insn = next_insn(p, BRW_OPCODE_ADD);
@@ -674,7 +678,7 @@ struct brw_instruction *brw_ELSE(struct brw_compile *p,
} else {
assert(if_insn-header.opcode == BRW_OPCODE_IF);
- if_insn-bits3.if_else.jump_count = insn - if_insn;
+ if_insn-bits3.if_else.jump_count = br * (insn - if_insn);
if_insn-bits3.if_else.pop_count = 1;
if_insn-bits3.if_else.pad0 = 0;
}
@@ -685,6 +689,11 @@ struct brw_instruction *brw_ELSE(struct brw_compile *p,
void brw_ENDIF(struct brw_compile *p,
struct brw_instruction *patch_insn)
{
+ GLuint br = 1;
+
+ if (BRW_IS_IGDNG(p-brw))
+ br = 2;
+
if (p-single_program_flow) {
/* In single program flow mode, there's no need to execute an ENDIF,
* since we don't need to do any stack operations, and if we're executing
@@ -716,11 +725,11 @@ void brw_ENDIF(struct brw_compile *p,
/* Automagically turn it into an IFF:
*/
patch_insn-header.opcode = BRW_OPCODE_IFF;
-patch_insn-bits3.if_else.jump_count = insn - patch_insn + 1;
+patch_insn-bits3.if_else.jump_count = br * (insn - patch_insn + 1);
patch_insn-bits3.if_else.pop_count = 0;
patch_insn-bits3.if_else.pad0 = 0;
} else if (patch_insn-header.opcode == BRW_OPCODE_ELSE) {
-patch_insn-bits3.if_else.jump_count = insn - patch_insn + 1;
+patch_insn-bits3.if_else.jump_count = br * (insn - patch_insn + 1);
patch_insn-bits3.if_else.pop_count = 1;
patch_insn-bits3.if_else.pad0 = 0;
} else {
@@ -794,6 +803,10 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p,
struct brw_instruction *do_insn)
{
struct brw_instruction *insn;
+ GLuint br = 1;
+
+ if (BRW_IS_IGDNG(p-brw))
+ br = 2;
if (p-single_program_flow)
insn = next_insn(p, BRW_OPCODE_ADD);
@@ -814,7 +827,7 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p,
insn-header.execution_size = do_insn-header.execution_size;
assert(do_insn-header.opcode == BRW_OPCODE_DO);
- insn-bits3.if_else.jump_count = do_insn - insn + 1;
+ insn-bits3.if_else.jump_count = br * (do_insn - insn + 1);
insn-bits3.if_else.pop_count = 0;
insn-bits3.if_else.pad0 = 0;
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index 38f2052..19f777f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -3000,17 +3000,22 @@ static void brw_wm_emit_glsl(struct brw_context *brw,
struct brw_wm_compile *c)
case OPCODE_ENDLOOP:
{
struct brw_instruction *inst0, *inst1;
+ GLuint br = 1;
+
+ if (BRW_IS_IGDNG(brw))
+ br = 2;
+
loop_depth--;
inst0 = inst1 = brw_WHILE(p, loop_inst[loop_depth]);
/* patch all the BREAK/CONT instructions from last BEGINLOOP
*/
while (inst0 loop_inst[loop_depth]) {
inst0--;
if (inst0-header.opcode == BRW_OPCODE_BREAK) {
- inst0-bits3.if_else.jump_count = inst1 - inst0 + 1;
+ inst0-bits3.if_else.jump_count = br * (inst1 - inst0 +
1);
inst0-bits3.if_else.pop_count = 0;
}
else if (inst0-header.opcode == BRW_OPCODE_CONTINUE) {
-inst0-bits3.if_else.jump_count = inst1 - inst0;
+inst0-bits3.if_else.jump_count = br * (inst1 - inst0);
inst0-bits3.if_else.pop_count = 0;
}
}
___
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Mesa (master): i965: fixes for JMPI
Module: Mesa
Branch: master
Commit: 73137997e23ff6c1145d036315d1a9ad96651281
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=73137997e23ff6c1145d036315d1a9ad96651281
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Thu Jul 2 16:32:19 2009 +0800
i965: fixes for JMPI
1. the data type of src1 (JMPI offset) must be D
2. execution size must be 1
3. NoMask
4. instruction compression isn't allowed.
---
src/mesa/drivers/dri/i965/brw_eu_emit.c |4
src/mesa/drivers/dri/i965/brw_sf_emit.c | 18 +-
src/mesa/drivers/dri/i965/brw_wm_emit.c |2 +-
3 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index da41d5a..0ee208d 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -484,6 +484,10 @@ struct brw_instruction *brw_JMPI(struct brw_compile *p,
{
struct brw_instruction *insn = brw_alu2(p, BRW_OPCODE_JMPI, dest, src0,
src1);
+ insn-header.execution_size = 1;
+ insn-header.compression_control = BRW_COMPRESSION_NONE;
+ insn-header.mask_control = BRW_MASK_DISABLE;
+
p-current-header.predicate_control = BRW_PREDICATE_NONE;
return insn;
diff --git a/src/mesa/drivers/dri/i965/brw_sf_emit.c
b/src/mesa/drivers/dri/i965/brw_sf_emit.c
index 2f63610..42726d4 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_emit.c
@@ -161,16 +161,16 @@ static void do_flatshade_triangle( struct brw_sf_compile
*c )
brw_push_insn_state(p);
- brw_MUL(p, c-pv, c-pv, brw_imm_ud(nr*2+1));
+ brw_MUL(p, c-pv, c-pv, brw_imm_d(nr*2+1));
brw_JMPI(p, ip, ip, c-pv);
copy_colors(c, c-vert[1], c-vert[0]);
copy_colors(c, c-vert[2], c-vert[0]);
- brw_JMPI(p, ip, ip, brw_imm_ud(nr*4+1));
+ brw_JMPI(p, ip, ip, brw_imm_d(nr*4+1));
copy_colors(c, c-vert[0], c-vert[1]);
copy_colors(c, c-vert[2], c-vert[1]);
- brw_JMPI(p, ip, ip, brw_imm_ud(nr*2));
+ brw_JMPI(p, ip, ip, brw_imm_d(nr*2));
copy_colors(c, c-vert[0], c-vert[2]);
copy_colors(c, c-vert[1], c-vert[2]);
@@ -195,11 +195,11 @@ static void do_flatshade_line( struct brw_sf_compile *c )
brw_push_insn_state(p);
- brw_MUL(p, c-pv, c-pv, brw_imm_ud(nr+1));
+ brw_MUL(p, c-pv, c-pv, brw_imm_d(nr+1));
brw_JMPI(p, ip, ip, c-pv);
copy_colors(c, c-vert[1], c-vert[0]);
- brw_JMPI(p, ip, ip, brw_imm_ud(nr));
+ brw_JMPI(p, ip, ip, brw_imm_d(nr));
copy_colors(c, c-vert[0], c-vert[1]);
brw_pop_insn_state(p);
@@ -218,7 +218,7 @@ static void alloc_regs( struct brw_sf_compile *c )
/* Values computed by fixed function unit:
*/
- c-pv = retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_UD);
+ c-pv = retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_D);
c-det = brw_vec1_grf(1, 2);
c-dx0 = brw_vec1_grf(1, 3);
c-dx2 = brw_vec1_grf(1, 4);
@@ -678,7 +678,7 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
(1_3DPRIM_POLYGON) |
(1_3DPRIM_RECTLIST) |
(1_3DPRIM_TRIFAN_NOSTIPPLE)));
- jmp = brw_JMPI(p, ip, ip, brw_imm_w(0));
+ jmp = brw_JMPI(p, ip, ip, brw_imm_d(0));
{
saveflag = p-flag_value;
brw_push_insn_state(p);
@@ -699,7 +699,7 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
(1_3DPRIM_LINESTRIP_CONT) |
(1_3DPRIM_LINESTRIP_BF) |
(1_3DPRIM_LINESTRIP_CONT_BF)));
- jmp = brw_JMPI(p, ip, ip, brw_imm_w(0));
+ jmp = brw_JMPI(p, ip, ip, brw_imm_d(0));
{
saveflag = p-flag_value;
brw_push_insn_state(p);
@@ -712,7 +712,7 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
brw_set_conditionalmod(p, BRW_CONDITIONAL_Z);
brw_AND(p, v1_null_ud, payload_attr,
brw_imm_ud(1BRW_SPRITE_POINT_ENABLE));
- jmp = brw_JMPI(p, ip, ip, brw_imm_w(0));
+ jmp = brw_JMPI(p, ip, ip, brw_imm_d(0));
{
saveflag = p-flag_value;
brw_push_insn_state(p);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c
b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index 4c3879f..4a8b9f9 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -1022,7 +1022,7 @@ static void emit_fb_write( struct brw_wm_compile *c,
get_element_ud(brw_vec8_grf(1,0), 6),
brw_imm_ud(126));
- jmp = brw_JMPI(p, ip, ip, brw_imm_w(0));
+ jmp = brw_JMPI(p, ip, ip, brw_imm_d(0));
{
emit_aa(c, arg1, 2);
fire_fb_write(c, 0, nr, target, eot);
___
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Mesa (master): i965: fix for RHW workaround
Module: Mesa
Branch: master
Commit: 68915fd6fac44dd80298e3afb0669e8754aa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=68915fd6fac44dd80298e3afb0669e8754aa
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Thu Feb 26 17:31:01 2009 +0800
i965: fix for RHW workaround
It is possible that an object whose vertices all are outside of a
view plane is passed to clip thread due to the RHW workaround. This
object should be rejected by clip thread. Fix bug #19879
---
src/mesa/drivers/dri/i965/brw_clip_line.c | 66 -
src/mesa/drivers/dri/i965/brw_clip_tri.c | 76 +
2 files changed, 99 insertions(+), 43 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c
b/src/mesa/drivers/dri/i965/brw_clip_line.c
index c45d48d..d830e49 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_line.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_line.c
@@ -181,34 +181,54 @@ static void clip_and_emit_line( struct brw_clip_compile
*c )
brw_DP4(p, vec4(c-reg.dp1), deref_4f(vtx1,
c-offset[VERT_RESULT_HPOS]), c-reg.plane_equation);
is_negative = brw_IF(p, BRW_EXECUTE_1);
{
- brw_ADD(p, c-reg.t, c-reg.dp1, negate(c-reg.dp0));
- brw_math_invert(p, c-reg.t, c-reg.t);
- brw_MUL(p, c-reg.t, c-reg.t, c-reg.dp1);
-
- brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c-reg.t,
c-reg.t1 );
- brw_MOV(p, c-reg.t1, c-reg.t);
- brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+ /*
+ * Both can be negative on GM965/G965 due to RHW workaround
+ * if so, this object should be rejected.
+ */
+ if (!BRW_IS_G4X(p-brw)) {
+ brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE,
c-reg.dp0, brw_imm_f(0.0));
+ is_neg2 = brw_IF(p, BRW_EXECUTE_1);
+ {
+ brw_clip_kill_thread(c);
+ }
+ brw_ENDIF(p, is_neg2);
+ }
+
+ brw_ADD(p, c-reg.t, c-reg.dp1, negate(c-reg.dp0));
+ brw_math_invert(p, c-reg.t, c-reg.t);
+ brw_MUL(p, c-reg.t, c-reg.t, c-reg.dp1);
+
+ brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c-reg.t,
c-reg.t1 );
+ brw_MOV(p, c-reg.t1, c-reg.t);
+ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
}
is_negative = brw_ELSE(p, is_negative);
{
- /* Coming back in. We know that both cannot be negative
-* because the line would have been culled in that case.
-*/
+ /* Coming back in. We know that both cannot be negative
+ * because the line would have been culled in that case.
+ */
+
+ /* If both are positive, do nothing */
+ /* Only on GM965/G965 */
+ if (!BRW_IS_G4X(p-brw)) {
+ brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L,
c-reg.dp0, brw_imm_f(0.0));
+ is_neg2 = brw_IF(p, BRW_EXECUTE_1);
+ }
- /* If both are positive, do nothing */
- brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c-reg.dp0,
brw_imm_f(0.0));
- is_neg2 = brw_IF(p, BRW_EXECUTE_1);
{
- brw_ADD(p, c-reg.t, c-reg.dp0, negate(c-reg.dp1));
- brw_math_invert(p, c-reg.t, c-reg.t);
- brw_MUL(p, c-reg.t, c-reg.t, c-reg.dp0);
-
- brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c-reg.t,
c-reg.t0 );
- brw_MOV(p, c-reg.t0, c-reg.t);
- brw_set_predicate_control(p, BRW_PREDICATE_NONE);
-}
-brw_ENDIF(p, is_neg2);
-}
+ brw_ADD(p, c-reg.t, c-reg.dp0, negate(c-reg.dp1));
+ brw_math_invert(p, c-reg.t, c-reg.t);
+ brw_MUL(p, c-reg.t, c-reg.t, c-reg.dp0);
+
+ brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c-reg.t,
c-reg.t0 );
+ brw_MOV(p, c-reg.t0, c-reg.t);
+ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+ }
+
+ if (!BRW_IS_G4X(p-brw)) {
+ brw_ENDIF(p, is_neg2);
+ }
+ }
brw_ENDIF(p, is_negative);
}
brw_ENDIF(p, plane_active);
diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c
b/src/mesa/drivers/dri/i965/brw_clip_tri.c
index 1dbba37..7fd37bd 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_tri.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c
@@ -455,6 +455,8 @@ static void brw_clip_test( struct brw_clip_compile *c )
struct brw_indirect vt2 = brw_indirect(2, 0);
struct brw_compile *p = c-func;
+struct brw_instruction *is_outside;
+struct brw_reg tmp0 = c-reg.loopcount; /* handy temporary */
brw_MOV(p, get_addr_reg(vt0), brw_address(c-reg.vertex[0]));
brw_MOV(p, get_addr_reg(vt1), brw_address(c-reg.vertex[1]));
@@
Mesa (master): intel: bump driver date
Module: Mesa Branch: master Commit: c157a5bb9131dc95f2e5519fda19cf8c3567543a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c157a5bb9131dc95f2e5519fda19cf8c3567543a Author: Xiang, Haihao haihao.xi...@intel.com Date: Wed Jan 14 09:32:55 2009 +0800 intel: bump driver date --- src/mesa/drivers/dri/intel/intel_context.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 44b276a..7b7f7d8 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -95,7 +95,7 @@ int INTEL_DEBUG = (0); #include extension_helper.h -#define DRIVER_DATE 20080716 +#define DRIVER_DATE 20090114 #define DRIVER_DATE_GEM GEM DRIVER_DATE static const GLubyte * ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (intel-2008-q4): intel: bump driver date
Module: Mesa Branch: intel-2008-q4 Commit: 200fa9165d7078a6f36c5c9d3e0c997c2438bde3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=200fa9165d7078a6f36c5c9d3e0c997c2438bde3 Author: Xiang, Haihao haihao.xi...@intel.com Date: Wed Jan 14 09:35:45 2009 +0800 intel: bump driver date --- src/mesa/drivers/dri/intel/intel_context.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index c779e2d..f4c70b4 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -95,7 +95,7 @@ int INTEL_DEBUG = (0); #include extension_helper.h -#define DRIVER_DATE 20080716 +#define DRIVER_DATE 20090114 2008Q4 release #define DRIVER_DATE_GEM GEM DRIVER_DATE static const GLubyte * ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (intel-2008-q4): i965: implement OPCODE_TRUNC (round toward zero) on vertex path.
Module: Mesa Branch: intel-2008-q4 Commit: 2300dfd449b06744331c709f2d5856ec36102f26 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2300dfd449b06744331c709f2d5856ec36102f26 Author: Brian Paul bri...@vmware.com Date: Mon Jan 5 10:09:28 2009 -0700 i965: implement OPCODE_TRUNC (round toward zero) on vertex path. Also, fix some RNDD vs. RNDZ confusion elsewhere. (cherry picked from commit 0d797365deb579cfeb2a32f21692515eb6904921) --- src/mesa/drivers/dri/i965/brw_eu.h |1 + src/mesa/drivers/dri/i965/brw_eu_emit.c |1 + src/mesa/drivers/dri/i965/brw_vs_emit.c |4 src/mesa/drivers/dri/i965/brw_wm_glsl.c |2 +- 4 files changed, 7 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index 49b422e..d12f15e 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -733,6 +733,7 @@ ALU2(ADD) ALU2(MUL) ALU1(FRC) ALU1(RNDD) +ALU1(RNDZ) ALU2(MAC) ALU2(MACH) ALU1(LZD) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index ce4cf46..4e099b5 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -439,6 +439,7 @@ ALU2(ADD) ALU2(MUL) ALU1(FRC) ALU1(RNDD) +ALU1(RNDZ) ALU2(MAC) ALU2(MACH) ALU1(LZD) diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index b594e47..aa3e46b 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -1146,6 +1146,10 @@ void brw_vs_emit(struct brw_vs_compile *c ) */ emit_swz(c, dst, inst-SrcReg[0] ); break; + case OPCODE_TRUNC: + /* round toward zero */ +brw_RNDZ(p, dst, args[0]); +break; case OPCODE_XPD: emit_xpd(p, dst, args[0], args[1]); break; diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index baecfdc..d43e326 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -267,7 +267,7 @@ static void emit_trunc( struct brw_wm_compile *c, struct brw_reg src, dst; dst = get_dst_reg(c, inst, i, 1) ; src = get_src_reg(c, inst-SrcReg[0], i, 1); - brw_RNDD(p, dst, src); + brw_RNDZ(p, dst, src); } } brw_set_saturate(p, 0); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (intel-2008-q4): mesa: Fix the number of components for GL_UNSIGNED_SHORT_1_5_5_5_REV. ( bug #19390)
Module: Mesa Branch: intel-2008-q4 Commit: a4cbfba6a27cd788b78143456f219b576a33a3c9 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4cbfba6a27cd788b78143456f219b576a33a3c9 Author: Xiang, Haihao haihao.xi...@intel.com Date: Tue Jan 6 15:30:34 2009 +0800 mesa: Fix the number of components for GL_UNSIGNED_SHORT_1_5_5_5_REV. (bug #19390) (cherry picked from commit 241c0bfc985363bb15e6cc0eca859c6ec36d1b35) --- src/mesa/main/texformat.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/main/texformat.c b/src/mesa/main/texformat.c index 4442ce3..1dd7bdd 100644 --- a/src/mesa/main/texformat.c +++ b/src/mesa/main/texformat.c @@ -1641,7 +1641,7 @@ _mesa_format_to_type_and_comps(const struct gl_texture_format *format, case MESA_FORMAT_ARGB1555: case MESA_FORMAT_ARGB1555_REV: *datatype = GL_UNSIGNED_SHORT_1_5_5_5_REV; - *comps = 3; + *comps = 4; return; case MESA_FORMAT_AL88: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (intel-2008-q4): mesa: Fix the size per pixel for packed pixel format data type.
Module: Mesa
Branch: intel-2008-q4
Commit: 0640a81b6cd281ea2fa3196dd59c057910779f20
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0640a81b6cd281ea2fa3196dd59c057910779f20
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Tue Jan 6 15:37:45 2009 +0800
mesa: Fix the size per pixel for packed pixel format data type.
(cherry picked from commit f1f022dbb103947b0edf5ae984fcff00f6a8e539)
---
src/mesa/main/image.c |2 +-
src/mesa/main/image.h |3 +++
src/mesa/main/mipmap.c |6 +-
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/image.c b/src/mesa/main/image.c
index c205b4b..4d86c54 100644
--- a/src/mesa/main/image.c
+++ b/src/mesa/main/image.c
@@ -61,7 +61,7 @@
/**
* \return GL_TRUE if type is packed pixel type, GL_FALSE otherwise.
*/
-static GLboolean
+GLboolean
_mesa_type_is_packed(GLenum type)
{
switch (type) {
diff --git a/src/mesa/main/image.h b/src/mesa/main/image.h
index 38e1374..0e0bbd9 100644
--- a/src/mesa/main/image.h
+++ b/src/mesa/main/image.h
@@ -36,6 +36,9 @@ _mesa_swap2( GLushort *p, GLuint n );
extern void
_mesa_swap4( GLuint *p, GLuint n );
+extern GLboolean
+_mesa_type_is_packed(GLenum type);
+
extern GLint
_mesa_sizeof_type( GLenum type );
diff --git a/src/mesa/main/mipmap.c b/src/mesa/main/mipmap.c
index 78d14b2..8569ee5 100644
--- a/src/mesa/main/mipmap.c
+++ b/src/mesa/main/mipmap.c
@@ -41,7 +41,11 @@ bytes_per_pixel(GLenum datatype, GLuint comps)
{
GLint b = _mesa_sizeof_packed_type(datatype);
assert(b = 0);
- return b * comps;
+
+ if (_mesa_type_is_packed(datatype))
+ return b;
+ else
+ return b * comps;
}
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Mesa (intel-2008-q4): mesa: fix GL_DEPTH_CLEAR_VALUE casting
Module: Mesa Branch: intel-2008-q4 Commit: a1e114a3e3ee8e5c9746a65d81f34c3c5f7731f4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1e114a3e3ee8e5c9746a65d81f34c3c5f7731f4 Author: Brian Paul bri...@vmware.com Date: Tue Jan 6 14:21:27 2009 -0700 mesa: fix GL_DEPTH_CLEAR_VALUE casting (cherry picked from commit d14d494dcda3d80ec2cf452551c680ffb432e306) (cherry picked from commit 814bc5ccda51009327b6b5ff0fc2c088d537a636) --- src/mesa/main/get.c |6 +++--- src/mesa/main/get_gen.py |2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c index f72aa6a..8ce9b0a 100644 --- a/src/mesa/main/get.c +++ b/src/mesa/main/get.c @@ -289,7 +289,7 @@ _mesa_GetBooleanv( GLenum pname, GLboolean *params ) params[0] = INT_TO_BOOLEAN(ctx-DrawBuffer-Visual.depthBits); break; case GL_DEPTH_CLEAR_VALUE: - params[0] = FLOAT_TO_BOOLEAN(ctx-Depth.Clear); + params[0] = FLOAT_TO_BOOLEAN(((GLfloat) ctx-Depth.Clear)); break; case GL_DEPTH_FUNC: params[0] = ENUM_TO_BOOLEAN(ctx-Depth.Func); @@ -2137,7 +2137,7 @@ _mesa_GetFloatv( GLenum pname, GLfloat *params ) params[0] = (GLfloat)(ctx-DrawBuffer-Visual.depthBits); break; case GL_DEPTH_CLEAR_VALUE: - params[0] = ctx-Depth.Clear; + params[0] = ((GLfloat) ctx-Depth.Clear); break; case GL_DEPTH_FUNC: params[0] = ENUM_TO_FLOAT(ctx-Depth.Func); @@ -3985,7 +3985,7 @@ _mesa_GetIntegerv( GLenum pname, GLint *params ) params[0] = ctx-DrawBuffer-Visual.depthBits; break; case GL_DEPTH_CLEAR_VALUE: - params[0] = FLOAT_TO_INT(ctx-Depth.Clear); + params[0] = FLOAT_TO_INT(((GLfloat) ctx-Depth.Clear)); break; case GL_DEPTH_FUNC: params[0] = ENUM_TO_INT(ctx-Depth.Func); diff --git a/src/mesa/main/get_gen.py b/src/mesa/main/get_gen.py index 152e378..a191b04 100644 --- a/src/mesa/main/get_gen.py +++ b/src/mesa/main/get_gen.py @@ -180,7 +180,7 @@ StateVars = [ ( GL_DEPTH_BIAS, GLfloat, [ctx-Pixel.DepthBias], , None ), ( GL_DEPTH_BITS, GLint, [ctx-DrawBuffer-Visual.depthBits], , None ), - ( GL_DEPTH_CLEAR_VALUE, GLfloatN, [ctx-Depth.Clear], , None ), + ( GL_DEPTH_CLEAR_VALUE, GLfloatN, [((GLfloat) ctx-Depth.Clear)], , None ), ( GL_DEPTH_FUNC, GLenum, [ctx-Depth.Func], , None ), ( GL_DEPTH_RANGE, GLfloatN, [ ctx-Viewport.Near, ctx-Viewport.Far ], , None ), ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (intel-2008-q4): i965: Add support for LRP in VPs.
Module: Mesa
Branch: intel-2008-q4
Commit: e3644db997ae2ba72c6cc4af5e4e105ea14af5ef
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e3644db997ae2ba72c6cc4af5e4e105ea14af5ef
Author: Eric Anholt e...@anholt.net
Date: Wed Jan 7 12:37:58 2009 -0800
i965: Add support for LRP in VPs.
Bug #19226.
(cherry picked from commit f53d9913ac8efa5cefa428eb21f91298aca78293)
---
src/mesa/drivers/dri/i965/brw_vs_emit.c | 42 +++
1 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c
b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index aa3e46b..e128380 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -196,6 +196,7 @@ static void unalias1( struct brw_vs_compile *c,
struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask);
func(c, tmp, arg0);
brw_MOV(p, dst, tmp);
+ release_tmp(c, tmp);
}
else {
func(c, dst, arg0);
@@ -217,12 +218,38 @@ static void unalias2( struct brw_vs_compile *c,
struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask);
func(c, tmp, arg0, arg1);
brw_MOV(p, dst, tmp);
+ release_tmp(c, tmp);
}
else {
func(c, dst, arg0, arg1);
}
}
+static void unalias3( struct brw_vs_compile *c,
+ struct brw_reg dst,
+ struct brw_reg arg0,
+ struct brw_reg arg1,
+ struct brw_reg arg2,
+ void (*func)( struct brw_vs_compile *,
+ struct brw_reg,
+ struct brw_reg,
+ struct brw_reg,
+ struct brw_reg ))
+{
+ if ((dst.file == arg0.file dst.nr == arg0.nr) ||
+ (dst.file == arg1.file dst.nr == arg1.nr) ||
+ (dst.file == arg2.file dst.nr == arg2.nr)) {
+ struct brw_compile *p = c-func;
+ struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask);
+ func(c, tmp, arg0, arg1, arg2);
+ brw_MOV(p, dst, tmp);
+ release_tmp(c, tmp);
+ }
+ else {
+ func(c, dst, arg0, arg1, arg2);
+ }
+}
+
static void emit_sop( struct brw_compile *p,
struct brw_reg dst,
struct brw_reg arg0,
@@ -595,6 +622,18 @@ static void emit_lit_noalias( struct brw_vs_compile *c,
brw_ENDIF(p, if_insn);
}
+static void emit_lrp_noalias(struct brw_vs_compile *c,
+struct brw_reg dst,
+struct brw_reg arg0,
+struct brw_reg arg1,
+struct brw_reg arg2)
+{
+ struct brw_compile *p = c-func;
+
+ brw_ADD(p, dst, negate(arg0), brw_imm_f(1.0));
+ brw_MUL(p, brw_null_reg(), dst, arg2);
+ brw_MAC(p, dst, arg0, arg1);
+}
/** 3 or 4-component vector normalization */
static void emit_nrm( struct brw_vs_compile *c,
@@ -1090,6 +1129,9 @@ void brw_vs_emit(struct brw_vs_compile *c )
case OPCODE_LIT:
unalias1(c, dst, args[0], emit_lit_noalias);
break;
+ case OPCODE_LRP:
+unalias3(c, dst, args[0], args[1], args[2], emit_lrp_noalias);
+break;
case OPCODE_MAD:
brw_MOV(p, brw_acc_reg(), args[2]);
brw_MAC(p, dst, args[0], args[1]);
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Mesa (intel-2008-q4): i965: init dst reg RelAddr field to zero
Module: Mesa Branch: intel-2008-q4 Commit: 796dd4b717136ebe20a144ab15e20a0b75972543 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=796dd4b717136ebe20a144ab15e20a0b75972543 Author: Brian Paul bri...@vmware.com Date: Wed Jan 7 15:06:06 2009 -0700 i965: init dst reg RelAddr field to zero (cherry picked from commit 95fa98d61a857448e690a0671b2e1e1d2873f0ec) --- src/mesa/drivers/dri/i965/brw_wm_fp.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c index 7f7b957..cb1e400 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_fp.c +++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c @@ -122,10 +122,11 @@ static struct prog_dst_register dst_reg(GLuint file, GLuint idx) reg.File = file; reg.Index = idx; reg.WriteMask = WRITEMASK_XYZW; + reg.RelAddr = 0; reg.CondMask = 0; reg.CondSwizzle = 0; - reg.pad = 0; reg.CondSrc = 0; + reg.pad = 0; return reg; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (intel-2008-q4): i965: Note when we drop saturate mode on the floor in a VP.
Module: Mesa
Branch: intel-2008-q4
Commit: 9ae22a4a2ae4d7f10463d7b85233dc569b7cfb40
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ae22a4a2ae4d7f10463d7b85233dc569b7cfb40
Author: Eric Anholt e...@anholt.net
Date: Wed Jan 7 12:38:34 2009 -0800
i965: Note when we drop saturate mode on the floor in a VP.
(cherry picked from commit 8112c9e2cc5b27a2b7fd1641c03d3660f992dabf)
---
src/mesa/drivers/dri/i965/brw_vs_emit.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c
b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index e128380..8bede41 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -1077,6 +1077,11 @@ void brw_vs_emit(struct brw_vs_compile *c )
else
dst = get_dst(c, inst-DstReg);
+ if (inst-SaturateMode != SATURATE_OFF) {
+_mesa_problem(NULL, Unsupported saturate %d in vertex shader,
+ inst-SaturateMode);
+ }
+
switch (inst-Opcode) {
case OPCODE_ABS:
brw_MOV(p, dst, brw_abs(args[0]));
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Mesa (intel-2008-q4): glsl: check that the fragment shader does not write both gl_FragColor and gl_FragData []
Module: Mesa
Branch: intel-2008-q4
Commit: 9d90e89b42dfe5198b891ec39d22641407d960a7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d90e89b42dfe5198b891ec39d22641407d960a7
Author: Brian Paul bri...@vmware.com
Date: Wed Jan 7 18:22:56 2009 -0700
glsl: check that the fragment shader does not write both gl_FragColor and
gl_FragData[]
(cherry picked from commit d1860bcd0ade44a884ac1b7e0c5b2bef8ed6afcb)
---
src/mesa/shader/slang/slang_link.c | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/src/mesa/shader/slang/slang_link.c
b/src/mesa/shader/slang/slang_link.c
index 08d7540..eea1a66 100644
--- a/src/mesa/shader/slang/slang_link.c
+++ b/src/mesa/shader/slang/slang_link.c
@@ -604,6 +604,17 @@ _slang_link(GLcontext *ctx,
}
}
+ /* check that gl_FragColor and gl_FragData are not both written to */
+ if (shProg-FragmentProgram) {
+ GLbitfield outputsWritten = shProg-FragmentProgram-Base.OutputsWritten;
+ if ((outputsWritten ((1 FRAG_RESULT_COLR)))
+ (outputsWritten = (1 FRAG_RESULT_DATA0))) {
+ link_error(shProg, Fragment program cannot write both gl_FragColor
+ and gl_FragData[].\n);
+ return;
+ }
+ }
+
if (fragProg shProg-FragmentProgram) {
/* Compute initial program's TexturesUsed info */
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Mesa (intel-2008-q4): i965: allow gl_FragData[0] usage when there' s only one color buffer
Module: Mesa
Branch: intel-2008-q4
Commit: 32e43b60027eb7a3be31abde661a221de97963b1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=32e43b60027eb7a3be31abde661a221de97963b1
Author: Brian Paul bri...@vmware.com
Date: Wed Jan 7 18:45:49 2009 -0700
i965: allow gl_FragData[0] usage when there's only one color buffer
If gl_FragData[0] is written but not gl_FragCOlor, use the former.
(cherry picked from commit f68f94c2bc950405d4c91a1e5582a35ff4b15bdf)
---
src/mesa/drivers/dri/i965/brw_wm_fp.c | 11 +--
1 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c
b/src/mesa/drivers/dri/i965/brw_wm_fp.c
index cb1e400..f458387 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_fp.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c
@@ -864,9 +864,9 @@ static void emit_fog( struct brw_wm_compile *c )
static void emit_fb_write( struct brw_wm_compile *c )
{
- struct prog_src_register outcolor = src_reg(PROGRAM_OUTPUT,
FRAG_RESULT_COLR);
struct prog_src_register payload_r0_depth = src_reg(PROGRAM_PAYLOAD,
PAYLOAD_DEPTH);
struct prog_src_register outdepth = src_reg(PROGRAM_OUTPUT,
FRAG_RESULT_DEPR);
+ struct prog_src_register outcolor;
GLuint i;
struct prog_instruction *inst, *last_inst;
@@ -890,7 +890,14 @@ static void emit_fb_write( struct brw_wm_compile *c )
}
}
last_inst-Sampler |= 1; //eot
- }else {
+ }
+ else {
+ /* if gl_FragData[0] is written, use it, else use gl_FragColor */
+ if (c-fp-program.Base.OutputsWritten (1 FRAG_RESULT_DATA0))
+ outcolor = src_reg(PROGRAM_OUTPUT, FRAG_RESULT_DATA0);
+ else
+ outcolor = src_reg(PROGRAM_OUTPUT, FRAG_RESULT_COLR);
+
inst = emit_op(c, WM_FB_WRITE, dst_mask(dst_undef(),0),
0, 0, 0, outcolor, payload_r0_depth, outdepth);
inst-Sampler = 1|(01);
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Mesa (intel-2008-q4): i965: Fix GLSL FS DPH to return the right value instead of src0.w * src1.w.
Module: Mesa Branch: intel-2008-q4 Commit: eef0dcc298f65158dc750a09f80317ded1101dc7 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=eef0dcc298f65158dc750a09f80317ded1101dc7 Author: Eric Anholt e...@anholt.net Date: Wed Jan 7 16:56:02 2009 -0800 i965: Fix GLSL FS DPH to return the right value instead of src0.w * src1.w. (cherry picked from commit 83a74521cfd2e81dd98ee1d84aff42a660613740) --- src/mesa/drivers/dri/i965/brw_wm_glsl.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index d43e326..942ebe1 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -623,7 +623,7 @@ static void emit_dph(struct brw_wm_compile *c, brw_MAC(p, brw_null_reg(), src0[1], src1[1]); brw_MAC(p, dst, src0[2], src1[2]); brw_set_saturate(p, (inst-SaturateMode != SATURATE_OFF) ? 1 : 0); -brw_ADD(p, dst, src0[3], src1[3]); +brw_ADD(p, dst, dst, src1[3]); brw_set_saturate(p, 0); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (intel-2008-q4): i965: Remove worrisome comment about _NEW_PROGRAM signaling fp change.
Module: Mesa
Branch: intel-2008-q4
Commit: 5b3bb7aaf7646ab5fb1ab632529ea0ae4511079d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b3bb7aaf7646ab5fb1ab632529ea0ae4511079d
Author: Eric Anholt e...@anholt.net
Date: Wed Jan 7 14:26:11 2009 -0800
i965: Remove worrisome comment about _NEW_PROGRAM signaling fp change.
Everything now depends on either BRW_NEW_FRAGMENT_PROGRAM or
BRW_NEW_VERTEX_PROGRAM.
(cherry picked from commit 6d2cf395f401b53da1c2fc4485a297fd975637c6)
---
src/mesa/drivers/dri/i965/brw_state_upload.c |4
1 files changed, 0 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 5124535..4845859 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -314,12 +314,8 @@ void brw_validate_state( struct brw_context *brw )
state-brw |= ~0;
}
- /* texenv program needs to notify us somehow when this happens:
-* Some confusion about which state flag should represent this change.
-*/
if (brw-fragment_program != brw-attribs.FragmentProgram-_Current) {
brw-fragment_program = brw-attribs.FragmentProgram-_Current;
- brw-state.dirty.mesa |= _NEW_PROGRAM;
brw-state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
}
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Mesa (intel-2008-q4): mesa: add GLushort cases for render to texture ( Z-buffers)
Module: Mesa
Branch: intel-2008-q4
Commit: caf684ddefe15483157f9714221096690aed3a52
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=caf684ddefe15483157f9714221096690aed3a52
Author: Brian Paul bri...@vmware.com
Date: Mon Jan 5 17:52:14 2009 -0700
mesa: add GLushort cases for render to texture (Z-buffers)
(cherry picked from commit c5c9241cca3c57684db955390410c8cda44b785e)
---
src/mesa/main/texrender.c | 52 +++-
1 files changed, 50 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/texrender.c b/src/mesa/main/texrender.c
index 163bda4..4ae13a7 100644
--- a/src/mesa/main/texrender.c
+++ b/src/mesa/main/texrender.c
@@ -49,6 +49,14 @@ texture_get_row(GLcontext *ctx, struct gl_renderbuffer *rb,
GLuint count,
trb-TexImage-FetchTexelc(trb-TexImage, x + i, y, z, rgbaOut + 4 *
i);
}
}
+ else if (rb-DataType == GL_UNSIGNED_SHORT) {
+ GLushort *zValues = (GLushort *) values;
+ for (i = 0; i count; i++) {
+ GLfloat flt;
+ trb-TexImage-FetchTexelf(trb-TexImage, x + i, y, z, flt);
+ zValues[i] = (GLushort) (flt * 0x);
+ }
+ }
else if (rb-DataType == GL_UNSIGNED_INT) {
GLuint *zValues = (GLuint *) values;
/*
@@ -96,6 +104,15 @@ texture_get_values(GLcontext *ctx, struct gl_renderbuffer
*rb, GLuint count,
z, rgbaOut + 4 * i);
}
}
+ else if (rb-DataType == GL_UNSIGNED_SHORT) {
+ GLushort *zValues = (GLushort *) values;
+ for (i = 0; i count; i++) {
+ GLfloat flt;
+ trb-TexImage-FetchTexelf(trb-TexImage, x[i], y[i] + trb-Yoffset,
+ z, flt);
+ zValues[i] = (GLushort) (flt * 0x);
+ }
+ }
else if (rb-DataType == GL_UNSIGNED_INT) {
GLuint *zValues = (GLuint *) values;
for (i = 0; i count; i++) {
@@ -147,6 +164,14 @@ texture_put_row(GLcontext *ctx, struct gl_renderbuffer
*rb, GLuint count,
rgba += 4;
}
}
+ else if (rb-DataType == GL_UNSIGNED_SHORT) {
+ const GLushort *zValues = (const GLushort *) values;
+ for (i = 0; i count; i++) {
+ if (!mask || mask[i]) {
+trb-Store(trb-TexImage, x + i, y, z, zValues + i);
+ }
+ }
+ }
else if (rb-DataType == GL_UNSIGNED_INT) {
const GLuint *zValues = (const GLuint *) values;
for (i = 0; i count; i++) {
@@ -189,6 +214,14 @@ texture_put_mono_row(GLcontext *ctx, struct
gl_renderbuffer *rb, GLuint count,
}
}
}
+ else if (rb-DataType == GL_UNSIGNED_SHORT) {
+ const GLushort zValue = *((const GLushort *) value);
+ for (i = 0; i count; i++) {
+ if (!mask || mask[i]) {
+trb-Store(trb-TexImage, x + i, y, z, zValue);
+ }
+ }
+ }
else if (rb-DataType == GL_UNSIGNED_INT) {
const GLuint zValue = *((const GLuint *) value);
for (i = 0; i count; i++) {
@@ -231,12 +264,19 @@ texture_put_values(GLcontext *ctx, struct gl_renderbuffer
*rb, GLuint count,
rgba += 4;
}
}
+ else if (rb-DataType == GL_UNSIGNED_SHORT) {
+ const GLushort *zValues = (const GLushort *) values;
+ for (i = 0; i count; i++) {
+ if (!mask || mask[i]) {
+trb-Store(trb-TexImage, x[i], y[i] + trb-Yoffset, z, zValues +
i);
+ }
+ }
+ }
else if (rb-DataType == GL_UNSIGNED_INT) {
const GLuint *zValues = (const GLuint *) values;
for (i = 0; i count; i++) {
if (!mask || mask[i]) {
-trb-Store(trb-TexImage, x[i], y[i] + trb-Yoffset, z,
- zValues + i);
+trb-Store(trb-TexImage, x[i], y[i] + trb-Yoffset, z, zValues +
i);
}
}
}
@@ -281,6 +321,14 @@ texture_put_mono_values(GLcontext *ctx, struct
gl_renderbuffer *rb,
}
}
}
+ else if (rb-DataType == GL_UNSIGNED_SHORT) {
+ const GLushort zValue = *((const GLushort *) value);
+ for (i = 0; i count; i++) {
+ if (!mask || mask[i]) {
+trb-Store(trb-TexImage, x[i], y[i] + trb-Yoffset, z, zValue);
+ }
+ }
+ }
else if (rb-DataType == GL_UNSIGNED_INT_24_8_EXT) {
const GLuint zValue = *((const GLuint *) value);
const GLfloat flt = (GLfloat) ((zValue 8) * (1.0 / 0xff));
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Mesa (intel-2008-q4): mesa: fix a GLSL swizzled writemask bug
Module: Mesa
Branch: intel-2008-q4
Commit: a39496b480cdcaeea40eb9f945428f29de7bb68b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a39496b480cdcaeea40eb9f945428f29de7bb68b
Author: Brian Paul bri...@vmware.com
Date: Mon Jan 5 13:12:12 2009 -0700
mesa: fix a GLSL swizzled writemask bug
This fixes cases such as:
vec4 v4;
vec2 v2;
v4.xz.yx = v2;
The last line now correctly compiles into MOV TEMP[1].xz, TEMP[0].yyxw;
Helps to fix the Humus Domino demo. See bug 19189.
(cherry picked from commit 9736d8f03364068c9ca786f88a4c2881d98d5768)
---
src/mesa/shader/slang/slang_codegen.c | 20 ++--
1 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/src/mesa/shader/slang/slang_codegen.c
b/src/mesa/shader/slang/slang_codegen.c
index 8abb642..5edb5b1 100644
--- a/src/mesa/shader/slang/slang_codegen.c
+++ b/src/mesa/shader/slang/slang_codegen.c
@@ -3028,6 +3028,22 @@ is_store_writable(const slang_assemble_ctx *A, const
slang_ir_storage *store)
/**
+ * Walk up an IR storage path to compute the final swizzle.
+ * This is used when we find an expression such as foo.xz.yx.
+ */
+static GLuint
+root_swizzle(const slang_ir_storage *st)
+{
+ GLuint swizzle = st-Swizzle;
+ while (st-Parent) {
+ st = st-Parent;
+ swizzle = _slang_swizzle_swizzle(st-Swizzle, swizzle);
+ }
+ return swizzle;
+}
+
+
+/**
* Generate IR tree for an assignment (=).
*/
static slang_ir_node *
@@ -3102,9 +3118,9 @@ _slang_gen_assignment(slang_assemble_ctx * A,
slang_operation *oper)
rhs = _slang_gen_operation(A, oper-children[1]);
if (lhs rhs) {
/* convert lhs swizzle into writemask */
+ const GLuint swizzle = root_swizzle(lhs-Store);
GLuint writemask, newSwizzle;
- if (!swizzle_to_writemask(A, lhs-Store-Swizzle,
- writemask, newSwizzle)) {
+ if (!swizzle_to_writemask(A, swizzle, writemask, newSwizzle)) {
/* Non-simple writemask, need to swizzle right hand side in
* order to put components into the right place.
*/
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Mesa (intel-2008-q4): i915: separate the fog term from the specular color term.
Module: Mesa
Branch: intel-2008-q4
Commit: 9d5a7eca3ef3d2d7fae7e3c773ccb5677536721a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d5a7eca3ef3d2d7fae7e3c773ccb5677536721a
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Wed Dec 24 09:26:46 2008 +0800
i915: separate the fog term from the specular color term.
Previously fog parameter and specular color are packed into the
same dword. Note specular color should be packed in BGRA for device,
so if fog parameter and specular color all are present, fog parameter
will dirty the alpha term of specular color. This fixes rendering
issue when playing 'Yo Frankie' on 915/945.
(cherry picked from commit 129b6bc4e33257dd27aa9b50c6fa934ccb14376e)
---
src/mesa/drivers/dri/i915/i915_fragprog.c | 22 +++---
1 files changed, 3 insertions(+), 19 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c
b/src/mesa/drivers/dri/i915/i915_fragprog.c
index 8bd761e..4760906 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -1105,30 +1105,14 @@ i915ValidateFragmentProgram(struct i915_context *i915)
EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, S4_VFMT_COLOR, 4);
}
- if ((inputsRead (FRAG_BIT_COL1 | FRAG_BIT_FOGC)) ||
- i915-vertex_fog != I915_FOG_NONE) {
-
- if (inputsRead FRAG_BIT_COL1) {
- intel-specoffset = offset / 4;
- EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, S4_VFMT_SPEC_FOG, 3);
- }
- else
- EMIT_PAD(3);
-
- if ((inputsRead FRAG_BIT_FOGC) || i915-vertex_fog != I915_FOG_NONE)
- EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1UB_1F, S4_VFMT_SPEC_FOG, 1);
- else
- EMIT_PAD(1);
+ if (inputsRead FRAG_BIT_COL1) {
+ intel-specoffset = offset / 4;
+ EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_4UB_4F_BGRA, S4_VFMT_SPEC_FOG, 4);
}
- /* XXX this was disabled, but enabling this code helped fix the Glean
-* tfragprog1 fog tests.
-*/
-#if 1
if ((inputsRead FRAG_BIT_FOGC) || i915-vertex_fog != I915_FOG_NONE) {
EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1F, S4_VFMT_FOG_PARAM, 4);
}
-#endif
for (i = 0; i p-ctx-Const.MaxTextureCoordUnits; i++) {
if (inputsRead FRAG_BIT_TEX(i)) {
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Mesa (intel-2008-q4): intel: enable ATI_texture_env_combine3. Fixes #17707
Module: Mesa
Branch: intel-2008-q4
Commit: fe3eef8ef262af56d8dcd9b2565a1a5e8a8a00f1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fe3eef8ef262af56d8dcd9b2565a1a5e8a8a00f1
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Mon Dec 29 09:30:41 2008 +0800
intel: enable ATI_texture_env_combine3. Fixes #17707
(cherry picked from commit 0674a238547f9f4f9de9c6cf5d72015e5960aa9e)
---
src/mesa/drivers/dri/intel/intel_context.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_context.c
b/src/mesa/drivers/dri/intel/intel_context.c
index 6c625b4..65c27a5 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -388,6 +388,7 @@ static const struct dri_extension card_extensions[] = {
{ GL_NV_vertex_program, GL_NV_vertex_program_functions },
{ GL_NV_vertex_program1_1, NULL },
{ GL_SGIS_generate_mipmap, NULL },
+ { GL_ATI_texture_env_combine3, NULL },
{ NULL, NULL }
};
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Mesa (intel-2008-q4): dri: Fix driWaitForMSC32 when divisor = 2 and msc 0.
Module: Mesa
Branch: intel-2008-q4
Commit: 37f489edd217f7a92998b7ca9207d43e2860b357
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=37f489edd217f7a92998b7ca9207d43e2860b357
Author: Eric Anholt e...@anholt.net
Date: Tue Dec 23 16:08:40 2008 -0800
dri: Fix driWaitForMSC32 when divisor = 2 and msc 0.
We'd come up with a negative remainder, while we were looking for the positive
version of it in the loop conditional. And, since the did we hit our target
break was disabled for the target_msc == 0 (Just make the divisor/remainder
work) path, we'd never exit.
Simplify the code by just using int64_t all over instead of trying to do it
in a u32 space.
(cherry picked from commit 6c01500228014a6cfa133b5dbba8c6d024833e84)
---
src/mesa/drivers/dri/common/vblank.c | 18 +-
1 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/common/vblank.c
b/src/mesa/drivers/dri/common/vblank.c
index d610253..12aeaa1 100644
--- a/src/mesa/drivers/dri/common/vblank.c
+++ b/src/mesa/drivers/dri/common/vblank.c
@@ -130,9 +130,8 @@ int driWaitForMSC32( __DRIdrawablePrivate *priv,
if ( divisor != 0 ) {
- unsigned int target = (unsigned int)target_msc;
- unsigned int next = target;
- unsigned int r;
+ int64_t next = target_msc;
+ int64_t r;
int dont_wait = (target_msc == 0);
do {
@@ -154,9 +153,9 @@ int driWaitForMSC32( __DRIdrawablePrivate *priv,
*msc = vblank_to_msc(priv, vbl.reply.sequence);
- dont_wait = 0;
- if (target_msc != 0 *msc == target)
+ if (!dont_wait *msc == next)
break;
+ dont_wait = 0;
/* Assuming the wait-done test fails, the next refresh to wait for
* will be one that satisfies (MSC % divisor) == remainder. The
@@ -165,11 +164,12 @@ int driWaitForMSC32( __DRIdrawablePrivate *priv,
* If this refresh has already happened, we add divisor to obtain
* the next refresh after the current one that will satisfy it.
*/
- r = (*msc % (unsigned int)divisor);
- next = (*msc - r + (unsigned int)remainder);
- if (next = *msc) next += (unsigned int)divisor;
+ r = ((uint64_t)*msc % divisor);
+ next = (*msc - r + remainder);
+ if (next = *msc)
+ next += divisor;
- } while ( r != (unsigned int)remainder );
+ } while (r != remainder);
}
else {
/* If the \c divisor is zero, just wait until the MSC is greater
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Mesa (intel-2008-q4): intel: disable ATI_texture_env_combine3 for i830( and related device).
Module: Mesa
Branch: intel-2008-q4
Commit: 7dd810c4618a93ac4a9315d92d052ff6178dd85c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7dd810c4618a93ac4a9315d92d052ff6178dd85c
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Tue Dec 30 11:25:45 2008 +0800
intel: disable ATI_texture_env_combine3 for i830( and related device).
Thanks to Eric for pointing it out.
(cherry picked from commit 0c4346e63258bcaaae6f3045bc44d0e24073dd0e)
---
src/mesa/drivers/dri/i915/i915_context.c |1 +
src/mesa/drivers/dri/intel/intel_context.c |2 +-
2 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i915_context.c
b/src/mesa/drivers/dri/i915/i915_context.c
index e0ddc7f..9bff742 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -55,6 +55,7 @@ static const struct dri_extension i915_extensions[] = {
{GL_ARB_fragment_program, NULL},
{GL_ARB_shadow, NULL},
{GL_ARB_texture_non_power_of_two, NULL},
+ {GL_ATI_texture_env_combine3, NULL},
{GL_EXT_shadow_funcs, NULL},
{NULL, NULL}
};
diff --git a/src/mesa/drivers/dri/intel/intel_context.c
b/src/mesa/drivers/dri/intel/intel_context.c
index 65c27a5..c779e2d 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -388,7 +388,6 @@ static const struct dri_extension card_extensions[] = {
{ GL_NV_vertex_program, GL_NV_vertex_program_functions },
{ GL_NV_vertex_program1_1, NULL },
{ GL_SGIS_generate_mipmap, NULL },
- { GL_ATI_texture_env_combine3, NULL },
{ NULL, NULL }
};
@@ -413,6 +412,7 @@ static const struct dri_extension brw_extensions[] = {
{ GL_EXT_shadow_funcs, NULL },
{ GL_EXT_texture_sRGB, NULL },
{ GL_ATI_separate_stencil, GL_ATI_separate_stencil_functions },
+ { GL_ATI_texture_env_combine3, NULL },
{ NULL,NULL }
};
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Mesa (intel-2008-q4): mesa: fix bug in evaluation of structure fields
Module: Mesa
Branch: intel-2008-q4
Commit: 41a9768b1037da9bb9246de068ebc5d2392197ad
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=41a9768b1037da9bb9246de068ebc5d2392197ad
Author: Brian Paul bri...@vmware.com
Date: Tue Dec 30 17:50:39 2008 -0700
mesa: fix bug in evaluation of structure fields
Fixes incorrect size information. See bug 19273.
(cherry picked from commit e8d7db31e2a6784c765911233cb3d888f612837f)
---
src/mesa/shader/slang/slang_emit.c |4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/src/mesa/shader/slang/slang_emit.c
b/src/mesa/shader/slang/slang_emit.c
index e3cb252..08230f0 100644
--- a/src/mesa/shader/slang/slang_emit.c
+++ b/src/mesa/shader/slang/slang_emit.c
@@ -1963,9 +1963,7 @@ emit_struct_field(slang_emit_info *emitInfo,
slang_ir_node *n)
_slang_copy_ir_storage(n-Store, n-Children[0]-Store);
n-Store-Index = n-Children[0]-Store-Index + fieldOffset / 4;
- /* XXX test this:
- n-Store-Index += fieldOffset / 4;
- */
+ n-Store-Size = fieldSize;
switch (fieldSize) {
case 1:
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Mesa (intel-2008-q4): intel: Share passthrough transform setup between glBitmap and glDrawPixels.
Module: Mesa
Branch: intel-2008-q4
Commit: 33459bcacea47ff6c32de9b29a99514cfc820c72
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=33459bcacea47ff6c32de9b29a99514cfc820c72
Author: Eric Anholt e...@anholt.net
Date: Wed Dec 31 00:29:49 2008 -0800
intel: Share passthrough transform setup between glBitmap and glDrawPixels.
The DrawPixels path was missing glViewport care, so blender's toolbar icons
would go to the wrong places.
Bug #19118.
(cherry picked from commit bfebeffc0045266d354a36968336337e099a9f27)
---
src/mesa/drivers/dri/intel/intel_context.h |3 ++
src/mesa/drivers/dri/intel/intel_pixel.c| 35 ++
src/mesa/drivers/dri/intel/intel_pixel.h|3 +-
src/mesa/drivers/dri/intel/intel_pixel_bitmap.c | 20 ++---
src/mesa/drivers/dri/intel/intel_pixel_draw.c | 36 ++-
5 files changed, 52 insertions(+), 45 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_context.h
b/src/mesa/drivers/dri/intel/intel_context.h
index 4d0ae0e..45beb91 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -165,6 +165,9 @@ struct intel_context
GLboolean saved_fp_enable;
struct gl_vertex_program *saved_vp;
GLboolean saved_vp_enable;
+
+ GLint saved_vp_x, saved_vp_y;
+ GLsizei saved_vp_width, saved_vp_height;
} meta;
GLint refcount;
diff --git a/src/mesa/drivers/dri/intel/intel_pixel.c
b/src/mesa/drivers/dri/intel/intel_pixel.c
index 91027d3..cf2f32d 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel.c
@@ -29,6 +29,7 @@
#include main/state.h
#include main/context.h
#include main/enable.h
+#include main/matrix.h
#include swrast/swrast.h
#include shader/arbprogram.h
#include shader/program.h
@@ -171,6 +172,40 @@ intel_check_blit_format(struct intel_region * region,
return GL_FALSE;
}
+void
+intel_meta_set_passthrough_transform(struct intel_context *intel)
+{
+ GLcontext *ctx = intel-ctx;
+
+ intel-meta.saved_vp_x = ctx-Viewport.X;
+ intel-meta.saved_vp_y = ctx-Viewport.Y;
+ intel-meta.saved_vp_width = ctx-Viewport.Width;
+ intel-meta.saved_vp_height = ctx-Viewport.Height;
+
+ _mesa_Viewport(0, 0, ctx-DrawBuffer-Width, ctx-DrawBuffer-Height);
+
+ _mesa_MatrixMode(GL_PROJECTION);
+ _mesa_PushMatrix();
+ _mesa_LoadIdentity();
+ _mesa_Ortho(0, ctx-DrawBuffer-Width, 0, ctx-DrawBuffer-Height, 1, -1);
+
+ _mesa_MatrixMode(GL_MODELVIEW);
+ _mesa_PushMatrix();
+ _mesa_LoadIdentity();
+}
+
+void
+intel_meta_restore_transform(struct intel_context *intel)
+{
+ _mesa_MatrixMode(GL_PROJECTION);
+ _mesa_PopMatrix();
+ _mesa_MatrixMode(GL_MODELVIEW);
+ _mesa_PopMatrix();
+
+ _mesa_Viewport(intel-meta.saved_vp_x, intel-meta.saved_vp_y,
+ intel-meta.saved_vp_width, intel-meta.saved_vp_height);
+}
+
/**
* Set up a vertex program to pass through the position and first texcoord
* for pixel path.
diff --git a/src/mesa/drivers/dri/intel/intel_pixel.h
b/src/mesa/drivers/dri/intel/intel_pixel.h
index 9556efc..76b8781 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel.h
+++ b/src/mesa/drivers/dri/intel/intel_pixel.h
@@ -31,7 +31,8 @@
#include main/mtypes.h
void intelInitPixelFuncs(struct dd_function_table *functions);
-
+void intel_meta_set_passthrough_transform(struct intel_context *intel);
+void intel_meta_restore_transform(struct intel_context *intel);
void intel_meta_set_passthrough_vertex_program(struct intel_context *intel);
void intel_meta_restore_vertex_program(struct intel_context *intel);
void intel_meta_set_fragment_program(struct intel_context *intel,
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
index 88e181a..1d7f15f 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
@@ -39,7 +39,6 @@
#include main/texobj.h
#include main/texstate.h
#include main/texparam.h
-#include main/matrix.h
#include main/varray.h
#include main/attrib.h
#include main/enable.h
@@ -425,7 +424,7 @@ intel_texture_bitmap(GLcontext * ctx,
}
/* Save GL state before we start setting up our drawing */
- _mesa_PushAttrib(GL_ENABLE_BIT | GL_TRANSFORM_BIT | GL_CURRENT_BIT |
+ _mesa_PushAttrib(GL_ENABLE_BIT | GL_CURRENT_BIT |
GL_VIEWPORT_BIT);
_mesa_PushClientAttrib(GL_CLIENT_VERTEX_ARRAY_BIT |
GL_CLIENT_PIXEL_STORE_BIT);
@@ -451,20 +450,11 @@ intel_texture_bitmap(GLcontext * ctx,
GL_ALPHA, GL_UNSIGNED_BYTE, a8_bitmap);
_mesa_free(a8_bitmap);
- _mesa_Viewport(0, 0, ctx-DrawBuffer-Width, ctx-DrawBuffer-Height);
- _mesa_MatrixMode(GL_PROJECTION);
- _mesa_PushMatrix();
- _mesa_LoadIdentity();
- _mesa_Ortho(0, ctx-DrawBuffer-Width, 0, ctx-DrawBuffer-Height, 1, -1);
-
- _mesa_MatrixMode(GL_MODELVIEW);
- _mesa_PushMatrix();
-
Mesa (intel-2008-q4): intel: Add support for glBitmap as metaops using GL calls.
Module: Mesa
Branch: intel-2008-q4
Commit: 425ede63089b1a13c9ef74d6b76b07501827fbb7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=425ede63089b1a13c9ef74d6b76b07501827fbb7
Author: Eric Anholt e...@anholt.net
Date: Wed Dec 31 00:02:43 2008 -0800
intel: Add support for glBitmap as metaops using GL calls.
This lets us avoid software fallbacks when clients forget to turn some state
off (engine demo) or just do crazy things to test conformance (OGLC).
This should probably be brought into mesa generic code so other drivers can
make use of it.
Bug #19016.
(cherry picked from commit e1a92175542c6645c23cc78f2a4fcd36dd0235e6)
---
src/mesa/drivers/dri/intel/intel_context.h | 10 ++
src/mesa/drivers/dri/intel/intel_pixel.c| 133 +++
src/mesa/drivers/dri/intel/intel_pixel.h|8 +
src/mesa/drivers/dri/intel/intel_pixel_bitmap.c | 199 +++
4 files changed, 350 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_context.h
b/src/mesa/drivers/dri/intel/intel_context.h
index ee43ed7..4d0ae0e 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -157,6 +157,16 @@ struct intel_context
void (*debug_batch)(struct intel_context *intel);
} vtbl;
+ struct {
+ struct gl_fragment_program *bitmap_fp;
+ struct gl_vertex_program *passthrough_vp;
+
+ struct gl_fragment_program *saved_fp;
+ GLboolean saved_fp_enable;
+ struct gl_vertex_program *saved_vp;
+ GLboolean saved_vp_enable;
+ } meta;
+
GLint refcount;
GLuint Fallback;
GLuint NewGLState;
diff --git a/src/mesa/drivers/dri/intel/intel_pixel.c
b/src/mesa/drivers/dri/intel/intel_pixel.c
index 5702ad9..91027d3 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel.c
@@ -27,7 +27,11 @@
#include main/enums.h
#include main/state.h
+#include main/context.h
+#include main/enable.h
#include swrast/swrast.h
+#include shader/arbprogram.h
+#include shader/program.h
#include intel_context.h
#include intel_pixel.h
@@ -167,6 +171,125 @@ intel_check_blit_format(struct intel_region * region,
return GL_FALSE;
}
+/**
+ * Set up a vertex program to pass through the position and first texcoord
+ * for pixel path.
+ */
+void
+intel_meta_set_passthrough_vertex_program(struct intel_context *intel)
+{
+ GLcontext *ctx = intel-ctx;
+ static const char *vp =
+ !!ARBvp1.0\n
+ TEMP vertexClip;\n
+ DP4 vertexClip.x, state.matrix.mvp.row[0], vertex.position;\n
+ DP4 vertexClip.y, state.matrix.mvp.row[1], vertex.position;\n
+ DP4 vertexClip.z, state.matrix.mvp.row[2], vertex.position;\n
+ DP4 vertexClip.w, state.matrix.mvp.row[3], vertex.position;\n
+ MOV result.position, vertexClip;\n
+ MOV result.texcoord[0], vertex.texcoord[0];\n
+ MOV result.color, vertex.color;\n
+ END\n;
+
+ assert(intel-meta.saved_vp == NULL);
+
+ _mesa_reference_vertprog(ctx, intel-meta.saved_vp,
+ ctx-VertexProgram.Current);
+ if (intel-meta.passthrough_vp == NULL) {
+ GLuint prog_name;
+ _mesa_GenPrograms(1, prog_name);
+ _mesa_BindProgram(GL_VERTEX_PROGRAM_ARB, prog_name);
+ _mesa_ProgramStringARB(GL_VERTEX_PROGRAM_ARB,
+GL_PROGRAM_FORMAT_ASCII_ARB,
+strlen(vp), (const GLubyte *)vp);
+ _mesa_reference_vertprog(ctx, intel-meta.passthrough_vp,
+ ctx-VertexProgram.Current);
+ _mesa_DeletePrograms(1, prog_name);
+ }
+
+ FLUSH_VERTICES(ctx, _NEW_PROGRAM);
+ _mesa_reference_vertprog(ctx, ctx-VertexProgram.Current,
+ intel-meta.passthrough_vp);
+ ctx-Driver.BindProgram(ctx, GL_VERTEX_PROGRAM_ARB,
+ intel-meta.passthrough_vp-Base);
+
+ intel-meta.saved_vp_enable = ctx-VertexProgram.Enabled;
+ _mesa_Enable(GL_VERTEX_PROGRAM_ARB);
+}
+
+/**
+ * Restores the previous vertex program after
+ * intel_meta_set_passthrough_vertex_program()
+ */
+void
+intel_meta_restore_vertex_program(struct intel_context *intel)
+{
+ GLcontext *ctx = intel-ctx;
+
+ FLUSH_VERTICES(ctx, _NEW_PROGRAM);
+ _mesa_reference_vertprog(ctx, ctx-VertexProgram.Current,
+ intel-meta.saved_vp);
+ _mesa_reference_vertprog(ctx, intel-meta.saved_vp, NULL);
+ ctx-Driver.BindProgram(ctx, GL_VERTEX_PROGRAM_ARB,
+ ctx-VertexProgram.Current-Base);
+
+ if (!intel-meta.saved_vp_enable)
+ _mesa_Disable(GL_VERTEX_PROGRAM_ARB);
+}
+
+/**
+ * Binds the given program string to GL_FRAGMENT_PROGRAM_ARB, caching the
+ * program object.
+ */
+void
+intel_meta_set_fragment_program(struct intel_context *intel,
+ struct gl_fragment_program **prog,
+ const char *prog_string)
+{
+ GLcontext *ctx = intel-ctx;
+ assert(intel-meta.saved_fp ==
Mesa (intel-2008-q4): i965: added OPCODE_NRM3/4
Module: Mesa
Branch: intel-2008-q4
Commit: b9921a9fb2bc937194eac7e80e31d30f81cb6bb1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9921a9fb2bc937194eac7e80e31d30f81cb6bb1
Author: Brian Paul bri...@vmware.com
Date: Wed Dec 31 17:16:44 2008 -0700
i965: added OPCODE_NRM3/4
(cherry picked from commit 32e03c4a2ff5ef07de892dcd26f6be3b82ab3ba1)
---
src/mesa/drivers/dri/i965/brw_wm.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c
b/src/mesa/drivers/dri/i965/brw_wm.c
index bad7679..5b4ee20 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -36,6 +36,7 @@
#include brw_state.h
+/** Return number of src args for given instruction */
GLuint brw_wm_nr_args( GLuint opcode )
{
switch (opcode) {
@@ -58,6 +59,8 @@ GLuint brw_wm_nr_args( GLuint opcode )
case OPCODE_TXP:
case OPCODE_KIL:
case OPCODE_LIT:
+ case OPCODE_NRM3:
+ case OPCODE_NRM4:
case WM_CINTERP:
case WM_WPOSXY:
return 1;
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Mesa (intel-2008-q4): i965: implement OPCODE_NRM3/NRM4
Module: Mesa
Branch: intel-2008-q4
Commit: 815f6664389fc51245cc1451225e1714d8daa7bf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=815f6664389fc51245cc1451225e1714d8daa7bf
Author: Brian Paul bri...@vmware.com
Date: Wed Dec 31 16:49:58 2008 -0700
i965: implement OPCODE_NRM3/NRM4
---
src/mesa/drivers/dri/i965/brw_vs_emit.c | 33 --
1 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c
b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index 4a95413..b594e47 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -596,7 +596,29 @@ static void emit_lit_noalias( struct brw_vs_compile *c,
}
+/** 3 or 4-component vector normalization */
+static void emit_nrm( struct brw_vs_compile *c,
+ struct brw_reg dst,
+ struct brw_reg arg0,
+ int num_comps)
+{
+ struct brw_compile *p = c-func;
+ struct brw_reg tmp = get_tmp(c);
+
+ /* tmp = dot(arg0, arg0) */
+ if (num_comps == 3)
+ brw_DP3(p, tmp, arg0, arg0);
+ else
+ brw_DP4(p, tmp, arg0, arg0);
+ /* tmp = 1 / tmp */
+ emit_math1(c, BRW_MATH_FUNCTION_RSQ, tmp, tmp, BRW_MATH_PRECISION_FULL);
+
+ /* dst = arg0 * tmp */
+ brw_MUL(p, dst, arg0, tmp);
+
+ release_tmp(c, tmp);
+}
/* TODO: relative addressing!
@@ -1035,6 +1057,12 @@ void brw_vs_emit(struct brw_vs_compile *c )
case OPCODE_DPH:
brw_DPH(p, dst, args[0], args[1]);
break;
+ case OPCODE_NRM3:
+emit_nrm(c, dst, args[0], 3);
+break;
+ case OPCODE_NRM4:
+emit_nrm(c, dst, args[0], 4);
+break;
case OPCODE_DST:
unalias2(c, dst, args[0], args[1], emit_dst_noalias);
break;
@@ -1160,11 +1188,10 @@ void brw_vs_emit(struct brw_vs_compile *c )
case OPCODE_ENDSUB:
break;
default:
-_mesa_printf(Unsupported opcode %i (%s) in vertex shader\n,
- inst-Opcode, inst-Opcode MAX_OPCODE ?
+_mesa_problem(NULL, Unsupported opcode %i (%s) in vertex shader,
+ inst-Opcode, inst-Opcode MAX_OPCODE ?
_mesa_opcode_string(inst-Opcode) :
unknown);
-break;
}
if ((inst-DstReg.File == PROGRAM_OUTPUT)
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Mesa (master): dri: correct the damage.
Module: Mesa
Branch: master
Commit: 7627c7f5dfa3b1bc7be9d1670668a81a70d9f64a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7627c7f5dfa3b1bc7be9d1670668a81a70d9f64a
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Tue Jan 6 11:22:19 2009 +0800
dri: correct the damage.
Fixes bug #17234
---
src/mesa/drivers/dri/common/dri_util.c | 19 +--
1 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/common/dri_util.c
b/src/mesa/drivers/dri/common/dri_util.c
index e9b1a80..ae79055 100644
--- a/src/mesa/drivers/dri/common/dri_util.c
+++ b/src/mesa/drivers/dri/common/dri_util.c
@@ -314,13 +314,28 @@ static void driReportDamage(__DRIdrawable *pdp,
static void driSwapBuffers(__DRIdrawable *dPriv)
{
__DRIscreen *psp = dPriv-driScreenPriv;
-
+drm_clip_rect_t *rects;
+int i;
+
if (!dPriv-numClipRects)
return;
psp-DriverAPI.SwapBuffers(dPriv);
-driReportDamage(dPriv, dPriv-pClipRects, dPriv-numClipRects);
+rects = _mesa_malloc(sizeof(*rects) * dPriv-numClipRects);
+
+if (!rects)
+return;
+
+for (i = 0; i dPriv-numClipRects; i++) {
+rects[i].x1 = dPriv-pClipRects[i].x1 - dPriv-x;
+rects[i].y1 = dPriv-pClipRects[i].y1 - dPriv-y;
+rects[i].x2 = dPriv-pClipRects[i].x2 - dPriv-x;
+rects[i].y2 = dPriv-pClipRects[i].y2 - dPriv-y;
+}
+
+driReportDamage(dPriv, rects, dPriv-numClipRects);
+_mesa_free(rects);
}
static int driDrawableGetMSC( __DRIscreen *sPriv, __DRIdrawable *dPriv,
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Mesa (master): mesa: Fix the number of components for GL_UNSIGNED_SHORT_1_5_5_5_REV. ( bug #19390)
Module: Mesa Branch: master Commit: 241c0bfc985363bb15e6cc0eca859c6ec36d1b35 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=241c0bfc985363bb15e6cc0eca859c6ec36d1b35 Author: Xiang, Haihao haihao.xi...@intel.com Date: Tue Jan 6 15:30:34 2009 +0800 mesa: Fix the number of components for GL_UNSIGNED_SHORT_1_5_5_5_REV. (bug #19390) --- src/mesa/main/texformat.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/main/texformat.c b/src/mesa/main/texformat.c index 4442ce3..1dd7bdd 100644 --- a/src/mesa/main/texformat.c +++ b/src/mesa/main/texformat.c @@ -1641,7 +1641,7 @@ _mesa_format_to_type_and_comps(const struct gl_texture_format *format, case MESA_FORMAT_ARGB1555: case MESA_FORMAT_ARGB1555_REV: *datatype = GL_UNSIGNED_SHORT_1_5_5_5_REV; - *comps = 3; + *comps = 4; return; case MESA_FORMAT_AL88: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa: Fix the size per pixel for packed pixel format data type.
Module: Mesa
Branch: master
Commit: f1f022dbb103947b0edf5ae984fcff00f6a8e539
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f1f022dbb103947b0edf5ae984fcff00f6a8e539
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Tue Jan 6 15:37:45 2009 +0800
mesa: Fix the size per pixel for packed pixel format data type.
---
src/mesa/main/image.c |2 +-
src/mesa/main/image.h |3 +++
src/mesa/main/mipmap.c |6 +-
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/image.c b/src/mesa/main/image.c
index c205b4b..4d86c54 100644
--- a/src/mesa/main/image.c
+++ b/src/mesa/main/image.c
@@ -61,7 +61,7 @@
/**
* \return GL_TRUE if type is packed pixel type, GL_FALSE otherwise.
*/
-static GLboolean
+GLboolean
_mesa_type_is_packed(GLenum type)
{
switch (type) {
diff --git a/src/mesa/main/image.h b/src/mesa/main/image.h
index 38e1374..0e0bbd9 100644
--- a/src/mesa/main/image.h
+++ b/src/mesa/main/image.h
@@ -36,6 +36,9 @@ _mesa_swap2( GLushort *p, GLuint n );
extern void
_mesa_swap4( GLuint *p, GLuint n );
+extern GLboolean
+_mesa_type_is_packed(GLenum type);
+
extern GLint
_mesa_sizeof_type( GLenum type );
diff --git a/src/mesa/main/mipmap.c b/src/mesa/main/mipmap.c
index 9e051ac..3dd4b33 100644
--- a/src/mesa/main/mipmap.c
+++ b/src/mesa/main/mipmap.c
@@ -41,7 +41,11 @@ bytes_per_pixel(GLenum datatype, GLuint comps)
{
GLint b = _mesa_sizeof_packed_type(datatype);
assert(b = 0);
- return b * comps;
+
+ if (_mesa_type_is_packed(datatype))
+ return b;
+ else
+ return b * comps;
}
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Mesa (master): intel: disable ATI_texture_env_combine3 for i830( and related device).
Module: Mesa
Branch: master
Commit: 0c4346e63258bcaaae6f3045bc44d0e24073dd0e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c4346e63258bcaaae6f3045bc44d0e24073dd0e
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Tue Dec 30 11:25:45 2008 +0800
intel: disable ATI_texture_env_combine3 for i830( and related device).
Thanks to Eric for pointing it out.
---
src/mesa/drivers/dri/i915/i915_context.c |1 +
src/mesa/drivers/dri/intel/intel_context.c |2 +-
2 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i915_context.c
b/src/mesa/drivers/dri/i915/i915_context.c
index e0ddc7f..9bff742 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -55,6 +55,7 @@ static const struct dri_extension i915_extensions[] = {
{GL_ARB_fragment_program, NULL},
{GL_ARB_shadow, NULL},
{GL_ARB_texture_non_power_of_two, NULL},
+ {GL_ATI_texture_env_combine3, NULL},
{GL_EXT_shadow_funcs, NULL},
{NULL, NULL}
};
diff --git a/src/mesa/drivers/dri/intel/intel_context.c
b/src/mesa/drivers/dri/intel/intel_context.c
index 83661df..44b276a 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -388,7 +388,6 @@ static const struct dri_extension card_extensions[] = {
{ GL_NV_vertex_program, GL_NV_vertex_program_functions },
{ GL_NV_vertex_program1_1, NULL },
{ GL_SGIS_generate_mipmap, NULL },
- { GL_ATI_texture_env_combine3, NULL },
{ NULL, NULL }
};
@@ -413,6 +412,7 @@ static const struct dri_extension brw_extensions[] = {
{ GL_EXT_shadow_funcs, NULL },
{ GL_EXT_texture_sRGB, NULL },
{ GL_ATI_separate_stencil, GL_ATI_separate_stencil_functions },
+ { GL_ATI_texture_env_combine3, NULL },
{ NULL,NULL }
};
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Mesa (master): intel: enable ATI_texture_env_combine3. Fixes #17707
Module: Mesa
Branch: master
Commit: 0674a238547f9f4f9de9c6cf5d72015e5960aa9e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0674a238547f9f4f9de9c6cf5d72015e5960aa9e
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Mon Dec 29 09:30:41 2008 +0800
intel: enable ATI_texture_env_combine3. Fixes #17707
---
src/mesa/drivers/dri/intel/intel_context.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_context.c
b/src/mesa/drivers/dri/intel/intel_context.c
index 6ff98e9..83661df 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -388,6 +388,7 @@ static const struct dri_extension card_extensions[] = {
{ GL_NV_vertex_program, GL_NV_vertex_program_functions },
{ GL_NV_vertex_program1_1, NULL },
{ GL_SGIS_generate_mipmap, NULL },
+ { GL_ATI_texture_env_combine3, NULL },
{ NULL, NULL }
};
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Mesa (master): i915: separate the fog term from the specular color term.
Module: Mesa
Branch: master
Commit: 129b6bc4e33257dd27aa9b50c6fa934ccb14376e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=129b6bc4e33257dd27aa9b50c6fa934ccb14376e
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Wed Dec 24 09:26:46 2008 +0800
i915: separate the fog term from the specular color term.
Previously fog parameter and specular color are packed into the
same dword. Note specular color should be packed in BGRA for device,
so if fog parameter and specular color all are present, fog parameter
will dirty the alpha term of specular color. This fixes rendering
issue when playing 'Yo Frankie' on 915/945.
---
src/mesa/drivers/dri/i915/i915_fragprog.c | 22 +++---
1 files changed, 3 insertions(+), 19 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c
b/src/mesa/drivers/dri/i915/i915_fragprog.c
index 8bd761e..4760906 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -1105,30 +1105,14 @@ i915ValidateFragmentProgram(struct i915_context *i915)
EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, S4_VFMT_COLOR, 4);
}
- if ((inputsRead (FRAG_BIT_COL1 | FRAG_BIT_FOGC)) ||
- i915-vertex_fog != I915_FOG_NONE) {
-
- if (inputsRead FRAG_BIT_COL1) {
- intel-specoffset = offset / 4;
- EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, S4_VFMT_SPEC_FOG, 3);
- }
- else
- EMIT_PAD(3);
-
- if ((inputsRead FRAG_BIT_FOGC) || i915-vertex_fog != I915_FOG_NONE)
- EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1UB_1F, S4_VFMT_SPEC_FOG, 1);
- else
- EMIT_PAD(1);
+ if (inputsRead FRAG_BIT_COL1) {
+ intel-specoffset = offset / 4;
+ EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_4UB_4F_BGRA, S4_VFMT_SPEC_FOG, 4);
}
- /* XXX this was disabled, but enabling this code helped fix the Glean
-* tfragprog1 fog tests.
-*/
-#if 1
if ((inputsRead FRAG_BIT_FOGC) || i915-vertex_fog != I915_FOG_NONE) {
EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1F, S4_VFMT_FOG_PARAM, 4);
}
-#endif
for (i = 0; i p-ctx-Const.MaxTextureCoordUnits; i++) {
if (inputsRead FRAG_BIT_TEX(i)) {
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Mesa (master): i915: fix abort issue. (bug #19147)
Module: Mesa
Branch: master
Commit: df73363ed1aa34cc0dc5feefb3933309591fa015
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=df73363ed1aa34cc0dc5feefb3933309591fa015
Author: Xiang, Haihao haihao.xi...@intel.com
Date: Thu Dec 18 10:07:45 2008 +0800
i915: fix abort issue. (bug #19147)
---
src/mesa/drivers/dri/i915/i830_vtbl.c | 15 +--
src/mesa/drivers/dri/i915/i915_vtbl.c | 13 +++--
2 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c
b/src/mesa/drivers/dri/i915/i830_vtbl.c
index 3b3ff2b..8fc8aa5 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -297,7 +297,7 @@ i830_emit_invarient_state(struct intel_context *intel)
{
BATCH_LOCALS;
- BEGIN_BATCH(40, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(30, IGNORE_CLIPRECTS);
OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
OUT_BATCH(0);
@@ -491,8 +491,17 @@ i830_emit_state(struct intel_context *intel)
}
if (dirty I830_UPLOAD_BUFFERS) {
+ GLuint count = 9;
+
DBG(I830_UPLOAD_BUFFERS:\n);
- BEGIN_BATCH(I830_DEST_SETUP_SIZE + 2, IGNORE_CLIPRECTS);
+
+ if (state-depth_region)
+ count += 3;
+
+ if (intel-constant_cliprect)
+ count += 6;
+
+ BEGIN_BATCH(count, IGNORE_CLIPRECTS);
OUT_BATCH(state-Buffer[I830_DESTREG_CBUFADDR0]);
OUT_BATCH(state-Buffer[I830_DESTREG_CBUFADDR1]);
OUT_RELOC(state-draw_region-buffer,
@@ -557,6 +566,8 @@ i830_emit_state(struct intel_context *intel)
OUT_BATCH(state-Tex[i][I830_TEXREG_TM0S4]);
OUT_BATCH(state-Tex[i][I830_TEXREG_MCS]);
OUT_BATCH(state-Tex[i][I830_TEXREG_CUBE]);
+
+ ADVANCE_BATCH();
}
if (dirty I830_UPLOAD_TEXBLEND(i)) {
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c
b/src/mesa/drivers/dri/i915/i915_vtbl.c
index e79c955..3f6d282 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -173,7 +173,7 @@ i915_emit_invarient_state(struct intel_context *intel)
{
BATCH_LOCALS;
- BEGIN_BATCH(200, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(20, IGNORE_CLIPRECTS);
OUT_BATCH(_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
@@ -376,9 +376,18 @@ i915_emit_state(struct intel_context *intel)
}
if (dirty I915_UPLOAD_BUFFERS) {
+ GLuint count = 9;
+
if (INTEL_DEBUG DEBUG_STATE)
fprintf(stderr, I915_UPLOAD_BUFFERS:\n);
- BEGIN_BATCH(I915_DEST_SETUP_SIZE + 2, IGNORE_CLIPRECTS);
+
+ if (state-depth_region)
+ count += 3;
+
+ if (intel-constant_cliprect)
+ count += 6;
+
+ BEGIN_BATCH(count, IGNORE_CLIPRECTS);
OUT_BATCH(state-Buffer[I915_DESTREG_CBUFADDR0]);
OUT_BATCH(state-Buffer[I915_DESTREG_CBUFADDR1]);
OUT_RELOC(state-draw_region-buffer,
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Mesa (master): i915: check WRAP_T instead of WRAP_R for cube map texture.
Module: Mesa Branch: master Commit: cb453244caa15342bf229ee5ae16a78d038b8bdc URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb453244caa15342bf229ee5ae16a78d038b8bdc Author: Xiang, Haihao haihao.xi...@intel.com Date: Thu Dec 18 12:57:41 2008 +0800 i915: check WRAP_T instead of WRAP_R for cube map texture. --- src/mesa/drivers/dri/i915/i915_texstate.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index d53e2cb..adbb52a 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -300,7 +300,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) */ if (tObj-Target == GL_TEXTURE_CUBE_MAP_ARB (((ws != GL_CLAMP) (ws != GL_CLAMP_TO_EDGE)) || - ((wr != GL_CLAMP) (wr != GL_CLAMP_TO_EDGE + ((wt != GL_CLAMP) (wt != GL_CLAMP_TO_EDGE return GL_FALSE; state[I915_TEXREG_SS3] = ss3; /* SS3_NORMALIZED_COORDS */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (intel-2008-q4): i915: check WRAP_T instead of WRAP_R for cube map texture.
Module: Mesa Branch: intel-2008-q4 Commit: f96baeaac3ef41260ac3975750627ece073fdce0 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f96baeaac3ef41260ac3975750627ece073fdce0 Author: Xiang, Haihao haihao.xi...@intel.com Date: Thu Dec 18 12:57:41 2008 +0800 i915: check WRAP_T instead of WRAP_R for cube map texture. (cherry picked from commit cb453244caa15342bf229ee5ae16a78d038b8bdc) --- src/mesa/drivers/dri/i915/i915_texstate.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index d53e2cb..adbb52a 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -300,7 +300,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) */ if (tObj-Target == GL_TEXTURE_CUBE_MAP_ARB (((ws != GL_CLAMP) (ws != GL_CLAMP_TO_EDGE)) || - ((wr != GL_CLAMP) (wr != GL_CLAMP_TO_EDGE + ((wt != GL_CLAMP) (wt != GL_CLAMP_TO_EDGE return GL_FALSE; state[I915_TEXREG_SS3] = ss3; /* SS3_NORMALIZED_COORDS */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (intel-2008-q4): 26 new commits
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d5b1e591b7fb2cf3109b7e147bb3ea6aa8f8b15 Author: Ian Romanick ian.d.roman...@intel.com Date: Sun Dec 14 18:42:11 2008 -0800 Perform range checking on app supplied texture base level It is possible for applications to specify any texture base level, including trivially invalid values (i.e., 4700). When an app specifies an invalide base level, we should gracefully disable the texture instead of accessing memory outside the gl_texture_object. This fixes an occasional segfault in one of our conformance tests. (cherry picked from commit 1126aa86bf9ca223218695eec1f41c6523068961) URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=75d337f9701fb25004e33aad3d2fad2554cfa2bd Author: Eric Anholt e...@anholt.net Date: Mon Dec 15 15:10:18 2008 -0800 intel: stub out CompressedTexSubImage2D instead of segfaulting. (cherry picked from commit dc58da3e063d2a4018eea9149b43a3656a93a7ca) URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2726e80e9dafcde210e0e72e210b5b42eceb5a51 Author: Eric Anholt e...@anholt.net Date: Mon Dec 15 13:25:20 2008 -0800 i965: Update state before checking for fallbacks in brw_try_draw_prims. This got flipped around in 7855b2aef6bd9e9c2d73260b5cd166159b2525c6. Bug #18907. Thanks to idr for pointing me at a nicer testcase than blender. (cherry picked from commit 095c3a5cb16dae5c1e4cf85bffd3cb2465ab9e28) URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e82e5650751689a67fef7509e53d6496067ec8e Author: Pierre Willenbrock pie...@pirsoft.de Date: Fri Dec 12 21:18:23 2008 +0100 intel: Don't steal renderbuffer from caller in intel_miptree_create_for_region Fixes double-frees of some regions, once from the renderbuffer code and once from the miptree itself. Bug #19062 (cherry picked from commit e72a44215312ae1f3c812ba28e47b4aec3589de9) URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c9349496c6d067a35492c36d3f60d49302f64535 Author: Ian Romanick ian.d.roman...@intel.com Date: Sun Dec 14 18:40:39 2008 -0800 GLX: Include glapi.h before glapitable.h A previous commit (2dbc515a669be123a019aeb4aa5aae6b1679f6a9) change some of the interdependencies between these two header files. Now glapi.h must be included before glapitable.h. (cherry picked from commit 63cca2ba10ce7dcc8481cfa4be3872dfc269dded) URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a94bf86e17b1bd99502dc9fe47db4d701cdc179d Author: Ian Romanick ian.d.roman...@intel.com Date: Fri Dec 12 12:59:59 2008 -0800 GLX: Change resulting from previous commit Commit db61cbfa2aa241da49589331d8b6875d9a77d826 made modifications to the protocol generator data and scripts. This commit represents the changes to the generated files resulting from the previous changes. This is the client-side part of the fix for bugzilla #11003. (cherry picked from commit 2dd0c16f2118a39484615b80ca33620d3276523f) URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5ecc77e4d1d4b8a93c09a1051ecf9d1e50c50ed Author: Neil Roberts n...@linux.intel.com Date: Tue Dec 2 15:03:01 2008 + Return 0 as the request size when the pixels parameter is NULL img_null_flag was being ignored when calculating the size of a request so a BadLength error gets thrown for glTexImage3D when the pixels parameter is NULL. See bug #11003 (cherry picked from commit 1709ab01ef24279c782e420568e9257b4b92b224) URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2eb5dc9fb2d748b144435849ab4955282f68dfb7 Author: Ian Romanick ian.d.roman...@intel.com Date: Tue Dec 9 14:43:09 2008 -0800 GLX: Fix protocol for glTexSubImage#D The TexSubImage commands do not have the NULL image flag that was introduced with glTexImage3D. However, there is a CARD32 pad element where that flag would be. Removing the img_null_flag causes the flag to be removed from the protocol. This changes the protocol and breaks everything. In order to prevent needing to hand-code all of the TexSubImage functions, a new attribute was added to the param element. This new attribute, called padding, is a boolean flag that selects whether or not the parameter is a real parameter (default / false) or is protocol padding (true) that does not appear in the function's parameter list. This change resulted in a number of changes to other Python scripts. In almost all cases parameters with the is_padding flag set should not be emitted. This patch only changes the the XML, the DTD, and the generator scripts. It does NOT include the resulting changes to the generated code. Generated code in the X server is also changed by the script / XML changes in this patch. Signed-off-by: Ian Romanick ian.d.roman...@intel.com (cherry picked
Mesa (master): intel: check for null texture. (fix #13902)
Module: Mesa Branch: master Commit: 8b69c42b356d51c3a37bc0af41738b016c2adc5b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b69c42b356d51c3a37bc0af41738b016c2adc5b Author: Xiang, Haihao haihao.xi...@intel.com Date: Fri Dec 12 10:02:05 2008 +0800 intel: check for null texture. (fix #13902) --- src/mesa/drivers/dri/intel/intel_mipmap_tree.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index b96ba72..c677ddd 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -111,9 +111,9 @@ intel_miptree_create(struct intel_context *intel, first_level, last_level, width0, height0, depth0, cpp, compress_byte); /* -* pitch == 0 indicates the null texture +* pitch == 0 || height == 0 indicates the null texture */ - if (!mt || !mt-pitch) + if (!mt || !mt-pitch || !mt-total_height) return NULL; mt-region = intel_region_alloc(intel, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i915: fallback for cube map texture.
Module: Mesa Branch: master Commit: c8b505d8260cccf289c947c629471df8f5c81c0d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c8b505d8260cccf289c947c629471df8f5c81c0d Author: Xiang, Haihao [EMAIL PROTECTED] Date: Thu Dec 11 14:03:00 2008 +0800 i915: fallback for cube map texture. The i915 (and related graphics cores) only support TEXCOORDMODE_CLAMP and TEXCOORDMODE_CUBE when using cube map texture coordinates, so fall back to software rendering for other modes to avoid potential gpu hang issue. This fixes scorched3d issue on 945GM(see bug 14539). --- src/mesa/drivers/dri/i915/i915_texstate.c |7 +++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index d1b0dcd..d53e2cb 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -295,6 +295,13 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) wt == GL_CLAMP_TO_BORDER || wr == GL_CLAMP_TO_BORDER)) return GL_FALSE; + /* Only support TEXCOORDMODE_CLAMP_EDGE and TEXCOORDMODE_CUBE (not + * used) when using cube map texture coordinates + */ + if (tObj-Target == GL_TEXTURE_CUBE_MAP_ARB + (((ws != GL_CLAMP) (ws != GL_CLAMP_TO_EDGE)) || + ((wr != GL_CLAMP) (wr != GL_CLAMP_TO_EDGE + return GL_FALSE; state[I915_TEXREG_SS3] = ss3; /* SS3_NORMALIZED_COORDS */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa: fix shadow sampling unit issue.
Module: Mesa
Branch: master
Commit: b6bb5e09e0ad1f61f96c65bbc870bd493df12f1a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b6bb5e09e0ad1f61f96c65bbc870bd493df12f1a
Author: Xiang, Haihao [EMAIL PROTECTED]
Date: Thu Nov 20 16:54:16 2008 +0800
mesa: fix shadow sampling unit issue.
texture comparison logic is bypassed if the currently bound texture is not
a depth/depth_stencil texture.
---
src/mesa/main/texenvprogram.c |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/src/mesa/main/texenvprogram.c b/src/mesa/main/texenvprogram.c
index dcd7f90..ba7ce4a 100644
--- a/src/mesa/main/texenvprogram.c
+++ b/src/mesa/main/texenvprogram.c
@@ -213,16 +213,21 @@ static void make_state_key( GLcontext *ctx, struct
state_key *key )
for (i=0;iMAX_TEXTURE_UNITS;i++) {
const struct gl_texture_unit *texUnit = ctx-Texture.Unit[i];
+ GLenum format;
if (!texUnit-_ReallyEnabled || !texUnit-Enabled)
continue;
+ format =
texUnit-_Current-Image[0][texUnit-_Current-BaseLevel]-_BaseFormat;
+
key-unit[i].enabled = 1;
key-enabled_units |= (1i);
key-unit[i].source_index =
translate_tex_src_bit(texUnit-_ReallyEnabled);
- key-unit[i].shadow = texUnit-_Current-CompareMode ==
GL_COMPARE_R_TO_TEXTURE;
+ key-unit[i].shadow = ((texUnit-_Current-CompareMode ==
GL_COMPARE_R_TO_TEXTURE)
+ ((format == GL_DEPTH_COMPONENT) ||
+ (format == GL_DEPTH_STENCIL_EXT)));
key-unit[i].NumArgsRGB = texUnit-_CurrentCombine-_NumArgsRGB;
key-unit[i].NumArgsA = texUnit-_CurrentCombine-_NumArgsA;
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Mesa (master): mesa: clamp luminance if needed.
Module: Mesa
Branch: master
Commit: 2f9ceb158afffe5ea390b909261988267e663e36
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f9ceb158afffe5ea390b909261988267e663e36
Author: Xiang, Haihao [EMAIL PROTECTED]
Date: Wed Nov 19 11:22:35 2008 +0800
mesa: clamp luminance if needed.
This fixes glReadPixels(GL_LUMINANCE, GL_FLOAT)/glGetTexImage(GL_LUMINANCE,
GL_FLOAT) issue
on fixed-point color buffers.
---
src/mesa/main/image.c|2 +-
src/mesa/main/texstore.c | 10 +-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/image.c b/src/mesa/main/image.c
index 1a6e864..4551b4a 100644
--- a/src/mesa/main/image.c
+++ b/src/mesa/main/image.c
@@ -1689,7 +1689,7 @@ _mesa_pack_rgba_span_float(GLcontext *ctx, GLuint n,
GLfloat rgba[][4],
if (dstFormat == GL_LUMINANCE || dstFormat == GL_LUMINANCE_ALPHA) {
/* compute luminance values */
- if (dstType != GL_FLOAT || ctx-Color.ClampReadColor == GL_TRUE) {
+ if (transferOps IMAGE_CLAMP_BIT) {
for (i = 0; i n; i++) {
GLfloat sum = rgba[i][RCOMP] + rgba[i][GCOMP] + rgba[i][BCOMP];
luminance[i] = CLAMP(sum, 0.0F, 1.0F);
diff --git a/src/mesa/main/texstore.c b/src/mesa/main/texstore.c
index abeed3b..4b2b129 100644
--- a/src/mesa/main/texstore.c
+++ b/src/mesa/main/texstore.c
@@ -3719,6 +3719,14 @@ _mesa_get_teximage(GLcontext *ctx, GLenum target, GLint
level,
/* general case: convert row to RGBA format */
GLfloat rgba[MAX_WIDTH][4];
GLint col;
+ GLbitfield transferOps = 0x0;
+
+ if (type == GL_FLOAT
+ ((ctx-Color.ClampReadColor == GL_TRUE) ||
+(ctx-Color.ClampReadColor == GL_FIXED_ONLY_ARB
+ texImage-TexFormat-DataType != GL_FLOAT)))
+ transferOps |= IMAGE_CLAMP_BIT;
+
for (col = 0; col width; col++) {
(*texImage-FetchTexelf)(texImage, col, row, img, rgba[col]);
if (texImage-TexFormat-BaseFormat == GL_ALPHA) {
@@ -3743,7 +3751,7 @@ _mesa_get_teximage(GLcontext *ctx, GLenum target, GLint
level,
}
_mesa_pack_rgba_span_float(ctx, width, (GLfloat (*)[4]) rgba,
format, type, dest,
- ctx-Pack, 0x0 /*image xfer ops*/);
+ ctx-Pack, transferOps /*image xfer
ops*/);
} /* format */
} /* row */
} /* img */
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Mesa (master): intel: reset cliprect_mode to IGNORE_CLIPRECTS.
Module: Mesa
Branch: master
Commit: 09623fe551771031ed02ba7542c94bdbdd83ecec
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=09623fe551771031ed02ba7542c94bdbdd83ecec
Author: Xiang, Haihao [EMAIL PROTECTED]
Date: Tue Nov 11 13:42:13 2008 +0800
intel: reset cliprect_mode to IGNORE_CLIPRECTS.
This ensures all batchbuffers have a same cliprect mode after calling
_intel_batchbuffer_flush even if there aren't invalid commands in the
current batch buffer. (fix bug#18362).
---
src/mesa/drivers/dri/intel/intel_batchbuffer.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index c9b88b0..9d99372 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -197,8 +197,10 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch,
const char *file,
GLuint used = batch-ptr - batch-map;
GLboolean was_locked = intel-locked;
- if (used == 0)
+ if (used == 0) {
+ batch-cliprect_mode = IGNORE_CLIPRECTS;
return;
+ }
if (INTEL_DEBUG DEBUG_BATCH)
fprintf(stderr, %s:%d: Batchbuffer flush with %db used\n, file, line,
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Mesa (master): mesa: use _bfc0 instead of _col0 when building back face lighting.
Module: Mesa
Branch: master
Commit: 4550b0562d5b59890fccb0e7eb0dbef967d1ccf9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4550b0562d5b59890fccb0e7eb0dbef967d1ccf9
Author: Xiang, Haihao [EMAIL PROTECTED]
Date: Fri Nov 7 14:58:04 2008 +0800
mesa: use _bfc0 instead of _col0 when building back face lighting.
---
src/mesa/main/ffvertex_prog.c |5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/mesa/main/ffvertex_prog.c b/src/mesa/main/ffvertex_prog.c
index 308b4ef..5155c01 100644
--- a/src/mesa/main/ffvertex_prog.c
+++ b/src/mesa/main/ffvertex_prog.c
@@ -1296,14 +1296,13 @@ static void build_lighting( struct tnl_program *p )
}
else if (!p-state-material_shininess_is_zero) {
emit_op1(p, OPCODE_LIT, lit, 0, dots);
- emit_op2(p, OPCODE_ADD, _col0, 0, ambient, _col0);
+ emit_op2(p, OPCODE_ADD, _bfc0, 0, ambient, _bfc0);
}
else {
emit_degenerate_lit(p, lit, dots);
- emit_op2(p, OPCODE_ADD, _col0, 0, ambient, _col0);
+ emit_op2(p, OPCODE_ADD, _bfc0, 0, ambient, _bfc0);
}
- emit_op2(p, OPCODE_ADD, _bfc0, 0, ambient, _bfc0);
emit_op3(p, OPCODE_MAD, res0, mask0, swizzle1(lit,Y), diffuse,
_bfc0);
emit_op3(p, OPCODE_MAD, res1, mask1, swizzle1(lit,Z), specular,
_bfc1);
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Mesa (master): intel: GL_FALSE on a BO if it won' t be modified when mapping this BO. (thanks Eric).
Module: Mesa Branch: master Commit: 2a877411dbe35abdd8c15fb4821d9232619d89cc URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a877411dbe35abdd8c15fb4821d9232619d89cc Author: Xiang, Haihao [EMAIL PROTECTED] Date: Sun Oct 26 06:31:33 2008 +0800 intel: GL_FALSE on a BO if it won't be modified when mapping this BO. (thanks Eric). --- src/mesa/drivers/dri/intel/intel_blit.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index 081d1dd..3c1f7f6 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -299,7 +299,7 @@ intelEmitCopyBlit(struct intel_context *intel, } dri_bo_map(dst_buffer, GL_TRUE); - dri_bo_map(src_buffer, GL_TRUE); + dri_bo_map(src_buffer, GL_FALSE); _mesa_copy_rect((GLubyte *)dst_buffer-virtual + dst_offset, cpp, dst_pitch, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (intel-2008-q3): intel: GL_FALSE on a BO if it won' t be modified when mapping this BO. (thanks Eric).
Module: Mesa Branch: intel-2008-q3 Commit: 8f8892525a560b0e68780d58a1e127b304a31e8b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f8892525a560b0e68780d58a1e127b304a31e8b Author: Xiang, Haihao [EMAIL PROTECTED] Date: Sun Oct 26 06:31:33 2008 +0800 intel: GL_FALSE on a BO if it won't be modified when mapping this BO. (thanks Eric). (cherry picked from commit 22c9851b94132bc626320dc1131bf52f68e8bb25) --- src/mesa/drivers/dri/intel/intel_blit.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index 8f7ed23..e29c85b 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -299,7 +299,7 @@ intelEmitCopyBlit(struct intel_context *intel, } dri_bo_map(dst_buffer, GL_TRUE); - dri_bo_map(src_buffer, GL_TRUE); + dri_bo_map(src_buffer, GL_FALSE); _mesa_copy_rect((GLubyte *)dst_buffer-virtual + dst_offset, cpp, dst_pitch, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: don' t emit state when dri_bufmgr_check_aperture_space fails.
Module: Mesa
Branch: master
Commit: ec8076264ea2390d4cb749be5c88bbf2bf5d4847
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec8076264ea2390d4cb749be5c88bbf2bf5d4847
Author: Xiang, Haihao [EMAIL PROTECTED]
Date: Fri Oct 24 16:05:48 2008 +0800
i965: don't emit state when dri_bufmgr_check_aperture_space fails.
This ensures there is an unfilled batchbuffer used for emitting states again.
Partial fix for #17964.
---
src/mesa/drivers/dri/i965/brw_curbe.c |4 +++-
src/mesa/drivers/dri/i965/brw_misc_state.c | 12 +---
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c
b/src/mesa/drivers/dri/i965/brw_curbe.c
index 7cddd3a..6ffa221 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -333,8 +333,10 @@ static void emit_constant_buffer(struct brw_context *brw)
brw-curbe.curbe_bo,
};
- if (dri_bufmgr_check_aperture_space(aper_array, ARRAY_SIZE(aper_array)))
+ if (dri_bufmgr_check_aperture_space(aper_array, ARRAY_SIZE(aper_array))) {
intel_batchbuffer_flush(intel-batch);
+ return;
+ }
BEGIN_BATCH(2, IGNORE_CLIPRECTS);
if (sz == 0) {
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 487c638..afa8694 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -86,8 +86,10 @@ static void upload_binding_table_pointers(struct brw_context
*brw)
brw-wm.bind_bo,
};
- if (dri_bufmgr_check_aperture_space(aper_array, ARRAY_SIZE(aper_array)))
+ if (dri_bufmgr_check_aperture_space(aper_array, ARRAY_SIZE(aper_array))) {
intel_batchbuffer_flush(intel-batch);
+ return;
+ }
BEGIN_BATCH(6, IGNORE_CLIPRECTS);
OUT_BATCH(CMD_BINDING_TABLE_PTRS 16 | (6 - 2));
@@ -152,8 +154,10 @@ static void upload_psp_urb_cbs(struct brw_context *brw )
brw-cc.state_bo,
};
- if (dri_bufmgr_check_aperture_space(aper_array, ARRAY_SIZE(aper_array)))
+ if (dri_bufmgr_check_aperture_space(aper_array, ARRAY_SIZE(aper_array))) {
intel_batchbuffer_flush(intel-batch);
+ return;
+ }
upload_pipelined_state_pointers(brw);
brw_upload_urb_fence(brw);
@@ -216,8 +220,10 @@ static void emit_depthbuffer(struct brw_context *brw)
return;
}
- if (dri_bufmgr_check_aperture_space(aper_array, ARRAY_SIZE(aper_array)))
+ if (dri_bufmgr_check_aperture_space(aper_array, ARRAY_SIZE(aper_array)))
{
intel_batchbuffer_flush(intel-batch);
+return;
+ }
BEGIN_BATCH(len, IGNORE_CLIPRECTS);
OUT_BATCH(CMD_DEPTH_BUFFER 16 | (len - 2));
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Mesa (intel-2008-q3): intel: fallback for intelEmitCopyBlit.
Module: Mesa
Branch: intel-2008-q3
Commit: ca658efbe44784e415289cae6e897bfa8b370f88
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca658efbe44784e415289cae6e897bfa8b370f88
Author: Xiang, Haihao [EMAIL PROTECTED]
Date: Fri Oct 24 15:55:32 2008 +0800
intel: fallback for intelEmitCopyBlit.
Use _mesa_copy_rect instead of BLT operation if dri_bufmgr_check_aperture_space
still fails after flushing batchbuffer. Partial fix for #17964.
(cherry picked from commit f657c8191128c500c2aa7204009154a1182e2abd)
---
src/mesa/drivers/dri/intel/intel_blit.c | 49 --
1 files changed, 39 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c
b/src/mesa/drivers/dri/intel/intel_blit.c
index 653f485..8f7ed23 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -272,24 +272,53 @@ intelEmitCopyBlit(struct intel_context *intel,
GLshort w, GLshort h,
GLenum logic_op)
{
- GLuint CMD, BR13;
+ GLuint CMD, BR13, pass = 0;
int dst_y2 = dst_y + h;
int dst_x2 = dst_x + w;
dri_bo *aper_array[3];
BATCH_LOCALS;
/* do space/cliprects check before going any further */
- intel_batchbuffer_require_space(intel-batch, 8 * 4, NO_LOOP_CLIPRECTS);
- again:
- aper_array[0] = intel-batch-buf;
- aper_array[1] = dst_buffer;
- aper_array[2] = src_buffer;
-
- if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
- intel_batchbuffer_flush(intel-batch);
- goto again;
+ do {
+ aper_array[0] = intel-batch-buf;
+ aper_array[1] = dst_buffer;
+ aper_array[2] = src_buffer;
+
+ if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
+ intel_batchbuffer_flush(intel-batch);
+ pass++;
+ } else
+ break;
+ } while (pass 2);
+
+ if (pass = 2) {
+ GLboolean locked = GL_FALSE;
+ if (!intel-locked) {
+ LOCK_HARDWARE(intel);
+ locked = GL_TRUE;
+ }
+
+ dri_bo_map(dst_buffer, GL_TRUE);
+ dri_bo_map(src_buffer, GL_TRUE);
+ _mesa_copy_rect((GLubyte *)dst_buffer-virtual + dst_offset,
+ cpp,
+ dst_pitch,
+ dst_x, dst_y,
+ w, h,
+ (GLubyte *)src_buffer-virtual + src_offset,
+ src_pitch,
+ src_x, src_y);
+
+ dri_bo_unmap(src_buffer);
+ dri_bo_unmap(dst_buffer);
+
+ if (locked)
+ UNLOCK_HARDWARE(intel);
+
+ return;
}
+ intel_batchbuffer_require_space(intel-batch, 8 * 4, NO_LOOP_CLIPRECTS);
DBG(%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n,
__FUNCTION__,
src_buffer, src_pitch, src_offset, src_x, src_y,
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Mesa (master): i915: fix carsh in i830_emit_state. (bug #17766)
Module: Mesa
Branch: master
Commit: b4bf9acc32ac8693b1fdf80f351523a468ba6bd1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b4bf9acc32ac8693b1fdf80f351523a468ba6bd1
Author: Xiang, Haihao [EMAIL PROTECTED]
Date: Tue Oct 21 10:30:39 2008 +0800
i915: fix carsh in i830_emit_state. (bug #17766)
---
src/mesa/drivers/dri/i915/i830_vtbl.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c
b/src/mesa/drivers/dri/i915/i830_vtbl.c
index 773a8b4..3c9851e 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -449,7 +449,8 @@ i830_emit_state(struct intel_context *intel)
aper_array[aper_count++] = intel-batch-buf;
if (dirty I830_UPLOAD_BUFFERS) {
aper_array[aper_count++] = state-draw_region-buffer;
- aper_array[aper_count++] = state-depth_region-buffer;
+ if (state-depth_region)
+ aper_array[aper_count++] = state-depth_region-buffer;
}
for (i = 0; i I830_TEX_UNITS; i++)
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Mesa (mesa_7_2_branch): i915: fix carsh in i830_emit_state. (bug #17766)
Module: Mesa
Branch: mesa_7_2_branch
Commit: 48c29b60a899877c76d643b9cd06d5277cd97b9c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=48c29b60a899877c76d643b9cd06d5277cd97b9c
Author: Xiang, Haihao [EMAIL PROTECTED]
Date: Tue Oct 21 10:30:39 2008 +0800
i915: fix carsh in i830_emit_state. (bug #17766)
---
src/mesa/drivers/dri/i915/i830_vtbl.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c
b/src/mesa/drivers/dri/i915/i830_vtbl.c
index c5a85fe..38f35dd 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -444,7 +444,8 @@ i830_emit_state(struct intel_context *intel)
ret = 0;
if (dirty I830_UPLOAD_BUFFERS) {
ret |= dri_bufmgr_check_aperture_space(state-draw_region-buffer);
- ret |= dri_bufmgr_check_aperture_space(state-depth_region-buffer);
+ if (state-depth_region)
+ ret |= dri_bufmgr_check_aperture_space(state-depth_region-buffer);
}
for (i = 0; i I830_TEX_UNITS; i++)
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Mesa (master): i915: Texture instructions use r/t/oC/ oD register as texture coordinate.
Module: Mesa
Branch: master
Commit: c238098bbcfb644ea01b33d3274b949d84822512
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c238098bbcfb644ea01b33d3274b949d84822512
Author: Xiang, Haihao [EMAIL PROTECTED]
Date: Mon Oct 13 13:04:04 2008 +0800
i915: Texture instructions use r/t/oC/oD register as texture coordinate.
Fix http://bugs.freedesktop.org/show_bug.cgi?id=16287.
---
src/mesa/drivers/dri/i915/i915_program.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i915_program.c
b/src/mesa/drivers/dri/i915/i915_program.c
index 350da5e..e87700f 100644
--- a/src/mesa/drivers/dri/i915/i915_program.c
+++ b/src/mesa/drivers/dri/i915/i915_program.c
@@ -245,6 +245,19 @@ GLuint i915_emit_texld( struct i915_fragment_program *p,
*/
assert(GET_UREG_TYPE(coord) != REG_TYPE_U);
+ if ((GET_UREG_TYPE(coord) != REG_TYPE_R)
+ (GET_UREG_TYPE(coord) != REG_TYPE_OC)
+ (GET_UREG_TYPE(coord) != REG_TYPE_OD)
+ (GET_UREG_TYPE(coord) != REG_TYPE_T)) {
+ GLuint tmpCoord = get_free_rreg(p, live_regs);
+
+ if (tmpCoord == UREG_BAD)
+ return 0;
+
+ i915_emit_arith(p, A0_MOV, tmpCoord, A0_DEST_CHANNEL_ALL, 0, coord,
0, 0);
+ coord = tmpCoord;
+ }
+
/* Output register being oC or oD defines a phase boundary */
if (GET_UREG_TYPE(dest) == REG_TYPE_OC ||
GET_UREG_TYPE(dest) == REG_TYPE_OD)
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Mesa (intel-2008-q3): i965: Fix a potential assertion failure.
Module: Mesa
Branch: intel-2008-q3
Commit: c281d3d5caedf75eaa3c877f94656f982aad868d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c281d3d5caedf75eaa3c877f94656f982aad868d
Author: Xiang, Haihao [EMAIL PROTECTED]
Date: Tue Oct 7 17:27:33 2008 +0800
i965: Fix a potential assertion failure.
(cherry picked from commit d01f9fa778cb0d230c697badaea078f6f37da743)
---
src/mesa/drivers/dri/i965/brw_draw_upload.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index f148b10..89b7c2a 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -365,8 +365,10 @@ static void brw_prepare_vertices(struct brw_context *brw)
if (i == 0) {
/* Position array not properly enabled:
*/
- if (input-glarray-StrideB == 0)
- return;
+if (input-glarray-StrideB == 0) {
+ intel-Fallback = 1;
+ return;
+}
interleave = input-glarray-StrideB;
ptr = input-glarray-Ptr;
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Mesa (master): i965: Fix a potential assertion failure.
Module: Mesa
Branch: master
Commit: 94d3a30df759bb7c2724fdcee9e89a350d3a4d8b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=94d3a30df759bb7c2724fdcee9e89a350d3a4d8b
Author: Xiang, Haihao [EMAIL PROTECTED]
Date: Wed Oct 8 09:30:12 2008 +0800
i965: Fix a potential assertion failure.
---
src/mesa/drivers/dri/i965/brw_draw_upload.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 303eaac..cc3d939 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -365,8 +365,10 @@ static void brw_prepare_vertices(struct brw_context *brw)
if (i == 0) {
/* Position array not properly enabled:
*/
- if (input-glarray-StrideB == 0)
- return;
+if (input-glarray-StrideB == 0) {
+ intel-Fallback = 1;
+ return;
+}
interleave = input-glarray-StrideB;
ptr = input-glarray-Ptr;
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mesa: Changes to 'mesa_7_0_branch'
The branch, mesa_7_0_branch has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=mesa_7_0_branch Summary of changes: src/mesa/drivers/dri/i965/brw_defines.h |3 ++- src/mesa/drivers/dri/i965/intel_context.h |1 + 2 files changed, 3 insertions(+), 1 deletions(-) via 052eef31b612f2ac1f7c812fc06b688e83a10fbc (commit) from 78e06ee5680e9d73598031d96dd1784ea600a290 (commit) - Commits --- commit 052eef31b612f2ac1f7c812fc06b688e83a10fbc Author: Xiang, Haihao [EMAIL PROTECTED] Date: Fri Sep 12 09:39:41 2008 +0800 i965: Add support for G41 chipset which is another 4 series chipset. - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'master'
The branch, master has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=master Summary of changes: src/mesa/drivers/dri/intel/intel_context.c | 16 1 files changed, 8 insertions(+), 8 deletions(-) via 3bb2a24921af0ec419afc928ee5b279982aa01ea (commit) from 0fd1a8c4a1201f3508cb6a98dc1c66ab9ebd919f (commit) - Commits --- commit 3bb2a24921af0ec419afc928ee5b279982aa01ea Author: Xiang, Haihao [EMAIL PROTECTED] Date: Wed Sep 3 14:47:36 2008 +0800 intel: Fix a crash if dri2 is disabled. - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'master'
The branch, master has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=master Summary of changes: src/mesa/drivers/dri/i965/brw_eu_emit.c | 13 + src/mesa/drivers/dri/i965/brw_wm_glsl.c |4 ++-- 2 files changed, 11 insertions(+), 6 deletions(-) via 7a2ab6d05573508389b38f8f1fa261ba56062865 (commit) via 6073b49c7915147c28e9887039a51b8e4e2e62c5 (commit) via fd81433a4efbe658db742b36c0c30c17c6effea6 (commit) from 6138ee9de0330b9a2bf300bc0d52b471191dd1ed (commit) - Commits --- commit 7a2ab6d05573508389b38f8f1fa261ba56062865 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Fri Aug 29 09:49:16 2008 +0800 i965: force thread switch after IF/ELSE/ENDIF. partial fix for #16882. A thread switch is implicitly invoked after the issuance of an IF/ELSE/ENDIF instruction if necessary. Unfortunately it seems sometimes a forced thread switch is needed. commit 6073b49c7915147c28e9887039a51b8e4e2e62c5 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Fri Aug 29 09:27:28 2008 +0800 i965: mask control for BREAK/CONT/DO/WHILE. partial fix fox #16882 commit fd81433a4efbe658db742b36c0c30c17c6effea6 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Fri Aug 29 09:22:41 2008 +0800 i965: Push/pop instruction state. partial fix for #16882 - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'mesa_7_2_branch'
The branch, mesa_7_2_branch has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=mesa_7_2_branch Summary of changes: src/mesa/drivers/dri/i965/brw_eu_emit.c | 13 + src/mesa/drivers/dri/i965/brw_wm_glsl.c |4 ++-- 2 files changed, 11 insertions(+), 6 deletions(-) via e4535e4d5e37965f5a19b2166d3933ee9d72c27b (commit) via a008813890a719ed351932c698181e9180c8cf4a (commit) via da50dc7bb3a00181d4a362f4cfe93a759128d55f (commit) from 7f628d9cbc58fed17ef4b9288c045a138050b6eb (commit) - Commits --- commit e4535e4d5e37965f5a19b2166d3933ee9d72c27b Author: Xiang, Haihao [EMAIL PROTECTED] Date: Fri Aug 29 09:49:16 2008 +0800 i965: force thread switch after IF/ELSE/ENDIF. partial fix for #16882. A thread switch is implicitly invoked after the issuance of an IF/ELSE/ENDIF instruction if necessary. Unfortunately it seems sometimes a forced thread switch is needed. commit a008813890a719ed351932c698181e9180c8cf4a Author: Xiang, Haihao [EMAIL PROTECTED] Date: Fri Aug 29 09:27:28 2008 +0800 i965: mask control for BREAK/CONT/DO/WHILE. partial fix fox #16882 commit da50dc7bb3a00181d4a362f4cfe93a759128d55f Author: Xiang, Haihao [EMAIL PROTECTED] Date: Fri Aug 29 09:22:41 2008 +0800 i965: Push/pop instruction state. partial fix for #16882 - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'master'
The branch, master has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=master Summary of changes: src/mesa/drivers/dri/i965/brw_wm_fp.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) via c20a1736566d301f38cc1271284b1fde9adb2741 (commit) from 8e8019b49ab137403ba92aef3e286f4e27049ad5 (commit) - Commits --- commit c20a1736566d301f38cc1271284b1fde9adb2741 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Wed Aug 6 14:15:31 2008 +0800 i965: update TexSrcUnit for OPCODE_TXB - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'master'
The branch, master has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=master Summary of changes: src/mesa/drivers/dri/i965/brw_wm_fp.c | 11 ++- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 14 +- 2 files changed, 15 insertions(+), 10 deletions(-) via a3024caff1c790cf9f24476926aa62198f1e7b53 (commit) from 62fb5f7b9ab70017d5de6ab3d0886bc4cbdbc57f (commit) - Commits --- commit a3024caff1c790cf9f24476926aa62198f1e7b53 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Tue Aug 5 10:18:56 2008 +0800 i965: Use program-SamplerUnits[] to get the appropriate texture unit. inst-TexSrcUnit is used as an index into program-SamplerUnits[] since the commit ade508312c701ce89d3c2cd717994dbbabb4f207, and program-SamplerUnits is a sampler-to-texture-unit mapping. - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'master'
The branch, master has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=master Summary of changes: src/mesa/drivers/dri/common/depthtmp.h|9 + src/mesa/drivers/dri/gamma/gamma_span.c |6 ++ src/mesa/drivers/dri/i810/i810span.c |2 ++ src/mesa/drivers/dri/intel/intel_span.c |5 - src/mesa/drivers/dri/mach64/mach64_span.c |2 ++ src/mesa/drivers/dri/mga/mgaspan.c|6 ++ src/mesa/drivers/dri/r128/r128_span.c |3 +++ src/mesa/drivers/dri/r200/r200_span.c |2 ++ src/mesa/drivers/dri/r300/radeon_span.c |4 src/mesa/drivers/dri/radeon/radeon_span.c |4 src/mesa/drivers/dri/s3v/s3v_span.c |6 ++ src/mesa/drivers/dri/savage/savagespan.c |8 src/mesa/drivers/dri/sis/sis_span.c |6 ++ src/mesa/drivers/dri/unichrome/via_span.c |5 + src/mesa/drivers/glide/fxddspan.c |4 15 files changed, 67 insertions(+), 5 deletions(-) via 8e8019b49ab137403ba92aef3e286f4e27049ad5 (commit) from a3024caff1c790cf9f24476926aa62198f1e7b53 (commit) - Commits --- commit 8e8019b49ab137403ba92aef3e286f4e27049ad5 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Tue Aug 5 11:28:54 2008 +0800 dri: Fix write/read depth buffer issue under 16bpp mode. See bug #16646 - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'master'
The branch, master has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=master Summary of changes: src/mesa/drivers/dri/i965/brw_fallback.c|5 - src/mesa/drivers/dri/intel/intel_mipmap_tree.c |5 - src/mesa/drivers/dri/intel/intel_tex_image.c|5 - src/mesa/drivers/dri/intel/intel_tex_validate.c |5 - 4 files changed, 16 insertions(+), 4 deletions(-) via b4b7326717d3253656f9702fc04f06f8d210a6aa (commit) from 3bfedb7ed4a35cfcc7187bc22314833ef1d96ec9 (commit) - Commits --- commit b4b7326717d3253656f9702fc04f06f8d210a6aa Author: Xiang, Haihao [EMAIL PROTECTED] Date: Fri Jul 18 17:40:11 2008 +0800 intel: fix texture border issue. (bug #16697) - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'mesa_7_0_branch'
The branch, mesa_7_0_branch has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=mesa_7_0_branch Summary of changes: src/mesa/drivers/dri/i915/i915_texstate.c |5 - src/mesa/drivers/dri/i965/brw_fallback.c |7 +-- src/mesa/drivers/dri/i965/intel_tex_validate.c |5 - 3 files changed, 13 insertions(+), 4 deletions(-) via 97eb33529ae2f96220eec5238d8d0e9a07ce91d5 (commit) from 5ce5cc93d51bc784a54aa4f51298715fa2c8d5aa (commit) - Commits --- commit 97eb33529ae2f96220eec5238d8d0e9a07ce91d5 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Fri Jul 18 22:39:12 2008 +0800 intel: fix texture border issue (bug #16697) - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'master'
The branch, master has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=master Summary of changes: src/mesa/drivers/dri/i965/brw_clip_line.c |2 +- src/mesa/drivers/dri/i965/brw_clip_state.c |2 +- src/mesa/drivers/dri/i965/brw_clip_tri.c |2 +- src/mesa/drivers/dri/i965/brw_defines.h| 13 +++-- src/mesa/drivers/dri/i965/brw_eu_emit.c| 16 src/mesa/drivers/dri/i965/brw_misc_state.c |8 src/mesa/drivers/dri/i965/brw_structs.h|4 ++-- src/mesa/drivers/dri/i965/brw_vs_emit.c|2 +- src/mesa/drivers/dri/intel/intel_chipset.h | 10 +- src/mesa/drivers/dri/intel/intel_context.c |4 +++- 10 files changed, 33 insertions(+), 30 deletions(-) via 92c075eeb7c330ea420400d1c2bae57356b19f03 (commit) from a36bf890e8be3473f6a98f5ba4369e3acc0463ad (commit) - Commits --- commit 92c075eeb7c330ea420400d1c2bae57356b19f03 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Tue Jul 8 14:14:04 2008 +0800 i965: official name for GM45 chipset - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'mesa_7_0_branch'
The branch, mesa_7_0_branch has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=mesa_7_0_branch Summary of changes: src/mesa/drivers/dri/i965/brw_aub_playback.c |4 ++-- src/mesa/drivers/dri/i965/brw_clip_line.c|2 +- src/mesa/drivers/dri/i965/brw_clip_state.c |2 +- src/mesa/drivers/dri/i965/brw_clip_tri.c |2 +- src/mesa/drivers/dri/i965/brw_defines.h | 13 ++--- src/mesa/drivers/dri/i965/brw_eu_emit.c | 16 src/mesa/drivers/dri/i965/brw_misc_state.c |4 ++-- src/mesa/drivers/dri/i965/brw_structs.h |2 +- src/mesa/drivers/dri/i965/brw_vs_emit.c |2 +- src/mesa/drivers/dri/i965/intel_context.c|4 +++- src/mesa/drivers/dri/i965/intel_context.h|2 +- 11 files changed, 27 insertions(+), 26 deletions(-) via aa522e14eecdb571ee0826a44b78b36a23213be6 (commit) from 2c9e332bceb85435aa5e4ad4d43fc97c7272bf98 (commit) - Commits --- commit aa522e14eecdb571ee0826a44b78b36a23213be6 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Tue Jul 8 14:39:01 2008 +0800 i965: official name for GM45 chipset - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'master'
The branch, master has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=master Summary of changes: src/mesa/drivers/dri/i915/i915_texstate.c | 11 --- 1 files changed, 4 insertions(+), 7 deletions(-) via 75e4db18049f3284197c9a8deabd9dd74aa7920e (commit) from 2f1b5ffcda283cebc97bd440b5af44168a9c8b00 (commit) - Commits --- commit 75e4db18049f3284197c9a8deabd9dd74aa7920e Author: Xiang, Haihao [EMAIL PROTECTED] Date: Wed Jul 9 13:08:09 2008 +0800 i915: fall back to software rendering when shadow comparison is enabled for 1D texture. fix #12176 - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'master'
The branch, master has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=master Summary of changes: src/mesa/tnl_dd/t_dd_tritmp.h |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) via 0c1e96e6d38c0acfd3fe6b4116f2a67f5bf62136 (commit) from 530df581dd1a502041b44afee8023a09d5b7e59f (commit) - Commits --- commit 0c1e96e6d38c0acfd3fe6b4116f2a67f5bf62136 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Fri Jul 4 09:53:51 2008 +0800 mesa: fix polygon offset issue (bug #12061) - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'master'
The branch, master has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=master Summary of changes: src/mesa/drivers/dri/common/texmem.c|1 + src/mesa/drivers/dri/intel/intel_tex_validate.c |1 + 2 files changed, 2 insertions(+), 0 deletions(-) via bcc2a3d7e3c5f81bb5a45b8d628a133f3b5499a5 (commit) from 5cae1b747bf7013124c21f15c410635c16593656 (commit) - Commits --- commit bcc2a3d7e3c5f81bb5a45b8d628a133f3b5499a5 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Tue Jul 1 11:38:07 2008 +0800 dri: Take the base image size into account when computing first level of the mipmap. fix #16210 - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'mesa_7_0_branch'
The branch, mesa_7_0_branch has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=mesa_7_0_branch Summary of changes: src/mesa/drivers/dri/common/texmem.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) via 9fa552eb0fb91d092f8a7df0e131696feda54130 (commit) from 5f8ad807be54c433229121aa4417aede7a91f5d4 (commit) - Commits --- commit 9fa552eb0fb91d092f8a7df0e131696feda54130 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Tue Jul 1 11:42:28 2008 +0800 dri: Take the base image size into account when computing first level of the mipmap. fix #16421 - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'mesa_7_0_branch'
The branch, mesa_7_0_branch has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=mesa_7_0_branch Summary of changes: src/mesa/drivers/dri/i965/brw_clip_line.c |9 +++ src/mesa/drivers/dri/i965/brw_clip_state.c |2 +- src/mesa/drivers/dri/i965/brw_clip_tri.c | 108 ++- src/mesa/drivers/dri/i965/brw_clip_util.c | 14 +--- 4 files changed, 116 insertions(+), 17 deletions(-) via b6e165d6613a395d8f45a04901a08bd436eb52dd (commit) from afbb6459069d75b233a5f4dcddd6d427c16d2ca5 (commit) - Commits --- commit b6e165d6613a395d8f45a04901a08bd436eb52dd Author: Zou Nan hai [EMAIL PROTECTED] Date: Fri Aug 31 13:42:20 2007 +0800 optimize 965 clip 1. increase clip thread number to 2 2. do cliptest for -rhw Cherry-picked from commits b47c9f8c915ae4ca8c7fa5ee3b6b64f17c38b569, aa88d11e7d881f0dd4c02fcefceb4085bdb3cf8a. - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'master'
The branch, master has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=master Summary of changes: src/mesa/drivers/dri/intel/intel_chipset.h | 12 ++-- src/mesa/drivers/dri/intel/intel_context.c |7 +++ 2 files changed, 17 insertions(+), 2 deletions(-) via 3e8aadee8beffaabd4e0c60c289b98124e288dcd (commit) from 30640695400b9b27656893753ae6b62f2082ce9b (commit) - Commits --- commit 3e8aadee8beffaabd4e0c60c289b98124e288dcd Author: Xiang, Haihao [EMAIL PROTECTED] Date: Wed Jun 18 15:33:33 2008 +0800 i965: add support for Intel 4 series chipsets - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'mesa_7_0_branch'
The branch, mesa_7_0_branch has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=mesa_7_0_branch Summary of changes: src/mesa/drivers/dri/i965/brw_defines.h |6 +- src/mesa/drivers/dri/i965/intel_context.c |6 ++ src/mesa/drivers/dri/i965/intel_context.h |5 - 3 files changed, 15 insertions(+), 2 deletions(-) via 2ac4919d24ad931eadc538add0a3fa353aa3aa10 (commit) from 3ed89025f3df9e72afe0a77c847aab13b2ee861b (commit) - Commits --- commit 2ac4919d24ad931eadc538add0a3fa353aa3aa10 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Wed Jun 18 15:48:45 2008 +0800 i965: add support for Intel 4 series chipsets - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'mesa_7_0_branch'
The branch, mesa_7_0_branch has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=mesa_7_0_branch Summary of changes: src/mesa/drivers/dri/i915/intel_pixel.c |8 1 files changed, 4 insertions(+), 4 deletions(-) via 3ed89025f3df9e72afe0a77c847aab13b2ee861b (commit) via 5b42bbce70ea093ee9a0e8fa7a0d42ddc4143832 (commit) from d2e0a11aab98764300b9019483dc701117be3fea (commit) - Commits --- commit 3ed89025f3df9e72afe0a77c847aab13b2ee861b Author: Xiang, Haihao [EMAIL PROTECTED] Date: Wed Jun 18 13:46:55 2008 +0800 i915: The pitch passed to intelEmitCopyBlitLocked should be in pixels, not in bytes. Reported by Christopher Dissauer. commit 5b42bbce70ea093ee9a0e8fa7a0d42ddc4143832 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Wed Jun 18 13:38:53 2008 +0800 i915: fix data size in intelTryDrawPixels. Reported by Christopher Dissauer - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'mesa_7_0_branch'
The branch, mesa_7_0_branch has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=mesa_7_0_branch Summary of changes: src/mesa/drivers/dri/i965/intel_batchbuffer.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) via 82a0e82232d61a75fee39d50333016d78938450f (commit) from 03447de338158cca962880fd04d7d3ecf4bd9c5b (commit) - Commits --- commit 82a0e82232d61a75fee39d50333016d78938450f Author: Xiang, Haihao [EMAIL PROTECTED] Date: Fri Jun 13 13:48:17 2008 +0800 i965: fix intel_batchbuffer_space. (bug#14709) - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'mesa_7_0_branch'
The branch, mesa_7_0_branch has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=mesa_7_0_branch Summary of changes: src/mesa/shader/program.c |2 -- 1 files changed, 0 insertions(+), 2 deletions(-) via 03447de338158cca962880fd04d7d3ecf4bd9c5b (commit) from ee5f4a4caf894dd7d91a8146af589bb18751a7bb (commit) - Commits --- commit 03447de338158cca962880fd04d7d3ecf4bd9c5b Author: Brian [EMAIL PROTECTED] Date: Mon Oct 29 10:01:15 2007 -0600 disable ctx-Driver.NewProgram() call in _mesa_new_program() This was causing infinite recursive calls w/ software drivers. All vertex/fragment shaders should be allocated by calling ctx-Driver.NewProgram(), not by calling _mesa_new_program(). (Cherry picked from commit 40133487dbdd14456a8a4f6a5716f57a36eb1ea7, 351a83163a9536dc91014cc59bb406a10cd26df4). - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'master'
The branch, master has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=master Summary of changes: src/mesa/drivers/dri/i965/brw_wm_glsl.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) via a742bed99ae840d806198172005f6b25399ec573 (commit) from 72f87b69471649ff02e80a89f902b69980f3d025 (commit) - Commits --- commit a742bed99ae840d806198172005f6b25399ec573 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Tue Jun 10 16:31:36 2008 +0800 i965: apply commit 6c1a98e97affb2163e776551eb3a9e669ff99bbf to glsl - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'mesa_7_0_branch'
The branch, mesa_7_0_branch has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=mesa_7_0_branch Summary of changes: src/mesa/drivers/dri/i915/i915_context.h |6 +++ src/mesa/drivers/dri/i915/i915_fragprog.c | 56 +--- src/mesa/drivers/dri/i915/i915_program.c | 38 ++-- src/mesa/drivers/dri/i915/i915_program.h |1 + src/mesa/drivers/dri/i915/i915_texprog.c |2 +- src/mesa/drivers/dri/i915/intel_tex.c |2 +- 6 files changed, 86 insertions(+), 19 deletions(-) via c04f3933abd5dbacf8ac1c7f35ded0384b19da48 (commit) via 8f328c45e5d51b738c8747400aae4b694905a26d (commit) from 6f4c8b5b5047c6ff6273e3acc98c7ec504bb0e21 (commit) - Commits --- commit c04f3933abd5dbacf8ac1c7f35ded0384b19da48 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Wed Jun 11 11:36:01 2008 +0800 i915: fix fd.o #14966 commit 8f328c45e5d51b738c8747400aae4b694905a26d Author: Xiang, Haihao [EMAIL PROTECTED] Date: Mon Jan 7 14:08:36 2008 +0800 i915: Keith Whitwell's swizzling TEX patch. fix #8283 Cherry picked from commit 3369cd9a6f943365242d7832e69788d4aede9a8f - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'mesa_7_0_branch'
The branch, mesa_7_0_branch has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=mesa_7_0_branch Summary of changes: src/mesa/drivers/dri/i915/i915_fragprog.c|2 +- src/mesa/drivers/dri/i965/brw_clip_unfilled.c|4 +- src/mesa/drivers/dri/i965/brw_draw_upload.c | 25 +++ src/mesa/drivers/dri/i965/brw_eu_emit.c |2 +- src/mesa/drivers/dri/i965/brw_vs_tnl.c |8 +- src/mesa/drivers/dri/i965/brw_wm.c |2 +- src/mesa/drivers/dri/i965/brw_wm_fp.c|2 +- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 11 ++-- src/mesa/drivers/dri/i965/intel_pixel_bitmap.c | 29 +++-- src/mesa/main/depthstencil.c |2 +- src/mesa/x86/read_rgba_span_x86.S|4 ++- 11 files changed, 65 insertions(+), 26 deletions(-) via 6f851d88758c2157d25751b9e2b5309b221faea7 (commit) via 9b99bf89c40e5b819e7e8a090b5cf7ca83bf1944 (commit) via 7346fca083cc59a52b5168b539d848b10af8bd34 (commit) via 7facbb69c6b308719dad7121adb1caaef0ea7932 (commit) via f59267d650961ea536bf790cce905747202cca6d (commit) via 71cb014195d11d0cdee4817e52c475397d955d94 (commit) via 6c0f8db9c25f4d0e44e748b8a45a2b6a92764b39 (commit) via 49f1e2fc4c738f123d654b466fc7beac0cff5007 (commit) via 2d26e195353a7f45c094a719e8a7b8ef28e74d8e (commit) via 5b0c6cd49a8b73afe466beee3f33ba231b658ab2 (commit) via c3ee8e46ccd6a011fe38c005ad84da8e51c4e7dd (commit) via 46aac242612b8570ec7d309b2835c5d6cdafa4b0 (commit) via e1032ce7182ad01ee4053a99ef1a7358954c0495 (commit) from ce636f36f293a137dc7f129afec464bfbc95eb4e (commit) - Commits --- commit 6f851d88758c2157d25751b9e2b5309b221faea7 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Wed May 14 09:52:46 2008 +0800 _generic_read_RGBA_span_BGRA_REV_SSE2: It should adjust the source and target pointers after do the first 2 pixels. fix bug #15850 Cherry-picked from commit 4b7d301c94d33394550322768a9d2232087b2d64 commit 9b99bf89c40e5b819e7e8a090b5cf7ca83bf1944 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Fri Mar 28 17:32:45 2008 +0800 i965: depth offset on glPolygonMode(GL_LINE/GL_POINT) Cherry picked from 184cf464f4183a664fa0358fe118735e6fd98afe commit 7346fca083cc59a52b5168b539d848b10af8bd34 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Mon Jun 2 14:15:24 2008 +0800 965: use RGB565 to render a bitmap if Depth is 16 Cherry-picked from commit 5982d397990fd2ae4c729977cf8d22da5ef29987. commit 7facbb69c6b308719dad7121adb1caaef0ea7932 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Fri Feb 15 16:13:11 2008 +0800 i965: don't swizzle fogcoord if FogOption is FOG_NONE. fix #10788 issue on 965. Cherry picked from commit 83068115e2104b1880431ada96fa37e632149a86 commit f59267d650961ea536bf790cce905747202cca6d Author: Xiang, Haihao [EMAIL PROTECTED] Date: Mon Jun 2 14:06:14 2008 +0800 i915: set fogcoord to (f,0,0,1). fix #10788 issue on 915. Cherry picked from commit 7eef52e975e852207ee840c74cd822c8f8c90a01 commit 71cb014195d11d0cdee4817e52c475397d955d94 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Tue Dec 25 14:16:05 2007 +0800 mesa: fix a bad cast in put_values_z24. The values passed to put_values_z24 are GLuint, not GLubyte. fix #13543 Cherry picked from commit cf46aee14a9df86ce336823fd02da650e262f77e commit 6c0f8db9c25f4d0e44e748b8a45a2b6a92764b39 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Tue Nov 27 09:45:32 2007 +0800 i965: The jump instruction count is added to IP pre-increment, and should point to the first instruction after the do instruction of the do-while block of code Cherry picked from commit 46e03d584a18b89fef956fed3d52e15775846250 commit 49f1e2fc4c738f123d654b466fc7beac0cff5007 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Thu Sep 20 17:42:13 2007 +0800 i965: fix an error in brw_vs_tnl.c Update the tnl program if the state of TEXMAT is changed. commit 2d26e195353a7f45c094a719e8a7b8ef28e74d8e Author: Eric Anholt [EMAIL PROTECTED] Date: Tue Jan 8 16:20:28 2008 -0800 [965] Clarify a bit of index buffer upload code. Cherry picked from commit 5a49e84fcd858a1ad9c0ad839ccbe93504593cd0 commit 5b0c6cd49a8b73afe466beee3f33ba231b658ab2 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Fri Sep 14 11:10:23 2007 +0800 i965: align the address of the first element within the index buffer. (fix#11910) Cherry picked from ea07a0df9a2f689b8f5acaf92c40bbbd602cab3c commit c3ee8e46ccd6a011fe38c005ad84da8e51c4e7dd Author: Xiang, Haihao [EMAIL PROTECTED] Date: Mon Aug 13 17:16:27 2007 +0800 i965: fix projtex_mask projtex_mask is only an 8bit field, and wm.input_size_masks includes other attributes'
mesa: Changes to 'mesa_7_0_branch'
The branch, mesa_7_0_branch has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=mesa_7_0_branch Summary of changes: docs/relnotes-7.0.4.html |1 + src/mesa/drivers/dri/i965/brw_defines.h |2 + src/mesa/drivers/dri/i965/brw_sf.c| 15 - src/mesa/drivers/dri/i965/brw_sf.h|9 +++- src/mesa/drivers/dri/i965/brw_sf_emit.c | 98 + src/mesa/drivers/dri/i965/brw_sf_state.c |1 + src/mesa/drivers/dri/i965/intel_context.c |5 ++ 7 files changed, 127 insertions(+), 4 deletions(-) via e92a53cd926d456b8f0994ccb0237f06c67abccc (commit) via 2467af98b1dca09b7bff5d16a0a99d989294e131 (commit) from 6f851d88758c2157d25751b9e2b5309b221faea7 (commit) - Commits --- commit e92a53cd926d456b8f0994ccb0237f06c67abccc Author: Zou Nan hai [EMAIL PROTECTED] Date: Thu Feb 14 11:01:34 2008 +0800 [i965] flip point sprite Cherry picked from commit 1202c434d91c56bccc4c918f8284f0602ef4ca0b commit 2467af98b1dca09b7bff5d16a0a99d989294e131 Author: Zou Nan hai [EMAIL PROTECTED] Date: Mon Jul 30 10:18:11 2007 +0800 ARB sprite point support on i965 Cherry picked from commmit 60179434d15989b81e2d4757f34033009184a678, 505453a04e8ba5e394c34401bd9ec320ffce2423 with manual changes. - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'mesa_7_0_branch'
The branch, mesa_7_0_branch has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=mesa_7_0_branch Summary of changes: docs/relnotes-7.0.4.html |1 + src/mesa/drivers/dri/i965/brw_tex.c | 19 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |5 src/mesa/drivers/dri/i965/intel_context.c|1 + src/mesa/main/texcompress_s3tc.c | 26 ++ src/mesa/main/texformat.h|2 + 6 files changed, 54 insertions(+), 0 deletions(-) via 64a4a03c2ae23e8e799038c2cca919736ee92e6b (commit) from b878c3f518026749b5303c38b7299fb9b3d17845 (commit) - Commits --- commit 64a4a03c2ae23e8e799038c2cca919736ee92e6b Author: Zou Nan hai [EMAIL PROTECTED] Date: Thu Aug 2 14:26:12 2007 +0800 EXT_texture_sRGB support on i965 Cherry picked from commit 6bf81a5edfa287a396f30188b107ff1761039f3f, 246d1d2522858a1bcf525d64ad165f9af11a2b4d. - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'mesa_7_0_branch'
The branch, mesa_7_0_branch has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=mesa_7_0_branch Summary of changes: src/mesa/drivers/dri/i965/brw_wm_sampler_state.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) via feb1fa1e833b817374fb2e3f3224c64be9a680d8 (commit) from f32462343d25c37bb61181e04e9404bd4e61e528 (commit) - Commits --- commit feb1fa1e833b817374fb2e3f3224c64be9a680d8 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Wed Aug 15 13:28:00 2007 +0800 i965: use BRW_TEXCOORDMODE_CLAMP instead of BRW_TEXCOORDMODE_CLAMP_BORDER to implement GL_CLAMP Cherry picked from commit ab999608582534bb5187a786b2ea437167f2d8a4. fix #16005 - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'master'
The branch, master has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=master Summary of changes: src/mesa/drivers/dri/i965/brw_draw.c | 18 -- 1 files changed, 8 insertions(+), 10 deletions(-) via c6b36e5498cf6593daf001123cacec4ccaf305ca (commit) from e469d78d33feff45f16235871ca1a3d483cdc950 (commit) - Commits --- commit c6b36e5498cf6593daf001123cacec4ccaf305ca Author: Xiang, Haihao [EMAIL PROTECTED] Date: Tue May 20 13:28:42 2008 +0800 i965: Check fallback before accounting for index/vertex buffer size. fix #16028. - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'mesa_7_0_branch'
The branch, mesa_7_0_branch has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=mesa_7_0_branch Summary of changes: src/mesa/drivers/dri/i915/intel_state.c |4 ++-- src/mesa/drivers/dri/i965/intel_buffers.c |5 ++--- 2 files changed, 4 insertions(+), 5 deletions(-) via 709f24adbb21419881f0d857c8454814f85c2757 (commit) from 52fe7ea3d15d525efa0c89d0a8be8cd9067a74b7 (commit) - Commits --- commit 709f24adbb21419881f0d857c8454814f85c2757 Author: Xiang, Haihao [EMAIL PROTECTED] Date: Wed May 14 15:01:00 2008 +0800 intel: Set right cliprects for the current draw region. fix #15057 - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
mesa: Changes to 'mesa_7_0_branch'
The branch, mesa_7_0_branch has been updated Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=mesa_7_0_branch Summary of changes: src/mesa/drivers/dri/i915/intel_context.c |2 ++ src/mesa/drivers/dri/i915/intel_context.h |1 + src/mesa/drivers/dri/i915/intel_screen.c |1 + 3 files changed, 4 insertions(+), 0 deletions(-) via 44f6a6f9c4195727e8819007ac4e3aeac898838a (commit) from ac88b3dd168ce04f5495fc73c3270a282d0ec1ca (commit) - Commits --- commit 44f6a6f9c4195727e8819007ac4e3aeac898838a Author: Xiang, Haihao [EMAIL PROTECTED] Date: Wed May 7 14:09:28 2008 +0800 i915: Add E7221 variant to i915. Cherry picked from commit 39bcbe0921e8a31b55ebee8726d2091fc5e0dd22 - ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
