Mesa (master): intel/blorp: Don't vertex fetch directly from clear values
Module: Mesa
Branch: master
Commit: 44c614843c8785be57af06cc56208ad1497d05bc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=44c614843c8785be57af06cc56208ad1497d05bc
Author: Jason Ekstrand
Date: Mon Jun 4 17:27:53 2018 -0700
intel/blorp: Don't vertex fetch directly from clear values
On gen8+, we have to VF cache flush whenever a vertex binding aliases a
previous binding at the same index modulo 4GiB. We deal with this in
Vulkan by ensuring that vertex buffers and the dynamic state (from which
BLORP pulls its vertex buffers) are in the same 4GiB region of the
address space. That doesn't work if we're reading clear colors with the
VF unit. In order to work around this we switch to using MI commands to
copy the clear value into the vertex buffer we allocate for the normal
constant data.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Kenneth Graunke
---
src/intel/blorp/blorp_genX_exec.h | 85 +++
1 file changed, 41 insertions(+), 44 deletions(-)
diff --git a/src/intel/blorp/blorp_genX_exec.h
b/src/intel/blorp/blorp_genX_exec.h
index 446743b591..bcaef4f367 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -200,6 +200,14 @@ emit_urb_config(struct blorp_batch *batch,
blorp_emit_urb_config(batch, vs_entry_size, sf_entry_size);
}
+#if GEN_GEN >= 7
+static void
+blorp_emit_memcpy(struct blorp_batch *batch,
+ struct blorp_address dst,
+ struct blorp_address src,
+ uint32_t size);
+#endif
+
static void
blorp_emit_vertex_data(struct blorp_batch *batch,
const struct blorp_params *params,
@@ -260,6 +268,31 @@ blorp_emit_input_varying_data(struct blorp_batch *batch,
}
blorp_flush_range(batch, data, *size);
+
+ if (params->dst_clear_color_as_input) {
+#if GEN_GEN >= 7
+ /* In this case, the clear color isn't known statically and instead
+ * comes in through an indirect which we have to copy into the vertex
+ * buffer before we execute the 3DPRIMITIVE. We already copied the
+ * value of params->wm_inputs.clear_color into the vertex buffer in the
+ * loop above. Now we emit code to stomp it from the GPU with the
+ * actual clear color value.
+ */
+ assert(num_varyings == 1);
+
+ /* The clear color is the first thing after the header */
+ struct blorp_address clear_color_input_addr = *addr;
+ clear_color_input_addr.offset += 16;
+
+ const unsigned clear_color_size =
+ GEN_GEN < 10 ? batch->blorp->isl_dev->ss.clear_value_size : 4 * 4;
+ blorp_emit_memcpy(batch, clear_color_input_addr,
+params->dst.clear_color_addr,
+clear_color_size);
+#else
+ unreachable("MCS partial resolve is not a thing on SNB and earlier");
+#endif
+ }
}
static void
@@ -298,6 +331,7 @@ blorp_emit_vertex_buffers(struct blorp_batch *batch,
const struct blorp_params *params)
{
struct GENX(VERTEX_BUFFER_STATE) vb[3];
+ uint32_t num_vbs = 2;
memset(vb, 0, sizeof(vb));
struct blorp_address addr;
@@ -308,15 +342,6 @@ blorp_emit_vertex_buffers(struct blorp_batch *batch,
blorp_emit_input_varying_data(batch, params, , );
blorp_fill_vertex_buffer_state(batch, vb, 1, addr, size, 0);
- uint32_t num_vbs = 2;
- if (params->dst_clear_color_as_input) {
- const unsigned clear_color_size =
- GEN_GEN < 10 ? batch->blorp->isl_dev->ss.clear_value_size : 4 * 4;
- blorp_fill_vertex_buffer_state(batch, vb, num_vbs++,
- params->dst.clear_color_addr,
- clear_color_size, 0);
- }
-
const unsigned num_dwords = 1 + num_vbs * GENX(VERTEX_BUFFER_STATE_length);
uint32_t *dw = blorp_emitn(batch, GENX(3DSTATE_VERTEX_BUFFERS), num_dwords);
if (!dw)
@@ -449,49 +474,21 @@ blorp_emit_vertex_elements(struct blorp_batch *batch,
};
slot++;
- if (params->dst_clear_color_as_input) {
- /* If the caller wants the destination indirect clear color, redirect
- * to vertex buffer 2 where we stored it earlier. The only users of
- * an indirect clear color source have that as their only vertex
- * attribute.
- */
- assert(num_varyings == 1);
+ for (unsigned i = 0; i < num_varyings; ++i) {
ve[slot] = (struct GENX(VERTEX_ELEMENT_STATE)) {
- .VertexBufferIndex = 2,
+ .VertexBufferIndex = 1,
.Valid = true,
- .SourceElementOffset = 0,
- .Component0Control = VFCOMP_STORE_SRC,
-#if GEN_GEN >= 9
.SourceElementFormat = ISL_FORMAT_R32G32B32A32_FLOAT,
+ .SourceElementOffset = 16 + i * 4 * sizeof(float),
+ .Component0Control = VFCOMP_STORE_SRC,
.Component1Control = VFCOMP_STORE_SRC,
.Component2Control = VFCOMP_ST
Mesa (master): intel/eu: Use a struct copy instead of a memcpy
Module: Mesa
Branch: master
Commit: 01ad2067bba17451c663983877ec85145de20f02
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=01ad2067bba17451c663983877ec85145de20f02
Author: Jason Ekstrand
Date: Tue Jun 5 14:33:12 2018 -0700
intel/eu: Use a struct copy instead of a memcpy
The memcpy had the wrong size and this was causing crashes on 32-bit
builds of the driver.
Fixes: 6a9525bf6729a8 "intel/eu: Switch to a logical state stack"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106830
Reviewed-by: Kenneth Graunke
---
src/intel/compiler/brw_eu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
index d0e4ea2070..6ef0a6a577 100644
--- a/src/intel/compiler/brw_eu.c
+++ b/src/intel/compiler/brw_eu.c
@@ -289,7 +289,7 @@ void brw_set_default_acc_write_control(struct brw_codegen
*p, unsigned value)
void brw_push_insn_state( struct brw_codegen *p )
{
assert(p->current != >stack[BRW_EU_MAX_INSN_STACK-1]);
- memcpy(p->current + 1, p->current, sizeof(brw_inst));
+ *(p->current + 1) = *p->current;
p->current++;
}
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Mesa (master): i965/miptree: Rename a parameter to create_for_dri_image
Module: Mesa
Branch: master
Commit: 6ab9fe7673c77a367ceca3e77d95617b5a2a412f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ab9fe7673c77a367ceca3e77d95617b5a2a412f
Author: Jason Ekstrand
Date: Thu May 31 11:42:17 2018 -0700
i965/miptree: Rename a parameter to create_for_dri_image
Instead of having it be a general "is this a winsys image" boolean, make
it more specific to the actual purpose.
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 +++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 7d1fa96b91..69024c0678 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1013,7 +1013,7 @@ struct intel_mipmap_tree *
intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image, GLenum target,
mesa_format format,
- bool is_winsys_image)
+ bool allow_internal_aux)
{
uint32_t bo_tiling, bo_swizzle;
brw_bo_get_tiling(image->bo, _tiling, _swizzle);
@@ -1056,7 +1056,7 @@ intel_miptree_create_for_dri_image(struct brw_context
*brw,
* other hand, have no resolve point so we can't have aux without a
* modifier.
*/
- if (!is_winsys_image)
+ if (!allow_internal_aux)
mt_create_flags |= MIPTREE_CREATE_NO_AUX;
/* If we have a modifier which specifies aux, don't create one yet */
@@ -1105,7 +1105,7 @@ intel_miptree_create_for_dri_image(struct brw_context
*brw,
* as part of the flush operation.
*/
mt->supports_fast_clear =
- is_winsys_image || mod_info->supports_clear_color;
+ allow_internal_aux || mod_info->supports_clear_color;
/* We don't know the actual state of the surface when we get it but we
* can make a pretty good guess based on the modifier. What we do know
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 42f73ba1f9..ef8f51840c 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -410,7 +410,7 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image,
GLenum target,
mesa_format format,
- bool is_winsys_image);
+ bool allow_internal_aux);
bool
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
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Mesa (master): i965: Disable internal CCS for shadows of multi-sampled windows
Module: Mesa Branch: master Commit: e99b32d4d6f0cce43ead45fee5d24c882004ba2f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e99b32d4d6f0cce43ead45fee5d24c882004ba2f Author: Jason Ekstrand Date: Thu May 31 17:00:35 2018 -0700 i965: Disable internal CCS for shadows of multi-sampled windows If window system supports Y-tiling but not CCS_E, we currently create an internal CCS for any window system buffers and then resolve right before handing it off to X or Wayland. In the case of the single-sampled shadow of a multi-sampled window system buffer, this is pointless because the only thing we do with it is use it as a MSAA resolve target so we do MSAA resolve -> CCS resolve -> hand to the window system. Instead, just disable CCS for the shadow and then the MSAA resolve will write uncompressed directly into it. If the window system supports CCS_E, we will still use CCS_E, we just won't do internal CCS. Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_context.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index bd1e20845f..9ced230ec1 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -1688,9 +1688,18 @@ intel_update_image_buffer(struct brw_context *intel, if (last_mt && last_mt->bo == buffer->bo) return; + /* Only allow internal compression if samples == 0. For multisampled +* window system buffers, the only thing the single-sampled buffer is used +* for is as a resolve target. If we do any compression beyond what is +* supported by the window system, we will just have to resolve so it's +* probably better to just not bother. +*/ + const bool allow_internal_aux = (num_samples == 0); + struct intel_mipmap_tree *mt = intel_miptree_create_for_dri_image(intel, buffer, GL_TEXTURE_2D, - intel_rb_format(rb), true); + intel_rb_format(rb), + allow_internal_aux); if (!mt) return; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Disable internal CCS for shadows of multi-sampled windows
Module: Mesa Branch: master Commit: 52d145e76308e58a9371fa4746f4aec5bd39357c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=52d145e76308e58a9371fa4746f4aec5bd39357c Author: Jason Ekstrand Date: Thu May 31 17:00:35 2018 -0700 i965: Disable internal CCS for shadows of multi-sampled windows If window system supports Y-tiling but not CCS_E, we currently create an internal CCS for any window system buffers and then resolve right before handing it off to X or Wayland. In the case of the single-sampled shadow of a multi-sampled window system buffer, this is pointless because the only thing we do with it is use it as a MSAA resolve target so we do MSAA resolve -> CCS resolve -> hand to the window system. Instead, just disable CCS for the shadow and then the MSAA resolve will write uncompressed directly into it. If the window system supports CCS_E, we will still use CCS_E, we just won't do internal CCS. Cc: Chad Versace --- src/mesa/drivers/dri/i965/brw_context.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index bd1e20845f..9ced230ec1 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -1688,9 +1688,18 @@ intel_update_image_buffer(struct brw_context *intel, if (last_mt && last_mt->bo == buffer->bo) return; + /* Only allow internal compression if samples == 0. For multisampled +* window system buffers, the only thing the single-sampled buffer is used +* for is as a resolve target. If we do any compression beyond what is +* supported by the window system, we will just have to resolve so it's +* probably better to just not bother. +*/ + const bool allow_internal_aux = (num_samples == 0); + struct intel_mipmap_tree *mt = intel_miptree_create_for_dri_image(intel, buffer, GL_TEXTURE_2D, - intel_rb_format(rb), true); + intel_rb_format(rb), + allow_internal_aux); if (!mt) return; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/miptree: Rename a parameter to create_for_dri_image
Module: Mesa
Branch: master
Commit: a71e515b98b5456ce8149f17b1d7b6204464a931
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a71e515b98b5456ce8149f17b1d7b6204464a931
Author: Jason Ekstrand
Date: Thu May 31 11:42:17 2018 -0700
i965/miptree: Rename a parameter to create_for_dri_image
Instead of having it be a general "is this a winsys image" boolean, make
it more specific to the actual purpose.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 +++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 7d1fa96b91..69024c0678 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1013,7 +1013,7 @@ struct intel_mipmap_tree *
intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image, GLenum target,
mesa_format format,
- bool is_winsys_image)
+ bool allow_internal_aux)
{
uint32_t bo_tiling, bo_swizzle;
brw_bo_get_tiling(image->bo, _tiling, _swizzle);
@@ -1056,7 +1056,7 @@ intel_miptree_create_for_dri_image(struct brw_context
*brw,
* other hand, have no resolve point so we can't have aux without a
* modifier.
*/
- if (!is_winsys_image)
+ if (!allow_internal_aux)
mt_create_flags |= MIPTREE_CREATE_NO_AUX;
/* If we have a modifier which specifies aux, don't create one yet */
@@ -1105,7 +1105,7 @@ intel_miptree_create_for_dri_image(struct brw_context
*brw,
* as part of the flush operation.
*/
mt->supports_fast_clear =
- is_winsys_image || mod_info->supports_clear_color;
+ allow_internal_aux || mod_info->supports_clear_color;
/* We don't know the actual state of the surface when we get it but we
* can make a pretty good guess based on the modifier. What we do know
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 42f73ba1f9..ef8f51840c 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -410,7 +410,7 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
__DRIimage *image,
GLenum target,
mesa_format format,
- bool is_winsys_image);
+ bool allow_internal_aux);
bool
intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
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Mesa (master): intel/eu: Set flag [sub]register number differently for 3src
Module: Mesa
Branch: master
Commit: db9675f5a4c68e39bb777eb7003f01854fd235dc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=db9675f5a4c68e39bb777eb7003f01854fd235dc
Author: Jason Ekstrand
Date: Tue May 29 15:28:36 2018 -0700
intel/eu: Set flag [sub]register number differently for 3src
Prior to gen8, the flag [sub]register number is in a different spot on
3src instructions than on other instructions. Starting with Broadwell,
they made it consistent. This commit fixes bugs that occur when a
conditional modifier gets propagated into a 3src instruction such as a
MAD.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Kenneth Graunke
---
src/intel/compiler/brw_eu_emit.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index a660d9eaaa..412a051bc9 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -701,9 +701,16 @@ brw_inst_set_state(const struct gen_device_info *devinfo,
brw_inst_set_pred_control(devinfo, insn, state->predicate);
brw_inst_set_pred_inv(devinfo, insn, state->pred_inv);
- brw_inst_set_flag_subreg_nr(devinfo, insn, state->flag_subreg % 2);
- if (devinfo->gen >= 7)
- brw_inst_set_flag_reg_nr(devinfo, insn, state->flag_subreg / 2);
+ if (is_3src(devinfo, brw_inst_opcode(devinfo, insn)) &&
+ state->access_mode == BRW_ALIGN_16) {
+ brw_inst_set_3src_a16_flag_subreg_nr(devinfo, insn, state->flag_subreg %
2);
+ if (devinfo->gen >= 7)
+ brw_inst_set_3src_a16_flag_reg_nr(devinfo, insn, state->flag_subreg /
2);
+ } else {
+ brw_inst_set_flag_subreg_nr(devinfo, insn, state->flag_subreg % 2);
+ if (devinfo->gen >= 7)
+ brw_inst_set_flag_reg_nr(devinfo, insn, state->flag_subreg / 2);
+ }
if (devinfo->gen >= 6)
brw_inst_set_acc_wr_control(devinfo, insn, state->acc_wr_control);
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Mesa (master): intel/eu: Switch to a logical state stack
Module: Mesa
Branch: master
Commit: 6a9525bf6729a8d2bb9c6a7b10ebdc9925c55463
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a9525bf6729a8d2bb9c6a7b10ebdc9925c55463
Author: Jason Ekstrand
Date: Tue May 29 14:37:35 2018 -0700
intel/eu: Switch to a logical state stack
Instead of the state stack that's based on copying a dummy instruction
around, we start using a logical stack of brw_insn_states. This uses a
bit less memory and is way less conceptually bogus.
Reviewed-by: Kenneth Graunke
---
src/intel/compiler/brw_eu.c | 90 +---
src/intel/compiler/brw_eu.h | 34 ++-
src/intel/compiler/brw_eu_emit.c | 74 ++---
3 files changed, 72 insertions(+), 126 deletions(-)
diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
index 5375209d4f..d0e4ea2070 100644
--- a/src/intel/compiler/brw_eu.c
+++ b/src/intel/compiler/brw_eu.c
@@ -129,91 +129,76 @@ brw_swizzle_immediate(enum brw_reg_type type, uint32_t x,
unsigned swz)
unsigned
brw_get_default_exec_size(struct brw_codegen *p)
{
- return brw_inst_exec_size(p->devinfo, p->current);
+ return p->current->exec_size;
}
unsigned
brw_get_default_group(struct brw_codegen *p)
{
- if (p->devinfo->gen >= 6) {
- unsigned group = brw_inst_qtr_control(p->devinfo, p->current) * 8;
- if (p->devinfo->gen >= 7)
- group += brw_inst_nib_control(p->devinfo, p->current) * 4;
- return group;
- } else {
- unsigned qtr_control = brw_inst_qtr_control(p->devinfo, p->current);
- if (qtr_control == BRW_COMPRESSION_COMPRESSED)
- return 0;
- else
- return qtr_control * 8;
- }
+ return p->current->group;
}
unsigned
brw_get_default_access_mode(struct brw_codegen *p)
{
- return brw_inst_access_mode(p->devinfo, p->current);
+ return p->current->access_mode;
}
void
brw_set_default_exec_size(struct brw_codegen *p, unsigned value)
{
- brw_inst_set_exec_size(p->devinfo, p->current, value);
+ p->current->exec_size = value;
}
void brw_set_default_predicate_control( struct brw_codegen *p, unsigned pc )
{
- brw_inst_set_pred_control(p->devinfo, p->current, pc);
+ p->current->predicate = pc;
}
void brw_set_default_predicate_inverse(struct brw_codegen *p, bool
predicate_inverse)
{
- brw_inst_set_pred_inv(p->devinfo, p->current, predicate_inverse);
+ p->current->pred_inv = predicate_inverse;
}
void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg)
{
- if (p->devinfo->gen >= 7)
- brw_inst_set_flag_reg_nr(p->devinfo, p->current, reg);
-
- brw_inst_set_flag_subreg_nr(p->devinfo, p->current, subreg);
+ assert(subreg < 2);
+ p->current->flag_subreg = reg * 2 + subreg;
}
void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode )
{
- brw_inst_set_access_mode(p->devinfo, p->current, access_mode);
+ p->current->access_mode = access_mode;
}
void
brw_set_default_compression_control(struct brw_codegen *p,
enum brw_compression compression_control)
{
- if (p->devinfo->gen >= 6) {
- /* Since we don't use the SIMD32 support in gen6, we translate
- * the pre-gen6 compression control here.
+ switch (compression_control) {
+ case BRW_COMPRESSION_NONE:
+ /* This is the "use the first set of bits of dmask/vmask/arf
+ * according to execsize" option.
*/
- switch (compression_control) {
- case BRW_COMPRESSION_NONE:
-/* This is the "use the first set of bits of dmask/vmask/arf
- * according to execsize" option.
- */
- brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_1Q);
-break;
- case BRW_COMPRESSION_2NDHALF:
-/* For SIMD8, this is "use the second set of 8 bits." */
- brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_2Q);
-break;
- case BRW_COMPRESSION_COMPRESSED:
-/* For SIMD16 instruction compression, use the first set of 16 bits
- * since we don't do SIMD32 dispatch.
- */
- brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_1H);
-break;
- default:
- unreachable("not reached");
- }
- } else {
- brw_inst_set_qtr_control(p->devinfo, p->current, compression_control);
+ p->current->group = 0;
+ break;
+ case BRW_COMPRESSION_2NDHALF:
+ /* For SIMD8, this is "use the second set of 8 bits." */
+ p->current->group = 8;
+ break;
+ case BRW_COMPRESSION_COMPRESSED:
+ /* For SIMD16 instruction compression, use the first set of 16 bits
+ * since we don't do SIMD32 dispatch.
+ */
+ p->cu
Mesa (master): intel/eu: Add some brw_get_default_ helpers
Module: Mesa
Branch: master
Commit: 381fac274054784e4cbd152168653aecb9f1e5dd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=381fac274054784e4cbd152168653aecb9f1e5dd
Author: Jason Ekstrand
Date: Tue May 29 14:50:46 2018 -0700
intel/eu: Add some brw_get_default_ helpers
This is much cleaner than everything that wants a default value poking
at the bits of p->current directly.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Kenneth Graunke
---
src/intel/compiler/brw_eu.c | 29 ++
src/intel/compiler/brw_eu.h | 3 +
src/intel/compiler/brw_eu_emit.c| 98 +++--
src/intel/compiler/brw_fs_generator.cpp | 4 +-
4 files changed, 79 insertions(+), 55 deletions(-)
diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
index 3646076a8e..5375209d4f 100644
--- a/src/intel/compiler/brw_eu.c
+++ b/src/intel/compiler/brw_eu.c
@@ -126,6 +126,35 @@ brw_swizzle_immediate(enum brw_reg_type type, uint32_t x,
unsigned swz)
}
}
+unsigned
+brw_get_default_exec_size(struct brw_codegen *p)
+{
+ return brw_inst_exec_size(p->devinfo, p->current);
+}
+
+unsigned
+brw_get_default_group(struct brw_codegen *p)
+{
+ if (p->devinfo->gen >= 6) {
+ unsigned group = brw_inst_qtr_control(p->devinfo, p->current) * 8;
+ if (p->devinfo->gen >= 7)
+ group += brw_inst_nib_control(p->devinfo, p->current) * 4;
+ return group;
+ } else {
+ unsigned qtr_control = brw_inst_qtr_control(p->devinfo, p->current);
+ if (qtr_control == BRW_COMPRESSION_COMPRESSED)
+ return 0;
+ else
+ return qtr_control * 8;
+ }
+}
+
+unsigned
+brw_get_default_access_mode(struct brw_codegen *p)
+{
+ return brw_inst_access_mode(p->devinfo, p->current);
+}
+
void
brw_set_default_exec_size(struct brw_codegen *p, unsigned value)
{
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 84d5a6f86b..d709d12b67 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -106,6 +106,9 @@ struct brw_codegen {
void brw_pop_insn_state( struct brw_codegen *p );
void brw_push_insn_state( struct brw_codegen *p );
+unsigned brw_get_default_exec_size(struct brw_codegen *p);
+unsigned brw_get_default_group(struct brw_codegen *p);
+unsigned brw_get_default_access_mode(struct brw_codegen *p);
void brw_set_default_exec_size(struct brw_codegen *p, unsigned value);
void brw_set_default_mask_control( struct brw_codegen *p, unsigned value );
void brw_set_default_saturate( struct brw_codegen *p, bool enable );
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index c442f8cc6f..80eea9ecba 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -997,7 +997,7 @@ brw_MOV(struct brw_codegen *p, struct brw_reg dest, struct
brw_reg src0)
* each element twice.
*/
if (devinfo->gen == 7 && !devinfo->is_haswell &&
- brw_inst_access_mode(devinfo, p->current) == BRW_ALIGN_1 &&
+ brw_get_default_access_mode(p) == BRW_ALIGN_1 &&
dest.type == BRW_REGISTER_TYPE_DF &&
(src0.type == BRW_REGISTER_TYPE_F ||
src0.type == BRW_REGISTER_TYPE_D ||
@@ -1119,7 +1119,7 @@ brw_inst *
brw_F32TO16(struct brw_codegen *p, struct brw_reg dst, struct brw_reg src)
{
const struct gen_device_info *devinfo = p->devinfo;
- const bool align16 = brw_inst_access_mode(devinfo, p->current) ==
BRW_ALIGN_16;
+ const bool align16 = brw_get_default_access_mode(p) == BRW_ALIGN_16;
/* The F32TO16 instruction doesn't support 32-bit destination types in
* Align1 mode, and neither does the Gen8 implementation in terms of a
* converting MOV. Gen7 does zero out the high 16 bits in Align16 mode as
@@ -1166,7 +1166,7 @@ brw_inst *
brw_F16TO32(struct brw_codegen *p, struct brw_reg dst, struct brw_reg src)
{
const struct gen_device_info *devinfo = p->devinfo;
- bool align16 = brw_inst_access_mode(devinfo, p->current) == BRW_ALIGN_16;
+ bool align16 = brw_get_default_access_mode(p) == BRW_ALIGN_16;
if (align16) {
assert(src.type == BRW_REGISTER_TYPE_UD);
@@ -1337,8 +1337,7 @@ gen6_IF(struct brw_codegen *p, enum brw_conditional_mod
conditional,
insn = next_insn(p, BRW_OPCODE_IF);
brw_set_dest(p, insn, brw_imm_w(0));
- brw_inst_set_exec_size(devinfo, insn,
- brw_inst_exec_size(devinfo, p->current));
+ brw_inst_set_exec_size(devinfo, insn, brw_get_default_exec_size(p));
brw_inst_set_gen6_jump_count(devinfo, insn, 0);
brw_set_src0(p, insn, src0);
brw_set_src1(p, insn, src1);
@@ -1624,8 +1623,7 @@ brw_BREAK(struct brw_codegen *p)
p->if_depth_in_loop[p->loop_stack_depth]);
}
brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
- brw_inst_set_exec_size(dev
Mesa (master): intel/eu: Copy fields manually in brw_next_insn
Module: Mesa
Branch: master
Commit: 2d20303e1874a862117f526ee87789b00b049078
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d20303e1874a862117f526ee87789b00b049078
Author: Jason Ekstrand
Date: Tue May 29 13:45:57 2018 -0700
intel/eu: Copy fields manually in brw_next_insn
Instead of doing a memcpy, this moves us to start with a blank
instruction (memset to zero) and copy the fields over one at a time.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Kenneth Graunke
---
src/intel/compiler/brw_eu_emit.c | 95 +++-
1 file changed, 94 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 80eea9ecba..a660d9eaaa 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -621,6 +621,94 @@ gen7_set_dp_scratch_message(struct brw_codegen *p,
brw_inst_set_scratch_addr_offset(devinfo, inst, addr_offset);
}
+struct brw_insn_state {
+ /* One of BRW_EXECUTE_* */
+ unsigned exec_size:3;
+
+ /* Group in units of channels */
+ unsigned group:5;
+
+ /* Compression control on gen4-5 */
+ bool compressed:1;
+
+ /* One of BRW_MASK_* */
+ unsigned mask_control:1;
+
+ bool saturate:1;
+
+ /* One of BRW_ALIGN_* */
+ unsigned access_mode:1;
+
+ /* One of BRW_PREDICATE_* */
+ enum brw_predicate predicate:4;
+
+ bool pred_inv:1;
+
+ /* Flag subreg. Bottom bit is subreg, top bit is reg */
+ unsigned flag_subreg:2;
+
+ bool acc_wr_control:1;
+};
+
+static struct brw_insn_state
+brw_inst_get_state(const struct gen_device_info *devinfo,
+ const brw_inst *insn)
+{
+ struct brw_insn_state state = { };
+
+ state.exec_size = brw_inst_exec_size(devinfo, insn);
+ if (devinfo->gen >= 6) {
+ state.group = brw_inst_qtr_control(devinfo, insn) * 8;
+ if (devinfo->gen >= 7)
+ state.group += brw_inst_nib_control(devinfo, insn) * 4;
+ } else {
+ unsigned qtr_control = brw_inst_qtr_control(devinfo, insn);
+ if (qtr_control == BRW_COMPRESSION_COMPRESSED) {
+ state.group = 0;
+ state.compressed = true;
+ } else {
+ state.group = qtr_control * 8;
+ state.compressed = false;
+ }
+ }
+ state.access_mode = brw_inst_access_mode(devinfo, insn);
+ state.mask_control = brw_inst_mask_control(devinfo, insn);
+ state.saturate = brw_inst_saturate(devinfo, insn);
+ state.predicate = brw_inst_pred_control(devinfo, insn);
+ state.pred_inv = brw_inst_pred_inv(devinfo, insn);
+
+ state.flag_subreg = brw_inst_flag_subreg_nr(devinfo, insn);
+ if (devinfo->gen >= 7)
+ state.flag_subreg += brw_inst_flag_reg_nr(devinfo, insn) * 2;
+
+ if (devinfo->gen >= 6)
+ state.acc_wr_control = brw_inst_acc_wr_control(devinfo, insn);
+
+ return state;
+}
+
+static void
+brw_inst_set_state(const struct gen_device_info *devinfo,
+ brw_inst *insn,
+ const struct brw_insn_state *state)
+{
+ brw_inst_set_exec_size(devinfo, insn, state->exec_size);
+ brw_inst_set_group(devinfo, insn, state->group);
+ brw_inst_set_compression(devinfo, insn, state->compressed);
+ brw_inst_set_access_mode(devinfo, insn, state->access_mode);
+ brw_inst_set_mask_control(devinfo, insn, state->mask_control);
+ brw_inst_set_saturate(devinfo, insn, state->saturate);
+ brw_inst_set_pred_control(devinfo, insn, state->predicate);
+ brw_inst_set_pred_inv(devinfo, insn, state->pred_inv);
+
+ brw_inst_set_flag_subreg_nr(devinfo, insn, state->flag_subreg % 2);
+ if (devinfo->gen >= 7)
+ brw_inst_set_flag_reg_nr(devinfo, insn, state->flag_subreg / 2);
+
+ if (devinfo->gen >= 6)
+ brw_inst_set_acc_wr_control(devinfo, insn, state->acc_wr_control);
+}
+
#define next_insn brw_next_insn
brw_inst *
brw_next_insn(struct brw_codegen *p, unsigned opcode)
@@ -635,9 +723,14 @@ brw_next_insn(struct brw_codegen *p, unsigned opcode)
p->next_insn_offset += 16;
insn = >store[p->nr_insn++];
- memcpy(insn, p->current, sizeof(*insn));
+ memset(insn, 0, sizeof(*insn));
brw_inst_set_opcode(devinfo, insn, opcode);
+
+ /* Apply the default instruction state */
+ struct brw_insn_state current = brw_inst_get_state(devinfo, p->current);
+ brw_inst_set_state(devinfo, insn, );
+
return insn;
}
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Mesa (master): anv: Don't even bother processing relocs if we have softpin
Module: Mesa
Branch: master
Commit: 64e619674e9b6b9c8101353cd8cda6e064d84199
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=64e619674e9b6b9c8101353cd8cda6e064d84199
Author: Jason Ekstrand
Date: Fri Jun 1 14:26:45 2018 -0700
anv: Don't even bother processing relocs if we have softpin
Reviewed-by: Scott D Phillips
---
src/intel/vulkan/anv_batch_chain.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/src/intel/vulkan/anv_batch_chain.c
b/src/intel/vulkan/anv_batch_chain.c
index de629c12f7..c47a81c8a4 100644
--- a/src/intel/vulkan/anv_batch_chain.c
+++ b/src/intel/vulkan/anv_batch_chain.c
@@ -996,6 +996,8 @@ struct anv_execbuf {
/* Allocated length of the 'objects' and 'bos' arrays */
uint32_t array_length;
+ bool has_relocs;
+
uint32_t fence_count;
uint32_t fence_array_length;
struct drm_i915_gem_exec_fence * fences;
@@ -1099,6 +1101,7 @@ anv_execbuf_add_bo(struct anv_execbuf *exec,
* this BO. Go ahead and set the relocations and then walk the list
* of relocations and add them all.
*/
+ exec->has_relocs = true;
obj->relocation_count = relocs->num_relocs;
obj->relocs_ptr = (uintptr_t) relocs->relocs;
@@ -1300,6 +1303,9 @@ static bool
relocate_cmd_buffer(struct anv_cmd_buffer *cmd_buffer,
struct anv_execbuf *exec)
{
+ if (!exec->has_relocs)
+ return true;
+
static int userspace_relocs = -1;
if (userspace_relocs < 0)
userspace_relocs = env_var_as_boolean("ANV_USERSPACE_RELOCS", true);
@@ -1403,14 +1409,20 @@ setup_execbuf_for_cmd_buffer(struct anv_execbuf
*execbuf,
first_batch_bo->bo.index = last_idx;
}
+ /* If we are pinning our BOs, we shouldn't have to relocate anything */
+ if (cmd_buffer->device->instance->physicalDevice.use_softpin)
+ assert(!execbuf->has_relocs);
+
/* Now we go through and fixup all of the relocation lists to point to
* the correct indices in the object array. We have to do this after we
* reorder the list above as some of the indices may have changed.
*/
- u_vector_foreach(bbo, _buffer->seen_bbos)
- anv_cmd_buffer_process_relocs(cmd_buffer, &(*bbo)->relocs);
+ if (execbuf->has_relocs) {
+ u_vector_foreach(bbo, _buffer->seen_bbos)
+ anv_cmd_buffer_process_relocs(cmd_buffer, &(*bbo)->relocs);
- anv_cmd_buffer_process_relocs(cmd_buffer, _buffer->surface_relocs);
+ anv_cmd_buffer_process_relocs(cmd_buffer, _buffer->surface_relocs);
+ }
if (!cmd_buffer->device->info.has_llc) {
__builtin_ia32_mfence();
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Mesa (master): anv: Refactor reloc handling in execbuf_add_bo
Module: Mesa
Branch: master
Commit: c7be17c8d32ca583be975d8c239585f3a6bbc39b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c7be17c8d32ca583be975d8c239585f3a6bbc39b
Author: Jason Ekstrand
Date: Fri Jun 1 14:59:14 2018 -0700
anv: Refactor reloc handling in execbuf_add_bo
This just separates the reloc list vs. BO set cases and lets us avoid an
allocation if relocs->deps->entries == 0.
Reviewed-by: Scott D Phillips
---
src/intel/vulkan/anv_batch_chain.c | 78 --
1 file changed, 42 insertions(+), 36 deletions(-)
diff --git a/src/intel/vulkan/anv_batch_chain.c
b/src/intel/vulkan/anv_batch_chain.c
index 5100450eec..de629c12f7 100644
--- a/src/intel/vulkan/anv_batch_chain.c
+++ b/src/intel/vulkan/anv_batch_chain.c
@@ -1091,52 +1091,58 @@ anv_execbuf_add_bo(struct anv_execbuf *exec,
obj->rsvd2 = 0;
}
- if (relocs != NULL && obj->relocation_count == 0) {
- /* This is the first time we've ever seen a list of relocations for
- * this BO. Go ahead and set the relocations and then walk the list
- * of relocations and add them all.
- */
- obj->relocation_count = relocs->num_relocs;
- obj->relocs_ptr = (uintptr_t) relocs->relocs;
+ if (relocs != NULL) {
+ assert(obj->relocation_count == 0);
- for (size_t i = 0; i < relocs->num_relocs; i++) {
- VkResult result;
+ if (relocs->num_relocs > 0) {
+ /* This is the first time we've ever seen a list of relocations for
+ * this BO. Go ahead and set the relocations and then walk the list
+ * of relocations and add them all.
+ */
+ obj->relocation_count = relocs->num_relocs;
+ obj->relocs_ptr = (uintptr_t) relocs->relocs;
- /* A quick sanity check on relocations */
- assert(relocs->relocs[i].offset < bo->size);
- result = anv_execbuf_add_bo(exec, relocs->reloc_bos[i], NULL,
- extra_flags, alloc);
+ for (size_t i = 0; i < relocs->num_relocs; i++) {
+VkResult result;
- if (result != VK_SUCCESS)
-return result;
+/* A quick sanity check on relocations */
+assert(relocs->relocs[i].offset < bo->size);
+result = anv_execbuf_add_bo(exec, relocs->reloc_bos[i], NULL,
+extra_flags, alloc);
+
+if (result != VK_SUCCESS)
+ return result;
+ }
}
- const uint32_t entries = relocs->deps->entries;
- struct anv_bo **bos =
- vk_alloc(alloc, entries * sizeof(*bos),
- 8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
- if (bos == NULL)
- return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+ if (relocs->deps && relocs->deps->entries > 0) {
+ const uint32_t entries = relocs->deps->entries;
+ struct anv_bo **bos =
+vk_alloc(alloc, entries * sizeof(*bos),
+ 8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
+ if (bos == NULL)
+return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
- struct set_entry *entry;
- struct anv_bo **bo = bos;
- set_foreach(relocs->deps, entry) {
- *bo++ = (void *)entry->key;
- }
+ struct set_entry *entry;
+ struct anv_bo **bo = bos;
+ set_foreach(relocs->deps, entry) {
+*bo++ = (void *)entry->key;
+ }
- qsort(bos, entries, sizeof(struct anv_bo*), _compare_bo_handles);
+ qsort(bos, entries, sizeof(struct anv_bo*), _compare_bo_handles);
- VkResult result = VK_SUCCESS;
- for (bo = bos; bo < bos + entries; bo++) {
- result = anv_execbuf_add_bo(exec, *bo, NULL, extra_flags, alloc);
- if (result != VK_SUCCESS)
-break;
- }
+ VkResult result = VK_SUCCESS;
+ for (bo = bos; bo < bos + entries; bo++) {
+result = anv_execbuf_add_bo(exec, *bo, NULL, extra_flags, alloc);
+if (result != VK_SUCCESS)
+ break;
+ }
- vk_free(alloc, bos);
+ vk_free(alloc, bos);
- if (result != VK_SUCCESS)
- return result;
+ if (result != VK_SUCCESS)
+return result;
+ }
}
return VK_SUCCESS;
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Mesa (master): anv: Assert that the kernel leaves pinned BO addresses alone
Module: Mesa
Branch: master
Commit: 7105b7890ae0ccfab0d30ff037af588dd1af7c96
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7105b7890ae0ccfab0d30ff037af588dd1af7c96
Author: Jason Ekstrand
Date: Fri Jun 1 14:05:53 2018 -0700
anv: Assert that the kernel leaves pinned BO addresses alone
Reviewed-by: Scott D Phillips
---
src/intel/vulkan/anv_queue.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_queue.c b/src/intel/vulkan/anv_queue.c
index 80dddeb11b..a0cbc344b5 100644
--- a/src/intel/vulkan/anv_queue.c
+++ b/src/intel/vulkan/anv_queue.c
@@ -49,8 +49,11 @@ anv_device_execbuf(struct anv_device *device,
struct drm_i915_gem_exec_object2 *objects =
(void *)(uintptr_t)execbuf->buffers_ptr;
- for (uint32_t k = 0; k < execbuf->buffer_count; k++)
+ for (uint32_t k = 0; k < execbuf->buffer_count; k++) {
+ if (execbuf_bos[k]->flags & EXEC_OBJECT_PINNED)
+ assert(execbuf_bos[k]->offset == objects[k].offset);
execbuf_bos[k]->offset = objects[k].offset;
+ }
return VK_SUCCESS;
}
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Mesa (master): anv: Soft-pin state pools
Module: Mesa
Branch: master
Commit: e662bdb82084a9e8136aea1da10423786e103beb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e662bdb82084a9e8136aea1da10423786e103beb
Author: Scott D Phillips
Date: Thu Mar 1 09:25:44 2018 -0800
anv: Soft-pin state pools
The state_pools reserve virtual address space of the full
BLOCK_POOL_MEMFD_SIZE, but maintain the current behavior of
growing from the middle.
v2: - rename block_pool::offset to block_pool::start_address (Jason)
- assign state pool start_address statically (Jason)
v3: - remove unnecessary bo_flags tampering for the dynamic pool (Jason)
Reviewed-by: Jason Ekstrand
Reviewed-by: Jordan Justen
---
src/intel/vulkan/anv_allocator.c | 9 +
src/intel/vulkan/anv_device.c | 19 +--
src/intel/vulkan/anv_private.h | 8
src/intel/vulkan/tests/block_pool_no_free.c| 2 +-
src/intel/vulkan/tests/state_pool.c| 2 +-
src/intel/vulkan/tests/state_pool_free_list_only.c | 2 +-
src/intel/vulkan/tests/state_pool_no_free.c| 2 +-
7 files changed, 34 insertions(+), 10 deletions(-)
diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index 642e1618c1..a597280930 100644
--- a/src/intel/vulkan/anv_allocator.c
+++ b/src/intel/vulkan/anv_allocator.c
@@ -243,6 +243,7 @@ anv_block_pool_expand_range(struct anv_block_pool *pool,
VkResult
anv_block_pool_init(struct anv_block_pool *pool,
struct anv_device *device,
+uint64_t start_address,
uint32_t initial_size,
uint64_t bo_flags)
{
@@ -250,6 +251,8 @@ anv_block_pool_init(struct anv_block_pool *pool,
pool->device = device;
pool->bo_flags = bo_flags;
+ pool->start_address = gen_canonical_address(start_address);
+
anv_bo_init(>bo, 0, 0);
pool->fd = memfd_create("block pool", MFD_CLOEXEC);
@@ -402,6 +405,10 @@ anv_block_pool_expand_range(struct anv_block_pool *pool,
* hard work for us.
*/
anv_bo_init(>bo, gem_handle, size);
+ if (pool->bo_flags & EXEC_OBJECT_PINNED) {
+ pool->bo.offset = pool->start_address + BLOCK_POOL_MEMFD_CENTER -
+ center_bo_offset;
+ }
pool->bo.flags = pool->bo_flags;
pool->bo.map = map;
@@ -610,10 +617,12 @@ anv_block_pool_alloc_back(struct anv_block_pool *pool,
VkResult
anv_state_pool_init(struct anv_state_pool *pool,
struct anv_device *device,
+uint64_t start_address,
uint32_t block_size,
uint64_t bo_flags)
{
VkResult result = anv_block_pool_init(>block_pool, device,
+ start_address,
block_size * 16,
bo_flags);
if (result != VK_SUCCESS)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 19fa1b708f..e7201ec672 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1615,21 +1615,28 @@ VkResult anv_CreateDevice(
if (result != VK_SUCCESS)
goto fail_batch_bo_pool;
- /* For the state pools we explicitly disable 48bit. */
- bo_flags = (physical_device->has_exec_async ? EXEC_OBJECT_ASYNC : 0) |
- (physical_device->has_exec_capture ? EXEC_OBJECT_CAPTURE : 0);
+ if (physical_device->use_softpin)
+ bo_flags |= EXEC_OBJECT_PINNED;
+ else
+ bo_flags &= ~EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
- result = anv_state_pool_init(>dynamic_state_pool, device, 16384,
+ result = anv_state_pool_init(>dynamic_state_pool, device,
+DYNAMIC_STATE_POOL_MIN_ADDRESS,
+16384,
bo_flags);
if (result != VK_SUCCESS)
goto fail_bo_cache;
- result = anv_state_pool_init(>instruction_state_pool, device, 16384,
+ result = anv_state_pool_init(>instruction_state_pool, device,
+INSTRUCTION_STATE_POOL_MIN_ADDRESS,
+16384,
bo_flags);
if (result != VK_SUCCESS)
goto fail_dynamic_state_pool;
- result = anv_state_pool_init(>surface_state_pool, device, 4096,
+ result = anv_state_pool_init(>surface_state_pool, device,
+SURFACE_STATE_POOL_MIN_ADDRESS,
+4096,
bo_flags);
if (result != VK_SUCCESS)
goto fail_instruction_state_pool;
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 67a12c7206..1641aaf7a6 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -617,6 +617,12 @@ struct anv_block_pool {
struct anv_bo bo;
+ /* The address where the st
Mesa (master): anv: For pinned BOs, skip relocations, but track bo usage
Module: Mesa
Branch: master
Commit: 27cc68d9e90c8d2031383fa6dc28fe910a351eb6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=27cc68d9e90c8d2031383fa6dc28fe910a351eb6
Author: Scott D Phillips
Date: Tue Mar 13 10:57:39 2018 -0700
anv: For pinned BOs, skip relocations, but track bo usage
References to pinned BOs won't need to be relocated at a later
point, so just write the final value of the reference into the bo
directly.
Add a `set` to the relocation lists for tracking dependencies that
were previously tracked by relocations. When a batch is executed, we
add the referenced pinned BOs to the exec list.
v2: - visit bos from the dependency set in a deterministic order (Jason)
v3: - compar => compare, drat (Jason)
- Reworded commit message, provided by (Jordan)
Reviewed-by: Jordan Justen
Reviewed-by: Jason Ekstrand
---
src/intel/vulkan/anv_batch_chain.c | 63 ++
src/intel/vulkan/anv_private.h | 3 ++
2 files changed, 66 insertions(+)
diff --git a/src/intel/vulkan/anv_batch_chain.c
b/src/intel/vulkan/anv_batch_chain.c
index 9e01a275a1..fd738d0a03 100644
--- a/src/intel/vulkan/anv_batch_chain.c
+++ b/src/intel/vulkan/anv_batch_chain.c
@@ -75,11 +75,24 @@ anv_reloc_list_init_clone(struct anv_reloc_list *list,
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
}
+ list->deps = _mesa_set_create(NULL, _mesa_hash_pointer,
+ _mesa_key_pointer_equal);
+
+ if (!list->deps) {
+ vk_free(alloc, list->relocs);
+ vk_free(alloc, list->reloc_bos);
+ return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+ }
+
if (other_list) {
memcpy(list->relocs, other_list->relocs,
list->array_length * sizeof(*list->relocs));
memcpy(list->reloc_bos, other_list->reloc_bos,
list->array_length * sizeof(*list->reloc_bos));
+ struct set_entry *entry;
+ set_foreach(other_list->deps, entry) {
+ _mesa_set_add_pre_hashed(list->deps, entry->hash, entry->key);
+ }
}
return VK_SUCCESS;
@@ -98,6 +111,7 @@ anv_reloc_list_finish(struct anv_reloc_list *list,
{
vk_free(alloc, list->relocs);
vk_free(alloc, list->reloc_bos);
+ _mesa_set_destroy(list->deps, NULL);
}
static VkResult
@@ -148,6 +162,11 @@ anv_reloc_list_add(struct anv_reloc_list *list,
struct drm_i915_gem_relocation_entry *entry;
int index;
+ if (target_bo->flags & EXEC_OBJECT_PINNED) {
+ _mesa_set_add(list->deps, target_bo);
+ return VK_SUCCESS;
+ }
+
VkResult result = anv_reloc_list_grow(list, alloc, 1);
if (result != VK_SUCCESS)
return result;
@@ -185,6 +204,12 @@ anv_reloc_list_append(struct anv_reloc_list *list,
list->relocs[i + list->num_relocs].offset += offset;
list->num_relocs += other->num_relocs;
+
+ struct set_entry *entry;
+ set_foreach(other->deps, entry) {
+ _mesa_set_add_pre_hashed(list->deps, entry->hash, entry->key);
+ }
+
return VK_SUCCESS;
}
@@ -338,6 +363,7 @@ anv_batch_bo_start(struct anv_batch_bo *bbo, struct
anv_batch *batch,
batch->end = bbo->bo.map + bbo->bo.size - batch_padding;
batch->relocs = >relocs;
bbo->relocs.num_relocs = 0;
+ _mesa_set_clear(bbo->relocs.deps, NULL);
}
static void
@@ -784,6 +810,7 @@ anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer)
cmd_buffer->bt_next = 0;
cmd_buffer->surface_relocs.num_relocs = 0;
+ _mesa_set_clear(cmd_buffer->surface_relocs.deps, NULL);
cmd_buffer->last_ss_pool_center = 0;
/* Reset the list of seen buffers */
@@ -986,6 +1013,15 @@ anv_execbuf_finish(struct anv_execbuf *exec,
vk_free(alloc, exec->syncobjs);
}
+static int
+_compare_bo_handles(const void *_bo1, const void *_bo2)
+{
+ struct anv_bo * const *bo1 = _bo1;
+ struct anv_bo * const *bo2 = _bo2;
+
+ return (*bo1)->gem_handle - (*bo2)->gem_handle;
+}
+
static VkResult
anv_execbuf_add_bo(struct anv_execbuf *exec,
struct anv_bo *bo,
@@ -1069,6 +1105,33 @@ anv_execbuf_add_bo(struct anv_execbuf *exec,
if (result != VK_SUCCESS)
return result;
}
+
+ const uint32_t entries = relocs->deps->entries;
+ struct anv_bo **bos =
+ vk_alloc(alloc, entries * sizeof(*bos),
+ 8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
+ if (bos == NULL)
+ return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+
+ struct set_entry *entry;
+ struct anv_bo **bo = bos;
+ set_foreach(relocs->deps, entry) {
+ *bo++ = (void *)entry->key;
+ }
+
+ qsort(bos, entries, sizeof(struct anv_bo*), _compare_bo_handles);
+
+ VkResult result = VK_SUCCESS;
+ for (bo = bos; bo < bos + entries; bo++) {
+ result = anv_execbuf_add_bo(exec, *bo, NULL, extra_flags, alloc);
+
Mesa (master): anv: Use a separate pool for binding tables when soft pinning
Module: Mesa
Branch: master
Commit: c7db0ed4e94dce563d722e1b098684fbd7315d51
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c7db0ed4e94dce563d722e1b098684fbd7315d51
Author: Scott D Phillips
Date: Wed Mar 14 10:31:16 2018 -0700
anv: Use a separate pool for binding tables when soft pinning
Soft pinning lets us satisfy the binding table address
requirements without using both sides of a growing state_pool.
If you do use both sides of a state pool, then you need to read
the state pool's center_bo_offset (with the device mutex held) to
know the final offset of relocations that target the state pool
bo.
By having a separate pool for binding tables that only grows in
the forward direction, the center_bo_offset is always 0 and
relocations don't need an update pass to adjust relocations with
the mutex held.
v2: - don't introduce a separate state flag for separate binding tables (Jason)
- replace bo and map accessors with a single binding_table_pool accessor
(Jason)
v3: - assert bt_block->offset >= 0 for the separate binding table (Jason)
Reviewed-by: Jason Ekstrand
Reviewed-by: Jordan Justen
---
src/intel/vulkan/anv_batch_chain.c | 26 --
src/intel/vulkan/anv_device.c | 14 +-
src/intel/vulkan/anv_private.h | 24
3 files changed, 53 insertions(+), 11 deletions(-)
diff --git a/src/intel/vulkan/anv_batch_chain.c
b/src/intel/vulkan/anv_batch_chain.c
index ec8815a3c4..9e01a275a1 100644
--- a/src/intel/vulkan/anv_batch_chain.c
+++ b/src/intel/vulkan/anv_batch_chain.c
@@ -452,7 +452,7 @@ anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer)
{
struct anv_state *bt_block = u_vector_head(_buffer->bt_block_states);
return (struct anv_address) {
- .bo = _buffer->device->surface_state_pool.block_pool.bo,
+ .bo = _binding_table_pool(cmd_buffer->device)->block_pool.bo,
.offset = bt_block->offset,
};
}
@@ -619,7 +619,8 @@ struct anv_state
anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
uint32_t entries, uint32_t *state_offset)
{
- struct anv_state_pool *state_pool = _buffer->device->surface_state_pool;
+ struct anv_device *device = cmd_buffer->device;
+ struct anv_state_pool *state_pool = >surface_state_pool;
struct anv_state *bt_block = u_vector_head(_buffer->bt_block_states);
struct anv_state state;
@@ -629,12 +630,19 @@ anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer,
return (struct anv_state) { 0 };
state.offset = cmd_buffer->bt_next;
- state.map = state_pool->block_pool.map + bt_block->offset + state.offset;
+ state.map = anv_binding_table_pool(device)->block_pool.map +
+ bt_block->offset + state.offset;
cmd_buffer->bt_next += state.alloc_size;
- assert(bt_block->offset < 0);
- *state_offset = -bt_block->offset;
+ if (device->instance->physicalDevice.use_softpin) {
+ assert(bt_block->offset >= 0);
+ *state_offset = device->surface_state_pool.block_pool.start_address -
+ device->binding_table_pool.block_pool.start_address -
bt_block->offset;
+ } else {
+ assert(bt_block->offset < 0);
+ *state_offset = -bt_block->offset;
+ }
return state;
}
@@ -658,15 +666,13 @@ anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer,
VkResult
anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer)
{
- struct anv_state_pool *state_pool = _buffer->device->surface_state_pool;
-
struct anv_state *bt_block = u_vector_add(_buffer->bt_block_states);
if (bt_block == NULL) {
anv_batch_set_error(_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
}
- *bt_block = anv_state_pool_alloc_back(state_pool);
+ *bt_block = anv_binding_table_pool_alloc(cmd_buffer->device);
cmd_buffer->bt_next = 0;
return VK_SUCCESS;
@@ -740,7 +746,7 @@ anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer)
{
struct anv_state *bt_block;
u_vector_foreach(bt_block, _buffer->bt_block_states)
- anv_state_pool_free(_buffer->device->surface_state_pool, *bt_block);
+ anv_binding_table_pool_free(cmd_buffer->device, *bt_block);
u_vector_finish(_buffer->bt_block_states);
anv_reloc_list_finish(_buffer->surface_relocs,
_buffer->pool->alloc);
@@ -772,7 +778,7 @@ anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer)
while (u_vector_length(_buffer->bt_block_states) > 1) {
struct anv_state *bt_block =
u_vector_remove(_buffer->bt_block_states);
- anv_state_pool_free(_buffer->device->surface_state_pool, *bt_block);
+ anv_binding_table_pool_free(cmd_buffer->device, *bt_block);
}
assert(u_vector_length(_buffer-&
Mesa (master): anv: Soft-pin client-allocated memory
Module: Mesa Branch: master Commit: e7d0378bd958e56e25fe0f185d9403e766f0be32 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7d0378bd958e56e25fe0f185d9403e766f0be32 Author: Jason Ekstrand Date: Wed May 30 16:06:39 2018 -0700 anv: Soft-pin client-allocated memory Now that we've done all that refactoring, addresses are now being directly written into surface states by ISL and BLORP whenever a BO is pinned so there's really nothing to do besides enable it. Reviewed-by: Scott D Phillips --- src/intel/vulkan/anv_device.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 69de75c737..8b44b1bb1e 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -2051,6 +2051,9 @@ VkResult anv_AllocateMemory( bo_flags |= EXEC_OBJECT_ASYNC; } + if (pdevice->use_softpin) + bo_flags |= EXEC_OBJECT_PINNED; + const VkImportMemoryFdInfoKHR *fd_info = vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv/batch_chain: Simplify secondary batch return chaining
Module: Mesa
Branch: master
Commit: a0b133286a39fb9ac3a99d90edc0992339735765
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0b133286a39fb9ac3a99d90edc0992339735765
Author: Jason Ekstrand
Date: Wed May 30 22:07:30 2018 -0700
anv/batch_chain: Simplify secondary batch return chaining
Previously, we did this weird thing where we left space and an empty
relocation for use in a hypothetical MI_BATCH_BUFFER_START that would be
added to the secondary later. Then, when it came time to chain it into
the primary, we would back that out and emit an MI_BATCH_BUFFER_START.
This worked well but it was always a bit hacky, fragile and ugly. This
commit instead adds a helper for rewriting the MI_BATCH_BUFFER_START at
the end of an anv_batch_bo and we use that helper for both batch bo list
cloning and handling returns from secondaries. The new helper doesn't
actually modify the batch in any way but instead just adjusts the
relocation as needed.
Reviewed-by: Scott D Phillips
---
src/intel/vulkan/anv_batch_chain.c | 76 ++
1 file changed, 36 insertions(+), 40 deletions(-)
diff --git a/src/intel/vulkan/anv_batch_chain.c
b/src/intel/vulkan/anv_batch_chain.c
index 9f85f818c8..9d3884c8ac 100644
--- a/src/intel/vulkan/anv_batch_chain.c
+++ b/src/intel/vulkan/anv_batch_chain.c
@@ -416,6 +416,30 @@ anv_batch_bo_grow(struct anv_cmd_buffer *cmd_buffer,
struct anv_batch_bo *bbo,
}
static void
+anv_batch_bo_link(struct anv_cmd_buffer *cmd_buffer,
+ struct anv_batch_bo *prev_bbo,
+ struct anv_batch_bo *next_bbo,
+ uint32_t next_bbo_offset)
+{
+ MAYBE_UNUSED const uint32_t bb_start_offset =
+ prev_bbo->length - GEN8_MI_BATCH_BUFFER_START_length * 4;
+ MAYBE_UNUSED const uint32_t *bb_start = prev_bbo->bo.map + bb_start_offset;
+
+ /* Make sure we're looking at a MI_BATCH_BUFFER_START */
+ assert(((*bb_start >> 29) & 0x07) == 0);
+ assert(((*bb_start >> 23) & 0x3f) == 49);
+
+ uint32_t reloc_idx = prev_bbo->relocs.num_relocs - 1;
+ assert(prev_bbo->relocs.relocs[reloc_idx].offset == bb_start_offset + 4);
+
+ prev_bbo->relocs.reloc_bos[reloc_idx] = _bbo->bo;
+ prev_bbo->relocs.relocs[reloc_idx].delta = next_bbo_offset;
+
+ /* Use a bogus presumed offset to force a relocation */
+ prev_bbo->relocs.relocs[reloc_idx].presumed_offset = -1;
+}
+
+static void
anv_batch_bo_destroy(struct anv_batch_bo *bbo,
struct anv_cmd_buffer *cmd_buffer)
{
@@ -441,16 +465,8 @@ anv_batch_bo_list_clone(const struct list_head *list,
break;
list_addtail(_bbo->link, new_list);
- if (prev_bbo) {
- /* As we clone this list of batch_bo's, they chain one to the
- * other using MI_BATCH_BUFFER_START commands. We need to fix up
- * those relocations as we go. Fortunately, this is pretty easy
- * as it will always be the last relocation in the list.
- */
- uint32_t last_idx = prev_bbo->relocs.num_relocs - 1;
- assert(prev_bbo->relocs.reloc_bos[last_idx] == >bo);
- prev_bbo->relocs.reloc_bos[last_idx] = _bbo->bo;
- }
+ if (prev_bbo)
+ anv_batch_bo_link(cmd_buffer, prev_bbo, new_bbo, 0);
prev_bbo = new_bbo;
}
@@ -864,13 +880,13 @@ anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer)
VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT)) {
cmd_buffer->exec_mode = ANV_CMD_BUFFER_EXEC_MODE_CHAIN;
- /* When we chain, we need to add an MI_BATCH_BUFFER_START command
- * with its relocation. In order to handle this we'll increment here
- * so we can unconditionally decrement right before adding the
- * MI_BATCH_BUFFER_START command.
+ /* In order to chain, we need this command buffer to contain an
+ * MI_BATCH_BUFFER_START which will jump back to the calling batch.
+ * It doesn't matter where it points now so long as has a valid
+ * relocation. We'll adjust it later as part of the chaining
+ * process.
*/
- batch_bo->relocs.num_relocs++;
- cmd_buffer->batch.next += GEN8_MI_BATCH_BUFFER_START_length * 4;
+ emit_batch_buffer_start(cmd_buffer, _bo->bo, 0);
} else {
cmd_buffer->exec_mode = ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN;
}
@@ -921,33 +937,13 @@ anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary,
struct anv_batch_bo *this_bbo = anv_cmd_buffer_current_batch_bo(primary);
assert(primary->batch.start == this_bbo->bo.map);
uint32_t offset = primary->batch.next - primary->batch.start;
- const uint32_t inst_size = GEN8_MI_BATCH_BUFFER_START_length * 4;
- /* Roll back the previous MI_BATCH_BUFFER_START and its relocation so we
- * can emit a new command and relocation for th
Mesa (master): anv/batch_chain: Call batch_bo_finish at the end of end_batch_buffer
Module: Mesa
Branch: master
Commit: 4f20c665b4dc48bf11b00f9c520ec249f5eecb1f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f20c665b4dc48bf11b00f9c520ec249f5eecb1f
Author: Jason Ekstrand
Date: Wed May 30 22:01:46 2018 -0700
anv/batch_chain: Call batch_bo_finish at the end of end_batch_buffer
The only reason we were calling it in the middle was that one of the
cases for figuring out the secondary command buffer execution type
wanted batch_bo->length which gets set by batch_bo_finish. It's easy
enough to recalculate and now batch_bo_finish is called in a sensible
location.
Reviewed-by: Scott D Phillips
---
src/intel/vulkan/anv_batch_chain.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/intel/vulkan/anv_batch_chain.c
b/src/intel/vulkan/anv_batch_chain.c
index fd738d0a03..9f85f818c8 100644
--- a/src/intel/vulkan/anv_batch_chain.c
+++ b/src/intel/vulkan/anv_batch_chain.c
@@ -843,20 +843,18 @@ anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer)
anv_batch_emit(_buffer->batch, GEN8_MI_NOOP, noop);
cmd_buffer->exec_mode = ANV_CMD_BUFFER_EXEC_MODE_PRIMARY;
- }
-
- anv_batch_bo_finish(batch_bo, _buffer->batch);
-
- if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY) {
+ } else {
+ assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY);
/* If this is a secondary command buffer, we need to determine the
* mode in which it will be executed with vkExecuteCommands. We
* determine this statically here so that this stays in sync with the
* actual ExecuteCommands implementation.
*/
+ const uint32_t length = cmd_buffer->batch.next - cmd_buffer->batch.start;
if (!cmd_buffer->device->can_chain_batches) {
cmd_buffer->exec_mode = ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT;
} else if ((cmd_buffer->batch_bos.next == cmd_buffer->batch_bos.prev) &&
- (batch_bo->length < ANV_CMD_BUFFER_BATCH_SIZE / 2)) {
+ (length < ANV_CMD_BUFFER_BATCH_SIZE / 2)) {
/* If the secondary has exactly one batch buffer in its list *and*
* that batch buffer is less than half of the maximum size, we're
* probably better of simply copying it into our batch.
@@ -877,6 +875,8 @@ anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer)
cmd_buffer->exec_mode = ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN;
}
}
+
+ anv_batch_bo_finish(batch_bo, _buffer->batch);
}
static VkResult
___
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mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv/allocator: Set the BO flags in bo_cache_alloc/import
Module: Mesa
Branch: master
Commit: b0d50247a7049350ef30adcefc609039ce86beee
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0d50247a7049350ef30adcefc609039ce86beee
Author: Jason Ekstrand
Date: Wed May 30 15:34:25 2018 -0700
anv/allocator: Set the BO flags in bo_cache_alloc/import
It's safer to set them there because we have the opportunity to properly
handle combining flags if a BO is imported more than once.
Reviewed-by: Scott D Phillips
---
src/intel/vulkan/anv_allocator.c | 30 --
src/intel/vulkan/anv_device.c| 38 --
src/intel/vulkan/anv_intel.c | 9 +
src/intel/vulkan/anv_private.h | 6 --
src/intel/vulkan/anv_queue.c | 5 +++--
5 files changed, 60 insertions(+), 28 deletions(-)
diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index a597280930..697da5f8c1 100644
--- a/src/intel/vulkan/anv_allocator.c
+++ b/src/intel/vulkan/anv_allocator.c
@@ -1237,11 +1237,19 @@ anv_bo_cache_lookup(struct anv_bo_cache *cache,
uint32_t gem_handle)
return bo ? >bo : NULL;
}
+#define ANV_BO_CACHE_SUPPORTED_FLAGS \
+ (EXEC_OBJECT_WRITE | \
+EXEC_OBJECT_ASYNC | \
+EXEC_OBJECT_SUPPORTS_48B_ADDRESS)
+
VkResult
anv_bo_cache_alloc(struct anv_device *device,
struct anv_bo_cache *cache,
- uint64_t size, struct anv_bo **bo_out)
+ uint64_t size, uint64_t bo_flags,
+ struct anv_bo **bo_out)
{
+ assert(bo_flags == (bo_flags & ANV_BO_CACHE_SUPPORTED_FLAGS));
+
struct anv_cached_bo *bo =
vk_alloc(>alloc, sizeof(struct anv_cached_bo), 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
@@ -1259,6 +1267,8 @@ anv_bo_cache_alloc(struct anv_device *device,
return result;
}
+ bo->bo.flags = bo_flags;
+
assert(bo->bo.gem_handle);
pthread_mutex_lock(>mutex);
@@ -1276,8 +1286,11 @@ anv_bo_cache_alloc(struct anv_device *device,
VkResult
anv_bo_cache_import(struct anv_device *device,
struct anv_bo_cache *cache,
-int fd, struct anv_bo **bo_out)
+int fd, uint64_t bo_flags,
+struct anv_bo **bo_out)
{
+ assert(bo_flags == (bo_flags & ANV_BO_CACHE_SUPPORTED_FLAGS));
+
pthread_mutex_lock(>mutex);
uint32_t gem_handle = anv_gem_fd_to_handle(device, fd);
@@ -1288,6 +1301,18 @@ anv_bo_cache_import(struct anv_device *device,
struct anv_cached_bo *bo = anv_bo_cache_lookup_locked(cache, gem_handle);
if (bo) {
+ /* We have to be careful how we combine flags so that it makes sense.
+ * Really, though, if we get to this case and it actually matters, the
+ * client has imported a BO twice in different ways and they get what
+ * they have coming.
+ */
+ uint64_t new_flags = 0;
+ new_flags |= (bo->bo.flags | bo_flags) & EXEC_OBJECT_WRITE;
+ new_flags |= (bo->bo.flags & bo_flags) & EXEC_OBJECT_ASYNC;
+ new_flags |= (bo->bo.flags & bo_flags) &
EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+
+ bo->bo.flags = new_flags;
+
__sync_fetch_and_add(>refcount, 1);
} else {
off_t size = lseek(fd, 0, SEEK_END);
@@ -1308,6 +1333,7 @@ anv_bo_cache_import(struct anv_device *device,
bo->refcount = 1;
anv_bo_init(>bo, gem_handle, size);
+ bo->bo.flags = bo_flags;
_mesa_hash_table_insert(cache->bo_map, (void *)(uintptr_t)gem_handle,
bo);
}
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 067f4369b7..69de75c737 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -2033,6 +2033,24 @@ VkResult anv_AllocateMemory(
mem->map = NULL;
mem->map_size = 0;
+ uint64_t bo_flags = 0;
+
+ assert(mem->type->heapIndex < pdevice->memory.heap_count);
+ if (pdevice->memory.heaps[mem->type->heapIndex].supports_48bit_addresses)
+ bo_flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+
+ const struct wsi_memory_allocate_info *wsi_info =
+ vk_find_struct_const(pAllocateInfo->pNext,
WSI_MEMORY_ALLOCATE_INFO_MESA);
+ if (wsi_info && wsi_info->implicit_sync) {
+ /* We need to set the WRITE flag on window system buffers so that GEM
+ * will know we're writing to them and synchronize uses on other rings
+ * (eg if the display server uses the blitter ring).
+ */
+ bo_flags |= EXEC_OBJECT_WRITE;
+ } else if (pdevice->has_exec_async) {
+ bo_flags |= EXEC_OBJECT_ASYNC;
+ }
+
const VkImportMemoryFdInfoKHR *fd_info =
vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
@@ -2047,7 +2065,7 @@ VkResult anv_AllocateMemory(
VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
result = anv_bo_cache_import(device, >bo_cache,
-
Mesa (master): anv: Soft-pin everything else
Module: Mesa
Branch: master
Commit: 4affeba1e9eb426a1ba13a3e8ced4673c4bb9b34
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4affeba1e9eb426a1ba13a3e8ced4673c4bb9b34
Author: Scott D Phillips
Date: Wed May 30 20:16:30 2018 -0700
anv: Soft-pin everything else
v2 (Jason Ekstrand):
- Break up Scott's mega-patch
Reviewed-by: Jason Ekstrand
Reviewed-by: Scott D Phillips
---
src/intel/vulkan/anv_allocator.c | 9 -
src/intel/vulkan/anv_device.c| 7 +++
src/intel/vulkan/genX_query.c| 6 ++
3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index 97fa8c9703..ab01d46cbe 100644
--- a/src/intel/vulkan/anv_allocator.c
+++ b/src/intel/vulkan/anv_allocator.c
@@ -1077,8 +1077,10 @@ anv_scratch_pool_finish(struct anv_device *device,
struct anv_scratch_pool *pool
for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
for (unsigned i = 0; i < 16; i++) {
struct anv_scratch_bo *bo = >bos[i][s];
- if (bo->exists > 0)
+ if (bo->exists > 0) {
+anv_vma_free(device, >bo);
anv_gem_close(device, bo->bo.gem_handle);
+ }
}
}
}
@@ -1176,6 +1178,11 @@ anv_scratch_pool_alloc(struct anv_device *device, struct
anv_scratch_pool *pool,
if (device->instance->physicalDevice.has_exec_async)
bo->bo.flags |= EXEC_OBJECT_ASYNC;
+ if (device->instance->physicalDevice.use_softpin)
+ bo->bo.flags |= EXEC_OBJECT_PINNED;
+
+ anv_vma_alloc(device, >bo);
+
/* Set the exists last because it may be read by other threads */
__sync_synchronize();
bo->exists = true;
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 1a2bde2df4..b02e1a2749 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1658,6 +1658,12 @@ VkResult anv_CreateDevice(
if (result != VK_SUCCESS)
goto fail_binding_table_pool;
+ if (physical_device->use_softpin)
+ device->workaround_bo.flags |= EXEC_OBJECT_PINNED;
+
+ if (!anv_vma_alloc(device, >workaround_bo))
+ goto fail_workaround_bo;
+
anv_device_init_trivial_batch(device);
if (device->info.gen >= 10)
@@ -1756,6 +1762,7 @@ void anv_DestroyDevice(
anv_scratch_pool_finish(device, >scratch_pool);
anv_gem_munmap(device->workaround_bo.map, device->workaround_bo.size);
+ anv_vma_free(device, >workaround_bo);
anv_gem_close(device, device->workaround_bo.gem_handle);
anv_vma_free(device, >trivial_batch_bo);
diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c
index de409be04e..e35e9b8584 100644
--- a/src/intel/vulkan/genX_query.c
+++ b/src/intel/vulkan/genX_query.c
@@ -94,9 +94,14 @@ VkResult genX(CreateQueryPool)(
if (pdevice->supports_48bit_addresses)
pool->bo.flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ if (pdevice->use_softpin)
+ pool->bo.flags |= EXEC_OBJECT_PINNED;
+
if (pdevice->has_exec_async)
pool->bo.flags |= EXEC_OBJECT_ASYNC;
+ anv_vma_alloc(device, >bo);
+
/* For query pools, we set the caching mode to I915_CACHING_CACHED. On LLC
* platforms, this does nothing. On non-LLC platforms, this means snooping
* which comes at a slight cost. However, the buffers aren't big, won't be
@@ -129,6 +134,7 @@ void genX(DestroyQueryPool)(
return;
anv_gem_munmap(pool->bo.map, pool->bo.size);
+ anv_vma_free(device, >bo);
anv_gem_close(device, pool->bo.gem_handle);
vk_free2(>alloc, pAllocator, pool);
}
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Mesa (master): anv/allocator: Support softpin in the BO cache
Module: Mesa
Branch: master
Commit: caf41c78cad7cbbc415a2b1f20a5997501e89729
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=caf41c78cad7cbbc415a2b1f20a5997501e89729
Author: Jason Ekstrand
Date: Wed May 30 15:25:04 2018 -0700
anv/allocator: Support softpin in the BO cache
Reviewed-by: Scott D Phillips
---
src/intel/vulkan/anv_allocator.c | 51 +++-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index 697da5f8c1..117851f759 100644
--- a/src/intel/vulkan/anv_allocator.c
+++ b/src/intel/vulkan/anv_allocator.c
@@ -1240,7 +1240,8 @@ anv_bo_cache_lookup(struct anv_bo_cache *cache, uint32_t
gem_handle)
#define ANV_BO_CACHE_SUPPORTED_FLAGS \
(EXEC_OBJECT_WRITE | \
EXEC_OBJECT_ASYNC | \
-EXEC_OBJECT_SUPPORTS_48B_ADDRESS)
+EXEC_OBJECT_SUPPORTS_48B_ADDRESS | \
+EXEC_OBJECT_PINNED)
VkResult
anv_bo_cache_alloc(struct anv_device *device,
@@ -1269,6 +1270,14 @@ anv_bo_cache_alloc(struct anv_device *device,
bo->bo.flags = bo_flags;
+ if (!anv_vma_alloc(device, >bo)) {
+ anv_gem_close(device, bo->bo.gem_handle);
+ vk_free(>alloc, bo);
+ return vk_errorf(device->instance, NULL,
+ VK_ERROR_OUT_OF_DEVICE_MEMORY,
+ "failed to allocate virtual address for BO");
+ }
+
assert(bo->bo.gem_handle);
pthread_mutex_lock(>mutex);
@@ -1310,6 +1319,35 @@ anv_bo_cache_import(struct anv_device *device,
new_flags |= (bo->bo.flags | bo_flags) & EXEC_OBJECT_WRITE;
new_flags |= (bo->bo.flags & bo_flags) & EXEC_OBJECT_ASYNC;
new_flags |= (bo->bo.flags & bo_flags) &
EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ new_flags |= (bo->bo.flags | bo_flags) & EXEC_OBJECT_PINNED;
+
+ /* It's theoretically possible for a BO to get imported such that it's
+ * both pinned and not pinned. The only way this can happen is if it
+ * gets imported as both a semaphore and a memory object and that would
+ * be an application error. Just fail out in that case.
+ */
+ if ((bo->bo.flags & EXEC_OBJECT_PINNED) !=
+ (bo_flags & EXEC_OBJECT_PINNED)) {
+ pthread_mutex_unlock(>mutex);
+ return vk_errorf(device->instance, NULL,
+ VK_ERROR_INVALID_EXTERNAL_HANDLE,
+ "The same BO was imported two different ways");
+ }
+
+ /* It's also theoretically possible that someone could export a BO from
+ * one heap and import it into another or to import the same BO into two
+ * different heaps. If this happens, we could potentially end up both
+ * allowing and disallowing 48-bit addresses. There's not much we can
+ * do about it if we're pinning so we just throw an error and hope no
+ * app is actually that stupid.
+ */
+ if ((new_flags & EXEC_OBJECT_PINNED) &&
+ (bo->bo.flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) !=
+ (bo_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS)) {
+ return vk_errorf(device->instance, NULL,
+ VK_ERROR_INVALID_EXTERNAL_HANDLE,
+ "The same BO was imported on two different heaps");
+ }
bo->bo.flags = new_flags;
@@ -1335,6 +1373,15 @@ anv_bo_cache_import(struct anv_device *device,
anv_bo_init(>bo, gem_handle, size);
bo->bo.flags = bo_flags;
+ if (!anv_vma_alloc(device, >bo)) {
+ anv_gem_close(device, bo->bo.gem_handle);
+ pthread_mutex_unlock(>mutex);
+ vk_free(>alloc, bo);
+ return vk_errorf(device->instance, NULL,
+ VK_ERROR_OUT_OF_DEVICE_MEMORY,
+ "failed to allocate virtual address for BO");
+ }
+
_mesa_hash_table_insert(cache->bo_map, (void *)(uintptr_t)gem_handle,
bo);
}
@@ -1416,6 +1463,8 @@ anv_bo_cache_release(struct anv_device *device,
if (bo->bo.map)
anv_gem_munmap(bo->bo.map, bo->bo.size);
+ anv_vma_free(device, >bo);
+
anv_gem_close(device, bo->bo.gem_handle);
/* Don't unlock until we've actually closed the BO. The whole point of
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Mesa (master): compiler/spirv: reject invalid shader code properly
Module: Mesa
Branch: master
Commit: 53719f818cf320add55dc7ed3612725c2f6128ce
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=53719f818cf320add55dc7ed3612725c2f6128ce
Author: Martin Pelikán
Date: Fri Jun 1 14:27:24 2018 +0200
compiler/spirv: reject invalid shader code properly
After bebe3d626e5, b->fail_jump is prepared after vtn_create_builder
which can longjmp(3) to it through its vtx_assert()s. This corrupts
the stack and creates confusing core dumps, so we need to avoid it.
While there, I decided to print the offending values for debugability.
Reviewed-by: Jason Ekstrand
---
src/compiler/spirv/spirv_to_nir.c | 39 ++-
src/compiler/spirv/vtn_private.h | 4
2 files changed, 38 insertions(+), 5 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 78437428aa..59a89df201 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -130,6 +130,18 @@ _vtn_warn(struct vtn_builder *b, const char *file,
unsigned line,
}
void
+_vtn_err(struct vtn_builder *b, const char *file, unsigned line,
+ const char *fmt, ...)
+{
+ va_list args;
+
+ va_start(args, fmt);
+ vtn_log_err(b, NIR_SPIRV_DEBUG_LEVEL_ERROR, "SPIR-V ERROR:\n",
+ file, line, fmt, args);
+ va_end(args);
+}
+
+void
_vtn_fail(struct vtn_builder *b, const char *file, unsigned line,
const char *fmt, ...)
{
@@ -4011,19 +4023,36 @@ vtn_create_builder(const uint32_t *words, size_t
word_count,
b->entry_point_name = entry_point_name;
b->options = options;
- /* Handle the SPIR-V header (first 4 dwords) */
- vtn_assert(word_count > 5);
+ /*
+* Handle the SPIR-V header (first 5 dwords).
+* Can't use vtx_assert() as the setjmp(3) target isn't initialized yet.
+*/
+ if (word_count <= 5)
+ goto fail;
+
+ if (words[0] != SpvMagicNumber) {
+ vtn_err("words[0] was 0x%x, want 0x%x", words[0], SpvMagicNumber);
+ goto fail;
+ }
+ if (words[1] < 0x1) {
+ vtn_err("words[1] was 0x%x, want >= 0x1", words[1]);
+ goto fail;
+ }
- vtn_assert(words[0] == SpvMagicNumber);
- vtn_assert(words[1] >= 0x1);
/* words[2] == generator magic */
unsigned value_id_bound = words[3];
- vtn_assert(words[4] == 0);
+ if (words[4] != 0) {
+ vtn_err("words[4] was %u, want 0", words[4]);
+ goto fail;
+ }
b->value_id_bound = value_id_bound;
b->values = rzalloc_array(b, struct vtn_value, value_id_bound);
return b;
+ fail:
+ ralloc_free(b);
+ return NULL;
}
nir_function *
diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index b501bbf9b4..3146d8eeb5 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -51,6 +51,10 @@ void _vtn_warn(struct vtn_builder *b, const char *file,
unsigned line,
const char *fmt, ...) PRINTFLIKE(4, 5);
#define vtn_warn(...) _vtn_warn(b, __FILE__, __LINE__, __VA_ARGS__)
+void _vtn_err(struct vtn_builder *b, const char *file, unsigned line,
+ const char *fmt, ...) PRINTFLIKE(4, 5);
+#define vtn_err(...) _vtn_err(b, __FILE__, __LINE__, __VA_ARGS__)
+
/** Fail SPIR-V parsing
*
* This function logs an error and then bails out of the shader compile using
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Mesa (master): anv/blorp: Write relocated values into surface states
Module: Mesa
Branch: master
Commit: 29a139b308d51560e0f1d5862fa228023c9a5a04
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=29a139b308d51560e0f1d5862fa228023c9a5a04
Author: Scott D Phillips
Date: Wed May 30 20:24:15 2018 -0700
anv/blorp: Write relocated values into surface states
v2 (Jason Ekstrand):
- Split the blorp bit into it's own patch and re-order a bit
- Use anv_address helpers
Reviewed-by: Jason Ekstrand
---
src/intel/vulkan/anv_batch_chain.c | 16
src/intel/vulkan/anv_private.h | 16
src/intel/vulkan/genX_blorp_exec.c | 6 ++
3 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/src/intel/vulkan/anv_batch_chain.c
b/src/intel/vulkan/anv_batch_chain.c
index a1fb8bf731..ec8815a3c4 100644
--- a/src/intel/vulkan/anv_batch_chain.c
+++ b/src/intel/vulkan/anv_batch_chain.c
@@ -1106,22 +1106,6 @@ anv_cmd_buffer_process_relocs(struct anv_cmd_buffer
*cmd_buffer,
}
static void
-write_reloc(const struct anv_device *device, void *p, uint64_t v, bool flush)
-{
- unsigned reloc_size = 0;
- if (device->info.gen >= 8) {
- reloc_size = sizeof(uint64_t);
- *(uint64_t *)p = gen_canonical_address(v);
- } else {
- reloc_size = sizeof(uint32_t);
- *(uint32_t *)p = v;
- }
-
- if (flush && !device->info.has_llc)
- gen_flush_range(p, reloc_size);
-}
-
-static void
adjust_relocations_from_state_pool(struct anv_state_pool *pool,
struct anv_reloc_list *relocs,
uint32_t last_pool_center_bo_offset)
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 5e07617054..67a12c7206 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1144,6 +1144,22 @@ anv_address_add(struct anv_address addr, uint64_t offset)
return addr;
}
+static inline void
+write_reloc(const struct anv_device *device, void *p, uint64_t v, bool flush)
+{
+ unsigned reloc_size = 0;
+ if (device->info.gen >= 8) {
+ reloc_size = sizeof(uint64_t);
+ *(uint64_t *)p = gen_canonical_address(v);
+ } else {
+ reloc_size = sizeof(uint32_t);
+ *(uint32_t *)p = v;
+ }
+
+ if (flush && !device->info.has_llc)
+ gen_flush_range(p, reloc_size);
+}
+
static inline uint64_t
_anv_combine_address(struct anv_batch *batch, void *location,
const struct anv_address address, uint32_t delta)
diff --git a/src/intel/vulkan/genX_blorp_exec.c
b/src/intel/vulkan/genX_blorp_exec.c
index 9023269d61..ecca3928de 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -62,6 +62,12 @@ blorp_surface_reloc(struct blorp_batch *batch, uint32_t
ss_offset,
ss_offset, address.buffer, address.offset + delta);
if (result != VK_SUCCESS)
anv_batch_set_error(_buffer->batch, result);
+
+ void *dest = cmd_buffer->device->surface_state_pool.block_pool.map +
+ ss_offset;
+ uint64_t val = ((struct anv_bo*)address.buffer)->offset + address.offset +
+ delta;
+ write_reloc(cmd_buffer->device, dest, val, false);
}
#if GEN_GEN >= 7 && GEN_GEN < 10
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Mesa (master): intel/common: Add an address de-canonicalization helper
Module: Mesa
Branch: master
Commit: 6e4672f881bbc73c56b0d81dfea93d09f8d39eec
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e4672f881bbc73c56b0d81dfea93d09f8d39eec
Author: Jason Ekstrand
Date: Wed May 30 20:00:37 2018 -0700
intel/common: Add an address de-canonicalization helper
Reviewed-by: Kenneth Graunke
Reviewed-by: Scott D Phillips
---
src/intel/common/gen_gem.h | 12
1 file changed, 12 insertions(+)
diff --git a/src/intel/common/gen_gem.h b/src/intel/common/gen_gem.h
index 842a455e05..7dd9ae6d54 100644
--- a/src/intel/common/gen_gem.h
+++ b/src/intel/common/gen_gem.h
@@ -40,4 +40,16 @@ gen_canonical_address(uint64_t v)
return (int64_t)(v << shift) >> shift;
}
+/**
+ * This returns a 48-bit address with the high 16 bits zeroed.
+ *
+ * It's the opposite of gen_canonicalize_address.
+ */
+static inline uint64_t
+gen_48b_address(uint64_t v)
+{
+ const int shift = 63 - 47;
+ return (uint64_t)(v << shift) >> shift;
+}
+
#endif /* GEN_GEM_H */
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Mesa (master): anv/cmd_buffer: Rework surface relocation helpers
Module: Mesa
Branch: master
Commit: 1f2328c3b703c846749c2bef165618f068fa18ae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f2328c3b703c846749c2bef165618f068fa18ae
Author: Jason Ekstrand
Date: Wed May 30 18:30:50 2018 -0700
anv/cmd_buffer: Rework surface relocation helpers
This commit renames add_surface_state_reloc to add_surface_reloc and
makes it takes an address. We also rename add_image_view_relocs to
add_surface_state_relocs because it takes an anv_surface_state and
doesn't really care about the image view anymore.
Reviewed-by: Scott D Phillips
---
src/intel/vulkan/genX_cmd_buffer.c | 44 --
1 file changed, 19 insertions(+), 25 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 65aea3f4ae..97b0f86b99 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -165,28 +165,27 @@ genX(cmd_buffer_emit_state_base_address)(struct
anv_cmd_buffer *cmd_buffer)
}
static void
-add_surface_state_reloc(struct anv_cmd_buffer *cmd_buffer,
-struct anv_state state,
-struct anv_bo *bo, uint32_t offset)
+add_surface_reloc(struct anv_cmd_buffer *cmd_buffer,
+ struct anv_state state, struct anv_address addr)
{
const struct isl_device *isl_dev = _buffer->device->isl_dev;
VkResult result =
anv_reloc_list_add(_buffer->surface_relocs, _buffer->pool->alloc,
- state.offset + isl_dev->ss.addr_offset, bo, offset);
+ state.offset + isl_dev->ss.addr_offset,
+ addr.bo, addr.offset);
if (result != VK_SUCCESS)
anv_batch_set_error(_buffer->batch, result);
}
static void
-add_image_view_relocs(struct anv_cmd_buffer *cmd_buffer,
- struct anv_surface_state state)
+add_surface_state_relocs(struct anv_cmd_buffer *cmd_buffer,
+ struct anv_surface_state state)
{
const struct isl_device *isl_dev = _buffer->device->isl_dev;
assert(!anv_address_is_null(state.address));
- add_surface_state_reloc(cmd_buffer, state.state,
- state.address.bo, state.address.offset);
+ add_surface_reloc(cmd_buffer, state.state, state.address);
if (!anv_address_is_null(state.aux_address)) {
VkResult result =
@@ -1268,7 +1267,7 @@ genX(cmd_buffer_setup_attachments)(struct anv_cmd_buffer
*cmd_buffer,
>attachments[i].color,
NULL);
-add_image_view_relocs(cmd_buffer, state->attachments[i].color);
+add_surface_state_relocs(cmd_buffer, state->attachments[i].color);
} else {
depth_stencil_attachment_compute_aux_usage(cmd_buffer->device,
state, i,
@@ -1287,7 +1286,7 @@ genX(cmd_buffer_setup_attachments)(struct anv_cmd_buffer
*cmd_buffer,
>attachments[i].input,
NULL);
-add_image_view_relocs(cmd_buffer, state->attachments[i].input);
+add_surface_state_relocs(cmd_buffer, state->attachments[i].input);
}
}
}
@@ -1968,9 +1967,6 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
if (stage == MESA_SHADER_COMPUTE &&
get_cs_prog_data(pipeline)->uses_num_work_groups) {
- struct anv_bo *bo = cmd_buffer->state.compute.num_workgroups.bo;
- uint32_t bo_offset = cmd_buffer->state.compute.num_workgroups.offset;
-
struct anv_state surface_state;
surface_state =
anv_cmd_buffer_alloc_surface_state(cmd_buffer);
@@ -1983,7 +1979,8 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
12, 1);
bt_map[0] = surface_state.offset + state_offset;
- add_surface_state_reloc(cmd_buffer, surface_state, bo, bo_offset);
+ add_surface_reloc(cmd_buffer, surface_state,
+cmd_buffer->state.compute.num_workgroups);
}
if (map->surface_count == 0)
@@ -2047,7 +2044,7 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
desc->image_view->planes[binding->plane].optimal_sampler_surface_state;
surface_state = sstate.state;
assert(surface_state.alloc_size);
- add_image_view_relocs(cmd_buffer, sstate);
+ add_surface_state_relocs(cmd_buffer, sstate);
break;
}
case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
@@ -2062,7 +2059,7 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
desc->image_view->planes[binding->plane].optimal_sampler_surface_state;
surface_state = sstate.state;
assert(surface_state.alloc_size);
-add_ima
Mesa (master): anv: Add some anv_address helpers
Module: Mesa
Branch: master
Commit: 94081ffc80cc993c1c76cf427d8efd37e68de6f8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=94081ffc80cc993c1c76cf427d8efd37e68de6f8
Author: Jason Ekstrand
Date: Wed May 30 18:16:50 2018 -0700
anv: Add some anv_address helpers
Reviewed-by: Scott D Phillips
---
src/intel/vulkan/anv_private.h | 24
1 file changed, 24 insertions(+)
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 60444d99a4..bcd2197e7f 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1120,6 +1120,30 @@ struct anv_address {
uint32_t offset;
};
+#define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
+
+static inline bool
+anv_address_is_null(struct anv_address addr)
+{
+ return addr.bo == NULL && addr.offset == 0;
+}
+
+static inline uint64_t
+anv_address_physical(struct anv_address addr)
+{
+ if (addr.bo && (addr.bo->flags & EXEC_OBJECT_PINNED))
+ return gen_canonical_address(addr.bo->offset + addr.offset);
+ else
+ return gen_canonical_address(addr.offset);
+}
+
+static inline struct anv_address
+anv_address_add(struct anv_address addr, uint64_t offset)
+{
+ addr.offset += offset;
+ return addr;
+}
+
static inline uint64_t
_anv_combine_address(struct anv_batch *batch, void *location,
const struct anv_address address, uint32_t delta)
___
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mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv: Use an address for each anv_image plane
Module: Mesa
Branch: master
Commit: bf34ef16ac7c5b59df936dc7a5932c9f518260d9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf34ef16ac7c5b59df936dc7a5932c9f518260d9
Author: Jason Ekstrand
Date: Wed May 30 18:55:00 2018 -0700
anv: Use an address for each anv_image plane
This is better than having BO and offset fields.
Reviewed-by: Scott D Phillips
---
src/intel/vulkan/anv_blorp.c | 12 ++--
src/intel/vulkan/anv_image.c | 26 --
src/intel/vulkan/anv_intel.c | 6 --
src/intel/vulkan/anv_private.h | 10 +++---
src/intel/vulkan/genX_cmd_buffer.c | 13 +++--
5 files changed, 32 insertions(+), 35 deletions(-)
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 359ebfb3ca..5373faaa68 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -207,8 +207,8 @@ get_blorp_surf_for_anv_image(const struct anv_device
*device,
*blorp_surf = (struct blorp_surf) {
.surf = >isl,
.addr = {
- .buffer = image->planes[plane].bo,
- .offset = image->planes[plane].bo_offset + surface->offset,
+ .buffer = image->planes[plane].address.bo,
+ .offset = image->planes[plane].address.offset + surface->offset,
.mocs = device->default_mocs,
},
};
@@ -217,8 +217,8 @@ get_blorp_surf_for_anv_image(const struct anv_device
*device,
const struct anv_surface *aux_surface =
>planes[plane].aux_surface;
blorp_surf->aux_surf = _surface->isl,
blorp_surf->aux_addr = (struct blorp_address) {
- .buffer = image->planes[plane].bo,
- .offset = image->planes[plane].bo_offset + aux_surface->offset,
+ .buffer = image->planes[plane].address.bo,
+ .offset = image->planes[plane].address.offset + aux_surface->offset,
.mocs = device->default_mocs,
};
blorp_surf->aux_usage = aux_usage;
@@ -1411,8 +1411,8 @@ anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer,
struct blorp_surf shadow_surf = {
.surf = >planes[0].shadow_surface.isl,
.addr = {
- .buffer = image->planes[0].bo,
- .offset = image->planes[0].bo_offset +
+ .buffer = image->planes[0].address.bo,
+ .offset = image->planes[0].address.offset +
image->planes[0].shadow_surface.offset,
.mocs = cmd_buffer->device->default_mocs,
},
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index bbb740e2c6..c62bf7ae2b 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -658,8 +658,9 @@ anv_DestroyImage(VkDevice _device, VkImage _image,
for (uint32_t p = 0; p < image->n_planes; ++p) {
if (image->planes[p].bo_is_owned) {
- assert(image->planes[p].bo != NULL);
- anv_bo_cache_release(device, >bo_cache, image->planes[p].bo);
+ assert(image->planes[p].address.bo != NULL);
+ anv_bo_cache_release(device, >bo_cache,
+ image->planes[p].address.bo);
}
}
@@ -675,13 +676,14 @@ static void anv_image_bind_memory_plane(struct anv_device
*device,
assert(!image->planes[plane].bo_is_owned);
if (!memory) {
- image->planes[plane].bo = NULL;
- image->planes[plane].bo_offset = 0;
+ image->planes[plane].address = ANV_NULL_ADDRESS;
return;
}
- image->planes[plane].bo = memory->bo;
- image->planes[plane].bo_offset = memory_offset;
+ image->planes[plane].address = (struct anv_address) {
+ .bo = memory->bo,
+ .offset = memory_offset,
+ };
}
VkResult anv_BindImageMemory(
@@ -1067,10 +1069,8 @@ anv_image_fill_surface_state(struct anv_device *device,
if (!clear_color)
clear_color = _clear_color;
- const struct anv_address address = {
- .bo = image->planes[plane].bo,
- .offset = image->planes[plane].bo_offset + surface->offset,
- };
+ const struct anv_address address =
+ anv_address_add(image->planes[plane].address, surface->offset);
if (view_usage == ISL_SURF_USAGE_STORAGE_BIT &&
!(flags & ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY) &&
@@ -1159,10 +1159,8 @@ anv_image_fill_surface_state(struct anv_device *device,
struct anv_address aux_address = ANV_NULL_ADDRESS;
if (aux_usage != ISL_AUX_USAGE_NONE) {
- aux_address = (struct anv_address) {
-.bo = image->planes[plane].bo,
-.offset = image->planes[plane].bo_offset + aux_surface->offset,
- };
+ aux_address = anv_address_add(image->planes[plane].address,
+ aux_surface->offset);
}
state_inout->aux_address = aux_address;
diff --git a/src/intel/vulkan/anv_intel.c b/src/intel/vulkan/anv_int
Mesa (master): anv: Add vma_heap allocators in anv_device
Module: Mesa
Branch: master
Commit: aaea46242d651a1b03f7292ac89a68f8a9086692
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aaea46242d651a1b03f7292ac89a68f8a9086692
Author: Scott D Phillips
Date: Wed Mar 7 09:18:37 2018 -0800
anv: Add vma_heap allocators in anv_device
These will be used to assign virtual addresses to soft pinned
buffers in a later patch.
Two allocators are added for separate 'low' and 'high' virtual
memory areas. Another alternative would have been to add a
double-sided allocator, which wasn't done here just because it
didn't appear to give any code complexity advantages.
v2 (Scott Phillips):
- rename has_exec_softpin to use_softpin (Jason)
- Only remove bottom one page and top 4 GiB from virt (Jason)
- refer to comment in anv_allocator about state address + size
overflowing 48 bits (Jason)
- Mention hi/lo allocators vs double-sided allocator in
commit message (Chris)
- assign state pool memory ranges statically (Jason)
v3 (Jason Ekstrand):
- Use (LOW|HIGH)_HEAP_(MIN|MAX)_ADDRESS rather than (1 << 31) for
determining which heap to use in anv_vma_free
- Only return de-canonicalized addresses to the heap
Reviewed-by: Jordan Justen
Reviewed-by: Jason Ekstrand
Reviewed-by: Scott D Phillips
---
src/intel/vulkan/anv_device.c | 84 ++
src/intel/vulkan/anv_private.h | 60 ++
2 files changed, 144 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 374fc16c4c..276e32bddd 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -374,6 +374,9 @@ anv_physical_device_init(struct anv_physical_device *device,
anv_gem_supports_syncobj_wait(fd);
device->has_context_priority = anv_gem_has_context_priority(fd);
+ device->use_softpin = anv_gem_get_param(fd, I915_PARAM_HAS_EXEC_SOFTPIN)
+ && device->supports_48bit_addresses;
+
bool swizzled = anv_gem_get_bit6_swizzle(fd, I915_TILING_X);
/* Starting with Gen10, the timestamp frequency of the command streamer may
@@ -1527,6 +1530,27 @@ VkResult anv_CreateDevice(
goto fail_fd;
}
+ if (physical_device->use_softpin) {
+ if (pthread_mutex_init(>vma_mutex, NULL) != 0) {
+ result = vk_error(VK_ERROR_INITIALIZATION_FAILED);
+ goto fail_fd;
+ }
+
+ /* keep the page with address zero out of the allocator */
+ util_vma_heap_init(>vma_lo, LOW_HEAP_MIN_ADDRESS, LOW_HEAP_SIZE);
+ device->vma_lo_available =
+ physical_device->memory.heaps[physical_device->memory.heap_count -
1].size;
+
+ /* Leave the last 4GiB out of the high vma range, so that no state base
+ * address + size can overflow 48 bits. For more information see the
+ * comment about Wa32bitGeneralStateOffset in anv_allocator.c
+ */
+ util_vma_heap_init(>vma_hi, HIGH_HEAP_MIN_ADDRESS,
+ HIGH_HEAP_SIZE);
+ device->vma_hi_available = physical_device->memory.heap_count == 1 ? 0 :
+ physical_device->memory.heaps[0].size;
+ }
+
/* As per spec, the driver implementation may deny requests to acquire
* a priority above the default priority (MEDIUM) if the caller does not
* have sufficient privileges. In this scenario VK_ERROR_NOT_PERMITTED_EXT
@@ -1887,6 +1911,66 @@ VkResult anv_DeviceWaitIdle(
return anv_device_submit_simple_batch(device, );
}
+bool
+anv_vma_alloc(struct anv_device *device, struct anv_bo *bo)
+{
+ if (!(bo->flags & EXEC_OBJECT_PINNED))
+ return true;
+
+ pthread_mutex_lock(>vma_mutex);
+
+ bo->offset = 0;
+
+ if (bo->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS &&
+ device->vma_hi_available >= bo->size) {
+ uint64_t addr = util_vma_heap_alloc(>vma_hi, bo->size, 4096);
+ if (addr) {
+ bo->offset = gen_canonical_address(addr);
+ assert(addr == gen_48b_address(bo->offset));
+ device->vma_hi_available -= bo->size;
+ }
+ }
+
+ if (bo->offset == 0 && device->vma_lo_available >= bo->size) {
+ uint64_t addr = util_vma_heap_alloc(>vma_lo, bo->size, 4096);
+ if (addr) {
+ bo->offset = gen_canonical_address(addr);
+ assert(addr == gen_48b_address(bo->offset));
+ device->vma_lo_available -= bo->size;
+ }
+ }
+
+ pthread_mutex_unlock(>vma_mutex);
+
+ return bo->offset != 0;
+}
+
+void
+anv_vma_free(struct anv_device *device, struct anv_bo *bo)
+{
+ if (!(bo->flags & EXEC_OBJECT_PINNED))
+ return;
+
+ const uint64_t addr_48b = gen_48b_address(bo->offset);
+
+ pthread_mutex_lock(>vma_mutex);
+
+ if (addr_48b >= LOW_HEAP_MIN_ADDRESS &&
+ addr_48b <= LOW_HEAP_MAX_ADDRESS) {
+ util_vma_heap_free(>vma_lo, addr_48b, bo->size);
+
Mesa (master): anv: Use an anv_address in anv_buffer
Module: Mesa
Branch: master
Commit: f270a0973741724d5b30e4b241caa12a1c29
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f270a0973741724d5b30e4b241caa12a1c29
Author: Jason Ekstrand
Date: Wed May 30 18:05:54 2018 -0700
anv: Use an anv_address in anv_buffer
Reviewed-by: Scott D Phillips
---
src/intel/vulkan/anv_blorp.c | 16
src/intel/vulkan/anv_descriptor_set.c | 5 +
src/intel/vulkan/anv_device.c | 12 ++--
src/intel/vulkan/anv_image.c | 5 +
src/intel/vulkan/anv_private.h| 3 +--
src/intel/vulkan/gen7_cmd_buffer.c| 8
src/intel/vulkan/gen8_cmd_buffer.c| 3 +--
src/intel/vulkan/genX_cmd_buffer.c| 32 +---
src/intel/vulkan/genX_query.c | 11 +++
9 files changed, 34 insertions(+), 61 deletions(-)
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index c4a3e4a405..359ebfb3ca 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -154,8 +154,8 @@ get_blorp_surf_for_anv_buffer(struct anv_device *device,
*blorp_surf = (struct blorp_surf) {
.surf = isl_surf,
.addr = {
- .buffer = buffer->bo,
- .offset = buffer->offset + offset,
+ .buffer = buffer->address.bo,
+ .offset = buffer->address.offset + offset,
.mocs = device->default_mocs,
},
};
@@ -662,13 +662,13 @@ void anv_CmdCopyBuffer(
for (unsigned r = 0; r < regionCount; r++) {
struct blorp_address src = {
- .buffer = src_buffer->bo,
- .offset = src_buffer->offset + pRegions[r].srcOffset,
+ .buffer = src_buffer->address.bo,
+ .offset = src_buffer->address.offset + pRegions[r].srcOffset,
.mocs = cmd_buffer->device->default_mocs,
};
struct blorp_address dst = {
- .buffer = dst_buffer->bo,
- .offset = dst_buffer->offset + pRegions[r].dstOffset,
+ .buffer = dst_buffer->address.bo,
+ .offset = dst_buffer->address.offset + pRegions[r].dstOffset,
.mocs = cmd_buffer->device->default_mocs,
};
@@ -720,8 +720,8 @@ void anv_CmdUpdateBuffer(
.mocs = cmd_buffer->device->default_mocs,
};
struct blorp_address dst = {
- .buffer = dst_buffer->bo,
- .offset = dst_buffer->offset + dstOffset,
+ .buffer = dst_buffer->address.bo,
+ .offset = dst_buffer->address.offset + dstOffset,
.mocs = cmd_buffer->device->default_mocs,
};
diff --git a/src/intel/vulkan/anv_descriptor_set.c
b/src/intel/vulkan/anv_descriptor_set.c
index 0380e13a88..9534ba81cd 100644
--- a/src/intel/vulkan/anv_descriptor_set.c
+++ b/src/intel/vulkan/anv_descriptor_set.c
@@ -746,10 +746,7 @@ anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set,
bview->format = anv_isl_format_for_descriptor_type(type);
bview->range = anv_buffer_get_range(buffer, offset, range);
- bview->address = (struct anv_address) {
- .bo = buffer->bo,
- .offset = buffer->offset + offset,
- };
+ bview->address = anv_address_add(buffer->address, offset);
/* If we're writing descriptors through a push command, we need to
* allocate the surface state from the command buffer. Otherwise it will
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 3deeea5a86..19fa1b708f 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -2516,11 +2516,12 @@ anv_bind_buffer_memory(const VkBindBufferMemoryInfo
*pBindInfo)
if (mem) {
assert((buffer->usage & mem->type->valid_buffer_usage) == buffer->usage);
- buffer->bo = mem->bo;
- buffer->offset = pBindInfo->memoryOffset;
+ buffer->address = (struct anv_address) {
+ .bo = mem->bo,
+ .offset = pBindInfo->memoryOffset,
+ };
} else {
- buffer->bo = NULL;
- buffer->offset = 0;
+ buffer->address = ANV_NULL_ADDRESS;
}
}
@@ -2686,8 +2687,7 @@ VkResult anv_CreateBuffer(
buffer->size = pCreateInfo->size;
buffer->usage = pCreateInfo->usage;
- buffer->bo = NULL;
- buffer->offset = 0;
+ buffer->address = ANV_NULL_ADDRESS;
*pBuffer = anv_buffer_to_handle(buffer);
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 090d0615e4..bbb740e2c6 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -1471,10 +1471,7 @@ anv_CreateBufferView(VkDevice _device,
pCreateInfo->range);
view->range = align_down_npot_u32(view->range, format_bs);
- view->address = (struct anv_address) {
- .bo = buffer->bo,
- .offset = buffer->offset + pCreateInfo->
Mesa (master): util: Add a virtual memory allocator
Module: Mesa
Branch: master
Commit: f19ad5d31fde8c447119c5483b3e3972922e9991
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f19ad5d31fde8c447119c5483b3e3972922e9991
Author: Jason Ekstrand
Date: Sat Jan 6 17:28:01 2018 -0800
util: Add a virtual memory allocator
This is simple linear-walk first-fit allocator roughly based on the
allocator in the radeon winsys code. This allocator has two primary
functional differences:
1) It cleanly returns 0 on allocation failure
2) It allocates addresses top-down instead of bottom-up.
The second one is needed for Intel because high addresses (with bit 47
set) need to be canonicalized in order to work properly. If we allocate
bottom-up, then high addresses will be very rare (if they ever happen).
We'd rather always have high addresses so that the canonicalization code
gets better testing.
v2: - [scott-ph] remove _heap_validate() if NDEBUG is defined (Jordan)
Reviewed-by: Scott D Phillips
Tested-by: Scott D Phillips
Reviewed-by: Kenneth Graunke
---
src/util/Makefile.sources | 4 +-
src/util/meson.build | 2 +
src/util/vma.c| 234 ++
src/util/vma.h| 53 +++
4 files changed, 292 insertions(+), 1 deletion(-)
diff --git a/src/util/Makefile.sources b/src/util/Makefile.sources
index 104ecae8ed..534520ce76 100644
--- a/src/util/Makefile.sources
+++ b/src/util/Makefile.sources
@@ -56,7 +56,9 @@ MESA_UTIL_FILES := \
u_string.h \
u_thread.h \
u_vector.c \
- u_vector.h
+ u_vector.h \
+ vma.c \
+ vma.h
MESA_UTIL_GENERATED_FILES = \
format_srgb.c
diff --git a/src/util/meson.build b/src/util/meson.build
index eece1cefef..14660e0fa0 100644
--- a/src/util/meson.build
+++ b/src/util/meson.build
@@ -81,6 +81,8 @@ files_mesa_util = files(
'u_thread.h',
'u_vector.c',
'u_vector.h',
+ 'vma.c',
+ 'vma.h',
)
install_data('drirc', install_dir : get_option('sysconfdir'))
diff --git a/src/util/vma.c b/src/util/vma.c
new file mode 100644
index 00..c8f55031c7
--- /dev/null
+++ b/src/util/vma.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include
+
+#include "util/u_math.h"
+#include "util/vma.h"
+
+struct util_vma_hole {
+ struct list_head link;
+ uint64_t offset;
+ uint64_t size;
+};
+
+#define util_vma_foreach_hole(_hole, _heap) \
+ list_for_each_entry(struct util_vma_hole, _hole, &(_heap)->holes, link)
+
+#define util_vma_foreach_hole_safe(_hole, _heap) \
+ list_for_each_entry_safe(struct util_vma_hole, _hole, &(_heap)->holes, link)
+
+void
+util_vma_heap_init(struct util_vma_heap *heap,
+ uint64_t start, uint64_t size)
+{
+ list_inithead(>holes);
+ util_vma_heap_free(heap, start, size);
+}
+
+void
+util_vma_heap_finish(struct util_vma_heap *heap)
+{
+ util_vma_foreach_hole_safe(hole, heap)
+ free(hole);
+}
+
+#ifndef NDEBUG
+static void
+util_vma_heap_validate(struct util_vma_heap *heap)
+{
+ uint64_t prev_offset = 0;
+ util_vma_foreach_hole(hole, heap) {
+ assert(hole->offset > 0);
+ assert(hole->size > 0);
+
+ if (>link == heap->holes.next) {
+ /* This must be the top-most hole. Assert that, if it overflows, it
+ * overflows to 0, i.e. 2^64.
+ */
+ assert(hole->size + hole->offset == 0 ||
+hole->size + hole->offset > hole->offset);
+ } else {
+ /* This is not the top-most hole so it must not overflow and, in
+ * fact, must be strictly lower than the top-most hole. If
+ * hole->size + hole->offset == prev_offset, then we failed to join
+ * holes during a util_vma_heap_free.
+ */
+ assert(h
Mesa (master): anv: Use an anv_address in anv_buffer_view
Module: Mesa
Branch: master
Commit: 1029458ee32dfada4431e67a17922e1602aba6a7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1029458ee32dfada4431e67a17922e1602aba6a7
Author: Jason Ekstrand
Date: Wed May 30 17:36:49 2018 -0700
anv: Use an anv_address in anv_buffer_view
Instead of storing a BO and offset separately, use an anv_address. This
changes anv_fill_buffer_surface_state to use anv_address and we now call
anv_address_physical and pass that into ISL.
Reviewed-by: Scott D Phillips
---
src/intel/vulkan/anv_descriptor_set.c | 8 +---
src/intel/vulkan/anv_device.c | 5 +++--
src/intel/vulkan/anv_image.c | 13 -
src/intel/vulkan/anv_private.h| 8
src/intel/vulkan/genX_cmd_buffer.c| 29 -
5 files changed, 36 insertions(+), 27 deletions(-)
diff --git a/src/intel/vulkan/anv_descriptor_set.c
b/src/intel/vulkan/anv_descriptor_set.c
index 67511e4b28..0380e13a88 100644
--- a/src/intel/vulkan/anv_descriptor_set.c
+++ b/src/intel/vulkan/anv_descriptor_set.c
@@ -745,9 +745,11 @@ anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set,
>buffer_views[bind_layout->buffer_index + element];
bview->format = anv_isl_format_for_descriptor_type(type);
- bview->bo = buffer->bo;
- bview->offset = buffer->offset + offset;
bview->range = anv_buffer_get_range(buffer, offset, range);
+ bview->address = (struct anv_address) {
+ .bo = buffer->bo,
+ .offset = buffer->offset + offset,
+ };
/* If we're writing descriptors through a push command, we need to
* allocate the surface state from the command buffer. Otherwise it will
@@ -758,7 +760,7 @@ anv_descriptor_set_write_buffer(struct anv_descriptor_set
*set,
anv_fill_buffer_surface_state(device, bview->surface_state,
bview->format,
-bview->offset, bview->range, 1);
+bview->address, bview->range, 1);
*desc = (struct anv_descriptor) {
.type = type,
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 276e32bddd..3deeea5a86 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -2711,10 +2711,11 @@ void anv_DestroyBuffer(
void
anv_fill_buffer_surface_state(struct anv_device *device, struct anv_state
state,
enum isl_format format,
- uint32_t offset, uint32_t range, uint32_t stride)
+ struct anv_address address,
+ uint32_t range, uint32_t stride)
{
isl_buffer_fill_state(>isl_dev, state.map,
- .address = offset,
+ .address = anv_address_physical(address),
.mocs = device->default_mocs,
.size = range,
.format = format,
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 52882080fd..090d0615e4 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -1467,18 +1467,21 @@ anv_CreateBufferView(VkDevice _device,
VK_IMAGE_ASPECT_COLOR_BIT,
VK_IMAGE_TILING_LINEAR);
const uint32_t format_bs = isl_format_get_layout(view->format)->bpb / 8;
- view->bo = buffer->bo;
- view->offset = buffer->offset + pCreateInfo->offset;
view->range = anv_buffer_get_range(buffer, pCreateInfo->offset,
pCreateInfo->range);
view->range = align_down_npot_u32(view->range, format_bs);
+ view->address = (struct anv_address) {
+ .bo = buffer->bo,
+ .offset = buffer->offset + pCreateInfo->offset,
+ };
+
if (buffer->usage & VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT) {
view->surface_state = alloc_surface_state(device);
anv_fill_buffer_surface_state(device, view->surface_state,
view->format,
-view->offset, view->range, format_bs);
+view->address, view->range, format_bs);
} else {
view->surface_state = (struct anv_state){ 0 };
}
@@ -1495,14 +1498,14 @@ anv_CreateBufferView(VkDevice _device,
anv_fill_buffer_surface_state(device, view->storage_surface_state,
storage_format,
-view->offset, view->range,
+view->address, view->range,
(storage_format == ISL_FORMAT_RAW ? 1 :
isl_format_get_layout(storage_format)->bpb / 8
Mesa (master): anv/cmd_buffer: Use anv_address for handling indirect parameters
Module: Mesa
Branch: master
Commit: 8a8bd39d5eba70a67bf463a461c86f3061fafae9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a8bd39d5eba70a67bf463a461c86f3061fafae9
Author: Jason Ekstrand
Date: Wed May 30 18:02:43 2018 -0700
anv/cmd_buffer: Use anv_address for handling indirect parameters
Reviewed-by: Scott D Phillips
---
src/intel/vulkan/genX_cmd_buffer.c | 95 --
1 file changed, 51 insertions(+), 44 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 97fb8ea30b..d38c5f8cab 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2599,7 +2599,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer
*cmd_buffer)
static void
emit_vertex_bo(struct anv_cmd_buffer *cmd_buffer,
- struct anv_bo *bo, uint32_t offset,
+ struct anv_address addr,
uint32_t size, uint32_t index)
{
uint32_t *p = anv_batch_emitn(_buffer->batch, 5,
@@ -2612,21 +2612,21 @@ emit_vertex_bo(struct anv_cmd_buffer *cmd_buffer,
.BufferPitch = 0,
#if (GEN_GEN >= 8)
.MemoryObjectControlState = GENX(MOCS),
- .BufferStartingAddress = { bo, offset },
+ .BufferStartingAddress = addr,
.BufferSize = size
#else
.VertexBufferMemoryObjectControlState = GENX(MOCS),
- .BufferStartingAddress = { bo, offset },
- .EndAddress = { bo, offset + size },
+ .BufferStartingAddress = addr,
+ .EndAddress = anv_address_add(addr, size),
#endif
});
}
static void
emit_base_vertex_instance_bo(struct anv_cmd_buffer *cmd_buffer,
- struct anv_bo *bo, uint32_t offset)
+ struct anv_address addr)
{
- emit_vertex_bo(cmd_buffer, bo, offset, 8, ANV_SVGS_VB_INDEX);
+ emit_vertex_bo(cmd_buffer, addr, 8, ANV_SVGS_VB_INDEX);
}
static void
@@ -2641,8 +2641,12 @@ emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer,
anv_state_flush(cmd_buffer->device, id_state);
- emit_base_vertex_instance_bo(cmd_buffer,
- _buffer->device->dynamic_state_pool.block_pool.bo, id_state.offset);
+ struct anv_address addr = {
+ .bo = _buffer->device->dynamic_state_pool.block_pool.bo,
+ .offset = id_state.offset,
+ };
+
+ emit_base_vertex_instance_bo(cmd_buffer, addr);
}
static void
@@ -2655,9 +2659,12 @@ emit_draw_index(struct anv_cmd_buffer *cmd_buffer,
uint32_t draw_index)
anv_state_flush(cmd_buffer->device, state);
- emit_vertex_bo(cmd_buffer,
- _buffer->device->dynamic_state_pool.block_pool.bo,
- state.offset, 4, ANV_DRAWID_VB_INDEX);
+ struct anv_address addr = {
+ .bo = _buffer->device->dynamic_state_pool.block_pool.bo,
+ .offset = state.offset,
+ };
+
+ emit_vertex_bo(cmd_buffer, addr, 4, ANV_DRAWID_VB_INDEX);
}
void genX(CmdDraw)(
@@ -2799,37 +2806,35 @@ emit_mul_gpr0(struct anv_batch *batch, uint32_t N)
static void
load_indirect_parameters(struct anv_cmd_buffer *cmd_buffer,
- struct anv_buffer *buffer, uint64_t offset,
+ struct anv_address addr,
bool indexed)
{
struct anv_batch *batch = _buffer->batch;
- struct anv_bo *bo = buffer->bo;
- uint32_t bo_offset = buffer->offset + offset;
- emit_lrm(batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
+ emit_lrm(batch, GEN7_3DPRIM_VERTEX_COUNT, addr.bo, addr.offset);
unsigned view_count = anv_subpass_view_count(cmd_buffer->state.subpass);
if (view_count > 1) {
#if GEN_IS_HASWELL || GEN_GEN >= 8
- emit_lrm(batch, CS_GPR(0), bo, bo_offset + 4);
+ emit_lrm(batch, CS_GPR(0), addr.bo, addr.offset + 4);
emit_mul_gpr0(batch, view_count);
emit_lrr(batch, GEN7_3DPRIM_INSTANCE_COUNT, CS_GPR(0));
#else
anv_finishme("Multiview + indirect draw requires MI_MATH; "
"MI_MATH is not supported on Ivy Bridge");
- emit_lrm(batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
+ emit_lrm(batch, GEN7_3DPRIM_INSTANCE_COUNT, addr.bo, addr.offset + 4);
#endif
} else {
- emit_lrm(batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
+ emit_lrm(batch, GEN7_3DPRIM_INSTANCE_COUNT, addr.bo, addr.offset + 4);
}
- emit_lrm(batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8);
+ emit_lrm(batch, GEN7_3DPRIM_START_VERTEX, addr.bo, addr.offset + 8);
if (indexed) {
- emit_lrm(batch, GEN7_3DPRIM_BASE_VERTEX, bo, bo_offset + 12);
- emit_lrm(batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 16);
+ emit_lrm(batch, GEN7_3DPRIM_BASE_VERTEX, addr.bo, addr.offset + 12);
+ emit_lrm(batch, GEN7_3DPRIM_START_INSTANCE, addr.bo, addr.offset + 16);
} else {
- emit_lrm(batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 12);
+ emit_lrm(batc
Mesa (master): util: Add a randomized test for the virtual memory allocator
Module: Mesa
Branch: master
Commit: 943fecc5691b55b8ce8740d133dd70614effb72d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=943fecc5691b55b8ce8740d133dd70614effb72d
Author: Scott D Phillips
Date: Fri May 4 17:11:13 2018 -0700
util: Add a randomized test for the virtual memory allocator
The test pseudo-randomly makes allocations and deallocations with
the virtual memory allocator and checks that the results are
consistent. Specifically, we test that:
* no result from the allocator overlaps an already allocated range
* allocated memory fulfills the stated alignment requirement
* a failed result from the allocator could not have been fulfilled
* memory freed to the allocator can later be allocated again
v2: - fix if() in test() to actually run fill()
v3: - add c++11 build flag (Jason)
- test the full 64-bit range (Jason)
Reviewed-by: Jason Ekstrand
---
configure.ac | 1 +
src/util/Makefile.am | 3 +-
src/util/meson.build | 1 +
src/util/tests/vma/Makefile.am | 39 ++
src/util/tests/vma/meson.build | 29
src/util/tests/vma/vma_random_test.cpp | 244 +
6 files changed, 316 insertions(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index 62063c1c8a..02dca4547c 100644
--- a/configure.ac
+++ b/configure.ac
@@ -3123,6 +3123,7 @@ AC_CONFIG_FILES([Makefile
src/util/Makefile
src/util/tests/hash_table/Makefile
src/util/tests/string_buffer/Makefile
+ src/util/tests/vma/Makefile
src/util/xmlpool/Makefile
src/vulkan/Makefile])
diff --git a/src/util/Makefile.am b/src/util/Makefile.am
index 07bf052175..b51dccdadf 100644
--- a/src/util/Makefile.am
+++ b/src/util/Makefile.am
@@ -22,7 +22,8 @@
SUBDIRS = . \
xmlpool \
tests/hash_table \
- tests/string_buffer
+ tests/string_buffer \
+ tests/vma
include Makefile.sources
diff --git a/src/util/meson.build b/src/util/meson.build
index 14660e0fa0..c777984e28 100644
--- a/src/util/meson.build
+++ b/src/util/meson.build
@@ -159,4 +159,5 @@ if with_tests
subdir('tests/hash_table')
subdir('tests/string_buffer')
+ subdir('tests/vma')
endif
diff --git a/src/util/tests/vma/Makefile.am b/src/util/tests/vma/Makefile.am
new file mode 100644
index 00..b9ca8f5977
--- /dev/null
+++ b/src/util/tests/vma/Makefile.am
@@ -0,0 +1,39 @@
+# Copyright © 2018 Intel Corporation
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice (including the next
+# paragraph) shall be included in all copies or substantial portions of the
+# Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+# IN THE SOFTWARE.
+
+AM_CPPFLAGS = \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/src/util \
+ $(DEFINES)
+
+TESTS = vma_random_test
+
+check_PROGRAMS = $(TESTS)
+
+vma_random_test_SOURCES = \
+ vma_random_test.cpp
+
+vma_random_test_LDADD = \
+ $(top_builddir)/src/util/libmesautil.la
+
+vma_random_test_CXXFLAGS = $(CXX11_CXXFLAGS)
+
+EXTRA_DIST = meson.build
diff --git a/src/util/tests/vma/meson.build b/src/util/tests/vma/meson.build
new file mode 100644
index 00..53562db312
--- /dev/null
+++ b/src/util/tests/vma/meson.build
@@ -0,0 +1,29 @@
+# Copyright © 2018 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Mesa (master): anv: Use full anv_addresses in anv_surface_state
Module: Mesa
Branch: master
Commit: de1c5c1b503fb190e5d169654ce20e699195
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=de1c5c1b503fb190e5d169654ce20e699195
Author: Jason Ekstrand
Date: Wed May 30 17:16:52 2018 -0700
anv: Use full anv_addresses in anv_surface_state
This refactors surface state filling to work entirely in terms of
anv_addresses instead of offsets. This should make things simpler for
when we go to soft-pin image buffers. Among other things,
add_image_view_relocs now only cares about the addresses in the surface
state and doesn't really need the image view anymore.
Reviewed-by: Scott D Phillips
---
src/intel/vulkan/anv_image.c | 64 ++
src/intel/vulkan/anv_private.h | 12 +++
src/intel/vulkan/genX_cmd_buffer.c | 30 +++---
3 files changed, 55 insertions(+), 51 deletions(-)
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 42496b6414..52882080fd 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -1067,20 +1067,10 @@ anv_image_fill_surface_state(struct anv_device *device,
if (!clear_color)
clear_color = _clear_color;
- const uint64_t address = image->planes[plane].bo_offset + surface->offset;
- const uint64_t aux_address = aux_usage == ISL_AUX_USAGE_NONE ?
- 0 : (image->planes[plane].bo_offset + aux_surface->offset);
-
- struct anv_address clear_address = { .bo = NULL };
- state_inout->clear_address = 0;
-
- if (device->info.gen >= 10 && aux_usage != ISL_AUX_USAGE_NONE) {
- if (aux_usage == ISL_AUX_USAGE_HIZ) {
- clear_address = (struct anv_address) { .bo = >hiz_clear_bo };
- } else {
- clear_address = anv_image_get_clear_color_addr(device, image, aspect);
- }
- }
+ const struct anv_address address = {
+ .bo = image->planes[plane].bo,
+ .offset = image->planes[plane].bo_offset + surface->offset,
+ };
if (view_usage == ISL_SURF_USAGE_STORAGE_BIT &&
!(flags & ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY) &&
@@ -1092,14 +1082,14 @@ anv_image_fill_surface_state(struct anv_device *device,
*/
assert(aux_usage == ISL_AUX_USAGE_NONE);
isl_buffer_fill_state(>isl_dev, state_inout->state.map,
-.address = address,
+.address = anv_address_physical(address),
.size = surface->isl.size,
.format = ISL_FORMAT_RAW,
.stride = 1,
.mocs = device->default_mocs);
state_inout->address = address,
- state_inout->aux_address = 0;
- state_inout->clear_address = 0;
+ state_inout->aux_address = ANV_NULL_ADDRESS;
+ state_inout->clear_address = ANV_NULL_ADDRESS;
} else {
if (view_usage == ISL_SURF_USAGE_STORAGE_BIT &&
!(flags & ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY)) {
@@ -1165,20 +1155,43 @@ anv_image_fill_surface_state(struct anv_device *device,
}
}
+ state_inout->address = anv_address_add(address, offset_B);
+
+ struct anv_address aux_address = ANV_NULL_ADDRESS;
+ if (aux_usage != ISL_AUX_USAGE_NONE) {
+ aux_address = (struct anv_address) {
+.bo = image->planes[plane].bo,
+.offset = image->planes[plane].bo_offset + aux_surface->offset,
+ };
+ }
+ state_inout->aux_address = aux_address;
+
+ struct anv_address clear_address = ANV_NULL_ADDRESS;
+ if (device->info.gen >= 10 && aux_usage != ISL_AUX_USAGE_NONE) {
+ if (aux_usage == ISL_AUX_USAGE_HIZ) {
+clear_address = (struct anv_address) {
+ .bo = >hiz_clear_bo,
+ .offset = 0,
+};
+ } else {
+clear_address = anv_image_get_clear_color_addr(device, image,
aspect);
+ }
+ }
+ state_inout->clear_address = clear_address;
+
isl_surf_fill_state(>isl_dev, state_inout->state.map,
.surf = isl_surf,
.view = ,
- .address = address + offset_B,
+ .address =
anv_address_physical(state_inout->address),
.clear_color = *clear_color,
.aux_surf = _surface->isl,
.aux_usage = aux_usage,
- .aux_address = aux_address,
- .clear_address = clear_address.offset,
- .use_clear_address = clear_address.bo != NULL,
+ .aux_address = anv_address_physical(aux_address),
+ .clear_address = anv_address_physical(clear_address),
+ .use_clear_address =
Mesa (master): intel/eu: Remove brw_codegen::compressed_stack.
Module: Mesa
Branch: master
Commit: 11c71f0e75bc5c42c9cdd11170325ff919f03c8b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=11c71f0e75bc5c42c9cdd11170325ff919f03c8b
Author: Francisco Jerez
Date: Thu Jan 5 19:26:13 2017 -0800
intel/eu: Remove brw_codegen::compressed_stack.
Reviewed-by: Jason Ekstrand
Reviewed-by: Kenneth Graunke
Reviewed-by: Matt Turner
---
src/intel/compiler/brw_eu.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 120a74f035..2655cdb0c5 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -63,7 +63,6 @@ struct brw_codegen {
/* Allow clients to push/pop instruction state:
*/
brw_inst stack[BRW_EU_MAX_INSN_STACK];
- bool compressed_stack[BRW_EU_MAX_INSN_STACK];
brw_inst *current;
/** Whether or not the user wants automatic exec sizes
___
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mesa-commit@lists.freedesktop.org
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Mesa (master): intel/fs: Use groups for SIMD16 LINTERP on gen11+
Module: Mesa
Branch: master
Commit: 71a86d1fc69a025754d8d4c21f5777b21c65a3ea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=71a86d1fc69a025754d8d4c21f5777b21c65a3ea
Author: Jason Ekstrand
Date: Wed May 16 17:33:17 2018 -0700
intel/fs: Use groups for SIMD16 LINTERP on gen11+
This is better than compression control because it naturally extends to
SIMD32.
v2:
- Push/pop instruction state around adjusted codegen (Ken)
Reviewed-by: Kenneth Graunke
Reviewed-by: Matt Turner
---
src/intel/compiler/brw_fs_generator.cpp | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/intel/compiler/brw_fs_generator.cpp
b/src/intel/compiler/brw_fs_generator.cpp
index 0c050a73b4..20e356e23e 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -781,6 +781,7 @@ fs_generator::generate_linterp(fs_inst *inst,
struct brw_reg dwQ = suboffset(interp, 1);
struct brw_reg dwR = suboffset(interp, 3);
+ brw_push_insn_state(p);
brw_set_default_exec_size(p, BRW_EXECUTE_8);
if (inst->exec_size == 8) {
@@ -795,16 +796,14 @@ fs_generator::generate_linterp(fs_inst *inst,
*/
brw_inst_set_saturate(p->devinfo, i[0], false);
} else {
- brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
+ brw_set_default_group(p, inst->group);
i[0] = brw_MAD(p,acc, dwR, offset(delta_x, 0), dwP);
i[1] = brw_MAD(p, offset(dst, 0), acc, offset(delta_x, 1), dwQ);
- brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
+ brw_set_default_group(p, inst->group + 8);
i[2] = brw_MAD(p,acc, dwR, offset(delta_y, 0), dwP);
i[3] = brw_MAD(p, offset(dst, 1), acc, offset(delta_y, 1), dwQ);
- brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
-
brw_inst_set_cond_modifier(p->devinfo, i[1], inst->conditional_mod);
brw_inst_set_cond_modifier(p->devinfo, i[3], inst->conditional_mod);
@@ -816,6 +815,8 @@ fs_generator::generate_linterp(fs_inst *inst,
brw_inst_set_saturate(p->devinfo, i[2], false);
}
+ brw_pop_insn_state(p);
+
return true;
} else if (devinfo->has_pln) {
/* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
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Mesa (master): intel/fs: Rename a local variable so it doesn't shadow component()
Module: Mesa
Branch: master
Commit: 4bfa2ac2eab7551b1d89309fa8da44a487542f72
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4bfa2ac2eab7551b1d89309fa8da44a487542f72
Author: Francisco Jerez
Date: Fri May 18 15:13:25 2018 -0700
intel/fs: Rename a local variable so it doesn't shadow component()
v2 (Jason Ekstrand):
- Break the refactor into its own patch
Reviewed-by: Jason Ekstrand
Reviewed-by: Kenneth Graunke
Reviewed-by: Matt Turner
---
src/intel/compiler/brw_fs_nir.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 1ce89520bf..ad945b890c 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -3372,15 +3372,15 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder ,
case nir_intrinsic_load_input: {
/* load_input is only used for flat inputs */
unsigned base = nir_intrinsic_base(instr);
- unsigned component = nir_intrinsic_component(instr);
+ unsigned comp = nir_intrinsic_component(instr);
unsigned num_components = instr->num_components;
enum brw_reg_type type = dest.type;
/* Special case fields in the VUE header */
if (base == VARYING_SLOT_LAYER)
- component = 1;
+ comp = 1;
else if (base == VARYING_SLOT_VIEWPORT)
- component = 2;
+ comp = 2;
if (nir_dest_bit_size(instr->dest) == 64) {
/* const_index is in 32-bit type size units that could not be aligned
@@ -3392,7 +3392,7 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder ,
}
for (unsigned int i = 0; i < num_components; i++) {
- struct brw_reg interp = interp_reg(base, component + i);
+ struct brw_reg interp = interp_reg(base, comp + i);
interp = suboffset(interp, 3);
bld.emit(FS_OPCODE_CINTERP, offset(retype(dest, type), bld, i),
retype(fs_reg(interp), type));
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Mesa (master): intel/fs: Assert that the gen4-6 plane restrictions are followed
Module: Mesa
Branch: master
Commit: a1a850cd3411400ce832e77c4be1f0e14924ce9e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1a850cd3411400ce832e77c4be1f0e14924ce9e
Author: Jason Ekstrand
Date: Wed May 16 17:30:04 2018 -0700
intel/fs: Assert that the gen4-6 plane restrictions are followed
The fall-back does not work correctly in SIMD16 mode and the register
allocator should ensure that we never hit this case anyway.
Reviewed-by: Matt Turner
---
src/intel/compiler/brw_fs_generator.cpp | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/intel/compiler/brw_fs_generator.cpp
b/src/intel/compiler/brw_fs_generator.cpp
index 6d5306a0ee..0c050a73b4 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -817,8 +817,14 @@ fs_generator::generate_linterp(fs_inst *inst,
}
return true;
- } else if (devinfo->has_pln &&
- (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
+ } else if (devinfo->has_pln) {
+ /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
+ *
+ *"[DevSNB]: must be even register aligned.
+ *
+ * This restriction is lifted on Ivy Bridge.
+ */
+ assert(devinfo->gen >= 7 || (delta_x.nr & 1) == 0);
brw_PLN(p, dst, interp, delta_x);
return false;
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Mesa (master): intel/fs: Use the ATTR file for FS inputs
Module: Mesa
Branch: master
Commit: 39de901a96bd1048b2c0de32a469014b398f38ae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=39de901a96bd1048b2c0de32a469014b398f38ae
Author: Francisco Jerez
Date: Mon Apr 25 18:33:22 2016 -0700
intel/fs: Use the ATTR file for FS inputs
This replaces the special magic opcodes which implicitly read inputs
with explicit use of the ATTR file.
v2 (Jason Ekstrand):
- Break into multiple patches
- Change the units of the FS ATTR to be in logical scalars
Reviewed-by: Jason Ekstrand
Reviewed-by: Matt Turner
---
src/intel/compiler/brw_fs.cpp | 32 ++--
src/intel/compiler/brw_fs.h | 2 +-
src/intel/compiler/brw_fs_nir.cpp | 8 +++-
src/intel/compiler/brw_fs_visitor.cpp | 10 --
4 files changed, 30 insertions(+), 22 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index b21996c168..8d9278684f 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -1079,8 +1079,8 @@ fs_visitor::emit_fragcoord_interpolation(fs_reg wpos)
bld.MOV(wpos, fs_reg(brw_vec8_grf(payload.source_depth_reg, 0)));
} else {
bld.emit(FS_OPCODE_LINTERP, wpos,
- this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL],
- interp_reg(VARYING_SLOT_POS, 2));
+ this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL],
+ component(interp_reg(VARYING_SLOT_POS, 2), 0));
}
wpos = offset(wpos, bld, 1);
@@ -1609,14 +1609,26 @@ fs_visitor::assign_urb_setup()
* setup regs, now that the location of the constants has been chosen.
*/
foreach_block_and_inst(block, fs_inst, inst, cfg) {
- if (inst->opcode == FS_OPCODE_LINTERP) {
-assert(inst->src[1].file == FIXED_GRF);
- inst->src[1].nr += urb_start;
- }
-
- if (inst->opcode == FS_OPCODE_CINTERP) {
-assert(inst->src[0].file == FIXED_GRF);
- inst->src[0].nr += urb_start;
+ for (int i = 0; i < inst->sources; i++) {
+ if (inst->src[i].file == ATTR) {
+/* ATTR regs in the FS are in units of logical scalar inputs each
+ * of which consumes half of a GRF register.
+ */
+assert(inst->src[i].offset < REG_SIZE / 2);
+const unsigned grf = urb_start + inst->src[i].nr / 2;
+const unsigned offset = (inst->src[i].nr % 2) * (REG_SIZE / 2) +
+inst->src[i].offset;
+const unsigned width = inst->src[i].stride == 0 ?
+ 1 : MIN2(inst->exec_size, 8);
+struct brw_reg reg = stride(
+ byte_offset(retype(brw_vec8_grf(grf, 0), inst->src[i].type),
+ offset),
+ width * inst->src[i].stride,
+ width, inst->src[i].stride);
+reg.abs = inst->src[i].abs;
+reg.negate = inst->src[i].negate;
+inst->src[i] = reg;
+ }
}
}
diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index e384db809d..faf5156863 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -276,7 +276,7 @@ public:
fs_reg get_timestamp(const brw::fs_builder );
- struct brw_reg interp_reg(int location, int channel);
+ fs_reg interp_reg(int location, int channel);
int implied_mrf_writes(fs_inst *inst) const;
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index ad945b890c..282b3bb3b9 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -3392,10 +3392,8 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder ,
}
for (unsigned int i = 0; i < num_components; i++) {
- struct brw_reg interp = interp_reg(base, comp + i);
- interp = suboffset(interp, 3);
bld.emit(FS_OPCODE_CINTERP, offset(retype(dest, type), bld, i),
- retype(fs_reg(interp), type));
+ retype(component(interp_reg(base, comp + i), 3), type));
}
if (nir_dest_bit_size(instr->dest) == 64) {
@@ -3568,8 +3566,8 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder ,
for (unsigned int i = 0; i < instr->num_components; i++) {
fs_reg interp =
-fs_reg(interp_reg(nir_intrinsic_base(instr),
- nir_intrinsic_component(instr) + i));
+component(interp_reg(nir_intrinsic_base(instr),
+ nir_intrinsic_component(instr) + i), 0);
interp.type = BRW_REGISTER_TYPE_F;
dest.type = BRW_REGISTER_TYPE_F;
diff --git a/src/intel/compiler/brw_fs_visitor.cpp
b/src/intel/compiler/brw_fs_visitor.cpp
index 7a5f6451f2..41dbd76106 100644
--- a/src/intel/compiler/brw_fs_visitor.cpp
+++ b/src/intel/compiler/brw_fs_visitor.cpp
@@ -135,17 +135,15
Mesa (master): intel/fs: Add explicit last_rt flag to fb writes orthogonal to eot.
Module: Mesa
Branch: master
Commit: 4bd2047deea31e877ae023a3845f925aab69cdc7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4bd2047deea31e877ae023a3845f925aab69cdc7
Author: Francisco Jerez
Date: Fri Jan 13 14:01:45 2017 -0800
intel/fs: Add explicit last_rt flag to fb writes orthogonal to eot.
When using multiple RT write messages to the same RT such as for
dual-source blending or all RT writes in SIMD32, we have to set the
"Last Render Target Select" bit on all write messages that target the
last RT but only set EOT on the last RT write in the shader.
Special-casing for dual-source blend works today because that is the
only case which requires multiple RT write messages per RT. When we
start doing SIMD32, this will become much more common so we add a
dedicated bit for it.
Reviewed-by: Jason Ekstrand
Reviewed-by: Matt Turner
---
src/intel/compiler/brw_fs.cpp | 1 +
src/intel/compiler/brw_fs_generator.cpp | 6 +-
src/intel/compiler/brw_fs_visitor.cpp | 2 ++
src/intel/compiler/brw_ir_fs.h | 1 +
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 8d9278684f..d67c0a4192 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -3246,6 +3246,7 @@ fs_visitor::emit_repclear_shader()
}
}
write->eot = true;
+ write->last_rt = true;
calculate_cfg();
diff --git a/src/intel/compiler/brw_fs_generator.cpp
b/src/intel/compiler/brw_fs_generator.cpp
index f310a84e25..f49ab442fb 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -289,10 +289,6 @@ fs_generator::fire_fb_write(fs_inst *inst,
*/
const uint32_t surf_index = inst->target;
- bool last_render_target = inst->eot ||
- (prog_data->dual_src_blend && dispatch_width ==
16);
-
-
brw_fb_WRITE(p,
payload,
implied_header,
@@ -301,7 +297,7 @@ fs_generator::fire_fb_write(fs_inst *inst,
nr,
0,
inst->eot,
-last_render_target,
+inst->last_rt,
inst->header_size != 0);
brw_mark_surface_used(_data->base, surf_index);
diff --git a/src/intel/compiler/brw_fs_visitor.cpp
b/src/intel/compiler/brw_fs_visitor.cpp
index 41dbd76106..a24808eac6 100644
--- a/src/intel/compiler/brw_fs_visitor.cpp
+++ b/src/intel/compiler/brw_fs_visitor.cpp
@@ -103,6 +103,7 @@ fs_visitor::emit_dummy_fs()
fs_inst *write;
write = bld.emit(FS_OPCODE_FB_WRITE);
write->eot = true;
+ write->last_rt = true;
if (devinfo->gen >= 6) {
write->base_mrf = 2;
write->mlen = 4 * reg_width;
@@ -459,6 +460,7 @@ fs_visitor::emit_fb_writes()
inst->target = 0;
}
+ inst->last_rt = true;
inst->eot = true;
}
diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h
index f06a33c516..92dad269a3 100644
--- a/src/intel/compiler/brw_ir_fs.h
+++ b/src/intel/compiler/brw_ir_fs.h
@@ -374,6 +374,7 @@ public:
uint8_t sources; /**< Number of fs_reg sources. */
+ bool last_rt:1;
bool pi_noperspective:1; /**< Pixel interpolator noperspective flag */
};
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Mesa (master): intel/fs: Replace the CINTERP opcode with a simple MOV
Module: Mesa
Branch: master
Commit: d3cd6b7215c11054b587fb0fd621c53c6d62c64b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d3cd6b7215c11054b587fb0fd621c53c6d62c64b
Author: Francisco Jerez
Date: Fri May 18 15:20:43 2018 -0700
intel/fs: Replace the CINTERP opcode with a simple MOV
The only reason it was it's own opcode was so that we could detect it
and adjust the source register based on the payload setup. Now that
we're using the ATTR file for FS inputs, there's no point in having a
magic opcode for this.
v2 (Jason Ekstrand):
- Break the bit which removes the CINTERP opcode into its own patch
Reviewed-by: Jason Ekstrand
Reviewed-by: Matt Turner
---
src/intel/compiler/brw_eu_defines.h | 1 -
src/intel/compiler/brw_fs_cse.cpp | 1 -
src/intel/compiler/brw_fs_generator.cpp | 3 ---
src/intel/compiler/brw_fs_nir.cpp | 4 ++--
src/intel/compiler/brw_shader.cpp | 6 +-
5 files changed, 3 insertions(+), 12 deletions(-)
diff --git a/src/intel/compiler/brw_eu_defines.h
b/src/intel/compiler/brw_eu_defines.h
index 332d627bc3..36519af63f 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -499,7 +499,6 @@ enum opcode {
*/
FS_OPCODE_DDY_COARSE,
FS_OPCODE_DDY_FINE,
- FS_OPCODE_CINTERP,
FS_OPCODE_LINTERP,
FS_OPCODE_PIXEL_X,
FS_OPCODE_PIXEL_Y,
diff --git a/src/intel/compiler/brw_fs_cse.cpp
b/src/intel/compiler/brw_fs_cse.cpp
index 48220efd73..6859733d58 100644
--- a/src/intel/compiler/brw_fs_cse.cpp
+++ b/src/intel/compiler/brw_fs_cse.cpp
@@ -75,7 +75,6 @@ is_expression(const fs_visitor *v, const fs_inst *const inst)
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
- case FS_OPCODE_CINTERP:
case FS_OPCODE_LINTERP:
case SHADER_OPCODE_FIND_LIVE_CHANNEL:
case SHADER_OPCODE_BROADCAST:
diff --git a/src/intel/compiler/brw_fs_generator.cpp
b/src/intel/compiler/brw_fs_generator.cpp
index 20e356e23e..f310a84e25 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -2112,9 +2112,6 @@ fs_generator::generate_code(const cfg_t *cfg, int
dispatch_width)
BRW_MATH_PRECISION_FULL);
}
break;
- case FS_OPCODE_CINTERP:
-brw_MOV(p, dst, src[0]);
-break;
case FS_OPCODE_LINTERP:
multiple_instructions_emitted = generate_linterp(inst, dst, src);
break;
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 282b3bb3b9..e287f11e47 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -3392,8 +3392,8 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder ,
}
for (unsigned int i = 0; i < num_components; i++) {
- bld.emit(FS_OPCODE_CINTERP, offset(retype(dest, type), bld, i),
- retype(component(interp_reg(base, comp + i), 3), type));
+ bld.MOV(offset(retype(dest, type), bld, i),
+ retype(component(interp_reg(base, comp + i), 3), type));
}
if (nir_dest_bit_size(instr->dest) == 64) {
diff --git a/src/intel/compiler/brw_shader.cpp
b/src/intel/compiler/brw_shader.cpp
index 537defd05d..6e81db9c29 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -378,8 +378,6 @@ brw_instruction_name(const struct gen_device_info *devinfo,
enum opcode op)
case FS_OPCODE_DDY_FINE:
return "ddy_fine";
- case FS_OPCODE_CINTERP:
- return "cinterp";
case FS_OPCODE_LINTERP:
return "linterp";
@@ -960,7 +958,6 @@ backend_instruction::can_do_cmod() const
case BRW_OPCODE_SHR:
case BRW_OPCODE_SUBB:
case BRW_OPCODE_XOR:
- case FS_OPCODE_CINTERP:
case FS_OPCODE_LINTERP:
return true;
default:
@@ -987,8 +984,7 @@ backend_instruction::writes_accumulator_implicitly(const
struct gen_device_info
return writes_accumulator ||
(devinfo->gen < 6 &&
((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
-(opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
- opcode != FS_OPCODE_CINTERP)));
+(opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP)));
}
bool
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Mesa (master): intel/blorp: Support blits and clears on surfaces with offsets
Module: Mesa
Branch: master
Commit: ae514ca695a599cdd0b7c22f48fd4d721671b0cb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae514ca695a599cdd0b7c22f48fd4d721671b0cb
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri May 25 12:27:17 2018 -0700
intel/blorp: Support blits and clears on surfaces with offsets
For certain EGLImage cases, we represent a single slice or LOD of an
image with a byte offset to a tile and X/Y intratile offsets to the
given slice. Most of i965 is fine with this but it breaks blorp. This
is a terrible way to represent slices of a surface in EGL and we should
stop some day but that's a very scary and thorny path. This gets blorp
to start working with those surfaces and fixes some dEQP EGL test bugs.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106629
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/blorp/blorp.c | 22 ++
src/intel/blorp/blorp.h | 3 +++
src/intel/blorp/blorp_blit.c | 4 +++-
src/intel/blorp/blorp_clear.c | 9 +
src/mesa/drivers/dri/i965/brw_blorp.c | 2 ++
5 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c
index e348cafb2e..73f8c67802 100644
--- a/src/intel/blorp/blorp.c
+++ b/src/intel/blorp/blorp.c
@@ -137,6 +137,28 @@ brw_blorp_surface_info_init(struct blorp_context *blorp,
*/
if (is_render_target && blorp->isl_dev->info->gen <= 6)
info->view.array_len = MIN2(info->view.array_len, 512);
+
+ if (surf->tile_x_sa || surf->tile_y_sa) {
+ /* This is only allowed on simple 2D surfaces without MSAA */
+ assert(info->surf.dim == ISL_SURF_DIM_2D);
+ assert(info->surf.samples == 1);
+ assert(info->surf.levels == 1);
+ assert(info->surf.logical_level0_px.array_len == 1);
+ assert(info->aux_usage == ISL_AUX_USAGE_NONE);
+
+ info->tile_x_sa = surf->tile_x_sa;
+ info->tile_y_sa = surf->tile_y_sa;
+
+ /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we
+ * place the image at the tile boundary and offset our sampling or
+ * rendering. For this reason, we need to grow the image by the offset
+ * to ensure that the hardware doesn't think we've gone past the edge.
+ */
+ info->surf.logical_level0_px.w += surf->tile_x_sa;
+ info->surf.logical_level0_px.h += surf->tile_y_sa;
+ info->surf.phys_level0_sa.w += surf->tile_x_sa;
+ info->surf.phys_level0_sa.h += surf->tile_y_sa;
+ }
}
diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index f22110bc84..0a10ff9157 100644
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -114,6 +114,9 @@ struct blorp_surf
* that it contains a swizzle of RGBA and resource min LOD of 0.
*/
struct blorp_address clear_color_addr;
+
+ /* Only allowed for simple 2D non-MSAA surfaces */
+ uint32_t tile_x_sa, tile_y_sa;
};
void
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 26bf4426c0..c3a093c400 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -2507,7 +2507,9 @@ blorp_copy(struct blorp_batch *batch,
dst_layer, ISL_FORMAT_UNSUPPORTED, true);
struct brw_blorp_blit_prog_key wm_prog_key = {
- .shader_type = BLORP_SHADER_TYPE_BLIT
+ .shader_type = BLORP_SHADER_TYPE_BLIT,
+ .need_src_offset = src_surf->tile_x_sa || src_surf->tile_y_sa,
+ .need_dst_offset = dst_surf->tile_x_sa || dst_surf->tile_y_sa,
};
const struct isl_format_layout *src_fmtl =
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index 832e8ee26f..4d3125aade 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -438,6 +438,15 @@ blorp_clear(struct blorp_batch *batch,
params.x1 = x1;
params.y1 = y1;
+ if (params.dst.tile_x_sa || params.dst.tile_y_sa) {
+ assert(params.dst.surf.samples == 1);
+ assert(num_layers == 1);
+ params.x0 += params.dst.tile_x_sa;
+ params.y0 += params.dst.tile_y_sa;
+ params.x1 += params.dst.tile_x_sa;
+ params.y1 += params.dst.tile_y_sa;
+ }
+
/* The MinLOD and MinimumArrayElement don't work properly for cube maps.
* Convert them to a single slice on gen4.
*/
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index d7a2cb25c6..8c6d77e1b7 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -152,6 +152,8 @@ blorp_surf_for_miptree(struct brw_context *brw,
.mocs = brw_get_bo_mocs(devinfo, mt->bo),
},
.aux_usage = aux_usage,
+ .tile_x_sa = mt->level[*level].level_x,
+
Mesa (master): i965: Delete the blitter path for CopyTexSubImage
Module: Mesa
Branch: master
Commit: 80fc3896f343c0ddc24e76abc9b0161f75511f3c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=80fc3896f343c0ddc24e76abc9b0161f75511f3c
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri May 11 11:19:06 2018 -0700
i965: Delete the blitter path for CopyTexSubImage
The blorp path (called first) can do anything the blitter path can do so
it's just dead code.
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/intel_tex_copy.c | 58 --
1 file changed, 58 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_tex_copy.c
b/src/mesa/drivers/dri/i965/intel_tex_copy.c
index 5a0e09f255..bc209c605b 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_copy.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_copy.c
@@ -37,61 +37,11 @@
#include "intel_mipmap_tree.h"
#include "intel_fbo.h"
#include "intel_tex.h"
-#include "intel_blit.h"
#include "brw_context.h"
#define FILE_DEBUG_FLAG DEBUG_TEXTURE
-static bool
-intel_copy_texsubimage(struct brw_context *brw,
- struct intel_texture_image *intelImage,
- GLint dstx, GLint dsty, GLint slice,
- struct intel_renderbuffer *irb,
- GLint x, GLint y, GLsizei width, GLsizei height)
-{
- const GLenum internalFormat = intelImage->base.Base.InternalFormat;
-
- if (!intelImage->mt || !irb || !irb->mt) {
- if (unlikely(INTEL_DEBUG & DEBUG_PERF))
-fprintf(stderr, "%s fail %p %p (0x%08x)\n",
-__func__, intelImage->mt, irb, internalFormat);
- return false;
- }
-
- /* No pixel transfer operations (zoom, bias, mapping), just a blit */
- if (brw->ctx._ImageTransferState)
- return false;
-
- intel_prepare_render(brw);
-
- /* glCopyTexSubImage() can be called on a multisampled renderbuffer (if
-* that renderbuffer is associated with the window system framebuffer),
-* however the hardware blitter can't handle this case, so fall back to
-* meta (which can, since it uses ReadPixels).
-*/
- if (irb->Base.Base.NumSamples != 0)
- return false;
-
- /* glCopyTexSubImage() can't be called on a multisampled texture. */
- assert(intelImage->base.Base.NumSamples == 0);
-
- /* account for view parameters and face index */
- int dst_level = intelImage->base.Base.Level +
- intelImage->base.Base.TexObject->MinLevel;
- int dst_slice = slice + intelImage->base.Base.Face +
- intelImage->base.Base.TexObject->MinLayer;
-
- /* blit from src buffer to texture */
- return intel_miptree_blit(brw,
- irb->mt, irb->mt_level, irb->mt_layer,
- x, y, irb->Base.Base.Name == 0,
- intelImage->mt, dst_level, dst_slice,
- dstx, dsty, false,
- width, height, COLOR_LOGICOP_COPY);
-}
-
-
static void
intelCopyTexSubImage(struct gl_context *ctx, GLuint dims,
struct gl_texture_image *texImage,
@@ -107,14 +57,6 @@ intelCopyTexSubImage(struct gl_context *ctx, GLuint dims,
xoffset, yoffset, width, height))
return;
- /* Next, try the BLT engine. */
- if (intel_copy_texsubimage(brw,
- intel_texture_image(texImage),
- xoffset, yoffset, slice,
- intel_renderbuffer(rb), x, y, width, height)) {
- return;
- }
-
/* Finally, fall back to meta. This will likely be slow. */
perf_debug("%s - fallback to swrast\n", __func__);
_mesa_meta_CopyTexSubImage(ctx, dims, texImage,
___
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Mesa (master): i965: Remove ring switching entirely
Module: Mesa
Branch: master
Commit: a347a5a12c2ed98c5959ab2da9ec4c0fcd365aeb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a347a5a12c2ed98c5959ab2da9ec4c0fcd365aeb
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri May 11 18:16:48 2018 -0700
i965: Remove ring switching entirely
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_compute.c | 2 +-
src/mesa/drivers/dri/i965/brw_context.h | 7 --
src/mesa/drivers/dri/i965/brw_draw.c | 2 +-
src/mesa/drivers/dri/i965/brw_misc_state.c| 2 +-
src/mesa/drivers/dri/i965/brw_pipe_control.c | 32 +++---
src/mesa/drivers/dri/i965/brw_urb.c | 2 +-
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 4 +-
src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +-
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 92 ++-
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 15 ++---
src/mesa/drivers/dri/i965/intel_blit.c| 6 +-
11 files changed, 61 insertions(+), 105 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_compute.c
b/src/mesa/drivers/dri/i965/brw_compute.c
index 5ce899bcbc..de08fc3ac1 100644
--- a/src/mesa/drivers/dri/i965/brw_compute.c
+++ b/src/mesa/drivers/dri/i965/brw_compute.c
@@ -182,7 +182,7 @@ brw_dispatch_compute_common(struct gl_context *ctx)
/* Flush the batch if the batch/state buffers are nearly full. We can
* grow them if needed, but this is not free, so we'd like to avoid it.
*/
- intel_batchbuffer_require_space(brw, 600, RENDER_RING);
+ intel_batchbuffer_require_space(brw, 600);
brw_require_statebuffer_space(brw, 2500);
intel_batchbuffer_save_state(brw);
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 773f104824..2613b9fda2 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -461,12 +461,6 @@ struct brw_query_object {
bool flushed;
};
-enum brw_gpu_ring {
- UNKNOWN_RING,
- RENDER_RING,
- BLT_RING,
-};
-
struct brw_reloc_list {
struct drm_i915_gem_relocation_entry *relocs;
int reloc_count;
@@ -497,7 +491,6 @@ struct intel_batchbuffer {
uint32_t *map_next;
uint32_t state_used;
- enum brw_gpu_ring ring;
bool use_shadow_copy;
bool use_batch_first;
bool needs_sol_reset;
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index ae3b7be2dd..18aa12feae 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -798,7 +798,7 @@ brw_draw_single_prim(struct gl_context *ctx,
/* Flush the batch if the batch/state buffers are nearly full. We can
* grow them if needed, but this is not free, so we'd like to avoid it.
*/
- intel_batchbuffer_require_space(brw, 1500, RENDER_RING);
+ intel_batchbuffer_require_space(brw, 1500);
brw_require_statebuffer_space(brw, 2400);
intel_batchbuffer_save_state(brw);
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 6d7ab92cf6..9a663b1d61 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -348,7 +348,7 @@ brw_emit_depthbuffer(struct brw_context *brw)
brw_emit_depth_stall_flushes(brw);
const unsigned ds_dwords = brw->isl_dev.ds.size / 4;
- intel_batchbuffer_begin(brw, ds_dwords, RENDER_RING);
+ intel_batchbuffer_begin(brw, ds_dwords);
uint32_t *ds_map = brw->batch.map_next;
const uint32_t ds_offset = (char *)ds_map - (char *)brw->batch.batch.map;
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index cbd2853f58..122ac26070 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -544,29 +544,17 @@ brw_emit_mi_flush(struct brw_context *brw)
{
const struct gen_device_info *devinfo = >screen->devinfo;
- if (brw->batch.ring == BLT_RING && devinfo->gen >= 6) {
- const unsigned n_dwords = devinfo->gen >= 8 ? 5 : 4;
- BEGIN_BATCH_BLT(n_dwords);
- OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- if (n_dwords == 5)
- OUT_BATCH(0);
- ADVANCE_BATCH();
- } else {
- int flags = PIPE_CONTROL_RENDER_TARGET_FLUSH;
- if (devinfo->gen >= 6) {
- flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
- PIPE_CONTROL_CONST_CACHE_INVALIDATE |
- PIPE_CONTROL_DATA_CACHE_FLUSH |
- PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- PIPE_CONTROL_VF_CACHE_INVALIDATE |
- PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
- PIPE_CONTROL_CS_STALL;
- }
- brw_emit_pipe_control_flush
Mesa (master): i965: Remove some unused includes of intel_blit.h
Module: Mesa Branch: master Commit: e596563b08abab5e70ee22664bc3228c42ea6a7f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e596563b08abab5e70ee22664bc3228c42ea6a7f Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Fri May 11 10:29:28 2018 -0700 i965: Remove some unused includes of intel_blit.h Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/brw_clear.c | 1 - src/mesa/drivers/dri/i965/intel_pixel_read.c | 1 - src/mesa/drivers/dri/i965/intel_tex_image.c| 1 - src/mesa/drivers/dri/i965/intel_tex_validate.c | 1 - 4 files changed, 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c index 24c8b24244..b097dfe346 100644 --- a/src/mesa/drivers/dri/i965/brw_clear.c +++ b/src/mesa/drivers/dri/i965/brw_clear.c @@ -30,7 +30,6 @@ #include "drivers/common/meta.h" #include "intel_batchbuffer.h" -#include "intel_blit.h" #include "intel_fbo.h" #include "intel_mipmap_tree.h" diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c b/src/mesa/drivers/dri/i965/intel_pixel_read.c index cf957378f9..6ed7895bc7 100644 --- a/src/mesa/drivers/dri/i965/intel_pixel_read.c +++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c @@ -39,7 +39,6 @@ #include "brw_blorp.h" #include "intel_screen.h" #include "intel_batchbuffer.h" -#include "intel_blit.h" #include "intel_buffers.h" #include "intel_fbo.h" #include "intel_mipmap_tree.h" diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c index 856216ecf9..fae179214d 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_image.c +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c @@ -21,7 +21,6 @@ #include "intel_buffer_objects.h" #include "intel_batchbuffer.h" #include "intel_tex.h" -#include "intel_blit.h" #include "intel_fbo.h" #include "intel_image.h" #include "intel_tiled_memcpy.h" diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c index eaa60ba0ce..72ce83c7ce 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_validate.c +++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c @@ -29,7 +29,6 @@ #include "brw_context.h" #include "intel_mipmap_tree.h" -#include "intel_blit.h" #include "intel_tex.h" #define FILE_DEBUG_FLAG DEBUG_TEXTURE ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Don't fall back to the blitter in BlitFramebuffer
Module: Mesa Branch: master Commit: 8162256b01f891758d14606ce15a2a9e792ff470 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8162256b01f891758d14606ce15a2a9e792ff470 Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Fri May 11 10:30:16 2018 -0700 i965: Don't fall back to the blitter in BlitFramebuffer On gen4-5, we try the blitter before we even try blorp. On newer platforms, blorp can do everything the blitter can so there's no point in even having the blitter fall-back path. Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/intel_fbo.c | 8 1 file changed, 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index ca4008f8a0..fb84b738c0 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -915,14 +915,6 @@ intel_blit_framebuffer(struct gl_context *ctx, assert(!"Invalid blit"); } - /* Try using the BLT engine. */ - mask = intel_blit_framebuffer_with_blitter(ctx, readFb, drawFb, - srcX0, srcY0, srcX1, srcY1, - dstX0, dstY0, dstX1, dstY1, - mask); - if (mask == 0x0) - return; - _swrast_BlitFramebuffer(ctx, readFb, drawFb, srcX0, srcY0, srcX1, srcY1, dstX0, dstY0, dstX1, dstY1, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Use meta for pixel ops on gen6+
Module: Mesa
Branch: master
Commit: 7fd962093f71d83ffc74962a8f7572b493d9030f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7fd962093f71d83ffc74962a8f7572b493d9030f
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri May 11 16:22:47 2018 -0700
i965: Use meta for pixel ops on gen6+
Using meta for anything is fairly aweful and definitely has more CPU
overhead. However, it also uses the 3D pipe and is therefore likely
faster in terms of GPU time than the blitter. Also, the blitter code
has so many early returns that it's probably not buying us that much.
We may as well just use meta all the time instead of working over-time
to find the tiny case where we can use the blitter. We keep gen4-5
using the old blit paths to avoid perturbing old hardware too much.
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/intel_pixel_bitmap.c | 6 --
src/mesa/drivers/dri/i965/intel_pixel_copy.c | 5 -
src/mesa/drivers/dri/i965/intel_pixel_draw.c | 3 ++-
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
index 5bc341bfc0..f9d4829416 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
@@ -348,11 +348,13 @@ intelBitmap(struct gl_context * ctx,
const struct gl_pixelstore_attrib *unpack,
const GLubyte * pixels)
{
+ struct brw_context *brw = brw_context(ctx);
+
if (!_mesa_check_conditional_render(ctx))
return;
- if (do_blit_bitmap(ctx, x, y, width, height,
- unpack, pixels))
+ if (brw->screen->devinfo.gen < 6 &&
+ do_blit_bitmap(ctx, x, y, width, height, unpack, pixels))
return;
_mesa_meta_Bitmap(ctx, x, y, width, height, unpack, pixels);
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_copy.c
b/src/mesa/drivers/dri/i965/intel_pixel_copy.c
index 8029ffbedd..31838cce13 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_copy.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_copy.c
@@ -196,12 +196,15 @@ intelCopyPixels(struct gl_context * ctx,
GLsizei width, GLsizei height,
GLint destx, GLint desty, GLenum type)
{
+ struct brw_context *brw = brw_context(ctx);
+
DBG("%s\n", __func__);
if (!_mesa_check_conditional_render(ctx))
return;
- if (do_blit_copypixels(ctx, srcx, srcy, width, height, destx, desty, type))
+ if (brw->screen->devinfo.gen < 6 &&
+ do_blit_copypixels(ctx, srcx, srcy, width, height, destx, desty, type))
return;
/* this will use swrast if needed */
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_draw.c
b/src/mesa/drivers/dri/i965/intel_pixel_draw.c
index 82dca4a2eb..d5d1b99e69 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_draw.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_draw.c
@@ -163,7 +163,8 @@ intelDrawPixels(struct gl_context * ctx,
return;
}
- if (_mesa_is_bufferobj(unpack->BufferObj)) {
+ if (brw->screen->devinfo.gen < 6 &&
+ _mesa_is_bufferobj(unpack->BufferObj)) {
if (do_blit_drawpixels(ctx, x, y, width, height, format, type, unpack,
pixels)) {
return;
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Mesa (master): i965/miptree: Use blorp for validation tex copies on gen6+
Module: Mesa
Branch: master
Commit: 0eedb0fca92c4a77ff650e0b565ee254adb7daee
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0eedb0fca92c4a77ff650e0b565ee254adb7daee
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri May 11 12:21:38 2018 -0700
i965/miptree: Use blorp for validation tex copies on gen6+
It's faster than the blitter and can handle things like stencil properly
so it doesn't require software fallbacks.
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 40 +++
1 file changed, 29 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f3c171eb7f..288d4806cb 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1567,6 +1567,7 @@ intel_miptree_copy_slice(struct brw_context *brw,
unsigned dst_level, unsigned dst_layer)
{
+ const struct gen_device_info *devinfo = >screen->devinfo;
mesa_format format = src_mt->format;
unsigned width = minify(src_mt->surf.phys_level0_sa.width,
src_level - src_mt->first_level);
@@ -1579,6 +1580,32 @@ intel_miptree_copy_slice(struct brw_context *brw,
assert(_mesa_get_srgb_format_linear(src_mt->format) ==
_mesa_get_srgb_format_linear(dst_mt->format));
+ DBG("validate blit mt %s %p %d,%d -> mt %s %p %d,%d (%dx%d)\n",
+ _mesa_get_format_name(src_mt->format),
+ src_mt, src_level, src_layer,
+ _mesa_get_format_name(dst_mt->format),
+ dst_mt, dst_level, dst_layer,
+ width, height);
+
+ if (devinfo->gen >= 6) {
+ /* On gen6 and above, we just use blorp. It's faster than the blitter
+ * and can handle everything without software fallbacks.
+ */
+ brw_blorp_copy_miptrees(brw,
+ src_mt, src_level, src_layer,
+ dst_mt, dst_level, dst_layer,
+ 0, 0, 0, 0, width, height);
+
+ if (src_mt->stencil_mt) {
+ assert(dst_mt->stencil_mt);
+ brw_blorp_copy_miptrees(brw,
+ src_mt->stencil_mt, src_level, src_layer,
+ dst_mt->stencil_mt, dst_level, dst_layer,
+ 0, 0, 0, 0, width, height);
+ }
+ return;
+ }
+
if (dst_mt->compressed) {
unsigned int i, j;
_mesa_get_format_block_size(dst_mt->format, , );
@@ -1586,17 +1613,8 @@ intel_miptree_copy_slice(struct brw_context *brw,
width = ALIGN_NPOT(width, i) / i;
}
- /* If it's a packed depth/stencil buffer with separate stencil, the blit
-* below won't apply since we can't do the depth's Y tiling or the
-* stencil's W tiling in the blitter.
-*/
- if (src_mt->stencil_mt) {
- intel_miptree_copy_slice_sw(brw,
- src_mt, src_level, src_layer,
- dst_mt, dst_level, dst_layer,
- width, height);
- return;
- }
+ /* Gen4-5 doesn't support separate stencil */
+ assert(!src_mt->stencil_mt);
uint32_t dst_x, dst_y, src_x, src_y;
intel_miptree_get_image_offset(dst_mt, dst_level, dst_layer,
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Mesa (master): i965: Remove support for the BLT ring
Module: Mesa
Branch: master
Commit: f566a1264c131b5883e5bb0e293a94ef1378c43e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f566a1264c131b5883e5bb0e293a94ef1378c43e
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri May 11 10:09:59 2018 -0700
i965: Remove support for the BLT ring
We still support the blitter on gen4-5 but it's on the same ring as 3D.
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index fe1ea02ca4..4f78d8d050 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -776,18 +776,12 @@ submit_batch(struct brw_context *brw, int in_fence_fd,
int *out_fence_fd)
* To avoid stalling, execobject.offset should match the current
* address of that object within the active context.
*/
- int flags = I915_EXEC_NO_RELOC;
+ assert(devinfo->gen < 6 || batch->ring == RENDER_RING);
+ int flags = I915_EXEC_NO_RELOC | I915_EXEC_RENDER;
- if (devinfo->gen >= 6 && batch->ring == BLT_RING) {
- flags |= I915_EXEC_BLT;
- } else {
- flags |= I915_EXEC_RENDER;
- }
if (batch->needs_sol_reset)
flags |= I915_EXEC_GEN7_SOL_RESET;
- uint32_t hw_ctx = batch->ring == RENDER_RING ? brw->hw_ctx : 0;
-
/* Set statebuffer relocations */
const unsigned state_index = batch->state.bo->index;
if (state_index < batch->exec_count &&
@@ -817,7 +811,7 @@ submit_batch(struct brw_context *brw, int in_fence_fd, int
*out_fence_fd)
batch->validation_list[index] = tmp;
}
- ret = execbuffer(dri_screen->fd, batch, hw_ctx,
+ ret = execbuffer(dri_screen->fd, batch, brw->hw_ctx,
4 * USED_BATCH(*batch),
in_fence_fd, out_fence_fd, flags);
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Mesa (master): i965/miptree: Use blorp for blit maps on gen6+
Module: Mesa
Branch: master
Commit: 33affda8bf6cbcff14d51f6d99635c8f41432cda
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=33affda8bf6cbcff14d51f6d99635c8f41432cda
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri May 11 12:29:07 2018 -0700
i965/miptree: Use blorp for blit maps on gen6+
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 36 +++
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 288d4806cb..ff7a1c00b9 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3087,16 +3087,23 @@ intel_miptree_unmap_blit(struct brw_context *brw,
unsigned int level,
unsigned int slice)
{
+ const struct gen_device_info *devinfo = >screen->devinfo;
struct gl_context *ctx = >ctx;
intel_miptree_unmap_raw(map->linear_mt);
if (map->mode & GL_MAP_WRITE_BIT) {
- bool ok = intel_miptree_copy(brw,
- map->linear_mt, 0, 0, 0, 0,
- mt, level, slice, map->x, map->y,
- map->w, map->h);
- WARN_ONCE(!ok, "Failed to blit from linear temporary mapping");
+ if (devinfo->gen >= 6) {
+ brw_blorp_copy_miptrees(brw, map->linear_mt, 0, 0,
+ mt, level, slice,
+ 0, 0, map->x, map->y, map->w, map->h);
+ } else {
+ bool ok = intel_miptree_copy(brw,
+ map->linear_mt, 0, 0, 0, 0,
+ mt, level, slice, map->x, map->y,
+ map->w, map->h);
+ WARN_ONCE(!ok, "Failed to blit from linear temporary mapping");
+ }
}
intel_miptree_release(>linear_mt);
@@ -3108,6 +3115,7 @@ intel_miptree_map_blit(struct brw_context *brw,
struct intel_miptree_map *map,
unsigned int level, unsigned int slice)
{
+ const struct gen_device_info *devinfo = >screen->devinfo;
map->linear_mt = intel_miptree_create(brw, GL_TEXTURE_2D, mt->format,
/* first_level */ 0,
/* last_level */ 0,
@@ -3127,12 +3135,18 @@ intel_miptree_map_blit(struct brw_context *brw,
* temporary buffer back out.
*/
if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) {
- if (!intel_miptree_copy(brw,
- mt, level, slice, map->x, map->y,
- map->linear_mt, 0, 0, 0, 0,
- map->w, map->h)) {
- fprintf(stderr, "Failed to blit\n");
- goto fail;
+ if (devinfo->gen >= 6) {
+ brw_blorp_copy_miptrees(brw, mt, level, slice,
+ map->linear_mt, 0, 0,
+ map->x, map->y, 0, 0, map->w, map->h);
+ } else {
+ if (!intel_miptree_copy(brw,
+ mt, level, slice, map->x, map->y,
+ map->linear_mt, 0, 0, 0, 0,
+ map->w, map->h)) {
+fprintf(stderr, "Failed to blit\n");
+goto fail;
+ }
}
}
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Mesa (master): i965/blit: Delete intel_emit_linear_blit
Module: Mesa
Branch: master
Commit: a9499374a9f7557daf61adafc0ee14294115af4b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9499374a9f7557daf61adafc0ee14294115af4b
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri May 11 11:49:26 2018 -0700
i965/blit: Delete intel_emit_linear_blit
This function is no longer used.
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/intel_blit.c | 56 --
src/mesa/drivers/dri/i965/intel_blit.h | 6
2 files changed, 62 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b/src/mesa/drivers/dri/i965/intel_blit.c
index dcecab677e..5ef78584ca 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -706,62 +706,6 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw,
return true;
}
-/* We don't have a memmove-type blit like some other hardware, so we'll do a
- * rectangular blit covering a large space, then emit 1-scanline blit at the
- * end to cover the last if we need.
- */
-void
-intel_emit_linear_blit(struct brw_context *brw,
- struct brw_bo *dst_bo,
- unsigned int dst_offset,
- struct brw_bo *src_bo,
- unsigned int src_offset,
- unsigned int size)
-{
- struct gl_context *ctx = >ctx;
- GLuint pitch, height;
- int16_t src_x, dst_x;
- bool ok;
-
- do {
- /* The pitch given to the GPU must be DWORD aligned, and
- * we want width to match pitch. Max width is (1 << 15 - 1),
- * rounding that down to the nearest DWORD is 1 << 15 - 4
- */
- pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 64), 4);
- height = (size < pitch || pitch == 0) ? 1 : size / pitch;
-
- src_x = src_offset % 64;
- dst_x = dst_offset % 64;
- pitch = ALIGN(MIN2(size, (1 << 15) - 64), 4);
- assert(src_x + pitch < 1 << 15);
- assert(dst_x + pitch < 1 << 15);
-
- ok = emit_copy_blit(brw, 1,
- pitch, src_bo, src_offset - src_x,
- ISL_TILING_LINEAR,
- pitch, dst_bo, dst_offset - dst_x,
- ISL_TILING_LINEAR,
- src_x, 0, /* src x/y */
- dst_x, 0, /* dst x/y */
- MIN2(size, pitch), height, /* w, h */
- COLOR_LOGICOP_COPY);
- if (!ok) {
- _mesa_problem(ctx, "Failed to linear blit %dx%d\n",
- MIN2(size, pitch), height);
- return;
- }
-
- pitch *= height;
- if (size <= pitch)
- return;
-
- src_offset += pitch;
- dst_offset += pitch;
- size -= pitch;
- } while (1);
-}
-
/**
* Used to initialize the alpha value of an ARGB miptree after copying
* into it from an XRGB source.
diff --git a/src/mesa/drivers/dri/i965/intel_blit.h
b/src/mesa/drivers/dri/i965/intel_blit.h
index f3ca7b0182..babdfa4ba7 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.h
+++ b/src/mesa/drivers/dri/i965/intel_blit.h
@@ -61,11 +61,5 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw,
GLshort x, GLshort y,
GLshort w, GLshort h,
enum gl_logicop_mode logic_op);
-void intel_emit_linear_blit(struct brw_context *brw,
- struct brw_bo *dst_bo,
- unsigned int dst_offset,
- struct brw_bo *src_bo,
- unsigned int src_offset,
- unsigned int size);
#endif
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Mesa (master): i965/miptree: Move the access_raw call to the individual map functions
Module: Mesa
Branch: master
Commit: b499b85b0f2cc0c82b7c9af91502c2814fdc8e67
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b499b85b0f2cc0c82b7c9af91502c2814fdc8e67
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri May 11 12:34:44 2018 -0700
i965/miptree: Move the access_raw call to the individual map functions
The only function that doesn't need to call access_raw is map_blit. If
it takes the blitter path, it will happen as part of intel_miptree_copy.
If map_blit takes the blorp path, brw_blorp_copy_miptrees will handle
doing whatever resolves are needed. This should save us resolves in
quite a few cases and will probably help performance a bit.
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index ff7a1c00b9..7d1fa96b91 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3053,6 +3053,9 @@ intel_miptree_map_gtt(struct brw_context *brw,
y /= bh;
x /= bw;
+ intel_miptree_access_raw(brw, mt, level, slice,
+map->mode & GL_MAP_WRITE_BIT);
+
base = intel_miptree_map_raw(brw, mt, map->mode);
if (base == NULL)
@@ -3191,6 +3194,8 @@ intel_miptree_map_movntdqa(struct brw_context *brw,
assert(map->mode & GL_MAP_READ_BIT);
assert(!(map->mode & GL_MAP_WRITE_BIT));
+ intel_miptree_access_raw(brw, mt, level, slice, false);
+
DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__,
map->x, map->y, map->w, map->h,
mt, _mesa_get_format_name(mt->format),
@@ -3285,6 +3290,9 @@ intel_miptree_map_s8(struct brw_context *brw,
if (!map->buffer)
return;
+ intel_miptree_access_raw(brw, mt, level, slice,
+map->mode & GL_MAP_WRITE_BIT);
+
/* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
* INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
* invalidate is set, since we'll be writing the whole rectangle from our
@@ -3367,6 +3375,8 @@ intel_miptree_map_etc(struct brw_context *brw,
assert(map->mode & GL_MAP_WRITE_BIT);
assert(map->mode & GL_MAP_INVALIDATE_RANGE_BIT);
+ intel_miptree_access_raw(brw, mt, level, slice, true);
+
map->stride = _mesa_format_row_stride(mt->etc_format, map->w);
map->buffer = malloc(_mesa_format_image_size(mt->etc_format,
map->w, map->h, 1));
@@ -3460,6 +3470,9 @@ intel_miptree_map_depthstencil(struct brw_context *brw,
if (!map->buffer)
return;
+ intel_miptree_access_raw(brw, mt, level, slice,
+map->mode & GL_MAP_WRITE_BIT);
+
/* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
* INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
* invalidate is set, since we'll be writing the whole rectangle from our
@@ -3641,9 +3654,6 @@ intel_miptree_map(struct brw_context *brw,
return;
}
- intel_miptree_access_raw(brw, mt, level, slice,
-map->mode & GL_MAP_WRITE_BIT);
-
if (mt->format == MESA_FORMAT_S_UINT8) {
intel_miptree_map_s8(brw, mt, map, level, slice);
} else if (mt->etc_format != MESA_FORMAT_NONE &&
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Mesa (master): intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0
Module: Mesa
Branch: master
Commit: 417b9e5770436008a7f00cfaffe9ddf4c5a13502
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=417b9e5770436008a7f00cfaffe9ddf4c5a13502
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri May 18 20:04:12 2018 -0700
intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0
Fixes: d6cd14f2131a5b "i965/fs: Define new shader opcode to..."
Reviewed-by: Jose Maria Casanova Crespo <jmcasan...@igalia.com>
---
src/intel/compiler/brw_eu_emit.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index ee5a048bca..6d81c636f2 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -3713,6 +3713,7 @@ brw_rounding_mode(struct brw_codegen *p,
if (bits != BRW_CR0_RND_MODE_MASK) {
brw_inst *inst = brw_AND(p, brw_cr0_reg(0), brw_cr0_reg(0),
brw_imm_ud(~BRW_CR0_RND_MODE_MASK));
+ brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1);
/* From the Skylake PRM, Volume 7, page 760:
* "Implementation Restriction on Register Access: When the control
@@ -3727,6 +3728,7 @@ brw_rounding_mode(struct brw_codegen *p,
if (bits) {
brw_inst *inst = brw_OR(p, brw_cr0_reg(0), brw_cr0_reg(0),
brw_imm_ud(bits));
+ brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1);
brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH);
}
}
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Mesa (master): intel/blorp: Use linear formats for CCS_E clear colors in copies
Module: Mesa Branch: master Commit: 18f8200a994440faa9fb9e80e99e8140ea912993 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=18f8200a994440faa9fb9e80e99e8140ea912993 Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Fri May 11 15:02:13 2018 -0700 intel/blorp: Use linear formats for CCS_E clear colors in copies It's clear that the original code meant to do this and there is even a 10-line comment explaining why. Originally, we had a simple function for packing the clear colors which was unaware of sRGB. However, in a6b66a7b26ae1, when we started using ISL to do the packing, the wrong format was used. Fixes: a6b66a7b26 "intel/blorp: Use ISL instead of bitcast_color..." Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/blorp/blorp_blit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c index e825862d71..26bf4426c0 100644 --- a/src/intel/blorp/blorp_blit.c +++ b/src/intel/blorp/blorp_blit.c @@ -2562,7 +2562,7 @@ blorp_copy(struct blorp_batch *batch, params.src.view.format)); uint32_t packed[4]; isl_color_value_pack(_color, - params.src.surf.format, packed); + linear_src_format, packed); isl_color_value_unpack(_color, params.src.view.format, packed); } @@ -2576,7 +2576,7 @@ blorp_copy(struct blorp_batch *batch, params.dst.view.format)); uint32_t packed[4]; isl_color_value_pack(_color, - params.dst.surf.format, packed); + linear_dst_format, packed); isl_color_value_unpack(_color, params.dst.view.format, packed); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv,nir: add generated files to .gitignore(s)
Module: Mesa Branch: master Commit: c879011c72cd6f088bf917497f5689db5bd5bda5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c879011c72cd6f088bf917497f5689db5bd5bda5 Author: Rhys Perry <pendingchao...@gmail.com> Date: Fri May 11 13:12:05 2018 +0100 anv,nir: add generated files to .gitignore(s) Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/compiler/nir/.gitignore | 2 ++ src/intel/vulkan/.gitignore | 1 + 2 files changed, 3 insertions(+) diff --git a/src/compiler/nir/.gitignore b/src/compiler/nir/.gitignore index 64828eba6d..8faf93f0b2 100644 --- a/src/compiler/nir/.gitignore +++ b/src/compiler/nir/.gitignore @@ -3,3 +3,5 @@ nir_opt_algebraic.c nir_opcodes.c nir_opcodes.h nir_constant_expressions.c +nir_intrinsics.c +nir_intrinsics.h diff --git a/src/intel/vulkan/.gitignore b/src/intel/vulkan/.gitignore index 4ea978d6e4..b84b17134f 100644 --- a/src/intel/vulkan/.gitignore +++ b/src/intel/vulkan/.gitignore @@ -1,5 +1,6 @@ # Generated source files /anv_extensions.c +/anv_extensions.h /anv_entrypoints.c /anv_entrypoints.h /anv_timestamp.h ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel/isl/storage: Don't lower most UNORM formats on gen11+
Module: Mesa Branch: master Commit: b784561c1a0c518f2e7bfe8fcb7b9b900d427bcb URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b784561c1a0c518f2e7bfe8fcb7b9b900d427bcb Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Mon May 7 14:47:06 2018 -0700 intel/isl/storage: Don't lower most UNORM formats on gen11+ Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com> Tested-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/intel/isl/isl_storage_image.c | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/src/intel/isl/isl_storage_image.c b/src/intel/isl/isl_storage_image.c index 20f6fd5faf..ed1c6008ae 100644 --- a/src/intel/isl/isl_storage_image.c +++ b/src/intel/isl/isl_storage_image.c @@ -161,32 +161,36 @@ isl_lower_storage_image_format(const struct gen_device_info *devinfo, /* No normalized fixed-point formats are supported by the hardware. */ case ISL_FORMAT_R16G16B16A16_UNORM: case ISL_FORMAT_R16G16B16A16_SNORM: - return (devinfo->gen >= 8 || devinfo->is_haswell ? + return (devinfo->gen >= 11 ? format : + devinfo->gen >= 8 || devinfo->is_haswell ? ISL_FORMAT_R16G16B16A16_UINT : ISL_FORMAT_R32G32_UINT); case ISL_FORMAT_R8G8B8A8_UNORM: case ISL_FORMAT_R8G8B8A8_SNORM: - return (devinfo->gen >= 8 || devinfo->is_haswell ? + return (devinfo->gen >= 11 ? format : + devinfo->gen >= 8 || devinfo->is_haswell ? ISL_FORMAT_R8G8B8A8_UINT : ISL_FORMAT_R32_UINT); case ISL_FORMAT_R16G16_UNORM: case ISL_FORMAT_R16G16_SNORM: - return (devinfo->gen >= 8 || devinfo->is_haswell ? + return (devinfo->gen >= 11 ? format : + devinfo->gen >= 8 || devinfo->is_haswell ? ISL_FORMAT_R16G16_UINT : ISL_FORMAT_R32_UINT); case ISL_FORMAT_R8G8_UNORM: case ISL_FORMAT_R8G8_SNORM: - return (devinfo->gen >= 8 || devinfo->is_haswell ? + return (devinfo->gen >= 11 ? format : + devinfo->gen >= 8 || devinfo->is_haswell ? ISL_FORMAT_R8G8_UINT : ISL_FORMAT_R16_UINT); case ISL_FORMAT_R16_UNORM: case ISL_FORMAT_R16_SNORM: - return ISL_FORMAT_R16_UINT; + return (devinfo->gen >= 11 ? format : ISL_FORMAT_R16_UINT); case ISL_FORMAT_R8_UNORM: case ISL_FORMAT_R8_SNORM: - return ISL_FORMAT_R8_UINT; + return (devinfo->gen >= 11 ? format : ISL_FORMAT_R8_UINT); default: assert(!"Unknown image format"); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel/isl: Several UNORM formats support typed writes on gen11+
Module: Mesa
Branch: master
Commit: 399962e7c6282837f7999c98b076f1d5ca477a11
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=399962e7c6282837f7999c98b076f1d5ca477a11
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Mon May 7 14:44:20 2018 -0700
intel/isl: Several UNORM formats support typed writes on gen11+
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
Tested-by: Anuj Phogat <anuj.pho...@gmail.com>
---
src/intel/isl/isl_format.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
index 37d2243a46..52997cf2eb 100644
--- a/src/intel/isl/isl_format.c
+++ b/src/intel/isl/isl_format.c
@@ -117,8 +117,8 @@ static const struct surface_format_info format_info[] = {
SF( x, x, x, x, x, x, Y, x, x, x, x, x,
R32G32B32_SSCALED)
SF( x, x, x, x, x, x, Y, x, x, x, x, x,
R32G32B32_USCALED)
SF( x, x, x, x, x, x, 75, x, x, x, x, x,
R32G32B32_SFIXED)
- SF( Y, Y, x, x, Y, 45, Y, x, 60, 70, x, 90,
R16G16B16A16_UNORM)
- SF( Y, Y, x, x, Y, 60, Y, x, x, 70, x, 90,
R16G16B16A16_SNORM)
+ SF( Y, Y, x, x, Y, 45, Y, x, 60, 70, 110, 90,
R16G16B16A16_UNORM)
+ SF( Y, Y, x, x, Y, 60, Y, x, x, 70, 110, 90,
R16G16B16A16_SNORM)
SF( Y, x, x, x, Y, x, Y, x, x, 70, 90, 90,
R16G16B16A16_SINT)
SF( Y, x, x, x, Y, x, Y, x, x, 70, 75, 90,
R16G16B16A16_UINT)
SF( Y, Y, x, x, Y, Y, Y, x, x, 70, 90, 90,
R16G16B16A16_FLOAT)
@@ -150,13 +150,13 @@ static const struct surface_format_info format_info[] = {
SF( Y, Y, x, x, x, x, x, x, 60, x, x, x,
R10G10B10A2_UNORM_SRGB)
SF( Y, x, x, x, Y, x, Y, x, x, 70, x, 100,
R10G10B10A2_UINT)
SF( Y, Y, x, x, x, x, Y, x, x, x, x, x,
R10G10B10_SNORM_A2_UNORM)
- SF( Y, Y, x, x, Y, Y, Y, x, 60, 70, x, 90,
R8G8B8A8_UNORM)
+ SF( Y, Y, x, x, Y, Y, Y, x, 60, 70, 110, 90,
R8G8B8A8_UNORM)
SF( Y, Y, x, x, Y, Y, x, x, 60, x, x, 100,
R8G8B8A8_UNORM_SRGB)
- SF( Y, Y, x, x, Y, 60, Y, x, x, 70, x, 90,
R8G8B8A8_SNORM)
+ SF( Y, Y, x, x, Y, 60, Y, x, x, 70, 110, 90,
R8G8B8A8_SNORM)
SF( Y, x, x, x, Y, x, Y, x, x, 70, 90, 90,
R8G8B8A8_SINT)
SF( Y, x, x, x, Y, x, Y, x, x, 70, 75, 90,
R8G8B8A8_UINT)
- SF( Y, Y, x, x, Y, 45, Y, x, x, 70, x, 90,
R16G16_UNORM)
- SF( Y, Y, x, x, Y, 60, Y, x, x, 70, x, 90,
R16G16_SNORM)
+ SF( Y, Y, x, x, Y, 45, Y, x, x, 70, 110, 90,
R16G16_UNORM)
+ SF( Y, Y, x, x, Y, 60, Y, x, x, 70, 110, 90,
R16G16_SNORM)
SF( Y, x, x, x, Y, x, Y, x, x, 70, 90, 90,
R16G16_SINT)
SF( Y, x, x, x, Y, x, Y, x, x, 70, 75, 90,
R16G16_UINT)
SF( Y, Y, x, x, Y, Y, Y, x, x, 70, 90, 90,
R16G16_FLOAT)
@@ -198,12 +198,12 @@ static const struct surface_format_info format_info[] = {
SF( Y, Y, x, x, Y, Y, x, x, x, x, x, x,
B5G5R5A1_UNORM_SRGB)
SF( Y, Y, x, Y, Y, Y, x, x, x, 70, x, x,
B4G4R4A4_UNORM)
SF( Y, Y, x, x, Y, Y, x, x, x, x, x, x,
B4G4R4A4_UNORM_SRGB)
- SF( Y, Y, x, x, Y, Y, Y, x, x, 70, x, x, R8G8_UNORM)
- SF( Y, Y, x, Y, Y, 60, Y, x, x, 70, x, x, R8G8_SNORM)
+ SF( Y, Y, x, x, Y, Y, Y, x, x, 70, 110, x, R8G8_UNORM)
+ SF( Y, Y, x, Y, Y, 60, Y, x, x, 70, 110, x, R8G8_SNORM)
SF( Y, x, x, x, Y, x, Y, x, x, 70, 90, x, R8G8_SINT)
SF( Y, x, x, x, Y, x, Y, x, x, 70, 75, x, R8G8_UINT)
- SF( Y, Y, Y, x, Y, 45, Y, x, 70, 70, x, x, R16_UNORM)
- SF( Y, Y, x, x, Y, 60, Y, x, x, 70, x, x, R16_SNORM)
+ SF( Y, Y, Y, x, Y, 45, Y, x, 70, 70, 110, x, R16_UNORM)
+ SF( Y, Y, x, x, Y, 60, Y, x, x, 70, 110, x, R16_SNORM)
SF( Y, x, x, x, Y, x, Y, x, x, 70, 90, x, R16_SINT)
SF( Y, x, x, x, Y, x, Y, x, x, 70, 75, x, R16_UINT)
SF( Y, Y, x, x, Y, Y, Y, x, x, 70, 90, x, R16_FLOAT)
@@ -235,11 +235,11 @@ static const struct surface_format_info format_info[] = {
SF( 80, 80, x, x, 90, x, x, x, x, x, x, x,
A4B4G4R4_UNORM)
SF( 90, x, x, x, x, x, x, x, x, x, x, x, L8A8_UINT)
SF( 90, x, x, x, x, x, x,
Mesa (master): i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL
Module: Mesa
Branch: master
Commit: a8a740f272a808a2694524b43fc33d2f0c0e3709
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8a740f272a808a2694524b43fc33d2f0c0e3709
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Wed May 9 15:06:13 2018 -0700
i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL
From the bspec docs for "Indirect State Pointers Disable":
"At the completion of the post-sync operation associated with this
pipe control packet, the indirect state pointers in the hardware are
considered invalid"
So the ISP disable is a post-sync type of operation which means that it
should be combined with a CS stall. Without this, the simulator throws
an error.
Fixes: 766d801ca "anv: emit pixel scoreboard stall before ISP disable"
Fixes: f536097f6 "i965: require pixel scoreboard stall prior to ISP disable"
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
src/intel/vulkan/genX_cmd_buffer.c | 1 +
src/mesa/drivers/dri/i965/brw_pipe_control.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 526e18af10..afccad8ef8 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1434,6 +1434,7 @@ emit_isp_disable(struct anv_cmd_buffer *cmd_buffer)
}
anv_batch_emit(_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.IndirectStatePointersDisable = true;
+ pc.CommandStreamerStallEnable = true;
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 879bfb660e..e31d625ddb 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -362,7 +362,8 @@ gen10_emit_isp_disable(struct brw_context *brw)
PIPE_CONTROL_CS_STALL,
NULL, 0, 0);
brw_emit_pipe_control(brw,
- PIPE_CONTROL_ISP_DIS,
+ PIPE_CONTROL_ISP_DIS |
+ PIPE_CONTROL_CS_STALL,
NULL, 0, 0);
brw->vs.base.push_constants_dirty = true;
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Mesa (master): 28 new commits
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=561348caa14a849dd50ed1df1d8f7abba7de66f7 Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Fri Jan 26 11:43:24 2018 -0800 intel/isl: Allow CCS_E on 1010102 formats On CNL and above, CCS_E supports 1010102 formats and R11G11B10F. We had shut them off during early enabling because blorp_copy couldn't handle them. Now it can handle 1010102 formats so we can turn them back on. Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ccb44b8a94654fc827eda784653e607062de3ca1 Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Fri Jan 26 11:42:35 2018 -0800 intel/blorp: Allow CCS copies of 1010102 formats Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1978de66f7160b5af8eac8041dfa8c4e0ec3bb83 Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Fri Jan 26 11:41:02 2018 -0800 intel/blorp: Add support for more format bitcasting nir_format_bitcast_uint_vec_unmasked can only be used to cast between formats with uniform channel sizes. In particular, it cannot handle 10_10_10_2 formats. By making use of the NIR helper for uint vector casts, we should now be able to bitcast between any two uint formats so long as their channels are in RGBA order (possibly with channels missing). In order to do this we need to rework the key a bit to pass the actual formats instead of just the number of bits in each. Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7998fe268e727c49388aeed854bc0d6ff1ef6a89 Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Fri Jan 26 11:35:04 2018 -0800 intel/blorp: Use nir_format_bitcast_uint_vec_unmasked Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=047e68389f0aa56213503e99d31d5357284acdde Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Fri Jan 26 11:34:04 2018 -0800 nir/format_convert: Add code for bitcasting vectors This is a fairly direct port from blorp. The only real change is that the nir_format_convert version doesn't assume that everything is a vec4. Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a6b66a7b26ae1cc01355d3ccfaa604a5c8e1dae5 Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Fri Jan 26 10:44:51 2018 -0800 intel/blorp: Use ISL instead of bitcast_color_value_to_uint Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=09ced6542049986f7fe52af8087aec9fc23d9f16 Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Thu Jun 22 18:45:24 2017 -0700 intel/isl: Add format conversion code This adds helpers to ISL to convert an isl_color_value to and from binary data encoded with a given isl_format. The conversion is done using ISL's built-in format introspection so it's fairly slow as format conversions go but it should be fine for a single pixel value. In particular, we can use this to convert clear colors. As a side-effect, we now rely on the sRGB helpers in libmesautil so we need to tweak the build system a bit. All prior uses of src/util in ISL were header-only. Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8152c60e012605df2ac3a3522974e17c2362b770 Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Thu Jun 22 23:18:06 2017 -0700 intel/isl/format: Get rid of the ALPHA colorspace Alpha-only formats are just linear. There's no need to specially deliminate them as being in their own colorspace. Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ab73790efbce705c84c5fd6e598d91ffe02b579 Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Thu Jun 22 17:12:36 2017 -0700 intel/isl/format: Add field locations informations to channel_layout Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=96598fbc02d2277a923d10aad168a7a3be0fb08b Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Thu Jun 22 16:52:56 2017 -0700 intel/isl/format: Add a column for channel order to the table Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d08d6a3da88aa3a07e0c867428c93ab7be23c9e4 Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Fri J
Mesa (master): i965: Move brw_emit_depth_stencil_hiz higher up in the file
Module: Mesa
Branch: master
Commit: 96f01501d7a5f5242cba8641a2f20e965ce3aa94
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=96f01501d7a5f5242cba8641a2f20e965ce3aa94
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri May 4 22:46:49 2018 -0700
i965: Move brw_emit_depth_stencil_hiz higher up in the file
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 90 +-
1 file changed, 40 insertions(+), 50 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index e44baf2518..03535f689e 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -262,7 +262,46 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
struct intel_mipmap_tree *stencil_mt,
bool hiz, bool separate_stencil,
uint32_t width, uint32_t height,
- uint32_t tile_x, uint32_t tile_y);
+ uint32_t tile_x, uint32_t tile_y)
+{
+ (void)hiz;
+ (void)separate_stencil;
+ (void)stencil_mt;
+
+ assert(!hiz);
+ assert(!separate_stencil);
+
+ const struct gen_device_info *devinfo = >screen->devinfo;
+ const unsigned len = (devinfo->is_g4x || devinfo->gen == 5) ? 6 : 5;
+
+ BEGIN_BATCH(len);
+ OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
+ OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
+ (depthbuffer_format << 18) |
+ (BRW_TILEWALK_YMAJOR << 26) |
+ (1 << 27) |
+ (depth_surface_type << 29));
+
+ if (depth_mt) {
+ OUT_RELOC(depth_mt->bo, RELOC_WRITE, depth_offset);
+ } else {
+ OUT_BATCH(0);
+ }
+
+ OUT_BATCH(((width + tile_x - 1) << 6) |
+ ((height + tile_y - 1) << 19));
+ OUT_BATCH(0);
+
+ if (devinfo->is_g4x || devinfo->gen >= 5)
+ OUT_BATCH(tile_x | (tile_y << 16));
+ else
+ assert(tile_x == 0 && tile_y == 0);
+
+ if (devinfo->gen >= 6)
+ OUT_BATCH(0);
+
+ ADVANCE_BATCH();
+}
void
brw_emit_depthbuffer(struct brw_context *brw)
@@ -469,55 +508,6 @@ brw_emit_depthbuffer(struct brw_context *brw)
brw->no_depth_or_stencil = !depth_mt && !stencil_mt;
}
-static void
-brw_emit_depth_stencil_hiz(struct brw_context *brw,
- struct intel_mipmap_tree *depth_mt,
- uint32_t depth_offset, uint32_t depthbuffer_format,
- uint32_t depth_surface_type,
- struct intel_mipmap_tree *stencil_mt,
- bool hiz, bool separate_stencil,
- uint32_t width, uint32_t height,
- uint32_t tile_x, uint32_t tile_y)
-{
- (void)hiz;
- (void)separate_stencil;
- (void)stencil_mt;
-
- assert(!hiz);
- assert(!separate_stencil);
-
- const struct gen_device_info *devinfo = >screen->devinfo;
- const unsigned len = (devinfo->is_g4x || devinfo->gen == 5) ? 6 : 5;
-
- BEGIN_BATCH(len);
- OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
- OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
- (depthbuffer_format << 18) |
- (BRW_TILEWALK_YMAJOR << 26) |
- (1 << 27) |
- (depth_surface_type << 29));
-
- if (depth_mt) {
- OUT_RELOC(depth_mt->bo, RELOC_WRITE, depth_offset);
- } else {
- OUT_BATCH(0);
- }
-
- OUT_BATCH(((width + tile_x - 1) << 6) |
- ((height + tile_y - 1) << 19));
- OUT_BATCH(0);
-
- if (devinfo->is_g4x || devinfo->gen >= 5)
- OUT_BATCH(tile_x | (tile_y << 16));
- else
- assert(tile_x == 0 && tile_y == 0);
-
- if (devinfo->gen >= 6)
- OUT_BATCH(0);
-
- ADVANCE_BATCH();
-}
-
const struct brw_tracked_state brw_depthbuffer = {
.dirty = {
.mesa = _NEW_BUFFERS,
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Mesa (master): i965/miptree: Remove redundant fields from intel_miptree_aux_buffer
Module: Mesa
Branch: master
Commit: 06d3841882ffd575452aee30bfd051a0830cb4db
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=06d3841882ffd575452aee30bfd051a0830cb4db
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri May 4 16:49:47 2018 -0700
i965/miptree: Remove redundant fields from intel_miptree_aux_buffer
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 19 +++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 25 -
2 files changed, 7 insertions(+), 37 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index b9a564552d..67086ee6c0 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -994,9 +994,6 @@ create_ccs_buf_for_image(struct brw_context *brw,
brw_bo_reference(image->bo);
mt->aux_buf->offset = image->aux_offset;
- mt->aux_buf->size = image->bo->size - image->aux_offset;
- mt->aux_buf->pitch = image->aux_pitch;
- mt->aux_buf->qpitch = 0;
mt->aux_buf->surf = temp_ccs_surf;
return true;
@@ -1683,7 +1680,7 @@ intel_miptree_init_mcs(struct brw_context *brw,
return;
}
void *data = map;
- memset(data, init_value, mt->aux_buf->size);
+ memset(data, init_value, mt->aux_buf->surf.size);
brw_bo_unmap(mt->aux_buf->bo);
}
@@ -1698,7 +1695,7 @@ intel_alloc_aux_buffer(struct brw_context *brw,
if (!buf)
return false;
- buf->size = aux_surf->size;
+ uint64_t size = aux_surf->size;
const struct gen_device_info *devinfo = >screen->devinfo;
if (devinfo->gen >= 10) {
@@ -1706,19 +1703,17 @@ intel_alloc_aux_buffer(struct brw_context *brw,
* will set a pointer to a dword somewhere that contains the color. So,
* allocate the space for the clear color value here on the aux buffer.
*/
- buf->clear_color_offset = buf->size;
- buf->size += brw->isl_dev.ss.clear_color_state_size;
+ buf->clear_color_offset = size;
+ size += brw->isl_dev.ss.clear_color_state_size;
}
- buf->pitch = aux_surf->row_pitch;
- buf->qpitch = isl_surf_get_array_pitch_sa_rows(aux_surf);
-
/* ISL has stricter set of alignment rules then the drm allocator.
* Therefore one can pass the ISL dimensions in terms of bytes instead of
* trying to recalculate based on different format block sizes.
*/
- buf->bo = brw_bo_alloc_tiled(brw->bufmgr, name, buf->size,
-I915_TILING_Y, buf->pitch, alloc_flags);
+ buf->bo = brw_bo_alloc_tiled(brw->bufmgr, name, size,
+I915_TILING_Y, aux_surf->row_pitch,
+alloc_flags);
if (!buf->bo) {
free(buf);
return NULL;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 8cea562dfa..9adcc5ab0c 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -162,31 +162,6 @@ struct intel_miptree_aux_buffer
*/
uint32_t offset;
- /*
-* Size of the MCS surface.
-*
-* This is needed when doing any gtt mapped operations on the buffer (which
-* will be Y-tiled). It is possible that it will not be the same as bo->size
-* when the drm allocator rounds up the requested size.
-*/
- size_t size;
-
- /**
-* Pitch in bytes.
-*
-* @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
-* @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
-*/
- uint32_t pitch;
-
- /**
-* The distance in rows between array slices.
-*
-* @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch
-* @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
-*/
- uint32_t qpitch;
-
/**
* Buffer object containing the indirect clear color.
*
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Mesa (master): i965: Use the brw_depthbuffer atom on all gens
Module: Mesa
Branch: master
Commit: ccd3dce3c059ad6d24ab50107ac6bb8827f46c3d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ccd3dce3c059ad6d24ab50107ac6bb8827f46c3d
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri May 4 22:41:19 2018 -0700
i965: Use the brw_depthbuffer atom on all gens
The only reason why we had two atoms was that the one we used for gen7+
depended on _NEW_DEPTH and _NEW_STENCIL as well as _NEW_BUFFERS. Since
this is no longer true, we can combine them into one atom. We do add a
dependence on BRW_NEW_AUX_STATE but that should never get set on gen4-5
so adding it is a no-op for those platforms.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_misc_state.c| 3 ++-
src/mesa/drivers/dri/i965/brw_state.h | 1 -
src/mesa/drivers/dri/i965/gen7_misc_state.c | 13 -
src/mesa/drivers/dri/i965/genX_state_upload.c | 4 ++--
4 files changed, 4 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 05517ebf58..0ab1f12801 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -410,7 +410,8 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
const struct brw_tracked_state brw_depthbuffer = {
.dirty = {
.mesa = _NEW_BUFFERS,
- .brw = BRW_NEW_BATCH |
+ .brw = BRW_NEW_AUX_STATE |
+ BRW_NEW_BATCH |
BRW_NEW_BLORP,
},
.emit = brw_emit_depthbuffer,
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 0417cc2aae..f89182a001 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -89,7 +89,6 @@ extern const struct brw_tracked_state gen6_sampler_state;
extern const struct brw_tracked_state gen6_sol_surface;
extern const struct brw_tracked_state gen6_sf_vp;
extern const struct brw_tracked_state gen6_urb;
-extern const struct brw_tracked_state gen7_depthbuffer;
extern const struct brw_tracked_state gen7_l3_state;
extern const struct brw_tracked_state gen7_push_constant_space;
extern const struct brw_tracked_state gen7_urb;
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 42ab271e6a..5c88cf55fa 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -186,16 +186,3 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
brw->no_depth_or_stencil = !mt;
}
-
-/**
- * \see brw_context.state.depth_region
- */
-const struct brw_tracked_state gen7_depthbuffer = {
- .dirty = {
- .mesa = _NEW_BUFFERS,
- .brw = BRW_NEW_AUX_STATE |
- BRW_NEW_BATCH |
- BRW_NEW_BLORP,
- },
- .emit = brw_emit_depthbuffer,
-};
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index b1867c1a1c..091e4137aa 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -5603,7 +5603,7 @@ genX(init_atoms)(struct brw_context *brw)
(scissor_state),
- _depthbuffer,
+ _depthbuffer,
(polygon_stipple),
(polygon_stipple_offset),
@@ -5694,7 +5694,7 @@ genX(init_atoms)(struct brw_context *brw)
(scissor_state),
- _depthbuffer,
+ _depthbuffer,
(polygon_stipple),
(polygon_stipple_offset),
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Mesa (master): i965: Always set depth/stencil write enables on gen7+
Module: Mesa
Branch: master
Commit: 514bb6f41ec139baeaf56b57d7bc1034fb114234
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=514bb6f41ec139baeaf56b57d7bc1034fb114234
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Mon May 7 10:57:49 2018 -0700
i965: Always set depth/stencil write enables on gen7+
The hardware will AND these fields with the corresponding fields in
DEPTH_STENCIL_STATE so there's no real reason to toggle them on and off
based on state bits. This removes our reliance on the _NEW_DEPTH and
_NEW_STENCIL state bits and better matches what ISL does.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/gen7_misc_state.c | 8 +++-
src/mesa/drivers/dri/i965/gen8_depth_state.c | 9 +++--
2 files changed, 6 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index e3a355fae3..42ab271e6a 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -109,8 +109,8 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
(depthbuffer_format << 18) |
((hiz ? 1 : 0) << 22) |
- ((stencil_mt != NULL && brw->stencil_write_enabled) << 27) |
- (brw_depth_writes_enabled(brw) << 28) |
+ ((stencil_mt != NULL) << 27) | /* Stencil Write Enable */
+ ((depth_mt != NULL) << 28) | /* Depth Write Enable */
(surftype << 29));
/* 3DSTATE_DEPTH_BUFFER dw2 */
@@ -192,9 +192,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
*/
const struct brw_tracked_state gen7_depthbuffer = {
.dirty = {
- .mesa = _NEW_BUFFERS |
- _NEW_DEPTH |
- _NEW_STENCIL,
+ .mesa = _NEW_BUFFERS,
.brw = BRW_NEW_AUX_STATE |
BRW_NEW_BATCH |
BRW_NEW_BLORP,
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 1c77218d2b..a00e22a686 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -39,9 +39,7 @@ emit_depth_packets(struct brw_context *brw,
struct intel_mipmap_tree *depth_mt,
uint32_t depthbuffer_format,
uint32_t depth_surface_type,
- bool depth_writable,
struct intel_mipmap_tree *stencil_mt,
- bool stencil_writable,
bool hiz,
uint32_t width,
uint32_t height,
@@ -64,8 +62,8 @@ emit_depth_packets(struct brw_context *brw,
BEGIN_BATCH(8);
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (8 - 2));
OUT_BATCH(depth_surface_type << 29 |
- (depth_writable ? (1 << 28) : 0) |
- (stencil_mt != NULL && stencil_writable) << 27 |
+ (depth_mt != NULL) << 28 | /* Depth Write Enable */
+ (stencil_mt != NULL) << 27 | /* Stencil Write Enable */
(hiz ? 1 : 0) << 22 |
depthbuffer_format << 18 |
(depth_mt ? depth_mt->surf.row_pitch - 1 : 0));
@@ -204,8 +202,7 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
}
emit_depth_packets(brw, depth_mt, brw_depthbuffer_format(brw), surftype,
- brw_depth_writes_enabled(brw),
- stencil_mt, brw->stencil_write_enabled,
+ stencil_mt,
hiz, width, height, depth, lod, min_array_element);
}
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Mesa (master): i965: Simplify brw_emit_depthbuffer and brw_emit_depth_stencil_hiz
Module: Mesa
Branch: master
Commit: 4f4779b367900ab2c2e892ab0f05e8ff62289fe2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f4779b367900ab2c2e892ab0f05e8ff62289fe2
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri May 4 22:57:09 2018 -0700
i965: Simplify brw_emit_depthbuffer and brw_emit_depth_stencil_hiz
Now that we're using ISL, a good chunk of brw_emit_depthstencil is
pointless checks which ISL will do for us anyway. Since we only have
one manual depth buffer emit function, move the useful bits into it.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 107 +++--
1 file changed, 26 insertions(+), 81 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 03535f689e..6d7ab92cf6 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -256,20 +256,33 @@ brw_workaround_depthstencil_alignment(struct brw_context
*brw,
static void
brw_emit_depth_stencil_hiz(struct brw_context *brw,
+ struct intel_renderbuffer *depth_irb,
struct intel_mipmap_tree *depth_mt,
- uint32_t depth_offset, uint32_t depthbuffer_format,
- uint32_t depth_surface_type,
- struct intel_mipmap_tree *stencil_mt,
- bool hiz, bool separate_stencil,
- uint32_t width, uint32_t height,
- uint32_t tile_x, uint32_t tile_y)
+ struct intel_renderbuffer *stencil_irb,
+ struct intel_mipmap_tree *stencil_mt)
{
- (void)hiz;
- (void)separate_stencil;
- (void)stencil_mt;
+ uint32_t tile_x = brw->depthstencil.tile_x;
+ uint32_t tile_y = brw->depthstencil.tile_y;
+ uint32_t depth_surface_type = BRW_SURFACE_NULL;
+ uint32_t depthbuffer_format = BRW_DEPTHFORMAT_D32_FLOAT;
+ uint32_t depth_offset = 0;
+ uint32_t width = 1, height = 1;
+
+ /* If there's a packed depth/stencil bound to stencil only, we need to
+* emit the packed depth/stencil buffer packet.
+*/
+ if (!depth_irb && stencil_irb) {
+ depth_irb = stencil_irb;
+ depth_mt = stencil_mt;
+ }
- assert(!hiz);
- assert(!separate_stencil);
+ if (depth_irb && depth_mt) {
+ depthbuffer_format = brw_depthbuffer_format(brw);
+ depth_surface_type = BRW_SURFACE_2D;
+ depth_offset = brw->depthstencil.depth_offset;
+ width = depth_irb->Base.Base.Width;
+ height = depth_irb->Base.Base.Height;
+ }
const struct gen_device_info *devinfo = >screen->devinfo;
const unsigned len = (devinfo->is_g4x || devinfo->gen == 5) ? 6 : 5;
@@ -314,72 +327,6 @@ brw_emit_depthbuffer(struct brw_context *brw)
struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb,
BUFFER_STENCIL);
struct intel_mipmap_tree *depth_mt = intel_renderbuffer_get_mt(depth_irb);
struct intel_mipmap_tree *stencil_mt = get_stencil_miptree(stencil_irb);
- uint32_t tile_x = brw->depthstencil.tile_x;
- uint32_t tile_y = brw->depthstencil.tile_y;
- bool hiz = depth_irb && intel_renderbuffer_has_hiz(depth_irb);
- bool separate_stencil = false;
- uint32_t depth_surface_type = BRW_SURFACE_NULL;
- uint32_t depthbuffer_format = BRW_DEPTHFORMAT_D32_FLOAT;
- uint32_t depth_offset = 0;
- uint32_t width = 1, height = 1;
-
- if (stencil_mt) {
- separate_stencil = stencil_mt->format == MESA_FORMAT_S_UINT8;
-
- /* Gen7 supports only separate stencil */
- assert(separate_stencil || devinfo->gen < 7);
- }
-
- /* If there's a packed depth/stencil bound to stencil only, we need to
-* emit the packed depth/stencil buffer packet.
-*/
- if (!depth_irb && stencil_irb && !separate_stencil) {
- depth_irb = stencil_irb;
- depth_mt = stencil_mt;
- }
-
- if (depth_irb && depth_mt) {
- /* When 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Enable is set, then
- * 3DSTATE_DEPTH_BUFFER.Surface_Format is not permitted to be a packed
- * depthstencil format.
- *
- * Gens prior to 7 require that HiZ_Enable and Separate_Stencil_Enable be
- * set to the same value. Gens after 7 implicitly always set
- * Separate_Stencil_Enable; software cannot disable it.
- */
- if ((devinfo->gen < 7 && hiz) || devinfo->gen >= 7) {
- assert(!_mesa_is_format_packed_depth_stencil(depth_mt->format));
- }
-
- /* Prior to Gen7, if using separate stencil, hiz must be enabled. */
- assert(devinfo->gen >= 7 || !separate_stencil || hiz);
-
- assert(devinfo->gen < 6 || depth_mt->surf.tiling == ISL_TILING_Y0);
- assert(!hiz || depth_mt->surf.tiling == I
Mesa (master): i965: Re-emit depth/stencil/hiz on BRW_NEW_AUX_STATE
Module: Mesa
Branch: master
Commit: 6fc34049119f9086638e8d768ef5ce09e9ba57e4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6fc34049119f9086638e8d768ef5ce09e9ba57e4
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Sat May 5 12:48:54 2018 -0700
i965: Re-emit depth/stencil/hiz on BRW_NEW_AUX_STATE
Certain things can change the aux usage or fast clear color of a depth
surface and we want to re-emit if that happens. For instance, if you do
a fast depth clear of an already clear depth surface, we will just set
the clear color and not do anything else. In that case, we could fail
to re-emit 3DSTATE_CLEAR_PARAMS and not get the new fast-clear color.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/gen7_misc_state.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 1ce76585f2..15084733c5 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -195,7 +195,8 @@ const struct brw_tracked_state gen7_depthbuffer = {
.mesa = _NEW_BUFFERS |
_NEW_DEPTH |
_NEW_STENCIL,
- .brw = BRW_NEW_BATCH |
+ .brw = BRW_NEW_AUX_STATE |
+ BRW_NEW_BATCH |
BRW_NEW_BLORP,
},
.emit = brw_emit_depthbuffer,
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Mesa (master): i965: Re-order depth/stencil/hiz/clear packets to match ISL
Module: Mesa
Branch: master
Commit: c4d00da7b7b819e21d07e00cdb9b14f670c8e262
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c4d00da7b7b819e21d07e00cdb9b14f670c8e262
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Sat May 5 12:35:01 2018 -0700
i965: Re-order depth/stencil/hiz/clear packets to match ISL
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/gen6_depth_state.c | 34 ++--
src/mesa/drivers/dri/i965/gen7_misc_state.c | 32 +-
src/mesa/drivers/dri/i965/gen8_depth_state.c | 28 +++
3 files changed, 47 insertions(+), 47 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c
b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index 8a1d580805..bca956e23d 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -155,44 +155,44 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
* failure to do so causes hangs on gen5 and a stall on gen6.
*/
- /* Emit hiz buffer. */
- if (hiz) {
- assert(depth_mt);
+ /* Emit stencil buffer. */
+ if (separate_stencil) {
+ assert(stencil_mt->format == MESA_FORMAT_S_UINT8);
+ assert(stencil_mt->surf.size > 0);
uint32_t offset;
- isl_surf_get_image_offset_B_tile_sa(_mt->aux_buf->surf,
+ isl_surf_get_image_offset_B_tile_sa(_mt->surf,
lod, 0, 0, , NULL, NULL);
BEGIN_BATCH(3);
-OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
-OUT_BATCH(depth_mt->aux_buf->surf.row_pitch - 1);
-OUT_RELOC(depth_mt->aux_buf->bo, RELOC_WRITE, offset);
+OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
+OUT_BATCH(stencil_mt->surf.row_pitch - 1);
+OUT_RELOC(stencil_mt->bo, RELOC_WRITE, offset);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(3);
-OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
+OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
}
- /* Emit stencil buffer. */
- if (separate_stencil) {
- assert(stencil_mt->format == MESA_FORMAT_S_UINT8);
- assert(stencil_mt->surf.size > 0);
+ /* Emit hiz buffer. */
+ if (hiz) {
+ assert(depth_mt);
uint32_t offset;
- isl_surf_get_image_offset_B_tile_sa(_mt->surf,
+ isl_surf_get_image_offset_B_tile_sa(_mt->aux_buf->surf,
lod, 0, 0, , NULL, NULL);
BEGIN_BATCH(3);
-OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
-OUT_BATCH(stencil_mt->surf.row_pitch - 1);
-OUT_RELOC(stencil_mt->bo, RELOC_WRITE, offset);
+OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
+OUT_BATCH(depth_mt->aux_buf->surf.row_pitch - 1);
+OUT_RELOC(depth_mt->aux_buf->bo, RELOC_WRITE, offset);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(3);
-OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
+OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 15084733c5..e3a355fae3 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -137,39 +137,39 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH((depth - 1) << 21);
ADVANCE_BATCH();
- if (!hiz) {
+ if (stencil_mt == NULL) {
BEGIN_BATCH(3);
- OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
+ OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
- assert(depth_mt);
+ stencil_mt->r8stencil_needs_update = true;
+ const int enabled = devinfo->is_haswell ? HSW_STENCIL_ENABLED : 0;
BEGIN_BATCH(3);
- OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
- OUT_BATCH((mocs << 25) |
-(depth_mt->aux_buf->pitch - 1));
- OUT_RELOC(depth_mt->aux_buf->bo, RELOC_WRITE, 0);
+ OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
+ OUT_BATCH(enabled |
+mocs << 25 |
+ (stencil_mt->surf.row_pitch - 1));
+ OUT_RELOC(stencil_mt->bo, RELOC_WRITE, 0);
ADVANCE_BATCH();
}
- if (stencil_mt == NULL) {
+ if (!hiz) {
BEGIN_BATCH(3);
- OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER
Mesa (master): i965: Use ISL for emitting depth/stencil/hiz state on gen6+
Module: Mesa
Branch: master
Commit: bdbb527a65fc729e7a9319ae67de60d03d06c3fd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bdbb527a65fc729e7a9319ae67de60d03d06c3fd
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri May 4 22:32:24 2018 -0700
i965: Use ISL for emitting depth/stencil/hiz state on gen6+
We leave gen4-5 alone because the ISL code hasn't really been well-
tested on gen4-5 or with combined depth-stencil because we don't use
BLORP for depth operations on gen4-5. Also, the gen4-5 code has to deal
with intratile offsets for LOD hacks and ISL doesn't handle those yet.
We could make ISL handle gen4-5 capable or we could just not bother.
Among other things, this should make future platform enabling easier
because it means we don't have to update multiple (or hand-rolled!)
depth stencil emit paths.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/Makefile.sources | 2 -
src/mesa/drivers/dri/i965/brw_context.c | 9 --
src/mesa/drivers/dri/i965/brw_context.h | 53 ---
src/mesa/drivers/dri/i965/brw_misc_state.c | 147 +++---
src/mesa/drivers/dri/i965/brw_state.h| 3 -
src/mesa/drivers/dri/i965/gen6_depth_state.c | 221 ---
src/mesa/drivers/dri/i965/gen7_misc_state.c | 188 ---
src/mesa/drivers/dri/i965/gen8_depth_state.c | 175 -
src/mesa/drivers/dri/i965/meson.build| 2 -
9 files changed, 129 insertions(+), 671 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
b/src/mesa/drivers/dri/i965/Makefile.sources
index 5e53d874d8..db6591ab90 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -68,14 +68,12 @@ i965_FILES = \
gen4_blorp_exec.h \
gen6_clip_state.c \
gen6_constant_state.c \
- gen6_depth_state.c \
gen6_multisample_state.c \
gen6_queryobj.c \
gen6_sampler_state.c \
gen6_sol.c \
gen6_urb.c \
gen7_l3_state.c \
- gen7_misc_state.c \
gen7_sol_state.c \
gen7_urb.c \
gen8_depth_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index b954a2916d..ec3fe3be40 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -922,15 +922,6 @@ brwCreateContext(gl_api api,
brw->gs.base.stage = MESA_SHADER_GEOMETRY;
brw->wm.base.stage = MESA_SHADER_FRAGMENT;
brw->cs.base.stage = MESA_SHADER_COMPUTE;
- if (devinfo->gen >= 8) {
- brw->vtbl.emit_depth_stencil_hiz = gen8_emit_depth_stencil_hiz;
- } else if (devinfo->gen >= 7) {
- brw->vtbl.emit_depth_stencil_hiz = gen7_emit_depth_stencil_hiz;
- } else if (devinfo->gen >= 6) {
- brw->vtbl.emit_depth_stencil_hiz = gen6_emit_depth_stencil_hiz;
- } else {
- brw->vtbl.emit_depth_stencil_hiz = brw_emit_depth_stencil_hiz;
- }
brw_init_driver_functions(brw, );
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 23406816a9..d8b0d94aaf 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -742,20 +742,6 @@ struct brw_context
struct
{
/**
- * Send the appropriate state packets to configure depth, stencil, and
- * HiZ buffers (i965+ only)
- */
- void (*emit_depth_stencil_hiz)(struct brw_context *brw,
- struct intel_mipmap_tree *depth_mt,
- uint32_t depth_offset,
- uint32_t depthbuffer_format,
- uint32_t depth_surface_type,
- struct intel_mipmap_tree *stencil_mt,
- bool hiz, bool separate_stencil,
- uint32_t width, uint32_t height,
- uint32_t tile_x, uint32_t tile_y);
-
- /**
* Emit an MI_REPORT_PERF_COUNT command packet.
*
* This asks the GPU to write a report of the current OA counter values
@@ -1708,45 +1694,6 @@ brw_depth_writes_enabled(const struct brw_context *brw)
void
brw_emit_depthbuffer(struct brw_context *brw);
-void
-brw_emit_depth_stencil_hiz(struct brw_context *brw,
- struct intel_mipmap_tree *depth_mt,
- uint32_t depth_offset, uint32_t depthbuffer_format,
- uint32_t depth_surface_type,
- struct intel_mipmap_tree *stencil_mt,
- bool hiz, bool separate_stencil,
- uint32_t width, uint32_t height,
- uint32_t tile_x, uint32_t tile_y);
-
-void
-gen6_emit_depth_stencil_hiz(struct br
Mesa (master): anv: Advertise variableMultisampleRate
Module: Mesa Branch: master Commit: bd35345e85ddaf9c8fe7b8ed089edd4926ee4fe1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd35345e85ddaf9c8fe7b8ed089edd4926ee4fe1 Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Thu Feb 8 09:03:03 2018 -0800 anv: Advertise variableMultisampleRate Initially, I didn't understand this feature. Turns out that all it means is that you can switch multisample rates in the middle of a zero-attachment subpass. We've been able to do this since forever. Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/intel/vulkan/anv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 856035b8b9..0563eae5c1 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -761,7 +761,7 @@ void anv_GetPhysicalDeviceFeatures( pdevice->info.has_64bit_types, .shaderInt16 = false, .shaderResourceMinLod = false, - .variableMultisampleRate = false, + .variableMultisampleRate = true, .inheritedQueries = true, }; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv: Don't advertise Float64 or Int64 on HW without 64-bit types
Module: Mesa Branch: master Commit: d5a0787f034d6165d3990561a08e933848993032 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5a0787f034d6165d3990561a08e933848993032 Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Mon Apr 30 15:15:37 2018 -0700 anv: Don't advertise Float64 or Int64 on HW without 64-bit types Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/intel/vulkan/anv_device.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 1c5dbb5189..11ab5e0c1d 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -755,8 +755,10 @@ void anv_GetPhysicalDeviceFeatures( .shaderStorageImageArrayDynamicIndexing = true, .shaderClipDistance = true, .shaderCullDistance = true, - .shaderFloat64= pdevice->info.gen >= 8, - .shaderInt64 = pdevice->info.gen >= 8, + .shaderFloat64= pdevice->info.gen >= 8 && + pdevice->info.has_64bit_types, + .shaderInt64 = pdevice->info.gen >= 8 && + pdevice->info.has_64bit_types, .shaderInt16 = false, .shaderResourceMinLod = false, .variableMultisampleRate = false, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv: Allow lookup of vkEnumerateInstanceVersion without an instance
Module: Mesa Branch: master Commit: d216ffc604573e514904a05691a47dfe5971e8ca URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d216ffc604573e514904a05691a47dfe5971e8ca Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Tue May 1 09:59:24 2018 -0700 anv: Allow lookup of vkEnumerateInstanceVersion without an instance Fixes: cbab2d1da5edfe9df27a010adf8b1aa9dbee473b Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/intel/vulkan/anv_device.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 11ab5e0c1d..856035b8b9 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -1179,6 +1179,7 @@ PFN_vkVoidFunction anv_GetInstanceProcAddr( LOOKUP_ANV_ENTRYPOINT(EnumerateInstanceExtensionProperties); LOOKUP_ANV_ENTRYPOINT(EnumerateInstanceLayerProperties); + LOOKUP_ANV_ENTRYPOINT(EnumerateInstanceVersion); LOOKUP_ANV_ENTRYPOINT(CreateInstance); #undef LOOKUP_ANV_ENTRYPOINT ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv/allocator: Don't shrink either end of the block pool
Module: Mesa Branch: master Commit: 3db93f9128e5329f6658c9018cf23eb31807c24c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3db93f9128e5329f6658c9018cf23eb31807c24c Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Fri Apr 20 21:52:41 2018 -0700 anv/allocator: Don't shrink either end of the block pool Previously, we only tried to ensure that we didn't shrink either end below what was already handed out. However, due to the way we handle relocations with block pools, we can't shrink the back end at all. It's probably best to not shrink in either direction. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105374 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106147 Tested-by: Eero Tamminen <eero.t.tammi...@intel.com> Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com> Cc: mesa-sta...@lists.freedesktop.org --- src/intel/vulkan/anv_allocator.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c index f884ac3b82..642e1618c1 100644 --- a/src/intel/vulkan/anv_allocator.c +++ b/src/intel/vulkan/anv_allocator.c @@ -508,12 +508,12 @@ anv_block_pool_grow(struct anv_block_pool *pool, struct anv_block_state *state) assert(center_bo_offset >= back_used); /* Make sure we don't shrink the back end of the pool */ - if (center_bo_offset < pool->back_state.end) - center_bo_offset = pool->back_state.end; + if (center_bo_offset < back_required) + center_bo_offset = back_required; /* Make sure that we don't shrink the front end of the pool */ - if (size - center_bo_offset < pool->state.end) - center_bo_offset = size - pool->state.end; + if (size - center_bo_offset < front_required) + center_bo_offset = size - front_required; } assert(center_bo_offset % PAGE_SIZE == 0); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/fs: Return mlen * 8 for size_read() for INTERPOLATE_AT_*
Module: Mesa Branch: master Commit: de1f22d595d40f6c2e2d80db73aa90d62a875de5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=de1f22d595d40f6c2e2d80db73aa90d62a875de5 Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Thu Apr 19 20:48:42 2018 -0700 i965/fs: Return mlen * 8 for size_read() for INTERPOLATE_AT_* They are send messages and this makes size_read() and mlen agree. For both of these opcodes, the payload is just a dummy so mlen == 1 and this should decrease register pressure a bit. Reviewed-by: Francisco Jerez <curroje...@riseup.net> Cc: mesa-sta...@lists.freedesktop.org --- src/intel/compiler/brw_fs.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 40896db26b..815650706c 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -842,6 +842,8 @@ fs_inst::size_read(int arg) const case SHADER_OPCODE_TYPED_ATOMIC: case SHADER_OPCODE_TYPED_SURFACE_READ: case SHADER_OPCODE_TYPED_SURFACE_WRITE: + case FS_OPCODE_INTERPOLATE_AT_SAMPLE: + case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET: case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: case SHADER_OPCODE_BYTE_SCATTERED_WRITE: case SHADER_OPCODE_BYTE_SCATTERED_READ: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv/blorp: Do the gen11 BTI flush
Module: Mesa Branch: master Commit: 185630c6bc973e9a2fec6172325bf31d70bc2eec URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=185630c6bc973e9a2fec6172325bf31d70bc2eec Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Tue Apr 17 15:06:46 2018 -0700 anv/blorp: Do the gen11 BTI flush Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com> Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/vulkan/genX_blorp_exec.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c index b423046d61..9023269d61 100644 --- a/src/intel/vulkan/genX_blorp_exec.c +++ b/src/intel/vulkan/genX_blorp_exec.c @@ -202,6 +202,20 @@ genX(blorp_exec)(struct blorp_batch *batch, genX(cmd_buffer_config_l3)(cmd_buffer, cfg); } +#if GEN_GEN >= 11 + /* The PIPE_CONTROL command description says: +* +*"Whenever a Binding Table Index (BTI) used by a Render Taget Message +* points to a different RENDER_SURFACE_STATE, SW must issue a Render +* Target Cache Flush by enabling this bit. When render target flush +* is set due to new association of BTI, PS Scoreboard Stall bit must +* be set in this packet." +*/ + cmd_buffer->state.pending_pipe_bits |= + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | + ANV_PIPE_STALL_AT_SCOREBOARD_BIT; +#endif + #if GEN_GEN == 7 /* The MI_LOAD/STORE_REGISTER_MEM commands which BLORP uses to implement * indirect fast-clear colors can cause GPU hangs if we don't stall first. ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/blorp: Do the gen11 BTI flush
Module: Mesa Branch: master Commit: 9d2ef3c9ecf9b2e00efa42ae245132d59571d08d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d2ef3c9ecf9b2e00efa42ae245132d59571d08d Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Tue Apr 17 15:07:13 2018 -0700 i965/blorp: Do the gen11 BTI flush Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com> Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/genX_blorp_exec.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c index b72ca9c515..581438966e 100644 --- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c +++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c @@ -241,6 +241,20 @@ genX(blorp_exec)(struct blorp_batch *batch, struct gl_context *ctx = >ctx; bool check_aperture_failed_once = false; +#if GEN_GEN >= 11 + /* The PIPE_CONTROL command description says: +* +* "Whenever a Binding Table Index (BTI) used by a Render Taget Message +* points to a different RENDER_SURFACE_STATE, SW must issue a Render +* Target Cache Flush by enabling this bit. When render target flush +* is set due to new association of BTI, PS Scoreboard Stall bit must +* be set in this packet." + */ + brw_emit_pipe_control_flush(brw, + PIPE_CONTROL_RENDER_TARGET_FLUSH | + PIPE_CONTROL_STALL_AT_SCOREBOARD); +#endif + /* Flush the sampler and render caches. We definitely need to flush the * sampler cache so that we get updated contents from the render cache for * the glBlitFramebuffer() source. Also, we are sometimes warned in the ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv,radv: Drop XML workarounds for VK_ANDROID_native_buffer
Module: Mesa Branch: master Commit: 72ab499c9f9fbfa27645168b688ad03ad5d51242 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=72ab499c9f9fbfa27645168b688ad03ad5d51242 Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Mon Apr 16 07:38:31 2018 -0700 anv,radv: Drop XML workarounds for VK_ANDROID_native_buffer Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/amd/vulkan/radv_extensions.py | 7 +-- src/intel/vulkan/anv_extensions_gen.py | 7 +-- 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/src/amd/vulkan/radv_extensions.py b/src/amd/vulkan/radv_extensions.py index db37d617f9..099cae78b1 100644 --- a/src/amd/vulkan/radv_extensions.py +++ b/src/amd/vulkan/radv_extensions.py @@ -161,12 +161,7 @@ def _init_exts_from_xml(xml): continue ext = ext_name_map[ext_name] -if ext_name == 'VK_ANDROID_native_buffer': -# VK_ANDROID_native_buffer is missing the type specifier. Just -# hard-code it to be a device extension for now. -ext.type = 'device' -else: -ext.type = ext_elem.attrib['type'] +ext.type = ext_elem.attrib['type'] _TEMPLATE_H = Template(COPYRIGHT + """ #ifndef RADV_EXTENSIONS_H diff --git a/src/intel/vulkan/anv_extensions_gen.py b/src/intel/vulkan/anv_extensions_gen.py index 57a528563e..5ea82204ee 100644 --- a/src/intel/vulkan/anv_extensions_gen.py +++ b/src/intel/vulkan/anv_extensions_gen.py @@ -46,12 +46,7 @@ def _init_exts_from_xml(xml): continue ext = ext_name_map[ext_name] -if ext_name == 'VK_ANDROID_native_buffer': -# VK_ANDROID_native_buffer is missing the type specifier. Just -# hard-code it to be a device extension for now. -ext.type = 'device' -else: -ext.type = ext_elem.attrib['type'] +ext.type = ext_elem.attrib['type'] _TEMPLATE_H = Template(COPYRIGHT + """ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nir: fix ir_binop_gequal glsl_to_nir conversion
Module: Mesa
Branch: master
Commit: d19b488339be4b908dbd3b1636a677d11a2232f0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d19b488339be4b908dbd3b1636a677d11a2232f0
Author: Erico Nunes <nunes.er...@gmail.com>
Date: Sat Apr 14 21:14:41 2018 +0200
nir: fix ir_binop_gequal glsl_to_nir conversion
ir_binop_gequal needs to be converted to nir_op_sge when native integers
are not supported in the driver.
Otherwise it becomes no different than ir_binop_less after the
conversion.
Signed-off-by: Erico Nunes <nunes.er...@gmail.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/compiler/glsl/glsl_to_nir.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/compiler/glsl/glsl_to_nir.cpp
b/src/compiler/glsl/glsl_to_nir.cpp
index 17d58acc4c..8e5e9c3491 100644
--- a/src/compiler/glsl/glsl_to_nir.cpp
+++ b/src/compiler/glsl/glsl_to_nir.cpp
@@ -1832,7 +1832,7 @@ nir_visitor::visit(ir_expression *ir)
else
result = nir_uge(, srcs[0], srcs[1]);
} else {
- result = nir_slt(, srcs[0], srcs[1]);
+ result = nir_sge(, srcs[0], srcs[1]);
}
break;
case ir_binop_equal:
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): vulkan: Update the XML and headers to 1.1.73
Module: Mesa
Branch: master
Commit: 35ef0f767e163f3be826cab7cb02bc95bd3e6565
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=35ef0f767e163f3be826cab7cb02bc95bd3e6565
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Mon Apr 16 07:32:03 2018 -0700
vulkan: Update the XML and headers to 1.1.73
Acked-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
include/vulkan/vulkan_core.h | 2 +-
src/vulkan/registry/vk.xml | 10 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/include/vulkan/vulkan_core.h b/include/vulkan/vulkan_core.h
index ed0d596f67..2cafcddf5e 100644
--- a/include/vulkan/vulkan_core.h
+++ b/include/vulkan/vulkan_core.h
@@ -43,7 +43,7 @@ extern "C" {
#define VK_VERSION_MINOR(version) (((uint32_t)(version) >> 12) & 0x3ff)
#define VK_VERSION_PATCH(version) ((uint32_t)(version) & 0xfff)
// Version of this file
-#define VK_HEADER_VERSION 72
+#define VK_HEADER_VERSION 73
#define VK_NULL_HANDLE 0
diff --git a/src/vulkan/registry/vk.xml b/src/vulkan/registry/vk.xml
index a97ae92746..3b19b3a707 100644
--- a/src/vulkan/registry/vk.xml
+++ b/src/vulkan/registry/vk.xml
@@ -137,7 +137,7 @@ server.
// Vulkan 1.1 version number
#define VK_API_VERSION_1_1 VK_MAKE_VERSION(1, 1,
0)// Patch version should always be set to 0
// Version of this file
-#define VK_HEADER_VERSION 72
+#define VK_HEADER_VERSION 73
#define VK_DEFINE_HANDLE(object) typedef struct object##_T*
object;
@@ -1410,7 +1410,7 @@ server.
uint32_t
maxGeometryOutputVerticesmax number of vertices that can
be emitted in geometry stage
uint32_t
maxGeometryTotalOutputComponentsmax total number of
components (all vertices) written in geometry stage
fragment stage limits
-uint32_t
maxFragmentInputComponentsmax number of input compontents
read in fragment stage
+uint32_t
maxFragmentInputComponentsmax number of input components
read in fragment stage
uint32_t
maxFragmentOutputAttachmentsmax number of output
attachments written in fragment stage
uint32_t
maxFragmentDualSrcAttachmentsmax number of output
attachments written when using dual source blending
uint32_t
maxFragmentCombinedOutputResourcesmax total number of
storage buffers, storage images and output buffers
@@ -2935,7 +2935,7 @@ server.
VkConservativeRasterizationModeEXT
conservativeRasterizationMode
float
extraPrimitiveOverestimationSize
-
+
VkStructureType
sType
void*
pNext
VkBool32
shaderInputAttachmentArrayDynamicIndexing
@@ -2959,7 +2959,7 @@ server.
VkBool32
descriptorBindingVariableDescriptorCount
VkBool32
runtimeDescriptorArray
-
+
VkStructureType
sType
void*
pNext
uint32_t
maxUpdateAfterBindDescriptorsInAllPools
@@ -6719,7 +6719,7 @@ server.
-
+
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Mesa (master): nir/vars_to_ssa: Remove an unnecessary deref_arry_type check
Module: Mesa
Branch: master
Commit: fac9dd1b93829a84f634525ce41f18953fe92433
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fac9dd1b93829a84f634525ce41f18953fe92433
Author: Caio Marcelo de Oliveira Filho <caio.olive...@intel.com>
Date: Tue Apr 10 23:13:39 2018 -0700
nir/vars_to_ssa: Remove an unnecessary deref_arry_type check
Only fully-qualified direct derefs, collected in direct_deref_nodes,
are checked for aliasing, so it is already known up front that they
have only array derefs of type direct.
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/compiler/nir/nir_lower_vars_to_ssa.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/compiler/nir/nir_lower_vars_to_ssa.c
b/src/compiler/nir/nir_lower_vars_to_ssa.c
index f327a14d9b..970eb05307 100644
--- a/src/compiler/nir/nir_lower_vars_to_ssa.c
+++ b/src/compiler/nir/nir_lower_vars_to_ssa.c
@@ -298,15 +298,16 @@ deref_may_be_aliased_node(struct deref_node *node,
nir_deref *deref,
switch (deref->child->deref_type) {
case nir_deref_type_array: {
nir_deref_array *arr = nir_deref_as_array(deref->child);
- if (arr->deref_array_type == nir_deref_array_type_indirect)
-return true;
+
+ /* This is a child of one of the derefs in direct_deref_nodes,
+ * so we know it is direct.
+ */
+ assert(arr->deref_array_type == nir_deref_array_type_direct);
/* If there is an indirect at this level, we're aliased. */
if (node->indirect)
return true;
- assert(arr->deref_array_type == nir_deref_array_type_direct);
-
if (node->children[arr->base_offset] &&
deref_may_be_aliased_node(node->children[arr->base_offset],
deref->child, state))
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Mesa (master): nir/vars_to_ssa: Simplify node matching code
Module: Mesa
Branch: master
Commit: 89542c9ce6842a162bf75b945f11e2f56b02ddba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=89542c9ce6842a162bf75b945f11e2f56b02ddba
Author: Caio Marcelo de Oliveira Filho <caio.olive...@intel.com>
Date: Tue Apr 10 23:13:40 2018 -0700
nir/vars_to_ssa: Simplify node matching code
The matching code doesn't make real use of the return value. The main
function return value is ignored, and while the worker function
propagate its return value, the actual callback never returns false.
v2: Style fixes. (Jason)
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/compiler/nir/nir_lower_vars_to_ssa.c | 67 +++-
1 file changed, 31 insertions(+), 36 deletions(-)
diff --git a/src/compiler/nir/nir_lower_vars_to_ssa.c
b/src/compiler/nir/nir_lower_vars_to_ssa.c
index 970eb05307..8bc847fd41 100644
--- a/src/compiler/nir/nir_lower_vars_to_ssa.c
+++ b/src/compiler/nir/nir_lower_vars_to_ssa.c
@@ -217,45 +217,42 @@ get_deref_node(nir_deref_var *deref, struct
lower_variables_state *state)
}
/* \sa foreach_deref_node_match */
-static bool
+static void
foreach_deref_node_worker(struct deref_node *node, nir_deref *deref,
- bool (* cb)(struct deref_node *node,
+ void (* cb)(struct deref_node *node,
struct lower_variables_state *state),
struct lower_variables_state *state)
{
if (deref->child == NULL) {
- return cb(node, state);
- } else {
- switch (deref->child->deref_type) {
- case nir_deref_type_array: {
- nir_deref_array *arr = nir_deref_as_array(deref->child);
- assert(arr->deref_array_type == nir_deref_array_type_direct);
- if (node->children[arr->base_offset] &&
- !foreach_deref_node_worker(node->children[arr->base_offset],
-deref->child, cb, state))
-return false;
+ cb(node, state);
+ return;
+ }
- if (node->wildcard &&
- !foreach_deref_node_worker(node->wildcard,
-deref->child, cb, state))
-return false;
+ switch (deref->child->deref_type) {
+ case nir_deref_type_array: {
+ nir_deref_array *arr = nir_deref_as_array(deref->child);
+ assert(arr->deref_array_type == nir_deref_array_type_direct);
- return true;
+ if (node->children[arr->base_offset]) {
+ foreach_deref_node_worker(node->children[arr->base_offset],
+ deref->child, cb, state);
}
+ if (node->wildcard)
+ foreach_deref_node_worker(node->wildcard, deref->child, cb, state);
+ break;
+ }
- case nir_deref_type_struct: {
- nir_deref_struct *str = nir_deref_as_struct(deref->child);
- if (node->children[str->index] &&
- !foreach_deref_node_worker(node->children[str->index],
-deref->child, cb, state))
-return false;
-
- return true;
+ case nir_deref_type_struct: {
+ nir_deref_struct *str = nir_deref_as_struct(deref->child);
+ if (node->children[str->index]) {
+ foreach_deref_node_worker(node->children[str->index],
+ deref->child, cb, state);
}
+ break;
+ }
- default:
- unreachable("Invalid deref child type");
- }
+ default:
+ unreachable("Invalid deref child type");
}
}
@@ -271,9 +268,9 @@ foreach_deref_node_worker(struct deref_node *node,
nir_deref *deref,
* The given deref must be a full-length and fully qualified (no wildcards
* or indirects) deref chain.
*/
-static bool
+static void
foreach_deref_node_match(nir_deref_var *deref,
- bool (* cb)(struct deref_node *node,
+ void (* cb)(struct deref_node *node,
struct lower_variables_state *state),
struct lower_variables_state *state)
{
@@ -282,9 +279,9 @@ foreach_deref_node_match(nir_deref_var *deref,
struct deref_node *node = get_deref_node(_deref, state);
if (node == NULL)
- return false;
+ return;
- return foreach_deref_node_worker(node, >deref, cb, state);
+ foreach_deref_node_worker(node, >deref, cb, state);
}
/* \sa deref_may_be_aliased */
@@ -441,12 +438,12 @@ register_variable_uses(nir_function_impl *impl,
/* Walks over all of the copy instructions to or from the given deref_node
* and lowers them to load/store intrinsics.
*/
-static bool
+static void
lower_copies_to_load_store(struct deref_node *node,
struct lower_variables_state *state)
{
if (!node->copies)
- re
Mesa (master): nir/vars_to_ssa: Rework register_variable_uses()
Module: Mesa
Branch: master
Commit: 1c9bccdeb8acf1a531b49bbb6c69ea96879e79de
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c9bccdeb8acf1a531b49bbb6c69ea96879e79de
Author: Caio Marcelo de Oliveira Filho <caio.olive...@intel.com>
Date: Tue Apr 10 23:13:38 2018 -0700
nir/vars_to_ssa: Rework register_variable_uses()
The return value was needed to make use of the old nir_foreach_block
helper, but not needed anymore with the macro version. Then go one
step further and move the foreach directly into the register variable
uses function.
v2: Move foreach to register_variable_uses(). (Jason)
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/compiler/nir/nir_lower_vars_to_ssa.c | 51 ++--
1 file changed, 23 insertions(+), 28 deletions(-)
diff --git a/src/compiler/nir/nir_lower_vars_to_ssa.c
b/src/compiler/nir/nir_lower_vars_to_ssa.c
index 0cc65143e7..f327a14d9b 100644
--- a/src/compiler/nir/nir_lower_vars_to_ssa.c
+++ b/src/compiler/nir/nir_lower_vars_to_ssa.c
@@ -406,36 +406,35 @@ register_copy_instr(nir_intrinsic_instr *copy_instr,
}
}
-/* Registers all variable uses in the given block. */
-static bool
-register_variable_uses_block(nir_block *block,
- struct lower_variables_state *state)
+static void
+register_variable_uses(nir_function_impl *impl,
+ struct lower_variables_state *state)
{
- nir_foreach_instr_safe(instr, block) {
- if (instr->type != nir_instr_type_intrinsic)
- continue;
+ nir_foreach_block(block, impl) {
+ nir_foreach_instr_safe(instr, block) {
+ if (instr->type != nir_instr_type_intrinsic)
+continue;
- nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
+ nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
- switch (intrin->intrinsic) {
- case nir_intrinsic_load_var:
- register_load_instr(intrin, state);
- break;
+ switch (intrin->intrinsic) {
+ case nir_intrinsic_load_var:
+register_load_instr(intrin, state);
+break;
- case nir_intrinsic_store_var:
- register_store_instr(intrin, state);
- break;
+ case nir_intrinsic_store_var:
+register_store_instr(intrin, state);
+break;
- case nir_intrinsic_copy_var:
- register_copy_instr(intrin, state);
- break;
+ case nir_intrinsic_copy_var:
+register_copy_instr(intrin, state);
+break;
- default:
- continue;
+ default:
+continue;
+ }
}
}
-
- return true;
}
/* Walks over all of the copy instructions to or from the given deref_node
@@ -654,9 +653,7 @@ nir_lower_vars_to_ssa_impl(nir_function_impl *impl)
/* Build the initial deref structures and direct_deref_nodes table */
state.add_to_direct_deref_nodes = true;
- nir_foreach_block(block, impl) {
- register_variable_uses_block(block, );
- }
+ register_variable_uses(impl, );
bool progress = false;
@@ -696,9 +693,7 @@ nir_lower_vars_to_ssa_impl(nir_function_impl *impl)
* added load/store instructions are registered. We need this
* information for phi node insertion below.
*/
- nir_foreach_block(block, impl) {
- register_variable_uses_block(block, );
- }
+ register_variable_uses(impl, );
state.phi_builder = nir_phi_builder_create(state.impl);
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Mesa (master): nir: Use nir_builder in lower_io_to_temporaries
Module: Mesa
Branch: master
Commit: bc2b170d6849d31fc88df4ece635ff789e4ad0c2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bc2b170d6849d31fc88df4ece635ff789e4ad0c2
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Mon Mar 26 15:38:49 2018 -0700
nir: Use nir_builder in lower_io_to_temporaries
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.olive...@intel.com>
---
src/compiler/nir/nir_lower_io_to_temporaries.c | 35 --
1 file changed, 16 insertions(+), 19 deletions(-)
diff --git a/src/compiler/nir/nir_lower_io_to_temporaries.c
b/src/compiler/nir/nir_lower_io_to_temporaries.c
index bff04b9768..3dae52220d 100644
--- a/src/compiler/nir/nir_lower_io_to_temporaries.c
+++ b/src/compiler/nir/nir_lower_io_to_temporaries.c
@@ -31,6 +31,7 @@
*/
#include "nir.h"
+#include "nir_builder.h"
struct lower_io_state {
nir_shader *shader;
@@ -40,7 +41,7 @@ struct lower_io_state {
};
static void
-emit_copies(nir_cursor cursor, nir_shader *shader, struct exec_list *dest_vars,
+emit_copies(nir_builder *b, struct exec_list *dest_vars,
struct exec_list *src_vars)
{
assert(exec_list_length(dest_vars) == exec_list_length(src_vars));
@@ -64,18 +65,16 @@ emit_copies(nir_cursor cursor, nir_shader *shader, struct
exec_list *dest_vars,
if (dest->data.read_only)
continue;
- nir_intrinsic_instr *copy =
- nir_intrinsic_instr_create(shader, nir_intrinsic_copy_var);
- copy->variables[0] = nir_deref_var_create(copy, dest);
- copy->variables[1] = nir_deref_var_create(copy, src);
-
- nir_instr_insert(cursor, >instr);
+ nir_copy_var(b, dest, src);
}
}
static void
emit_output_copies_impl(struct lower_io_state *state, nir_function_impl *impl)
{
+ nir_builder b;
+ nir_builder_init(, impl);
+
if (state->shader->info.stage == MESA_SHADER_GEOMETRY) {
/* For geometry shaders, we have to emit the output copies right
* before each EmitVertex call.
@@ -87,16 +86,14 @@ emit_output_copies_impl(struct lower_io_state *state,
nir_function_impl *impl)
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
if (intrin->intrinsic == nir_intrinsic_emit_vertex) {
- nir_cursor cursor = nir_before_instr(>instr);
- emit_copies(cursor, state->shader, >shader->outputs,
- >old_outputs);
+ b.cursor = nir_before_instr(>instr);
+ emit_copies(, >shader->outputs, >old_outputs);
}
}
}
} else if (impl == state->entrypoint) {
- nir_cursor cursor = nir_before_block(nir_start_block(impl));
- emit_copies(cursor, state->shader, >old_outputs,
- >shader->outputs);
+ b.cursor = nir_before_block(nir_start_block(impl));
+ emit_copies(, >old_outputs, >shader->outputs);
/* For all other shader types, we need to do the copies right before
* the jumps to the end block.
@@ -104,9 +101,8 @@ emit_output_copies_impl(struct lower_io_state *state,
nir_function_impl *impl)
struct set_entry *block_entry;
set_foreach(impl->end_block->predecessors, block_entry) {
struct nir_block *block = (void *)block_entry->key;
- nir_cursor cursor = nir_after_block_before_jump(block);
- emit_copies(cursor, state->shader, >shader->outputs,
- >old_outputs);
+ b.cursor = nir_after_block_before_jump(block);
+ emit_copies(, >shader->outputs, >old_outputs);
}
}
}
@@ -115,9 +111,10 @@ static void
emit_input_copies_impl(struct lower_io_state *state, nir_function_impl *impl)
{
if (impl == state->entrypoint) {
- nir_cursor cursor = nir_before_block(nir_start_block(impl));
- emit_copies(cursor, state->shader, >old_inputs,
- >shader->inputs);
+ nir_builder b;
+ nir_builder_init(, impl);
+ b.cursor = nir_before_block(nir_start_block(impl));
+ emit_copies(, >old_inputs, >shader->inputs);
}
}
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Mesa (master): vulkan: Drop vk_android_native_buffer.xml
Module: Mesa Branch: master Commit: 69f447553c6cd8c9004b80c099630ce7167a0a28 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=69f447553c6cd8c9004b80c099630ce7167a0a28 Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Mon Apr 9 22:01:14 2018 -0700 vulkan: Drop vk_android_native_buffer.xml All the information in vk_android_native_buffer.xml is now in vk.xml. The only exception is the extension type attribute which we can work around in the generators while we wait for the XML to be fixed. Reviewed-by: Dylan Baker <dy...@pnwbakers.com> --- src/Makefile.am | 1 - src/amd/vulkan/Makefile.am | 3 -- src/amd/vulkan/meson.build | 4 +- src/amd/vulkan/radv_extensions.py| 17 +++- src/intel/Android.vulkan.mk | 6 +-- src/intel/Makefile.vulkan.am | 13 ++ src/intel/vulkan/anv_extensions_gen.py | 17 +++- src/intel/vulkan/meson.build | 12 +++--- src/vulkan/Android.mk| 4 +- src/vulkan/Makefile.am | 5 +-- src/vulkan/meson.build | 1 - src/vulkan/registry/vk_android_native_buffer.xml | 52 12 files changed, 26 insertions(+), 109 deletions(-) diff --git a/src/Makefile.am b/src/Makefile.am index 014ffaf3e2..fd5ae44550 100644 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -67,7 +67,6 @@ SUBDIRS += vulkan endif EXTRA_DIST += vulkan/registry/vk.xml -EXTRA_DIST += vulkan/registry/vk_android_native_buffer.xml if HAVE_AMD_DRIVERS SUBDIRS += amd diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am index 00b808229f..18f263ab44 100644 --- a/src/amd/vulkan/Makefile.am +++ b/src/amd/vulkan/Makefile.am @@ -117,13 +117,11 @@ nodist_EXTRA_libvulkan_radeon_la_SOURCES = dummy.cpp libvulkan_radeon_la_SOURCES = $(VULKAN_GEM_FILES) vulkan_api_xml = $(top_srcdir)/src/vulkan/registry/vk.xml -vk_android_native_buffer_xml = $(top_srcdir)/src/vulkan/registry/vk_android_native_buffer.xml radv_entrypoints.c: radv_entrypoints_gen.py radv_extensions.py $(vulkan_api_xml) $(MKDIR_GEN) $(AM_V_GEN)$(PYTHON2) $(srcdir)/radv_entrypoints_gen.py \ --xml $(vulkan_api_xml) \ - --xml $(vk_android_native_buffer_xml) \ --outdir $(builddir) radv_entrypoints.h: radv_entrypoints.c @@ -132,7 +130,6 @@ radv_extensions.c: radv_extensions.py \ $(MKDIR_GEN) $(AM_V_GEN)$(PYTHON2) $(srcdir)/radv_extensions.py \ --xml $(vulkan_api_xml) \ - --xml $(vk_android_native_buffer_xml) \ --out-c radv_extensions.c \ --out-h radv_extensions.h radv_extensions.h: radv_extensions.c diff --git a/src/amd/vulkan/meson.build b/src/amd/vulkan/meson.build index c3a6a8182b..b5a99fe91e 100644 --- a/src/amd/vulkan/meson.build +++ b/src/amd/vulkan/meson.build @@ -31,10 +31,10 @@ radv_entrypoints = custom_target( radv_extensions_c = custom_target( 'radv_extensions.c', - input : ['radv_extensions.py', vk_api_xml, vk_android_native_buffer_xml], + input : ['radv_extensions.py', vk_api_xml], output : ['radv_extensions.c', 'radv_extensions.h'], command : [ -prog_python2, '@INPUT0@', '--xml', '@INPUT1@', '--xml', '@INPUT2@', '--out-c', '@OUTPUT0@', +prog_python2, '@INPUT0@', '--xml', '@INPUT1@', '--out-c', '@OUTPUT0@', '--out-h', '@OUTPUT1@' ], ) diff --git a/src/amd/vulkan/radv_extensions.py b/src/amd/vulkan/radv_extensions.py index a25db637e2..a680f42dec 100644 --- a/src/amd/vulkan/radv_extensions.py +++ b/src/amd/vulkan/radv_extensions.py @@ -159,18 +159,13 @@ def _init_exts_from_xml(xml): if ext_name not in ext_name_map: continue -# Workaround for VK_ANDROID_native_buffer. Its element in -# vk.xml lists it as supported="disabled" and provides only a stub -# definition. Its element in Mesa's custom -# vk_android_native_buffer.xml, though, lists it as -# supported='android-vendor' and fully defines the extension. We want -# to skip the element in vk.xml. -if ext_elem.attrib['supported'] == 'disabled': -assert ext_name == 'VK_ANDROID_native_buffer' -continue - ext = ext_name_map[ext_name] -ext.type = ext_elem.attrib['type'] +if ext_name == 'VK_ANDROID_native_buffer': +# VK_ANDROID_native_buffer is missing the type specifier. Just +# hard-code it to be a device extension for now. +ext.type = 'device' +else: +ext.type = ext_elem.attrib['type'] _TEMPLATE_H = Template(COPYRIGHT + """ #ifndef RADV_EXTENSIONS_H diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk index 0ec0d78a2f..09dc22875a 100644 --- a/src/intel/Android.vulkan.mk +++ b/src/i
Mesa (master): nir/lower_atomics: Rework the main walker loop a bit
Module: Mesa
Branch: master
Commit: ae3a856c34e348f721c2d647999813801b5eb33c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae3a856c34e348f721c2d647999813801b5eb33c
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Tue Mar 20 15:44:16 2018 -0700
nir/lower_atomics: Rework the main walker loop a bit
This replaces some "if (...} { }" with "if (...) continue;" to reduce
nesting depth and makes nir_metadata_preserve conditional on progress
for the given impl.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.olive...@intel.com>
---
src/compiler/nir/nir_lower_atomics.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/src/compiler/nir/nir_lower_atomics.c
b/src/compiler/nir/nir_lower_atomics.c
index 6b046bc426..ee66aa3d7d 100644
--- a/src/compiler/nir/nir_lower_atomics.c
+++ b/src/compiler/nir/nir_lower_atomics.c
@@ -183,18 +183,26 @@ nir_lower_atomics(nir_shader *shader,
bool progress = false;
nir_foreach_function(function, shader) {
- if (function->impl) {
- nir_foreach_block(block, function->impl) {
-nir_foreach_instr_safe(instr, block) {
- if (instr->type == nir_instr_type_intrinsic)
- progress |= lower_instr(nir_instr_as_intrinsic(instr),
- shader_program, shader,
- use_binding_as_idx);
-}
+ if (!function->impl)
+ continue;
+
+ bool impl_progress = false;
+
+ nir_foreach_block(block, function->impl) {
+ nir_foreach_instr_safe(instr, block) {
+if (instr->type != nir_instr_type_intrinsic)
+ continue;
+
+impl_progress |= lower_instr(nir_instr_as_intrinsic(instr),
+ shader_program, shader,
+ use_binding_as_idx);
}
+ }
+ if (impl_progress) {
nir_metadata_preserve(function->impl, nir_metadata_block_index |
nir_metadata_dominance);
+ progress = true;
}
}
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Mesa (master): anv/pipeline: Lower more constant initializers earlier
Module: Mesa Branch: master Commit: c3f9d5c235734757f7a9cf2413d823b3a06cf0ad URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c3f9d5c235734757f7a9cf2413d823b3a06cf0ad Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Thu Mar 22 18:37:42 2018 -0700 anv/pipeline: Lower more constant initializers earlier Once we've gotten rid of everything but the main entrypoint, there's no reason why we should go ahead and lower them all. This is what radv does and it will make future work easier. Reviewed-by: Caio Marcelo de Oliveira Filho <caio.olive...@intel.com> --- src/intel/vulkan/anv_pipeline.c | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 4ca1e0be34..e64602d284 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -186,10 +186,12 @@ anv_shader_compile_to_nir(struct anv_pipeline *pipeline, assert(exec_list_length(>functions) == 1); entry_point->name = ralloc_strdup(entry_point, "main"); - /* Make sure we lower constant initializers on output variables so that -* nir_remove_dead_variables below sees the corresponding stores + /* Now that we've deleted all but the main function, we can go ahead and +* lower the rest of the constant initializers. We do this here so that +* nir_remove_dead_variables and split_per_member_structs below see the +* corresponding stores. */ - NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out); + NIR_PASS_V(nir, nir_lower_constant_initializers, ~0); NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_shader_in | nir_var_shader_out | nir_var_system_value); @@ -197,10 +199,6 @@ anv_shader_compile_to_nir(struct anv_pipeline *pipeline, if (stage == MESA_SHADER_FRAGMENT) NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable); - /* Now that we've deleted all but the main function, we can go ahead and -* lower the rest of the constant initializers. -*/ - NIR_PASS_V(nir, nir_lower_constant_initializers, ~0); NIR_PASS_V(nir, nir_propagate_invariant); NIR_PASS_V(nir, nir_lower_io_to_temporaries, entry_point->impl, true, false); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): spirv: Use the LOCAL_GROUP_SIZE system value
Module: Mesa
Branch: master
Commit: 14e0a222d959523252a300aec8dc94abe7d64529
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=14e0a222d959523252a300aec8dc94abe7d64529
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Wed Mar 21 17:20:00 2018 -0700
spirv: Use the LOCAL_GROUP_SIZE system value
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.olive...@intel.com>
---
src/compiler/spirv/vtn_variables.c | 17 ++---
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/src/compiler/spirv/vtn_variables.c
b/src/compiler/spirv/vtn_variables.c
index b2897407fb..0673fe8067 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1276,8 +1276,8 @@ vtn_get_builtin_location(struct vtn_builder *b,
set_mode_system_value(b, mode);
break;
case SpvBuiltInWorkgroupSize:
- /* This should already be handled */
- vtn_fail("unsupported builtin");
+ *location = SYSTEM_VALUE_LOCAL_GROUP_SIZE;
+ set_mode_system_value(b, mode);
break;
case SpvBuiltInWorkgroupId:
*location = SYSTEM_VALUE_WORK_GROUP_ID;
@@ -1407,19 +1407,6 @@ apply_var_decoration(struct vtn_builder *b, nir_variable
*nir_var,
case SpvDecorationBuiltIn: {
SpvBuiltIn builtin = dec->literals[0];
- if (builtin == SpvBuiltInWorkgroupSize) {
- /* This shouldn't be a builtin. It's actually a constant. */
- nir_var->data.mode = nir_var_global;
- nir_var->data.read_only = true;
-
- nir_constant *c = rzalloc(nir_var, nir_constant);
- c->values[0].u32[0] = b->shader->info.cs.local_size[0];
- c->values[0].u32[1] = b->shader->info.cs.local_size[1];
- c->values[0].u32[2] = b->shader->info.cs.local_size[2];
- nir_var->constant_initializer = c;
- break;
- }
-
nir_variable_mode mode = nir_var->data.mode;
vtn_get_builtin_location(b, builtin, _var->data.location, );
nir_var->data.mode = mode;
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Mesa (master): nir/lower_system_values: Support SYSTEM_VALUE_LOCAL_GROUP_SIZE
Module: Mesa
Branch: master
Commit: 131d454c35400fc61b317121ab12881140457208
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=131d454c35400fc61b317121ab12881140457208
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Wed Mar 21 17:18:05 2018 -0700
nir/lower_system_values: Support SYSTEM_VALUE_LOCAL_GROUP_SIZE
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.olive...@intel.com>
---
src/compiler/nir/nir_lower_system_values.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/compiler/nir/nir_lower_system_values.c
b/src/compiler/nir/nir_lower_system_values.c
index fb560ee21b..40e0f85dee 100644
--- a/src/compiler/nir/nir_lower_system_values.c
+++ b/src/compiler/nir/nir_lower_system_values.c
@@ -101,6 +101,16 @@ convert_block(nir_block *block, nir_builder *b)
break;
}
+ case SYSTEM_VALUE_LOCAL_GROUP_SIZE: {
+ nir_const_value local_size;
+ memset(_size, 0, sizeof(local_size));
+ local_size.u32[0] = b->shader->info.cs.local_size[0];
+ local_size.u32[1] = b->shader->info.cs.local_size[1];
+ local_size.u32[2] = b->shader->info.cs.local_size[2];
+ sysval = nir_build_imm(b, 3, 32, local_size);
+ break;
+ }
+
case SYSTEM_VALUE_VERTEX_ID:
if (b->shader->options->vertex_id_zero_based) {
sysval = nir_iadd(b,
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Mesa (master): nir: rename variables in nir_lower_io_to_temporaries for clarity
Module: Mesa
Branch: master
Commit: 67c728f7a9450b04d4de1a29f1dcfb9265a7ebfd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=67c728f7a9450b04d4de1a29f1dcfb9265a7ebfd
Author: Caio Marcelo de Oliveira Filho <caio.olive...@intel.com>
Date: Wed Apr 4 16:16:39 2018 -0700
nir: rename variables in nir_lower_io_to_temporaries for clarity
In the emit_copies() function, the use of "newv" and "temp" names made
sense when only copies from temporaries to the new variables were
being done. But now there are other calls to copy with other pairings,
and "temp" doesn't always refer to a temporary created in this
pass. Use the names "dest" and "src" instead.
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/compiler/nir/nir_lower_io_to_temporaries.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/compiler/nir/nir_lower_io_to_temporaries.c
b/src/compiler/nir/nir_lower_io_to_temporaries.c
index 301ba65892..bff04b9768 100644
--- a/src/compiler/nir/nir_lower_io_to_temporaries.c
+++ b/src/compiler/nir/nir_lower_io_to_temporaries.c
@@ -40,34 +40,34 @@ struct lower_io_state {
};
static void
-emit_copies(nir_cursor cursor, nir_shader *shader, struct exec_list *new_vars,
- struct exec_list *old_vars)
+emit_copies(nir_cursor cursor, nir_shader *shader, struct exec_list *dest_vars,
+struct exec_list *src_vars)
{
- assert(exec_list_length(new_vars) == exec_list_length(old_vars));
+ assert(exec_list_length(dest_vars) == exec_list_length(src_vars));
- foreach_two_lists(new_node, new_vars, old_node, old_vars) {
- nir_variable *newv = exec_node_data(nir_variable, new_node, node);
- nir_variable *temp = exec_node_data(nir_variable, old_node, node);
+ foreach_two_lists(dest_node, dest_vars, src_node, src_vars) {
+ nir_variable *dest = exec_node_data(nir_variable, dest_node, node);
+ nir_variable *src = exec_node_data(nir_variable, src_node, node);
/* No need to copy the contents of a non-fb_fetch_output output variable
* to the temporary allocated for it, since its initial value is
* undefined.
*/
- if (temp->data.mode == nir_var_shader_out &&
- !temp->data.fb_fetch_output)
+ if (src->data.mode == nir_var_shader_out &&
+ !src->data.fb_fetch_output)
continue;
/* Can't copy the contents of the temporary back to a read-only
* interface variable. The value of the temporary won't have been
* modified by the shader anyway.
*/
- if (newv->data.read_only)
+ if (dest->data.read_only)
continue;
nir_intrinsic_instr *copy =
nir_intrinsic_instr_create(shader, nir_intrinsic_copy_var);
- copy->variables[0] = nir_deref_var_create(copy, newv);
- copy->variables[1] = nir_deref_var_create(copy, temp);
+ copy->variables[0] = nir_deref_var_create(copy, dest);
+ copy->variables[1] = nir_deref_var_create(copy, src);
nir_instr_insert(cursor, >instr);
}
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Mesa (master): anv: Add WSI support for the I915_FORMAT_MOD_Y_TILED_CCS
Module: Mesa
Branch: master
Commit: c5b87c94d8e3bc4b11a2cd0e9f4acabe9515e4cb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c5b87c94d8e3bc4b11a2cd0e9f4acabe9515e4cb
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Tue Feb 13 14:26:05 2018 -0800
anv: Add WSI support for the I915_FORMAT_MOD_Y_TILED_CCS
v2 (Jason Ekstrand):
- Return the correct enum values from anv_layout_to_fast_clear_type
v3 (Jason Ekstrand):
- Always return ANV_FAST_CLEAR_NONE and leave doing the right thing for
the patch which adds a modifier which supports fast-clears.
Reviewed-by: Daniel Stone <dani...@collabora.com>
Tested-by: Daniel Stone <dani...@collabora.com>
Acked-by: Nanley Chery <nanley.g.ch...@intel.com>
---
src/intel/vulkan/anv_formats.c | 9
src/intel/vulkan/anv_image.c | 50 ++
2 files changed, 40 insertions(+), 19 deletions(-)
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 085706402c..3b821f10bd 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -671,9 +671,18 @@ get_wsi_format_modifier_properties_list(const struct
anv_physical_device *physic
DRM_FORMAT_MOD_LINEAR,
I915_FORMAT_MOD_X_TILED,
I915_FORMAT_MOD_Y_TILED,
+ I915_FORMAT_MOD_Y_TILED_CCS,
};
for (uint32_t i = 0; i < ARRAY_SIZE(modifiers); i++) {
+ const struct isl_drm_modifier_info *mod_info =
+ isl_drm_modifier_get_info(modifiers[i]);
+
+ if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E &&
+ !isl_format_supports_ccs_e(_device->info,
+ anv_format->planes[0].isl_format))
+ continue;
+
vk_outarray_append(, mod_props) {
mod_props->modifier = modifiers[i];
if (isl_drm_modifier_has_aux(modifiers[i]))
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index a941559eb3..42496b6414 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -519,6 +519,7 @@ score_drm_format_mod(uint64_t modifier)
case DRM_FORMAT_MOD_LINEAR: return 1;
case I915_FORMAT_MOD_X_TILED: return 2;
case I915_FORMAT_MOD_Y_TILED: return 3;
+ case I915_FORMAT_MOD_Y_TILED_CCS: return 4;
default: unreachable("bad DRM format modifier");
}
}
@@ -750,8 +751,14 @@ void anv_GetImageSubresourceLayout(
VkSubresourceLayout*layout)
{
ANV_FROM_HANDLE(anv_image, image, _image);
- const struct anv_surface *surface =
- get_surface(image, subresource->aspectMask);
+
+ const struct anv_surface *surface;
+ if (subresource->aspectMask == VK_IMAGE_ASPECT_PLANE_1_BIT_KHR &&
+ image->drm_format_mod != DRM_FORMAT_MOD_INVALID &&
+ isl_drm_modifier_has_aux(image->drm_format_mod))
+ surface = >planes[0].aux_surface;
+ else
+ surface = get_surface(image, subresource->aspectMask);
assert(__builtin_popcount(subresource->aspectMask) == 1);
@@ -866,25 +873,20 @@ anv_layout_to_aux_usage(const struct gen_device_info *
const devinfo,
}
- case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR:
+ case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR: {
assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
- /* On SKL+, the render buffer can be decompressed by the presentation
- * engine. Support for this feature has not yet landed in the wider
- * ecosystem. TODO: Update this code when support lands.
- *
- * From the BDW PRM, Vol 7, Render Target Resolve:
- *
- *If the MCS is enabled on a non-multisampled render target, the
- *render target must be resolved before being used for other
- *purposes (display, texture, CPU lock) The clear value from
- *SURFACE_STATE is written into pixels in the render target
- *indicated as clear in the MCS.
- *
- * Pre-SKL, the render buffer must be resolved before being used for
- * presentation. We can infer that the auxiliary buffer is not used.
+ /* When handing the image off to the presentation engine, we need to
+ * ensure that things are properly resolved. For images with no
+ * modifier, we assume that they follow the old rules and always need
+ * a full resolve because the PE doesn't understand any form of
+ * compression. For images with modifiers, we use the aux usage from
+ * the modifier.
*/
- return ISL_AUX_USAGE_NONE;
+ const struct isl_drm_modifier_info *mod_info =
+ isl_drm_modifier_get_info(image->drm_format_mod);
+ return mod_info ? mod_info->aux_usage : ISL_AUX_USAGE_NONE;
+ }
/* Rendering Layouts */
@@ -966,8 +968,18 @@ anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo,
case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
return ANV_FAST_CLEAR_ANY;
- case VK
Mesa (master): prog/nir: Simplify some load/store operations
Module: Mesa
Branch: master
Commit: e85b95269e49036402c3a8204450707eb6111d15
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e85b95269e49036402c3a8204450707eb6111d15
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Mon Mar 19 13:43:35 2018 -0700
prog/nir: Simplify some load/store operations
Reviewed-by: Eric Anholt <e...@anholt.net>
---
src/compiler/nir/nir_builder.h | 6 +
src/mesa/program/prog_to_nir.c | 53 +++---
2 files changed, 19 insertions(+), 40 deletions(-)
diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h
index 8f7ddf1483..d699b5ee1b 100644
--- a/src/compiler/nir/nir_builder.h
+++ b/src/compiler/nir/nir_builder.h
@@ -526,6 +526,12 @@ nir_ssa_for_alu_src(nir_builder *build, nir_alu_instr
*instr, unsigned srcn)
}
static inline nir_ssa_def *
+nir_load_reg(nir_builder *build, nir_register *reg)
+{
+ return nir_ssa_for_src(build, nir_src_for_reg(reg), reg->num_components);
+}
+
+static inline nir_ssa_def *
nir_load_var(nir_builder *build, nir_variable *var)
{
const unsigned num_components = glsl_get_vector_elements(var->type);
diff --git a/src/mesa/program/prog_to_nir.c b/src/mesa/program/prog_to_nir.c
index b49616c0cf..3ee44ce489 100644
--- a/src/mesa/program/prog_to_nir.c
+++ b/src/mesa/program/prog_to_nir.c
@@ -136,15 +136,8 @@ ptn_get_src(struct ptn_compile *c, const struct
prog_src_register *prog_src)
assert(prog_src->Index >= 0 && prog_src->Index < VARYING_SLOT_MAX);
- nir_intrinsic_instr *load =
- nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_var);
- load->num_components = 4;
- load->variables[0] = nir_deref_var_create(load,
c->input_vars[prog_src->Index]);
-
- nir_ssa_dest_init(>instr, >dest, 4, 32, NULL);
- nir_builder_instr_insert(b, >instr);
-
- src.src = nir_src_for_ssa(>dest.ssa);
+ nir_variable *var = c->input_vars[prog_src->Index];
+ src.src = nir_src_for_ssa(nir_load_var(b, var));
break;
}
case PROGRAM_STATE_VAR:
@@ -861,27 +854,17 @@ ptn_add_output_stores(struct ptn_compile *c)
nir_builder *b = >build;
nir_foreach_variable(var, >shader->outputs) {
- nir_intrinsic_instr *store =
- nir_intrinsic_instr_create(b->shader, nir_intrinsic_store_var);
- store->num_components = glsl_get_vector_elements(var->type);
- nir_intrinsic_set_write_mask(store, (1 << store->num_components) - 1);
- store->variables[0] =
- nir_deref_var_create(store, c->output_vars[var->data.location]);
-
+ nir_ssa_def *src = nir_load_reg(b, c->output_regs[var->data.location]);
if (c->prog->Target == GL_FRAGMENT_PROGRAM_ARB &&
var->data.location == FRAG_RESULT_DEPTH) {
/* result.depth has this strange convention of being the .z component
of
* a vec4 with undefined .xyw components. We resolve it to a scalar,
to
* match GLSL's gl_FragDepth and the expectations of most backends.
*/
- nir_alu_src alu_src = { NIR_SRC_INIT };
- alu_src.src = nir_src_for_reg(c->output_regs[FRAG_RESULT_DEPTH]);
- alu_src.swizzle[0] = SWIZZLE_Z;
- store->src[0] = nir_src_for_ssa(nir_fmov_alu(b, alu_src, 1));
- } else {
- store->src[0].reg.reg = c->output_regs[var->data.location];
+ src = nir_channel(b, src, 2);
}
- nir_builder_instr_insert(b, >instr);
+ unsigned num_components = glsl_get_vector_elements(var->type);
+ nir_store_var(b, var, src, (1 << num_components) - 1);
}
}
@@ -914,26 +897,16 @@ setup_registers_and_variables(struct ptn_compile *c)
*/
var->type = glsl_float_type();
-nir_intrinsic_instr *load_x =
- nir_intrinsic_instr_create(shader, nir_intrinsic_load_var);
-load_x->num_components = 1;
-load_x->variables[0] = nir_deref_var_create(load_x, var);
-nir_ssa_dest_init(_x->instr, _x->dest, 1, 32, NULL);
-nir_builder_instr_insert(b, _x->instr);
-
-nir_ssa_def *f001 = nir_vec4(b, _x->dest.ssa,
nir_imm_float(b, 0.0),
- nir_imm_float(b, 0.0),
nir_imm_float(b, 1.0));
-
nir_variable *fullvar =
nir_local_variable_create(b->impl, glsl_vec4_type(),
"fogcoord_tmp");
-nir_intrinsic_instr *store =
- nir_intrinsic_instr_create(shader, nir_intrinsic_store_var);
-store->num_components = 4;
-nir_intrinsic_set_write_mask(store, WRITEMASK_XYZW);
-store->variables[0] = nir_deref_var_create(store, fullvar);
-store->src[0] = nir_src_for_ssa(f001);
-
Mesa (master): nir/lower_vec_to_movs: Only coalesce if the vec had a SSA destination
Module: Mesa
Branch: master
Commit: 800df942eadc5356840f5cbc2ceaa8a65c01ee91
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=800df942eadc5356840f5cbc2ceaa8a65c01ee91
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Mar 23 11:05:04 2018 -0700
nir/lower_vec_to_movs: Only coalesce if the vec had a SSA destination
Otherwise we may end up trying to coalesce in a case such as
ssa_1 = fadd r1, r2
r3.x = fneg(r2);
r3 = vec4(ssa_1, ssa_1.y, ...)
and that would cause us to move the writes to r3 from the vec to the
fadd which would re-order them with respect to the write from the fneg.
In order to solve this, we just don't coalesce if the destination of the
vec is not SSA. We could try to get clever and still coalesce if there
are no writes to the destination of the vec between the vec and the ALU
source. However, since registers only come from phi webs and indirects,
the chances of having a vec with a register destination that is actually
coalescable into its source is very slim.
Shader-db results on Haswell:
total instructions in shared programs: 13657906 -> 13659101 (<.01%)
instructions in affected programs: 149291 -> 150486 (0.80%)
helped: 0
HURT: 592
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105440
Fixes: 2458ea95c56 "nir/lower_vec_to_movs: Coalesce movs on-the-fly when
possible"
Reported-by: Vadym Shovkoplias <vadym.shovkopl...@globallogic.com>
Tested-by: Vadym Shovkoplias <vadym.shovkopl...@globallogic.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
---
src/compiler/nir/nir_lower_vec_to_movs.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir_lower_vec_to_movs.c
b/src/compiler/nir/nir_lower_vec_to_movs.c
index 711ddd38bd..8b24376b0a 100644
--- a/src/compiler/nir/nir_lower_vec_to_movs.c
+++ b/src/compiler/nir/nir_lower_vec_to_movs.c
@@ -230,6 +230,7 @@ lower_vec_to_movs_block(nir_block *block, nir_function_impl
*impl)
continue; /* The loop */
}
+ bool vec_had_ssa_dest = vec->dest.dest.is_ssa;
if (vec->dest.dest.is_ssa) {
/* Since we insert multiple MOVs, we have a register destination. */
nir_register *reg = nir_local_reg_create(impl);
@@ -263,7 +264,11 @@ lower_vec_to_movs_block(nir_block *block,
nir_function_impl *impl)
if (!(vec->dest.write_mask & (1 << i)))
continue;
- if (!(finished_write_mask & (1 << i)))
+ /* Coalescing moves the register writes from the vec up to the ALU
+ * instruction in the source. We can only do this if the original
+ * vecN had an SSA destination.
+ */
+ if (vec_had_ssa_dest && !(finished_write_mask & (1 << i)))
finished_write_mask |= try_coalesce(vec, i);
if (!(finished_write_mask & (1 << i)))
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Mesa (master): anv: Fix close(fd) before import issue in vkCreateDmaBufImageINTEL
Module: Mesa Branch: master Commit: 5bbde9b80fe2e6a384db5d636725b8f8065bc5c5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5bbde9b80fe2e6a384db5d636725b8f8065bc5c5 Author: Kevin Strasser <kevin.stras...@intel.com> Date: Tue Apr 3 14:21:34 2018 -0700 anv: Fix close(fd) before import issue in vkCreateDmaBufImageINTEL If we close the fd before calling DRM_IOCTL_PRIME_FD_TO_HANDLE the kernel will hit a -EBADF error. Move the close(fd) call to the end of anv_CreateDmaBufImageINTEL(). Signed-off-by: Kevin Strasser <kevin.stras...@intel.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/intel/vulkan/anv_intel.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/vulkan/anv_intel.c b/src/intel/vulkan/anv_intel.c index 82373f0c91..976c83308e 100644 --- a/src/intel/vulkan/anv_intel.c +++ b/src/intel/vulkan/anv_intel.c @@ -71,8 +71,6 @@ VkResult anv_CreateDmaBufImageINTEL( if (result != VK_SUCCESS) goto fail; - close(pCreateInfo->fd); - image = anv_image_from_handle(image_h); result = anv_bo_cache_import(device, >bo_cache, @@ -105,6 +103,8 @@ VkResult anv_CreateDmaBufImageINTEL( *pMem = anv_device_memory_to_handle(mem); *pImage = anv_image_to_handle(image); + close(pCreateInfo->fd); + return VK_SUCCESS; fail_import: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nir/validator: Validate that all used variables exist
Module: Mesa
Branch: master
Commit: 9978f55cd1d28ccc5014ac56cafdd997eac5f222
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9978f55cd1d28ccc5014ac56cafdd997eac5f222
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Tue Mar 20 16:57:51 2018 -0700
nir/validator: Validate that all used variables exist
We were validating this for locals but nothing else.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/compiler/nir/nir_validate.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/src/compiler/nir/nir_validate.c b/src/compiler/nir/nir_validate.c
index 565cb2ef16..5566ceb298 100644
--- a/src/compiler/nir/nir_validate.c
+++ b/src/compiler/nir/nir_validate.c
@@ -96,7 +96,9 @@ typedef struct {
/* bitset of registers we have currently found; used to check uniqueness */
BITSET_WORD *regs_found;
- /* map of local variable -> function implementation where it is defined */
+ /* map of variable -> function implementation where it is defined or NULL
+* if it is a global variable
+*/
struct hash_table *var_defs;
/* map of instruction/var/etc to failed assert string */
@@ -450,12 +452,10 @@ validate_deref_chain(nir_deref *deref, nir_variable_mode
mode,
static void
validate_var_use(nir_variable *var, validate_state *state)
{
- if (var->data.mode == nir_var_local) {
- struct hash_entry *entry = _mesa_hash_table_search(state->var_defs, var);
-
- validate_assert(state, entry);
+ struct hash_entry *entry = _mesa_hash_table_search(state->var_defs, var);
+ validate_assert(state, entry);
+ if (var->data.mode == nir_var_local)
validate_assert(state, (nir_function_impl *) entry->data == state->impl);
- }
}
static void
@@ -1002,9 +1002,8 @@ validate_var_decl(nir_variable *var, bool is_global,
validate_state *state)
* support)
*/
- if (!is_global) {
- _mesa_hash_table_insert(state->var_defs, var, state->impl);
- }
+ _mesa_hash_table_insert(state->var_defs, var,
+ is_global ? NULL : state->impl);
state->var = NULL;
}
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Mesa (master): intel/vec4: Set channel_sizes for MOV_INDIRECT sources
Module: Mesa
Branch: master
Commit: 2b977989f3f01c186677988494bbf9b7342b31f2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b977989f3f01c186677988494bbf9b7342b31f2
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Mar 23 09:27:55 2018 -0700
intel/vec4: Set channel_sizes for MOV_INDIRECT sources
Otherwise, any indirect push constant access results in an assertion
failure when we start digging through the channel_sizes array. This
fixes dEQP-VK.pipeline.push_constant.graphics_pipeline.dynamic_index_vert
on Haswell. It should be a harmless no-op for GL since indirect push
constants aren't used there.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Fixes: e69e5c7006d "i965/vec4: load dvec3/4 uniforms first in the..."
---
src/intel/compiler/brw_vec4.cpp | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 2f352a1118..218925ccb1 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -695,8 +695,11 @@ vec4_visitor::pack_uniform_registers()
* the next part of our packing algorithm.
*/
int reg = inst->src[0].nr;
- for (unsigned i = 0; i < vec4s_read; i++)
+ int channel_size = type_sz(inst->src[0].type) / 4;
+ for (unsigned i = 0; i < vec4s_read; i++) {
chans_used[reg + i] = 4;
+channel_sizes[reg + i] = MAX2(channel_sizes[reg + i],
channel_size);
+ }
}
}
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Mesa (master): nir/lower_indirect_derefs: Support interp_var_at intrinsics
Module: Mesa
Branch: master
Commit: 6018f5b07966a0f85dea1ee6775d50a8c85fdee1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6018f5b07966a0f85dea1ee6775d50a8c85fdee1
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Tue Mar 20 12:12:12 2018 -0700
nir/lower_indirect_derefs: Support interp_var_at intrinsics
This fixes the fs-interpolateAtCentroid-block-array piglit test on i965.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Cc: mesa-sta...@lists.freedesktop.org
---
src/compiler/nir/nir_lower_indirect_derefs.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/compiler/nir/nir_lower_indirect_derefs.c
b/src/compiler/nir/nir_lower_indirect_derefs.c
index c949224b15..02f202dea3 100644
--- a/src/compiler/nir/nir_lower_indirect_derefs.c
+++ b/src/compiler/nir/nir_lower_indirect_derefs.c
@@ -95,9 +95,15 @@ emit_load_store(nir_builder *b, nir_intrinsic_instr
*orig_instr,
if (src == NULL) {
/* This is a load instruction */
nir_intrinsic_instr *load =
- nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_var);
+ nir_intrinsic_instr_create(b->shader, orig_instr->intrinsic);
load->num_components = orig_instr->num_components;
load->variables[0] = nir_deref_var_clone(deref, load);
+
+ /* Copy over any sources. This is needed for interp_var_at */
+ for (unsigned i = 0;
+ i < nir_intrinsic_infos[orig_instr->intrinsic].num_srcs; i++)
+ nir_src_copy(>src[i], _instr->src[i], load);
+
unsigned bit_size = orig_instr->dest.ssa.bit_size;
nir_ssa_dest_init(>instr, >dest,
load->num_components, bit_size, NULL);
@@ -142,6 +148,9 @@ lower_indirect_block(nir_block *block, nir_builder *b,
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
if (intrin->intrinsic != nir_intrinsic_load_var &&
+ intrin->intrinsic != nir_intrinsic_interp_var_at_centroid &&
+ intrin->intrinsic != nir_intrinsic_interp_var_at_sample &&
+ intrin->intrinsic != nir_intrinsic_interp_var_at_offset &&
intrin->intrinsic != nir_intrinsic_store_var)
continue;
@@ -158,7 +167,7 @@ lower_indirect_block(nir_block *block, nir_builder *b,
b->cursor = nir_before_instr(>instr);
- if (intrin->intrinsic == nir_intrinsic_load_var) {
+ if (intrin->intrinsic != nir_intrinsic_store_var) {
nir_ssa_def *result;
emit_load_store(b, intrin, intrin->variables[0],
>variables[0]->deref, , NULL);
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Mesa (master): nir: Add src/dest num_components helpers
Module: Mesa
Branch: master
Commit: 956f17395bfcf7f8ce9dd5ac9fd14a13e86f3a8f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=956f17395bfcf7f8ce9dd5ac9fd14a13e86f3a8f
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Wed Mar 14 21:44:51 2018 -0700
nir: Add src/dest num_components helpers
We already have these for bit_size
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/compiler/nir/nir.h | 12
1 file changed, 12 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 9fff1f4647..5ba6a1f068 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -632,11 +632,23 @@ nir_src_bit_size(nir_src src)
}
static inline unsigned
+nir_src_num_components(nir_src src)
+{
+ return src.is_ssa ? src.ssa->num_components : src.reg.reg->num_components;
+}
+
+static inline unsigned
nir_dest_bit_size(nir_dest dest)
{
return dest.is_ssa ? dest.ssa.bit_size : dest.reg.reg->bit_size;
}
+static inline unsigned
+nir_dest_num_components(nir_dest dest)
+{
+ return dest.is_ssa ? dest.ssa.num_components : dest.reg.reg->num_components;
+}
+
void nir_src_copy(nir_src *dest, const nir_src *src, void *instr_or_if);
void nir_dest_copy(nir_dest *dest, const nir_dest *src, nir_instr *instr);
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Mesa (master): nir: Return a cursor from nir_instr_remove
Module: Mesa
Branch: master
Commit: a1452a94fca458c1129f527b775e1124a449ed2b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1452a94fca458c1129f527b775e1124a449ed2b
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Mar 16 09:52:04 2018 -0700
nir: Return a cursor from nir_instr_remove
Because nir_instr_remove is an inline wrapper around nir_instr_remove_v,
the compiler should be able to tell that the return value is unused and
not emit the extra code in most cases.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/compiler/nir/nir.c| 2 +-
src/compiler/nir/nir.h| 16 +++-
src/compiler/nir/nir_opt_copy_prop_vars.c | 19 ++-
3 files changed, 18 insertions(+), 19 deletions(-)
diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index 3fb16e6ca5..8364197480 100644
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -1159,7 +1159,7 @@ remove_defs_uses(nir_instr *instr)
nir_foreach_src(instr, remove_use_cb, instr);
}
-void nir_instr_remove(nir_instr *instr)
+void nir_instr_remove_v(nir_instr *instr)
{
remove_defs_uses(instr);
exec_node_remove(>node);
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 5ba6a1f068..cc7c401b40 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2274,7 +2274,21 @@ nir_instr_insert_after_cf_list(struct exec_list *list,
nir_instr *after)
nir_instr_insert(nir_after_cf_list(list), after);
}
-void nir_instr_remove(nir_instr *instr);
+void nir_instr_remove_v(nir_instr *instr);
+
+static inline nir_cursor
+nir_instr_remove(nir_instr *instr)
+{
+ nir_cursor cursor;
+ nir_instr *prev = nir_instr_prev(instr);
+ if (prev) {
+ cursor = nir_after_instr(prev);
+ } else {
+ cursor = nir_before_block(instr->block);
+ }
+ nir_instr_remove_v(instr);
+ return cursor;
+}
/** @} */
diff --git a/src/compiler/nir/nir_opt_copy_prop_vars.c
b/src/compiler/nir/nir_opt_copy_prop_vars.c
index 89ddc8dd40..cc8f00f9d3 100644
--- a/src/compiler/nir/nir_opt_copy_prop_vars.c
+++ b/src/compiler/nir/nir_opt_copy_prop_vars.c
@@ -349,21 +349,6 @@ store_to_entry(struct copy_prop_var_state *state, struct
copy_entry *entry,
}
}
-/* Remove an instruction and return a cursor pointing to where it was */
-static nir_cursor
-instr_remove_cursor(nir_instr *instr)
-{
- nir_cursor cursor;
- nir_instr *prev = nir_instr_prev(instr);
- if (prev) {
- cursor = nir_after_instr(prev);
- } else {
- cursor = nir_before_block(instr->block);
- }
- nir_instr_remove(instr);
- return cursor;
-}
-
/* Do a "load" from an SSA-based entry return it in "value" as a value with a
* single SSA def. Because an entry could reference up to 4 different SSA
* defs, a vecN operation may be inserted to combine them into a single SSA
@@ -396,7 +381,7 @@ load_from_ssa_entry_value(struct copy_prop_var_state *state,
if (all_same) {
/* Our work here is done */
- b->cursor = instr_remove_cursor(>instr);
+ b->cursor = nir_instr_remove(>instr);
intrin->instr.block = NULL;
return true;
}
@@ -594,7 +579,7 @@ load_from_deref_entry_value(struct copy_prop_var_state
*state,
value_tail->child = nir_deref_clone(src_tail->child, value_tail);
}
- b->cursor = instr_remove_cursor(>instr);
+ b->cursor = nir_instr_remove(>instr);
return true;
}
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Mesa (master): nir/vars_to_ssa: Remove copies from the correct set
Module: Mesa Branch: master Commit: 0517d65f9639349d626aeb2af48ba9e4e605900d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0517d65f9639349d626aeb2af48ba9e4e605900d Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Thu Mar 15 16:42:13 2018 -0700 nir/vars_to_ssa: Remove copies from the correct set Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> Cc: mesa-sta...@lists.freedesktop.org --- src/compiler/nir/nir_lower_vars_to_ssa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_lower_vars_to_ssa.c b/src/compiler/nir/nir_lower_vars_to_ssa.c index e8cfe308d2..0cc65143e7 100644 --- a/src/compiler/nir/nir_lower_vars_to_ssa.c +++ b/src/compiler/nir/nir_lower_vars_to_ssa.c @@ -464,7 +464,7 @@ lower_copies_to_load_store(struct deref_node *node, struct set_entry *arg_entry = _mesa_set_search(arg_node->copies, copy); assert(arg_entry); - _mesa_set_remove(node->copies, arg_entry); + _mesa_set_remove(arg_node->copies, arg_entry); } nir_instr_remove(>instr); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel/fs: Don't emit a des copy for image ops with has_dest == false
Module: Mesa
Branch: master
Commit: 7e38f49a8f6a1ee765613e581844f8e9af414b10
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e38f49a8f6a1ee765613e581844f8e9af414b10
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Tue Mar 27 16:27:20 2018 -0700
intel/fs: Don't emit a des copy for image ops with has_dest == false
This was causing us to walk dest_components times over a thing with no
destination. This happened to work because all of the image intrinsics
without a destination also happened to have dest_components == 0. We
shouldn't be reading dest_components if has_dest == false.
Reviewed-by: Matt Turner <matts...@gmail.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
---
src/intel/compiler/brw_fs_nir.cpp | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index f5d5399259..197d41062e 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -3848,9 +3848,12 @@ fs_visitor::nir_emit_intrinsic(const fs_builder ,
nir_intrinsic_instr *instr
get_image_atomic_op(instr->intrinsic, type));
/* Assign the result. */
- for (unsigned c = 0; c < info->dest_components; ++c)
- bld.MOV(offset(retype(dest, base_type), bld, c),
- offset(tmp, bld, c));
+ if (nir_intrinsic_infos[instr->intrinsic].has_dest) {
+ for (unsigned c = 0; c < info->dest_components; ++c) {
+bld.MOV(offset(retype(dest, base_type), bld, c),
+offset(tmp, bld, c));
+ }
+ }
break;
}
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Mesa (master): nir/intrinsics: Don't report negative dest_components
Module: Mesa
Branch: master
Commit: 5f21a7afe072f8a6e558ccc47407a0a94e0d1313
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f21a7afe072f8a6e558ccc47407a0a94e0d1313
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Tue Mar 27 16:12:16 2018 -0700
nir/intrinsics: Don't report negative dest_components
I have no idea why but having dest_components == -1 was causing a memory
leak somewhere. Without this, you can't get through a full shader-db
run without running out of memory.
Reviewed-by: Rob Clark <robdcl...@gmail.com>
---
src/compiler/nir/nir_intrinsics_c.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir_intrinsics_c.py
b/src/compiler/nir/nir_intrinsics_c.py
index 339214ac53..4410bc6346 100644
--- a/src/compiler/nir/nir_intrinsics_c.py
+++ b/src/compiler/nir/nir_intrinsics_c.py
@@ -35,7 +35,7 @@ const nir_intrinsic_info
nir_intrinsic_infos[nir_num_intrinsics] = {
},
% endif
.has_dest = ${"true" if opcode.has_dest else "false"},
- .dest_components = ${opcode.dest_components},
+ .dest_components = ${max(opcode.dest_components, 0)},
.num_variables = ${opcode.num_variables},
.num_indices = ${opcode.num_indices},
% if opcode.indices:
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