Mesa (master): meson: Fix with_intel_vk and with_amd_vk variables
Module: Mesa
Branch: master
Commit: b0c57740278f6c05b9b514e0011bb3646acd97ef
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0c57740278f6c05b9b514e0011bb3646acd97ef
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Tue Apr 24 18:12:51 2018 -0700
meson: Fix with_intel_vk and with_amd_vk variables
Fixes: 5608d0a2cee "meson: use array type options"
Cc: Dylan Baker <dy...@pnwbakers.com>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>
---
meson.build | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/meson.build b/meson.build
index 52a1075823..c0e5c94d79 100644
--- a/meson.build
+++ b/meson.build
@@ -213,8 +213,8 @@ if _vulkan_drivers.contains('auto')
endif
endif
if _vulkan_drivers != ['']
- with_intel_vk = _drivers.contains('intel')
- with_amd_vk = _drivers.contains('amd')
+ with_intel_vk = _vulkan_drivers.contains('intel')
+ with_amd_vk = _vulkan_drivers.contains('amd')
with_any_vk = true
endif
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Mesa (master): anv: Add gen11 to anv_genX_call
Module: Mesa Branch: master Commit: af8535d02f9ca896292501cb4bb0e658c5229007 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=af8535d02f9ca896292501cb4bb0e658c5229007 Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Thu Mar 22 12:04:12 2018 -0700 anv: Add gen11 to anv_genX_call Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> --- src/intel/vulkan/anv_cmd_buffer.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/intel/vulkan/anv_cmd_buffer.c b/src/intel/vulkan/anv_cmd_buffer.c index 8f4bf3f0bb..33687920a3 100644 --- a/src/intel/vulkan/anv_cmd_buffer.c +++ b/src/intel/vulkan/anv_cmd_buffer.c @@ -332,6 +332,9 @@ VkResult anv_ResetCommandBuffer( case 10:\ gen10_##func(__VA_ARGS__); \ break; \ + case 11:\ + gen11_##func(__VA_ARGS__); \ + break; \ default:\ assert(!"Unknown hardware generation"); \ } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv: Set genX_table for gen11
Module: Mesa
Branch: master
Commit: d60eaf7b1fe154bd96408c4a9ec5b400293e47f1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d60eaf7b1fe154bd96408c4a9ec5b400293e47f1
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Fri Mar 23 14:55:52 2018 -0700
anv: Set genX_table for gen11
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
src/intel/vulkan/anv_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 4cacba9343..d400a1328b 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1367,6 +1367,9 @@ anv_device_init_dispatch(struct anv_device *device)
{
const struct anv_dispatch_table *genX_table;
switch (device->info.gen) {
+ case 11:
+ genX_table = _dispatch_table;
+ break;
case 10:
genX_table = _dispatch_table;
break;
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Mesa (master): glsl: Remove api_enabled tracking for transform feedback
Module: Mesa
Branch: master
Commit: 9b473f9e3cc6820a6d1441e046be5ece22e03d17
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b473f9e3cc6820a6d1441e046be5ece22e03d17
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Tue Mar 13 10:49:28 2018 -0700
glsl: Remove api_enabled tracking for transform feedback
We used this to prevent usage of the disk shader cache when transform
feedback was enabled via the GL API. This is no longer used.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105444
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
---
src/compiler/glsl/link_varyings.cpp | 2 --
src/mesa/main/mtypes.h | 3 ---
2 files changed, 5 deletions(-)
diff --git a/src/compiler/glsl/link_varyings.cpp
b/src/compiler/glsl/link_varyings.cpp
index 0a484ce132..1fdfcb877d 100644
--- a/src/compiler/glsl/link_varyings.cpp
+++ b/src/compiler/glsl/link_varyings.cpp
@@ -1336,8 +1336,6 @@ store_tfeedback_info(struct gl_context *ctx, struct
gl_shader_program *prog,
if (has_xfb_qualifiers) {
qsort(tfeedback_decls, num_tfeedback_decls, sizeof(*tfeedback_decls),
cmp_xfb_offset);
- } else {
- xfb_prog->sh.LinkedTransformFeedback->api_enabled = true;
}
xfb_prog->sh.LinkedTransformFeedback->Varyings =
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 734fefc97f..5ee27d9977 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1861,9 +1861,6 @@ struct gl_transform_feedback_buffer
/** Post-link transform feedback info. */
struct gl_transform_feedback_info
{
- /* Was xfb enabled via the api or in shader layout qualifiers */
- bool api_enabled;
-
unsigned NumOutputs;
/* Bitmask of active buffer indices. */
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Mesa (master): i965: Allow disk shader cache usage with LINKING_SUCCESS status
Module: Mesa Branch: master Commit: d2b74ca2b503e1b8c1e58ac1c33d3631e1b30d6e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2b74ca2b503e1b8c1e58ac1c33d3631e1b30d6e Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Tue Mar 13 12:14:23 2018 -0700 i965: Allow disk shader cache usage with LINKING_SUCCESS status Currently, we only look in the disk shader cache if we see that the shader program is in the cache during the link step. If the shader cache entry isn't found during the program link, there are still some (fairly unlikely) scenarios where later it might be useful to search the cache for gen binary programs. 1. If the cache evicts the serialized glsl cache, there might still be valid gen program entries in the disk cache. 2. If two applications are running in parallel, then it is possible that one may write out the cached gen program item which the other application can then make use of. Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Tapani Pälli <tapani.pa...@intel.com> Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com> --- src/mesa/drivers/dri/i965/brw_disk_cache.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_disk_cache.c b/src/mesa/drivers/dri/i965/brw_disk_cache.c index c77e921b6a..ee6067ca51 100644 --- a/src/mesa/drivers/dri/i965/brw_disk_cache.c +++ b/src/mesa/drivers/dri/i965/brw_disk_cache.c @@ -283,9 +283,6 @@ brw_disk_cache_upload_program(struct brw_context *brw, gl_shader_stage stage) if (brw->ctx._Shader->Flags & GLSL_CACHE_FALLBACK) goto fail; - if (prog->sh.data->LinkStatus != LINKING_SKIPPED) - goto fail; - if (!read_and_upload(brw, cache, prog, stage)) goto fail; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Allow disk shader cache usage with transform feedback
Module: Mesa Branch: master Commit: fc4a7aaa8297370ba505b306b91a71a3b8545d18 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc4a7aaa8297370ba505b306b91a71a3b8545d18 Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Tue Mar 13 10:47:19 2018 -0700 i965: Allow disk shader cache usage with transform feedback Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105444 Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Tapani Pälli <tapani.pa...@intel.com> Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com> --- src/mesa/drivers/dri/i965/brw_disk_cache.c | 8 1 file changed, 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_disk_cache.c b/src/mesa/drivers/dri/i965/brw_disk_cache.c index 0671dd20f8..c77e921b6a 100644 --- a/src/mesa/drivers/dri/i965/brw_disk_cache.c +++ b/src/mesa/drivers/dri/i965/brw_disk_cache.c @@ -280,14 +280,6 @@ brw_disk_cache_upload_program(struct brw_context *brw, gl_shader_stage stage) if (prog == NULL) return false; - /* FIXME: For now we don't read from the cache if transform feedback is -* enabled via the API. However the shader cache does support transform -* feedback when enabled via in shader xfb qualifiers. -*/ - if (prog->sh.LinkedTransformFeedback && - prog->sh.LinkedTransformFeedback->api_enabled) - return false; - if (brw->ctx._Shader->Flags & GLSL_CACHE_FALLBACK) goto fail; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl/shader_cache: Allow shader cache usage with transform feedback
Module: Mesa
Branch: master
Commit: 6d830940f78109db44293d41e74d9ec0a47da49b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d830940f78109db44293d41e74d9ec0a47da49b
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Tue Mar 13 10:44:39 2018 -0700
glsl/shader_cache: Allow shader cache usage with transform feedback
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105444
Suggested-by: Timothy Arceri <tarc...@itsqueeze.com>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
---
src/compiler/glsl/linker.cpp | 11 +--
src/compiler/glsl/shader_cache.cpp | 6 ++
2 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index 1444b68cb0..af09b7d03e 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -4773,16 +4773,7 @@ link_shaders(struct gl_context *ctx, struct
gl_shader_program *prog)
}
#ifdef ENABLE_SHADER_CACHE
- /* If transform feedback used on the program then compile all shaders. */
- bool skip_cache = false;
- if (prog->TransformFeedback.NumVarying > 0) {
- for (unsigned i = 0; i < prog->NumShaders; i++) {
- _mesa_glsl_compile_shader(ctx, prog->Shaders[i], false, false, true);
- }
- skip_cache = true;
- }
-
- if (!skip_cache && shader_cache_read_program_metadata(ctx, prog))
+ if (shader_cache_read_program_metadata(ctx, prog))
return;
#endif
diff --git a/src/compiler/glsl/shader_cache.cpp
b/src/compiler/glsl/shader_cache.cpp
index bf884af790..e43ed7aa67 100644
--- a/src/compiler/glsl/shader_cache.cpp
+++ b/src/compiler/glsl/shader_cache.cpp
@@ -160,6 +160,12 @@ shader_cache_read_program_metadata(struct gl_context *ctx,
prog->FragDataBindings->iterate(create_binding_str, );
ralloc_strcat(, "fbi: ");
prog->FragDataIndexBindings->iterate(create_binding_str, );
+ ralloc_asprintf_append(, "tf: %d ", prog->TransformFeedback.BufferMode);
+ for (unsigned int i = 0; i < prog->TransformFeedback.NumVarying; i++) {
+ ralloc_asprintf_append(, "%s:%d ",
+ prog->TransformFeedback.VaryingNames[i],
+ prog->TransformFeedback.BufferStride[i]);
+ }
/* SSO has an effect on the linked program so include this when generating
* the sha also.
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Mesa (master): glsl/serialize: Save shader program metadata sha1
Module: Mesa
Branch: master
Commit: b5baaee0d6b06a2c021d1b2673a056ada733a2a9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5baaee0d6b06a2c021d1b2673a056ada733a2a9
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sat Mar 10 01:59:47 2018 -0800
glsl/serialize: Save shader program metadata sha1
When the shader cache is used, this can be generated. In fact, the
shader cache uses this sha1 to lookup the serialized GL shader
program.
If a GL shader program is restored with ProgramBinary, the shaders are
not available, and therefore the correct sha1 cannot be generated. If
this is restored, then we can use the shader cache to restore the
binary programs to the program that was loaded with ProgramBinary.
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>
---
src/compiler/glsl/serialize.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/src/compiler/glsl/serialize.cpp b/src/compiler/glsl/serialize.cpp
index 9d2033bddf..1fdbaa990f 100644
--- a/src/compiler/glsl/serialize.cpp
+++ b/src/compiler/glsl/serialize.cpp
@@ -1163,6 +1163,8 @@ extern "C" void
serialize_glsl_program(struct blob *blob, struct gl_context *ctx,
struct gl_shader_program *prog)
{
+ blob_write_bytes(blob, prog->data->sha1, sizeof(prog->data->sha1));
+
write_uniforms(blob, prog);
write_hash_tables(blob, prog);
@@ -1219,6 +1221,8 @@ deserialize_glsl_program(struct blob_reader *blob, struct
gl_context *ctx,
assert(prog->data->UniformStorage == NULL);
+ blob_copy_bytes(blob, prog->data->sha1, sizeof(prog->data->sha1));
+
read_uniforms(blob, prog);
read_hash_tables(blob, prog);
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Mesa (master): main/program_binary: In ProgramBinary set link status as LINKING_SKIPPED
Module: Mesa Branch: master Commit: 2ed288363fe8dced45f06b7cd66adbbf703a2012 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ed288363fe8dced45f06b7cd66adbbf703a2012 Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Sun Mar 11 01:18:55 2018 -0800 main/program_binary: In ProgramBinary set link status as LINKING_SKIPPED This change allows the disk shader cache to work with programs loaded with ProgramBinary. Drivers check for LINKING_SKIPPED, and if set, then they try to use the shader cache. Since the program loaded by ProgramBinary is similar to loading the shader from the disk cache, this is probably more appropriate. Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Tapani Pälli <tapani.pa...@intel.com> Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com> --- src/mesa/main/program_binary.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/main/program_binary.c b/src/mesa/main/program_binary.c index 3df7005934..021f6315e7 100644 --- a/src/mesa/main/program_binary.c +++ b/src/mesa/main/program_binary.c @@ -287,5 +287,5 @@ _mesa_program_binary(struct gl_context *ctx, struct gl_shader_program *sh_prog, return; } - sh_prog->data->LinkStatus = LINKING_SUCCESS; + sh_prog->data->LinkStatus = LINKING_SKIPPED; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Add INTEL_DEBUG stages support for disk shader cache
Module: Mesa
Branch: master
Commit: d07a49fb1840bb441e600ce942cb0088e7ea15c7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d07a49fb1840bb441e600ce942cb0088e7ea15c7
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Fri Mar 16 16:44:22 2018 -0700
i965: Add INTEL_DEBUG stages support for disk shader cache
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
---
src/mesa/drivers/dri/i965/brw_disk_cache.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_disk_cache.c
b/src/mesa/drivers/dri/i965/brw_disk_cache.c
index 41f742e858..0671dd20f8 100644
--- a/src/mesa/drivers/dri/i965/brw_disk_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_disk_cache.c
@@ -31,6 +31,9 @@
#include "util/macros.h"
#include "util/mesa-sha1.h"
+#include "compiler/brw_eu.h"
+#include "common/gen_debug.h"
+
#include "brw_context.h"
#include "brw_program.h"
#include "brw_cs.h"
@@ -39,6 +42,16 @@
#include "brw_vs.h"
#include "brw_wm.h"
+static bool
+debug_enabled_for_stage(gl_shader_stage stage)
+{
+ static const uint64_t stage_debug_flags[] = {
+ DEBUG_VS, DEBUG_TCS, DEBUG_TES, DEBUG_GS, DEBUG_WM, DEBUG_CS,
+ };
+ assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_debug_flags));
+ return (INTEL_DEBUG & stage_debug_flags[stage]) != 0;
+}
+
static void
gen_shader_sha1(struct brw_context *brw, struct gl_program *prog,
gl_shader_stage stage, void *key, unsigned char *out_sha1)
@@ -230,6 +243,19 @@ read_and_upload(struct brw_context *brw, struct disk_cache
*cache,
brw_alloc_stage_scratch(brw, stage_state, prog_data->total_scratch);
+ if (unlikely(debug_enabled_for_stage(stage))) {
+ fprintf(stderr, "NIR for %s program %d loaded from disk shader cache:\n",
+ _mesa_shader_stage_to_abbrev(stage), brw_program(prog)->id);
+ brw_program_deserialize_nir(>ctx, prog, stage);
+ nir_shader *nir = prog->nir;
+ nir_print_shader(nir, stderr);
+ fprintf(stderr, "Native code for %s %s shader %s from disk cache:\n",
+ nir->info.label ? nir->info.label : "unnamed",
+ _mesa_shader_stage_to_string(nir->info.stage), nir->info.name);
+ brw_disassemble(>screen->devinfo, program, 0,
+ prog_data->program_size, stderr);
+ }
+
brw_upload_cache(>cache, cache_id, _key, brw_prog_key_size(stage),
program, prog_data->program_size, prog_data,
brw_prog_data_size(stage), _state->prog_offset,
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Mesa (master): intel/vulkan: Hard code CS scratch_ids_per_subslice for Cherryview
Module: Mesa
Branch: master
Commit: 24b415270ffeef873ba4772d1b3c7c185c9b1958
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=24b415270ffeef873ba4772d1b3c7c185c9b1958
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Tue Mar 6 23:28:00 2018 -0800
intel/vulkan: Hard code CS scratch_ids_per_subslice for Cherryview
Ken suggested that we might be underallocating scratch space on HD
400. Allocating scratch space as though there was actually 8 EUs
seems to help with a GPU hang seen on synmark CSDof.
Cc: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/vulkan/anv_allocator.c | 45 +---
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index fe14d6cfab..a27af4eccc 100644
--- a/src/intel/vulkan/anv_allocator.c
+++ b/src/intel/vulkan/anv_allocator.c
@@ -1097,24 +1097,35 @@ anv_scratch_pool_alloc(struct anv_device *device,
struct anv_scratch_pool *pool,
>instance->physicalDevice;
const struct gen_device_info *devinfo = _device->info;
- /* WaCSScratchSize:hsw
-*
-* Haswell's scratch space address calculation appears to be sparse
-* rather than tightly packed. The Thread ID has bits indicating which
-* subslice, EU within a subslice, and thread within an EU it is.
-* There's a maximum of two slices and two subslices, so these can be
-* stored with a single bit. Even though there are only 10 EUs per
-* subslice, this is stored in 4 bits, so there's an effective maximum
-* value of 16 EUs. Similarly, although there are only 7 threads per EU,
-* this is stored in a 3 bit number, giving an effective maximum value
-* of 8 threads per EU.
-*
-* This means that we need to use 16 * 8 instead of 10 * 7 for the
-* number of threads per subslice.
-*/
const unsigned subslices = MAX2(physical_device->subslice_total, 1);
- const unsigned scratch_ids_per_subslice =
- device->info.is_haswell ? 16 * 8 : devinfo->max_cs_threads;
+
+ unsigned scratch_ids_per_subslice;
+ if (devinfo->is_haswell) {
+ /* WaCSScratchSize:hsw
+ *
+ * Haswell's scratch space address calculation appears to be sparse
+ * rather than tightly packed. The Thread ID has bits indicating
+ * which subslice, EU within a subslice, and thread within an EU it
+ * is. There's a maximum of two slices and two subslices, so these
+ * can be stored with a single bit. Even though there are only 10 EUs
+ * per subslice, this is stored in 4 bits, so there's an effective
+ * maximum value of 16 EUs. Similarly, although there are only 7
+ * threads per EU, this is stored in a 3 bit number, giving an
+ * effective maximum value of 8 threads per EU.
+ *
+ * This means that we need to use 16 * 8 instead of 10 * 7 for the
+ * number of threads per subslice.
+ */
+ scratch_ids_per_subslice = 16 * 8;
+ } else if (devinfo->is_cherryview) {
+ /* Cherryview devices have either 6 or 8 EUs per subslice, and each EU
+ * has 7 threads. The 6 EU devices appear to calculate thread IDs as if
+ * it had 8 EUs.
+ */
+ scratch_ids_per_subslice = 8 * 7;
+ } else {
+ scratch_ids_per_subslice = devinfo->max_cs_threads;
+ }
uint32_t max_threads[] = {
[MESA_SHADER_VERTEX] = devinfo->max_vs_threads,
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Mesa (master): i965: Hard code CS scratch_ids_per_subslice for Cherryview
Module: Mesa
Branch: master
Commit: 06e3bd02c01e499332a9c02b40f506df9695bced
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=06e3bd02c01e499332a9c02b40f506df9695bced
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Tue Mar 6 08:35:50 2018 -0800
i965: Hard code CS scratch_ids_per_subslice for Cherryview
Ken suggested that we might be underallocating scratch space on HD
400. Allocating scratch space as though there was actually 8 EUs
seems to help with a GPU hang seen on synmark CSDof.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104636
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105290
Cc: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Tested-by: Eero Tamminen <eero.t.tammi...@intel.com>
---
src/mesa/drivers/dri/i965/brw_program.c | 44 -
1 file changed, 27 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_program.c
b/src/mesa/drivers/dri/i965/brw_program.c
index 527f003977..4ba46a3c82 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -402,23 +402,33 @@ brw_alloc_stage_scratch(struct brw_context *brw,
if (devinfo->gen >= 9)
subslices = 4 * brw->screen->devinfo.num_slices;
- /* WaCSScratchSize:hsw
- *
- * Haswell's scratch space address calculation appears to be sparse
- * rather than tightly packed. The Thread ID has bits indicating
- * which subslice, EU within a subslice, and thread within an EU
- * it is. There's a maximum of two slices and two subslices, so these
- * can be stored with a single bit. Even though there are only 10 EUs
- * per subslice, this is stored in 4 bits, so there's an effective
- * maximum value of 16 EUs. Similarly, although there are only 7
- * threads per EU, this is stored in a 3 bit number, giving an effective
- * maximum value of 8 threads per EU.
- *
- * This means that we need to use 16 * 8 instead of 10 * 7 for the
- * number of threads per subslice.
- */
- const unsigned scratch_ids_per_subslice =
- devinfo->is_haswell ? 16 * 8 : devinfo->max_cs_threads;
+ unsigned scratch_ids_per_subslice;
+ if (devinfo->is_haswell) {
+ /* WaCSScratchSize:hsw
+ *
+ * Haswell's scratch space address calculation appears to be sparse
+ * rather than tightly packed. The Thread ID has bits indicating
+ * which subslice, EU within a subslice, and thread within an EU it
+ * is. There's a maximum of two slices and two subslices, so these
+ * can be stored with a single bit. Even though there are only 10 EUs
+ * per subslice, this is stored in 4 bits, so there's an effective
+ * maximum value of 16 EUs. Similarly, although there are only 7
+ * threads per EU, this is stored in a 3 bit number, giving an
+ * effective maximum value of 8 threads per EU.
+ *
+ * This means that we need to use 16 * 8 instead of 10 * 7 for the
+ * number of threads per subslice.
+ */
+ scratch_ids_per_subslice = 16 * 8;
+ } else if (devinfo->is_cherryview) {
+ /* Cherryview devices have either 6 or 8 EUs per subslice, and each
+ * EU has 7 threads. The 6 EU devices appear to calculate thread IDs
+ * as if it had 8 EUs.
+ */
+ scratch_ids_per_subslice = 8 * 7;
+ } else {
+ scratch_ids_per_subslice = devinfo->max_cs_threads;
+ }
thread_count = scratch_ids_per_subslice * subslices;
break;
___
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Mesa (master): intel/isl: Add isl_format_is_valid
Module: Mesa
Branch: master
Commit: bd3392423ddc82f1e8fe63c10b673b1bb70decf3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd3392423ddc82f1e8fe63c10b673b1bb70decf3
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Mon Feb 26 17:57:19 2018 -0800
intel/isl: Add isl_format_is_valid
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
---
src/intel/isl/gen_format_layout.py | 8
src/intel/isl/isl.h| 2 ++
2 files changed, 10 insertions(+)
diff --git a/src/intel/isl/gen_format_layout.py
b/src/intel/isl/gen_format_layout.py
index 0ca42dbab8..53cdd3b811 100644
--- a/src/intel/isl/gen_format_layout.py
+++ b/src/intel/isl/gen_format_layout.py
@@ -89,6 +89,14 @@ isl_format_layouts[] = {
% endfor
};
+bool
+isl_format_is_valid(enum isl_format format)
+{
+if (format >= sizeof(isl_format_layouts) / sizeof(isl_format_layouts[0]))
+return false;
+return isl_format_layouts[format].name;
+}
+
enum isl_format
isl_format_srgb_to_linear(enum isl_format format)
{
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 863b6e4bef..0da6abb71d 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1410,6 +1410,8 @@ isl_format_get_layout(enum isl_format fmt)
return _format_layouts[fmt];
}
+bool isl_format_is_valid(enum isl_format);
+
static inline const char * ATTRIBUTE_CONST
isl_format_get_name(enum isl_format fmt)
{
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Mesa (master): intel: Split gen_device_info out into libintel_dev
Module: Mesa
Branch: master
Commit: 272bef0601a1bdb5292771aefc8d62fcbdf4c47f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=272bef0601a1bdb5292771aefc8d62fcbdf4c47f
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Mon Feb 26 15:39:59 2018 -0800
intel: Split gen_device_info out into libintel_dev
Split out the device info so isl doesn't depend on intel/common. Now
it will depend on the new intel/dev device info lib.
This will allow the decoder in intel/common to use isl, allowing us to
apply Ken's patch that removes the genxml duplication of surface
formats.
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
---
src/intel/Android.dev.mk | 35 ++
src/intel/Makefile.am | 1 +
src/intel/Makefile.dev.am | 31 +++
src/intel/Makefile.isl.am | 2 +-
src/intel/Makefile.sources | 6 ++--
src/intel/Makefile.tools.am| 4 +++
src/intel/Makefile.vulkan.am | 1 +
src/intel/blorp/blorp_genX_exec.h | 2 +-
src/intel/common/gen_decoder.h | 2 +-
src/intel/common/gen_l3_config.h | 2 +-
src/intel/common/meson.build | 2 --
src/intel/compiler/brw_compiler.h | 2 +-
src/intel/compiler/brw_inst.h | 2 +-
src/intel/compiler/brw_reg_type.c | 2 +-
src/intel/{common => dev}/gen_device_info.c| 0
src/intel/{common => dev}/gen_device_info.h| 0
src/intel/dev/meson.build | 33
src/intel/genxml/gen_bits_header.py| 2 +-
src/intel/isl/isl_drm.c| 2 +-
src/intel/isl/isl_format.c | 2 +-
src/intel/isl/isl_priv.h | 2 +-
src/intel/isl/meson.build | 2 +-
.../isl/tests/isl_surf_get_image_offset_test.c | 2 +-
src/intel/meson.build | 1 +
src/intel/tools/gen_disasm.h | 2 +-
src/intel/tools/meson.build| 4 +--
src/intel/vulkan/anv_private.h | 2 +-
src/intel/vulkan/meson.build | 8 ++---
src/mesa/drivers/dri/i965/Makefile.am | 1 +
src/mesa/drivers/dri/i965/brw_bufmgr.c | 2 +-
src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +-
src/mesa/drivers/dri/i965/intel_screen.h | 2 +-
src/mesa/drivers/dri/i965/meson.build | 3 +-
33 files changed, 137 insertions(+), 29 deletions(-)
diff --git a/src/intel/Android.dev.mk b/src/intel/Android.dev.mk
new file mode 100644
index 00..956f32c119
--- /dev/null
+++ b/src/intel/Android.dev.mk
@@ -0,0 +1,35 @@
+# Copyright © 2016 Intel Corporation
+# Copyright © 2016 Mauro Rossi <issor.or...@gmail.com>
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included
+# in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+# ---
+# Build libmesa_intel_dev
+# ---
+
+include $(CLEAR_VARS)
+
+LOCAL_MODULE := libmesa_intel_dev
+
+LOCAL_MODULE_CLASS := STATIC_LIBRARIES
+
+LOCAL_SRC_FILES := $(DEV_FILES)
+
+include $(MESA_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
diff --git a/src/intel/Makefile.am b/src/intel/Makefile.am
index cde4a70fbc..bfb7f5b9f0 100644
--- a/src/intel/Makefile.am
+++ b/src/intel/Makefile.am
@@ -75,6 +75,7 @@ EXTRA_DIST = \
include Makefile.blorp.am
include Makefile.common.am
include Makefile.compiler.am
+include Makefile.dev.am
include Makefile.genxml.am
include Makefile.isl.am
include Makefile.tools.am
diff --git a/src/intel/Makefile.dev.am b/src/intel/Makefile.dev.am
new file mode 100644
index 00
Mesa (master): intel/common: Use isl for decoder surface formats
Module: Mesa
Branch: master
Commit: 755e7e6c20b8778bd5becb516c437f44c7b37984
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=755e7e6c20b8778bd5becb516c437f44c7b37984
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Mon Feb 26 20:31:22 2018 -0800
intel/common: Use isl for decoder surface formats
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
---
src/intel/common/gen_decoder.c | 8
src/intel/common/meson.build | 1 +
src/intel/meson.build | 2 +-
3 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 87a81b4b05..7ca71c0d9f 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -35,6 +35,7 @@
#include "gen_decoder.h"
+#include "isl/isl.h"
#include "genxml/genX_xml.h"
#define XML_BUFFER_SIZE 4096
@@ -954,6 +955,13 @@ iter_decode_field(struct gen_field_iterator *iter)
int length = strlen(iter->value);
snprintf(iter->value + length, sizeof(iter->value) - length,
" (%s)", enum_name);
+ } else if (strcmp(iter->name, "Surface Format") == 0) {
+ if (isl_format_is_valid((enum isl_format)v.qw)) {
+ const char *fmt_name = isl_format_get_name((enum isl_format)v.qw);
+ int length = strlen(iter->value);
+ snprintf(iter->value + length, sizeof(iter->value) - length,
+ " (%s)", fmt_name);
+ }
}
}
diff --git a/src/intel/common/meson.build b/src/intel/common/meson.build
index d35d5e8f78..5e0394a5b8 100644
--- a/src/intel/common/meson.build
+++ b/src/intel/common/meson.build
@@ -38,5 +38,6 @@ libintel_common = static_library(
files_libintel_common,
include_directories : [inc_common, inc_intel],
c_args : [c_vis_args, no_override_init_args],
+ link_with : [libisl],
dependencies : [dep_expat, dep_libdrm, dep_thread],
)
diff --git a/src/intel/meson.build b/src/intel/meson.build
index 28a2d79350..ccaf16a76f 100644
--- a/src/intel/meson.build
+++ b/src/intel/meson.build
@@ -23,8 +23,8 @@ inc_intel = include_directories('.')
subdir('blorp')
subdir('dev')
subdir('genxml')
-subdir('common')
subdir('isl')
+subdir('common')
subdir('compiler')
subdir('tools')
if with_intel_vk
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Mesa (master): intel: Drop SURFACE_FORMAT enum from genxml.
Module: Mesa Branch: master Commit: 0472aa3efe325ba53dc25a20a541f18d30d31b0c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0472aa3efe325ba53dc25a20a541f18d30d31b0c Author: Kenneth Graunke <kenn...@whitecape.org> Date: Tue Feb 13 18:13:51 2018 -0800 intel: Drop SURFACE_FORMAT enum from genxml. We want people to be using ISL_FORMAT_*, rather than the genxml format enumerations. This patch drops 10 separate copies, and drops a bunch of ugly casting. Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com> [jordan.l.jus...@intel.com: Minor changes for rebase] Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/blorp/blorp_genX_exec.h | 14 +- src/intel/genxml/gen10.xml| 229 +- src/intel/genxml/gen11.xml| 229 +- src/intel/genxml/gen4.xml | 222 + src/intel/genxml/gen45.xml| 222 + src/intel/genxml/gen5.xml | 226 + src/intel/genxml/gen6.xml | 228 + src/intel/genxml/gen7.xml | 228 + src/intel/genxml/gen75.xml| 228 + src/intel/genxml/gen8.xml | 228 + src/intel/genxml/gen9.xml | 228 + src/intel/isl/isl_surface_state.c | 6 +- src/intel/vulkan/genX_gpu_memcpy.c| 2 +- src/intel/vulkan/genX_pipeline.c | 6 +- src/mesa/drivers/dri/i965/genX_state_upload.c | 8 +- 15 files changed, 35 insertions(+), 2269 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=0472aa3efe325ba53dc25a20a541f18d30d31b0c ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Use gen_get_pci_device_id_override
Module: Mesa
Branch: master
Commit: 843f6d187a2896386a6fb8c17daed378aefbdb91
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=843f6d187a2896386a6fb8c17daed378aefbdb91
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Fri Feb 9 18:48:18 2018 -0800
i965: Use gen_get_pci_device_id_override
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/mesa/drivers/dri/i965/intel_screen.c | 57 +++-
1 file changed, 5 insertions(+), 52 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index 1f9b0efa42..9e0c15bad2 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -2359,57 +2359,6 @@ shader_perf_log_mesa(void *data, const char *fmt, ...)
va_end(args);
}
-static int
-parse_devid_override(const char *devid_override)
-{
- static const struct {
- const char *name;
- int pci_id;
- } name_map[] = {
- { "brw", 0x2a02 },
- { "g4x", 0x2a42 },
- { "ilk", 0x0042 },
- { "snb", 0x0126 },
- { "ivb", 0x016a },
- { "hsw", 0x0d2e },
- { "byt", 0x0f33 },
- { "bdw", 0x162e },
- { "chv", 0x22B3 },
- { "skl", 0x1912 },
- { "bxt", 0x5A85 },
- { "kbl", 0x5912 },
- { "glk", 0x3185 },
- { "cnl", 0x5a52 },
- };
-
- for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
- if (!strcmp(name_map[i].name, devid_override))
- return name_map[i].pci_id;
- }
-
- return strtol(devid_override, NULL, 0);
-}
-
-/**
- * Get the PCI ID for the device. This can be overridden by setting the
- * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
- *
- * Returns -1 on ioctl failure.
- */
-static int
-get_pci_device_id(struct intel_screen *screen)
-{
- if (geteuid() == getuid()) {
- char *devid_override = getenv("INTEL_DEVID_OVERRIDE");
- if (devid_override) {
- screen->no_hw = true;
- return parse_devid_override(devid_override);
- }
- }
-
- return intel_get_integer(screen, I915_PARAM_CHIPSET_ID);
-}
-
/**
* This is the driver specific part of the createNewScreen entry point.
* Called when using DRI2.
@@ -2447,7 +2396,11 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
screen->driScrnPriv = dri_screen;
dri_screen->driverPrivate = (void *) screen;
- screen->deviceID = get_pci_device_id(screen);
+ screen->deviceID = gen_get_pci_device_id_override();
+ if (screen->deviceID < 0)
+ screen->deviceID = intel_get_integer(screen, I915_PARAM_CHIPSET_ID);
+ else
+ screen->no_hw = true;
if (!gen_get_device_info(screen->deviceID, >devinfo))
return NULL;
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Mesa (master): intel/common: Add gen_device_name_to_pci_device_id
Module: Mesa
Branch: master
Commit: 8ff89250ffc24ef908f0c1b8b0b96820c49a492f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ff89250ffc24ef908f0c1b8b0b96820c49a492f
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Fri Feb 9 19:06:12 2018 -0800
intel/common: Add gen_device_name_to_pci_device_id
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_device_info.c | 19 +--
src/intel/common/gen_device_info.h | 1 +
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/src/intel/common/gen_device_info.c
b/src/intel/common/gen_device_info.c
index 113a9dca1f..ef0ae4ce8c 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -30,8 +30,13 @@
#include "compiler/shader_enums.h"
#include "util/macros.h"
-static int
-parse_devid_override(const char *devid_override)
+/**
+ * Get the PCI ID for the device name.
+ *
+ * Returns -1 if the device is not known.
+ */
+int
+gen_device_name_to_pci_device_id(const char *name)
{
static const struct {
const char *name;
@@ -54,11 +59,11 @@ parse_devid_override(const char *devid_override)
};
for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
- if (!strcmp(name_map[i].name, devid_override))
+ if (!strcmp(name_map[i].name, name))
return name_map[i].pci_id;
}
- return strtol(devid_override, NULL, 0);
+ return -1;
}
/**
@@ -72,8 +77,10 @@ gen_get_pci_device_id_override(void)
{
if (geteuid() == getuid()) {
const char *devid_override = getenv("INTEL_DEVID_OVERRIDE");
- if (devid_override)
- return parse_devid_override(devid_override);
+ if (devid_override) {
+ const int id = gen_device_name_to_pci_device_id(devid_override);
+ return id >= 0 ? id : strtol(devid_override, NULL, 0);
+ }
}
return -1;
diff --git a/src/intel/common/gen_device_info.h
b/src/intel/common/gen_device_info.h
index 6a96143ceb..3e9c087f58 100644
--- a/src/intel/common/gen_device_info.h
+++ b/src/intel/common/gen_device_info.h
@@ -200,6 +200,7 @@ struct gen_device_info
((devinfo)->is_broxton || (devinfo)->is_geminilake)
int gen_get_pci_device_id_override(void);
+int gen_device_name_to_pci_device_id(const char *name);
bool gen_get_device_info(int devid, struct gen_device_info *devinfo);
const char *gen_get_device_name(int devid);
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Mesa (master): intel/vulkan: Support INTEL_NO_HW environment variable
Module: Mesa
Branch: master
Commit: 6b274d5cc6186c06dbb8b594e54022e75f80ed8e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b274d5cc6186c06dbb8b594e54022e75f80ed8e
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Fri Feb 9 18:36:43 2018 -0800
intel/vulkan: Support INTEL_NO_HW environment variable
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/vulkan/anv_device.c | 3 +++
src/intel/vulkan/anv_private.h | 2 ++
src/intel/vulkan/anv_queue.c | 2 +-
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index a83b7a39f6..dd5f2f4928 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -294,6 +294,8 @@ anv_physical_device_init(struct anv_physical_device *device,
assert(strlen(path) < ARRAY_SIZE(device->path));
strncpy(device->path, path, ARRAY_SIZE(device->path));
+ device->no_hw = getenv("INTEL_NO_HW") != NULL;
+
device->chipset_id = anv_gem_get_param(fd, I915_PARAM_CHIPSET_ID);
if (!device->chipset_id) {
result = vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
@@ -1368,6 +1370,7 @@ VkResult anv_CreateDevice(
device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
device->instance = physical_device->instance;
device->chipset_id = physical_device->chipset_id;
+ device->no_hw = physical_device->no_hw;
device->lost = false;
if (pAllocator)
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 104b28ee5d..fb4fd19178 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -749,6 +749,7 @@ struct anv_physical_device {
struct anv_instance * instance;
uint32_tchipset_id;
+boolno_hw;
charpath[20];
const char *name;
struct gen_device_info info;
@@ -852,6 +853,7 @@ struct anv_device {
struct anv_instance * instance;
uint32_tchipset_id;
+boolno_hw;
struct gen_device_info info;
struct isl_device isl_dev;
int context_id;
diff --git a/src/intel/vulkan/anv_queue.c b/src/intel/vulkan/anv_queue.c
index c6b2e01c62..b0dcc882ed 100644
--- a/src/intel/vulkan/anv_queue.c
+++ b/src/intel/vulkan/anv_queue.c
@@ -39,7 +39,7 @@ anv_device_execbuf(struct anv_device *device,
struct drm_i915_gem_execbuffer2 *execbuf,
struct anv_bo **execbuf_bos)
{
- int ret = anv_gem_execbuffer(device, execbuf);
+ int ret = device->no_hw ? 0 : anv_gem_execbuffer(device, execbuf);
if (ret != 0) {
/* We don't know the real error. */
device->lost = true;
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Mesa (master): intel/common: Add gen_get_pci_device_id_override
Module: Mesa
Branch: master
Commit: e560bb9dc2025cceee19d05c45197d10388eb759
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e560bb9dc2025cceee19d05c45197d10388eb759
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Fri Feb 9 17:12:05 2018 -0800
intel/common: Add gen_get_pci_device_id_override
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/common/gen_device_info.c | 51 ++
src/intel/common/gen_device_info.h | 1 +
2 files changed, 52 insertions(+)
diff --git a/src/intel/common/gen_device_info.c
b/src/intel/common/gen_device_info.c
index a08a13a32a..113a9dca1f 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -24,10 +24,61 @@
#include
#include
#include
+#include
+#include
#include "gen_device_info.h"
#include "compiler/shader_enums.h"
#include "util/macros.h"
+static int
+parse_devid_override(const char *devid_override)
+{
+ static const struct {
+ const char *name;
+ int pci_id;
+ } name_map[] = {
+ { "brw", 0x2a02 },
+ { "g4x", 0x2a42 },
+ { "ilk", 0x0042 },
+ { "snb", 0x0126 },
+ { "ivb", 0x016a },
+ { "hsw", 0x0d2e },
+ { "byt", 0x0f33 },
+ { "bdw", 0x162e },
+ { "chv", 0x22B3 },
+ { "skl", 0x1912 },
+ { "bxt", 0x5A85 },
+ { "kbl", 0x5912 },
+ { "glk", 0x3185 },
+ { "cnl", 0x5a52 },
+ };
+
+ for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
+ if (!strcmp(name_map[i].name, devid_override))
+ return name_map[i].pci_id;
+ }
+
+ return strtol(devid_override, NULL, 0);
+}
+
+/**
+ * Get the overridden PCI ID for the device. This is set with the
+ * INTEL_DEVID_OVERRIDE environment variable.
+ *
+ * Returns -1 if the override is not set.
+ */
+int
+gen_get_pci_device_id_override(void)
+{
+ if (geteuid() == getuid()) {
+ const char *devid_override = getenv("INTEL_DEVID_OVERRIDE");
+ if (devid_override)
+ return parse_devid_override(devid_override);
+ }
+
+ return -1;
+}
+
static const struct gen_device_info gen_device_info_i965 = {
.gen = 4,
.has_negative_rhw_bug = true,
diff --git a/src/intel/common/gen_device_info.h
b/src/intel/common/gen_device_info.h
index fd9c17531d..6a96143ceb 100644
--- a/src/intel/common/gen_device_info.h
+++ b/src/intel/common/gen_device_info.h
@@ -199,6 +199,7 @@ struct gen_device_info
#define gen_device_info_is_9lp(devinfo) \
((devinfo)->is_broxton || (devinfo)->is_geminilake)
+int gen_get_pci_device_id_override(void);
bool gen_get_device_info(int devid, struct gen_device_info *devinfo);
const char *gen_get_device_name(int devid);
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Mesa (master): intel/vulkan: Support INTEL_DEVID_OVERRIDE environment variable
Module: Mesa
Branch: master
Commit: c2134f94c8a819cd100e503cf56cbe6fe11a6a2f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2134f94c8a819cd100e503cf56cbe6fe11a6a2f
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Fri Feb 9 18:38:28 2018 -0800
intel/vulkan: Support INTEL_DEVID_OVERRIDE environment variable
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/vulkan/anv_device.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index dd5f2f4928..8be88acc52 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -296,10 +296,16 @@ anv_physical_device_init(struct anv_physical_device
*device,
device->no_hw = getenv("INTEL_NO_HW") != NULL;
- device->chipset_id = anv_gem_get_param(fd, I915_PARAM_CHIPSET_ID);
- if (!device->chipset_id) {
- result = vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
- goto fail;
+ const int pci_id_override = gen_get_pci_device_id_override();
+ if (pci_id_override < 0) {
+ device->chipset_id = anv_gem_get_param(fd, I915_PARAM_CHIPSET_ID);
+ if (!device->chipset_id) {
+ result = vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
+ goto fail;
+ }
+ } else {
+ device->chipset_id = pci_id_override;
+ device->no_hw = true;
}
device->name = gen_get_device_name(device->chipset_id);
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Mesa (master): intel/tools: Use gen_device_name_to_pci_device_id in aubinator
Module: Mesa
Branch: master
Commit: 9f223d860b6fed0ae296bcd1b8ae14dca66a7986
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f223d860b6fed0ae296bcd1b8ae14dca66a7986
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Fri Feb 9 19:06:43 2018 -0800
intel/tools: Use gen_device_name_to_pci_device_id in aubinator
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/tools/aubinator.c | 30 ++
1 file changed, 6 insertions(+), 24 deletions(-)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index 92aa208a61..77bad29051 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -549,22 +549,6 @@ int main(int argc, char *argv[])
struct aub_file *file;
int c, i;
bool help = false, pager = true;
- const struct {
- const char *name;
- int pci_id;
- } gens[] = {
- { "ilk", 0x0046 }, /* Intel(R) Ironlake Mobile */
- { "snb", 0x0126 }, /* Intel(R) Sandybridge Mobile GT2 */
- { "ivb", 0x0166 }, /* Intel(R) Ivybridge Mobile GT2 */
- { "hsw", 0x0416 }, /* Intel(R) Haswell Mobile GT2 */
- { "byt", 0x0155 }, /* Intel(R) Bay Trail */
- { "bdw", 0x1616 }, /* Intel(R) HD Graphics 5500 (Broadwell GT2) */
- { "chv", 0x22B3 }, /* Intel(R) HD Graphics (Cherryview) */
- { "skl", 0x1912 }, /* Intel(R) HD Graphics 530 (Skylake GT2) */
- { "kbl", 0x591D }, /* Intel(R) Kabylake GT2 */
- { "bxt", 0x0A84 }, /* Intel(R) HD Graphics (Broxton) */
- { "cnl", 0x5A52 }, /* Intel(R) HD Graphics (Cannonlake) */
- };
const struct option aubinator_opts[] = {
{ "help", no_argument, (int *) , true },
{ "no-pager", no_argument, (int *) ,false
},
@@ -581,19 +565,17 @@ int main(int argc, char *argv[])
i = 0;
while ((c = getopt_long(argc, argv, "", aubinator_opts, )) != -1) {
switch (c) {
- case 'g':
- for (i = 0; i < ARRAY_SIZE(gens); i++) {
-if (!strcmp(optarg, gens[i].name)) {
- pci_id = gens[i].pci_id;
- break;
-}
- }
- if (i == ARRAY_SIZE(gens)) {
+ case 'g': {
+ const int id = gen_device_name_to_pci_device_id(optarg);
+ if (id < 0) {
fprintf(stderr, "can't parse gen: '%s', expected ivb, byt, hsw, "
"bdw, chv, skl, kbl or bxt\n", optarg);
exit(EXIT_FAILURE);
+ } else {
+pci_id = id;
}
break;
+ }
case 'c':
if (optarg == NULL || strcmp(optarg, "always") == 0)
option_color = COLOR_ALWAYS;
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Mesa (18.0): i965: Support 0 ARB_get_program_binary formats for compat profiles
Module: Mesa
Branch: 18.0
Commit: 719f2c934030f74ce0a4892233f494f168852698
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=719f2c934030f74ce0a4892233f494f168852698
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Wed Feb 14 23:42:50 2018 -0800
i965: Support 0 ARB_get_program_binary formats for compat profiles
The QT framework has a bug in their shader program cache, which is
built on GL_ARB_get_program_binary.
To give QT and distributions time to fix the bug and roll the fix out
to users, for the 18.0 release we will advertise support for 0 binary
formats for compatibility profiles.
This is only being done on the 18.0 release branch.
Ref: https://bugreports.qt.io/browse/QTBUG-66420
Ref: https://bugs.freedesktop.org/show_bug.cgi?id=105065
Cc: "18.0" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Tested-by: Scott D Phillips <scott.d.phill...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
docs/relnotes/17.4.0.html | 4 +++-
src/mesa/drivers/dri/i965/brw_context.c | 9 -
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/docs/relnotes/17.4.0.html b/docs/relnotes/17.4.0.html
index 412c0fc455..f3ab46ad87 100644
--- a/docs/relnotes/17.4.0.html
+++ b/docs/relnotes/17.4.0.html
@@ -53,7 +53,9 @@ Note: some of the new features are only available with
certain drivers.
GL_ARB_enhanced_layouts on r600/evergreen+
GL_ARB_bindless_texture on nvc0/kepler
OpenGL 4.3 on r600/evergreen with hw fp64 support
-Support 1 binary format for GL_ARB_get_program_binary on i965
+Support 1 binary format for GL_ARB_get_program_binary on i965.
+(For the 18.0 release, 0 formats continue to be supported in
+compatibility profiles.)
Bug fixes
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index e9358b7bc9..58527d7726 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -704,7 +704,14 @@ brw_initialize_context_constants(struct brw_context *brw)
ctx->Const.AllowMappedBuffersDuringExecution = true;
/* GL_ARB_get_program_binary */
- ctx->Const.NumProgramBinaryFormats = 1;
+ /* The QT framework has a bug in their shader program cache, which is built
+* on GL_ARB_get_program_binary. In an effort to allow them to fix the bug
+* we don't enable more than 1 binary format for compatibility profiles.
+* This is only being done on the 18.0 release branch.
+*/
+ if (ctx->API != API_OPENGL_COMPAT) {
+ ctx->Const.NumProgramBinaryFormats = 1;
+ }
}
static void
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Mesa (master): i965: Enable disk shader cache by default
Module: Mesa
Branch: master
Commit: 96fe36f7acc62130c40a8881c02ad6b8155b5533
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=96fe36f7acc62130c40a8881c02ad6b8155b5533
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Wed Nov 8 15:42:14 2017 -0800
i965: Enable disk shader cache by default
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>
Acked-by: Kenneth Graunke <kenn...@whitecape.org>
---
docs/relnotes/18.1.0.html | 1 +
src/mesa/drivers/dri/i965/brw_disk_cache.c | 3 ---
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/docs/relnotes/18.1.0.html b/docs/relnotes/18.1.0.html
index 93cf1f2b4f..0aca0aa1ab 100644
--- a/docs/relnotes/18.1.0.html
+++ b/docs/relnotes/18.1.0.html
@@ -47,6 +47,7 @@ Note: some of the new features are only available with
certain drivers.
GL_ARB_bindless_texture on nvc0/maxwell+
GL_EXT_semaphore on radeonsi
GL_EXT_semaphore_fd on radeonsi
+Disk shader cache support for i965 enabled by default
Bug fixes
diff --git a/src/mesa/drivers/dri/i965/brw_disk_cache.c
b/src/mesa/drivers/dri/i965/brw_disk_cache.c
index f989456bcd..41f742e858 100644
--- a/src/mesa/drivers/dri/i965/brw_disk_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_disk_cache.c
@@ -407,9 +407,6 @@ void
brw_disk_cache_init(struct intel_screen *screen)
{
#ifdef ENABLE_SHADER_CACHE
- if (env_var_as_boolean("MESA_GLSL_CACHE_DISABLE", true))
- return;
-
char renderer[10];
MAYBE_UNUSED int len = snprintf(renderer, sizeof(renderer), "i965_%04x",
screen->deviceID);
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Mesa (master): i965: Create new program cache bo when clearing the program cache
Module: Mesa
Branch: master
Commit: 83e60ce927142752c57163fcb8b30eca2370d014
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=83e60ce927142752c57163fcb8b30eca2370d014
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Fri Feb 2 13:03:10 2018 -0800
i965: Create new program cache bo when clearing the program cache
When the disk shader cache CI testing was enabled, we started noticing
occasional failures on deqp test runs. (Mainly SNB, rarely HSW)
Before this change, when we cleared the (in memory) program cache we
reused the same bo. Since the disk shader cache quickly restores
programs, it appears that this would lead to overwrites of the older
program binaries in the in memory program cache that apparently were
still executing in some cases. If these programs were still executing,
this could cause a GPU hang.
This issue is probably not disk shader cache specific, but may have
been hidden due to the compiler taking time to recompile programs
after the cache was cleared.
v2:
* Don't add `copy` param to brw_cache_new_bo (Ken)
* Call from brw_program_cache_check_size (Ken)
Cc: Kenneth Graunke <kenn...@whitecape.org>
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_program_cache.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_program_cache.c
b/src/mesa/drivers/dri/i965/brw_program_cache.c
index 9266273b5d..14c356db32 100644
--- a/src/mesa/drivers/dri/i965/brw_program_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_program_cache.c
@@ -460,6 +460,7 @@ brw_program_cache_check_size(struct brw_context *brw)
perf_debug("Exceeded state cache size limit. Clearing the set "
"of compiled programs, which will trigger recompiles\n");
brw_clear_cache(brw, >cache);
+ brw_cache_new_bo(>cache, brw->cache.bo->size);
}
}
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Mesa (master): docs: add 18.1.0-devel release notes template
Module: Mesa Branch: master Commit: 62b68d05e7e704332ff5f5c890354859774f17e2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=62b68d05e7e704332ff5f5c890354859774f17e2 Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Wed Jan 24 17:07:30 2018 -0800 docs: add 18.1.0-devel release notes template Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> --- docs/relnotes/18.1.0.html | 64 +++ 1 file changed, 64 insertions(+) diff --git a/docs/relnotes/18.1.0.html b/docs/relnotes/18.1.0.html new file mode 100644 index 00..ddacbb4656 --- /dev/null +++ b/docs/relnotes/18.1.0.html @@ -0,0 +1,64 @@ +http://www.w3.org/TR/html4/loose.dtd;> + + + + Mesa Release Notes + + + + + + The Mesa 3D Graphics Library + + + + + +Mesa 18.1.0 Release Notes / TBD + + +Mesa 18.1.0 is a new development release. People who are concerned +with stability and reliability should stick with a previous release or +wait for Mesa 18.1.1. + + +Mesa 18.1.0 implements the OpenGL 4.5 API, but the version reported by +glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) / +glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used. +Some drivers don't support all the features required in OpenGL 4.5. OpenGL +4.5 is only available if requested at context creation +because compatibility contexts are not supported. + + + +SHA256 checksums + +TBD. + + + +New features + + +Note: some of the new features are only available with certain drivers. + + + +TBD + + +Bug fixes + + +TBD + + +Changes + + +TBD + + + + + ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa: bump version to 18.1.0-devel
Module: Mesa Branch: master Commit: 65c18b02fc5436f5fe0f6d37b6673daff36a9fe5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=65c18b02fc5436f5fe0f6d37b6673daff36a9fe5 Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Wed Jan 24 17:02:55 2018 -0800 mesa: bump version to 18.1.0-devel Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index 96db1413d9..1670340a51 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -17.4.0-devel +18.1.0-devel ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): aubinator: extract aubinator_init() out of the header handler function
Module: Mesa
Branch: master
Commit: 8cdf5bd29215c82d48ea9d869afeb9eb93b6e1f6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8cdf5bd29215c82d48ea9d869afeb9eb93b6e1f6
Author: Scott D Phillips <scott.d.phill...@intel.com>
Date: Tue Nov 28 15:52:09 2017 -0800
aubinator: extract aubinator_init() out of the header handler function
A later patch will use the aubinator_init() function from the
memtrace aub header handler.
Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>
---
src/intel/tools/aubinator.c | 39 +++
1 file changed, 23 insertions(+), 16 deletions(-)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index 46b0a47bcd..fcb46073f3 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -161,20 +161,8 @@ get_gen_batch_bo(void *user_data, uint64_t address)
}
static void
-handle_trace_header(uint32_t *p)
+aubinator_init(uint16_t aub_pci_id, const char *app_name)
{
- /* The intel_aubdump tool from IGT is kind enough to put a PCI-ID= tag in
-* the AUB header comment. If the user hasn't specified a hardware
-* generation, try to use the one from the AUB file.
-*/
- uint32_t *end = p + (p[0] & 0x) + 2;
- int aub_pci_id = 0;
- if (end > [12] && p[12] > 0)
- sscanf((char *)[13], "PCI-ID=%i", _pci_id);
-
- if (pci_id == 0)
- pci_id = aub_pci_id;
-
if (!gen_get_device_info(pci_id, )) {
fprintf(stderr, "can't find device information: pci_id=0x%x\n", pci_id);
exit(EXIT_FAILURE);
@@ -205,9 +193,6 @@ handle_trace_header(uint32_t *p)
if (aub_pci_id)
fprintf(outfile, "PCI ID: 0x%x\n", aub_pci_id);
- char app_name[33];
- strncpy(app_name, (char *)[2], 32);
- app_name[32] = 0;
fprintf(outfile, "Application name: %s\n", app_name);
fprintf(outfile, "Decoding as: %s\n", gen_get_device_name(pci_id));
@@ -216,6 +201,28 @@ handle_trace_header(uint32_t *p)
fprintf(outfile, "\n");
}
+static void
+handle_trace_header(uint32_t *p)
+{
+ /* The intel_aubdump tool from IGT is kind enough to put a PCI-ID= tag in
+* the AUB header comment. If the user hasn't specified a hardware
+* generation, try to use the one from the AUB file.
+*/
+ uint32_t *end = p + (p[0] & 0x) + 2;
+ int aub_pci_id = 0;
+ if (end > [12] && p[12] > 0)
+ sscanf((char *)[13], "PCI-ID=%i", _pci_id);
+
+ if (pci_id == 0)
+ pci_id = aub_pci_id;
+
+ char app_name[33];
+ strncpy(app_name, (char *)[2], 32);
+ app_name[32] = 0;
+
+ aubinator_init(aub_pci_id, app_name);
+}
+
struct aub_file {
FILE *stream;
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Mesa (master): aubinator: add support for aubinating memtrace aubs
Module: Mesa
Branch: master
Commit: 42f421cbbfcdadd29543246191697a12f0461e40
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=42f421cbbfcdadd29543246191697a12f0461e40
Author: Scott D Phillips <scott.d.phill...@intel.com>
Date: Tue Nov 28 15:52:10 2017 -0800
aubinator: add support for aubinating memtrace aubs
Memtrace aubs are similar to classic aubs, with the major
difference being how command submission is serialized (as register
writes instead of a high-level submit message). Some internal
tools generate or consume only memtrace aubs.
Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>
---
src/intel/tools/aubinator.c | 118 +++-
1 file changed, 83 insertions(+), 35 deletions(-)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index fcb46073f3..92aa208a61 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -223,6 +223,81 @@ handle_trace_header(uint32_t *p)
aubinator_init(aub_pci_id, app_name);
}
+static void
+handle_memtrace_version(uint32_t *p)
+{
+ int header_length = p[0] & 0x;
+ char app_name[64];
+ int app_name_len = MIN2(4 * (header_length + 1 - 5), ARRAY_SIZE(app_name) -
1);
+ int pci_id_len = 0;
+ int aub_pci_id = 0;
+
+ strncpy(app_name, (char *)[5], app_name_len);
+ app_name[app_name_len] = 0;
+ sscanf(app_name, "PCI-ID=%i %n", _pci_id, _id_len);
+ if (pci_id == 0)
+ pci_id = aub_pci_id;
+ aubinator_init(aub_pci_id, app_name + pci_id_len);
+}
+
+static void
+handle_memtrace_reg_write(uint32_t *p)
+{
+ uint32_t offset = p[1];
+ uint32_t value = p[5];
+ int engine;
+ static int render_elsp_writes = 0;
+ static int blitter_elsp_writes = 0;
+
+ if (offset == 0x2230) {
+ render_elsp_writes++;
+ engine = GEN_ENGINE_RENDER;
+ } else if (offset == 0x22230) {
+ blitter_elsp_writes++;
+ engine = GEN_ENGINE_BLITTER;
+ } else {
+ return;
+ }
+
+ if (render_elsp_writes > 3)
+ render_elsp_writes = 0;
+ else if (blitter_elsp_writes > 3)
+ blitter_elsp_writes = 0;
+ else
+ return;
+
+ uint8_t *pphwsp = (uint8_t*)gtt + (value & 0xf000);
+ const uint32_t pphwsp_size = 4096;
+ uint32_t *context = (uint32_t*)(pphwsp + pphwsp_size);
+ uint32_t ring_buffer_head = context[5];
+ uint32_t ring_buffer_tail = context[7];
+ uint32_t ring_buffer_start = context[9];
+ uint32_t *commands = (uint32_t*)((uint8_t*)gtt + ring_buffer_start +
ring_buffer_head);
+ (void)engine; /* TODO */
+ gen_print_batch(_ctx, commands, ring_buffer_tail - ring_buffer_head,
0);
+}
+
+static void
+handle_memtrace_mem_write(uint32_t *p)
+{
+ uint64_t address = *(uint64_t*)[1];
+ uint32_t address_space = p[3] >> 28;
+ uint32_t size = p[4];
+ uint32_t *data = p + 5;
+
+ if (address_space != 1)
+ return;
+
+ if (gtt_size < address + size) {
+ fprintf(stderr, "overflow gtt space: %s\n", strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
+ memcpy((char *) gtt + address, data, size);
+ if (gtt_end < address + size)
+ gtt_end = address + size;
+}
+
struct aub_file {
FILE *stream;
@@ -292,35 +367,14 @@ aub_file_stdin(void)
/* Newer version AUB opcode */
#define OPCODE_NEW_AUB 0x2e
-#define SUBOPCODE_VERSION 0x00
+#define SUBOPCODE_REG_POLL 0x02
#define SUBOPCODE_REG_WRITE 0x03
#define SUBOPCODE_MEM_POLL 0x05
#define SUBOPCODE_MEM_WRITE 0x06
+#define SUBOPCODE_VERSION 0x0e
#define MAKE_GEN(major, minor) ( ((major) << 8) | (minor) )
-struct {
- const char *name;
- uint32_t gen;
-} device_map[] = {
- { "bwr", MAKE_GEN(4, 0) },
- { "cln", MAKE_GEN(4, 0) },
- { "blc", MAKE_GEN(4, 0) },
- { "ctg", MAKE_GEN(4, 0) },
- { "el", MAKE_GEN(4, 0) },
- { "il", MAKE_GEN(4, 0) },
- { "sbr", MAKE_GEN(6, 0) },
- { "ivb", MAKE_GEN(7, 0) },
- { "lrb2", MAKE_GEN(0, 0) },
- { "hsw", MAKE_GEN(7, 5) },
- { "vlv", MAKE_GEN(7, 0) },
- { "bdw", MAKE_GEN(8, 0) },
- { "skl", MAKE_GEN(9, 0) },
- { "chv", MAKE_GEN(8, 0) },
- { "bxt", MAKE_GEN(9, 0) },
- { "cnl", MAKE_GEN(10, 0) },
-};
-
enum {
AUB_ITEM_DECODE_OK,
AUB_ITEM_DECODE_FAILED,
@@ -330,7 +384,7 @@ enum {
static int
aub_file_decode_batch(struct aub_file *file)
{
- uint32_t *p, h, device, data_type, *new_cursor;
+ uint32_t *p, h, *new_cursor;
int header_length, bias;
if (file->end - file->cursor < 1)
@@ -374,25 +428,19 @@ aub_file_decode_batch(struct aub_file *file)
case MAKE_HEADER(TYPE_AUB, OPCODE_AUB, SUBOPCODE_BMP):
break;
case MAKE_HEADER(TYPE_AUB, OPCODE_NEW_AUB, SUBOPCODE_VERSION):
- fprintf(outfile, "version block: dw1 %08x\n", p[1]);
- device = (p[1] >> 8) & 0xff;
- fprintf(outfile, "
Mesa (master): .gitignore: Ignore new generated files
Module: Mesa
Branch: master
Commit: 161a97c3d5e9195dce064d35446caec5ab59943d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=161a97c3d5e9195dce064d35446caec5ab59943d
Author: Scott D Phillips <scott.d.phill...@intel.com>
Date: Fri Jan 5 10:52:27 2018 -0800
.gitignore: Ignore new generated files
New generated files from:
bb1e6ff161c ("spirv: Add a prepass to set types on vtn_values")
65fc16c9741 ("autotools: set XA versions in configure.ac and configure header
file")
Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>
---
src/compiler/spirv/.gitignore| 1 +
src/gallium/state_trackers/xa/.gitignore | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/compiler/spirv/.gitignore b/src/compiler/spirv/.gitignore
index f723c31b04..fd06285b40 100644
--- a/src/compiler/spirv/.gitignore
+++ b/src/compiler/spirv/.gitignore
@@ -1 +1,2 @@
/spirv_info.c
+/vtn_gather_types.c
diff --git a/src/gallium/state_trackers/xa/.gitignore
b/src/gallium/state_trackers/xa/.gitignore
new file mode 100644
index 00..6a5bb3e1e3
--- /dev/null
+++ b/src/gallium/state_trackers/xa/.gitignore
@@ -0,0 +1 @@
+/xa_tracker.h
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Mesa (master): aubinator: honor --color option when printing the header
Module: Mesa Branch: master Commit: 4f0a2ff4c12c7a7a45c7a360a67f82a859a9634e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f0a2ff4c12c7a7a45c7a360a67f82a859a9634e Author: Scott D Phillips <scott.d.phill...@intel.com> Date: Tue Nov 28 15:52:08 2017 -0800 aubinator: honor --color option when printing the header Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com> --- src/intel/tools/aubinator.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c index ed7446cf1e..46b0a47bcd 100644 --- a/src/intel/tools/aubinator.c +++ b/src/intel/tools/aubinator.c @@ -192,8 +192,12 @@ handle_trace_header(uint32_t *p) gen_batch_decode_ctx_init(_ctx, , outfile, batch_flags, xml_path, get_gen_batch_bo, NULL); + char *color = GREEN_HEADER, *reset_color = NORMAL; + if (option_color == COLOR_NEVER) + color = reset_color = ""; + fprintf(outfile, "%sAubinator: Intel AUB file decoder.%-80s%s\n", - GREEN_HEADER, "", NORMAL); + color, "", reset_color); if (input_file) fprintf(outfile, "File name:%s\n", input_file); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): program: Don' t reset SamplersValidated when restoring from shader cache
Module: Mesa
Branch: master
Commit: dc07bb5fd188a4352ec90edb6c6107ae1ce11b50
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc07bb5fd188a4352ec90edb6c6107ae1ce11b50
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Tue Dec 12 11:44:01 2017 -0800
program: Don't reset SamplersValidated when restoring from shader cache
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103988
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
---
src/mesa/program/ir_to_mesa.cpp | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
index 5f663b3d09..29198509a6 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/program/ir_to_mesa.cpp
@@ -3115,15 +3115,17 @@ _mesa_glsl_link_shader(struct gl_context *ctx, struct
gl_shader_program *prog)
link_shaders(ctx, prog);
}
- if (prog->data->LinkStatus) {
- /* Reset sampler validated to true, validation happens via the
- * LinkShader call below.
- */
+ /* If LinkStatus is linking_success, then reset sampler validated to true.
+* Validation happens via the LinkShader call below. If LinkStatus is
+* linking_skipped, then SamplersValidated will have been restored from the
+* shader cache.
+*/
+ if (prog->data->LinkStatus == linking_success) {
prog->SamplersValidated = GL_TRUE;
+ }
- if (!ctx->Driver.LinkShader(ctx, prog)) {
- prog->data->LinkStatus = linking_failure;
- }
+ if (prog->data->LinkStatus && !ctx->Driver.LinkShader(ctx, prog)) {
+ prog->data->LinkStatus = linking_failure;
}
/* Return early if we are loading the shader from on-disk cache */
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Mesa (master): i965: Serialize nir later in the linking process
Module: Mesa
Branch: master
Commit: fc033742d2128ccfda6bf4c92254f632b9445b0c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc033742d2128ccfda6bf4c92254f632b9445b0c
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Thu Nov 30 17:48:57 2017 -0800
i965: Serialize nir later in the linking process
Fixes MESA_GLSL=cache_fb with piglit
tests/spec/glsl-1.50/execution/geometry/clip-distance-vs-gs-out.shader_test
Fixes: 0610a624a12 i965/link: Serialize program to nir after linking for shader
cache
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103988
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_link.cpp | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp
b/src/mesa/drivers/dri/i965/brw_link.cpp
index d18521e792..6177c8f5eb 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -302,15 +302,6 @@ brw_link_shader(struct gl_context *ctx, struct
gl_shader_program *shProg)
NIR_PASS_V(prog->nir, nir_lower_atomics_to_ssbo,
prog->nir->info.num_abos);
- if (brw->ctx.Cache) {
- struct blob writer;
- blob_init();
- nir_serialize(, prog->nir);
- prog->driver_cache_blob = ralloc_size(NULL, writer.size);
- memcpy(prog->driver_cache_blob, writer.data, writer.size);
- prog->driver_cache_blob_size = writer.size;
- }
-
infos[stage] = >nir->info;
update_xfb_info(prog->sh.LinkedTransformFeedback, infos[stage]);
@@ -357,6 +348,22 @@ brw_link_shader(struct gl_context *ctx, struct
gl_shader_program *shProg)
}
}
+ if (brw->ctx.Cache) {
+ for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
+ struct gl_linked_shader *shader = shProg->_LinkedShaders[stage];
+ if (!shader)
+continue;
+
+ struct gl_program *prog = shader->Program;
+ struct blob writer;
+ blob_init();
+ nir_serialize(, prog->nir);
+ prog->driver_cache_blob = ralloc_size(NULL, writer.size);
+ memcpy(prog->driver_cache_blob, writer.data, writer.size);
+ prog->driver_cache_blob_size = writer.size;
+ }
+ }
+
if (brw->precompile && !brw_shader_precompile(ctx, shProg))
return false;
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Mesa (master): i965: Support decoding INTERFACE_DESCRIPTOR_DATA with INTEL_DEBUG=bat
Module: Mesa
Branch: master
Commit: 386f6cd041c973de82ee76ba983a2ea36868a5bc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=386f6cd041c973de82ee76ba983a2ea36868a5bc
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Tue Nov 14 16:27:34 2017 -0800
i965: Support decoding INTERFACE_DESCRIPTOR_DATA with INTEL_DEBUG=bat
This will dump the INTERFACE_DESCRIPTOR_DATA along with the associated
samplers & surfaces.
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 24
1 file changed, 24 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 3412b1d0a5..216073129b 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -564,6 +564,30 @@ do_batch_dump(struct brw_context *brw)
decode_struct(brw, spec, "DEPTH_STENCIL_STATE", state,
state_gtt_offset, p[1] & ~0x3fu, color);
break;
+ case MEDIA_INTERFACE_DESCRIPTOR_LOAD: {
+ struct gen_group *group =
+gen_spec_find_struct(spec, "RENDER_SURFACE_STATE");
+ if (!group)
+break;
+
+ uint32_t idd_offset = p[3] & ~0x1fu;
+ decode_struct(brw, spec, "INTERFACE_DESCRIPTOR_DATA", state,
+ state_gtt_offset, idd_offset, color);
+
+ uint32_t ss_offset = state[idd_offset / 4 + 3] & ~0x1fu;
+ decode_structs(brw, spec, "SAMPLER_STATE", state,
+state_gtt_offset, ss_offset, 4 * 4, color);
+
+ uint32_t bt_offset = state[idd_offset / 4 + 4] & ~0x1fu;
+ int bt_entries = brw_state_batch_size(brw, bt_offset) / 4;
+ uint32_t *bt_pointers = [bt_offset / 4];
+ for (int i = 0; i < bt_entries; i++) {
+fprintf(stderr, "SURFACE_STATE - BTI = %d\n", i);
+gen_print_group(stderr, group, state_gtt_offset + bt_pointers[i],
+[bt_pointers[i] / 4], color);
+ }
+ break;
+ }
}
}
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Mesa (master): 26 new commits
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a61a8b9a7c7cdbb42b74a76c2ec825f7107cc83 Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Sat Feb 25 02:30:06 2017 -0800 i965: Initialize disk shader cache if MESA_GLSL_CACHE_DISABLE is false (Apologies for the double negative.) For now, the shader cache is disabled by default on i965 to allow us to verify its stability. In other words, to enable the shader cache on i965, set MESA_GLSL_CACHE_DISABLE to false or 0. If the variable is unset, then the shader cache will be disabled. We use the build-id of i965_dri.so for the timestamp, and the pci device id for the device name. v2: * Simplify code by forcing link to include build id sha. (Matt) v3: * Don't use a for loop with snprintf for bin to hex. (Matt) * Assume fixed length render and timestamp string to further simplify code. Cc: Matt Turner <matts...@gmail.com> Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ccb700526f647e0d02cb1c500b6aee083ba1b9d7 Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Wed Oct 18 15:04:37 2017 -0700 dri drivers: Always add the sha1 build-id v4: * Add Android build changes. (Emil) Cc: Dylan Baker <dylanx.c.ba...@intel.com> Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> Reviewed-by: Dylan Baker <dylanx.c.ba...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5b141634cff3aa1f68699f39a2c3794261a32b1 Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Fri Oct 13 22:04:52 2017 -0700 disk_cache: Fix issue reading GLSL metadata This would cause the read of the metadata content to fail, which would prevent the linking from being skipped. Seen on Rocket League with i965 shader cache. Fixes: b86ecea3446e "util/disk_cache: write cache item metadata to disk" Cc: Timothy Arceri <tarc...@itsqueeze.com> Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6ecd7d73fdbbca45ed398185eee2823e381d472 Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Tue Mar 28 11:48:55 2017 -0700 glsl/shader_cache: Save fs (BlendSupport) metadata Fixes many GL 4.5 CTS blend tests, such as: * GL45-CTS.blend_equation_advanced.extension_directive_enable * GL45-CTS.blend_equation_advanced.extension_directive_warn * GL45-CTS.blend_equation_advanced.blend_all.GL_MULTIPLY_KHR_all_qualifier * GL45-CTS.blend_equation_advanced.blend_specific.GL_COLORBURN_KHR v2: * Directly save the BlendSupport field to avoid potentially including a pointer in the future in the structure is updated. (tarceri) Cc: Timothy Arceri <tarc...@itsqueeze.com> Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f5204a0dbfc2c3ab240842f06d3afb2e7b9ed2c Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Sat Feb 25 17:36:28 2017 -0800 i965: Initialize sha1 hash of dri config options Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=478a73fdfaf1fed57bc7f05e672f6728e27ab110 Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Sat Feb 25 02:37:57 2017 -0800 i965: Don't link when the program was found in the disk cache Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Cc: Timothy Arceri <tarc...@itsqueeze.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c3a8ae105ca4c6abdd967bd569b9605967cfcf25 Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Wed Oct 18 19:25:48 2017 -0700 i965: add cache fallback support using serialized nir If the i965 gen program cannot be loaded from the cache, then we fallback to using a serialized nir program. This is based on "i965: ad
Mesa (master): glsl: Add field initializers for glsl_struct_field default constructor
Module: Mesa
Branch: master
Commit: abbcdc9b69901528c9ea4469a4dc2977c71ff9f9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=abbcdc9b69901528c9ea4469a4dc2977c71ff9f9
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Fri Oct 20 18:54:17 2017 -0700
glsl: Add field initializers for glsl_struct_field default constructor
This helps valgrind when encode_type_to_blob is used.
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/compiler/glsl_types.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/compiler/glsl_types.h b/src/compiler/glsl_types.h
index b5e97e638b..0b4a66ca4d 100644
--- a/src/compiler/glsl_types.h
+++ b/src/compiler/glsl_types.h
@@ -1045,6 +1045,13 @@ struct glsl_struct_field {
}
glsl_struct_field()
+ : type(NULL), name(NULL), location(0), offset(0), xfb_buffer(0),
+xfb_stride(0), interpolation(0), centroid(0),
+sample(0), matrix_layout(0), patch(0),
+precision(0), memory_read_only(0),
+memory_write_only(0), memory_coherent(0), memory_volatile(0),
+memory_restrict(0), image_format(0), explicit_xfb_buffer(0),
+implicit_sized_array(0)
{
/* empty */
}
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Mesa (master): glsl_to_nir: Zero nir_variable struct for valgrind & nir_serialize
Module: Mesa Branch: master Commit: 16867154d8c7bb6b2b46f00203ed94a4a810abde URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=16867154d8c7bb6b2b46f00203ed94a4a810abde Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Mon Oct 2 00:17:22 2017 -0700 glsl_to_nir: Zero nir_variable struct for valgrind & nir_serialize Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/compiler/glsl/glsl_to_nir.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp index 63694fd41f..1d1085ffbc 100644 --- a/src/compiler/glsl/glsl_to_nir.cpp +++ b/src/compiler/glsl/glsl_to_nir.cpp @@ -311,7 +311,7 @@ nir_visitor::visit(ir_variable *ir) if (ir->data.mode == ir_var_shader_shared) return; - nir_variable *var = ralloc(shader, nir_variable); + nir_variable *var = rzalloc(shader, nir_variable); var->type = ir->type; var->name = ralloc_strdup(var, ir->name); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nir: Zero nir_load_const_instr:: value for valgrind & nir_serialize
Module: Mesa
Branch: master
Commit: 78550869a1e0892e7950eafcde805e8b9e749801
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=78550869a1e0892e7950eafcde805e8b9e749801
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Mon Oct 2 00:14:51 2017 -0700
nir: Zero nir_load_const_instr::value for valgrind & nir_serialize
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/compiler/nir/nir.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index fe48451694..7380bf436a 100644
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -480,7 +480,7 @@ nir_load_const_instr *
nir_load_const_instr_create(nir_shader *shader, unsigned num_components,
unsigned bit_size)
{
- nir_load_const_instr *instr = ralloc(shader, nir_load_const_instr);
+ nir_load_const_instr *instr = rzalloc(shader, nir_load_const_instr);
instr_init(>instr, nir_instr_type_load_const);
nir_ssa_def_init(>instr, >def, num_components, bit_size,
NULL);
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Mesa (master): glsl: move shader_cache type handling to glsl_types
Module: Mesa
Branch: master
Commit: 7686f0b316883087c7668c9df3adebcaae684132
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7686f0b316883087c7668c9df3adebcaae684132
Author: Connor Abbott <cwabbo...@gmail.com>
Date: Tue Sep 12 20:16:22 2017 -0400
glsl: move shader_cache type handling to glsl_types
Not sure if this is the best place to put it, but we're going to need
this for NIR too.
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/compiler/glsl/shader_cache.cpp | 171 -
src/compiler/glsl_types.cpp| 171 +
src/compiler/glsl_types.h | 7 ++
3 files changed, 178 insertions(+), 171 deletions(-)
diff --git a/src/compiler/glsl/shader_cache.cpp
b/src/compiler/glsl/shader_cache.cpp
index f3c7a57699..ca90cfde35 100644
--- a/src/compiler/glsl/shader_cache.cpp
+++ b/src/compiler/glsl/shader_cache.cpp
@@ -75,177 +75,6 @@ compile_shaders(struct gl_context *ctx, struct
gl_shader_program *prog) {
}
static void
-get_struct_type_field_and_pointer_sizes(size_t *s_field_size,
-size_t *s_field_ptrs)
-{
- *s_field_size = sizeof(glsl_struct_field);
- *s_field_ptrs =
- sizeof(((glsl_struct_field *)0)->type) +
- sizeof(((glsl_struct_field *)0)->name);
-}
-
-static void
-encode_type_to_blob(struct blob *blob, const glsl_type *type)
-{
- uint32_t encoding;
-
- if (!type) {
- blob_write_uint32(blob, 0);
- return;
- }
-
- switch (type->base_type) {
- case GLSL_TYPE_UINT:
- case GLSL_TYPE_INT:
- case GLSL_TYPE_FLOAT:
- case GLSL_TYPE_BOOL:
- case GLSL_TYPE_DOUBLE:
- case GLSL_TYPE_UINT64:
- case GLSL_TYPE_INT64:
- encoding = (type->base_type << 24) |
- (type->vector_elements << 4) |
- (type->matrix_columns);
- break;
- case GLSL_TYPE_SAMPLER:
- encoding = (type->base_type) << 24 |
- (type->sampler_dimensionality << 4) |
- (type->sampler_shadow << 3) |
- (type->sampler_array << 2) |
- (type->sampled_type);
- break;
- case GLSL_TYPE_SUBROUTINE:
- encoding = type->base_type << 24;
- blob_write_uint32(blob, encoding);
- blob_write_string(blob, type->name);
- return;
- case GLSL_TYPE_IMAGE:
- encoding = (type->base_type) << 24 |
- (type->sampler_dimensionality << 3) |
- (type->sampler_array << 2) |
- (type->sampled_type);
- break;
- case GLSL_TYPE_ATOMIC_UINT:
- encoding = (type->base_type << 24);
- break;
- case GLSL_TYPE_ARRAY:
- blob_write_uint32(blob, (type->base_type) << 24);
- blob_write_uint32(blob, type->length);
- encode_type_to_blob(blob, type->fields.array);
- return;
- case GLSL_TYPE_STRUCT:
- case GLSL_TYPE_INTERFACE:
- blob_write_uint32(blob, (type->base_type) << 24);
- blob_write_string(blob, type->name);
- blob_write_uint32(blob, type->length);
-
- size_t s_field_size, s_field_ptrs;
- get_struct_type_field_and_pointer_sizes(_field_size, _field_ptrs);
-
- for (unsigned i = 0; i < type->length; i++) {
- encode_type_to_blob(blob, type->fields.structure[i].type);
- blob_write_string(blob, type->fields.structure[i].name);
-
- /* Write the struct field skipping the pointers */
- blob_write_bytes(blob,
- ((char *)>fields.structure[i]) + s_field_ptrs,
- s_field_size - s_field_ptrs);
- }
-
- if (type->is_interface()) {
- blob_write_uint32(blob, type->interface_packing);
- blob_write_uint32(blob, type->interface_row_major);
- }
- return;
- case GLSL_TYPE_VOID:
- case GLSL_TYPE_ERROR:
- default:
- assert(!"Cannot encode type!");
- encoding = 0;
- break;
- }
-
- blob_write_uint32(blob, encoding);
-}
-
-static const glsl_type *
-decode_type_from_blob(struct blob_reader *blob)
-{
- uint32_t u = blob_read_uint32(blob);
-
- if (u == 0) {
- return NULL;
- }
-
- glsl_base_type base_type = (glsl_base_type) (u >> 24);
-
- switch (base_type) {
- case GLSL_TYPE_UINT:
- case GLSL_TYPE_INT:
- case GLSL_TYPE_FLOAT:
- case GLSL_TYPE_BOOL:
- case GLSL_TYPE_DOUBLE:
- case GLSL_TYPE_UINT64:
- case GLSL_TYPE_INT64:
- return glsl_type::get_instance(base_type, (u >> 4) & 0x0f, u & 0x0f);
- case GLSL_TYPE_SAMPLER:
- return glsl_type::get_sampler_instance((enum glsl_sampler_dim) ((u >> 4)
& 0x07),
- (u >> 3) & 0x01,
- (u >
Mesa (master): intel/nir: Zero local index const struct for valgrind & nir_serialize
Module: Mesa Branch: master Commit: b35e8c3b868a2c8ba086cc8667fee2736e157fad URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b35e8c3b868a2c8ba086cc8667fee2736e157fad Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Mon Oct 2 00:08:55 2017 -0700 intel/nir: Zero local index const struct for valgrind & nir_serialize Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/intel/compiler/brw_nir_lower_cs_intrinsics.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw_nir_lower_cs_intrinsics.c b/src/intel/compiler/brw_nir_lower_cs_intrinsics.c index f9322654e7..d27727624c 100644 --- a/src/intel/compiler/brw_nir_lower_cs_intrinsics.c +++ b/src/intel/compiler/brw_nir_lower_cs_intrinsics.c @@ -116,6 +116,7 @@ lower_cs_intrinsics_convert_block(struct lower_intrinsics_state *state, nir_ssa_def *local_index = nir_load_local_invocation_index(b); nir_const_value uvec3; + memset(, 0, sizeof(uvec3)); uvec3.u32[0] = 1; uvec3.u32[1] = size[0]; uvec3.u32[2] = size[0] * size[1]; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nir: Zero local_size const struct for valgrind & nir_serialize
Module: Mesa Branch: master Commit: d917f57c2f22ee9283795f29fc5977f8189cd3e8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d917f57c2f22ee9283795f29fc5977f8189cd3e8 Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Mon Oct 2 00:05:28 2017 -0700 nir: Zero local_size const struct for valgrind & nir_serialize Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/compiler/nir/nir_lower_system_values.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/nir/nir_lower_system_values.c b/src/compiler/nir/nir_lower_system_values.c index ba20d3083f..39b1a260bd 100644 --- a/src/compiler/nir/nir_lower_system_values.c +++ b/src/compiler/nir/nir_lower_system_values.c @@ -58,6 +58,7 @@ convert_block(nir_block *block, nir_builder *b) */ nir_const_value local_size; + memset(_size, 0, sizeof(local_size)); local_size.u32[0] = b->shader->info.cs.local_size[0]; local_size.u32[1] = b->shader->info.cs.local_size[1]; local_size.u32[2] = b->shader->info.cs.local_size[2]; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nir/intrinsics: Set the correct num_indices for load_output
Module: Mesa
Branch: master
Commit: c1b84256ccc443a9792893bc780bba970c0dcd4e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c1b84256ccc443a9792893bc780bba970c0dcd4e
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Sep 15 16:22:00 2017 -0700
nir/intrinsics: Set the correct num_indices for load_output
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>
---
src/compiler/nir/nir_intrinsics.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir_intrinsics.h
b/src/compiler/nir/nir_intrinsics.h
index 0de7080bfa..cefd18be90 100644
--- a/src/compiler/nir/nir_intrinsics.h
+++ b/src/compiler/nir/nir_intrinsics.h
@@ -434,7 +434,7 @@ INTRINSIC(load_interpolated_input, 2, ARR(2, 1), true, 0, 0,
/* src[] = { buffer_index, offset }. No const_index */
LOAD(ssbo, 2, 0, xx, xx, xx, NIR_INTRINSIC_CAN_ELIMINATE)
/* src[] = { offset }. const_index[] = { base, component } */
-LOAD(output, 1, 1, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE)
+LOAD(output, 1, 2, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE)
/* src[] = { vertex, offset }. const_index[] = { base, component } */
LOAD(per_vertex_output, 2, 1, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE)
/* src[] = { offset }. const_index[] = { base } */
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Mesa (master): compiler/types: Support [de]serializing void types
Module: Mesa Branch: master Commit: 23327af91c3ccb82be3a5de3ed1b2b3f49168d75 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=23327af91c3ccb82be3a5de3ed1b2b3f49168d75 Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Thu Sep 14 16:49:14 2017 -0700 compiler/types: Support [de]serializing void types Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com> Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com> --- src/compiler/glsl_types.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp index a7fc7ff7f6..704b63c5cf 100644 --- a/src/compiler/glsl_types.cpp +++ b/src/compiler/glsl_types.cpp @@ -2149,6 +2149,8 @@ encode_type_to_blob(struct blob *blob, const glsl_type *type) } return; case GLSL_TYPE_VOID: + encoding = (type->base_type << 24); + break; case GLSL_TYPE_ERROR: default: assert(!"Cannot encode type!"); @@ -2230,6 +2232,7 @@ decode_type_from_blob(struct blob_reader *blob) return t; } case GLSL_TYPE_VOID: + return glsl_type::void_type; case GLSL_TYPE_ERROR: default: assert(!"Cannot decode type!"); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl_to_nir: Zero nir_constant in constant_copy for valgrind & nir_serialize
Module: Mesa Branch: master Commit: 87e71726e0c44871778c3e1428dc81649cd9f292 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=87e71726e0c44871778c3e1428dc81649cd9f292 Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Mon Oct 2 00:19:31 2017 -0700 glsl_to_nir: Zero nir_constant in constant_copy for valgrind & nir_serialize Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/compiler/glsl/glsl_to_nir.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp index 1d1085ffbc..c659a25ca7 100644 --- a/src/compiler/glsl/glsl_to_nir.cpp +++ b/src/compiler/glsl/glsl_to_nir.cpp @@ -219,7 +219,7 @@ constant_copy(ir_constant *ir, void *mem_ctx) if (ir == NULL) return NULL; - nir_constant *ret = ralloc(mem_ctx, nir_constant); + nir_constant *ret = rzalloc(mem_ctx, nir_constant); const unsigned rows = ir->type->vector_elements; const unsigned cols = ir->type->matrix_columns; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/link: Make better use of temporary variables
Module: Mesa Branch: master Commit: 69ed3244d4d9898e5353d34be6a160db409b6dc8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=69ed3244d4d9898e5353d34be6a160db409b6dc8 Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Thu Sep 28 09:55:15 2017 -0700 i965/link: Make better use of temporary variables The way NIR_PASS works (and, by extension, nir_optimize) is that they may clone the shader and throw the old one away. (We use this for testing nir_clone.) It's better if we just make a temporary variable, use it for everything, and re-assign to the gl_program at the end. [jordan.l.jus...@intel.com: Tested NIR_TEST_CLONE=1 with valgrind] Tested-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com> --- src/mesa/drivers/dri/i965/brw_link.cpp | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp index 9ddf023018..80868569ed 100644 --- a/src/mesa/drivers/dri/i965/brw_link.cpp +++ b/src/mesa/drivers/dri/i965/brw_link.cpp @@ -297,14 +297,15 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg) nir_lower_indirect_derefs(consumer, indirect_mask); const bool p_is_scalar = compiler->scalar_stage[producer->stage]; - shProg->_LinkedShaders[i]->Program->nir = - brw_nir_optimize(producer, compiler, p_is_scalar); + producer = brw_nir_optimize(producer, compiler, p_is_scalar); const bool c_is_scalar = compiler->scalar_stage[producer->stage]; - shProg->_LinkedShaders[next]->Program->nir = - brw_nir_optimize(consumer, compiler, c_is_scalar); + consumer = brw_nir_optimize(consumer, compiler, c_is_scalar); } +shProg->_LinkedShaders[i]->Program->nir = producer; +shProg->_LinkedShaders[next]->Program->nir = consumer; + next = i; } } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/link: Use prog->nir instead of creating a temporary
Module: Mesa Branch: master Commit: 2df897cf1ffd5ae01ecdbb66195d292a2a15df91 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2df897cf1ffd5ae01ecdbb66195d292a2a15df91 Author: Jason Ekstrand <jason.ekstr...@intel.com> Date: Thu Sep 28 09:58:59 2017 -0700 i965/link: Use prog->nir instead of creating a temporary This way, when NIR_PASS_V makes a clone of the shader (for testing nir_clone), the new and lowered version gets re-assigned to prog->nir. [jordan.l.jus...@intel.com: Tested NIR_TEST_CLONE=1 with valgrind] Tested-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com> --- src/mesa/drivers/dri/i965/brw_link.cpp | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp index dd6f895db0..1fe5ad66f5 100644 --- a/src/mesa/drivers/dri/i965/brw_link.cpp +++ b/src/mesa/drivers/dri/i965/brw_link.cpp @@ -316,11 +316,10 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg) continue; struct gl_program *prog = shader->Program; - nir_shader *nir = shader->Program->nir; - brw_shader_gather_info(nir, prog); + brw_shader_gather_info(prog->nir, prog); - NIR_PASS_V(nir, nir_lower_samplers, shProg); - NIR_PASS_V(nir, nir_lower_atomics, shProg); + NIR_PASS_V(prog->nir, nir_lower_samplers, shProg); + NIR_PASS_V(prog->nir, nir_lower_atomics, shProg); infos[stage] = >nir->info; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/link: Make more use of NIR_PASS
Module: Mesa
Branch: master
Commit: 006533d5ef0914ae7be258dc5b7d47ba5339ca20
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=006533d5ef0914ae7be258dc5b7d47ba5339ca20
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Thu Sep 28 09:58:38 2017 -0700
i965/link: Make more use of NIR_PASS
[jordan.l.jus...@intel.com: Tested NIR_TEST_CLONE=1 with valgrind]
Tested-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>
---
src/mesa/drivers/dri/i965/brw_link.cpp | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp
b/src/mesa/drivers/dri/i965/brw_link.cpp
index 80868569ed..dd6f895db0 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -278,12 +278,12 @@ brw_link_shader(struct gl_context *ctx, struct
gl_shader_program *shProg)
nir_shader *producer = shProg->_LinkedShaders[i]->Program->nir;
nir_shader *consumer = shProg->_LinkedShaders[next]->Program->nir;
-nir_remove_dead_variables(producer, nir_var_shader_out);
-nir_remove_dead_variables(consumer, nir_var_shader_in);
+NIR_PASS_V(producer, nir_remove_dead_variables,
nir_var_shader_out);
+NIR_PASS_V(consumer, nir_remove_dead_variables, nir_var_shader_in);
if (nir_remove_unused_varyings(producer, consumer)) {
- nir_lower_global_vars_to_local(producer);
- nir_lower_global_vars_to_local(consumer);
+ NIR_PASS_V(producer, nir_lower_global_vars_to_local);
+ NIR_PASS_V(consumer, nir_lower_global_vars_to_local);
nir_variable_mode indirect_mask = (nir_variable_mode) 0;
if (compiler->glsl_compiler_options[i].EmitNoIndirectTemp)
@@ -293,8 +293,8 @@ brw_link_shader(struct gl_context *ctx, struct
gl_shader_program *shProg)
* temporaries so we need to lower indirects on any of the
* varyings we have demoted here.
*/
- nir_lower_indirect_derefs(producer, indirect_mask);
- nir_lower_indirect_derefs(consumer, indirect_mask);
+ NIR_PASS_V(producer, nir_lower_indirect_derefs, indirect_mask);
+ NIR_PASS_V(consumer, nir_lower_indirect_derefs, indirect_mask);
const bool p_is_scalar =
compiler->scalar_stage[producer->stage];
producer = brw_nir_optimize(producer, compiler, p_is_scalar);
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Mesa (master): docs: Add Vulkan to features.txt
Module: Mesa
Branch: master
Commit: fe3d2559d941f8f69dbdb369221af69a9974d017
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fe3d2559d941f8f69dbdb369221af69a9974d017
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Mon Jul 31 14:32:04 2017 -0700
docs: Add Vulkan to features.txt
To get the extension list:
$ git grep -hE "extension name=\"VK_KHR" src/vulkan/registry/vk.xml | \
grep -v disabled | awk '{print $2}' | sed -E 's/(name=)?"//g' | sort
To find anv(il) and radv supported extensions:
$ git grep -hE "'VK_([A-Z]+)_[a-z]" src/intel/
$ git grep -hE "'VK_([A-Z]+)_[a-z]" src/amd/
v2:
* Add radv to Vulkan 1.0 list (Bas)
* 'started' => 'in progress'
* Drop KHX and EXT extensions (Jason)
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Acked-by: Jason Ekstrand <ja...@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
---
docs/features.txt | 41 +
1 file changed, 41 insertions(+)
diff --git a/docs/features.txt b/docs/features.txt
index 672a23e99b..28842ed0f2 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -339,6 +339,47 @@ we DO NOT WANT implementations of these extensions for
Mesa.
GL_ARB_shadow_ambient Superseded by
GL_ARB_fragment_program
GL_ARB_vertex_blend Superseded by
GL_ARB_vertex_program
+Vulkan 1.0 -- all DONE: anv, radv
+
+Khronos extensions that are not part of any Vulkan version:
+ VK_KHR_16bit_storage in progress (Alejandro)
+ VK_KHR_android_surfacenot started
+ VK_KHR_dedicated_allocation DONE (anv, radv)
+ VK_KHR_descriptor_update_template DONE (anv, radv)
+ VK_KHR_displaynot started
+ VK_KHR_display_swapchain not started
+ VK_KHR_external_fence not started
+ VK_KHR_external_fence_capabilitiesnot started
+ VK_KHR_external_fence_fd not started
+ VK_KHR_external_fence_win32 not started
+ VK_KHR_external_memoryDONE (anv, radv)
+ VK_KHR_external_memory_capabilities DONE (anv, radv)
+ VK_KHR_external_memory_fd DONE (anv, radv)
+ VK_KHR_external_memory_win32 not started
+ VK_KHR_external_semaphore DONE (radv)
+ VK_KHR_external_semaphore_capabilitiesDONE (radv)
+ VK_KHR_external_semaphore_fd DONE (radv)
+ VK_KHR_external_semaphore_win32 not started
+ VK_KHR_get_memory_requirements2 DONE (anv, radv)
+ VK_KHR_get_physical_device_properties2DONE (anv, radv)
+ VK_KHR_get_surface_capabilities2 DONE (anv)
+ VK_KHR_incremental_presentDONE (anv, radv)
+ VK_KHR_maintenance1 DONE (anv, radv)
+ VK_KHR_mir_surfacenot started
+ VK_KHR_push_descriptorDONE (anv, radv)
+ VK_KHR_sampler_mirror_clamp_to_edge DONE (anv, radv)
+ VK_KHR_shader_draw_parameters DONE (anv, radv)
+ VK_KHR_shared_presentable_image not started
+ VK_KHR_storage_buffer_storage_class DONE (anv, radv)
+ VK_KHR_surfaceDONE (anv, radv)
+ VK_KHR_swapchain DONE (anv, radv)
+ VK_KHR_variable_pointers DONE (anv, radv)
+ VK_KHR_wayland_surfaceDONE (anv, radv)
+ VK_KHR_win32_keyed_mutex not started
+ VK_KHR_win32_surface not started
+ VK_KHR_xcb_surfaceDONE (anv, radv)
+ VK_KHR_xlib_surface DONE (anv, radv)
+
A graphical representation of this information can be found at
https://mesamatrix.net/
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Mesa (master): intel/aubinator: Stop searching after a custom handler is found
Module: Mesa
Branch: master
Commit: 0370350d11bcb5f1ca82a4f9ee0ae6eb239d32db
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0370350d11bcb5f1ca82a4f9ee0ae6eb239d32db
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Tue Mar 28 13:36:11 2017 -0700
intel/aubinator: Stop searching after a custom handler is found
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
src/intel/tools/aubinator.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index 05d932ea6c..f1bedd271e 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -725,8 +725,10 @@ parse_commands(struct gen_spec *spec, uint32_t *cmds, int
size, int engine)
decode_group(inst, p, 0);
for (i = 0; i < ARRAY_LENGTH(custom_handlers); i++) {
-if (gen_group_get_opcode(inst) == custom_handlers[i].opcode)
+if (gen_group_get_opcode(inst) == custom_handlers[i].opcode) {
custom_handlers[i].handle(spec, p);
+ break;
+}
}
}
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Mesa (master): intel/gen_decoder: return -1 for unknown command formats
Module: Mesa
Branch: master
Commit: d5bd0e411ede67f5c56f95ae4d905d8d94c9be2f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5bd0e411ede67f5c56f95ae4d905d8d94c9be2f
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Tue Mar 28 12:03:37 2017 -0700
intel/gen_decoder: return -1 for unknown command formats
Decoding with aubinator encountered a command of 0x. With the
previous code, it caused aubinator to jump 255 + 2 dwords to start
decoding again.
Instead we can attempt to detect the known instruction formats. If the
format is not recognized, then we can advance just 1 dword.
v2:
* Update aubinator_error_decode
* Actually convert the length variable returned into a *signed* integer
in aubinator.c, intel_batchbuffer.c and aubinator_error_decode.c.
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
src/intel/common/gen_decoder.c| 22 +++---
src/intel/tools/aubinator.c | 7 ---
src/intel/tools/aubinator_error_decode.c | 7 ---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 8
4 files changed, 27 insertions(+), 17 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 1244f4c448..03c9c7f8d4 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -692,28 +692,36 @@ gen_group_get_length(struct gen_group *group, const
uint32_t *p)
case 3: /* Render */ {
uint32_t subtype = field(h, 27, 28);
+ uint32_t opcode = field(h, 24, 26);
switch (subtype) {
case 0:
- return field(h, 0, 7) + 2;
+ if (opcode < 2)
+return field(h, 0, 7) + 2;
+ else
+return -1;
case 1:
- return 1;
+ if (opcode < 2)
+return 1;
+ else
+return -1;
case 2: {
- uint32_t opcode = field(h, 24, 26);
- assert(opcode < 3 /* 3 and above currently reserved */);
if (opcode == 0)
return field(h, 0, 7) + 2;
else if (opcode < 3)
return field(h, 0, 15) + 2;
else
-return 1; /* FIXME: if more opcodes are added */
+return -1;
}
case 3:
- return field(h, 0, 7) + 2;
+ if (opcode < 4)
+return field(h, 0, 7) + 2;
+ else
+return -1;
}
}
}
- unreachable("bad opcode");
+ return -1;
}
void
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index cae578baba..05d932ea6c 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -682,17 +682,18 @@ static void
parse_commands(struct gen_spec *spec, uint32_t *cmds, int size, int engine)
{
uint32_t *p, *end = cmds + size / 4;
- unsigned int length, i;
+ int length, i;
struct gen_group *inst;
for (p = cmds; p < end; p += length) {
inst = gen_spec_find_instruction(spec, p);
+ length = gen_group_get_length(inst, p);
+ assert(inst == NULL || length > 0);
+ length = MAX2(1, length);
if (inst == NULL) {
fprintf(outfile, "unknown instruction %08x\n", p[0]);
- length = (p[0] & 0xff) + 2;
continue;
}
- length = gen_group_get_length(inst, p);
const char *color, *reset_color = NORMAL;
uint64_t offset;
diff --git a/src/intel/tools/aubinator_error_decode.c
b/src/intel/tools/aubinator_error_decode.c
index 1bdab00a66..2e623698ed 100644
--- a/src/intel/tools/aubinator_error_decode.c
+++ b/src/intel/tools/aubinator_error_decode.c
@@ -217,7 +217,7 @@ static void decode(struct gen_spec *spec,
int *count)
{
uint32_t *p, *end = (data + *count);
- unsigned int length;
+ int length;
struct gen_group *inst;
for (p = data; p < end; p += length) {
@@ -226,9 +226,11 @@ static void decode(struct gen_spec *spec,
uint64_t offset = gtt_offset + 4 * (p - data);
inst = gen_spec_find_instruction(spec, p);
+ length = gen_group_get_length(inst, p);
+ assert(inst == NULL || length > 0);
+ length = MAX2(1, length);
if (inst == NULL) {
printf("unknown instruction %08x\n", p[0]);
- length = (p[0] & 0xff) + 2;
continue;
}
if (option_color == COLOR_NEVER) {
@@ -241,7 +243,6 @@ static void decode(struct gen_spec *spec,
gen_print_group(stdout, inst, offset, p,
option_color == COLOR_ALWAYS);
- length = gen_group_get_length(inst, p);
}
}
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 54bab9efb0..54777d1c34 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -220,7 +220,7 @@ do_batch_dump(st
Mesa (master): intel/aubinator_error_decode: Fix structure decode data
Module: Mesa
Branch: master
Commit: 3c77a5722252e01f2f5e4e320d2772f1f6c03f2c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3c77a5722252e01f2f5e4e320d2772f1f6c03f2c
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Wed Apr 5 22:34:42 2017 -0700
intel/aubinator_error_decode: Fix structure decode data
The call to gen_print_group should provide a pointer to the beginning
of the the structure data, not the start of the batch data.
Cc: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
src/intel/tools/aubinator_error_decode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/tools/aubinator_error_decode.c
b/src/intel/tools/aubinator_error_decode.c
index 8a67f4f169..1bdab00a66 100644
--- a/src/intel/tools/aubinator_error_decode.c
+++ b/src/intel/tools/aubinator_error_decode.c
@@ -239,7 +239,7 @@ static void decode(struct gen_spec *spec,
printf("%s0x%08"PRIx64": 0x%08x: %-80s%s\n",
color, offset, p[0], gen_group_get_name(inst), reset_color);
- gen_print_group(stdout, inst, offset, data,
+ gen_print_group(stdout, inst, offset, p,
option_color == COLOR_ALWAYS);
length = gen_group_get_length(inst, p);
}
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Mesa (master): intel/gen_decoder: Fix length for Media State/ Object commands
Module: Mesa
Branch: master
Commit: 7c33372f82707d42293b1772d53ab50a2f56d6a3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c33372f82707d42293b1772d53ab50a2f56d6a3
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Tue Mar 28 11:55:26 2017 -0700
intel/gen_decoder: Fix length for Media State/Object commands
From BDW PRM, Volume 6: Command Stream Programming, 'Render Command
Header Format'.
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
src/intel/common/gen_decoder.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 1ae78c88e3..1244f4c448 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -697,8 +697,16 @@ gen_group_get_length(struct gen_group *group, const
uint32_t *p)
return field(h, 0, 7) + 2;
case 1:
return 1;
- case 2:
- return 2;
+ case 2: {
+ uint32_t opcode = field(h, 24, 26);
+ assert(opcode < 3 /* 3 and above currently reserved */);
+ if (opcode == 0)
+return field(h, 0, 7) + 2;
+ else if (opcode < 3)
+return field(h, 0, 15) + 2;
+ else
+return 1; /* FIXME: if more opcodes are added */
+ }
case 3:
return field(h, 0, 7) + 2;
}
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Mesa (master): i965/vec4: Fix mapping attributes
Module: Mesa
Branch: master
Commit: 56ee2df4bf9b1e8c26cf8689f5ef20237c95466b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=56ee2df4bf9b1e8c26cf8689f5ef20237c95466b
Author: Juan A. Suarez Romero <jasua...@igalia.com>
Date: Fri Jan 13 17:47:57 2017 +0100
i965/vec4: Fix mapping attributes
This patch reverts 57bab6708f2bbc1ab8a3d202e9a467963596d462, which was
causing issues with ILK and earlier VS programs.
1. brw_nir.c: Revert "i965/vec4/nir: vec4 also needs to remap vs attributes"
Do not perform a remap in vec4 backend. Rather, do it later when
setup attributes
2. brw_vec4.cpp: This fixes mapping ATTRx to proper GRFn.
Suggested-by: Kenneth Graunke <kenn...@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99391
[jordan.l.jus...@intel.com: merge Juan's two patches from bugzilla]
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_nir.c| 32 ++--
src/mesa/drivers/dri/i965/brw_vec4.cpp | 2 +-
2 files changed, 11 insertions(+), 23 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c
b/src/mesa/drivers/dri/i965/brw_nir.c
index b39e2b1..3c1bc51 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -95,19 +95,9 @@ add_const_offset_to_base(nir_shader *nir, nir_variable_mode
mode)
}
}
-struct remap_vs_attrs_params {
- shader_info *nir_info;
- bool is_scalar;
-};
-
static bool
-remap_vs_attrs(nir_block *block, void *closure)
+remap_vs_attrs(nir_block *block, shader_info *nir_info)
{
- struct remap_vs_attrs_params *params =
- (struct remap_vs_attrs_params *) closure;
- shader_info *nir_info = params->nir_info;
- bool is_scalar = params->is_scalar;
-
nir_foreach_instr(instr, block) {
if (instr->type != nir_instr_type_intrinsic)
continue;
@@ -123,7 +113,7 @@ remap_vs_attrs(nir_block *block, void *closure)
int attr = intrin->const_index[0];
int slot = _mesa_bitcount_64(nir_info->inputs_read &
BITFIELD64_MASK(attr));
- intrin->const_index[0] = is_scalar ? 4 * slot : slot;
+ intrin->const_index[0] = 4 * slot;
}
}
return true;
@@ -267,11 +257,6 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
bool use_legacy_snorm_formula,
const uint8_t *vs_attrib_wa_flags)
{
- struct remap_vs_attrs_params params = {
- .nir_info = nir->info,
- .is_scalar = is_scalar
- };
-
/* Start with the location of the variable's base. */
foreach_list_typed(nir_variable, var, node, >inputs) {
var->data.driver_location = var->data.location;
@@ -291,11 +276,14 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
brw_nir_apply_attribute_workarounds(nir, use_legacy_snorm_formula,
vs_attrib_wa_flags);
- /* Finally, translate VERT_ATTRIB_* values into the actual registers. */
- nir_foreach_function(function, nir) {
- if (function->impl) {
- nir_foreach_block(block, function->impl) {
-remap_vs_attrs(block, );
+ if (is_scalar) {
+ /* Finally, translate VERT_ATTRIB_* values into the actual registers. */
+
+ nir_foreach_function(function, nir) {
+ if (function->impl) {
+nir_foreach_block(block, function->impl) {
+ remap_vs_attrs(block, nir->info);
+}
}
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 748a068..5e60eb6 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1739,7 +1739,7 @@ vec4_vs_visitor::setup_attributes(int payload_reg)
int needed_slots =
(vs_prog_data->double_inputs_read & BITFIELD64_BIT(first)) ? 2 : 1;
for (int c = 0; c < needed_slots; c++) {
- attribute_map[nr_attributes] = payload_reg + nr_attributes;
+ attribute_map[first + c] = payload_reg + nr_attributes;
nr_attributes++;
vs_inputs &= ~BITFIELD64_BIT(first + c);
}
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Mesa (master): intel/blorp_blit: Fix max blit size for gen6
Module: Mesa
Branch: master
Commit: 097c9dc2d4abc57bac5195fa0bed327828a4a895
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=097c9dc2d4abc57bac5195fa0bed327828a4a895
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Fri Dec 23 18:41:15 2016 -0800
intel/blorp_blit: Fix max blit size for gen6
Fixes
ES3-CTS.gtf.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_stencil_blit
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/intel/blorp/blorp_blit.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 8abe3a8..1cbd940 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -1522,10 +1522,11 @@ static unsigned
get_max_surface_size(const struct gen_device_info *devinfo,
const struct blorp_params *params)
{
+ const unsigned max = devinfo->gen >= 7 ? 16384 : 8192;
if (split_blorp_blit_debug && can_shrink_surfaces(params))
- return 16384 >> 4; /* A smaller restriction when debug is enabled */
+ return max >> 4; /* A smaller restriction when debug is enabled */
else
- return 16384;
+ return max;
}
struct blt_axis {
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Mesa (master): intel/blorp_blit: Adjust blorp surface parameters for split blits
Module: Mesa
Branch: master
Commit: edf3113aeddcf66cb24906e53a2d4f41616f8985
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=edf3113aeddcf66cb24906e53a2d4f41616f8985
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Mon Nov 7 14:08:22 2016 -0800
intel/blorp_blit: Adjust blorp surface parameters for split blits
If try_blorp_blit() previously returned that a blit was too large,
shrink_surface_params() will be used to update the surface parameters
for the smaller blit so the blit operation can proceed.
v2:
* Use double instead of float. (Jason)
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/intel/blorp/blorp_blit.c | 97 ++--
1 file changed, 94 insertions(+), 3 deletions(-)
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 05977f0..b976eef 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -1484,6 +1484,12 @@ surf_retile_w_to_y(const struct isl_device *isl_dev,
info->tile_y_sa /= 2;
}
+static bool
+can_shrink_surfaces(const struct blorp_params *params)
+{
+ return false;
+}
+
struct blt_axis {
double src0, src1, dst0, dst1;
bool mirror;
@@ -1738,12 +1744,88 @@ adjust_split_source_coords(const struct blt_axis *orig,
split_coords->src1 = orig->src1 + (scale >= 0.0 ? delta1 : delta0);
}
+static const struct isl_extent2d
+get_px_size_sa(const struct isl_surf *surf)
+{
+ static const struct isl_extent2d one_to_one = { .w = 1, .h = 1 };
+
+ if (surf->msaa_layout != ISL_MSAA_LAYOUT_INTERLEAVED)
+ return one_to_one;
+ else
+ return isl_get_interleaved_msaa_px_size_sa(surf->samples);
+}
+
+static void
+shrink_surface_params(const struct isl_device *dev,
+ struct brw_blorp_surface_info *info,
+ double *x0, double *x1, double *y0, double *y1)
+{
+ uint32_t byte_offset, x_offset_sa, y_offset_sa, size;
+ struct isl_extent2d px_size_sa;
+ int adjust;
+
+ surf_convert_to_single_slice(dev, info);
+
+ px_size_sa = get_px_size_sa(>surf);
+
+ /* Because this gets called after we lower compressed images, the tile
+* offsets may be non-zero and we need to incorporate them in our
+* calculations.
+*/
+ x_offset_sa = (uint32_t)*x0 * px_size_sa.w + info->tile_x_sa;
+ y_offset_sa = (uint32_t)*y0 * px_size_sa.h + info->tile_y_sa;
+ isl_tiling_get_intratile_offset_sa(dev, info->surf.tiling,
+ info->surf.format, info->surf.row_pitch,
+ x_offset_sa, y_offset_sa,
+ _offset,
+ >tile_x_sa, >tile_y_sa);
+
+ info->addr.offset += byte_offset;
+
+ adjust = (int)info->tile_x_sa / px_size_sa.w - (int)*x0;
+ *x0 += adjust;
+ *x1 += adjust;
+ info->tile_x_sa = 0;
+
+ adjust = (int)info->tile_y_sa / px_size_sa.h - (int)*y0;
+ *y0 += adjust;
+ *y1 += adjust;
+ info->tile_y_sa = 0;
+
+ size = MIN2((uint32_t)ceil(*x1), info->surf.logical_level0_px.width);
+ info->surf.logical_level0_px.width = size;
+ info->surf.phys_level0_sa.width = size * px_size_sa.w;
+
+ size = MIN2((uint32_t)ceil(*y1), info->surf.logical_level0_px.height);
+ info->surf.logical_level0_px.height = size;
+ info->surf.phys_level0_sa.height = size * px_size_sa.h;
+}
+
+static void
+shrink_surfaces(const struct isl_device *dev,
+struct blorp_params *params,
+struct brw_blorp_blit_prog_key *wm_prog_key,
+struct blt_coords *coords)
+{
+ /* Shrink source surface */
+ shrink_surface_params(dev, >src, >x.src0, >x.src1,
+ >y.src0, >y.src1);
+ wm_prog_key->need_src_offset = false;
+
+ /* Shrink destination surface */
+ shrink_surface_params(dev, >dst, >x.dst0, >x.dst1,
+ >y.dst0, >y.dst1);
+ wm_prog_key->need_dst_offset = false;
+}
+
static void
do_blorp_blit(struct blorp_batch *batch,
- struct blorp_params *params,
+ const struct blorp_params *orig_params,
struct brw_blorp_blit_prog_key *wm_prog_key,
const struct blt_coords *orig)
{
+ struct blorp_params params;
+ struct blt_coords blit_coords;
struct blt_coords split_coords = *orig;
double w = orig->x.dst1 - orig->x.dst0;
double h = orig->y.dst1 - orig->y.dst0;
@@ -1755,9 +1837,15 @@ do_blorp_blit(struct blorp_batch *batch,
y_scale = -y_scale;
bool x_done, y_done;
+ bool shrink = false;
do {
+ params = *orig_params;
+ blit_coords = split_coords;
+ if (shrink)
+ shrink_surfaces(batch->blorp->isl_dev, , wm_prog_key,
+ _coords);
enum blit_shrink_status r
Mesa (master): intel/blorp_blit: Add split_blorp_blit_debug switch
Module: Mesa
Branch: master
Commit: d6526d724765e14fc9bb25cd2a53463a4d1c5fff
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6526d724765e14fc9bb25cd2a53463a4d1c5fff
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Tue Nov 22 17:20:42 2016 -0800
intel/blorp_blit: Add split_blorp_blit_debug switch
Enabling this debug switch causes surface shrinking to happen by
default, and lowers the surface size limit which causes blorp blits to
be split.
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/intel/blorp/blorp_blit.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 280d6e1..8abe3a8 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -28,6 +28,8 @@
#define FILE_DEBUG_FLAG DEBUG_BLORP
+static const bool split_blorp_blit_debug = false;
+
/**
* Enum to specify the order of arguments in a sampler message
*/
@@ -1517,9 +1519,13 @@ can_shrink_surfaces(const struct blorp_params *params)
}
static unsigned
-get_max_surface_size()
+get_max_surface_size(const struct gen_device_info *devinfo,
+ const struct blorp_params *params)
{
- return 16384;
+ if (split_blorp_blit_debug && can_shrink_surfaces(params))
+ return 16384 >> 4; /* A smaller restriction when debug is enabled */
+ else
+ return 16384;
}
struct blt_axis {
@@ -1940,7 +1946,7 @@ do_blorp_blit(struct blorp_batch *batch,
y_scale = -y_scale;
bool x_done, y_done;
- bool shrink = false;
+ bool shrink = split_blorp_blit_debug && can_shrink_surfaces(orig_params);
do {
params = *orig_params;
blit_coords = split_coords;
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Mesa (master): intel/blorp_blit: Enable splitting large blorp blits
Module: Mesa
Branch: master
Commit: da381ae6475dfd35f1ab8c6063b4dce368ef7588
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=da381ae6475dfd35f1ab8c6063b4dce368ef7588
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Mon Nov 7 14:07:07 2016 -0800
intel/blorp_blit: Enable splitting large blorp blits
Detect when the surface sizes are too large for a blorp blit. When it
is too large, the blorp blit will be split into a smaller operation
and attempted again.
For gen7, this fixes the cts test:
ES3-CTS.gtf.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_multisampled_to_singlesampled_blit
It will also enable us to increase our renderable size from 8k x 8k to
16k x 16k.
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/intel/blorp/blorp_blit.c | 41 -
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index d16bab2..280d6e1 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -1485,9 +1485,41 @@ surf_retile_w_to_y(const struct isl_device *isl_dev,
}
static bool
+can_shrink_surface(const struct brw_blorp_surface_info *surf)
+{
+ /* The current code doesn't support offsets into the aux buffers. This
+* should be possible, but we need to make sure the offset is page
+* aligned for both the surface and the aux buffer surface. Generally
+* this mean using the page aligned offset for the aux buffer.
+*
+* Currently the cases where we must split the blit are limited to cases
+* where we don't have a aux buffer.
+*/
+ if (surf->aux_addr.buffer != NULL)
+ return false;
+
+ /* We can't support splitting the blit for gen <= 7, because the qpitch
+* size is calculated by the hardware based on the surface height for
+* gen <= 7. In gen >= 8, the qpitch is controlled by the driver.
+*/
+ if (surf->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY)
+ return false;
+
+ return true;
+}
+
+static bool
can_shrink_surfaces(const struct blorp_params *params)
{
- return false;
+ return
+ can_shrink_surface(>src) &&
+ can_shrink_surface(>dst);
+}
+
+static unsigned
+get_max_surface_size()
+{
+ return 16384;
}
struct blt_axis {
@@ -1781,6 +1813,13 @@ try_blorp_blit(struct blorp_batch *batch,
brw_blorp_get_blit_kernel(batch->blorp, params, wm_prog_key);
unsigned result = 0;
+ unsigned max_surface_size = get_max_surface_size(devinfo, params);
+ if (params->src.surf.logical_level0_px.width > max_surface_size ||
+ params->dst.surf.logical_level0_px.width > max_surface_size)
+ result |= BLIT_WIDTH_SHRINK;
+ if (params->src.surf.logical_level0_px.height > max_surface_size ||
+ params->dst.surf.logical_level0_px.height > max_surface_size)
+ result |= BLIT_HEIGHT_SHRINK;
if (result == 0) {
batch->blorp->exec(batch, params);
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Mesa (master): i965: Increase max texture to 16k for gen7+
Module: Mesa
Branch: master
Commit: e9133dd90ec498cfb6a23fa22504e06488352c51
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9133dd90ec498cfb6a23fa22504e06488352c51
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Thu Nov 3 12:20:19 2016 -0700
i965: Increase max texture to 16k for gen7+
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98297
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_context.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index b928f94..4ca77c7 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -527,14 +527,21 @@ brw_initialize_context_constants(struct brw_context *brw)
ctx->Const.MaxTextureCoordUnits = 8; /* Mesa limit */
ctx->Const.MaxImageUnits = MAX_IMAGE_UNITS;
- ctx->Const.MaxRenderbufferSize = 8192;
- ctx->Const.MaxTextureLevels = MIN2(14 /* 8192 */, MAX_TEXTURE_LEVELS);
+ if (brw->gen >= 7) {
+ ctx->Const.MaxRenderbufferSize = 16384;
+ ctx->Const.MaxTextureLevels = MIN2(15 /* 16384 */, MAX_TEXTURE_LEVELS);
+ ctx->Const.MaxCubeTextureLevels = 15; /* 16384 */
+ } else {
+ ctx->Const.MaxRenderbufferSize = 8192;
+ ctx->Const.MaxTextureLevels = MIN2(14 /* 8192 */, MAX_TEXTURE_LEVELS);
+ ctx->Const.MaxCubeTextureLevels = 14; /* 8192 */
+ }
ctx->Const.Max3DTextureLevels = 12; /* 2048 */
- ctx->Const.MaxCubeTextureLevels = 14; /* 8192 */
ctx->Const.MaxArrayTextureLayers = brw->gen >= 7 ? 2048 : 512;
ctx->Const.MaxTextureMbytes = 1536;
ctx->Const.MaxTextureRectSize = 1 << 12;
ctx->Const.MaxTextureMaxAnisotropy = 16.0;
+ ctx->Const.MaxTextureLodBias = 15.0;
ctx->Const.StripTextureBorder = true;
if (brw->gen >= 7) {
ctx->Const.MaxProgramTextureGatherComponents = 4;
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Mesa (master): intel/blorp_blit: Create structure for src & dst coordinates
Module: Mesa
Branch: master
Commit: b74d4f6ca02715470d8f7726d19aff342873dbc6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b74d4f6ca02715470d8f7726d19aff342873dbc6
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Mon Nov 7 14:06:49 2016 -0800
intel/blorp_blit: Create structure for src & dst coordinates
This will be useful for splitting blits into smaller sizes.
We also make the coordinates of type double rather than float. Since
we will be splitting and scaling the coordinates, we might require
extra precision in the calculations.
v2:
* Use double instead of float. (Jason)
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/intel/blorp/blorp_blit.c | 75 +---
1 file changed, 56 insertions(+), 19 deletions(-)
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 69b98c2..fffc03e 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -1484,15 +1484,20 @@ surf_retile_w_to_y(const struct isl_device *isl_dev,
info->tile_y_sa /= 2;
}
+struct blt_axis {
+ double src0, src1, dst0, dst1;
+ bool mirror;
+};
+
+struct blt_coords {
+ struct blt_axis x, y;
+};
+
static void
do_blorp_blit(struct blorp_batch *batch,
struct blorp_params *params,
struct brw_blorp_blit_prog_key *wm_prog_key,
- float src_x0, float src_y0,
- float src_x1, float src_y1,
- float dst_x0, float dst_y0,
- float dst_x1, float dst_y1,
- bool mirror_x, bool mirror_y)
+ const struct blt_coords *coords)
{
const struct gen_device_info *devinfo = batch->blorp->isl_dev->info;
@@ -1519,15 +1524,19 @@ do_blorp_blit(struct blorp_batch *batch,
/* Round floating point values to nearest integer to avoid "off by one
texel"
* kind of errors when blitting.
*/
- params->x0 = params->wm_inputs.discard_rect.x0 = roundf(dst_x0);
- params->y0 = params->wm_inputs.discard_rect.y0 = roundf(dst_y0);
- params->x1 = params->wm_inputs.discard_rect.x1 = roundf(dst_x1);
- params->y1 = params->wm_inputs.discard_rect.y1 = roundf(dst_y1);
+ params->x0 = params->wm_inputs.discard_rect.x0 = round(coords->x.dst0);
+ params->y0 = params->wm_inputs.discard_rect.y0 = round(coords->y.dst0);
+ params->x1 = params->wm_inputs.discard_rect.x1 = round(coords->x.dst1);
+ params->y1 = params->wm_inputs.discard_rect.y1 = round(coords->y.dst1);
brw_blorp_setup_coord_transform(>wm_inputs.coord_transform[0],
- src_x0, src_x1, dst_x0, dst_x1, mirror_x);
+ coords->x.src0, coords->x.src1,
+ coords->x.dst0, coords->x.dst1,
+ coords->x.mirror);
brw_blorp_setup_coord_transform(>wm_inputs.coord_transform[1],
- src_y0, src_y1, dst_y0, dst_y1, mirror_y);
+ coords->y.src0, coords->y.src1,
+ coords->y.dst0, coords->y.dst1,
+ coords->y.mirror);
if (devinfo->gen > 6 &&
params->dst.surf.msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) {
@@ -1764,10 +1773,24 @@ blorp_blit(struct blorp_batch *batch,
minify(params.src.surf.logical_level0_px.height, src_level) *
wm_prog_key.y_scale - 1.0f;
- do_blorp_blit(batch, , _prog_key,
- src_x0, src_y0, src_x1, src_y1,
- dst_x0, dst_y0, dst_x1, dst_y1,
- mirror_x, mirror_y);
+ struct blt_coords coords = {
+ .x = {
+ .src0 = src_x0,
+ .src1 = src_x1,
+ .dst0 = dst_x0,
+ .dst1 = dst_x1,
+ .mirror = mirror_x
+ },
+ .y = {
+ .src0 = src_y0,
+ .src1 = src_y1,
+ .dst0 = dst_y0,
+ .dst1 = dst_y1,
+ .mirror = mirror_y
+ }
+ };
+
+ do_blorp_blit(batch, , _prog_key, );
}
static enum isl_format
@@ -2076,8 +2099,22 @@ blorp_copy(struct blorp_batch *batch,
wm_prog_key.need_dst_offset = true;
}
- do_blorp_blit(batch, , _prog_key,
- src_x, src_y, src_x + src_width, src_y + src_height,
- dst_x, dst_y, dst_x + dst_width, dst_y + dst_height,
- false, false);
+ struct blt_coords coords = {
+ .x = {
+ .src0 = src_x,
+ .src1 = src_x + src_width,
+ .dst0 = dst_x,
+ .dst1 = dst_x + dst_width,
+ .mirror = false
+ },
+ .y = {
+ .src0 = src_y,
+ .src1 = src_y + src_height,
+ .dst0 = dst_y,
+ .dst1 = dst_y + dst_height,
+ .mirror = false
+ }
+ };
+
+ do_blorp_blit(batch, , _prog
Mesa (master): intel/blorp_blit: Move RGB=> R conversion to follow blit splitting
Module: Mesa
Branch: master
Commit: efea8e724458f6a388fb70421db3e655719fffb0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=efea8e724458f6a388fb70421db3e655719fffb0
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Wed Nov 30 15:53:48 2016 -0800
intel/blorp_blit: Move RGB=>R conversion to follow blit splitting
In blorp_copy, when RGB surfaces are copied, we convert the
destination surface to a Red only surface, but 3 times as wide. This
introduces an implicit restriction of "mod 3" for the destination
width.
It is easier to handle the blorp split buffer offsetting with the
original RGB surface, and do the RGB=>R after this.
Suggested-by: Jason Ekstrand <ja...@jlekstrand.net>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/intel/blorp/blorp_blit.c | 113 +--
1 file changed, 65 insertions(+), 48 deletions(-)
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index b976eef..d16bab2 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -1499,6 +1499,68 @@ struct blt_coords {
struct blt_axis x, y;
};
+static void
+surf_fake_rgb_with_red(const struct isl_device *isl_dev,
+ struct brw_blorp_surface_info *info,
+ uint32_t *x, uint32_t *width)
+{
+ surf_convert_to_single_slice(isl_dev, info);
+
+ info->surf.logical_level0_px.width *= 3;
+ info->surf.phys_level0_sa.width *= 3;
+ *x *= 3;
+ *width *= 3;
+
+ enum isl_format red_format;
+ switch (info->view.format) {
+ case ISL_FORMAT_R8G8B8_UNORM:
+ red_format = ISL_FORMAT_R8_UNORM;
+ break;
+ case ISL_FORMAT_R8G8B8_UINT:
+ red_format = ISL_FORMAT_R8_UINT;
+ break;
+ case ISL_FORMAT_R16G16B16_UNORM:
+ red_format = ISL_FORMAT_R16_UNORM;
+ break;
+ case ISL_FORMAT_R16G16B16_UINT:
+ red_format = ISL_FORMAT_R16_UINT;
+ break;
+ case ISL_FORMAT_R32G32B32_UINT:
+ red_format = ISL_FORMAT_R32_UINT;
+ break;
+ default:
+ unreachable("Invalid RGB copy destination format");
+ }
+ assert(isl_format_get_layout(red_format)->channels.r.type ==
+ isl_format_get_layout(info->view.format)->channels.r.type);
+ assert(isl_format_get_layout(red_format)->channels.r.bits ==
+ isl_format_get_layout(info->view.format)->channels.r.bits);
+
+ info->surf.format = info->view.format = red_format;
+}
+
+static void
+fake_dest_rgb_with_red(const struct isl_device *dev,
+ struct blorp_params *params,
+ struct brw_blorp_blit_prog_key *wm_prog_key,
+ struct blt_coords *coords)
+{
+ /* Handle RGB destinations for blorp_copy */
+ const struct isl_format_layout *dst_fmtl =
+ isl_format_get_layout(params->dst.surf.format);
+
+ if (dst_fmtl->bpb % 3 == 0) {
+ uint32_t dst_x = coords->x.dst0;
+ uint32_t dst_width = coords->x.dst1 - dst_x;
+ surf_fake_rgb_with_red(dev, >dst,
+ _x, _width);
+ coords->x.dst0 = dst_x;
+ coords->x.dst1 = dst_x + dst_width;
+ wm_prog_key->dst_rgb = true;
+ wm_prog_key->need_dst_offset = true;
+ }
+}
+
enum blit_shrink_status {
BLIT_NO_SHRINK = 0,
BLIT_WIDTH_SHRINK = 1,
@@ -1513,10 +1575,12 @@ static enum blit_shrink_status
try_blorp_blit(struct blorp_batch *batch,
struct blorp_params *params,
struct brw_blorp_blit_prog_key *wm_prog_key,
- const struct blt_coords *coords)
+ struct blt_coords *coords)
{
const struct gen_device_info *devinfo = batch->blorp->isl_dev->info;
+ fake_dest_rgb_with_red(batch->blorp->isl_dev, params, wm_prog_key, coords);
+
if (isl_format_has_sint_channel(params->src.view.format)) {
wm_prog_key->texture_data_type = nir_type_int;
} else if (isl_format_has_uint_channel(params->src.view.format)) {
@@ -2149,46 +2213,6 @@ surf_convert_to_uncompressed(const struct isl_device
*isl_dev,
info->surf.format = get_copy_format_for_bpb(isl_dev, fmtl->bpb);
}
-static void
-surf_fake_rgb_with_red(const struct isl_device *isl_dev,
- struct brw_blorp_surface_info *info,
- uint32_t *x, uint32_t *width)
-{
- surf_convert_to_single_slice(isl_dev, info);
-
- info->surf.logical_level0_px.width *= 3;
- info->surf.phys_level0_sa.width *= 3;
- *x *= 3;
- *width *= 3;
-
- enum isl_format red_format;
- switch (info->view.format) {
- case ISL_FORMAT_R8G8B8_UNORM:
- red_format = ISL_FORMAT_R8_UNORM;
- break;
- case ISL_FORMAT_R8G8B8_UINT:
- red_format = ISL_FORMAT_R8_UINT;
- break;
- case ISL_FORMAT_R16G16B16_UNORM:
- red_format = ISL_FORMAT_R16_UNORM;
- br
Mesa (master): intel/blorp_blit: Split blorp blits if they are too large
Module: Mesa
Branch: master
Commit: 12e0a6e25967e097f9d18e9ee25b30248f617b28
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=12e0a6e25967e097f9d18e9ee25b30248f617b28
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Mon Nov 7 14:06:56 2016 -0800
intel/blorp_blit: Split blorp blits if they are too large
We rename do_blorp_blit() to try_blorp_blit(), and add a return error
if the surface size for the blit is too large. Now, do_blorp_blit() is
rewritten to try to split the blit into smaller operations if
try_blorp_blit() fails.
Note: In this commit, try_blorp_blit() will always attempt to blit and
never return an error, which matches the previous behavior. We will
enable the size checking and splitting in a future commit.
The motivation for this splitting is that in some cases when we
flatten an image, it's dimensions grow, and this can then exceed the
programmable hardware limits. An example is w-tiled+MSAA blits.
v2:
* Use double instead of float. (Jason)
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/intel/blorp/blorp_blit.c | 102 ---
1 file changed, 96 insertions(+), 6 deletions(-)
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index fffc03e..05977f0 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -1493,11 +1493,21 @@ struct blt_coords {
struct blt_axis x, y;
};
-static void
-do_blorp_blit(struct blorp_batch *batch,
- struct blorp_params *params,
- struct brw_blorp_blit_prog_key *wm_prog_key,
- const struct blt_coords *coords)
+enum blit_shrink_status {
+ BLIT_NO_SHRINK = 0,
+ BLIT_WIDTH_SHRINK = 1,
+ BLIT_HEIGHT_SHRINK = 2,
+};
+
+/* Try to blit. If the surface parameters exceed the size allowed by hardware,
+ * then enum blit_shrink_status will be returned. If BLIT_NO_SHRINK is
+ * returned, then the blit was successful.
+ */
+static enum blit_shrink_status
+try_blorp_blit(struct blorp_batch *batch,
+ struct blorp_params *params,
+ struct brw_blorp_blit_prog_key *wm_prog_key,
+ const struct blt_coords *coords)
{
const struct gen_device_info *devinfo = batch->blorp->isl_dev->info;
@@ -1700,7 +1710,87 @@ do_blorp_blit(struct blorp_batch *batch,
brw_blorp_get_blit_kernel(batch->blorp, params, wm_prog_key);
- batch->blorp->exec(batch, params);
+ unsigned result = 0;
+
+ if (result == 0) {
+ batch->blorp->exec(batch, params);
+ }
+
+ return result;
+}
+
+/* Adjust split blit source coordinates for the current destination
+ * coordinates.
+ */
+static void
+adjust_split_source_coords(const struct blt_axis *orig,
+ struct blt_axis *split_coords,
+ double scale)
+{
+ /* When scale is greater than 0, then we are growing from the start, so
+* src0 uses delta0, and src1 uses delta1. When scale is less than 0, the
+* source range shrinks from the end. In that case src0 is adjusted by
+* delta1, and src1 is adjusted by delta0.
+*/
+ double delta0 = scale * (split_coords->dst0 - orig->dst0);
+ double delta1 = scale * (split_coords->dst1 - orig->dst1);
+ split_coords->src0 = orig->src0 + (scale >= 0.0 ? delta0 : delta1);
+ split_coords->src1 = orig->src1 + (scale >= 0.0 ? delta1 : delta0);
+}
+
+static void
+do_blorp_blit(struct blorp_batch *batch,
+ struct blorp_params *params,
+ struct brw_blorp_blit_prog_key *wm_prog_key,
+ const struct blt_coords *orig)
+{
+ struct blt_coords split_coords = *orig;
+ double w = orig->x.dst1 - orig->x.dst0;
+ double h = orig->y.dst1 - orig->y.dst0;
+ double x_scale = (orig->x.src1 - orig->x.src0) / w;
+ double y_scale = (orig->y.src1 - orig->y.src0) / h;
+ if (orig->x.mirror)
+ x_scale = -x_scale;
+ if (orig->y.mirror)
+ y_scale = -y_scale;
+
+ bool x_done, y_done;
+ do {
+ enum blit_shrink_status result =
+ try_blorp_blit(batch, params, wm_prog_key, _coords);
+
+ if (result & BLIT_WIDTH_SHRINK) {
+ w /= 2.0;
+ assert(w >= 1.0);
+ split_coords.x.dst1 = MIN2(split_coords.x.dst0 + w, orig->x.dst1);
+ adjust_split_source_coords(>x, _coords.x, x_scale);
+ }
+ if (result & BLIT_HEIGHT_SHRINK) {
+ h /= 2.0;
+ assert(h >= 1.0);
+ split_coords.y.dst1 = MIN2(split_coords.y.dst0 + h, orig->y.dst1);
+ adjust_split_source_coords(>y, _coords.y, y_scale);
+ }
+
+ if (result != 0)
+ continue;
+
+ y_done = (orig->y.dst1 - split_coords.y.dst1 < 0.5);
+ x_done = y_done && (orig->x.dst1 - split_coords.x.dst1 < 0.5);
+ if (x_done) {
+ break;
+ } else if (y_do
Mesa (master): i965/gen7: Only advertise 4 samples for RGBA32F on GLES
Module: Mesa
Branch: master
Commit: 72c00e7c478f23835b4d94ef3a7c6ef2524d40fa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=72c00e7c478f23835b4d94ef3a7c6ef2524d40fa
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Fri Jul 22 15:23:55 2016 -0700
i965/gen7: Only advertise 4 samples for RGBA32F on GLES
We can't render to 8x MSAA if the width is greater than 64 bits. (see
brw_render_target_supported)
Fixes ES31-CTS.sample_variables.mask.rgba32f.samples_8.mask_*
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
Reviewed-by: Iago Toral Quiroga <ito...@igalia.com>
---
src/mesa/drivers/dri/i965/brw_formatquery.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_formatquery.c
b/src/mesa/drivers/dri/i965/brw_formatquery.c
index 8f7a910..96cc6e0 100644
--- a/src/mesa/drivers/dri/i965/brw_formatquery.c
+++ b/src/mesa/drivers/dri/i965/brw_formatquery.c
@@ -23,6 +23,7 @@
#include "brw_context.h"
#include "brw_state.h"
+#include "main/context.h"
#include "main/formatquery.h"
#include "main/glformats.h"
@@ -50,9 +51,24 @@ brw_query_samples_for_format(struct gl_context *ctx, GLenum
target,
return 3;
case 7:
- samples[0] = 8;
- samples[1] = 4;
- return 2;
+ if (internalFormat == GL_RGBA32F && _mesa_is_gles(ctx)) {
+ /* For GLES, we are allowed to return a smaller number of samples for
+ * GL_RGBA32F. See OpenGLES 3.2 spec, section 20.3.1 Internal Format
+ * Query Parameters, under SAMPLES:
+ *
+ * "A value less than or equal to the value of MAX_SAMPLES, if
+ * internalformat is RGBA16F, R32F, RG32F, or RGBA32F."
+ *
+ * In brw_render_target_supported, we prevent formats with a size
+ * greater than 8 bytes from using 8x MSAA on gen7.
+ */
+ samples[0] = 4;
+ return 1;
+ } else {
+ samples[0] = 8;
+ samples[1] = 4;
+ return 2;
+ }
case 6:
samples[0] = 4;
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Mesa (master): i965/hsw: Set integer mode in sampling state for stencil texturing
Module: Mesa
Branch: master
Commit: 44c5ed02d1b173c061c3188e245d384fd4c0abba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=44c5ed02d1b173c061c3188e245d384fd4c0abba
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sat Nov 19 14:52:29 2016 -0800
i965/hsw: Set integer mode in sampling state for stencil texturing
Fixes:
ES31-CTS.functional.texture.border_clamp.formats.depth24_stencil8_sample_stencil.nearest_size_pot
ES31-CTS.functional.texture.border_clamp.formats.depth24_stencil8_sample_stencil.nearest_size_npot
ES31-CTS.functional.texture.border_clamp.formats.depth32f_stencil8_sample_stencil.nearest_size_pot
ES31-CTS.functional.texture.border_clamp.formats.depth32f_stencil8_sample_stencil.nearest_size_npot
ES31-CTS.functional.texture.border_clamp.unused_channels.depth24_stencil8_sample_stencil
ES31-CTS.functional.texture.border_clamp.unused_channels.depth32f_stencil8_sample_stencil
Cc: "13.0" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_sampler_state.c | 18 +-
src/mesa/drivers/dri/i965/brw_state.h | 9 -
2 files changed, 9 insertions(+), 18 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c
b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index 7df2c55..412efb9 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -213,7 +213,7 @@ static void
upload_default_color(struct brw_context *brw,
const struct gl_sampler_object *sampler,
mesa_format format, GLenum base_format,
- bool is_integer_format,
+ bool is_integer_format, bool is_stencil_sampling,
uint32_t *sdc_offset)
{
union gl_color_union color;
@@ -277,7 +277,7 @@ upload_default_color(struct brw_context *brw,
uint32_t *sdc = brw_state_batch(brw, AUB_TRACE_SAMPLER_DEFAULT_COLOR,
4 * 4, 64, sdc_offset);
memcpy(sdc, color.ui, 4 * 4);
- } else if (brw->is_haswell && is_integer_format) {
+ } else if (brw->is_haswell && (is_integer_format || is_stencil_sampling)) {
/* Haswell's integer border color support is completely insane:
* SAMPLER_BORDER_COLOR_STATE is 20 DWords. The first four are
* for float colors. The next 12 DWords are MBZ and only exist to
@@ -291,10 +291,9 @@ upload_default_color(struct brw_context *brw,
memset(sdc, 0, 20 * 4);
sdc = [16];
+ bool stencil = format == MESA_FORMAT_S_UINT8 || is_stencil_sampling;
const int bits_per_channel =
- _mesa_get_format_bits(format,
- format == MESA_FORMAT_S_UINT8 ?
- GL_STENCIL_BITS : GL_RED_BITS);
+ _mesa_get_format_bits(format, stencil ? GL_STENCIL_BITS :
GL_RED_BITS);
/* From the Haswell PRM, "Command Reference: Structures", Page 36:
* "If any color channel is missing from the surface format,
@@ -389,12 +388,13 @@ upload_default_color(struct brw_context *brw,
* Sets the sampler state for a single unit based off of the sampler key
* entry.
*/
-void
+static void
brw_update_sampler_state(struct brw_context *brw,
GLenum target, bool tex_cube_map_seamless,
GLfloat tex_unit_lod_bias,
mesa_format format, GLenum base_format,
bool is_integer_format,
+ bool is_stencil_sampling,
const struct gl_sampler_object *sampler,
uint32_t *sampler_state,
uint32_t batch_offset_for_sampler_state)
@@ -516,8 +516,8 @@ brw_update_sampler_state(struct brw_context *brw,
if (wrap_mode_needs_border_color(wrap_s) ||
wrap_mode_needs_border_color(wrap_t) ||
wrap_mode_needs_border_color(wrap_r)) {
- upload_default_color(brw, sampler,
- format, base_format, is_integer_format,
+ upload_default_color(brw, sampler, format, base_format,
+ is_integer_format, is_stencil_sampling,
_color_offset);
}
@@ -555,7 +555,7 @@ update_sampler_state(struct brw_context *brw,
brw_update_sampler_state(brw, texObj->Target, ctx->Texture.CubeMapSeamless,
texUnit->LodBias,
firstImage->TexFormat, firstImage->_BaseFormat,
-texObj->_IsIntegerFormat,
+texObj->_IsIntegerFormat, texObj->StencilSampling,
sampler,
sampler_state, batch_offset_for_sampler_state);
}
diff --git a/src/mesa/drivers/dri/i965/br
Mesa (master): i965/gen7: Minify blit size for stencil tree copy
Module: Mesa Branch: master Commit: 0cee3fd5c73acf7e3841a7d790e3ec3031b0fe41 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0cee3fd5c73acf7e3841a7d790e3ec3031b0fe41 Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Tue Nov 15 17:55:41 2016 -0800 i965/gen7: Minify blit size for stencil tree copy Found by the piglit 'fbo-depth-array stencil-clear' test when implementing blorp blit splitting for gen7. Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Ben Widawsky <b...@bwidawsk.net> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 28001b6..e7f71c0 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -2373,9 +2373,11 @@ intel_update_r8stencil(struct brw_context *brw, dst, level, layers_per_blit * layer, MESA_FORMAT_R_UNORM8, 0, 0, - src->logical_width0, src->logical_height0, + minify(src->logical_width0, level), + minify(src->logical_height0, level), 0, 0, - dst->logical_width0, dst->logical_height0, + minify(dst->logical_width0, level), + minify(dst->logical_height0, level), GL_NEAREST, false, false /*mirror x, y*/, false, false /* decode/encode srgb */); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel/blorp: Use designated initializers in surf_convert_to_single_slice
Module: Mesa
Branch: master
Commit: 615ccf44cf0305976b15bad48252943802e41345
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=615ccf44cf0305976b15bad48252943802e41345
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Tue Nov 15 02:21:00 2016 -0800
intel/blorp: Use designated initializers in surf_convert_to_single_slice
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/intel/blorp/blorp_blit.c | 29 +
1 file changed, 13 insertions(+), 16 deletions(-)
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 1108335..c0b56c3 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -1347,22 +1347,19 @@ surf_convert_to_single_slice(const struct isl_device
*isl_dev,
uint32_t tile_x_px, tile_y_px;
surf_get_intratile_offset_px(info, _x_px, _y_px);
- /* TODO: Once this file gets converted to C, we shouls just use designated
-* initializers.
-*/
- struct isl_surf_init_info init_info = { 0, };
-
- init_info.dim = ISL_SURF_DIM_2D;
- init_info.format = info->surf.format;
- init_info.width = slice_width_px + tile_x_px;
- init_info.height = slice_height_px + tile_y_px;
- init_info.depth = 1;
- init_info.levels = 1;
- init_info.array_len = 1;
- init_info.samples = info->surf.samples;
- init_info.min_pitch = info->surf.row_pitch;
- init_info.usage = info->surf.usage;
- init_info.tiling_flags = 1 << info->surf.tiling;
+ struct isl_surf_init_info init_info = {
+ .dim = ISL_SURF_DIM_2D,
+ .format = info->surf.format,
+ .width = slice_width_px + tile_x_px,
+ .height = slice_height_px + tile_y_px,
+ .depth = 1,
+ .levels = 1,
+ .array_len = 1,
+ .samples = info->surf.samples,
+ .min_pitch = info->surf.row_pitch,
+ .usage = info->surf.usage,
+ .tiling_flags = 1 << info->surf.tiling,
+ };
isl_surf_init_s(isl_dev, >surf, _info);
assert(info->surf.row_pitch == init_info.min_pitch);
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Mesa (master): isl: Fix height calculation in isl_msaa_interleaved_scale_px_to_sa
Module: Mesa Branch: master Commit: 0ac57afa6fbe59e9fd8eef38365cb3da8ec67f95 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ac57afa6fbe59e9fd8eef38365cb3da8ec67f95 Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Tue Nov 15 02:18:25 2016 -0800 isl: Fix height calculation in isl_msaa_interleaved_scale_px_to_sa No known fixed tests, but it looks like a typo from: commit 8ac99eabb6570f0f3c5f7d7da1332a99ce636362 intel/isl: Add a helper for getting the size of an interleaved pixel Cc: "13.0" <mesa-sta...@lists.freedesktop.org> Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/intel/isl/isl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 7831c5e..32463b1 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -339,7 +339,7 @@ isl_msaa_interleaved_scale_px_to_sa(uint32_t samples, if (width) *width = isl_align(*width, 2) * px_size_sa.width; if (height) - *height = isl_align(*height, 2) * px_size_sa.width; + *height = isl_align(*height, 2) * px_size_sa.height; } static enum isl_array_pitch_span ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/compute: Allow ARB_compute_shader in compat profile
Module: Mesa Branch: master Commit: 7bcb94bc2fc45fde806ad3fd062bf2ce97342359 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7bcb94bc2fc45fde806ad3fd062bf2ce97342359 Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Thu Nov 3 15:22:11 2016 -0700 i965/compute: Allow ARB_compute_shader in compat profile Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97447 Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Tested-by: Evan Odabashian <eodab...@gmail.com> Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> --- src/mesa/drivers/dri/i965/brw_context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index a01decd..e67b957 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -501,7 +501,7 @@ brw_initialize_context_constants(struct brw_context *brw) [MESA_SHADER_GEOMETRY] = brw->gen >= 6, [MESA_SHADER_FRAGMENT] = true, [MESA_SHADER_COMPUTE] = - (ctx->API == API_OPENGL_CORE && + ((ctx->API == API_OPENGL_COMPAT || ctx->API == API_OPENGL_CORE) && ctx->Const.MaxComputeWorkGroupSize[0] >= 1024) || (ctx->API == API_OPENGLES2 && ctx->Const.MaxComputeWorkGroupSize[0] >= 128) || ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/cs: Don' t use a thread channel ID for small local sizes
Module: Mesa
Branch: master
Commit: 64c3d735354932c3b14397e9c292f5989a9da710
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=64c3d735354932c3b14397e9c292f5989a9da710
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Wed Jul 6 15:08:27 2016 -0700
i965/cs: Don't use a thread channel ID for small local sizes
When the local group size is 8 or less, we will execute the program at
most 1 time. Therefore, the local channel ID will always be 0. By
using a constant 0 in this case we can prevent using push constant
data.
This is not expected to be common a occurance in real applications,
but it has been seen in tests.
We could extend this optimization to 16 and 32 for SIMD16 and SIMD32,
but it gets a bit more complicated, because this optimization is
currently being done early on, before we have decided the SIMD size.
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
---
src/mesa/drivers/dri/i965/brw_nir_intrinsics.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_nir_intrinsics.c
b/src/mesa/drivers/dri/i965/brw_nir_intrinsics.c
index 9ae161f..d63570f 100644
--- a/src/mesa/drivers/dri/i965/brw_nir_intrinsics.c
+++ b/src/mesa/drivers/dri/i965/brw_nir_intrinsics.c
@@ -39,12 +39,21 @@ struct lower_intrinsics_state {
static nir_ssa_def *
read_thread_local_id(struct lower_intrinsics_state *state)
{
+ nir_builder *b = >builder;
+ nir_shader *nir = state->nir;
+ const unsigned *sizes = nir->info.cs.local_size;
+ const unsigned group_size = sizes[0] * sizes[1] * sizes[2];
+
+ /* Some programs have local_size dimensions so small that the thread local
+* ID will always be 0.
+*/
+ if (group_size <= 8)
+ return nir_imm_int(b, 0);
+
assert(state->cs_prog_data->thread_local_id_index >= 0);
state->cs_thread_id_used = true;
const int id_index = state->cs_prog_data->thread_local_id_index;
- nir_builder *b = >builder;
- nir_shader *nir = state->nir;
nir_intrinsic_instr *load =
nir_intrinsic_instr_create(nir, nir_intrinsic_load_uniform);
load->num_components = 1;
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Mesa (master): i965/cs: Use udiv/umod for local IDs
Module: Mesa Branch: master Commit: 1fa000a33b010436ac3bf4b3c8da2974d3788382 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1fa000a33b010436ac3bf4b3c8da2974d3788382 Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Wed Oct 19 10:25:21 2016 -0700 i965/cs: Use udiv/umod for local IDs This allows for more optimizations relating to power-of-two divisions. Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Ian Romanick <ian.d.roman...@intel.com> --- src/mesa/drivers/dri/i965/brw_nir_intrinsics.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_nir_intrinsics.c b/src/mesa/drivers/dri/i965/brw_nir_intrinsics.c index 059d14d..9ae161f 100644 --- a/src/mesa/drivers/dri/i965/brw_nir_intrinsics.c +++ b/src/mesa/drivers/dri/i965/brw_nir_intrinsics.c @@ -116,7 +116,7 @@ lower_cs_intrinsics_convert_block(struct lower_intrinsics_state *state, uvec3.u32[2] = size[2]; nir_ssa_def *mod_val = nir_build_imm(b, 3, 32, uvec3); - sysval = nir_imod(b, nir_idiv(b, local_index, div_val), mod_val); + sysval = nir_umod(b, nir_udiv(b, local_index, div_val), mod_val); break; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/hsw: Enable ARB_ES3_1_compatibility extension
Module: Mesa
Branch: master
Commit: 5e76baa2ad261c72f96a3df42ace4773a1c7daa9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e76baa2ad261c72f96a3df42ace4773a1c7daa9
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sat Aug 27 14:13:23 2016 -0700
i965/hsw: Enable ARB_ES3_1_compatibility extension
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Acked-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
---
docs/features.txt| 2 +-
src/mesa/drivers/dri/i965/intel_extensions.c | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/docs/features.txt b/docs/features.txt
index 26e8ff7..218fa6c 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -208,7 +208,7 @@ GL 4.4, GLSL 4.40 -- all DONE: i965/gen8+
GL 4.5, GLSL 4.50:
- GL_ARB_ES3_1_compatibilityDONE (i965/gen8+,
nvc0, radeonsi)
+ GL_ARB_ES3_1_compatibilityDONE (i965/hsw+, nvc0,
radeonsi)
GL_ARB_clip_control DONE (i965, nv50,
nvc0, r600, radeonsi, llvmpipe, softpipe, swr)
GL_ARB_conditional_render_invertedDONE (i965, nv50,
nvc0, r600, radeonsi, llvmpipe, softpipe, swr)
GL_ARB_cull_distance DONE (i965, nv50,
nvc0, llvmpipe, softpipe, swr)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 3ca30d0..76b585d 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -365,7 +365,8 @@ intelInitExtensions(struct gl_context *ctx)
if ((brw->gen >= 8 || brw->intelScreen->cmd_parser_version >= 5) &&
ctx->Const.MaxComputeWorkGroupSize[0] >= 1024) {
ctx->Extensions.ARB_compute_shader = true;
-ctx->Extensions.ARB_ES3_1_compatibility = brw->gen >= 8;
+ctx->Extensions.ARB_ES3_1_compatibility =
+ brw->gen >= 8 || brw->is_haswell;
}
if (brw->intelScreen->cmd_parser_version >= 2)
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Mesa (master): i965: Enable ARB_stencil_texturing for Haswell
Module: Mesa
Branch: master
Commit: f20f616324a79b8be91b84b6d965a0bc0096789c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f20f616324a79b8be91b84b6d965a0bc0096789c
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Wed Jun 8 13:21:10 2016 -0700
i965: Enable ARB_stencil_texturing for Haswell
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
---
src/mesa/drivers/dri/i965/intel_extensions.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index dd0d240..be004a2 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -373,6 +373,10 @@ intelInitExtensions(struct gl_context *ctx)
}
}
+ if (brw->gen >= 8 || brw->is_haswell) {
+ ctx->Extensions.ARB_stencil_texturing = true;
+ }
+
if (brw->gen >= 8 || brw->is_haswell || brw->is_baytrail) {
ctx->Extensions.ARB_robust_buffer_access_behavior = true;
}
@@ -391,7 +395,6 @@ intelInitExtensions(struct gl_context *ctx)
if (brw->gen >= 8) {
ctx->Extensions.ARB_shader_precision = true;
- ctx->Extensions.ARB_stencil_texturing = true;
ctx->Extensions.ARB_texture_stencil8 = true;
ctx->Extensions.ARB_gpu_shader_fp64 = true;
ctx->Extensions.ARB_vertex_attrib_64bit = true;
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Mesa (master): i965/hsw: Don' t advertise more than 64 threads for compute shaders
Module: Mesa
Branch: master
Commit: 30fee52036ac5e0180073ace4a8fd760556495be
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=30fee52036ac5e0180073ace4a8fd760556495be
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Tue Jun 14 15:04:34 2016 -0700
i965/hsw: Don't advertise more than 64 threads for compute shaders
thread_width_max in the GPGPU walker command limits us to a maximum of
64 threads.
This fixes a crash on Haswell in the OpenGLES 3.1 conformance test
suite which tests the advertised limits of the max invocation counts.
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
---
src/mesa/drivers/dri/i965/brw_context.c | 39 +
1 file changed, 25 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 1364393..58cd03d 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -769,12 +769,35 @@ brw_initialize_context_constants(struct brw_context *brw)
}
static void
-brw_initialize_cs_context_constants(struct brw_context *brw, unsigned
max_threads)
+brw_initialize_cs_context_constants(struct brw_context *brw)
{
struct gl_context *ctx = >ctx;
+ const struct intel_screen *screen = brw->intelScreen;
+ const struct brw_device_info *devinfo = screen->devinfo;
+
+ /* FINISHME: Do this for all platforms that the kernel supports */
+ if (brw->is_cherryview &&
+ screen->subslice_total > 0 && screen->eu_total > 0) {
+ /* Logical CS threads = EUs per subslice * 7 threads per EU */
+ brw->max_cs_threads = screen->eu_total / screen->subslice_total * 7;
+
+ /* Fuse configurations may give more threads than expected, never less.
*/
+ if (brw->max_cs_threads < devinfo->max_cs_threads)
+ brw->max_cs_threads = devinfo->max_cs_threads;
+ } else {
+ brw->max_cs_threads = devinfo->max_cs_threads;
+ }
+
/* Maximum number of scalar compute shader invocations that can be run in
* parallel in the same subslice assuming SIMD32 dispatch.
+*
+* We don't advertise more than 64 threads, because we are limited to 64 by
+* our usage of thread_width_max in the gpgpu walker command. This only
+* currently impacts Haswell, which otherwise might be able to advertise 70
+* threads. With SIMD32 and 64 threads, Haswell still provides twice the
+* required the number of invocation needed for ARB_compute_shader.
*/
+ const unsigned max_threads = MIN2(64, brw->max_cs_threads);
const uint32_t max_invocations = 32 * max_threads;
ctx->Const.MaxComputeWorkGroupSize[0] = max_invocations;
ctx->Const.MaxComputeWorkGroupSize[1] = max_invocations;
@@ -978,7 +1001,7 @@ brwCreateContext(gl_api api,
if (INTEL_DEBUG & DEBUG_PERF)
brw->perf_debug = true;
- brw_initialize_cs_context_constants(brw, devinfo->max_cs_threads);
+ brw_initialize_cs_context_constants(brw);
brw_initialize_context_constants(brw);
ctx->Const.ResetStrategy = notify_reset
@@ -1025,18 +1048,6 @@ brwCreateContext(gl_api api,
brw->max_ds_threads = devinfo->max_ds_threads;
brw->max_gs_threads = devinfo->max_gs_threads;
brw->max_wm_threads = devinfo->max_wm_threads;
- /* FINISHME: Do this for all platforms that the kernel supports */
- if (brw->is_cherryview &&
- screen->subslice_total > 0 && screen->eu_total > 0) {
- /* Logical CS threads = EUs per subslice * 7 threads per EU */
- brw->max_cs_threads = screen->eu_total / screen->subslice_total * 7;
-
- /* Fuse configurations may give more threads than expected, never less.
*/
- if (brw->max_cs_threads < devinfo->max_cs_threads)
- brw->max_cs_threads = devinfo->max_cs_threads;
- } else {
- brw->max_cs_threads = devinfo->max_cs_threads;
- }
brw->urb.size = devinfo->urb.size;
brw->urb.min_vs_entries = devinfo->urb.min_vs_entries;
brw->urb.max_vs_entries = devinfo->urb.max_vs_entries;
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Mesa (master): i965/gen7: Use R8_UINT stencil copy when sampling the stencil texture
Module: Mesa
Branch: master
Commit: 751682434ecb0489df3945f88e565079ecbe9f31
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=751682434ecb0489df3945f88e565079ecbe9f31
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sat Jun 11 16:41:18 2016 -0700
i965/gen7: Use R8_UINT stencil copy when sampling the stencil texture
v2:
* Check gen <= 7, rather than gen == 7. (Ian)
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 023b1ff..bfd973b 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -499,8 +499,16 @@ brw_update_texture_surface(struct gl_context *ctx,
}
if (obj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL)
{
- assert(brw->gen >= 8);
- mt = mt->stencil_mt;
+ if (brw->gen <= 7) {
+assert(mt->r8stencil_mt &&
!mt->stencil_mt->r8stencil_needs_update);
+mt = mt->r8stencil_mt;
+ } else {
+mt = mt->stencil_mt;
+ }
+ format = BRW_SURFACEFORMAT_R8_UINT;
+ } else if (brw->gen <= 7 && mt->format == MESA_FORMAT_S_UINT8) {
+ assert(mt->r8stencil_mt && !mt->r8stencil_needs_update);
+ mt = mt->r8stencil_mt;
format = BRW_SURFACEFORMAT_R8_UINT;
}
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Mesa (master): main: Add MESA_VERBOSE=api support for glClearStencil
Module: Mesa
Branch: master
Commit: 861c9cbee3d741ea332a9ceee8ae64db49f114c2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=861c9cbee3d741ea332a9ceee8ae64db49f114c2
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sat Jun 11 16:23:44 2016 -0700
main: Add MESA_VERBOSE=api support for glClearStencil
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
---
src/mesa/main/stencil.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/main/stencil.c b/src/mesa/main/stencil.c
index 409b2f0..b303bb7 100644
--- a/src/mesa/main/stencil.c
+++ b/src/mesa/main/stencil.c
@@ -109,6 +109,9 @@ _mesa_ClearStencil( GLint s )
{
GET_CURRENT_CONTEXT(ctx);
+ if (MESA_VERBOSE & VERBOSE_API)
+ _mesa_debug(ctx, "glClearStencil(%d)\n", s);
+
ctx->Stencil.Clear = (GLuint) s;
}
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Mesa (master): i965/hsw: Adjust uploading default color for stencil surfaces
Module: Mesa
Branch: master
Commit: b82bb98441609579c753351295a9f5317b572604
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b82bb98441609579c753351295a9f5317b572604
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Mon Aug 22 22:47:50 2016 -0700
i965/hsw: Adjust uploading default color for stencil surfaces
v2:
* has_component (Ken); const bits_per_channel (Topi)
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
---
src/mesa/drivers/dri/i965/brw_sampler_state.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c
b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index 9f56c81..0eed8f9 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -196,6 +196,16 @@ wrap_mode_needs_border_color(unsigned wrap_mode)
wrap_mode == GEN8_TEXCOORDMODE_HALF_BORDER;
}
+static bool
+has_component(mesa_format format, int i)
+{
+ if (_mesa_is_format_color_format(format))
+ return _mesa_format_has_color_component(format, i);
+
+ /* depth and stencil have only one component */
+ return i == 0;
+}
+
/**
* Upload SAMPLER_BORDER_COLOR_STATE.
*/
@@ -281,7 +291,10 @@ upload_default_color(struct brw_context *brw,
memset(sdc, 0, 20 * 4);
sdc = [16];
- int bits_per_channel = _mesa_get_format_bits(format, GL_RED_BITS);
+ const int bits_per_channel =
+ _mesa_get_format_bits(format,
+ format == MESA_FORMAT_S_UINT8 ?
+ GL_STENCIL_BITS : GL_RED_BITS);
/* From the Haswell PRM, "Command Reference: Structures", Page 36:
* "If any color channel is missing from the surface format,
@@ -291,7 +304,7 @@ upload_default_color(struct brw_context *brw,
*/
unsigned c[4] = { 0, 0, 0, 1 };
for (int i = 0; i < 4; i++) {
- if (_mesa_format_has_color_component(format, i))
+ if (has_component(format, i))
c[i] = color.ui[i];
}
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Mesa (master): i965: Add function to copy a stencil miptree to an R8_UINT miptree
Module: Mesa
Branch: master
Commit: 7af51b8f0359131dbb11cf64c54638029aebad84
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7af51b8f0359131dbb11cf64c54638029aebad84
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sat Jun 11 16:44:27 2016 -0700
i965: Add function to copy a stencil miptree to an R8_UINT miptree
v2:
* Cleanups suggested by Ian, Matt and Topi
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 57 ++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 4 ++
2 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index d4f6c34..c33d8fc 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -674,7 +674,6 @@ miptree_create(struct brw_context *brw,
etc_format = (format != tex_format) ? tex_format : MESA_FORMAT_NONE;
- assert((layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) == 0);
assert((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0);
mt = intel_miptree_create_layout(brw, target, format,
first_level, last_level, width0,
@@ -2286,6 +2285,62 @@ intel_miptree_updownsample(struct brw_context *brw,
}
}
+void
+intel_update_r8stencil(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+ assert(brw->gen >= 7);
+ struct intel_mipmap_tree *src =
+ mt->format == MESA_FORMAT_S_UINT8 ? mt : mt->stencil_mt;
+ if (!src || brw->gen >= 8 || !src->r8stencil_needs_update)
+ return;
+
+ if (!mt->r8stencil_mt) {
+ const uint32_t r8stencil_flags =
+ MIPTREE_LAYOUT_ACCELERATED_UPLOAD | MIPTREE_LAYOUT_TILING_Y |
+ MIPTREE_LAYOUT_DISABLE_AUX;
+ assert(brw->gen > 6); /* Handle MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD */
+ mt->r8stencil_mt = intel_miptree_create(brw,
+ src->target,
+ MESA_FORMAT_R_UINT8,
+ src->first_level,
+ src->last_level,
+ src->logical_width0,
+ src->logical_height0,
+ src->logical_depth0,
+ src->num_samples,
+ r8stencil_flags);
+ assert(mt->r8stencil_mt);
+ }
+
+ struct intel_mipmap_tree *dst = mt->r8stencil_mt;
+
+ for (int level = src->first_level; level <= src->last_level; level++) {
+ const unsigned depth = src->level[level].depth;
+ const int layers_per_blit =
+ (dst->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
+ dst->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ?
+ dst->num_samples : 1;
+
+ for (unsigned layer = 0; layer < depth; layer++) {
+ brw_blorp_blit_miptrees(brw,
+ src, level, layer,
+ src->format, SWIZZLE_X,
+ dst, level, layers_per_blit * layer,
+ MESA_FORMAT_R_UNORM8,
+ 0, 0,
+ src->logical_width0, src->logical_height0,
+ 0, 0,
+ dst->logical_width0, dst->logical_height0,
+ GL_NEAREST, false, false /*mirror x, y*/,
+ false, false /* decode/encode srgb */);
+ }
+ }
+
+ brw_render_cache_set_check_flush(brw, dst->bo);
+ src->r8stencil_needs_update = false;
+}
+
static void *
intel_miptree_map_raw(struct brw_context *brw, struct intel_mipmap_tree *mt)
{
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 4473126..e7d4de0 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -974,6 +974,10 @@ intel_miptree_updownsample(struct brw_context *brw,
struct intel_mipmap_tree *src,
struct intel_mipmap_tree *dst);
+void
+intel_update_r8stencil(struct brw_context *brw,
+ struct intel_mipmap_tree *mt);
+
/**
* Horizontal distance from one slice to the next in the two-dimensional
* miptree layout.
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Mesa (master): i965: Track that the stencil data was updated when clearing
Module: Mesa
Branch: master
Commit: 7bd87c1e6e168b048cdf2318af8848d07caa6706
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7bd87c1e6e168b048cdf2318af8848d07caa6706
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sat Jun 11 16:27:48 2016 -0700
i965: Track that the stencil data was updated when clearing
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_clear.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
b/src/mesa/drivers/dri/i965/brw_clear.c
index 1dfff09..18b8fcb 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -239,6 +239,14 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
}
}
+ if (mask & BUFFER_BIT_STENCIL) {
+ struct intel_renderbuffer *stencil_irb =
+ intel_get_renderbuffer(fb, BUFFER_STENCIL);
+ struct intel_mipmap_tree *mt = stencil_irb->mt;
+ if (mt && mt->stencil_mt)
+ mt->stencil_mt->r8stencil_needs_update = true;
+ }
+
/* BLORP is currently only supported on Gen6+. */
if (brw->gen >= 6 && (mask & BUFFER_BITS_COLOR)) {
const bool encode_srgb = ctx->Color.sRGBEnabled;
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Mesa (master): docs: Update stencil texturing & ES 3.1 status for i965 Haswell
Module: Mesa Branch: master Commit: 7970238fcff37c2450aebaae76e84b5c446d1b46 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7970238fcff37c2450aebaae76e84b5c446d1b46 Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Thu Aug 18 15:05:13 2016 -0700 docs: Update stencil texturing & ES 3.1 status for i965 Haswell Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Ian Romanick <ian.d.roman...@intel.com> --- docs/GL3.txt | 6 +++--- docs/relnotes/12.1.0.html | 3 +++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/docs/GL3.txt b/docs/GL3.txt index 084c17e..5dd9e41 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -180,7 +180,7 @@ GL 4.3, GLSL 4.30 -- all DONE: nvc0, radeonsi GL_ARB_robust_buffer_access_behavior DONE (i965) GL_ARB_shader_image_size DONE (i965, softpipe) GL_ARB_shader_storage_buffer_object DONE (i965, softpipe) - GL_ARB_stencil_texturing DONE (i965/gen8+, nv50, r600, llvmpipe, softpipe, swr) + GL_ARB_stencil_texturing DONE (i965/hsw+, nv50, r600, llvmpipe, softpipe, swr) GL_ARB_texture_buffer_range DONE (nv50, i965, r600, llvmpipe) GL_ARB_texture_query_levels DONE (all drivers that support GLSL 1.30) GL_ARB_texture_storage_multisampleDONE (all drivers that support GL_ARB_texture_multisample) @@ -203,7 +203,7 @@ GL 4.4, GLSL 4.40: GL_ARB_multi_bind DONE (all drivers) GL_ARB_query_buffer_objectDONE (i965/hsw+, nvc0) GL_ARB_texture_mirror_clamp_to_edge DONE (i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr) - GL_ARB_texture_stencil8 DONE (i965/gen8+, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr) + GL_ARB_texture_stencil8 DONE (i965/hsw+, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr) GL_ARB_vertex_type_10f_11f_11f_revDONE (i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr) GL 4.5, GLSL 4.50: @@ -222,7 +222,7 @@ GL 4.5, GLSL 4.50: GL_EXT_shader_integer_mix DONE (all drivers that support GLSL) These are the extensions cherry-picked to make GLES 3.1 -GLES3.1, GLSL ES 3.1 -- all DONE: i965/gen8+, nvc0, radeonsi +GLES3.1, GLSL ES 3.1 -- all DONE: i965/hsw+, nvc0, radeonsi GL_ARB_arrays_of_arrays DONE (all drivers that support GLSL 1.30) GL_ARB_compute_shader DONE (i965/gen7+, softpipe) diff --git a/docs/relnotes/12.1.0.html b/docs/relnotes/12.1.0.html index 5181fa0..2643a0c 100644 --- a/docs/relnotes/12.1.0.html +++ b/docs/relnotes/12.1.0.html @@ -53,6 +53,9 @@ Note: some of the new features are only available with certain drivers. GL_EXT_window_rectangles on nv50, nvc0 GL_KHR_texture_compression_astc_sliced_3d on i965 GL_OES_copy_image on nv50, nvc0, r600, radeonsi, softpipe, llvmpipe +GL_ARB_stencil_texturing on i965/hsw +GL_ARB_texture_stencil8 on i965/hsw +OpenGL ES 3.1 on i965/hsw Bug fixes ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Enable ARB_texture_stencil8 for Haswell
Module: Mesa
Branch: master
Commit: 116b6e12d4d6f08d1c86475f5a2655d074804d6f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=116b6e12d4d6f08d1c86475f5a2655d074804d6f
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Tue Jun 14 15:57:49 2016 -0700
i965: Enable ARB_texture_stencil8 for Haswell
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
---
src/mesa/drivers/dri/i965/intel_extensions.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index be004a2..15009b0 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -375,6 +375,7 @@ intelInitExtensions(struct gl_context *ctx)
if (brw->gen >= 8 || brw->is_haswell) {
ctx->Extensions.ARB_stencil_texturing = true;
+ ctx->Extensions.ARB_texture_stencil8 = true;
}
if (brw->gen >= 8 || brw->is_haswell || brw->is_baytrail) {
@@ -395,7 +396,6 @@ intelInitExtensions(struct gl_context *ctx)
if (brw->gen >= 8) {
ctx->Extensions.ARB_shader_precision = true;
- ctx->Extensions.ARB_texture_stencil8 = true;
ctx->Extensions.ARB_gpu_shader_fp64 = true;
ctx->Extensions.ARB_vertex_attrib_64bit = true;
ctx->Extensions.OES_shader_io_blocks = true;
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Mesa (master): i965/gen7: Add R8_UINT stencil miptree copy for sampling
Module: Mesa
Branch: master
Commit: 2a9c65a01d133fe196fd6e40affb431295d0b9cc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a9c65a01d133fe196fd6e40affb431295d0b9cc
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sat Jun 11 16:21:36 2016 -0700
i965/gen7: Add R8_UINT stencil miptree copy for sampling
For gen < 8, we can't sample from the stencil buffer, which is
required for the ARB_stencil_texturing extension. We'll make a copy of
the stencil data into a new texture that we can sample using the
R8_UINT surface type.
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 12
2 files changed, 14 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 5fe6e47..d4f6c34 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -534,6 +534,7 @@ intel_miptree_create_layout(struct brw_context *brw,
intel_miptree_release();
return NULL;
}
+ mt->stencil_mt->r8stencil_needs_update = true;
/* Fix up the Z miptree format for how we're splitting out separate
* stencil. Gen7 expects there to be no stencil bits in its depth
buffer.
@@ -997,6 +998,7 @@ intel_miptree_release(struct intel_mipmap_tree **mt)
drm_intel_bo_unreference((*mt)->bo);
intel_miptree_release(&(*mt)->stencil_mt);
+ intel_miptree_release(&(*mt)->r8stencil_mt);
if ((*mt)->hiz_buf) {
if ((*mt)->hiz_buf->mt)
intel_miptree_release(&(*mt)->hiz_buf->mt);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index a49da8c..4473126 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -615,6 +615,18 @@ struct intel_mipmap_tree
struct intel_mipmap_tree *stencil_mt;
/**
+* \brief Stencil texturing miptree for sampling from a stencil texture
+*
+* Some hardware doesn't support sampling from the stencil texture as
+* required by the GL_ARB_stencil_texturing extenion. To workaround this we
+* blit the texture into a new texture that can be sampled.
+*
+* \see intel_update_r8stencil()
+*/
+ struct intel_mipmap_tree *r8stencil_mt;
+ bool r8stencil_needs_update;
+
+ /**
* \brief MCS miptree.
*
* This miptree contains the "multisample control surface", which stores
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Mesa (master): i965: Enable OpenGLES 3.1 for Haswell
Module: Mesa Branch: master Commit: 93f5eb7ae75b68d1091c725912e576d533e91b2d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=93f5eb7ae75b68d1091c725912e576d533e91b2d Author: Jordan Justen <jordan.l.jus...@intel.com> Date: Wed Jun 8 13:17:41 2016 -0700 i965: Enable OpenGLES 3.1 for Haswell Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> Reviewed-by: Ian Romanick <ian.d.roman...@intel.com> --- src/mesa/drivers/dri/i965/intel_screen.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index cb007d7..84977a7 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -1432,6 +1432,11 @@ set_max_gl_versions(struct intel_screen *screen) psp->max_gl_es2_version = 31; break; case 7: + psp->max_gl_core_version = 33; + psp->max_gl_compat_version = 30; + psp->max_gl_es1_version = 11; + psp->max_gl_es2_version = screen->devinfo->is_haswell ? 31 : 30; + break; case 6: psp->max_gl_core_version = 33; psp->max_gl_compat_version = 30; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Fix assert with multisampling and cubemaps
Module: Mesa
Branch: master
Commit: 91627d1956a7e82a5821500a0bca537ffd6e5157
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=91627d1956a7e82a5821500a0bca537ffd6e5157
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Tue Aug 23 21:46:58 2016 -0700
i965: Fix assert with multisampling and cubemaps
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index e7aa631..5fe6e47 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -384,6 +384,7 @@ intel_miptree_create_layout(struct brw_context *brw,
mt->msaa_layout = INTEL_MSAA_LAYOUT_NONE;
mt->refcount = 1;
+ int depth_multiply = 1;
if (num_samples > 1) {
/* Adjust width/height/depth for MSAA */
mt->msaa_layout = compute_msaa_layout(brw, format,
@@ -470,7 +471,8 @@ intel_miptree_create_layout(struct brw_context *brw,
}
} else {
/* Non-interleaved */
- depth0 *= num_samples;
+ depth_multiply = num_samples;
+ depth0 *= depth_multiply;
}
}
@@ -500,7 +502,7 @@ intel_miptree_create_layout(struct brw_context *brw,
}
if (target == GL_TEXTURE_CUBE_MAP)
- assert(depth0 == 6);
+ assert(depth0 == 6 * depth_multiply);
mt->physical_width0 = width0;
mt->physical_height0 = height0;
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Mesa (master): i965: Track that the stencil data was updated when rendering
Module: Mesa
Branch: master
Commit: 101b56bab26d13691cde877075fb13554ac780f9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=101b56bab26d13691cde877075fb13554ac780f9
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sat Jun 11 16:29:36 2016 -0700
i965: Track that the stencil data was updated when rendering
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/gen7_misc_state.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index ffdf6f2..271d962 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -166,6 +166,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
+ stencil_mt->r8stencil_needs_update = true;
const int enabled = brw->is_haswell ? HSW_STENCIL_ENABLED : 0;
BEGIN_BATCH(3);
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Mesa (master): i965: Track that the stencil data was updated when using Tex*Image
Module: Mesa
Branch: master
Commit: c8194dc737464d19521c948aa555d936f47f381a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c8194dc737464d19521c948aa555d936f47f381a
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Wed Jul 6 15:50:34 2016 -0700
i965: Track that the stencil data was updated when using Tex*Image
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/intel_tex_image.c| 3 +++
src/mesa/drivers/dri/i965/intel_tex_subimage.c | 7 +--
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 958f8bd..7affe08 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -108,6 +108,9 @@ intelTexImage(struct gl_context * ctx,
assert(intelImage->mt);
+ if (intelImage->mt->format == MESA_FORMAT_S_UINT8)
+ intelImage->mt->r8stencil_needs_update = true;
+
ok = _mesa_meta_pbo_TexSubImage(ctx, dims, texImage, 0, 0, 0,
texImage->Width, texImage->Height,
texImage->Depth,
diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
index 9561968..74d4c57 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
@@ -199,10 +199,13 @@ intelTexSubImage(struct gl_context * ctx,
const GLvoid * pixels,
const struct gl_pixelstore_attrib *packing)
{
- struct intel_texture_image *intelImage = intel_texture_image(texImage);
+ struct intel_mipmap_tree *mt = intel_texture_image(texImage)->mt;
bool ok;
- bool tex_busy = intelImage->mt && drm_intel_bo_busy(intelImage->mt->bo);
+ bool tex_busy = mt && drm_intel_bo_busy(mt->bo);
+
+ if (mt && mt->format == MESA_FORMAT_S_UINT8)
+ mt->r8stencil_needs_update = true;
DBG("%s mesa_format %s target %s format %s type %s level %d %dx%dx%d\n",
__func__, _mesa_get_format_name(texImage->TexFormat),
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Mesa (master): i965/gen7: Copy stencil when sampling the stencil texture
Module: Mesa
Branch: master
Commit: 8d78b096f8bbcad5e15000539ee475a8733140ca
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d78b096f8bbcad5e15000539ee475a8733140ca
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sat Jun 11 16:46:13 2016 -0700
i965/gen7: Copy stencil when sampling the stencil texture
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
---
src/mesa/drivers/dri/i965/brw_context.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 58cd03d..888097d 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -235,6 +235,11 @@ intel_update_state(struct gl_context * ctx, GLuint
new_state)
0 : INTEL_MIPTREE_IGNORE_CCS_E;
intel_miptree_resolve_color(brw, tex_obj->mt, flags);
brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
+
+ if (tex_obj->base.StencilSampling ||
+ tex_obj->mt->format == MESA_FORMAT_S_UINT8) {
+ intel_update_r8stencil(brw, tex_obj->mt);
+ }
}
/* Resolve color for each active shader image. */
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Mesa (master): main: Add MESA_VERBOSE=api support for glTexImage
Module: Mesa
Branch: master
Commit: 9a1f950bef862776cb81255b442be0a7e64cb5dd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a1f950bef862776cb81255b442be0a7e64cb5dd
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Fri Jul 15 18:03:29 2016 -0700
main: Add MESA_VERBOSE=api support for glTexImage
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
---
src/mesa/main/teximage.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 8869b3d..efde114 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -5341,6 +5341,11 @@ texture_image_multisample(struct gl_context *ctx, GLuint
dims,
GLenum sample_count_error;
bool dsa = strstr(func, "ture") ? true : false;
+ if (MESA_VERBOSE & (VERBOSE_API|VERBOSE_TEXTURE)) {
+ _mesa_debug(ctx, "%s(target=%s, samples=%d)\n", func,
+ _mesa_enum_to_string(target), samples);
+ }
+
if (!((ctx->Extensions.ARB_texture_multisample
&& _mesa_is_desktop_gl(ctx))) && !_mesa_is_gles31(ctx)) {
_mesa_error(ctx, GL_INVALID_OPERATION, "%s(unsupported)", func);
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Mesa (master): i965: Use miptree to decide format on multi-plane images for gen < 7
Module: Mesa
Branch: master
Commit: 367cf3a2e3e51466429a6446ef14ed398a5fb948
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=367cf3a2e3e51466429a6446ef14ed398a5fb948
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sat Jun 11 18:16:47 2016 -0700
i965: Use miptree to decide format on multi-plane images for gen < 7
This wasn't handled correctly for multi-plane images on gen < 7 in
727a9b24933d384f5440ed4318fb720ed11d6dd1.
Reported-by: Mark Janes <mark.a.ja...@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96674
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Cc: "12.0" <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index d241ec9..eed16ac 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -316,7 +316,8 @@ brw_update_texture_surface(struct gl_context *ctx,
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
6 * 4, 32, surf_offset);
- uint32_t tex_format = translate_tex_format(brw, intelObj->_Format,
+ mesa_format mesa_fmt = plane == 0 ? intelObj->_Format : mt->format;
+ uint32_t tex_format = translate_tex_format(brw, mesa_fmt,
sampler->sRGBDecode);
if (for_gather) {
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Mesa (master): i965: Skip update_texture_surface when the plane doesn' t exist
Module: Mesa
Branch: master
Commit: 727a9b24933d384f5440ed4318fb720ed11d6dd1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=727a9b24933d384f5440ed4318fb720ed11d6dd1
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sat Jun 11 18:16:47 2016 -0700
i965: Skip update_texture_surface when the plane doesn't exist
Reported-by: Grazvydas Ignotas <nota...@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96607
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Kristian Høgsberg <k...@bitplanet.net>
Cc: "12.0" <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Chad Versace <chad.vers...@intel.com>
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 15 ++-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 21 ++---
src/mesa/drivers/dri/i965/gen8_surface_state.c| 19 ++-
3 files changed, 26 insertions(+), 29 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index cfce2c9..d241ec9 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -307,21 +307,18 @@ brw_update_texture_surface(struct gl_context *ctx,
return;
}
+ if (plane > 0) {
+ if (mt->plane[plane - 1] == NULL)
+ return;
+ mt = mt->plane[plane - 1];
+ }
+
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
6 * 4, 32, surf_offset);
uint32_t tex_format = translate_tex_format(brw, intelObj->_Format,
sampler->sRGBDecode);
- if (tObj->Target == GL_TEXTURE_EXTERNAL_OES) {
- if (plane > 0)
- mt = mt->plane[plane - 1];
- if (mt == NULL)
- return;
-
- tex_format = translate_tex_format(brw, mt->format, sampler->sRGBDecode);
- }
-
if (for_gather) {
/* Sandybridge's gather4 message is broken for integer formats.
* To work around this, we pretend the surface is UNORM for
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 2a7ae31..932e62e 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -365,6 +365,13 @@ gen7_update_texture_surface(struct gl_context *ctx,
} else {
struct intel_texture_object *intel_obj = intel_texture_object(obj);
struct intel_mipmap_tree *mt = intel_obj->mt;
+
+ if (plane > 0) {
+ if (mt->plane[plane - 1] == NULL)
+return;
+ mt = mt->plane[plane - 1];
+ }
+
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
/* If this is a view with restricted NumLayers, then our effective depth
* is not just the miptree depth.
@@ -383,17 +390,9 @@ gen7_update_texture_surface(struct gl_context *ctx,
const unsigned swizzle = (unlikely(alpha_depth) ? SWIZZLE_XYZW :
brw_get_texture_swizzle(>ctx, obj));
- unsigned format = translate_tex_format(
- brw, intel_obj->_Format, sampler->sRGBDecode);
-
- if (obj->Target == GL_TEXTURE_EXTERNAL_OES) {
- if (plane > 0)
-mt = mt->plane[plane - 1];
- if (mt == NULL)
-return;
-
- format = translate_tex_format(brw, mt->format, sampler->sRGBDecode);
- }
+ mesa_format mesa_fmt = plane == 0 ? intel_obj->_Format : mt->format;
+ unsigned format = translate_tex_format(brw, mesa_fmt,
+ sampler->sRGBDecode);
if (for_gather && format == BRW_SURFACEFORMAT_R32G32_FLOAT)
format = BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index f4375ea..bd9e2a1 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -374,6 +374,13 @@ gen8_update_texture_surface(struct gl_context *ctx,
struct gl_texture_image *firstImage = obj->Image[0][obj->BaseLevel];
struct intel_texture_object *intel_obj = intel_texture_object(obj);
struct intel_mipmap_tree *mt = intel_obj->mt;
+
+ if (plane > 0) {
+ if (mt->plane[plane - 1] == NULL)
+return;
+ mt = mt->plane[plane - 1];
+ }
+
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
/* If this is a view with restricted NumLayers, then our effective depth
* is not just the miptree depth.
@@ -391,19 +398,13 @@ gen8_update_texture_surface(struct gl_context *ctx,
const unsigned swizzle = (unlikely(alpha_depth) ? SWIZZLE_XYZW :
brw_get_texture_swizzle(>ctx, obj)
Mesa (master): i965: Preserve the internal format of the dri image
Module: Mesa
Branch: master
Commit: c36a363a2d305a987ef2ea843fe9fc860b576eed
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c36a363a2d305a987ef2ea843fe9fc860b576eed
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Wed Jun 22 17:34:08 2016 +
i965: Preserve the internal format of the dri image
Since the OpenGLES API is strict about the internal format matching
the for many operations, we need to preserve it.
See _mesa_es3_error_check_format_and_type in
src/mesa/main/glformats.c.
Fixes ES2-CTS.gtf.GL2ExtensionTests.egl_image.egl_image
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96351
Reported-by: Mark Janes <mark.a.ja...@intel.com>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Kristian Høgsberg <k...@bitplanet.net>
Cc: Chad Versace <chad.vers...@intel.com>
Cc: "12.0" <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Chad Versace <chad.vers...@intel.com>
---
src/mesa/drivers/dri/i965/intel_tex_image.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 9cc426c..958f8bd 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -138,10 +138,10 @@ intelTexImage(struct gl_context * ctx,
static void
intel_set_texture_image_mt(struct brw_context *brw,
struct gl_texture_image *image,
+ GLenum internal_format,
struct intel_mipmap_tree *mt)
{
- const uint32_t internal_format = _mesa_get_format_base_format(mt->format);
struct gl_texture_object *texobj = image->TexObject;
struct intel_texture_object *intel_texobj = intel_texture_object(texobj);
struct intel_texture_image *intel_image = intel_texture_image(image);
@@ -264,6 +264,7 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
struct gl_texture_image *texImage;
mesa_format texFormat = MESA_FORMAT_NONE;
struct intel_mipmap_tree *mt;
+ GLenum internal_format = 0;
texObj = _mesa_get_current_tex_object(ctx, target);
@@ -283,12 +284,15 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
if (rb->mt->cpp == 4) {
if (texture_format == __DRI_TEXTURE_FORMAT_RGB) {
+ internal_format = GL_RGB;
texFormat = MESA_FORMAT_B8G8R8X8_UNORM;
}
else {
+ internal_format = GL_RGBA;
texFormat = MESA_FORMAT_B8G8R8A8_UNORM;
}
} else if (rb->mt->cpp == 2) {
+ internal_format = GL_RGB;
texFormat = MESA_FORMAT_B5G6R5_UNORM;
}
@@ -305,7 +309,7 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
_mesa_lock_texture(>ctx, texObj);
texImage = _mesa_get_tex_image(ctx, texObj, target, 0);
- intel_set_texture_image_mt(brw, texImage, mt);
+ intel_set_texture_image_mt(brw, texImage, internal_format, mt);
intel_miptree_release();
_mesa_unlock_texture(>ctx, texObj);
}
@@ -399,7 +403,10 @@ intel_image_target_texture_2d(struct gl_context *ctx,
GLenum target,
struct intel_texture_object *intel_texobj = intel_texture_object(texObj);
intel_texobj->planar_format = image->planar_format;
- intel_set_texture_image_mt(brw, texImage, mt);
+ const GLenum internal_format =
+ image->internal_format != 0 ?
+ image->internal_format : _mesa_get_format_base_format(mt->format);
+ intel_set_texture_image_mt(brw, texImage, internal_format, mt);
intel_miptree_release();
}
___
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Mesa (master): i965: Enable cross-thread constants and compact local IDs for hsw+
Module: Mesa
Branch: master
Commit: b1f22c6317940dac543e44dd638ea9f4fbcd6ca7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1f22c6317940dac543e44dd638ea9f4fbcd6ca7
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Tue May 31 15:45:24 2016 -0700
i965: Enable cross-thread constants and compact local IDs for hsw+
The cross thread constant support appears on Haswell. It allows us to
upload a set of uniform data for all threads without duplicating it
per thread.
One complication is that cross-thread constants are loaded into
registers before per-thread constants. Previously, our local IDs were
loaded before the uniform data and treated as 'payload' data, even
though they were actually pushed into the registers like the other
uniform data.
Therefore, in this patch we simultaneously enable a newer layout where
each thread now uses a single uniform slot for a unique local ID for
the thread. This uniform is handled specially to make sure it is added
last into the uniform push constant registers. This minimizes our
usage of push constant registers, and maximizes our ability to use
cross-thread constants for registers.
To swap from the old to the new layout, we also need to flip some
lowering pass switches to let our driver handle the lowering instead.
We also no longer force thread_local_id_index to -1.
v4:
* Minimize size of patch that switches from the old local ID layout
to the new layout (Jason)
Cc: "12.0" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_compiler.c | 3 +--
src/mesa/drivers/dri/i965/brw_context.c | 1 -
src/mesa/drivers/dri/i965/brw_fs.cpp | 16 +---
3 files changed, 6 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.c
b/src/mesa/drivers/dri/i965/brw_compiler.c
index bb06733..a4855a0 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.c
+++ b/src/mesa/drivers/dri/i965/brw_compiler.c
@@ -40,8 +40,7 @@
.lower_fdiv = true,\
.lower_flrp64 = true, \
.native_integers = true, \
- .vertex_id_zero_based = true, \
- .lower_cs_local_index_from_id = true
+ .vertex_id_zero_based = true
static const struct nir_shader_compiler_options scalar_nir_options = {
COMMON_OPTIONS,
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index ad8d514..97dc226 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -599,7 +599,6 @@ brw_initialize_context_constants(struct brw_context *brw)
ctx->Const.MaxClipPlanes = 8;
ctx->Const.LowerTessLevel = true;
- ctx->Const.LowerCsDerivedVariables = true;
ctx->Const.PrimitiveRestartForPatches = true;
ctx->Const.Program[MESA_SHADER_VERTEX].MaxNativeInstructions = 16 * 1024;
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 4de2563..0b766a4 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -6586,7 +6586,7 @@ cs_fill_push_const_info(const struct brw_device_info
*devinfo,
bool fill_thread_id =
cs_prog_data->thread_local_id_index >= 0 &&
cs_prog_data->thread_local_id_index < (int)prog_data->nr_params;
- bool cross_thread_supported = false; /* Not yet supported by driver. */
+ bool cross_thread_supported = devinfo->gen > 7 || devinfo->is_haswell;
/* The thread ID should be stored in the last param dword */
assert(prog_data->nr_params > 0 || !fill_thread_id);
@@ -6652,19 +6652,13 @@ brw_compile_cs(const struct brw_compiler *compiler,
void *log_data,
brw_nir_lower_cs_shared(shader);
prog_data->base.total_shared += shader->num_shared;
- /* The driver isn't yet ready to support thread_local_id_index, so we force
-* it to disabled for now.
-*/
- prog_data->thread_local_id_index = -1;
-
/* Now that we cloned the nir_shader, we can update num_uniforms based on
* the thread_local_id_index.
*/
- if (prog_data->thread_local_id_index >= 0) {
- shader->num_uniforms =
- MAX2(shader->num_uniforms,
- (unsigned)4 * (prog_data->thread_local_id_index + 1));
- }
+ assert(prog_data->thread_local_id_index >= 0);
+ shader->num_uniforms =
+ MAX2(shader->num_uniforms,
+ (unsigned)4 * (prog_data->thread_local_id_index + 1));
brw_nir_lower_intrinsics(shader, _data->base);
shader = brw_postprocess_nir(shader, compiler->devinfo, true);
___
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Mesa (master): i965: Remove old CS local ID handling
Module: Mesa
Branch: master
Commit: 0a3acff5b53d409181dcd2f31a4a50af06f73a57
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a3acff5b53d409181dcd2f31a4a50af06f73a57
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sun May 22 22:31:06 2016 -0700
i965: Remove old CS local ID handling
The old method pushed data for each channels uvec3 data of
gl_LocalInvocationID.
The new method pushes 1 dword of data that is a 'thread local ID'
value. Based on that value, we can generate gl_LocalInvocationIndex
and gl_LocalInvocationID with some calculations.
Cc: "12.0" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/intel/vulkan/anv_cmd_buffer.c | 5 +-
src/mesa/drivers/dri/i965/brw_compiler.h | 8 ---
src/mesa/drivers/dri/i965/brw_fs.cpp | 94 +-
src/mesa/drivers/dri/i965/brw_fs.h | 1 -
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 7 --
src/mesa/drivers/dri/i965/brw_nir_intrinsics.c | 7 --
src/mesa/drivers/dri/i965/gen7_cs_state.c | 5 +-
7 files changed, 3 insertions(+), 124 deletions(-)
diff --git a/src/intel/vulkan/anv_cmd_buffer.c
b/src/intel/vulkan/anv_cmd_buffer.c
index edaaa3d..3d37de2 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -1094,13 +1094,10 @@ anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer)
}
if (cs_prog_data->push.per_thread.size > 0) {
- brw_cs_fill_local_id_payload(cs_prog_data, u32_map,
cs_prog_data->threads,
- cs_prog_data->push.per_thread.size);
for (unsigned t = 0; t < cs_prog_data->threads; t++) {
unsigned dst =
8 * (cs_prog_data->push.per_thread.regs * t +
- cs_prog_data->push.cross_thread.regs +
- cs_prog_data->local_invocation_id_regs);
+ cs_prog_data->push.cross_thread.regs);
unsigned src = cs_prog_data->push.cross_thread.dwords;
for ( ; src < prog_data->nr_params; src++, dst++) {
if (src != cs_prog_data->thread_local_id_index) {
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h
b/src/mesa/drivers/dri/i965/brw_compiler.h
index dda6297..6e6d20c 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.h
+++ b/src/mesa/drivers/dri/i965/brw_compiler.h
@@ -439,7 +439,6 @@ struct brw_cs_prog_data {
unsigned threads;
bool uses_barrier;
bool uses_num_work_groups;
- unsigned local_invocation_id_regs;
int thread_local_id_index;
struct {
@@ -831,13 +830,6 @@ brw_compile_cs(const struct brw_compiler *compiler, void
*log_data,
unsigned *final_assembly_size,
char **error_str);
-/**
- * Fill out local id payload for compute shader according to cs_prog_data.
- */
-void
-brw_cs_fill_local_id_payload(const struct brw_cs_prog_data *cs_prog_data,
- void *buffer, uint32_t threads, uint32_t stride);
-
#ifdef __cplusplus
} /* extern "C" */
#endif
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 0b766a4..9abe73a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -5581,31 +5581,6 @@ fs_visitor::setup_vs_payload()
payload.num_regs = 2;
}
-/**
- * We are building the local ID push constant data using the simplest possible
- * method. We simply push the local IDs directly as they should appear in the
- * registers for the uvec3 gl_LocalInvocationID variable.
- *
- * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
- * registers worth of push constant space.
- *
- * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
- * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
- * to coordinated.
- *
- * FINISHME: There are a few easy optimizations to consider.
- *
- * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
- *no need for using push constant space for that dimension.
- *
- * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
- *easily use 16-bit words rather than 32-bit dwords in the push constant
- *data.
- *
- * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
- *conveying the data, and thereby reduce push constant usage.
- *
- */
void
fs_visitor::setup_gs_payload()
{
@@ -5649,16 +5624,7 @@ void
fs_visitor::setup_cs_payload()
{
assert(devinfo->gen >= 7);
- brw_cs_prog_data *prog_data = (brw_cs_prog_data*) this->prog_data;
-
payload.num_regs = 1;
-
- if (nir->info.system_values_read & SYSTEM_BIT_LOCAL_INVOCATION_ID &&
- prog_data->thread_local_id_index < 0) {
- prog_data->local_invocation_id_regs =
Mesa (master): anv: Support new local ID generation & cross-thread constants
Module: Mesa
Branch: master
Commit: 3ba9594f32239031ddeff764e9896d48d05125d0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ba9594f32239031ddeff764e9896d48d05125d0
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Fri May 27 00:53:27 2016 -0700
anv: Support new local ID generation & cross-thread constants
The cross thread constant support appears on Haswell. It allows us to
upload a set of uniform data for all threads without duplicating it
per thread.
We also support per-thread data which allows us to store a per-thread
ID in one of the uniforms that can be used to calculate the
gl_LocalInvocationIndex and gl_LocalInvocationID variables.
v4:
* Support the old local ID push constant layout as well (Jason)
Cc: "12.0" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/intel/vulkan/anv_cmd_buffer.c | 54 +-
src/intel/vulkan/gen7_cmd_buffer.c | 13 -
src/intel/vulkan/gen8_cmd_buffer.c | 13 -
src/intel/vulkan/genX_pipeline.c | 10 ++-
4 files changed, 42 insertions(+), 48 deletions(-)
diff --git a/src/intel/vulkan/anv_cmd_buffer.c
b/src/intel/vulkan/anv_cmd_buffer.c
index 63d096c..edaaa3d 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -1065,23 +1065,14 @@ anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer)
const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
const struct brw_stage_prog_data *prog_data = _prog_data->base;
- const unsigned local_id_dwords = cs_prog_data->local_invocation_id_regs * 8;
- const unsigned push_constant_data_size =
- (local_id_dwords + prog_data->nr_params) * 4;
- const unsigned reg_aligned_constant_size = ALIGN(push_constant_data_size,
32);
- const unsigned param_aligned_count =
- reg_aligned_constant_size / sizeof(uint32_t);
-
/* If we don't actually have any push constants, bail. */
- if (reg_aligned_constant_size == 0)
+ if (cs_prog_data->push.total.size == 0)
return (struct anv_state) { .offset = 0 };
- const unsigned total_push_constants_size =
- reg_aligned_constant_size * cs_prog_data->threads;
const unsigned push_constant_alignment =
cmd_buffer->device->info.gen < 8 ? 32 : 64;
const unsigned aligned_total_push_constants_size =
- ALIGN(total_push_constants_size, push_constant_alignment);
+ ALIGN(cs_prog_data->push.total.size, push_constant_alignment);
struct anv_state state =
anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
aligned_total_push_constants_size,
@@ -1090,21 +1081,36 @@ anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer)
/* Walk through the param array and fill the buffer with data */
uint32_t *u32_map = state.map;
- brw_cs_fill_local_id_payload(cs_prog_data, u32_map, cs_prog_data->threads,
-reg_aligned_constant_size);
-
- /* Setup uniform data for the first thread */
- for (unsigned i = 0; i < prog_data->nr_params; i++) {
- uint32_t offset = (uintptr_t)prog_data->param[i];
- u32_map[local_id_dwords + i] = *(uint32_t *)((uint8_t *)data + offset);
+ if (cs_prog_data->push.cross_thread.size > 0) {
+ assert(cs_prog_data->thread_local_id_index < 0 ||
+ cs_prog_data->thread_local_id_index >=
+cs_prog_data->push.cross_thread.dwords);
+ for (unsigned i = 0;
+ i < cs_prog_data->push.cross_thread.dwords;
+ i++) {
+ uint32_t offset = (uintptr_t)prog_data->param[i];
+ u32_map[i] = *(uint32_t *)((uint8_t *)data + offset);
+ }
}
- /* Copy uniform data from the first thread to every other thread */
- const size_t uniform_data_size = prog_data->nr_params * sizeof(uint32_t);
- for (unsigned t = 1; t < cs_prog_data->threads; t++) {
- memcpy(_map[t * param_aligned_count + local_id_dwords],
- _map[local_id_dwords],
- uniform_data_size);
+ if (cs_prog_data->push.per_thread.size > 0) {
+ brw_cs_fill_local_id_payload(cs_prog_data, u32_map,
cs_prog_data->threads,
+ cs_prog_data->push.per_thread.size);
+ for (unsigned t = 0; t < cs_prog_data->threads; t++) {
+ unsigned dst =
+8 * (cs_prog_data->push.per_thread.regs * t +
+ cs_prog_data->push.cross_thread.regs +
+ cs_prog_data->local_invocation_id_regs);
+ unsigned src = cs_prog_data->push.cross_thread.dwords;
+ for ( ; src < prog_data->nr_params; src++, dst++) {
+if (src != cs_prog_data->thread_local_id_index) {
+ uint32_t offset = (uintptr_t)prog_data
Mesa (master): i965: Add CS push constant info to brw_cs_prog_data
Module: Mesa
Branch: master
Commit: d437798ace47e47dbcb1244734dc1af3ecb5ab84
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d437798ace47e47dbcb1244734dc1af3ecb5ab84
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sun May 22 21:46:28 2016 -0700
i965: Add CS push constant info to brw_cs_prog_data
We need information about push constants in a few places for the GL
driver, and another couple places for the vulkan driver.
When we add support for uploading both a common (cross-thread) set of
push constants, combined with the previous per-thread push constant
data, things are going to get even more complicated. To simplify
things, we add push constant info into the cs prog_data struct.
The cross-thread constant support is added as of Haswell. To support
it we need to make sure all push constants with uniform values are
added to earlier registers. The register that varies per thread and
holds the thread invocation's unique local ID needs to be added last.
For now we add the code that would calculate cross-thread constatn
information for hsw+, but we force it (cross_thread_supported) off
until the other parts of the driver support it.
v4:
* Support older local ID push constant layout as well. (Jason)
Cc: "12.0" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_compiler.h | 12 +++
src/mesa/drivers/dri/i965/brw_fs.cpp | 61
2 files changed, 73 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h
b/src/mesa/drivers/dri/i965/brw_compiler.h
index f1f9e56..dda6297 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.h
+++ b/src/mesa/drivers/dri/i965/brw_compiler.h
@@ -424,6 +424,12 @@ struct brw_wm_prog_data {
int urb_setup[VARYING_SLOT_MAX];
};
+struct brw_push_const_block {
+ unsigned dwords; /* Dword count, not reg aligned */
+ unsigned regs;
+ unsigned size; /* Bytes, register aligned */
+};
+
struct brw_cs_prog_data {
struct brw_stage_prog_data base;
@@ -437,6 +443,12 @@ struct brw_cs_prog_data {
int thread_local_id_index;
struct {
+ struct brw_push_const_block cross_thread;
+ struct brw_push_const_block per_thread;
+ struct brw_push_const_block total;
+ } push;
+
+ struct {
/** @{
* surface indices the CS-specific surfaces
*/
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 14b0b42..4de2563 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -6570,6 +6570,64 @@ fs_visitor::emit_cs_work_group_id_setup()
}
static void
+fill_push_const_block_info(struct brw_push_const_block *block, unsigned dwords)
+{
+ block->dwords = dwords;
+ block->regs = DIV_ROUND_UP(dwords, 8);
+ block->size = block->regs * 32;
+}
+
+static void
+cs_fill_push_const_info(const struct brw_device_info *devinfo,
+struct brw_cs_prog_data *cs_prog_data)
+{
+ const struct brw_stage_prog_data *prog_data =
+ (struct brw_stage_prog_data*) cs_prog_data;
+ bool fill_thread_id =
+ cs_prog_data->thread_local_id_index >= 0 &&
+ cs_prog_data->thread_local_id_index < (int)prog_data->nr_params;
+ bool cross_thread_supported = false; /* Not yet supported by driver. */
+
+ /* The thread ID should be stored in the last param dword */
+ assert(prog_data->nr_params > 0 || !fill_thread_id);
+ assert(!fill_thread_id ||
+ cs_prog_data->thread_local_id_index ==
+ (int)prog_data->nr_params - 1);
+
+ unsigned cross_thread_dwords, per_thread_dwords;
+ if (!cross_thread_supported) {
+ cross_thread_dwords = 0u;
+ per_thread_dwords =
+ 8 * cs_prog_data->local_invocation_id_regs +
+ prog_data->nr_params;
+ } else if (fill_thread_id) {
+ /* Fill all but the last register with cross-thread payload */
+ cross_thread_dwords = 8 * (cs_prog_data->thread_local_id_index / 8);
+ per_thread_dwords = prog_data->nr_params - cross_thread_dwords;
+ assert(per_thread_dwords > 0 && per_thread_dwords <= 8);
+ } else {
+ /* Fill all data using cross-thread payload */
+ cross_thread_dwords = prog_data->nr_params;
+ per_thread_dwords = 0u;
+ }
+
+ fill_push_const_block_info(_prog_data->push.cross_thread,
cross_thread_dwords);
+ fill_push_const_block_info(_prog_data->push.per_thread,
per_thread_dwords);
+
+ unsigned total_dwords =
+ (cs_prog_data->push.per_thread.size * cs_prog_data->threads +
+ cs_prog_data->push.cross_thread.size) / 4;
+ fill_push_const_block_info(_prog_data->push.total, total_dwords);
+
+ assert(cs_prog_data->push.cross_thread.dwords % 8 == 0 ||
+ cs_prog_data->push.per_thr
Mesa (master): i965: Add uniform for a CS thread local base ID
Module: Mesa
Branch: master
Commit: fa279dfbf0fc89b07007141ad8850ac42206e397
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa279dfbf0fc89b07007141ad8850ac42206e397
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sat May 28 23:45:21 2016 -0700
i965: Add uniform for a CS thread local base ID
v4:
* Force thread_local_id_index to -1 for now, and have
fs_visitor::setup_cs_payload look at thread_local_id_index. This
enables us to more easily cut over from the old local ID layout to
the new layout, as suggested by Jason.
Cc: "12.0" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/intel/vulkan/anv_pipeline.c | 4
src/mesa/drivers/dri/i965/brw_compiler.h | 1 +
src/mesa/drivers/dri/i965/brw_cs.c | 3 +++
src/mesa/drivers/dri/i965/brw_fs.cpp | 18 +-
4 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 789bc1a..504f0be 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -338,6 +338,10 @@ anv_pipeline_compile(struct anv_pipeline *pipeline,
pipeline->needs_data_cache = true;
}
+ if (stage == MESA_SHADER_COMPUTE)
+ ((struct brw_cs_prog_data *)prog_data)->thread_local_id_index =
+ prog_data->nr_params++; /* The CS Thread ID uniform */
+
if (nir->info.num_ssbos > 0)
pipeline->needs_data_cache = true;
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h
b/src/mesa/drivers/dri/i965/brw_compiler.h
index 0844694..bed969c 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.h
+++ b/src/mesa/drivers/dri/i965/brw_compiler.h
@@ -433,6 +433,7 @@ struct brw_cs_prog_data {
bool uses_barrier;
bool uses_num_work_groups;
unsigned local_invocation_id_regs;
+ int thread_local_id_index;
struct {
/** @{
diff --git a/src/mesa/drivers/dri/i965/brw_cs.c
b/src/mesa/drivers/dri/i965/brw_cs.c
index a9cbde9..2a25584 100644
--- a/src/mesa/drivers/dri/i965/brw_cs.c
+++ b/src/mesa/drivers/dri/i965/brw_cs.c
@@ -93,6 +93,9 @@ brw_codegen_cs_prog(struct brw_context *brw,
*/
int param_count = cp->program.Base.nir->num_uniforms / 4;
+ /* The backend also sometimes add a param for the thread local id. */
+ prog_data.thread_local_id_index = param_count++;
+
/* The backend also sometimes adds params for texture size. */
param_count += 2 *
ctx->Const.Program[MESA_SHADER_COMPUTE].MaxTextureImageUnits;
prog_data.base.param =
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index bd026de..645f2c7 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -5629,7 +5629,8 @@ fs_visitor::setup_cs_payload()
payload.num_regs = 1;
- if (nir->info.system_values_read & SYSTEM_BIT_LOCAL_INVOCATION_ID) {
+ if (nir->info.system_values_read & SYSTEM_BIT_LOCAL_INVOCATION_ID &&
+ prog_data->thread_local_id_index < 0) {
prog_data->local_invocation_id_regs = dispatch_width * 3 / 8;
payload.local_invocation_id_reg = payload.num_regs;
payload.num_regs += prog_data->local_invocation_id_regs;
@@ -6559,6 +6560,21 @@ brw_compile_cs(const struct brw_compiler *compiler, void
*log_data,
true);
brw_nir_lower_cs_shared(shader);
prog_data->base.total_shared += shader->num_shared;
+
+ /* The driver isn't yet ready to support thread_local_id_index, so we force
+* it to disabled for now.
+*/
+ prog_data->thread_local_id_index = -1;
+
+ /* Now that we cloned the nir_shader, we can update num_uniforms based on
+* the thread_local_id_index.
+*/
+ if (prog_data->thread_local_id_index >= 0) {
+ shader->num_uniforms =
+ MAX2(shader->num_uniforms,
+ (unsigned)4 * (prog_data->thread_local_id_index + 1));
+ }
+
shader = brw_postprocess_nir(shader, compiler->devinfo, true);
prog_data->local_size[0] = shader->info.cs.local_size[0];
___
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mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl: Add glsl LowerCsDerivedVariables option
Module: Mesa
Branch: master
Commit: 7b9def35835232a10010f256b9c108219f97f752
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b9def35835232a10010f256b9c108219f97f752
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sat May 21 14:21:32 2016 -0700
glsl: Add glsl LowerCsDerivedVariables option
v2:
* Move lower flag to context constants. (Ken)
Cc: "12.0" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> (v1)
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/compiler/glsl/builtin_variables.cpp | 29 ++---
src/compiler/glsl/glsl_parser_extras.cpp | 2 +-
src/compiler/glsl/ir.h | 3 ++-
src/mesa/drivers/dri/i965/brw_context.c | 1 +
src/mesa/main/mtypes.h | 3 +++
src/mesa/state_tracker/st_extensions.c | 1 +
6 files changed, 26 insertions(+), 13 deletions(-)
diff --git a/src/compiler/glsl/builtin_variables.cpp
b/src/compiler/glsl/builtin_variables.cpp
index 401c713..05b3b0b 100644
--- a/src/compiler/glsl/builtin_variables.cpp
+++ b/src/compiler/glsl/builtin_variables.cpp
@@ -1201,8 +1201,15 @@ builtin_variable_generator::generate_cs_special_vars()
"gl_LocalInvocationID");
add_system_value(SYSTEM_VALUE_WORK_GROUP_ID, uvec3_t, "gl_WorkGroupID");
add_system_value(SYSTEM_VALUE_NUM_WORK_GROUPS, uvec3_t, "gl_NumWorkGroups");
- add_variable("gl_GlobalInvocationID", uvec3_t, ir_var_auto, 0);
- add_variable("gl_LocalInvocationIndex", uint_t, ir_var_auto, 0);
+ if (state->ctx->Const.LowerCsDerivedVariables) {
+ add_variable("gl_GlobalInvocationID", uvec3_t, ir_var_auto, 0);
+ add_variable("gl_LocalInvocationIndex", uint_t, ir_var_auto, 0);
+ } else {
+ add_system_value(SYSTEM_VALUE_GLOBAL_INVOCATION_ID,
+ uvec3_t, "gl_GlobalInvocationID");
+ add_system_value(SYSTEM_VALUE_LOCAL_INVOCATION_INDEX,
+ uint_t, "gl_LocalInvocationIndex");
+ }
}
@@ -1431,16 +1438,16 @@ initialize_cs_derived_variables(gl_shader *shader,
* These are initialized in the main function.
*/
void
-_mesa_glsl_initialize_derived_variables(gl_shader *shader)
+_mesa_glsl_initialize_derived_variables(struct gl_context *ctx,
+gl_shader *shader)
{
/* We only need to set CS variables currently. */
- if (shader->Stage != MESA_SHADER_COMPUTE)
- return;
+ if (shader->Stage == MESA_SHADER_COMPUTE &&
+ ctx->Const.LowerCsDerivedVariables) {
+ ir_function_signature *const main_sig =
+ _mesa_get_main_function_signature(shader);
- ir_function_signature *const main_sig =
- _mesa_get_main_function_signature(shader);
- if (main_sig == NULL)
- return;
-
- initialize_cs_derived_variables(shader, main_sig);
+ if (main_sig != NULL)
+ initialize_cs_derived_variables(shader, main_sig);
+ }
}
diff --git a/src/compiler/glsl/glsl_parser_extras.cpp
b/src/compiler/glsl/glsl_parser_extras.cpp
index 2e3395e..c9654ac 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -1907,7 +1907,7 @@ _mesa_glsl_compile_shader(struct gl_context *ctx, struct
gl_shader *shader,
}
}
- _mesa_glsl_initialize_derived_variables(shader);
+ _mesa_glsl_initialize_derived_variables(ctx, shader);
delete state->symbols;
ralloc_free(state);
diff --git a/src/compiler/glsl/ir.h b/src/compiler/glsl/ir.h
index e8efd27..93716c4 100644
--- a/src/compiler/glsl/ir.h
+++ b/src/compiler/glsl/ir.h
@@ -2562,7 +2562,8 @@ _mesa_glsl_initialize_variables(exec_list *instructions,
struct _mesa_glsl_parse_state *state);
extern void
-_mesa_glsl_initialize_derived_variables(gl_shader *shader);
+_mesa_glsl_initialize_derived_variables(struct gl_context *ctx,
+gl_shader *shader);
extern void
_mesa_glsl_initialize_functions(_mesa_glsl_parse_state *state);
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 97dc226..ad8d514 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -599,6 +599,7 @@ brw_initialize_context_constants(struct brw_context *brw)
ctx->Const.MaxClipPlanes = 8;
ctx->Const.LowerTessLevel = true;
+ ctx->Const.LowerCsDerivedVariables = true;
ctx->Const.PrimitiveRestartForPatches = true;
ctx->Const.Program[MESA_SHADER_VERTEX].MaxNativeInstructions = 16 * 1024;
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 2233526..d0f3760 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -3763,6 +3763,9 @@ struct gl_constant
Mesa (master): i965: Add nir based intrinsic lowering and thread ID uniform
Module: Mesa
Branch: master
Commit: 3ef0957dac11edee7babc9746ec766dcb055d909
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ef0957dac11edee7babc9746ec766dcb055d909
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sun May 22 00:08:06 2016 -0700
i965: Add nir based intrinsic lowering and thread ID uniform
We add a lowering pass for nir intrinsics. This pass can replace nir
intrinsics with driver specific nir lower code.
We lower the gl_LocalInvocationIndex intrinsic based on a uniform
which is loaded with a thread specific ID.
We also lower the gl_LocalInvocationID based on
gl_LocalInvocationIndex.
v2:
* Create variable during lowering pass. (Ken)
v3:
* Don't create a variable, but instead just insert an intrisic call
to load a uniform from the allocated location. (Jason)
v4:
* Don't run this pass if thread_local_id_index < 0
Cc: "12.0" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +
src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
src/mesa/drivers/dri/i965/brw_nir.h| 2 +
src/mesa/drivers/dri/i965/brw_nir_intrinsics.c | 186 +
4 files changed, 190 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
b/src/mesa/drivers/dri/i965/Makefile.sources
index d8711ed..f448551 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -46,6 +46,7 @@ i965_compiler_FILES = \
brw_nir.c \
brw_nir_analyze_boolean_resolves.c \
brw_nir_attribute_workarounds.c \
+ brw_nir_intrinsics.c \
brw_nir_opt_peephole_ffma.c \
brw_packed_float.c \
brw_predicated_break.cpp \
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 6bd2871..975ac9e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -6599,6 +6599,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void
*log_data,
(unsigned)4 * (prog_data->thread_local_id_index + 1));
}
+ brw_nir_lower_intrinsics(shader, _data->base);
shader = brw_postprocess_nir(shader, compiler->devinfo, true);
prog_data->local_size[0] = shader->info.cs.local_size[0];
diff --git a/src/mesa/drivers/dri/i965/brw_nir.h
b/src/mesa/drivers/dri/i965/brw_nir.h
index 409e49a..74c354f 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.h
+++ b/src/mesa/drivers/dri/i965/brw_nir.h
@@ -91,6 +91,8 @@ void brw_nir_analyze_boolean_resolves(nir_shader *nir);
nir_shader *brw_preprocess_nir(const struct brw_compiler *compiler,
nir_shader *nir);
+bool brw_nir_lower_intrinsics(nir_shader *nir,
+ struct brw_stage_prog_data *prog_data);
void brw_nir_lower_vs_inputs(nir_shader *nir,
const struct brw_device_info *devinfo,
bool is_scalar,
diff --git a/src/mesa/drivers/dri/i965/brw_nir_intrinsics.c
b/src/mesa/drivers/dri/i965/brw_nir_intrinsics.c
new file mode 100644
index 000..972b117
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_nir_intrinsics.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "brw_nir.h"
+#include "compiler/nir/nir_builder.h"
+
+struct lower_intrinsics_state {
+ nir_shader *nir;
+ union {
+ struct brw_stage_prog_data *prog_data;
+ struct brw_cs_prog_data *cs_prog_data;
+ };
+ nir_function_impl *impl;
+ bool progress;
+ nir_builder builder;
+ bool cs_thread_id_used;
+};
+
+static nir_ssa_def *
+read_thread_local_id(struct lower_intrinsics_state *state)
Mesa (master): i965: Put CS local thread ID uniform in last push register
Module: Mesa
Branch: master
Commit: 04fc72501a90af94b0b5699e57fea68ad6e8795b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=04fc72501a90af94b0b5699e57fea68ad6e8795b
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sun May 22 21:29:53 2016 -0700
i965: Put CS local thread ID uniform in last push register
This thread ID uniform will be used to compute the
gl_LocalInvocationIndex and gl_LocalInvocationID values.
It is important for this uniform to be added in the last push constant
register. fs_visitor::assign_constant_locations is updated to make
sure this happens.
The reason this is important is that the cross-thread push constant
registers are loaded first, and the per-thread push constant registers
are loaded after that. (Broadwell adds another push constant upload
mechanism which reverses this order, but we are ignoring this for
now.)
v2:
* Add variable in intrinsics lowering pass
* Make sure the ID is pushed last in assign_constant_locations, and
that we save a spot for the ID in the push constants
v3:
* Simplify code based with Jason's suggestions.
Cc: "12.0" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 645f2c7..6bd2871 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2097,6 +2097,10 @@ fs_visitor::assign_constant_locations()
bool contiguous[uniforms];
memset(contiguous, 0, sizeof(contiguous));
+ int thread_local_id_index =
+ (stage == MESA_SHADER_COMPUTE) ?
+ ((brw_cs_prog_data*)stage_prog_data)->thread_local_id_index : -1;
+
/* First, we walk through the instructions and do two things:
*
* 1) Figure out which uniforms are live.
@@ -2141,6 +2145,9 @@ fs_visitor::assign_constant_locations()
}
}
+ if (thread_local_id_index >= 0 && !is_live[thread_local_id_index])
+ thread_local_id_index = -1;
+
/* Only allow 16 registers (128 uniform components) as push constants.
*
* Just demote the end of the list. We could probably do better
@@ -2149,7 +2156,9 @@ fs_visitor::assign_constant_locations()
* If changing this value, note the limitation about total_regs in
* brw_curbe.c.
*/
- const unsigned int max_push_components = 16 * 8;
+ unsigned int max_push_components = 16 * 8;
+ if (thread_local_id_index >= 0)
+ max_push_components--; /* Save a slot for the thread ID */
/* We push small arrays, but no bigger than 16 floats. This is big enough
* for a vec4 but hopefully not large enough to push out other stuff. We
@@ -2187,6 +2196,10 @@ fs_visitor::assign_constant_locations()
if (!is_live[u] || is_live_64bit[u])
continue;
+ /* Skip thread_local_id_index to put it in the last push register. */
+ if (thread_local_id_index == (int)u)
+ continue;
+
set_push_pull_constant_loc(u, _start, contiguous[u],
push_constant_loc, pull_constant_loc,
_push_constants, _pull_constants,
@@ -2194,6 +2207,10 @@ fs_visitor::assign_constant_locations()
stage_prog_data);
}
+ /* Add the CS local thread ID uniform at the end of the push constants */
+ if (thread_local_id_index >= 0)
+ push_constant_loc[thread_local_id_index] = num_push_constants++;
+
/* As the uniforms are going to be reordered, take the data from a temporary
* copy of the original param[].
*/
@@ -2212,6 +2229,7 @@ fs_visitor::assign_constant_locations()
* push_constant_loc[i] <= i and we can do it in one smooth loop without
* having to make a copy.
*/
+ int new_thread_local_id_index = -1;
for (unsigned int i = 0; i < uniforms; i++) {
const gl_constant_value *value = param[i];
@@ -2219,9 +2237,15 @@ fs_visitor::assign_constant_locations()
stage_prog_data->pull_param[pull_constant_loc[i]] = value;
} else if (push_constant_loc[i] != -1) {
stage_prog_data->param[push_constant_loc[i]] = value;
+ if (thread_local_id_index == (int)i)
+new_thread_local_id_index = push_constant_loc[i];
}
}
ralloc_free(param);
+
+ if (stage == MESA_SHADER_COMPUTE)
+ ((brw_cs_prog_data*)stage_prog_data)->thread_local_id_index =
+ new_thread_local_id_index;
}
/**
___
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Mesa (master): nir: Make lowering gl_LocalInvocationIndex optional
Module: Mesa
Branch: master
Commit: 6f316c9d8658e870b0140b0f601d35d1fcf133b9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f316c9d8658e870b0140b0f601d35d1fcf133b9
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sun May 22 15:54:48 2016 -0700
nir: Make lowering gl_LocalInvocationIndex optional
Cc: "12.0" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/compiler/nir/nir.c | 4
src/compiler/nir/nir.h | 2 ++
src/compiler/nir/nir_gather_info.c | 1 +
src/compiler/nir/nir_intrinsics.h | 1 +
src/compiler/nir/nir_lower_system_values.c | 16
src/mesa/drivers/dri/i965/brw_compiler.c | 3 ++-
6 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index 2741eb6..3c8b4e0 100644
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -1752,6 +1752,8 @@ nir_intrinsic_from_system_value(gl_system_value val)
return nir_intrinsic_load_sample_mask_in;
case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
return nir_intrinsic_load_local_invocation_id;
+ case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX:
+ return nir_intrinsic_load_local_invocation_index;
case SYSTEM_VALUE_WORK_GROUP_ID:
return nir_intrinsic_load_work_group_id;
case SYSTEM_VALUE_NUM_WORK_GROUPS:
@@ -1801,6 +1803,8 @@ nir_system_value_from_intrinsic(nir_intrinsic_op intrin)
return SYSTEM_VALUE_SAMPLE_MASK_IN;
case nir_intrinsic_load_local_invocation_id:
return SYSTEM_VALUE_LOCAL_INVOCATION_ID;
+ case nir_intrinsic_load_local_invocation_index:
+ return SYSTEM_VALUE_LOCAL_INVOCATION_INDEX;
case nir_intrinsic_load_num_work_groups:
return SYSTEM_VALUE_NUM_WORK_GROUPS;
case nir_intrinsic_load_work_group_id:
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 2e1bdfb..20f6520 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1682,6 +1682,8 @@ typedef struct nir_shader_compiler_options {
/* Indicates that the driver only has zero-based vertex id */
bool vertex_id_zero_based;
+
+ bool lower_cs_local_index_from_id;
} nir_shader_compiler_options;
typedef struct nir_shader_info {
diff --git a/src/compiler/nir/nir_gather_info.c
b/src/compiler/nir/nir_gather_info.c
index 7900fd1..15a9a4f 100644
--- a/src/compiler/nir/nir_gather_info.c
+++ b/src/compiler/nir/nir_gather_info.c
@@ -44,6 +44,7 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader
*shader)
case nir_intrinsic_load_primitive_id:
case nir_intrinsic_load_invocation_id:
case nir_intrinsic_load_local_invocation_id:
+ case nir_intrinsic_load_local_invocation_index:
case nir_intrinsic_load_work_group_id:
case nir_intrinsic_load_num_work_groups:
shader->info.system_values_read |=
diff --git a/src/compiler/nir/nir_intrinsics.h
b/src/compiler/nir/nir_intrinsics.h
index bd00fbb..aeb6038 100644
--- a/src/compiler/nir/nir_intrinsics.h
+++ b/src/compiler/nir/nir_intrinsics.h
@@ -299,6 +299,7 @@ SYSTEM_VALUE(tess_level_outer, 4, 0, xx, xx, xx)
SYSTEM_VALUE(tess_level_inner, 2, 0, xx, xx, xx)
SYSTEM_VALUE(patch_vertices_in, 1, 0, xx, xx, xx)
SYSTEM_VALUE(local_invocation_id, 3, 0, xx, xx, xx)
+SYSTEM_VALUE(local_invocation_index, 1, 0, xx, xx, xx)
SYSTEM_VALUE(work_group_id, 3, 0, xx, xx, xx)
SYSTEM_VALUE(user_clip_plane, 4, 1, UCP_ID, xx, xx)
SYSTEM_VALUE(num_work_groups, 3, 0, xx, xx, xx)
diff --git a/src/compiler/nir/nir_lower_system_values.c
b/src/compiler/nir/nir_lower_system_values.c
index 8310e38..3ca8e08 100644
--- a/src/compiler/nir/nir_lower_system_values.c
+++ b/src/compiler/nir/nir_lower_system_values.c
@@ -48,7 +48,7 @@ convert_block(nir_block *block, nir_builder *b)
b->cursor = nir_after_instr(_var->instr);
- nir_ssa_def *sysval;
+ nir_ssa_def *sysval = NULL;
switch (var->data.location) {
case SYSTEM_VALUE_GLOBAL_INVOCATION_ID: {
/* From the GLSL man page for gl_GlobalInvocationID:
@@ -74,6 +74,12 @@ convert_block(nir_block *block, nir_builder *b)
}
case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX: {
+ /* If lower_cs_local_index_from_id is true, then we derive the local
+ * index from the local id.
+ */
+ if (!b->shader->options->lower_cs_local_index_from_id)
+break;
+
/* From the GLSL man page for gl_LocalInvocationIndex:
*
*"The value of gl_LocalInvocationIndex is equal to
@@ -111,12 +117,14 @@ convert_block(nir_block *block, nir_builder *b)
nir_load_system_value(b, nir_intrinsic_load_base_instance, 0));
break;
- default: {
+ default:
+ break;
+ }
+
+ if (sysval == NULL) {
nir_intrinsic_op sysval_op =
nir_intri
Mesa (master): i965: Support new local ID push constant & cross-thread constants
Module: Mesa
Branch: master
Commit: 30685392e0e41e6c6ba232a63df6b0e2ed83
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=30685392e0e41e6c6ba232a63df6b0e2ed83
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sun May 22 21:55:43 2016 -0700
i965: Support new local ID push constant & cross-thread constants
The cross thread constant support appears on Haswell. It allows us to
upload a set of uniform data for all threads without duplicating it
per thread.
We also support per-thread data which allows us to store a per-thread
ID in one of the uniforms that can be used to calculate the
gl_LocalInvocationIndex and gl_LocalInvocationID variables.
v4:
* Support the old local ID push constant layout as well (Jason)
Cc: "12.0" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_defines.h | 3 +
src/mesa/drivers/dri/i965/gen7_cs_state.c | 94 ---
2 files changed, 52 insertions(+), 45 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 4eb6b1f..e7d1a9f 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -2943,6 +2943,9 @@ enum brw_wm_barycentric_interp_mode {
# define MEDIA_GPGPU_THREAD_COUNT_MASK INTEL_MASK(7, 0)
# define GEN8_MEDIA_GPGPU_THREAD_COUNT_SHIFT0
# define GEN8_MEDIA_GPGPU_THREAD_COUNT_MASK INTEL_MASK(9, 0)
+/* GEN7 DW6, GEN8+ DW7 */
+# define CROSS_THREAD_READ_LENGTH_SHIFT 0
+# define CROSS_THREAD_READ_LENGTH_MASK INTEL_MASK(7, 0)
#define MEDIA_STATE_FLUSH 0x7004
#define GPGPU_WALKER0x7105
/* GEN7 DW0 */
diff --git a/src/mesa/drivers/dri/i965/gen7_cs_state.c
b/src/mesa/drivers/dri/i965/gen7_cs_state.c
index 619edfb..f97c26a 100644
--- a/src/mesa/drivers/dri/i965/gen7_cs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_cs_state.c
@@ -42,7 +42,6 @@ brw_upload_cs_state(struct brw_context *brw)
uint32_t offset;
uint32_t *desc = (uint32_t*) brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
8 * 4, 64, );
- struct gl_program *prog = (struct gl_program *) brw->compute_program;
struct brw_stage_state *stage_state = >cs.base;
struct brw_cs_prog_data *cs_prog_data = brw->cs.prog_data;
struct brw_stage_prog_data *prog_data = _prog_data->base;
@@ -59,16 +58,6 @@ brw_upload_cs_state(struct brw_context *brw)
prog_data->binding_table.size_bytes,
32, _state->bind_bo_offset);
- unsigned local_id_dwords = 0;
-
- if (prog->SystemValuesRead & SYSTEM_BIT_LOCAL_INVOCATION_ID)
- local_id_dwords = cs_prog_data->local_invocation_id_regs * 8;
-
- unsigned push_constant_data_size =
- (prog_data->nr_params + local_id_dwords) * sizeof(gl_constant_value);
- unsigned reg_aligned_constant_size = ALIGN(push_constant_data_size, 32);
- unsigned push_constant_regs = reg_aligned_constant_size / 32;
-
uint32_t dwords = brw->gen < 8 ? 8 : 9;
BEGIN_BATCH(dwords);
OUT_BATCH(MEDIA_VFE_STATE << 16 | (dwords - 2));
@@ -118,7 +107,8 @@ brw_upload_cs_state(struct brw_context *brw)
* Note: The constant data is built in brw_upload_cs_push_constants below.
*/
const uint32_t vfe_curbe_allocation =
- push_constant_regs * cs_prog_data->threads;
+ ALIGN(cs_prog_data->push.per_thread.regs * cs_prog_data->threads +
+cs_prog_data->push.cross_thread.regs, 2);
OUT_BATCH(SET_FIELD(vfe_urb_allocation, MEDIA_VFE_STATE_URB_ALLOC) |
SET_FIELD(vfe_curbe_allocation, MEDIA_VFE_STATE_CURBE_ALLOC));
OUT_BATCH(0);
@@ -126,11 +116,11 @@ brw_upload_cs_state(struct brw_context *brw)
OUT_BATCH(0);
ADVANCE_BATCH();
- if (reg_aligned_constant_size > 0) {
+ if (cs_prog_data->push.total.size > 0) {
BEGIN_BATCH(4);
OUT_BATCH(MEDIA_CURBE_LOAD << 16 | (4 - 2));
OUT_BATCH(0);
- OUT_BATCH(ALIGN(reg_aligned_constant_size * cs_prog_data->threads, 64));
+ OUT_BATCH(ALIGN(cs_prog_data->push.total.size, 64));
OUT_BATCH(stage_state->push_const_offset);
ADVANCE_BATCH();
}
@@ -149,7 +139,8 @@ brw_upload_cs_state(struct brw_context *brw)
desc[dw++] = stage_state->sampler_offset |
((stage_state->sampler_count + 3) / 4);
desc[dw++] = stage_state->bind_bo_offset;
- desc[dw++] = SET_FIELD(push_constant_regs, MEDIA_CURBE_READ_LENGTH);
+ desc[dw++] = SET_FIELD(cs_prog_data->push.per_thread.regs,
+ MEDIA_CURBE_READ_LENGTH);
const uint32_t media_threads =
brw->gen >= 8 ?
SET_FIELD(cs_prog_dat
Mesa (master): i965: Store number of threads in brw_cs_prog_data
Module: Mesa
Branch: master
Commit: 1b79e7ebbd77a7e714fafadd91459059aacf2407
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b79e7ebbd77a7e714fafadd91459059aacf2407
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Thu May 26 13:49:07 2016 -0700
i965: Store number of threads in brw_cs_prog_data
Cc: "12.0" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/intel/vulkan/anv_cmd_buffer.c | 7 +++
src/intel/vulkan/anv_private.h| 1 -
src/intel/vulkan/gen7_cmd_buffer.c| 2 +-
src/intel/vulkan/gen8_cmd_buffer.c| 2 +-
src/intel/vulkan/genX_cmd_buffer.c| 4 ++--
src/intel/vulkan/genX_pipeline.c | 4 +---
src/mesa/drivers/dri/i965/brw_compiler.h | 1 +
src/mesa/drivers/dri/i965/brw_fs.cpp | 15 ---
src/mesa/drivers/dri/i965/gen7_cs_state.c | 32 ++-
9 files changed, 31 insertions(+), 37 deletions(-)
diff --git a/src/intel/vulkan/anv_cmd_buffer.c
b/src/intel/vulkan/anv_cmd_buffer.c
index 4d0fd7c..63d096c 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -1076,9 +1076,8 @@ anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer)
if (reg_aligned_constant_size == 0)
return (struct anv_state) { .offset = 0 };
- const unsigned threads = pipeline->cs_thread_width_max;
const unsigned total_push_constants_size =
- reg_aligned_constant_size * threads;
+ reg_aligned_constant_size * cs_prog_data->threads;
const unsigned push_constant_alignment =
cmd_buffer->device->info.gen < 8 ? 32 : 64;
const unsigned aligned_total_push_constants_size =
@@ -1091,7 +1090,7 @@ anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer)
/* Walk through the param array and fill the buffer with data */
uint32_t *u32_map = state.map;
- brw_cs_fill_local_id_payload(cs_prog_data, u32_map, threads,
+ brw_cs_fill_local_id_payload(cs_prog_data, u32_map, cs_prog_data->threads,
reg_aligned_constant_size);
/* Setup uniform data for the first thread */
@@ -1102,7 +1101,7 @@ anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer)
/* Copy uniform data from the first thread to every other thread */
const size_t uniform_data_size = prog_data->nr_params * sizeof(uint32_t);
- for (unsigned t = 1; t < threads; t++) {
+ for (unsigned t = 1; t < cs_prog_data->threads; t++) {
memcpy(_map[t * param_aligned_count + local_id_dwords],
_map[local_id_dwords],
uniform_data_size);
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 7325f3f..26ffbd6 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1474,7 +1474,6 @@ struct anv_pipeline {
bool primitive_restart;
uint32_t topology;
- uint32_t cs_thread_width_max;
uint32_t cs_right_mask;
struct {
diff --git a/src/intel/vulkan/gen7_cmd_buffer.c
b/src/intel/vulkan/gen7_cmd_buffer.c
index 331275e..40ab008 100644
--- a/src/intel/vulkan/gen7_cmd_buffer.c
+++ b/src/intel/vulkan/gen7_cmd_buffer.c
@@ -271,7 +271,7 @@ flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer)
.BarrierEnable = cs_prog_data->uses_barrier,
.SharedLocalMemorySize = slm_size,
.NumberofThreadsinGPGPUThreadGroup =
- pipeline->cs_thread_width_max);
+ cs_prog_data->threads);
const uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) *
sizeof(uint32_t);
anv_batch_emit(_buffer->batch,
diff --git a/src/intel/vulkan/gen8_cmd_buffer.c
b/src/intel/vulkan/gen8_cmd_buffer.c
index 547fedd..e139e8a 100644
--- a/src/intel/vulkan/gen8_cmd_buffer.c
+++ b/src/intel/vulkan/gen8_cmd_buffer.c
@@ -356,7 +356,7 @@ flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer)
.BarrierEnable = cs_prog_data->uses_barrier,
.SharedLocalMemorySize = slm_size,
.NumberofThreadsinGPGPUThreadGroup =
- pipeline->cs_thread_width_max);
+ cs_prog_data->threads);
uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
anv_batch_emit(_buffer->batch,
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index e7d322c..d9acf58 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -773,7 +773,7 @@ void genX(CmdDispatch)(
ggw.SIMDSi
