Module: Mesa Branch: main Commit: 43bc212aeb8b5905ddd69d1a39ac7b5e2d175426 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=43bc212aeb8b5905ddd69d1a39ac7b5e2d175426
Author: Danylo Piliaiev <dpilia...@igalia.com> Date: Thu Jan 11 17:46:04 2024 +0100 ir3: Add fullsync and fullnop ir3 dbg options for over-syncing - fullsync - adds (ss)(sy) after each cat4/cat5/cat6 - fullnop - adds (rpt4) nop before every instruction Useful to debug errors in inter-instruction synchronization. Signed-off-by: Danylo Piliaiev <dpilia...@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27012> --- src/freedreno/ir3/ir3_compiler.c | 2 ++ src/freedreno/ir3/ir3_compiler.h | 2 ++ src/freedreno/ir3/ir3_legalize.c | 35 +++++++++++++++++++++++++++++++++++ src/freedreno/vulkan/tu_device.h | 2 +- 4 files changed, 40 insertions(+), 1 deletion(-) diff --git a/src/freedreno/ir3/ir3_compiler.c b/src/freedreno/ir3/ir3_compiler.c index 80ca0656df7..7c38d392a2d 100644 --- a/src/freedreno/ir3/ir3_compiler.c +++ b/src/freedreno/ir3/ir3_compiler.c @@ -47,6 +47,8 @@ static const struct debug_named_value shader_debug_options[] = { {"nocache", IR3_DBG_NOCACHE, "Disable shader cache"}, {"spillall", IR3_DBG_SPILLALL, "Spill as much as possible to test the spiller"}, {"nopreamble", IR3_DBG_NOPREAMBLE, "Disable the preamble pass"}, + {"fullsync", IR3_DBG_FULLSYNC, "Add (sy) + (ss) after each cat5/cat6"}, + {"fullnop", IR3_DBG_FULLNOP, "Add nops before each instruction"}, #ifdef DEBUG /* DEBUG-only options: */ {"schedmsgs", IR3_DBG_SCHEDMSGS, "Enable scheduler debug messages"}, diff --git a/src/freedreno/ir3/ir3_compiler.h b/src/freedreno/ir3/ir3_compiler.h index 08eb53e9e82..7a550dcea08 100644 --- a/src/freedreno/ir3/ir3_compiler.h +++ b/src/freedreno/ir3/ir3_compiler.h @@ -299,6 +299,8 @@ enum ir3_shader_debug { IR3_DBG_SPILLALL = BITFIELD_BIT(12), IR3_DBG_NOPREAMBLE = BITFIELD_BIT(13), IR3_DBG_SHADER_INTERNAL = BITFIELD_BIT(14), + IR3_DBG_FULLSYNC = BITFIELD_BIT(15), + IR3_DBG_FULLNOP = BITFIELD_BIT(16), /* DEBUG-only options: */ IR3_DBG_SCHEDMSGS = BITFIELD_BIT(20), diff --git a/src/freedreno/ir3/ir3_legalize.c b/src/freedreno/ir3/ir3_legalize.c index e7db858ba28..958a08d23a9 100644 --- a/src/freedreno/ir3/ir3_legalize.c +++ b/src/freedreno/ir3/ir3_legalize.c @@ -948,6 +948,33 @@ nop_sched(struct ir3 *ir, struct ir3_shader_variant *so) } } +static void +dbg_sync_sched(struct ir3 *ir, struct ir3_shader_variant *so) +{ + foreach_block (block, &ir->block_list) { + foreach_instr_safe (instr, &block->instr_list) { + if (opc_cat(instr->opc) == 4 || opc_cat(instr->opc) == 5 || + opc_cat(instr->opc) == 6) { + struct ir3_instruction *nop = ir3_NOP(block); + nop->flags |= IR3_INSTR_SS | IR3_INSTR_SY; + ir3_instr_move_after(nop, instr); + } + } + } +} + +static void +dbg_nop_sched(struct ir3 *ir, struct ir3_shader_variant *so) +{ + foreach_block (block, &ir->block_list) { + foreach_instr_safe (instr, &block->instr_list) { + struct ir3_instruction *nop = ir3_NOP(block); + nop->repeat = 5; + ir3_instr_move_before(nop, instr); + } + } +} + struct ir3_helper_block_data { /* Whether helper invocations may be used on any path starting at the * beginning of the block. @@ -1230,6 +1257,14 @@ ir3_legalize(struct ir3 *ir, struct ir3_shader_variant *so, int *max_bary) nop_sched(ir, so); + if (ir3_shader_debug & IR3_DBG_FULLSYNC) { + dbg_sync_sched(ir, so); + } + + if (ir3_shader_debug & IR3_DBG_FULLNOP) { + dbg_nop_sched(ir, so); + } + while (opt_jump(ir)) ; diff --git a/src/freedreno/vulkan/tu_device.h b/src/freedreno/vulkan/tu_device.h index bd7e715807c..e0434148211 100644 --- a/src/freedreno/vulkan/tu_device.h +++ b/src/freedreno/vulkan/tu_device.h @@ -31,7 +31,7 @@ #define TU_BORDER_COLOR_COUNT 4096 #define TU_BORDER_COLOR_BUILTIN 6 -#define TU_BLIT_SHADER_SIZE 1024 +#define TU_BLIT_SHADER_SIZE 4096 /* extra space in vsc draw/prim streams */ #define VSC_PAD 0x40
