Mesa (master): mesa: Fix format specifier warning in mesa_DispatchComputeIndirect()

[Jordan Justen]

Module: Mesa
Branch: master
Commit: 83018f5c20a2a1b48f88704a25ebb8410b2f9c71
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=83018f5c20a2a1b48f88704a25ebb8410b2f9c71

Author: Rhys Kidd 
Date:   Wed Sep 30 23:18:52 2015 +1000

mesa: Fix format specifier warning in mesa_DispatchComputeIndirect()

Commit 1665d29ee3125743fd6daf3c43fc715f543d5669 introduced an incorrect
format specifier that operates on GLintptr indirect within the function
_mesa_DispatchComputeIndirect().

This patch mitigates the introduced GCC warning:

src/mesa/main/compute.c: In function '_mesa_DispatchComputeIndirect':
src/mesa/main/compute.c:53:7: warning: format '%d' expects argument of type 
'int', but argument 3 has type 'GLintptr' [-Wformat=]
   _mesa_debug(ctx, "glDispatchComputeIndirect(%d)\n", indirect);
   ^

v2: Amend for Boyan Ding  feedback.

Signed-off-by: Rhys Kidd 
Reviewed-by: Jordan Justen 

---

 src/mesa/main/compute.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/main/compute.c b/src/mesa/main/compute.c
index 8bc3bcd..53e7a50 100644
--- a/src/mesa/main/compute.c
+++ b/src/mesa/main/compute.c
@@ -50,7 +50,7 @@ _mesa_DispatchComputeIndirect(GLintptr indirect)
GET_CURRENT_CONTEXT(ctx);
 
if (MESA_VERBOSE & VERBOSE_API)
-  _mesa_debug(ctx, "glDispatchComputeIndirect(%d)\n", indirect);
+  _mesa_debug(ctx, "glDispatchComputeIndirect(%ld)\n", (long) indirect);
 
if (!_mesa_validate_DispatchComputeIndirect(ctx, indirect))
   return;

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Mesa (master): i965/cs: Upload UBO/SSBO surfaces

[Jordan Justen]

Module: Mesa
Branch: master
Commit: 7b391142e9da6186221a9eb39977e487f079ef72
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b391142e9da6186221a9eb39977e487f079ef72

Author: Jordan Justen 
Date:   Tue Sep 29 17:04:03 2015 -0700

i965/cs: Upload UBO/SSBO surfaces

Signed-off-by: Jordan Justen 
Reviewed-by: Samuel Iglesias Gonsálvez 

---

 src/mesa/drivers/dri/i965/brw_context.h  |2 +-
 src/mesa/drivers/dri/i965/brw_state.h|1 +
 src/mesa/drivers/dri/i965/brw_state_upload.c |2 ++
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |   26 ++
 4 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 1dd48f6..19a5117 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1516,7 +1516,7 @@ struct brw_context
 
int num_atoms[BRW_NUM_PIPELINES];
const struct brw_tracked_state render_atoms[60];
-   const struct brw_tracked_state compute_atoms[7];
+   const struct brw_tracked_state compute_atoms[8];
 
/* If (INTEL_DEBUG & DEBUG_BATCH) */
struct {
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 3b7a433..dc2b941 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -87,6 +87,7 @@ extern const struct brw_tracked_state brw_vs_binding_table;
 extern const struct brw_tracked_state brw_wm_ubo_surfaces;
 extern const struct brw_tracked_state brw_wm_abo_surfaces;
 extern const struct brw_tracked_state brw_wm_image_surfaces;
+extern const struct brw_tracked_state brw_cs_ubo_surfaces;
 extern const struct brw_tracked_state brw_cs_abo_surfaces;
 extern const struct brw_tracked_state brw_cs_image_surfaces;
 extern const struct brw_tracked_state brw_wm_unit;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 46687e3..79b8301 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -259,6 +259,7 @@ static const struct brw_tracked_state *gen7_compute_atoms[] 
=
_state_base_address,
_cs_image_surfaces,
_cs_push_constants,
+   _cs_ubo_surfaces,
_cs_abo_surfaces,
_texture_surfaces,
_cs_work_groups_surface,
@@ -352,6 +353,7 @@ static const struct brw_tracked_state *gen8_compute_atoms[] 
=
_state_base_address,
_cs_image_surfaces,
_cs_push_constants,
+   _cs_ubo_surfaces,
_cs_abo_surfaces,
_texture_surfaces,
_cs_work_groups_surface,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index c931696..4e70cae 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1001,6 +1001,32 @@ const struct brw_tracked_state brw_wm_ubo_surfaces = {
.emit = brw_upload_wm_ubo_surfaces,
 };
 
+static void
+brw_upload_cs_ubo_surfaces(struct brw_context *brw)
+{
+   struct gl_context *ctx = >ctx;
+   /* _NEW_PROGRAM */
+   struct gl_shader_program *prog =
+  ctx->_Shader->CurrentProgram[MESA_SHADER_COMPUTE];
+
+   if (!prog)
+  return;
+
+   /* BRW_NEW_CS_PROG_DATA */
+   brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_COMPUTE],
+   >cs.base, >cs.prog_data->base, true);
+}
+
+const struct brw_tracked_state brw_cs_ubo_surfaces = {
+   .dirty = {
+  .mesa = _NEW_PROGRAM,
+  .brw = BRW_NEW_BATCH |
+ BRW_NEW_CS_PROG_DATA |
+ BRW_NEW_UNIFORM_BUFFER,
+   },
+   .emit = brw_upload_cs_ubo_surfaces,
+};
+
 void
 brw_upload_abo_surfaces(struct brw_context *brw,
struct gl_shader_program *prog,

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Mesa (master): util: use strnlen() in strndup() implementations

[Samuel Iglesias Gonsálvez]

Module: Mesa
Branch: master
Commit: f3afcbecc63ec565a0386cda554d145ca908367d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f3afcbecc63ec565a0386cda554d145ca908367d

Author: Samuel Iglesias Gonsalvez 
Date:   Tue Sep 29 16:10:02 2015 +0200

util: use strnlen() in strndup() implementations

If the string being copied is not NULL-terminated the result of
strlen() is undefined.

Signed-off-by: Samuel Iglesias Gonsalvez 
Reviewed-by: Neil Roberts 
Reviewed-by: Jose Fonseca 

---

 src/util/ralloc.c  |5 +
 src/util/strndup.c |5 +
 2 files changed, 2 insertions(+), 8 deletions(-)

diff --git a/src/util/ralloc.c b/src/util/ralloc.c
index 01719c8..e07fce7 100644
--- a/src/util/ralloc.c
+++ b/src/util/ralloc.c
@@ -359,10 +359,7 @@ ralloc_strndup(const void *ctx, const char *str, size_t 
max)
if (unlikely(str == NULL))
   return NULL;
 
-   n = strlen(str);
-   if (n > max)
-  n = max;
-
+   n = strnlen(str, max);
ptr = ralloc_array(ctx, char, n + 1);
memcpy(ptr, str, n);
ptr[n] = '\0';
diff --git a/src/util/strndup.c b/src/util/strndup.c
index ca1c6f5..5ceb32f 100644
--- a/src/util/strndup.c
+++ b/src/util/strndup.c
@@ -35,10 +35,7 @@ strndup(const char *str, size_t max)
if (!str)
   return NULL;
 
-   n = strlen(str);
-   if (n > max)
-  n = max;
-
+   n = strnlen(str, max);
ptr = (char *) calloc(n + 1, sizeof(char));
if (!ptr)
   return NULL;

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Mesa (master): i965/vec4/nir: add nir_intrinsic_memory_barrier support

[Samuel Iglesias Gonsálvez]

Module: Mesa
Branch: master
Commit: 023165a734b3bae52a449ad01bc1ea5ba4384ec1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=023165a734b3bae52a449ad01bc1ea5ba4384ec1

Author: Samuel Iglesias Gonsalvez 
Date:   Tue Sep 15 11:16:29 2015 +0200

i965/vec4/nir: add nir_intrinsic_memory_barrier support

Fix OpenGL ES 3.1 conformance tests: advanced-readWrite-case1-vsfs
and advanced-matrix-vsfs.

v2:
- Fix SHADER_OPCODE_MEMORY_FENCE emission and the allocation of 'tmp'
  (Francisco).

Signed-off-by: Samuel Iglesias Gonsalvez 
Tested-by: Tapani Pälli 
Reviewed-by: Francisco Jerez 

---

 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp |9 +
 1 file changed, 9 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 94906d2..2555038 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -921,6 +921,15 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr 
*instr)
   break;
}
 
+   case nir_intrinsic_memory_barrier: {
+  const vec4_builder bld =
+ vec4_builder(this).at_end().annotate(current_annotation, base_ir);
+  const dst_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, 2);
+  bld.emit(SHADER_OPCODE_MEMORY_FENCE, tmp)
+ ->regs_written = 2;
+  break;
+   }
+
default:
   unreachable("Unknown intrinsic");
}

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Mesa (master): glsl: assert base_alignment > 0 for records

[Samuel Iglesias Gonsálvez]

Module: Mesa
Branch: master
Commit: e21bb9e7bdea0f73809759d3c248048eedd79663
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e21bb9e7bdea0f73809759d3c248048eedd79663

Author: Samuel Iglesias Gonsalvez 
Date:   Mon Sep 28 11:47:33 2015 +0200

glsl: assert base_alignment > 0 for records

From GLSL 1.50 spec, section 4.1.8 "Structures":

"Structures must have at least one member declaration."

So the base_alignment should be higher than zero.

Signed-off-by: Samuel Iglesias Gonsalvez 
Reviewed-by: Ilia Mirkin 

---

 src/glsl/glsl_types.cpp |1 +
 1 file changed, 1 insertion(+)

diff --git a/src/glsl/glsl_types.cpp b/src/glsl/glsl_types.cpp
index 0ead0f2..8586b2e 100644
--- a/src/glsl/glsl_types.cpp
+++ b/src/glsl/glsl_types.cpp
@@ -1511,6 +1511,7 @@ glsl_type::std430_base_alignment(bool row_major) const
  base_alignment = MAX2(base_alignment,

field_type->std430_base_alignment(field_row_major));
   }
+  assert(base_alignment > 0);
   return base_alignment;
}
assert(!"not reached");

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Mesa (master): glsl: apply shader storage block member rules when adding program resources

[Samuel Iglesias Gonsálvez]

Module: Mesa
Branch: master
Commit: f24e5e68d6bd640da2d9a3ae1cf7898ef9ed2fce
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f24e5e68d6bd640da2d9a3ae1cf7898ef9ed2fce

Author: Samuel Iglesias Gonsalvez 
Date:   Wed Sep 16 15:47:34 2015 +0200

glsl: apply shader storage block member rules when adding program resources

From ARB_program_interface_query:

"For an active shader storage block member declared as an array, an
 entry will be generated only for the first array element, regardless
 of its type. For arrays of aggregate types, the enumeration rules are
 applied recursively for the single enumerated array element."

v2:
- Simplify 'if' conditions and return true if it is not a buffer
  variable, because these rules only apply to buffer variables (Timothy).

Signed-off-by: Samuel Iglesias Gonsalvez 
Reviewed-by: Timothy Arceri 

---

 src/glsl/linker.cpp |   58 +++
 1 file changed, 58 insertions(+)

diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index 87c7d4b..dbf300a 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -3134,6 +3134,60 @@ check_explicit_uniform_locations(struct gl_context *ctx,
 }
 
 static bool
+should_add_buffer_variable(struct gl_shader_program *shProg,
+   GLenum type, const char *name)
+{
+   bool found_interface = false;
+   const char *block_name = NULL;
+
+   /* These rules only apply to buffer variables. So we return
+* true for the rest of types.
+*/
+   if (type != GL_BUFFER_VARIABLE)
+  return true;
+
+   for (unsigned i = 0; i < shProg->NumBufferInterfaceBlocks; i++) {
+  block_name = shProg->UniformBlocks[i].Name;
+  if (strncmp(block_name, name, strlen(block_name)) == 0) {
+ found_interface = true;
+ break;
+  }
+   }
+
+   /* We remove the interface name from the buffer variable name,
+* including the dot that follows it.
+*/
+   if (found_interface)
+  name = name + strlen(block_name) + 1;
+
+   /* From: ARB_program_interface_query extension:
+*
+*  "For an active shader storage block member declared as an array, an
+*   entry will be generated only for the first array element, regardless
+*   of its type.  For arrays of aggregate types, the enumeration rules are
+*   applied recursively for the single enumerated array element.
+*/
+   const char *first_dot = strchr(name, '.');
+   const char *first_square_bracket = strchr(name, '[');
+
+   /* The buffer variable is on top level and it is not an array */
+   if (!first_square_bracket) {
+  return true;
+   /* The shader storage block member is a struct, then generate the entry */
+   } else if (first_dot && first_dot < first_square_bracket) {
+  return true;
+   } else {
+  /* Shader storage block member is an array, only generate an entry for 
the
+   * first array element.
+   */
+  if (strncmp(first_square_bracket, "[0]", 3) == 0)
+ return true;
+   }
+
+   return false;
+}
+
+static bool
 add_program_resource(struct gl_shader_program *prog, GLenum type,
  const void *data, uint8_t stages)
 {
@@ -3412,6 +3466,10 @@ build_program_resource_list(struct gl_shader_program 
*shProg)
 
   bool is_shader_storage =  shProg->UniformStorage[i].is_shader_storage;
   GLenum type = is_shader_storage ? GL_BUFFER_VARIABLE : GL_UNIFORM;
+  if (!should_add_buffer_variable(shProg, type,
+  shProg->UniformStorage[i].name))
+ continue;
+
   if (!add_program_resource(shProg, type,
 >UniformStorage[i], stageref))
  return;

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Mesa (master): i965: Remove early release of DRI2 miptree

[Martin Peres]

Module: Mesa
Branch: master
Commit: 70e91d61fde239e8ae58148cacd4ff891126e2aa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=70e91d61fde239e8ae58148cacd4ff891126e2aa

Author: Chris Wilson 
Date:   Fri Aug  7 21:13:12 2015 +0100

i965: Remove early release of DRI2 miptree

intel_update_winsys_renderbuffer_miptree() will release the existing
miptree when wrapping a new DRI2 buffer, so we can remove the early
release and so prevent a NULL mt dereference should importing the new
DRI2 name fail for any reason. (Reusing the old DRI2 name will result
in the rendering going astray, to a stale buffer, and not shown on the
screen, but it allows us to issue a warning and not crash much later in
innocent code.)

Signed-off-by: Chris Wilson 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86281
Reviewed-by: Martin Peres 
Reviewed-by: Chad Versace 

---

 src/mesa/drivers/dri/i965/brw_context.c |1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 9dcdaf5..4d49929 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1436,7 +1436,6 @@ intel_process_dri2_buffer(struct brw_context *brw,
   buffer->cpp, buffer->pitch);
}
 
-   intel_miptree_release(>mt);
bo = drm_intel_bo_gem_create_from_name(brw->bufmgr, buffer_name,
   buffer->name);
if (!bo) {

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Mesa (master): i965: Remove duplicate copy of is_scalar_shader_stage().

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 651395b6e8332160023ecdddb45b03a313d26077
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=651395b6e8332160023ecdddb45b03a313d26077

Author: Kenneth Graunke 
Date:   Wed Sep 30 09:13:08 2015 -0700

i965: Remove duplicate copy of is_scalar_shader_stage().

Jason open coded this in 60befc63 when cleaning up some ugly code;
using our existing helper tidies it up a bit more.

v2: Drop inline (suggested by Matt).

Signed-off-by: Kenneth Graunke 
Reviewed-by: Jason Ekstrand 
Reviewed-by: Matt Turner 

---

 src/mesa/drivers/dri/i965/brw_shader.cpp |   51 --
 1 file changed, 20 insertions(+), 31 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp 
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 785cb27..af85bd2 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -72,6 +72,20 @@ shader_perf_log_mesa(void *data, const char *fmt, ...)
va_end(args);
 }
 
+static bool
+is_scalar_shader_stage(const struct brw_compiler *compiler, int stage)
+{
+   switch (stage) {
+   case MESA_SHADER_FRAGMENT:
+   case MESA_SHADER_COMPUTE:
+  return true;
+   case MESA_SHADER_VERTEX:
+  return compiler->scalar_vs;
+   default:
+  return false;
+   }
+}
+
 struct brw_compiler *
 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
 {
@@ -118,19 +132,7 @@ brw_compiler_create(void *mem_ctx, const struct 
brw_device_info *devinfo)
   compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
   compiler->glsl_compiler_options[i].LowerClipDistance = true;
 
-  bool is_scalar;
-  switch (i) {
-  case MESA_SHADER_FRAGMENT:
-  case MESA_SHADER_COMPUTE:
- is_scalar = true;
- break;
-  case MESA_SHADER_VERTEX:
- is_scalar = compiler->scalar_vs;
- break;
-  default:
- is_scalar = false;
- break;
-  }
+  bool is_scalar = is_scalar_shader_stage(compiler, i);
 
   compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
   compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
@@ -192,20 +194,6 @@ brw_shader_precompile(struct gl_context *ctx,
return true;
 }
 
-static inline bool
-is_scalar_shader_stage(struct brw_context *brw, int stage)
-{
-   switch (stage) {
-   case MESA_SHADER_FRAGMENT:
-   case MESA_SHADER_COMPUTE:
-  return true;
-   case MESA_SHADER_VERTEX:
-  return brw->intelScreen->compiler->scalar_vs;
-   default:
-  return false;
-   }
-}
-
 static void
 brw_lower_packing_builtins(struct brw_context *brw,
gl_shader_stage shader_type,
@@ -216,7 +204,7 @@ brw_lower_packing_builtins(struct brw_context *brw,
| LOWER_PACK_UNORM_2x16
| LOWER_UNPACK_UNORM_2x16;
 
-   if (is_scalar_shader_stage(brw, shader_type)) {
+   if (is_scalar_shader_stage(brw->intelScreen->compiler, shader_type)) {
   ops |= LOWER_UNPACK_UNORM_4x8
| LOWER_UNPACK_SNORM_4x8
| LOWER_PACK_UNORM_4x8
@@ -229,7 +217,7 @@ brw_lower_packing_builtins(struct brw_context *brw,
* lowering is needed. For SOA code, the Half2x16 ops must be
* scalarized.
*/
-  if (is_scalar_shader_stage(brw, shader_type)) {
+  if (is_scalar_shader_stage(brw->intelScreen->compiler, shader_type)) {
  ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
  |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
   }
@@ -310,7 +298,7 @@ process_glsl_ir(gl_shader_stage stage,
do {
   progress = false;
 
-  if (is_scalar_shader_stage(brw, shader->Stage)) {
+  if (is_scalar_shader_stage(brw->intelScreen->compiler, shader->Stage)) {
  brw_do_channel_expressions(shader->ir);
  brw_do_vector_splitting(shader->ir);
   }
@@ -348,6 +336,7 @@ GLboolean
 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 {
struct brw_context *brw = brw_context(ctx);
+   const struct brw_compiler *compiler = brw->intelScreen->compiler;
unsigned int stage;
 
for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
@@ -404,7 +393,7 @@ brw_link_shader(struct gl_context *ctx, struct 
gl_shader_program *shProg)
 
   if (options->NirOptions) {
  prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage,
-is_scalar_shader_stage(brw, stage));
+is_scalar_shader_stage(compiler, stage));
   }
 
   _mesa_reference_program(ctx, , NULL);

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Mesa (master): i915: Remember to call intel_prepare_render() before blitting

[Ian Romanick]

Module: Mesa
Branch: master
Commit: a1a3f0961b20907b6948959c1f224bb055bd4f3d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1a3f0961b20907b6948959c1f224bb055bd4f3d

Author: Ville Syrjälä 
Date:   Mon Mar 23 14:47:33 2015 +0200

i915: Remember to call intel_prepare_render() before blitting

Bring over the following fix from i965:
 commit fb3d62fe3d4fc40ba4ad9804d8b6f451316c9ae2
 Author: Kenneth Graunke 
 Date:   Tue Aug 6 14:36:09 2013 -0700

i965: Remember to call intel_prepare_render() before blitting.

Fixes a crash in the following piglit tests:
 bin/fbo-sys-blit -auto
 bin/fbo-sys-sub-blit -auto

Signed-off-by: Ville Syrjälä 
Reviewed-by: Ian Romanick 
Cc: "11.0" 

---

 src/mesa/drivers/dri/i915/intel_fbo.c |5 +
 1 file changed, 5 insertions(+)

diff --git a/src/mesa/drivers/dri/i915/intel_fbo.c 
b/src/mesa/drivers/dri/i915/intel_fbo.c
index 6701366..12cc7e3 100644
--- a/src/mesa/drivers/dri/i915/intel_fbo.c
+++ b/src/mesa/drivers/dri/i915/intel_fbo.c
@@ -658,6 +658,11 @@ intel_blit_framebuffer_with_blitter(struct gl_context *ctx,
 {
struct intel_context *intel = intel_context(ctx);
 
+   /* Sync up the state of window system buffers.  We need to do this before
+* we go looking for the buffers.
+*/
+   intel_prepare_render(intel);
+
if (mask & GL_COLOR_BUFFER_BIT) {
   GLint i;
   struct gl_renderbuffer *src_rb = readFb->_ColorReadBuffer;

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Mesa (master): i830: Fix collision between I830_UPLOAD_RASTER_RULES and I830_UPLOAD_TEX(0)

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 9504740f3e6698d860ac93310a33f51f01c10c4f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9504740f3e6698d860ac93310a33f51f01c10c4f

Author: Ville Syrjälä 
Date:   Mon Mar 23 14:47:24 2015 +0200

i830: Fix collision between I830_UPLOAD_RASTER_RULES and I830_UPLOAD_TEX(0)

I830_UPLOAD_RASTER_RULES and I830_UPLOAD_TEX(0) are trying to occupy
the same bit. Move the texture bits upwards a bit to make room for
I830_UPLOAD_RASTER_RULES.

Now the driver will actually upload the raster rules which is rather
important to get the provoking vertex right. Fixes the appearance
of glxgears teeth on gen2.

Signed-off-by: Ville Syrjälä 
Reviewed-by: Ian Romanick 
Cc: "10.6 11.0" 

---

 src/mesa/drivers/dri/i915/i830_context.h |8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/i830_context.h 
b/src/mesa/drivers/dri/i915/i830_context.h
index 140f617..92952cf 100644
--- a/src/mesa/drivers/dri/i915/i830_context.h
+++ b/src/mesa/drivers/dri/i915/i830_context.h
@@ -42,10 +42,10 @@
 #define I830_UPLOAD_STIPPLE  0x4
 #define I830_UPLOAD_INVARIENT0x8
 #define I830_UPLOAD_RASTER_RULES 0x10
-#define I830_UPLOAD_TEX(i)   (0x10<<(i))
-#define I830_UPLOAD_TEXBLEND(i)  (0x100<<(i))
-#define I830_UPLOAD_TEX_ALL  (0x0f0)
-#define I830_UPLOAD_TEXBLEND_ALL (0xf00)
+#define I830_UPLOAD_TEX(i)   (0x0100<<(i))
+#define I830_UPLOAD_TEXBLEND(i)  (0x1000<<(i))
+#define I830_UPLOAD_TEX_ALL  (0x0f00)
+#define I830_UPLOAD_TEXBLEND_ALL (0xf000)
 
 /* State structure offsets - these will probably disappear.
  */

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Mesa (master): i915: Fix texcoord vs. varying collision in fragment programs

[Ian Romanick]

Module: Mesa
Branch: master
Commit: c349031c27b7f66151f07d785625c585e10a92c2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c349031c27b7f66151f07d785625c585e10a92c2

Author: Ville Syrjälä 
Date:   Mon Mar 23 14:47:36 2015 +0200

i915: Fix texcoord vs. varying collision in fragment programs

i915 fragment programs utilize the texture coordinate registers
for both texture coordinates and varyings. Unfortunately the
code doesn't check if the same index might be in use for both.
It just naively uses the index to pick a texture unit, which
could lead to collisions.

Add an extra mapping step to allocate non conflicting texture
units for both uses.

The issue can be reproduced with a pair of simple shaders like
these:
 attribute vec4 in_mod;
 varying vec4 mod;
 void main() {
   mod = in_mod;
   gl_TexCoord[0] = gl_MultiTexCoord0;
   gl_Position = gl_ModelViewProjectionMatrix * gl_Vertex;
 }

 varying vec4 mod;
 uniform sampler2D tex;
 void main() {
   gl_FragColor = texture2D(tex, vec2(gl_TexCoord[0])) * mod;
 }

Fixes many piglit tests on i915:

glsl-link-varyings-2
glsl-orangebook-ch06-bump
interpolation-none-gl_frontcolor-smooth-fixed
interpolation-none-gl_frontcolor-smooth-none
interpolation-none-gl_frontcolor-smooth-vertex
interpolation-none-gl_frontsecondarycolor-smooth-fixed
interpolation-none-gl_frontsecondarycolor-smooth-vertex
interpolation-none-gl_frontsecondarycolor-smooth-none
interpolation-none-other-flat-fixed
interpolation-none-other-flat-none
interpolation-none-other-flat-vertex
interpolation-none-other-smooth-fixed
interpolation-none-other-smooth-none
interpolation-none-other-smooth-vertex

v2 [idr]: Minor formatting tweaks.

Signed-off-by: Ville Syrjälä 
Reviewed-by: Ian Romanick 
Cc: "11.0" 

---

 src/mesa/drivers/dri/i915/i915_context.h  |   14 ++---
 src/mesa/drivers/dri/i915/i915_fragprog.c |   83 +++--
 2 files changed, 71 insertions(+), 26 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/i915_context.h 
b/src/mesa/drivers/dri/i915/i915_context.h
index fa58ecb..d8f592b 100644
--- a/src/mesa/drivers/dri/i915/i915_context.h
+++ b/src/mesa/drivers/dri/i915/i915_context.h
@@ -115,6 +115,8 @@ enum {
I915_RASTER_RULES_SETUP_SIZE,
 };
 
+#define I915_TEX_UNITS 8
+
 #define I915_MAX_CONSTANT  32
 #define I915_CONSTANT_SIZE (2+(4*I915_MAX_CONSTANT))
 
@@ -194,7 +196,8 @@ struct i915_fragment_program
 
/* Helpers for i915_fragprog.c:
 */
-   GLuint wpos_tex;
+   uint8_t texcoord_mapping[I915_TEX_UNITS];
+   uint8_t wpos_tex;
bool depth_written;
 
struct
@@ -205,15 +208,6 @@ struct i915_fragment_program
GLuint nr_params;
 };
 
-
-
-
-
-
-
-#define I915_TEX_UNITS 8
-
-
 struct i915_hw_state
 {
GLuint Ctx[I915_CTX_SETUP_SIZE];
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c 
b/src/mesa/drivers/dri/i915/i915_fragprog.c
index 03c32e5..1a5943c 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -72,6 +72,22 @@ static const GLfloat cos_constants[4] = { 1.0,
-1.0 / (6 * 5 * 4 * 3 * 2 * 1)
 };
 
+/* texcoord_mapping[unit] = index | TEXCOORD_{TEX,VAR} */
+#define TEXCOORD_TEX (0<<7)
+#define TEXCOORD_VAR (1<<7)
+
+static unsigned
+get_texcoord_mapping(struct i915_fragment_program *p, uint8_t texcoord)
+{
+   for (unsigned i = 0; i < p->ctx->Const.MaxTextureCoordUnits; i++) {
+  if (p->texcoord_mapping[i] == texcoord)
+ return i;
+   }
+
+   /* blah */
+   return p->ctx->Const.MaxTextureCoordUnits - 1;
+}
+
 /**
  * Retrieve a ureg for the given source register.  Will emit
  * constants, apply swizzling and negation as needed.
@@ -82,6 +98,7 @@ src_vector(struct i915_fragment_program *p,
const struct gl_fragment_program *program)
 {
GLuint src;
+   unsigned unit;
 
switch (source->File) {
 
@@ -119,8 +136,10 @@ src_vector(struct i915_fragment_program *p,
   case VARYING_SLOT_TEX5:
   case VARYING_SLOT_TEX6:
   case VARYING_SLOT_TEX7:
+ unit = get_texcoord_mapping(p, (source->Index -
+ VARYING_SLOT_TEX0) | TEXCOORD_TEX);
  src = i915_emit_decl(p, REG_TYPE_T,
-  T_TEX0 + (source->Index - VARYING_SLOT_TEX0),
+  T_TEX0 + unit,
   D0_CHANNEL_ALL);
 break;
 
@@ -132,8 +151,10 @@ src_vector(struct i915_fragment_program *p,
   case VARYING_SLOT_VAR0 + 5:
   case VARYING_SLOT_VAR0 + 6:
   case VARYING_SLOT_VAR0 + 7:
+ unit = get_texcoord_mapping(p, (source->Index -
+ VARYING_SLOT_VAR0) | TEXCOORD_VAR);
  src = i915_emit_decl(p, REG_TYPE_T,
-  T_TEX0 + (source->Index - VARYING_SLOT_VAR0),
+  

Mesa (master): i965/miptree: Rename intel_miptree_map::mt -> ::linear_mt ( v2)

[Chad Versace]

Module: Mesa
Branch: master
Commit: 56367b0290919651e4c104b3e798cc5588272d3c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=56367b0290919651e4c104b3e798cc5588272d3c

Author: Chad Versace 
Date:   Fri Sep 25 09:52:26 2015 -0700

i965/miptree: Rename intel_miptree_map::mt -> ::linear_mt (v2)

Because that's what it is. It's an untiled, *linear* miptree.

v2:
  - Add space after /*.
  - Use one comment per function argument.

Reviewed-by: Anuj Phogat 
Acked-by: Ben Widawsky 

---

 src/mesa/drivers/dri/i965/intel_mipmap_tree.c |   30 +
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |2 +-
 2 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 9c0304c..727ef35 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2168,16 +2168,18 @@ intel_miptree_map_blit(struct brw_context *brw,
   struct intel_miptree_map *map,
   unsigned int level, unsigned int slice)
 {
-   map->mt = intel_miptree_create(brw, GL_TEXTURE_2D, mt->format,
-  0, 0,
-  map->w, map->h, 1,
-  0, MIPTREE_LAYOUT_TILING_NONE);
-
-   if (!map->mt) {
+   map->linear_mt = intel_miptree_create(brw, GL_TEXTURE_2D, mt->format,
+ /* first_level */ 0,
+ /* last_level */ 0,
+ map->w, map->h, 1,
+ /* samples */ 0,
+ MIPTREE_LAYOUT_TILING_NONE);
+
+   if (!map->linear_mt) {
   fprintf(stderr, "Failed to allocate blit temporary\n");
   goto fail;
}
-   map->stride = map->mt->pitch;
+   map->stride = map->linear_mt->pitch;
 
/* One of either READ_BIT or WRITE_BIT or both is set.  READ_BIT implies no
 * INVALIDATE_RANGE_BIT.  WRITE_BIT needs the original values read in unless
@@ -2188,7 +2190,7 @@ intel_miptree_map_blit(struct brw_context *brw,
   if (!intel_miptree_blit(brw,
   mt, level, slice,
   map->x, map->y, false,
-  map->mt, 0, 0,
+  map->linear_mt, 0, 0,
   0, 0, false,
   map->w, map->h, GL_COPY)) {
  fprintf(stderr, "Failed to blit\n");
@@ -2196,7 +2198,7 @@ intel_miptree_map_blit(struct brw_context *brw,
   }
}
 
-   map->ptr = intel_miptree_map_raw(brw, map->mt);
+   map->ptr = intel_miptree_map_raw(brw, map->linear_mt);
 
DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__,
map->x, map->y, map->w, map->h,
@@ -2206,7 +2208,7 @@ intel_miptree_map_blit(struct brw_context *brw,
return;
 
 fail:
-   intel_miptree_release(>mt);
+   intel_miptree_release(>linear_mt);
map->ptr = NULL;
map->stride = 0;
 }
@@ -2220,11 +,11 @@ intel_miptree_unmap_blit(struct brw_context *brw,
 {
struct gl_context *ctx = >ctx;
 
-   intel_miptree_unmap_raw(map->mt);
+   intel_miptree_unmap_raw(map->linear_mt);
 
if (map->mode & GL_MAP_WRITE_BIT) {
   bool ok = intel_miptree_blit(brw,
-   map->mt, 0, 0,
+   map->linear_mt, 0, 0,
0, 0, false,
mt, level, slice,
map->x, map->y, false,
@@ -2232,7 +2234,7 @@ intel_miptree_unmap_blit(struct brw_context *brw,
   WARN_ONCE(!ok, "Failed to blit from linear temporary mapping");
}
 
-   intel_miptree_release(>mt);
+   intel_miptree_release(>linear_mt);
 }
 
 /**
@@ -2756,7 +2758,7 @@ intel_miptree_unmap(struct brw_context *brw,
   intel_miptree_unmap_etc(brw, mt, map, level, slice);
} else if (mt->stencil_mt && !(map->mode & BRW_MAP_DIRECT_BIT)) {
   intel_miptree_unmap_depthstencil(brw, mt, map, level, slice);
-   } else if (map->mt) {
+   } else if (map->linear_mt) {
   intel_miptree_unmap_blit(brw, mt, map, level, slice);
 #if defined(USE_SSE41)
} else if (map->buffer && cpu_has_sse4_1) {
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 5eb5052..eba7203 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -82,7 +82,7 @@ struct intel_miptree_map {
/** Possibly malloced temporary buffer for the mapping. */
void *buffer;
/** Possible pointer to a temporary linear miptree for the mapping. */
-   struct intel_mipmap_tree *mt;
+   struct intel_mipmap_tree *linear_mt;
/** Pointer to the start of (map_x, map_y) returned by the mapping. */
  

Mesa (master): i965/miptree: Fix comments for map mode

[Chad Versace]

Module: Mesa
Branch: master
Commit: b7882ae6777d53b32f1625c6270cdc95e5b7b802
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7882ae6777d53b32f1625c6270cdc95e5b7b802

Author: Chad Versace 
Date:   Fri Sep 25 09:46:19 2015 -0700

i965/miptree: Fix comments for map mode

The comment for intel_miptree_map::mode claimed that it was a bitmask of
GL_MAP_{READ,WRITE,INVALIDATE}_BIT. In reality, the bitmask may include
any of {GL,BRW}_MAP_*_BIT.

Reviewed-by: Anuj Phogat 
Acked-by: Ben Widawsky 

---

 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 2e13783..5eb5052 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -75,7 +75,7 @@ struct intel_texture_image;
 #define BRW_MAP_DIRECT_BIT 0x8000
 
 struct intel_miptree_map {
-   /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
+   /** Bitfield of GL_MAP_*_BIT and BRW_MAP_*_BIT. */
GLbitfield mode;
/** Region of interest for the map. */
int x, y, w, h;

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Mesa (master): i965/miptree: Add PRM references for most struct members ( v2)

[Chad Versace]

Module: Mesa
Branch: master
Commit: b217e6f0351f185d7181712db2871611de2f89ea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b217e6f0351f185d7181712db2871611de2f89ea

Author: Chad Versace 
Date:   Fri Sep 25 11:16:13 2015 -0700

i965/miptree: Add PRM references for most struct members (v2)

Add comments that link the driver's miptree structures to the hardware
structures documented in the PRM.  This provides sorely needed
orientation to developers new to the miptree code. And for miptree
veterans, this clarifies some of the more obscure miptree data.

For each driver struct field that closely corresponds to a
hardware struct field, add a PRM reference to that hardware field's
name. For example,

struct intel_mipmap_tree {
   ...
   /**
* @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
*
* @see RENDER_SURFACE_STATE.SurfaceType
* @see RENDER_SURFACE_STATE.SurfaceArray
* @see 3DSTATE_DEPTH_BUFFER.SurfaceType
*/
   GLenum target;
   ...
};

Also annotate the INTEL_MSAA_LAYOUT_* enums with the name of the PRM
sections that documents the layout.

v2: Replace "2D subimage" with "slice", and define what a "slice" is.
For Ben.

Reviewed-by: Anuj Phogat  (v1)
Reviewed-by: Ben Widawsky  (v1)

---

 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  179 +
 1 file changed, 154 insertions(+), 25 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index e4acf8b..486e5c6 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -142,6 +142,9 @@ struct intel_mipmap_level
* \code
* x = mt->level[l].slice[s].x_offset
* y = mt->level[l].slice[s].y_offset
+   *
+   * On some hardware generations, we program these offsets into
+   * RENDER_SURFACE_STATE.XOffset and RENDER_SURFACE_STATE.YOffset.
*/
   GLuint x_offset;
   GLuint y_offset;
@@ -170,12 +173,16 @@ enum intel_msaa_layout
 * accommodated by scaling up the width and the height of the surface so
 * that all the samples corresponding to a pixel are located at nearby
 * memory locations.
+*
+* @see PRM section "Interleaved Multisampled Surfaces"
 */
INTEL_MSAA_LAYOUT_IMS,
 
/**
 * Uncompressed Multisample Surface.  The surface is stored as a 2D array,
 * with array slice n containing all pixel data for sample n.
+*
+* @see PRM section "Uncompressed Multisampled Surfaces"
 */
INTEL_MSAA_LAYOUT_UMS,
 
@@ -187,6 +194,8 @@ enum intel_msaa_layout
 * the common case (where all samples constituting a pixel have the same
 * color value) to be stored efficiently by just using a single array
 * slice.
+*
+* @see PRM section "Compressed Multisampled Surfaces"
 */
INTEL_MSAA_LAYOUT_CMS,
 };
@@ -320,14 +329,34 @@ enum miptree_array_layout {
  */
 struct intel_miptree_aux_buffer
 {
-   /** Buffer object containing the pixel data. */
+   /**
+* Buffer object containing the pixel data.
+*
+* @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
+* @see 3DSTATE_HIER_DEPTH_BUFFER.AuxiliarySurfaceBaseAddress
+*/
drm_intel_bo *bo;
 
-   uint32_t pitch; /**< pitch in bytes. */
+   /**
+* Pitch in bytes.
+*
+* @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
+* @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
+*/
+   uint32_t pitch;
 
-   uint32_t qpitch; /**< The distance in rows between array slices. */
+   /**
+* The distance in rows between array slices.
+*
+* @see RENDER_SURFACE_STATE.AuxiliarySurfaceQPitch
+* @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceQPitch
+*/
+   uint32_t qpitch;
 
-   struct intel_mipmap_tree *mt; /**< hiz miptree used with Gen6 */
+   /**
+* Hiz miptree. Used only by Gen6.
+*/
+   struct intel_mipmap_tree *mt;
 };
 
 /* Tile resource modes */
@@ -339,15 +368,49 @@ enum intel_miptree_tr_mode {
 
 struct intel_mipmap_tree
 {
-   /** Buffer object containing the pixel data. */
+   /**
+* Buffer object containing the surface.
+*
+* @see intel_mipmap_tree::offset
+* @see RENDER_SURFACE_STATE.SurfaceBaseAddress
+* @see RENDER_SURFACE_STATE.AuxiliarySurfaceBaseAddress
+* @see 3DSTATE_DEPTH_BUFFER.SurfaceBaseAddress
+* @see 3DSTATE_HIER_DEPTH_BUFFER.SurfaceBaseAddress
+* @see 3DSTATE_STENCIL_BUFFER.SurfaceBaseAddress
+*/
drm_intel_bo *bo;
 
-   uint32_t pitch; /**< pitch in bytes. */
+   /**
+* Pitch in bytes.
+*
+* @see RENDER_SURFACE_STATE.SurfacePitch
+* @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
+* @see 3DSTATE_DEPTH_BUFFER.SurfacePitch
+* @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
+* @see 3DSTATE_STENCIL_BUFFER.SurfacePitch
+*/
+   uint32_t pitch;
+
+   /**
+* One of the 

Mesa (master): i965/miptree: More comments for BRW_MAP_DIRECT_BIT (v2)

[Chad Versace]

Module: Mesa
Branch: master
Commit: bd191b7cc614f0c74320fff09d84c2cfaa7b8fcd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd191b7cc614f0c74320fff09d84c2cfaa7b8fcd

Author: Chad Versace 
Date:   Fri Sep 25 09:44:22 2015 -0700

i965/miptree: More comments for BRW_MAP_DIRECT_BIT (v2)

Clarify that this bit extends the set of GL_MAP_*_BIT enums.
Also fix typo of "temporary".

Reviewed-by: Anuj Phogat 
Acked-by: Ben Widawsky 

---

 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 7610d75..2e13783 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -62,9 +62,11 @@ struct intel_resolve_map;
 struct intel_texture_image;
 
 /**
+ * This bit extends the set of GL_MAP_*_BIT enums.
+ *
  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
- * tmeporary and recreate the kind of data requested by Mesa core, since we're
+ * temporary and recreate the kind of data requested by Mesa core, since we're
  * satisfying some glGetTexImage() request or something.
  *
  * However, occasionally you want to actually map the miptree's current data

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Mesa (master): i965/miptree: Rename align_w,align_h -> halign,valign

[Chad Versace]

Module: Mesa
Branch: master
Commit: f7fe9fb0f19196f74864e0b0f57ac61c066c9d10
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7fe9fb0f19196f74864e0b0f57ac61c066c9d10

Author: Chad Versace 
Date:   Fri Sep 25 10:04:48 2015 -0700

i965/miptree: Rename align_w,align_h -> halign,valign

The values of intel_mipmap_tree::align_w and ::align_h correspond to the
hardware enums HALIGN_* and VALIGN_*.

See the confusion?
align_h != HALIGN
align_h == VALIGN

Reduce the confusion by renaming the variables to match the hardware
enum names:
git ls-files |
xargs sed -i -e 's/align_w/halign/g' \
 -e 's/align_h/valign/g'

Suggested-by: Kenneth Graunke 
Acked-by: Ben Widawsky 
Reviewed-by: Anuj Phogat 

---

 src/mesa/drivers/dri/i965/brw_tex_layout.c|   62 ++---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c  |4 +-
 src/mesa/drivers/dri/i965/gen6_blorp.cpp  |2 +-
 src/mesa/drivers/dri/i965/gen6_surface_state.c|2 +-
 src/mesa/drivers/dri/i965/gen7_blorp.cpp  |4 +-
 src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |8 +--
 src/mesa/drivers/dri/i965/gen8_surface_state.c|   12 ++--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c |2 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |   18 --
 9 files changed, 62 insertions(+), 52 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c 
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 268b995..2955c8d 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -282,7 +282,7 @@ gen9_miptree_layout_1d(struct intel_mipmap_tree *mt)
/* When this layout is used the horizontal alignment is fixed at 64 and the
 * hardware ignores the value given in the surface state
 */
-   const unsigned int align_w = 64;
+   const unsigned int halign = 64;
 
mt->total_height = mt->physical_height0;
mt->total_width = 0;
@@ -292,7 +292,7 @@ gen9_miptree_layout_1d(struct intel_mipmap_tree *mt)
 
   intel_miptree_set_level_info(mt, level, x, 0, depth);
 
-  img_width = ALIGN(width, align_w);
+  img_width = ALIGN(width, halign);
 
   mt->total_width = MAX2(mt->total_width, x + img_width);
 
@@ -328,10 +328,10 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
unsigned mip1_width;
 
if (mt->compressed) {
-  mip1_width = ALIGN_NPOT(minify(mt->physical_width0, 1), mt->align_w) 
+
+  mip1_width = ALIGN_NPOT(minify(mt->physical_width0, 1), mt->halign) +
  ALIGN_NPOT(minify(mt->physical_width0, 2), bw);
} else {
-  mip1_width = ALIGN_NPOT(minify(mt->physical_width0, 1), mt->align_w) 
+
+  mip1_width = ALIGN_NPOT(minify(mt->physical_width0, 1), mt->halign) +
  minify(mt->physical_width0, 2);
}
 
@@ -348,7 +348,7 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
 
   intel_miptree_set_level_info(mt, level, x, y, depth);
 
-  img_height = ALIGN_NPOT(height, mt->align_h);
+  img_height = ALIGN_NPOT(height, mt->valign);
   if (mt->compressed)
 img_height /= bh;
 
@@ -365,7 +365,7 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
   /* Layout_below: step right after second mipmap.
*/
   if (level == mt->first_level + 1) {
-x += ALIGN_NPOT(width, mt->align_w) / bw;
+x += ALIGN_NPOT(width, mt->halign) / bw;
   } else {
 y += img_height;
   }
@@ -385,7 +385,7 @@ brw_miptree_get_horizontal_slice_pitch(const struct 
brw_context *brw,
 {
if ((brw->gen < 9 && mt->target == GL_TEXTURE_3D) ||
(brw->gen == 4 && mt->target == GL_TEXTURE_CUBE_MAP)) {
-  return ALIGN_NPOT(minify(mt->physical_width0, level), mt->align_w);
+  return ALIGN_NPOT(minify(mt->physical_width0, level), mt->halign);
} else {
   return 0;
}
@@ -426,13 +426,13 @@ brw_miptree_get_vertical_slice_pitch(const struct 
brw_context *brw,
} else if (mt->target == GL_TEXTURE_3D ||
   (brw->gen == 4 && mt->target == GL_TEXTURE_CUBE_MAP) ||
   mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
-  return ALIGN_NPOT(minify(mt->physical_height0, level), mt->align_h);
+  return ALIGN_NPOT(minify(mt->physical_height0, level), mt->valign);
 
} else {
-  const unsigned h0 = ALIGN_NPOT(mt->physical_height0, mt->align_h);
-  const unsigned h1 = ALIGN_NPOT(minify(mt->physical_height0, 1), 
mt->align_h);
+  const unsigned h0 = ALIGN_NPOT(mt->physical_height0, mt->valign);
+  const unsigned h1 = ALIGN_NPOT(minify(mt->physical_height0, 1), 
mt->valign);
 
-  return h0 + h1 + (brw->gen >= 7 ? 12 : 11) * mt->align_h;
+  return h0 + h1 + (brw->gen >= 7 ? 12 : 11) * mt->valign;
}
 }
 
@@ -502,9 +502,9 @@ brw_miptree_layout_texture_array(struct brw_context *brw,
 
for (unsigned level = 

Mesa (master): meta: Handle array textures in scaled MSAA blits

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 9bd9cf1fa402bf948020ee5d560259a5cfd2a739
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9bd9cf1fa402bf948020ee5d560259a5cfd2a739

Author: Ian Romanick 
Date:   Tue Sep 22 14:42:32 2015 -0700

meta: Handle array textures in scaled MSAA blits

The old code had some significant problems with respect to
sampler2DArray textures.  The biggest problem was that some of the code
would use vec3 for the texture coordinate type, and other parts of the
code would use vec2.  The resulting shader would not even compile.
Since there were not tests for this path, nobody noticed.

The input to the fragment shader is always treated as a vec3.  If the
source data is only vec2, the vertex puller will supply 0 for the .z
component.  The texture coordinate passed to the fragment shader is
always a vec2 that comes from the .xy part of the vertex shader input.
The layer, taken from the .z of the vertex shader input is passed
separately as a flat integer.  If the generated fragment shader does not
use the layer integer, the GLSL linker will eliminate all the dead code
in the vertex shader.

Fixes the new piglit tests "blit-scaled samples=2 with
gl_texture_2d_multisample_array", etc. on i965.

Note for stable maintainer: This patch may depend on 46037237, and that
patch should be safe for stable.

Signed-off-by: Ian Romanick 
Reviewed-by: Anuj Phogat 
Cc: Topi Pohjolainen 
Cc: Jordan Justen 
Cc: "10.6 11.0" 

---

 src/mesa/drivers/common/meta_blit.c |   35 ---
 1 file changed, 20 insertions(+), 15 deletions(-)

diff --git a/src/mesa/drivers/common/meta_blit.c 
b/src/mesa/drivers/common/meta_blit.c
index a41fe42..5972a5a 100644
--- a/src/mesa/drivers/common/meta_blit.c
+++ b/src/mesa/drivers/common/meta_blit.c
@@ -71,9 +71,7 @@ setup_glsl_msaa_blit_scaled_shader(struct gl_context *ctx,
char *sample_map_str = rzalloc_size(mem_ctx, 1);
char *sample_map_expr = rzalloc_size(mem_ctx, 1);
char *texel_fetch_macro = rzalloc_size(mem_ctx, 1);
-   const char *vs_source;
const char *sampler_array_suffix = "";
-   const char *texcoord_type = "vec2";
float y_scale;
enum blit_msaa_shader shader_index;
 
@@ -99,7 +97,6 @@ setup_glsl_msaa_blit_scaled_shader(struct gl_context *ctx,
   shader_index += BLIT_2X_MSAA_SHADER_2D_MULTISAMPLE_ARRAY_SCALED_RESOLVE -
   BLIT_2X_MSAA_SHADER_2D_MULTISAMPLE_SCALED_RESOLVE;
   sampler_array_suffix = "Array";
-  texcoord_type = "vec3";
}
 
if (blit->msaa_shaders[shader_index]) {
@@ -150,28 +147,37 @@ setup_glsl_msaa_blit_scaled_shader(struct gl_context *ctx,
   "   const int sample_map[%d] = int[%d](%s);\n",
   samples, samples, sample_map_str);
 
-   ralloc_asprintf_append(_fetch_macro,
-  "#define TEXEL_FETCH(coord) texelFetch(texSampler, 
i%s(coord), %s);\n",
-  texcoord_type, sample_number);
+   if (target == GL_TEXTURE_2D_MULTISAMPLE) {
+  ralloc_asprintf_append(_fetch_macro,
+ "#define TEXEL_FETCH(coord) 
texelFetch(texSampler, ivec2(coord), %s);\n",
+ sample_number);
+   } else {
+  ralloc_asprintf_append(_fetch_macro,
+ "#define TEXEL_FETCH(coord) 
texelFetch(texSampler, ivec3(coord, layer), %s);\n",
+ sample_number);
+   }
 
-   vs_source = ralloc_asprintf(mem_ctx,
+   static const char vs_source[] =
"#version 130\n"
"in vec2 position;\n"
-   "in %s textureCoords;\n"
-   "out %s texCoords;\n"
+   "in vec3 textureCoords;\n"
+   "out vec2 texCoords;\n"
+   "flat out int layer;\n"
"void main()\n"
"{\n"
-   "   texCoords = textureCoords;\n"
+   "   texCoords = textureCoords.xy;\n"
+   "   layer = int(textureCoords.z);\n"
"   gl_Position = vec4(position, 0.0, 1.0);\n"
-   "}\n",
-   texcoord_type,
-   texcoord_type);
+   "}\n"
+  ;
+
fs_source = ralloc_asprintf(mem_ctx,
"#version 130\n"
"#extension GL_ARB_texture_multisample : 
enable\n"
"uniform sampler2DMS%s texSampler;\n"
"uniform float src_width, src_height;\n"
-   "in %s texCoords;\n"
+

Mesa (master): mesa: use strtok_s for strtok_r on windows

[Tapani Pälli]

Module: Mesa
Branch: master
Commit: ca2e16d26ec46e604c76ab72d3ec14a7a8643cc8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca2e16d26ec46e604c76ab72d3ec14a7a8643cc8

Author: Tapani Pälli 
Date:   Wed Sep 30 20:38:13 2015 +0300

mesa: use strtok_s for strtok_r on windows

https://msdn.microsoft.com/en-us/library/ftsafwz3.aspx

v2: use _WIN32 instead of _MSC_VER (Brian Paul)

Signed-off-by: Tapani Pälli 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92183
Reviewed-by: Brian Paul 

---

 src/mesa/main/imports.h |3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/main/imports.h b/src/mesa/main/imports.h
index d61279a..9024758 100644
--- a/src/mesa/main/imports.h
+++ b/src/mesa/main/imports.h
@@ -423,6 +423,9 @@ _mesa_vsnprintf(char *str, size_t size, const char *fmt, 
va_list arg);
 #define snprintf _snprintf
 #endif
 
+#if defined(_WIN32) && !defined(strtok_r)
+#define strtok_r strtok_s
+#endif
 
 #ifdef __cplusplus
 }

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Mesa (master): i965: Get rid of prog_data compare functions

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 3948ac19a40663bd00deb84518ac747daa5f401f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3948ac19a40663bd00deb84518ac747daa5f401f

Author: Jason Ekstrand 
Date:   Tue Sep 29 18:06:49 2015 -0700

i965: Get rid of prog_data compare functions

They are no longer used.

Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_context.h |   27 +--
 src/mesa/drivers/dri/i965/brw_cs.c  |   21 -
 src/mesa/drivers/dri/i965/brw_cs.h  |2 --
 src/mesa/drivers/dri/i965/brw_gs.c  |   21 -
 src/mesa/drivers/dri/i965/brw_gs.h  |2 --
 src/mesa/drivers/dri/i965/brw_program.c |   17 -
 src/mesa/drivers/dri/i965/brw_program.h |4 
 src/mesa/drivers/dri/i965/brw_vs.c  |   21 -
 src/mesa/drivers/dri/i965/brw_vs.h  |1 -
 src/mesa/drivers/dri/i965/brw_wm.c  |   19 ---
 src/mesa/drivers/dri/i965/brw_wm.h  |1 -
 11 files changed, 1 insertion(+), 135 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 3bae90d..1dd48f6 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -340,9 +340,6 @@ struct brw_shader {
bool compiled_once;
 };
 
-/* Note: If adding fields that need anything besides a normal memcmp() for
- * comparing them, be sure to go fix brw_stage_prog_data_compare().
- */
 struct brw_stage_prog_data {
struct {
   /** size of our binding table. */
@@ -378,18 +375,11 @@ struct brw_stage_prog_data {
 
/* Pointers to tracked values (only valid once
 * _mesa_load_state_parameters has been called at runtime).
-*
-* These must be the last fields of the struct (see
-* brw_stage_prog_data_compare()).
 */
const gl_constant_value **param;
const gl_constant_value **pull_param;
 
-   /**
-* Image metadata passed to the shader as uniforms.  This is deliberately
-* ignored by brw_stage_prog_data_compare() because its contents don't have
-* any influence on program compilation.
-*/
+   /** Image metadata passed to the shader as uniforms. */
struct brw_image_param *image_param;
 };
 
@@ -443,9 +433,6 @@ struct brw_image_param {
  * there can be many of these, each in a different GL state
  * corresponding to a different brw_wm_prog_key struct, with different
  * compiled programs.
- *
- * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
- * struct!
  */
 struct brw_wm_prog_data {
struct brw_stage_prog_data base;
@@ -489,9 +476,6 @@ struct brw_wm_prog_data {
int urb_setup[VARYING_SLOT_MAX];
 };
 
-/* Note: brw_cs_prog_data_compare() must be updated when adding fields to this
- * struct!
- */
 struct brw_cs_prog_data {
struct brw_stage_prog_data base;
 
@@ -692,9 +676,6 @@ enum shader_dispatch_mode {
DISPATCH_MODE_SIMD8 = 3,
 };
 
-/* Note: brw_vue_prog_data_compare() must be updated when adding fields to
- * this struct!
- */
 struct brw_vue_prog_data {
struct brw_stage_prog_data base;
struct brw_vue_map vue_map;
@@ -712,9 +693,6 @@ struct brw_vue_prog_data {
 };
 
 
-/* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
- * struct!
- */
 struct brw_vs_prog_data {
struct brw_vue_prog_data base;
 
@@ -774,9 +752,6 @@ struct brw_vs_prog_data {
 
 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
 
-/* Note: brw_gs_prog_data_compare() must be updated when adding fields to
- * this struct!
- */
 struct brw_gs_prog_data
 {
struct brw_vue_prog_data base;
diff --git a/src/mesa/drivers/dri/i965/brw_cs.c 
b/src/mesa/drivers/dri/i965/brw_cs.c
index cb3fae6..02eeeda 100644
--- a/src/mesa/drivers/dri/i965/brw_cs.c
+++ b/src/mesa/drivers/dri/i965/brw_cs.c
@@ -31,27 +31,6 @@
 #include "brw_state.h"
 #include "intel_batchbuffer.h"
 
-bool
-brw_cs_prog_data_compare(const void *in_a, const void *in_b)
-{
-   const struct brw_cs_prog_data *a =
-  (const struct brw_cs_prog_data *)in_a;
-   const struct brw_cs_prog_data *b =
-  (const struct brw_cs_prog_data *)in_b;
-
-   /* Compare the base structure. */
-   if (!brw_stage_prog_data_compare(>base, >base))
-  return false;
-
-   /* Compare the rest of the structure. */
-   const unsigned offset = sizeof(struct brw_stage_prog_data);
-   if (memcmp(((char *) a) + offset, ((char *) b) + offset,
-  sizeof(struct brw_cs_prog_data) - offset))
-  return false;
-
-   return true;
-}
-
 static bool
 brw_codegen_cs_prog(struct brw_context *brw,
 struct gl_shader_program *prog,
diff --git a/src/mesa/drivers/dri/i965/brw_cs.h 
b/src/mesa/drivers/dri/i965/brw_cs.h
index 746fb05..0018c04 100644
--- a/src/mesa/drivers/dri/i965/brw_cs.h
+++ b/src/mesa/drivers/dri/i965/brw_cs.h
@@ -36,8 +36,6 @@ struct brw_cs_prog_key {
 extern "C" {
 #endif
 
-bool 

Mesa (master): i965/state_cache: Remove the aux_compare fields

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: bfdc76c133bb9e91049824b7480f862f142e4195
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfdc76c133bb9e91049824b7480f862f142e4195

Author: Jason Ekstrand 
Date:   Tue Sep 29 18:05:55 2015 -0700

i965/state_cache: Remove the aux_compare fields

They haven't been used since 1bba29ed403e735ba0bf04ed8aa2e571884fcaaf so
there's no good reason to keep them around.

Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_context.h |7 ---
 src/mesa/drivers/dri/i965/brw_state_cache.c |4 
 2 files changed, 11 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 8b790fe..3bae90d 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -869,7 +869,6 @@ struct brw_cache_item {
 };
 
 
-typedef bool (*cache_aux_compare_func)(const void *a, const void *b);
 typedef void (*cache_aux_free_func)(const void *aux);
 
 struct brw_cache {
@@ -882,12 +881,6 @@ struct brw_cache {
uint32_t next_offset;
bool bo_used_by_gpu;
 
-   /**
-* Optional functions used in determining whether the prog_data for a new
-* cache item matches an existing cache item (in case there's relevant data
-* outside of the prog_data).  If NULL, a plain memcmp is done.
-*/
-   cache_aux_compare_func aux_compare[BRW_MAX_CACHE];
/** Optional functions for freeing other pointers attached to a prog_data. 
*/
cache_aux_free_func aux_free[BRW_MAX_CACHE];
 };
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c 
b/src/mesa/drivers/dri/i965/brw_state_cache.c
index fbc0419..2fbcd14 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -350,10 +350,6 @@ brw_init_caches(struct brw_context *brw)
if (brw->has_llc)
   drm_intel_gem_bo_map_unsynchronized(cache->bo);
 
-   cache->aux_compare[BRW_CACHE_VS_PROG] = brw_vs_prog_data_compare;
-   cache->aux_compare[BRW_CACHE_GS_PROG] = brw_gs_prog_data_compare;
-   cache->aux_compare[BRW_CACHE_FS_PROG] = brw_wm_prog_data_compare;
-   cache->aux_compare[BRW_CACHE_CS_PROG] = brw_cs_prog_data_compare;
cache->aux_free[BRW_CACHE_VS_PROG] = brw_stage_prog_data_free;
cache->aux_free[BRW_CACHE_GS_PROG] = brw_stage_prog_data_free;
cache->aux_free[BRW_CACHE_FS_PROG] = brw_stage_prog_data_free;

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Mesa (master): i965/copy_image: Fix a copy+past error

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: a4734b34b3928ca6150b8d93f402da54ed69e6e7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4734b34b3928ca6150b8d93f402da54ed69e6e7

Author: Jason Ekstrand 
Date:   Mon Sep 28 16:57:27 2015 -0700

i965/copy_image: Fix a copy+past error

Reported-by: Ilia Mirkin 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/intel_copy_image.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_copy_image.c 
b/src/mesa/drivers/dri/i965/intel_copy_image.c
index d57651c..0a3337e 100644
--- a/src/mesa/drivers/dri/i965/intel_copy_image.c
+++ b/src/mesa/drivers/dri/i965/intel_copy_image.c
@@ -235,7 +235,7 @@ intel_copy_image_sub_data(struct gl_context *ctx,
} else {
   assert(dst_renderbuffer);
   dst_mt = intel_renderbuffer(dst_renderbuffer)->mt;
-  src_image = src_renderbuffer->TexImage;
+  dst_image = dst_renderbuffer->TexImage;
}
 
if (src_mt->num_samples > 0 || dst_mt->num_samples > 0) {

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