Mesa (master): st/mesa: fix sRGB BlitFramebuffer regression

[Marek Olšák]

Module: Mesa
Branch: master
Commit: b662c70aeab6a92751514f30719c13a6de253b40
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b662c70aeab6a92751514f30719c13a6de253b40

Author: Nicolai Hähnle 
Date:   Thu Aug 11 13:06:47 2016 +0200

st/mesa: fix sRGB BlitFramebuffer regression

Broken since: 3190c7ee9727161d627f107c2e7f8ec3a11941c1

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97285

Tested-by: Edmondo Tommasina 
Signed-off-by: Marek Olšák 

---

 src/mesa/state_tracker/st_cb_blit.c | 34 ++
 1 file changed, 18 insertions(+), 16 deletions(-)

diff --git a/src/mesa/state_tracker/st_cb_blit.c 
b/src/mesa/state_tracker/st_cb_blit.c
index cfcf3f7..8aa849b 100644
--- a/src/mesa/state_tracker/st_cb_blit.c
+++ b/src/mesa/state_tracker/st_cb_blit.c
@@ -45,15 +45,6 @@
 #include "util/u_format.h"
 
 static void
-st_adjust_blit_for_srgb(struct pipe_blit_info *blit, bool framebuffer_srgb)
-{
-   if (!framebuffer_srgb) {
-  blit->dst.format = util_format_linear(blit->dst.format);
-  blit->src.format = util_format_linear(blit->src.format);
-   }
-}
-
-static void
 st_BlitFramebuffer(struct gl_context *ctx,
struct gl_framebuffer *readFB,
struct gl_framebuffer *drawFB,
@@ -199,7 +190,11 @@ st_BlitFramebuffer(struct gl_context *ctx,
st_renderbuffer(drawFB->_ColorDrawBuffers[i]);
 
 if (dstRb) {
-   struct pipe_surface *dstSurf = dstRb->surface;
+   struct pipe_surface *dstSurf;
+
+   st_update_renderbuffer_surface(st, dstRb);
+
+   dstSurf = dstRb->surface;
 
if (dstSurf) {
   blit.dst.resource = dstSurf->texture;
@@ -212,7 +207,8 @@ st_BlitFramebuffer(struct gl_context *ctx,
   blit.src.box.z = srcAtt->Zoffset + srcAtt->CubeMapFace;
   blit.src.format = srcObj->pt->format;
 
-  st_adjust_blit_for_srgb(, ctx->Color.sRGBEnabled);
+  if (!ctx->Color.sRGBEnabled)
+ blit.src.format = util_format_linear(blit.src.format);
 
   st->pipe->blit(st->pipe, );
   dstRb->defined = true; /* front buffer tracking */
@@ -226,9 +222,13 @@ st_BlitFramebuffer(struct gl_context *ctx,
  struct pipe_surface *srcSurf;
  GLuint i;
 
- if (!srcRb || !srcRb->surface) {
+ if (!srcRb)
+return;
+
+ st_update_renderbuffer_surface(st, srcRb);
+
+ if (!srcRb->surface)
 return;
- }
 
  srcSurf = srcRb->surface;
 
@@ -237,7 +237,11 @@ st_BlitFramebuffer(struct gl_context *ctx,
st_renderbuffer(drawFB->_ColorDrawBuffers[i]);
 
 if (dstRb) {
-   struct pipe_surface *dstSurf = dstRb->surface;
+   struct pipe_surface *dstSurf;
+
+   st_update_renderbuffer_surface(st, dstRb);
+
+   dstSurf = dstRb->surface;
 
if (dstSurf) {
   blit.dst.resource = dstSurf->texture;
@@ -250,8 +254,6 @@ st_BlitFramebuffer(struct gl_context *ctx,
   blit.src.box.z = srcSurf->u.tex.first_layer;
   blit.src.format = srcSurf->format;
 
-  st_adjust_blit_for_srgb(, ctx->Color.sRGBEnabled);
-
   st->pipe->blit(st->pipe, );
   dstRb->defined = true; /* front buffer tracking */
}

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Mesa (master): loader/dri3: Overhaul dri3_update_num_back

[Michel Dänzer]

Module: Mesa
Branch: master
Commit: 1e3218bc5ba2b739261f0c0bacf4eb662d377236
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e3218bc5ba2b739261f0c0bacf4eb662d377236

Author: Michel Dänzer 
Date:   Wed Aug 17 17:02:04 2016 +0900

loader/dri3: Overhaul dri3_update_num_back

Always use 3 buffers when flipping. With only 2 buffers, we have to wait
for a flip to complete (which takes non-0 time even with asynchronous
flips) before we can start working on the next frame. We were previously
only using 2 buffers for flipping if the X server supports asynchronous
flips, even when we're not using asynchronous flips. This could result
in bad performance (the referenced bug report is an extreme case, where
the inter-frame stalls were preventing the GPU from reaching its maximum
clocks).

I couldn't measure any performance boost using 4 buffers with flipping.
Performance actually seemed to go down slightly, but that might have
been just noise.

Without flipping, a single back buffer is enough for swap interval 0,
but we need to use 2 back buffers when the swap interval is non-0,
otherwise we have to wait for the swap interval to pass before we can
start working on the next frame. This condition was previously reversed.

Cc: "12.0 11.2" 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97260
Reviewed-by: Frank Binns 
Reviewed-by: Eric Anholt 

---

 src/loader/loader_dri3_helper.c | 15 ++-
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/src/loader/loader_dri3_helper.c b/src/loader/loader_dri3_helper.c
index e9fb97b..86ae5ae 100644
--- a/src/loader/loader_dri3_helper.c
+++ b/src/loader/loader_dri3_helper.c
@@ -68,15 +68,12 @@ dri3_fence_await(xcb_connection_t *c, struct 
loader_dri3_buffer *buffer)
 static void
 dri3_update_num_back(struct loader_dri3_drawable *draw)
 {
-   draw->num_back = 1;
-   if (draw->flipping) {
-  if (!draw->is_pixmap &&
-  !(draw->present_capabilities & XCB_PRESENT_CAPABILITY_ASYNC))
- draw->num_back++;
-  draw->num_back++;
-   }
-   if (draw->vtable->get_swap_interval(draw) == 0)
-  draw->num_back++;
+   if (draw->flipping)
+  draw->num_back = 3;
+   else if (draw->vtable->get_swap_interval(draw) != 0)
+  draw->num_back = 2;
+   else
+  draw->num_back = 1;
 }
 
 void

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Mesa (master): radeonsi: disable SDMA texture copying on Carrizo

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 3ff0b67e1b6b492d5793c1580f4be0c6f58a1bc2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ff0b67e1b6b492d5793c1580f4be0c6f58a1bc2

Author: Marek Olšák 
Date:   Wed Aug 24 23:34:01 2016 +0200

radeonsi: disable SDMA texture copying on Carrizo

Cc: 12.0 
Reviewed-by: Michel Dänzer 

---

 src/gallium/drivers/radeonsi/cik_sdma.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c 
b/src/gallium/drivers/radeonsi/cik_sdma.c
index a36bbce..d15d8dc 100644
--- a/src/gallium/drivers/radeonsi/cik_sdma.c
+++ b/src/gallium/drivers/radeonsi/cik_sdma.c
@@ -520,6 +520,12 @@ static void cik_sdma_copy(struct pipe_context *ctx,
return;
}
 
+   /* Carrizo SDMA texture copying is very broken for some users.
+* https://bugs.freedesktop.org/show_bug.cgi?id=97029
+*/
+   if (sctx->b.family == CHIP_CARRIZO)
+   goto fallback;
+
if (cik_sdma_copy_texture(sctx, dst, dst_level, dstx, dsty, dstz,
  src, src_level, src_box))
return;

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Mesa (master): gallium/noop: use 3-space indentation

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 1276316d67b3a663175a26802536b8fd6addc9b0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1276316d67b3a663175a26802536b8fd6addc9b0

Author: Marek Olšák 
Date:   Sun Aug 21 12:41:29 2016 +0200

gallium/noop: use 3-space indentation

Reviewed-by: Brian Paul 

---

 src/gallium/drivers/noop/noop_pipe.c  | 314 +-
 src/gallium/drivers/noop/noop_state.c | 270 ++---
 2 files changed, 292 insertions(+), 292 deletions(-)

diff --git a/src/gallium/drivers/noop/noop_pipe.c 
b/src/gallium/drivers/noop/noop_pipe.c
index 4eb6051..b3e2a3e 100644
--- a/src/gallium/drivers/noop/noop_pipe.c
+++ b/src/gallium/drivers/noop/noop_pipe.c
@@ -36,26 +36,26 @@ DEBUG_GET_ONCE_BOOL_OPTION(noop, "GALLIUM_NOOP", FALSE)
 void noop_init_state_functions(struct pipe_context *ctx);
 
 struct noop_pipe_screen {
-   struct pipe_screen  pscreen;
-   struct pipe_screen  *oscreen;
+   struct pipe_screen  pscreen;
+   struct pipe_screen  *oscreen;
 };
 
 /*
  * query
  */
 struct noop_query {
-   unsignedquery;
+   unsignedquery;
 };
 static struct pipe_query *noop_create_query(struct pipe_context *ctx, unsigned 
query_type, unsigned index)
 {
-   struct noop_query *query = CALLOC_STRUCT(noop_query);
+   struct noop_query *query = CALLOC_STRUCT(noop_query);
 
-   return (struct pipe_query *)query;
+   return (struct pipe_query *)query;
 }
 
 static void noop_destroy_query(struct pipe_context *ctx, struct pipe_query 
*query)
 {
-   FREE(query);
+   FREE(query);
 }
 
 static boolean noop_begin_query(struct pipe_context *ctx, struct pipe_query 
*query)
@@ -69,14 +69,14 @@ static bool noop_end_query(struct pipe_context *ctx, struct 
pipe_query *query)
 }
 
 static boolean noop_get_query_result(struct pipe_context *ctx,
-   struct pipe_query *query,
-   boolean wait,
-   union pipe_query_result *vresult)
+ struct pipe_query *query,
+ boolean wait,
+ union pipe_query_result *vresult)
 {
-   uint64_t *result = (uint64_t*)vresult;
+   uint64_t *result = (uint64_t*)vresult;
 
-   *result = 0;
-   return TRUE;
+   *result = 0;
+   return TRUE;
 }
 
 static void
@@ -89,67 +89,67 @@ noop_set_active_query_state(struct pipe_context *pipe, 
boolean enable)
  * resource
  */
 struct noop_resource {
-   struct pipe_resourcebase;
-   unsignedsize;
-   char*data;
-   struct sw_displaytarget *dt;
+   struct pipe_resourcebase;
+   unsignedsize;
+   char*data;
+   struct sw_displaytarget *dt;
 };
 
 static struct pipe_resource *noop_resource_create(struct pipe_screen *screen,
-   const struct pipe_resource 
*templ)
+  const struct pipe_resource 
*templ)
 {
-   struct noop_resource *nresource;
-   unsigned stride;
+   struct noop_resource *nresource;
+   unsigned stride;
 
-   nresource = CALLOC_STRUCT(noop_resource);
-   if (!nresource)
-   return NULL;
+   nresource = CALLOC_STRUCT(noop_resource);
+   if (!nresource)
+  return NULL;
 
-   stride = util_format_get_stride(templ->format, templ->width0);
-   nresource->base = *templ;
-   nresource->base.screen = screen;
-   nresource->size = stride * templ->height0 * templ->depth0;
-   nresource->data = MALLOC(nresource->size);
-   pipe_reference_init(>base.reference, 1);
-   if (nresource->data == NULL) {
-   FREE(nresource);
-   return NULL;
-   }
-   return >base;
+   stride = util_format_get_stride(templ->format, templ->width0);
+   nresource->base = *templ;
+   nresource->base.screen = screen;
+   nresource->size = stride * templ->height0 * templ->depth0;
+   nresource->data = MALLOC(nresource->size);
+   pipe_reference_init(>base.reference, 1);
+   if (nresource->data == NULL) {
+  FREE(nresource);
+  return NULL;
+   }
+   return >base;
 }
 
 static struct pipe_resource *noop_resource_from_handle(struct pipe_screen 
*screen,
-   const struct 
pipe_resource *templ,
-   struct winsys_handle 
*handle,
+   const struct 
pipe_resource *templ,
+   struct winsys_handle 
*handle,
unsigned usage)
 {
-   struct noop_pipe_screen *noop_screen = (struct noop_pipe_screen*)screen;
-   struct pipe_screen *oscreen = noop_screen->oscreen;
-   struct pipe_resource 

Mesa (master): gallium: add a pipe_context parameter to resource_get_handle

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 9daaa6f5a66ab6cc99c6f0af37fc1007ab3d09af
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9daaa6f5a66ab6cc99c6f0af37fc1007ab3d09af

Author: Marek Olšák 
Date:   Sun Aug 21 12:24:59 2016 +0200

gallium: add a pipe_context parameter to resource_get_handle

radeonsi needs to do some operations (DCC decompression) for OpenGL-OpenCL
interop and this is the only way to make it coherent with the current
context. It can optionally be set to NULL.

Reviewed-by: Brian Paul 

---

 src/gallium/auxiliary/util/u_transfer.c   |  1 +
 src/gallium/auxiliary/util/u_transfer.h   |  1 +
 src/gallium/auxiliary/vl/vl_winsys_dri3.c |  2 +-
 src/gallium/drivers/ddebug/dd_screen.c|  4 +++-
 src/gallium/drivers/ilo/ilo_resource.c|  1 +
 src/gallium/drivers/llvmpipe/lp_texture.c |  1 +
 src/gallium/drivers/noop/noop_pipe.c  |  1 +
 src/gallium/drivers/r300/r300_texture.c   |  1 +
 src/gallium/drivers/r300/r300_texture.h   |  1 +
 src/gallium/drivers/radeon/r600_texture.c |  1 +
 src/gallium/drivers/rbug/rbug_screen.c|  5 -
 src/gallium/drivers/softpipe/sp_texture.c |  1 +
 src/gallium/drivers/trace/tr_screen.c |  5 -
 src/gallium/include/pipe/p_screen.h   |  7 +++
 src/gallium/state_trackers/dri/dri2.c | 13 +++--
 src/gallium/state_trackers/nine/swapchain9.c  |  3 ++-
 src/gallium/state_trackers/va/buffer.c|  3 ++-
 src/gallium/state_trackers/vdpau/output.c |  3 ++-
 src/gallium/state_trackers/vdpau/surface.c|  3 ++-
 src/gallium/state_trackers/xa/xa_tracker.c|  3 ++-
 src/gallium/winsys/sw/wrapper/wrapper_sw_winsys.c |  2 +-
 21 files changed, 46 insertions(+), 16 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_transfer.c 
b/src/gallium/auxiliary/util/u_transfer.c
index 82cf68d..ba4b9dc 100644
--- a/src/gallium/auxiliary/util/u_transfer.c
+++ b/src/gallium/auxiliary/util/u_transfer.c
@@ -111,6 +111,7 @@ u_resource( struct pipe_resource *res )
 }
 
 boolean u_resource_get_handle_vtbl(struct pipe_screen *screen,
+   struct pipe_context *ctx,
struct pipe_resource *resource,
struct winsys_handle *handle,
unsigned usage)
diff --git a/src/gallium/auxiliary/util/u_transfer.h 
b/src/gallium/auxiliary/util/u_transfer.h
index 7f680bc..ab787ab 100644
--- a/src/gallium/auxiliary/util/u_transfer.h
+++ b/src/gallium/auxiliary/util/u_transfer.h
@@ -73,6 +73,7 @@ struct u_resource {
 
 
 boolean u_resource_get_handle_vtbl(struct pipe_screen *screen,
+   struct pipe_context *ctx,
struct pipe_resource *resource,
struct winsys_handle *handle,
unsigned usage);
diff --git a/src/gallium/auxiliary/vl/vl_winsys_dri3.c 
b/src/gallium/auxiliary/vl/vl_winsys_dri3.c
index 61d6205..3d596a6 100644
--- a/src/gallium/auxiliary/vl/vl_winsys_dri3.c
+++ b/src/gallium/auxiliary/vl/vl_winsys_dri3.c
@@ -243,7 +243,7 @@ dri3_alloc_back_buffer(struct vl_dri3_screen *scrn)
memset(, 0, sizeof(whandle));
whandle.type= DRM_API_HANDLE_TYPE_FD;
usage = PIPE_HANDLE_USAGE_EXPLICIT_FLUSH | PIPE_HANDLE_USAGE_READ;
-   scrn->base.pscreen->resource_get_handle(scrn->base.pscreen,
+   scrn->base.pscreen->resource_get_handle(scrn->base.pscreen, NULL,
buffer->texture, ,
usage);
buffer_fd = whandle.handle;
diff --git a/src/gallium/drivers/ddebug/dd_screen.c 
b/src/gallium/drivers/ddebug/dd_screen.c
index 3deba0a..4050e39 100644
--- a/src/gallium/drivers/ddebug/dd_screen.c
+++ b/src/gallium/drivers/ddebug/dd_screen.c
@@ -237,13 +237,15 @@ dd_screen_resource_destroy(struct pipe_screen *_screen,
 
 static boolean
 dd_screen_resource_get_handle(struct pipe_screen *_screen,
+  struct pipe_context *_pipe,
   struct pipe_resource *resource,
   struct winsys_handle *handle,
   unsigned usage)
 {
struct pipe_screen *screen = dd_screen(_screen)->screen;
+   struct pipe_context *pipe = dd_context(_pipe)->pipe;
 
-   return screen->resource_get_handle(screen, resource, handle, usage);
+   return screen->resource_get_handle(screen, pipe, resource, handle, usage);
 }
 
 
diff --git a/src/gallium/drivers/ilo/ilo_resource.c 
b/src/gallium/drivers/ilo/ilo_resource.c
index 0afbfc6..7961288 100644
--- a/src/gallium/drivers/ilo/ilo_resource.c
+++ b/src/gallium/drivers/ilo/ilo_resource.c
@@ -725,6 +725,7 @@ ilo_resource_from_handle(struct pipe_screen *screen,
 
 static boolean
 ilo_resource_get_handle(struct pipe_screen 

Mesa (master): swrast: fix incorrectly positioned putImage() in swrast driver

[Brian Paul]

Module: Mesa
Branch: master
Commit: 2a2dc416b6816ac8914c5f45ac80545d2c09246f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a2dc416b6816ac8914c5f45ac80545d2c09246f

Author: Brian Paul 
Date:   Wed Aug 24 08:52:29 2016 -0600

swrast: fix incorrectly positioned putImage() in swrast driver

Some front buffer rendering was in the wrong position.  This included
scissored clears, glDrawPixels and glCopyPixels.  The problem was the
y coordinate passed to putImage() didn't match the y coordinate passed
to getImage().

We fix this by setting xrb->map_y to the inverted coordinate in
swrast_map_renderbuffer() which is used later by the putImage() call.
Also pass xrb->map_y to getImage() to be symmetric.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97426
Cc: 
Reviewed-by: Eric Anholt 

---

 src/mesa/drivers/dri/swrast/swrast.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/swrast/swrast.c 
b/src/mesa/drivers/dri/swrast/swrast.c
index 6d3b00b..0402232 100644
--- a/src/mesa/drivers/dri/swrast/swrast.c
+++ b/src/mesa/drivers/dri/swrast/swrast.c
@@ -484,14 +484,14 @@ swrast_map_renderbuffer(struct gl_context *ctx,
 
   xrb->map_mode = mode;
   xrb->map_x = x;
-  xrb->map_y = y;
+  xrb->map_y = rb->Height - y - h;
   xrb->map_w = w;
   xrb->map_h = h;
 
   stride = w * cpp;
   xrb->Base.Buffer = malloc(h * stride);
 
-  sPriv->swrast_loader->getImage(dPriv, x, rb->Height - y - h, w, h,
+  sPriv->swrast_loader->getImage(dPriv, x, xrb->map_y, w, h,
 (char *) xrb->Base.Buffer,
 dPriv->loaderPrivate);
 

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Mesa (master): meta: Always do GenerateMipmaps in linear colorspace.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 6cf8708ce55fb38c400c8f005e55170f54241187
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6cf8708ce55fb38c400c8f005e55170f54241187

Author: Kenneth Graunke 
Date:   Fri Aug 12 14:48:54 2016 -0700

meta: Always do GenerateMipmaps in linear colorspace.

When generating mipmaps for sRGB textures, force both decode and encode,
so the filtering is done in linear colorspace, regardless of settings.

Fixes a WebGL conformance test in Chrome:
https://www.khronos.org/registry/webgl/sdk/tests/conformance2/textures/misc/tex-srgb-mipmap.html?webglVersion=2

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97322
Signed-off-by: Kenneth Graunke 
Reviewed-by: Topi Pohjolainen 

---

 src/mesa/drivers/common/meta_generate_mipmap.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/common/meta_generate_mipmap.c 
b/src/mesa/drivers/common/meta_generate_mipmap.c
index 9cebbf7..bbe9d6d 100644
--- a/src/mesa/drivers/common/meta_generate_mipmap.c
+++ b/src/mesa/drivers/common/meta_generate_mipmap.c
@@ -221,9 +221,17 @@ _mesa_meta_GenerateMipmap(struct gl_context *ctx, GLenum 
target,
 GL_LINEAR);
   _mesa_set_sampler_wrap(ctx, mipmap->samp_obj, GL_CLAMP_TO_EDGE,
  GL_CLAMP_TO_EDGE, GL_CLAMP_TO_EDGE);
+   }
+
+   if (ctx->Extensions.EXT_texture_sRGB_decode) {
+  const struct gl_texture_image *baseImage =
+ _mesa_select_tex_image(texObj, target, texObj->BaseLevel);
+  const bool srgb =
+ _mesa_get_format_color_encoding(baseImage->TexFormat) == GL_SRGB;
 
-  /* We don't want to encode or decode sRGB values; treat them as linear. 
*/
-  _mesa_set_sampler_srgb_decode(ctx, mipmap->samp_obj, GL_SKIP_DECODE_EXT);
+  _mesa_set_sampler_srgb_decode(ctx, mipmap->samp_obj,
+srgb ? GL_DECODE_EXT : GL_SKIP_DECODE_EXT);
+  _mesa_set_framebuffer_srgb(ctx, srgb);
}
 
_mesa_bind_sampler(ctx, ctx->Texture.CurrentUnit, mipmap->samp_obj);

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Mesa (master): configure.ac: raise Mako required version to 0.8.0

[Emil Velikov]

Module: Mesa
Branch: master
Commit: ed871af91c2a34efde5073c91d87d1d31d50f5a8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed871af91c2a34efde5073c91d87d1d31d50f5a8

Author: Eric Engestrom 
Date:   Tue Jul 19 13:41:36 2016 +0100

configure.ac: raise Mako required version to 0.8.0

It seems [0] old versions of Mako are no longer supported. Emil mentioned it
might need v0.8.0 [1] for isl_format_layout [2], although I didn't get
a confirmation that it's really the minimum.
Let's raise it to that to avoid getting other bugs.
We might lower it a bit again later if it turns out we can.

[0] https://lists.freedesktop.org/archives/mesa-dev/2016-July/122772.html
[1] https://lists.freedesktop.org/archives/mesa-dev/2016-July/122775.html
[2] https://lists.freedesktop.org/archives/mesa-dev/2016-July/123278.html

Signed-off-by: Eric Engestrom 
Reviewed-by: Emil Velikov 
Acked-by: Dave Airlie 

---

 configure.ac | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configure.ac b/configure.ac
index 5a35599..d3dace8 100644
--- a/configure.ac
+++ b/configure.ac
@@ -90,7 +90,7 @@ XCBDRI2_REQUIRED=1.8
 XCBGLX_REQUIRED=1.8.1
 XSHMFENCE_REQUIRED=1.1
 XVMC_REQUIRED=1.0.6
-PYTHON_MAKO_REQUIRED=0.3.4
+PYTHON_MAKO_REQUIRED=0.8.0
 
 dnl Check for progs
 AC_PROG_CPP

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Mesa (master): mesa: Drop sed of now dead Plo files.

[Matt Turner]

Module: Mesa
Branch: master
Commit: e6673e7ac285e013ba25ce0e8c5bba691b1cdf3e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6673e7ac285e013ba25ce0e8c5bba691b1cdf3e

Author: Matt Turner 
Date:   Thu Aug 25 11:19:55 2016 -0700

mesa: Drop sed of now dead Plo files.

gen6/7/8_blorp.c were removed in commits c8bc1ae96a, e198983c61, and
16a9fcbbb6 respectively.

---

 configure.ac | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/configure.ac b/configure.ac
index d3dace8..6da7b38 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2779,9 +2779,6 @@ AC_OUTPUT
 # Fix up dependencies in *.Plo files, where we changed the extension of a
 # source file
 $SED -i -e 's/brw_blorp.cpp/brw_blorp.c/' 
src/mesa/drivers/dri/i965/.deps/brw_blorp.Plo
-$SED -i -e 's/gen6_blorp.cpp/gen6_blorp.c/' 
src/mesa/drivers/dri/i965/.deps/gen6_blorp.Plo
-$SED -i -e 's/gen7_blorp.cpp/gen7_blorp.c/' 
src/mesa/drivers/dri/i965/.deps/gen7_blorp.Plo
-$SED -i -e 's/gen8_blorp.cpp/gen8_blorp.c/' 
src/mesa/drivers/dri/i965/.deps/gen8_blorp.Plo
 
 
 dnl

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Mesa (master): 32 new commits

[Francisco Jerez]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=da85b5a9f1b22a8f6cae1a3b335dc5f31011bcb1
Author: Francisco Jerez 
Date:   Fri Jul 22 15:52:49 2016 -0700

i965: Expose shader framebuffer fetch extensions on Gen9+.

Reviewed-by: Kenneth Graunke 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4135fc22ff735a40c36fcf051c1735fe23d154f2
Author: Francisco Jerez 
Date:   Thu Aug 18 22:12:37 2016 -0700

i965/fs: Hook up coherent framebuffer reads to the NIR front-end.

Reviewed-by: Kenneth Graunke 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=be12a1f36efcdd4628f199d4e11b01cc06787e8a
Author: Francisco Jerez 
Date:   Thu Jul 21 16:56:05 2016 -0700

i965/fs: Remove special casing of framebuffer writes in scheduler code.

The reason why it was safe for the scheduler to ignore the side
effects of framebuffer write instructions was that its side effects
couldn't have had any influence on any other instruction in the
program, because we weren't doing framebuffer reads, and framebuffer
writes were always non-overlapping.  We need actual memory dependency
analysis in order to determine whether a side-effectful instruction
can be reordered with respect to other instructions in the program.

Reviewed-by: Kenneth Graunke 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3daa0fae4b39a271f50f473edbe44712b6c8f040
Author: Francisco Jerez 
Date:   Wed Jul 6 20:49:58 2016 -0700

i965/fs: Don't CSE render target messages with different target index.

We weren't checking the fs_inst::target field when comparing whether
two instructions are equal.  For FB writes it doesn't matter because
they aren't CSE-able anyway, but this would have become a problem with
FB reads which are expression-like instructions.

Reviewed-by: Kenneth Graunke 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=db123df74773f458e573a9c034ee783570a3ed0f
Author: Francisco Jerez 
Date:   Thu Jul 21 16:55:45 2016 -0700

i965/fs: Define logical framebuffer read opcode and lower it to physical 
reads.

Reviewed-by: Kenneth Graunke 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2f75b0cf05d2519d618c71b19d2187b8ed0d545
Author: Francisco Jerez 
Date:   Thu Jul 21 16:52:33 2016 -0700

i965/fs: Define framebuffer read virtual opcode.

Reviewed-by: Kenneth Graunke 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=71d639f69ee868fbeadd0a1b8bbdd76e17398b43
Author: Francisco Jerez 
Date:   Tue Jul 19 11:52:23 2016 -0700

i965/disasm: Fix RC message type strings on Gen7+.

Reviewed-by: Kenneth Graunke 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=26ac16fe2f73507041062f63646286dea60053da
Author: Francisco Jerez 
Date:   Thu Jul 21 19:13:55 2016 -0700

i965/eu: Add codegen support for the Gen9+ render target read message.

Reviewed-by: Kenneth Graunke 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=29eb8059fd7906d2595ea99bc65a27691b9fbe53
Author: Francisco Jerez 
Date:   Thu Jul 21 18:49:36 2016 -0700

i965/eu: Take into account the target cache argument in 
brw_set_dp_read_message.

brw_set_dp_read_message() was setting the data cache as send message
SFID on Gen7+ hardware, ignoring the target cache specified by the
caller.  Some of the callers were passing a bogus target cache value
as argument relying on brw_set_dp_read_message not to take it into
account.  Fix them too.

Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Kenneth Graunke 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a2f19a7772c80fcac85d6bdfa8e588d6cea1beb
Author: Francisco Jerez 
Date:   Tue Jul 19 15:23:30 2016 -0700

i965: Flip the non-coherent framebuffer fetch extension bit on G45-Gen8 
hardware.

This is not enabled on the original Gen4 part because it lacks surface
state tile offsets so it may not be possible to sample from arbitrary
non-zero layers of the framebuffer depending on the miptree layout (it
should be possible to work around this by allocating a scratch surface
and doing the same hack currently used for render targets, but meh...).

On Gen9+ even though it should mostly work (feel free to force-enable
it in order to compare the coherent and non-coherent paths in terms of
performance), there are some corner cases like 1D array layered
framebuffers that cannot be handled easily by the non-coherent path

Mesa (master): nir/phi_builder: Don't recurse in value_get_block_def

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 78715c7211aa81a1b189c3a29df4b2b98d2e0fc3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=78715c7211aa81a1b189c3a29df4b2b98d2e0fc3

Author: Jason Ekstrand 
Date:   Wed Aug 24 21:49:10 2016 -0700

nir/phi_builder: Don't recurse in value_get_block_def

In some programs, we can have very deep dominance trees and the recursion
can cause us to risk stack overflows.  Instead, we replace the recursion
with a pair of loops, one at the start and one at the end.  This is
functionally equivalent to what we had before and it's actually a bit
easier to read in the new form without the recursion.

Signed-off-by: Jason Ekstrand 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97225
Reviewed-by: Connor Abbott 
Reviewed-by: Matt Turner 

---

 src/compiler/nir/nir_phi_builder.c | 65 +-
 1 file changed, 36 insertions(+), 29 deletions(-)

diff --git a/src/compiler/nir/nir_phi_builder.c 
b/src/compiler/nir/nir_phi_builder.c
index dd48975..f96dad7 100644
--- a/src/compiler/nir/nir_phi_builder.c
+++ b/src/compiler/nir/nir_phi_builder.c
@@ -172,31 +172,27 @@ nir_ssa_def *
 nir_phi_builder_value_get_block_def(struct nir_phi_builder_value *val,
 nir_block *block)
 {
-   /* For each block, we have one of three types of values */
-   if (val->defs[block->index] == NULL) {
-  /* NULL indicates that we have no SSA def for this block. */
-  if (block->imm_dom) {
- /* Grab it from our immediate dominator.  We'll stash it here for
-  * easy access later.
-  */
- val->defs[block->index] =
-nir_phi_builder_value_get_block_def(val, block->imm_dom);
- return val->defs[block->index];
-  } else {
- /* No immediate dominator means that this block is either the
-  * start block or unreachable.  In either case, the value is
-  * undefined so we need an SSA undef.
-  */
- nir_ssa_undef_instr *undef =
-nir_ssa_undef_instr_create(val->builder->shader,
-   val->num_components,
-   val->bit_size);
- nir_instr_insert(nir_before_cf_list(>builder->impl->body),
-  >instr);
- val->defs[block->index] = >def;
- return >def;
-  }
-   } else if (val->defs[block->index] == NEEDS_PHI) {
+   /* Crawl up the dominance tree and find the closest dominator for which we
+* have a valid ssa_def, if any.
+*/
+   nir_block *dom = block;
+   while (dom && val->defs[dom->index] == NULL)
+  dom = dom->imm_dom;
+
+   nir_ssa_def *def;
+   if (dom == NULL) {
+  /* No dominator means either that we crawled to the top without ever
+   * finding a definition or that this block is unreachable.  In either
+   * case, the value is undefined so we need an SSA undef.
+   */
+  nir_ssa_undef_instr *undef =
+ nir_ssa_undef_instr_create(val->builder->shader,
+val->num_components,
+val->bit_size);
+  nir_instr_insert(nir_before_cf_list(>builder->impl->body),
+   >instr);
+  def = >def;
+   } else if (val->defs[dom->index] == NEEDS_PHI) {
   /* The magic value NEEDS_PHI indicates that the block needs a phi node
* but none has been created.  We need to create one now so we can
* return it to the caller.
@@ -218,17 +214,28 @@ nir_phi_builder_value_get_block_def(struct 
nir_phi_builder_value *val,
   nir_phi_instr *phi = nir_phi_instr_create(val->builder->shader);
   nir_ssa_dest_init(>instr, >dest, val->num_components,
 val->bit_size, NULL);
-  phi->instr.block = block;
+  phi->instr.block = dom;
   exec_list_push_tail(>phis, >instr.node);
-  val->defs[block->index] = >dest.ssa;
-  return >dest.ssa;
+  def = >dest.ssa;
} else {
   /* In this case, we have an actual SSA def.  It's either the result of a
* phi node created by the case above or one passed to us through
* nir_phi_builder_value_set_block_def().
*/
-  return val->defs[block->index];
+  def = val->defs[dom->index];
}
+
+   /* Walk the chain and stash the def in all of the applicable blocks.  We do
+* this for two reasons:
+*
+*  1) To speed up lookup next time even if the next time is called from a
+* block that is not dominated by this one.
+*  2) To avoid unneeded recreation of phi nodes and undefs.
+*/
+   for (dom = block; dom && val->defs[dom->index] == NULL; dom = dom->imm_dom)
+  val->defs[dom->index] = def;
+
+   return def;
 }
 
 static int

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Mesa (master): nir: Walk blocks in source code order in lower_vars_to_ssa.

[Matt Turner]

Module: Mesa
Branch: master
Commit: e53130cc27b966a09d48be53cb51e09ea7ad0649
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e53130cc27b966a09d48be53cb51e09ea7ad0649

Author: Matt Turner 
Date:   Wed Aug 24 19:25:58 2016 -0700

nir: Walk blocks in source code order in lower_vars_to_ssa.

Prior to this commit rename_variables_block() is recursively called,
performing a depth-first traversal of the control flow graph. The
function uses a non-trivial amount of stack space for local variables,
which puts us in danger of smashing the stack, given a sufficiently deep
dominance tree.

XCOM: Enemy Within contains a shader with such a dominance tree (1574
nir_blocks in total, depth of at least 143).

Jason tells me that he believes that any walk over the nir_blocks that
respects dominance is sufficient (a DFS might have been necessary prior
to the introduction of nir_phi_builder).

In fact, the introduction of nir_phi_builder made the problem worse:
rename_variables_block(), walks to the bottom of the dominance tree
before calling nir_phi_builder_value_get_block_def() which walks back to
the top of the dominance tree...

In any case, this patch ensures we avoid that problem as well.

Cc: mesa-sta...@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97225
Reviewed-by: Connor Abbott 

---

 src/compiler/nir/nir_lower_vars_to_ssa.c | 209 +++
 src/compiler/nir/nir_phi_builder.h   |   3 +-
 2 files changed, 106 insertions(+), 106 deletions(-)

diff --git a/src/compiler/nir/nir_lower_vars_to_ssa.c 
b/src/compiler/nir/nir_lower_vars_to_ssa.c
index 317647b..25dc70c 100644
--- a/src/compiler/nir/nir_lower_vars_to_ssa.c
+++ b/src/compiler/nir/nir_lower_vars_to_ssa.c
@@ -471,7 +471,7 @@ lower_copies_to_load_store(struct deref_node *node,
return true;
 }
 
-/* Performs variable renaming by doing a DFS of the dominance tree
+/* Performs variable renaming
  *
  * This algorithm is very similar to the one outlined in "Efficiently
  * Computing Static Single Assignment Form and the Control Dependence
@@ -479,133 +479,132 @@ lower_copies_to_load_store(struct deref_node *node,
  * SSA def on the stack per block.
  */
 static bool
-rename_variables_block(nir_block *block, struct lower_variables_state *state)
+rename_variables(struct lower_variables_state *state)
 {
nir_builder b;
nir_builder_init(, state->impl);
 
-   nir_foreach_instr_safe(instr, block) {
-  if (instr->type != nir_instr_type_intrinsic)
- continue;
-
-  nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
-
-  switch (intrin->intrinsic) {
-  case nir_intrinsic_load_var: {
- struct deref_node *node =
-get_deref_node(intrin->variables[0], state);
-
- if (node == NULL) {
-/* If we hit this path then we are referencing an invalid
- * value.  Most likely, we unrolled something and are
- * reading past the end of some array.  In any case, this
- * should result in an undefined value.
- */
-nir_ssa_undef_instr *undef =
-   nir_ssa_undef_instr_create(state->shader,
-  intrin->num_components,
-  intrin->dest.ssa.bit_size);
-
-nir_instr_insert_before(>instr, >instr);
-nir_instr_remove(>instr);
-
-nir_ssa_def_rewrite_uses(>dest.ssa,
- nir_src_for_ssa(>def));
+   nir_foreach_block(block, state->impl) {
+  nir_foreach_instr_safe(instr, block) {
+ if (instr->type != nir_instr_type_intrinsic)
 continue;
- }
 
- if (!node->lower_to_ssa)
-continue;
+ nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
+
+ switch (intrin->intrinsic) {
+ case nir_intrinsic_load_var: {
+struct deref_node *node =
+   get_deref_node(intrin->variables[0], state);
+
+if (node == NULL) {
+   /* If we hit this path then we are referencing an invalid
+* value.  Most likely, we unrolled something and are
+* reading past the end of some array.  In any case, this
+* should result in an undefined value.
+*/
+   nir_ssa_undef_instr *undef =
+  nir_ssa_undef_instr_create(state->shader,
+ intrin->num_components,
+ intrin->dest.ssa.bit_size);
+
+   nir_instr_insert_before(>instr, >instr);
+   nir_instr_remove(>instr);
+
+   nir_ssa_def_rewrite_uses(>dest.ssa,
+nir_src_for_ssa(>def));
+   continue;
+}
 
- nir_alu_instr *mov = nir_alu_instr_create(state->shader,
-  

Mesa (master): .mailmap: Update my address again

[Chad Versace]

Module: Mesa
Branch: master
Commit: 3eddf5219e3ac17e46403849b40bfd217eb6e9d8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3eddf5219e3ac17e46403849b40bfd217eb6e9d8

Author: Chad Versace 
Date:   Thu Aug 25 13:54:47 2016 -0700

.mailmap: Update my address again

I joined Google's Chrome OS graphics team.

---

 .mailmap | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/.mailmap b/.mailmap
index 469599e..756b066 100644
--- a/.mailmap
+++ b/.mailmap
@@ -88,10 +88,11 @@ Carl-Philip Hänsch  Carl-Philip 
Haensch  Carl-Philip Haensch 

 Carl-Philip Hänsch  Carl-Philip Haensch 

 
-Chad Versace  
-Chad Versace  
-Chad Versace  
-Chad Versace  
+Chad Versace  
+Chad Versace  
+Chad Versace  
+Chad Versace  
+Chad Versace  
 
 Chia-I Wu  
 Chia-I Wu  Chia-Wu 

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Mesa (master): radeonsi: don't use allocas for arrays with LLVM 3.8

[Marek Olšák]

Module: Mesa
Branch: master
Commit: a491b9e945423a81f785220b85a9b395060952aa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a491b9e945423a81f785220b85a9b395060952aa

Author: Marek Olšák 
Date:   Thu Aug 25 20:22:59 2016 +0200

radeonsi: don't use allocas for arrays with LLVM 3.8

It crashes.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97413

---

 src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c 
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 71f52fd..4643e6d 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -559,8 +559,10 @@ static void emit_declaration(struct lp_build_tgsi_context 
*bld_base,
 * FIXME: We shouldn't need to have the non-alloca
 * code path for arrays. LLVM should be smart enough to
 * promote allocas into registers when profitable.
+*
+* LLVM 3.8 crashes with this.
 */
-   if (array_size > 16) {
+   if (HAVE_LLVM >= 0x0309 && array_size > 16) {
array_alloca = LLVMBuildAlloca(builder,
LLVMArrayType(bld_base->base.vec_type,
  array_size), "array");

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Mesa (master): gallium/radeon: unify and simplify checking for an empty gfx IB

[Marek Olšák]

Module: Mesa
Branch: master
Commit: fe91ae06d3ecc2080b61a6bc35867653de0da418
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fe91ae06d3ecc2080b61a6bc35867653de0da418

Author: Marek Olšák 
Date:   Thu Aug 25 01:26:54 2016 +0200

gallium/radeon: unify and simplify checking for an empty gfx IB

We can take advantage of the fact that multi_fence does the obvious thing
with NULL fences.

This fixes unflushed fences that can get stuck due to empty IBs.

---

 src/gallium/drivers/r600/r600_hw_context.c|  8 +---
 src/gallium/drivers/radeon/r600_pipe_common.c | 29 ++-
 src/gallium/drivers/radeonsi/si_hw_context.c  | 13 +++-
 3 files changed, 23 insertions(+), 27 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_hw_context.c 
b/src/gallium/drivers/r600/r600_hw_context.c
index 4447393..58ba09d 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -255,14 +255,8 @@ void r600_context_gfx_flush(void *context, unsigned flags,
struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
struct radeon_winsys *ws = ctx->b.ws;
 
-   if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size) &&
-   (!fence || ctx->b.last_gfx_fence)) {
-   if (fence)
-   ws->fence_reference(fence, ctx->b.last_gfx_fence);
-   if (!(flags & RADEON_FLUSH_ASYNC))
-   ws->cs_sync_flush(cs);
+   if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size))
return;
-   }
 
r600_preflush_suspend_features(>b);
 
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index ab620eb..b1da22f 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -265,6 +265,7 @@ static void r600_flush_from_st(struct pipe_context *ctx,
 {
struct pipe_screen *screen = ctx->screen;
struct r600_common_context *rctx = (struct r600_common_context *)ctx;
+   struct radeon_winsys *ws = rctx->ws;
unsigned rflags = 0;
struct pipe_fence_handle *gfx_fence = NULL;
struct pipe_fence_handle *sdma_fence = NULL;
@@ -279,26 +280,34 @@ static void r600_flush_from_st(struct pipe_context *ctx,
rctx->dma.flush(rctx, rflags, fence ? _fence : NULL);
}
 
-   /* Instead of flushing, create a deferred fence. Constraints:
-* - The state tracker must allow a deferred flush.
-* - The state tracker must request a fence.
-* Thread safety in fence_finish must be ensured by the state tracker.
-*/
-   if (flags & PIPE_FLUSH_DEFERRED && fence) {
-   gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
-   deferred_fence = true;
+   if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
+   if (fence)
+   ws->fence_reference(_fence, rctx->last_gfx_fence);
+   if (!(rflags & RADEON_FLUSH_ASYNC))
+   ws->cs_sync_flush(rctx->gfx.cs);
} else {
-   rctx->gfx.flush(rctx, rflags, fence ? _fence : NULL);
+   /* Instead of flushing, create a deferred fence. Constraints:
+* - The state tracker must allow a deferred flush.
+* - The state tracker must request a fence.
+* Thread safety in fence_finish must be ensured by the state 
tracker.
+*/
+   if (flags & PIPE_FLUSH_DEFERRED && fence) {
+   gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
+   deferred_fence = true;
+   } else {
+   rctx->gfx.flush(rctx, rflags, fence ? _fence : 
NULL);
+   }
}
 
/* Both engines can signal out of order, so we need to keep both 
fences. */
-   if (gfx_fence || sdma_fence) {
+   if (fence) {
struct r600_multi_fence *multi_fence =
CALLOC_STRUCT(r600_multi_fence);
if (!multi_fence)
return;
 
multi_fence->reference.count = 1;
+   /* If both fences are NULL, fence_finish will always return 
true. */
multi_fence->gfx = gfx_fence;
multi_fence->sdma = sdma_fence;
 
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c 
b/src/gallium/drivers/radeonsi/si_hw_context.c
index 49d1a35..aeccb2d 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -100,17 +100,10 @@ void si_context_gfx_flush(void *context, unsigned flags,
if (ctx->gfx_flush_in_progress)
return;
 
-   ctx->gfx_flush_in_progress = true;
-
-   if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size) &&
-   (!fence || ctx->b.last_gfx_fence)) {
-   if (fence)
-   

Mesa (master): intel: Flatten the makefile structure

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: bebc1a1d995e33f173ea207848bcddd81f6dd19a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bebc1a1d995e33f173ea207848bcddd81f6dd19a

Author: Jason Ekstrand 
Date:   Mon Aug 22 14:10:46 2016 -0700

intel: Flatten the makefile structure

This pulls isl and genxml into a single make file so that they can properly
build in parallel.  This isn't terribly important now as genxml just
generates sources which happens serially first anyway but it will be more
important as we add more stuff to src/intel.

Signed-off-by: Jason Ekstrand 
Reviewed-by: Matt Turner 

---

 configure.ac   |   2 -
 src/intel/Makefile.am  |  37 ++-
 .../{genxml/Makefile.am => Makefile.genxml.am} |  41 
 src/intel/Makefile.isl.am  |  84 
 src/intel/Makefile.sources |  50 ++
 src/intel/genxml/Makefile.sources  |   9 --
 src/intel/isl/Makefile.am  | 108 -
 src/intel/isl/Makefile.sources |  40 
 src/intel/isl/gen_format_layout.py |   2 +-
 9 files changed, 189 insertions(+), 184 deletions(-)

diff --git a/configure.ac b/configure.ac
index 6da7b38..75b1de4 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2746,8 +2746,6 @@ AC_CONFIG_FILES([Makefile
src/glx/tests/Makefile
src/gtest/Makefile
src/intel/Makefile
-   src/intel/genxml/Makefile
-   src/intel/isl/Makefile
src/intel/tools/Makefile
src/intel/vulkan/Makefile
src/loader/Makefile
diff --git a/src/intel/Makefile.am b/src/intel/Makefile.am
index 520602d..3b7d2f3 100644
--- a/src/intel/Makefile.am
+++ b/src/intel/Makefile.am
@@ -19,4 +19,39 @@
 # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 # IN THE SOFTWARE.
 
-SUBDIRS = genxml isl
+include Makefile.sources
+
+# The gallium includes are for the util/u_math.h include from main/macros.h
+AM_CPPFLAGS = \
+   -I$(top_srcdir)/include \
+   -I$(top_builddir)/src \
+   -I$(top_srcdir)/src \
+   -I$(top_builddir)/src/intel \
+   -I$(top_srcdir)/src/intel \
+   -I$(top_srcdir)/src/mapi \
+   -I$(top_srcdir)/src/mesa \
+   -I$(top_srcdir)/src/mesa/drivers/dri/i965 \
+   -I$(top_srcdir)/src/gallium/auxiliary \
+   -I$(top_srcdir)/src/gallium/include \
+   $(INTEL_CFLAGS) \
+   $(VALGRIND_CFLAGS) \
+   $(DEFINES)
+
+AM_CFLAGS = \
+   $(VISIBILITY_CFLAGS) \
+   -Wno-override-init
+
+MKDIR_GEN = $(AM_V_at)$(MKDIR_P) $(@D)
+PYTHON_GEN = $(AM_V_GEN)$(PYTHON2) $(PYTHON_FLAGS)
+
+noinst_LTLIBRARIES =
+check_PROGRAMS =
+TESTS =
+BUILT_SOURCES =
+CLEANFILES =
+EXTRA_DIST =
+
+include Makefile.genxml.am
+include Makefile.isl.am
+
+CLEANFILES += $(BUILT_SOURCES)
diff --git a/src/intel/genxml/Makefile.am b/src/intel/Makefile.genxml.am
similarity index 73%
rename from src/intel/genxml/Makefile.am
rename to src/intel/Makefile.genxml.am
index 95c1ff9..f80e2fd 100644
--- a/src/intel/genxml/Makefile.am
+++ b/src/intel/Makefile.genxml.am
@@ -19,31 +19,26 @@
 # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 # IN THE SOFTWARE.
 
-include Makefile.sources
-
-BUILT_SOURCES = $(GENXML_GENERATED_FILES)
-
-PYTHON_GEN = $(AM_V_GEN)$(PYTHON2) $(PYTHON_FLAGS)
+BUILT_SOURCES += $(GENXML_GENERATED_FILES)
 
 SUFFIXES = _pack.h .xml
 
-$(BUILT_SOURCES): gen_pack_header.py
+$(GENXML_GENERATED_FILES): genxml/gen_pack_header.py
 
 .xml_pack.h:
-   $(PYTHON_GEN) $(srcdir)/gen_pack_header.py $< > $@
-
-CLEANFILES = $(BUILT_SOURCES)
-
-EXTRA_DIST = \
-   gen4.xml \
-   gen45.xml \
-   gen5.xml \
-   gen6.xml \
-   gen7.xml \
-   gen75.xml \
-   gen8.xml \
-   gen9.xml \
-   genX_pack.h \
-   gen_macros.h \
-   gen_pack_header.py \
-   README
+   $(MKDIR_GEN)
+   $(PYTHON_GEN) $(srcdir)/genxml/gen_pack_header.py $< > $@
+
+EXTRA_DIST += \
+   genxml/gen4.xml \
+   genxml/gen45.xml \
+   genxml/gen5.xml \
+   genxml/gen6.xml \
+   genxml/gen7.xml \
+   genxml/gen75.xml \
+   genxml/gen8.xml \
+   genxml/gen9.xml \
+   genxml/genX_pack.h \
+   genxml/gen_macros.h \
+   genxml/gen_pack_header.py \
+   genxml/README
diff --git a/src/intel/Makefile.isl.am b/src/intel/Makefile.isl.am
new file mode 100644
index 000..8871684
--- /dev/null
+++ b/src/intel/Makefile.isl.am
@@ -0,0 +1,84 @@
+# Copyright 2015-2016 Intel Corporation
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, 

Mesa (master): isl/tests: Use a longer path for isl.h

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: c19fc5e0198cbc1eead3db9672d51c56c1aa3f1d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c19fc5e0198cbc1eead3db9672d51c56c1aa3f1d

Author: Jason Ekstrand 
Date:   Mon Aug 22 14:24:01 2016 -0700

isl/tests: Use a longer path for isl.h

The tests assumed that isl would be in the include path but that usually
isn't the case.  Instead, we usually have src/intel and you need to add an
"isl/" prefix.

Signed-off-by: Jason Ekstrand 
Reviewed-by: Matt Turner 

---

 src/intel/isl/tests/isl_surf_get_image_offset_test.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/isl/tests/isl_surf_get_image_offset_test.c 
b/src/intel/isl/tests/isl_surf_get_image_offset_test.c
index 9d6a834..9015f0e 100644
--- a/src/intel/isl/tests/isl_surf_get_image_offset_test.c
+++ b/src/intel/isl/tests/isl_surf_get_image_offset_test.c
@@ -27,8 +27,8 @@
 #include 
 
 #include "brw_device_info.h"
-#include "isl.h"
-#include "isl_priv.h"
+#include "isl/isl.h"
+#include "isl/isl_priv.h"
 
 #define BDW_GT2_DEVID 0x161a
 

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Mesa (master): intel/isl: Pass the dim_layout into choose_alignment_el

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: cda1a5dc0e1b7660d25513261358c92d7b36940c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cda1a5dc0e1b7660d25513261358c92d7b36940c

Author: Jason Ekstrand 
Date:   Tue Aug 23 21:46:23 2016 -0700

intel/isl: Pass the dim_layout into choose_alignment_el

Signed-off-by: Jason Ekstrand 
Reviewed-by: Topi Pohjolainen 
Reviewed-by: Chad Versace 

---

 src/intel/isl/isl.c  | 23 ---
 src/intel/isl/isl_gen4.c |  1 +
 src/intel/isl/isl_gen4.h |  1 +
 src/intel/isl/isl_gen6.c |  1 +
 src/intel/isl/isl_gen6.h |  1 +
 src/intel/isl/isl_gen7.c |  1 +
 src/intel/isl/isl_gen7.h |  1 +
 src/intel/isl/isl_gen8.c |  1 +
 src/intel/isl/isl_gen8.h |  1 +
 src/intel/isl/isl_gen9.c |  5 +++--
 src/intel/isl/isl_gen9.h |  1 +
 11 files changed, 24 insertions(+), 13 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 05a0a9b..59429fb 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -421,6 +421,7 @@ static void
 isl_choose_image_alignment_el(const struct isl_device *dev,
   const struct isl_surf_init_info *restrict info,
   enum isl_tiling tiling,
+  enum isl_dim_layout dim_layout,
   enum isl_msaa_layout msaa_layout,
   struct isl_extent3d *image_align_el)
 {
@@ -434,20 +435,20 @@ isl_choose_image_alignment_el(const struct isl_device 
*dev,
}
 
if (ISL_DEV_GEN(dev) >= 9) {
-  gen9_choose_image_alignment_el(dev, info, tiling, msaa_layout,
- image_align_el);
+  gen9_choose_image_alignment_el(dev, info, tiling, dim_layout,
+ msaa_layout, image_align_el);
} else if (ISL_DEV_GEN(dev) >= 8) {
-  gen8_choose_image_alignment_el(dev, info, tiling, msaa_layout,
- image_align_el);
+  gen8_choose_image_alignment_el(dev, info, tiling, dim_layout,
+ msaa_layout, image_align_el);
} else if (ISL_DEV_GEN(dev) >= 7) {
-  gen7_choose_image_alignment_el(dev, info, tiling, msaa_layout,
- image_align_el);
+  gen7_choose_image_alignment_el(dev, info, tiling, dim_layout,
+ msaa_layout, image_align_el);
} else if (ISL_DEV_GEN(dev) >= 6) {
-  gen6_choose_image_alignment_el(dev, info, tiling, msaa_layout,
- image_align_el);
+  gen6_choose_image_alignment_el(dev, info, tiling, dim_layout,
+ msaa_layout, image_align_el);
} else {
-  gen4_choose_image_alignment_el(dev, info, tiling, msaa_layout,
- image_align_el);
+  gen4_choose_image_alignment_el(dev, info, tiling, dim_layout,
+ msaa_layout, image_align_el);
}
 }
 
@@ -1146,7 +1147,7 @@ isl_surf_init_s(const struct isl_device *dev,
return false;
 
struct isl_extent3d image_align_el;
-   isl_choose_image_alignment_el(dev, info, tiling, msaa_layout,
+   isl_choose_image_alignment_el(dev, info, tiling, dim_layout, msaa_layout,
  _align_el);
 
struct isl_extent3d image_align_sa =
diff --git a/src/intel/isl/isl_gen4.c b/src/intel/isl/isl_gen4.c
index 52aa565..1d584fc 100644
--- a/src/intel/isl/isl_gen4.c
+++ b/src/intel/isl/isl_gen4.c
@@ -41,6 +41,7 @@ void
 gen4_choose_image_alignment_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
enum isl_tiling tiling,
+   enum isl_dim_layout dim_layout,
enum isl_msaa_layout msaa_layout,
struct isl_extent3d *image_align_el)
 {
diff --git a/src/intel/isl/isl_gen4.h b/src/intel/isl/isl_gen4.h
index 06cd70b..48175ca 100644
--- a/src/intel/isl/isl_gen4.h
+++ b/src/intel/isl/isl_gen4.h
@@ -39,6 +39,7 @@ void
 gen4_choose_image_alignment_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
enum isl_tiling tiling,
+   enum isl_dim_layout dim_layout,
enum isl_msaa_layout msaa_layout,
struct isl_extent3d *image_align_el);
 
diff --git a/src/intel/isl/isl_gen6.c b/src/intel/isl/isl_gen6.c
index de95a8f..2c52e38 100644
--- a/src/intel/isl/isl_gen6.c
+++ b/src/intel/isl/isl_gen6.c
@@ -86,6 +86,7 @@ void
 gen6_choose_image_alignment_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict info,
enum isl_tiling tiling,
+

Mesa (master): intel/isl/gen9: Only use the magic 1D alignment for GEN9_1D surfaces

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 8bdf605214874804369a879ca7d2f2de01e2af09
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8bdf605214874804369a879ca7d2f2de01e2af09

Author: Jason Ekstrand 
Date:   Tue Aug 23 21:46:58 2016 -0700

intel/isl/gen9: Only use the magic 1D alignment for GEN9_1D surfaces

If the surface has a layout of GEN4_2D then we need to compute a normal 2D
alignment and not use the magic linewar 1D alignment.

Signed-off-by: Jason Ekstrand 
Reviewed-by: Topi Pohjolainen 
Reviewed-by: Chad Versace 

---

 src/intel/isl/isl_gen9.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/isl/isl_gen9.c b/src/intel/isl/isl_gen9.c
index ca6..da8c749 100644
--- a/src/intel/isl/isl_gen9.c
+++ b/src/intel/isl/isl_gen9.c
@@ -174,7 +174,7 @@ gen9_choose_image_alignment_el(const struct isl_device *dev,
   return;
}
 
-   if (info->dim == ISL_SURF_DIM_1D) {
+   if (dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
   /* See the Skylake BSpec > Memory Views > Common Surface Formats > 
Surface
* Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
*/

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Mesa (master): intel/isl: Use DIM_LAYOUT_GEN4_2D for tiled 1-D surfaces on SKL

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: f68cfb05fa1ac9a6f5e0b921a7dce00e315fa52c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f68cfb05fa1ac9a6f5e0b921a7dce00e315fa52c

Author: Jason Ekstrand 
Date:   Tue Aug 23 21:35:36 2016 -0700

intel/isl: Use DIM_LAYOUT_GEN4_2D for tiled 1-D surfaces on SKL

The Sky Lake 1D layout is only used if the surface is linear.  For tiled
surfaces such as depth and stencil the old gen4 2D layout is used.

Signed-off-by: Jason Ekstrand 
Reviewed-by: Topi Pohjolainen 
Reviewed-by: Chad Versace 

---

 src/intel/isl/isl.c | 28 +++-
 1 file changed, 23 insertions(+), 5 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 18e95e2..05a0a9b 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -453,12 +453,30 @@ isl_choose_image_alignment_el(const struct isl_device 
*dev,
 
 static enum isl_dim_layout
 isl_surf_choose_dim_layout(const struct isl_device *dev,
-   enum isl_surf_dim logical_dim)
+   enum isl_surf_dim logical_dim,
+   enum isl_tiling tiling)
 {
if (ISL_DEV_GEN(dev) >= 9) {
   switch (logical_dim) {
   case ISL_SURF_DIM_1D:
- return ISL_DIM_LAYOUT_GEN9_1D;
+ /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
+  *
+  *One-dimensional surfaces use a tiling mode of linear.
+  *Technically, they are not tiled resources, but the Tiled
+  *Resource Mode field in RENDER_SURFACE_STATE is still used to
+  *indicate the alignment requirements for this linear surface
+  *(See 1D Alignment requirements for how 4K and 64KB Tiled
+  *Resource Modes impact alignment). Alternatively, a 1D surface
+  *can be defined as a 2D tiled surface (e.g. TileY or TileX) with
+  *a height of 0.
+  *
+  * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear
+  * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used.
+  */
+ if (tiling == ISL_TILING_LINEAR)
+return ISL_DIM_LAYOUT_GEN9_1D;
+ else
+return ISL_DIM_LAYOUT_GEN4_2D;
   case ISL_SURF_DIM_2D:
   case ISL_SURF_DIM_3D:
  return ISL_DIM_LAYOUT_GEN4_2D;
@@ -1112,9 +1130,6 @@ isl_surf_init_s(const struct isl_device *dev,
   .a = info->array_len,
};
 
-   enum isl_dim_layout dim_layout =
-  isl_surf_choose_dim_layout(dev, info->dim);
-
enum isl_tiling tiling;
if (!isl_surf_choose_tiling(dev, info, ))
   return false;
@@ -1123,6 +1138,9 @@ isl_surf_init_s(const struct isl_device *dev,
if (!isl_tiling_get_info(dev, tiling, fmtl->bpb, _info))
   return false;
 
+   const enum isl_dim_layout dim_layout =
+  isl_surf_choose_dim_layout(dev, info->dim, tiling);
+
enum isl_msaa_layout msaa_layout;
if (!isl_choose_msaa_layout(dev, info, tiling, _layout))
return false;

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Mesa (master): vc4: Add support for fddx/fddy

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 00c72acba5a98965622000d949b6835f28a9d71a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=00c72acba5a98965622000d949b6835f28a9d71a

Author: Eric Anholt 
Date:   Thu Aug 25 12:32:19 2016 -0700

vc4: Add support for fddx/fddy

Based vaguely on a patch by jonasarrow on github.

---

 src/gallium/drivers/vc4/vc4_program.c | 52 +++
 1 file changed, 52 insertions(+)

diff --git a/src/gallium/drivers/vc4/vc4_program.c 
b/src/gallium/drivers/vc4/vc4_program.c
index dd8c421..19bb8a3 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -932,6 +932,46 @@ out:
 return qir_SEL(c, QPU_COND_NS, src[1], src[2]);
 }
 
+static struct qreg
+ntq_fddx(struct vc4_compile *c, struct qreg src)
+{
+/* Make sure that we have a bare temp to use for MUL rotation, so it
+ * can be allocated to an accumulator.
+ */
+if (src.pack || src.file != QFILE_TEMP)
+src = qir_MOV(c, src);
+
+struct qreg from_left = qir_ROT_MUL(c, src, 1);
+struct qreg from_right = qir_ROT_MUL(c, src, 15);
+
+/* Distinguish left/right pixels of the quad. */
+qir_SF(c, qir_AND(c, qir_reg(QFILE_QPU_ELEMENT, 0),
+  qir_uniform_ui(c, 1)));
+
+return qir_SEL(c, QPU_COND_ZS,
+   qir_FSUB(c, from_right, src),
+   qir_FSUB(c, src, from_left));
+}
+
+static struct qreg
+ntq_fddy(struct vc4_compile *c, struct qreg src)
+{
+if (src.pack || src.file != QFILE_TEMP)
+src = qir_MOV(c, src);
+
+struct qreg from_bottom = qir_ROT_MUL(c, src, 2);
+struct qreg from_top = qir_ROT_MUL(c, src, 14);
+
+/* Distinguish top/bottom pixels of the quad. */
+qir_SF(c, qir_AND(c,
+  qir_reg(QFILE_QPU_ELEMENT, 0),
+  qir_uniform_ui(c, 2)));
+
+return qir_SEL(c, QPU_COND_ZS,
+   qir_FSUB(c, from_top, src),
+   qir_FSUB(c, src, from_bottom));
+}
+
 static void
 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
 {
@@ -1158,6 +1198,18 @@ ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
 result = qir_V8MULD(c, src[0], src[1]);
 break;
 
+case nir_op_fddx:
+case nir_op_fddx_coarse:
+case nir_op_fddx_fine:
+result = ntq_fddx(c, src[0]);
+break;
+
+case nir_op_fddy:
+case nir_op_fddy_coarse:
+case nir_op_fddy_fine:
+result = ntq_fddy(c, src[0]);
+break;
+
 default:
 fprintf(stderr, "unknown NIR ALU inst: ");
 nir_print_instr(>instr, stderr);

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Mesa (master): vc4: Add support for the 2-bit LOAD_IMM variants.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 074f1f3c0c2cd15213a62eb7f589423ece6391c8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=074f1f3c0c2cd15213a62eb7f589423ece6391c8

Author: Eric Anholt 
Date:   Thu Aug 25 12:15:29 2016 -0700

vc4: Add support for the 2-bit LOAD_IMM variants.

Extracted and fixed up from a patch by jonasarrow on github.  This ended
up not getting used for ddx/ddy, but seems like it might still be useful.

---

 src/gallium/drivers/vc4/vc4_qir.c |  2 ++
 src/gallium/drivers/vc4/vc4_qir.h | 26 ++
 src/gallium/drivers/vc4/vc4_qpu.c | 14 ++
 src/gallium/drivers/vc4/vc4_qpu.h |  2 ++
 src/gallium/drivers/vc4/vc4_qpu_defines.h |  6 ++
 src/gallium/drivers/vc4/vc4_qpu_emit.c|  8 
 6 files changed, 58 insertions(+)

diff --git a/src/gallium/drivers/vc4/vc4_qir.c 
b/src/gallium/drivers/vc4/vc4_qir.c
index 0919d32..9b4a28e 100644
--- a/src/gallium/drivers/vc4/vc4_qir.c
+++ b/src/gallium/drivers/vc4/vc4_qir.c
@@ -83,6 +83,8 @@ static const struct qir_op_info qir_op_info[] = {
 [QOP_TEX_RESULT] = { "tex_result", 1, 0, true },
 
 [QOP_LOAD_IMM] = { "load_imm", 0, 1 },
+[QOP_LOAD_IMM_U2] = { "load_imm_u2", 0, 1 },
+[QOP_LOAD_IMM_I2] = { "load_imm_i2", 0, 1 },
 
 [QOP_BRANCH] = { "branch", 0, 0, true },
 [QOP_UNIFORMS_RESET] = { "uniforms_reset", 0, 2, true },
diff --git a/src/gallium/drivers/vc4/vc4_qir.h 
b/src/gallium/drivers/vc4/vc4_qir.h
index 9e61200..90cc138 100644
--- a/src/gallium/drivers/vc4/vc4_qir.h
+++ b/src/gallium/drivers/vc4/vc4_qir.h
@@ -156,8 +156,18 @@ enum qop {
  */
 QOP_TEX_RESULT,
 
+/* 32-bit immediate loaded to each SIMD channel */
 QOP_LOAD_IMM,
 
+/* 32-bit immediate divided into 16 2-bit unsigned int values and
+ * loaded to each corresponding SIMD channel.
+ */
+QOP_LOAD_IMM_U2,
+/* 32-bit immediate divided into 16 2-bit signed int values and
+ * loaded to each corresponding SIMD channel.
+ */
+QOP_LOAD_IMM_I2,
+
 /* Jumps to block->successor[0] if the qinst->cond (as a
  * QPU_COND_BRANCH_*) passes, or block->successor[1] if not.  Note
  * that block->successor[1] may be unset if the condition is ALWAYS.
@@ -796,6 +806,22 @@ qir_LOAD_IMM(struct vc4_compile *c, uint32_t val)
 qir_reg(QFILE_LOAD_IMM, val), 
c->undef));
 }
 
+static inline struct qreg
+qir_LOAD_IMM_U2(struct vc4_compile *c, uint32_t val)
+{
+return qir_emit_def(c, qir_inst(QOP_LOAD_IMM_U2, c->undef,
+qir_reg(QFILE_LOAD_IMM, val),
+c->undef));
+}
+
+static inline struct qreg
+qir_LOAD_IMM_I2(struct vc4_compile *c, uint32_t val)
+{
+return qir_emit_def(c, qir_inst(QOP_LOAD_IMM_I2, c->undef,
+qir_reg(QFILE_LOAD_IMM, val),
+c->undef));
+}
+
 static inline void
 qir_MOV_cond(struct vc4_compile *c, uint8_t cond,
  struct qreg dest, struct qreg src)
diff --git a/src/gallium/drivers/vc4/vc4_qpu.c 
b/src/gallium/drivers/vc4/vc4_qpu.c
index cf74c42..d022d10 100644
--- a/src/gallium/drivers/vc4/vc4_qpu.c
+++ b/src/gallium/drivers/vc4/vc4_qpu.c
@@ -165,6 +165,20 @@ qpu_load_imm_ui(struct qpu_reg dst, uint32_t val)
 }
 
 uint64_t
+qpu_load_imm_u2(struct qpu_reg dst, uint32_t val)
+{
+return qpu_load_imm_ui(dst, val) | QPU_SET_FIELD(QPU_LOAD_IMM_MODE_U2,
+ QPU_LOAD_IMM_MODE);
+}
+
+uint64_t
+qpu_load_imm_i2(struct qpu_reg dst, uint32_t val)
+{
+return qpu_load_imm_ui(dst, val) | QPU_SET_FIELD(QPU_LOAD_IMM_MODE_I2,
+ QPU_LOAD_IMM_MODE);
+}
+
+uint64_t
 qpu_branch(uint32_t cond, uint32_t target)
 {
 uint64_t inst = 0;
diff --git a/src/gallium/drivers/vc4/vc4_qpu.h 
b/src/gallium/drivers/vc4/vc4_qpu.h
index a0aac15..437e4f5 100644
--- a/src/gallium/drivers/vc4/vc4_qpu.h
+++ b/src/gallium/drivers/vc4/vc4_qpu.h
@@ -143,6 +143,8 @@ uint64_t qpu_m_alu2(enum qpu_op_mul op, struct qpu_reg dst,
 struct qpu_reg src0, struct qpu_reg src1) ATTRIBUTE_CONST;
 uint64_t qpu_merge_inst(uint64_t a, uint64_t b) ATTRIBUTE_CONST;
 uint64_t qpu_load_imm_ui(struct qpu_reg dst, uint32_t val) ATTRIBUTE_CONST;
+uint64_t qpu_load_imm_u2(struct qpu_reg dst, uint32_t val) ATTRIBUTE_CONST;
+uint64_t qpu_load_imm_i2(struct qpu_reg dst, uint32_t val) ATTRIBUTE_CONST;
 uint64_t qpu_branch(uint32_t cond, uint32_t target) ATTRIBUTE_CONST;
 uint64_t qpu_set_sig(uint64_t inst, uint32_t sig) ATTRIBUTE_CONST;
 uint64_t qpu_set_cond_add(uint64_t inst, uint32_t cond) ATTRIBUTE_CONST;
diff --git a/src/gallium/drivers/vc4/vc4_qpu_defines.h 
b/src/gallium/drivers/vc4/vc4_qpu_defines.h
index 3ca5aba..e6ca345 100644

Mesa (master): vc4: Add register allocation support for MUL output rotation.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: e763e19808a84ae0218117c89864ff50cb6b0d16
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e763e19808a84ae0218117c89864ff50cb6b0d16

Author: Eric Anholt 
Date:   Thu Aug 25 14:32:47 2016 -0700

vc4: Add register allocation support for MUL output rotation.

We need the source to be in r0-r3, so make a new register class for it.
It will be up to the surrounding passes to make sure that the r0-r3
allocation of its source won't conflict with anything other class
requirements on that temp.

---

 src/gallium/drivers/vc4/vc4_context.h   |  1 +
 src/gallium/drivers/vc4/vc4_register_allocate.c | 13 +
 2 files changed, 14 insertions(+)

diff --git a/src/gallium/drivers/vc4/vc4_context.h 
b/src/gallium/drivers/vc4/vc4_context.h
index c3474a0..63a1dfb 100644
--- a/src/gallium/drivers/vc4/vc4_context.h
+++ b/src/gallium/drivers/vc4/vc4_context.h
@@ -283,6 +283,7 @@ struct vc4_context {
 struct ra_regs *regs;
 unsigned int reg_class_any;
 unsigned int reg_class_a_or_b_or_acc;
+unsigned int reg_class_r0_r3;
 unsigned int reg_class_r4_or_a;
 unsigned int reg_class_a;
 
diff --git a/src/gallium/drivers/vc4/vc4_register_allocate.c 
b/src/gallium/drivers/vc4/vc4_register_allocate.c
index 203b459..fc44764 100644
--- a/src/gallium/drivers/vc4/vc4_register_allocate.c
+++ b/src/gallium/drivers/vc4/vc4_register_allocate.c
@@ -119,6 +119,7 @@ vc4_alloc_reg_set(struct vc4_context *vc4)
 vc4->reg_class_a_or_b_or_acc = ra_alloc_reg_class(vc4->regs);
 vc4->reg_class_r4_or_a = ra_alloc_reg_class(vc4->regs);
 vc4->reg_class_a = ra_alloc_reg_class(vc4->regs);
+vc4->reg_class_r0_r3 = ra_alloc_reg_class(vc4->regs);
 for (uint32_t i = 0; i < ARRAY_SIZE(vc4_regs); i++) {
 /* Reserve ra31/rb31 for spilling fixup_raddr_conflict() in
  * vc4_qpu_emit.c
@@ -135,6 +136,9 @@ vc4_alloc_reg_set(struct vc4_context *vc4)
 continue;
 }
 
+if (vc4_regs[i].mux <= QPU_MUX_R3)
+ra_class_add_reg(vc4->regs, vc4->reg_class_r0_r3, i);
+
 ra_class_add_reg(vc4->regs, vc4->reg_class_any, i);
 ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b_or_acc, i);
 }
@@ -164,6 +168,7 @@ node_to_temp_priority(const void *in_a, const void *in_b)
 #define CLASS_BIT_A(1 << 0)
 #define CLASS_BIT_B_OR_ACC (1 << 1)
 #define CLASS_BIT_R4   (1 << 2)
+#define CLASS_BIT_R0_R3(1 << 4)
 
 /**
  * Returns a mapping from QFILE_TEMP indices to struct qpu_regs.
@@ -240,6 +245,11 @@ vc4_register_allocate(struct vc4_context *vc4, struct 
vc4_compile *c)
 AB_INDEX + QPU_R_FRAG_PAYLOAD_ZW * 2);
 break;
 
+case QOP_ROT_MUL:
+assert(inst->src[0].file == QFILE_TEMP);
+class_bits[inst->src[0].index] &= ~CLASS_BIT_R0_R3;
+break;
+
 default:
 break;
 }
@@ -287,6 +297,9 @@ vc4_register_allocate(struct vc4_context *vc4, struct 
vc4_compile *c)
 case CLASS_BIT_A:
 ra_set_node_class(g, node, vc4->reg_class_a);
 break;
+case CLASS_BIT_R0_R3:
+ra_set_node_class(g, node, vc4->reg_class_r0_r3);
+break;
 default:
 fprintf(stderr, "temp %d: bad class bits: 0x%x\n",
 i, class_bits[i]);

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Mesa (master): vc4: Add a QIR value for the QPU element register.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 31da39ddc92e780dc539bf34d2de7f82fc65fa86
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=31da39ddc92e780dc539bf34d2de7f82fc65fa86

Author: Eric Anholt 
Date:   Thu Aug 25 13:48:21 2016 -0700

vc4: Add a QIR value for the QPU element register.

This will be used in the ddx/ddy support for "Am I the top half?" or "Am I
the left half?" checks.

---

 src/gallium/drivers/vc4/vc4_qir.c  | 1 +
 src/gallium/drivers/vc4/vc4_qir.h  | 1 +
 src/gallium/drivers/vc4/vc4_qir_validate.c | 2 ++
 src/gallium/drivers/vc4/vc4_qpu_emit.c | 4 
 4 files changed, 8 insertions(+)

diff --git a/src/gallium/drivers/vc4/vc4_qir.c 
b/src/gallium/drivers/vc4/vc4_qir.c
index 9ff1561..0919d32 100644
--- a/src/gallium/drivers/vc4/vc4_qir.c
+++ b/src/gallium/drivers/vc4/vc4_qir.c
@@ -292,6 +292,7 @@ qir_print_reg(struct vc4_compile *c, struct qreg reg, bool 
write)
 [QFILE_FRAG_X] = "frag_x",
 [QFILE_FRAG_Y] = "frag_y",
 [QFILE_FRAG_REV_FLAG] = "frag_rev_flag",
+[QFILE_QPU_ELEMENT] = "elem",
 };
 
 switch (reg.file) {
diff --git a/src/gallium/drivers/vc4/vc4_qir.h 
b/src/gallium/drivers/vc4/vc4_qir.h
index 6b48959..9e61200 100644
--- a/src/gallium/drivers/vc4/vc4_qir.h
+++ b/src/gallium/drivers/vc4/vc4_qir.h
@@ -61,6 +61,7 @@ enum qfile {
 QFILE_FRAG_X,
 QFILE_FRAG_Y,
 QFILE_FRAG_REV_FLAG,
+QFILE_QPU_ELEMENT,
 
 /**
  * Stores an immediate value in the index field that will be used
diff --git a/src/gallium/drivers/vc4/vc4_qir_validate.c 
b/src/gallium/drivers/vc4/vc4_qir_validate.c
index e8d4372..e7cfe5a 100644
--- a/src/gallium/drivers/vc4/vc4_qir_validate.c
+++ b/src/gallium/drivers/vc4/vc4_qir_validate.c
@@ -79,6 +79,7 @@ void qir_validate(struct vc4_compile *c)
 case QFILE_FRAG_X:
 case QFILE_FRAG_Y:
 case QFILE_FRAG_REV_FLAG:
+case QFILE_QPU_ELEMENT:
 case QFILE_SMALL_IMM:
 case QFILE_LOAD_IMM:
 fail_instr(c, inst, "Bad dest file");
@@ -98,6 +99,7 @@ void qir_validate(struct vc4_compile *c)
 case QFILE_UNIF:
 case QFILE_VPM:
 case QFILE_LOAD_IMM:
+case QFILE_QPU_ELEMENT:
 break;
 
 case QFILE_SMALL_IMM:
diff --git a/src/gallium/drivers/vc4/vc4_qpu_emit.c 
b/src/gallium/drivers/vc4/vc4_qpu_emit.c
index 8249929..77aa4f6 100644
--- a/src/gallium/drivers/vc4/vc4_qpu_emit.c
+++ b/src/gallium/drivers/vc4/vc4_qpu_emit.c
@@ -339,6 +339,9 @@ vc4_generate_code_block(struct vc4_compile *c,
 case QFILE_FRAG_REV_FLAG:
 src[i] = qpu_rb(QPU_R_MS_REV_FLAGS);
 break;
+case QFILE_QPU_ELEMENT:
+src[i] = qpu_ra(QPU_R_ELEM_QPU);
+break;
 
 case QFILE_TLB_COLOR_WRITE:
 case QFILE_TLB_COLOR_WRITE_MS:
@@ -383,6 +386,7 @@ vc4_generate_code_block(struct vc4_compile *c,
 case QFILE_FRAG_X:
 case QFILE_FRAG_Y:
 case QFILE_FRAG_REV_FLAG:
+case QFILE_QPU_ELEMENT:
 assert(!"not reached");
 break;
 }

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Mesa (master): vc4: Add disassembly for constant MUL rotates

[Eric Anholt]

Module: Mesa
Branch: master
Commit: b0b99a7952675eea4b28b86899082a475f459a77
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0b99a7952675eea4b28b86899082a475f459a77

Author: Eric Anholt 
Date:   Thu Aug 25 13:26:50 2016 -0700

vc4: Add disassembly for constant MUL rotates

---

 src/gallium/drivers/vc4/vc4_qpu_disasm.c | 20 +++-
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/vc4/vc4_qpu_disasm.c 
b/src/gallium/drivers/vc4/vc4_qpu_disasm.c
index c902d4f..5294722 100644
--- a/src/gallium/drivers/vc4/vc4_qpu_disasm.c
+++ b/src/gallium/drivers/vc4/vc4_qpu_disasm.c
@@ -317,7 +317,7 @@ print_alu_dst(uint64_t inst, bool is_mul)
 }
 
 static void
-print_alu_src(uint64_t inst, uint32_t mux)
+print_alu_src(uint64_t inst, uint32_t mux, bool is_mul)
 {
 bool is_a = mux != QPU_MUX_B;
 const char *file = is_a ? "a" : "b";
@@ -325,12 +325,14 @@ print_alu_src(uint64_t inst, uint32_t mux)
   QPU_GET_FIELD(inst, QPU_RADDR_A) :
   QPU_GET_FIELD(inst, QPU_RADDR_B));
 uint32_t unpack = QPU_GET_FIELD(inst, QPU_UNPACK);
+bool has_si = QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_SMALL_IMM;
+uint32_t si = QPU_GET_FIELD(inst, QPU_SMALL_IMM);
 
-if (mux <= QPU_MUX_R5)
+if (mux <= QPU_MUX_R5) {
 fprintf(stderr, "r%d", mux);
-else if (!is_a &&
- QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_SMALL_IMM) {
-uint32_t si = QPU_GET_FIELD(inst, QPU_SMALL_IMM);
+if (has_si && is_mul && si >= QPU_SMALL_IMM_MUL_ROT + 1)
+fprintf(stderr, "+%d", si - QPU_SMALL_IMM_MUL_ROT);
+} else if (!is_a && has_si) {
 if (si <= 15)
 fprintf(stderr, "%d", si);
 else if (si <= 31)
@@ -380,12 +382,12 @@ print_add_op(uint64_t inst)
 print_alu_dst(inst, false);
 fprintf(stderr, ", ");
 
-print_alu_src(inst, QPU_GET_FIELD(inst, QPU_ADD_A));
+print_alu_src(inst, QPU_GET_FIELD(inst, QPU_ADD_A), false);
 
 if (!is_mov) {
 fprintf(stderr, ", ");
 
-print_alu_src(inst, QPU_GET_FIELD(inst, QPU_ADD_B));
+print_alu_src(inst, QPU_GET_FIELD(inst, QPU_ADD_B), false);
 }
 }
 
@@ -414,11 +416,11 @@ print_mul_op(uint64_t inst)
 print_alu_dst(inst, true);
 fprintf(stderr, ", ");
 
-print_alu_src(inst, QPU_GET_FIELD(inst, QPU_MUL_A));
+print_alu_src(inst, QPU_GET_FIELD(inst, QPU_MUL_A), true);
 
 if (!is_mov) {
 fprintf(stderr, ", ");
-print_alu_src(inst, QPU_GET_FIELD(inst, QPU_MUL_B));
+print_alu_src(inst, QPU_GET_FIELD(inst, QPU_MUL_B), true);
 }
 }
 

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Mesa (master): vc4: Add QPU scheduling to handle MUL rotate sources.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 3da4e38f4864f0ae4a588a000204042de5ea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3da4e38f4864f0ae4a588a000204042de5ea

Author: Eric Anholt 
Date:   Thu Aug 25 13:40:27 2016 -0700

vc4: Add QPU scheduling to handle MUL rotate sources.

We need MUL rotates to do ddx/ddy support.

---

 src/gallium/drivers/vc4/vc4_qpu_schedule.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/src/gallium/drivers/vc4/vc4_qpu_schedule.c 
b/src/gallium/drivers/vc4/vc4_qpu_schedule.c
index 1caee51..25adbe6 100644
--- a/src/gallium/drivers/vc4/vc4_qpu_schedule.c
+++ b/src/gallium/drivers/vc4/vc4_qpu_schedule.c
@@ -486,6 +486,19 @@ reads_too_soon_after_write(struct choose_scoreboard 
*scoreboard, uint64_t inst)
 }
 }
 
+if (sig == QPU_SIG_SMALL_IMM &&
+QPU_GET_FIELD(inst, QPU_SMALL_IMM) >= QPU_SMALL_IMM_MUL_ROT) {
+uint32_t mux_a = QPU_GET_FIELD(inst, QPU_MUL_A);
+uint32_t mux_b = QPU_GET_FIELD(inst, QPU_MUL_B);
+
+if (scoreboard->last_waddr_a == mux_a + QPU_W_ACC0 ||
+scoreboard->last_waddr_a == mux_b + QPU_W_ACC0 ||
+scoreboard->last_waddr_b == mux_a + QPU_W_ACC0 ||
+scoreboard->last_waddr_b == mux_b + QPU_W_ACC0) {
+return true;
+}
+}
+
 if (reads_uniform(inst) &&
 scoreboard->tick - scoreboard->last_uniforms_reset_tick <= 2) {
 return true;

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Mesa (master): vc4: Add support for MUL output rotation.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 8ce65261789f085e657e6a487db93d38ee6bea63
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ce65261789f085e657e6a487db93d38ee6bea63

Author: Eric Anholt 
Date:   Thu Aug 25 12:31:49 2016 -0700

vc4: Add support for MUL output rotation.

Extracted from a patch by jonasarrow on github.

---

 src/gallium/drivers/vc4/vc4_opt_copy_propagation.c |  8 
 src/gallium/drivers/vc4/vc4_qir.c  |  3 +++
 src/gallium/drivers/vc4/vc4_qir.h  | 12 
 src/gallium/drivers/vc4/vc4_qpu.c  | 13 +
 src/gallium/drivers/vc4/vc4_qpu.h  |  1 +
 src/gallium/drivers/vc4/vc4_qpu_emit.c | 14 ++
 6 files changed, 51 insertions(+)

diff --git a/src/gallium/drivers/vc4/vc4_opt_copy_propagation.c 
b/src/gallium/drivers/vc4/vc4_opt_copy_propagation.c
index f8f1365..d20ee5e 100644
--- a/src/gallium/drivers/vc4/vc4_opt_copy_propagation.c
+++ b/src/gallium/drivers/vc4/vc4_opt_copy_propagation.c
@@ -90,6 +90,14 @@ try_copy_prop(struct vc4_compile *c, struct qinst *inst, 
struct qinst **movs)
 continue;
 }
 
+/* Mul rotation's source needs to be in an r0-r3 accumulator,
+ * so no uniforms or regfile-a/r4 unpacking allowed.
+ */
+if (inst->op == QOP_ROT_MUL &&
+(mov->src[0].file != QFILE_TEMP ||
+ mov->src[0].pack))
+continue;
+
 uint8_t unpack;
 if (mov->src[0].pack) {
 /* Make sure that the meaning of the unpack
diff --git a/src/gallium/drivers/vc4/vc4_qir.c 
b/src/gallium/drivers/vc4/vc4_qir.c
index 9b4a28e..446af66 100644
--- a/src/gallium/drivers/vc4/vc4_qir.c
+++ b/src/gallium/drivers/vc4/vc4_qir.c
@@ -86,6 +86,8 @@ static const struct qir_op_info qir_op_info[] = {
 [QOP_LOAD_IMM_U2] = { "load_imm_u2", 0, 1 },
 [QOP_LOAD_IMM_I2] = { "load_imm_i2", 0, 1 },
 
+[QOP_ROT_MUL] = { "rot_mul", 0, 2 },
+
 [QOP_BRANCH] = { "branch", 0, 0, true },
 [QOP_UNIFORMS_RESET] = { "uniforms_reset", 0, 2, true },
 };
@@ -164,6 +166,7 @@ qir_is_mul(struct qinst *inst)
 case QOP_V8MAX:
 case QOP_V8ADDS:
 case QOP_V8SUBS:
+case QOP_ROT_MUL:
 return true;
 default:
 return false;
diff --git a/src/gallium/drivers/vc4/vc4_qir.h 
b/src/gallium/drivers/vc4/vc4_qir.h
index 90cc138..a82c47c 100644
--- a/src/gallium/drivers/vc4/vc4_qir.h
+++ b/src/gallium/drivers/vc4/vc4_qir.h
@@ -168,6 +168,8 @@ enum qop {
  */
 QOP_LOAD_IMM_I2,
 
+QOP_ROT_MUL,
+
 /* Jumps to block->successor[0] if the qinst->cond (as a
  * QPU_COND_BRANCH_*) passes, or block->successor[1] if not.  Note
  * that block->successor[1] may be unset if the condition is ALWAYS.
@@ -822,6 +824,16 @@ qir_LOAD_IMM_I2(struct vc4_compile *c, uint32_t val)
 c->undef));
 }
 
+/** Shifts the multiply output to the right by rot channels */
+static inline struct qreg
+qir_ROT_MUL(struct vc4_compile *c, struct qreg val, uint32_t rot)
+{
+return qir_emit_def(c, qir_inst(QOP_ROT_MUL, c->undef,
+val,
+qir_reg(QFILE_LOAD_IMM,
+QPU_SMALL_IMM_MUL_ROT + rot)));
+}
+
 static inline void
 qir_MOV_cond(struct vc4_compile *c, uint8_t cond,
  struct qreg dest, struct qreg src)
diff --git a/src/gallium/drivers/vc4/vc4_qpu.c 
b/src/gallium/drivers/vc4/vc4_qpu.c
index d022d10..67850a8 100644
--- a/src/gallium/drivers/vc4/vc4_qpu.c
+++ b/src/gallium/drivers/vc4/vc4_qpu.c
@@ -234,6 +234,19 @@ qpu_m_alu2(enum qpu_op_mul op,
 return inst;
 }
 
+uint64_t
+qpu_m_rot(struct qpu_reg dst, struct qpu_reg src0, int rot)
+{
+   uint64_t inst = 0;
+   inst = qpu_m_alu2(QPU_M_V8MIN, dst, src0, src0);
+
+   inst = QPU_UPDATE_FIELD(inst, QPU_SIG_SMALL_IMM, QPU_SIG);
+   inst = QPU_UPDATE_FIELD(inst, QPU_SMALL_IMM_MUL_ROT + rot,
+QPU_SMALL_IMM);
+
+   return inst;
+}
+
 static bool
 merge_fields(uint64_t *merge,
  uint64_t a, uint64_t b,
diff --git a/src/gallium/drivers/vc4/vc4_qpu.h 
b/src/gallium/drivers/vc4/vc4_qpu.h
index 437e4f5..5ec80f0 100644
--- a/src/gallium/drivers/vc4/vc4_qpu.h
+++ b/src/gallium/drivers/vc4/vc4_qpu.h
@@ -150,6 +150,7 @@ uint64_t qpu_set_sig(uint64_t inst, uint32_t sig) 
ATTRIBUTE_CONST;
 uint64_t qpu_set_cond_add(uint64_t inst, uint32_t cond) ATTRIBUTE_CONST;
 uint64_t qpu_set_cond_mul(uint64_t inst, uint32_t cond) ATTRIBUTE_CONST;
 uint32_t qpu_encode_small_immediate(uint32_t i) ATTRIBUTE_CONST;
+uint64_t qpu_m_rot(struct qpu_reg dst, struct qpu_reg src, int rot) 
ATTRIBUTE_CONST;
 
 bool 

Mesa (master): vc4: Add real validation for MUL rotation.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: b160708e0307ea0baa2c7891ad9760cdfd39b4bc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b160708e0307ea0baa2c7891ad9760cdfd39b4bc

Author: Eric Anholt 
Date:   Thu Aug 25 13:21:58 2016 -0700

vc4: Add real validation for MUL rotation.

Caught problems in the upcoming DDX/DDY implementation.

---

 src/gallium/drivers/vc4/vc4_qpu_defines.h  |  4 +++
 src/gallium/drivers/vc4/vc4_qpu_validate.c | 49 --
 2 files changed, 43 insertions(+), 10 deletions(-)

diff --git a/src/gallium/drivers/vc4/vc4_qpu_defines.h 
b/src/gallium/drivers/vc4/vc4_qpu_defines.h
index c0b7c56..3ca5aba 100644
--- a/src/gallium/drivers/vc4/vc4_qpu_defines.h
+++ b/src/gallium/drivers/vc4/vc4_qpu_defines.h
@@ -286,6 +286,10 @@ enum qpu_unpack {
 #define QPU_RADDR_B_MASKQPU_MASK(17, 12)
 #define QPU_SMALL_IMM_SHIFT 12
 #define QPU_SMALL_IMM_MASK  QPU_MASK(17, 12)
+/* Small immediate value for rotate-by-r5, and 49-63 are "rotate by n
+ * channels"
+ */
+#define QPU_SMALL_IMM_MUL_ROT  48
 
 #define QPU_ADD_A_SHIFT 9
 #define QPU_ADD_A_MASK  QPU_MASK(11, 9)
diff --git a/src/gallium/drivers/vc4/vc4_qpu_validate.c 
b/src/gallium/drivers/vc4/vc4_qpu_validate.c
index 10bb84d..02fadaf 100644
--- a/src/gallium/drivers/vc4/vc4_qpu_validate.c
+++ b/src/gallium/drivers/vc4/vc4_qpu_validate.c
@@ -258,19 +258,48 @@ vc4_qpu_validate(uint64_t *insts, uint32_t num_inst)
 last_sfu_inst = i;
 }
 
-int last_r5_write = -10;
 for (int i = 0; i < num_inst - 1; i++) {
 uint64_t inst = insts[i];
 
-/* "An instruction that does a vector rotate by r5 must not
- *  immediately follow an instruction that writes to r5."
- */
-if (last_r5_write == i - 1 &&
-QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_SMALL_IMM &&
-QPU_GET_FIELD(inst, QPU_SMALL_IMM) == 48) {
-fail_instr(inst,
-   "vector rotate by r5 immediately "
-   "after r5 write");
+if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_SMALL_IMM &&
+QPU_GET_FIELD(inst, QPU_SMALL_IMM) >=
+QPU_SMALL_IMM_MUL_ROT) {
+uint32_t mux_a = QPU_GET_FIELD(inst, QPU_MUL_A);
+uint32_t mux_b = QPU_GET_FIELD(inst, QPU_MUL_B);
+
+/* "The full horizontal vector rotate is only
+ *  available when both of the mul ALU input arguments
+ *  are taken from accumulators r0-r3."
+ */
+if (mux_a > QPU_MUX_R3 || mux_b > QPU_MUX_R3) {
+fail_instr(inst,
+   "MUL rotate using non-accumulator "
+   "input");
+}
+
+if (QPU_GET_FIELD(inst, QPU_SMALL_IMM) ==
+QPU_SMALL_IMM_MUL_ROT) {
+/* "An instruction that does a vector rotate
+ *  by r5 must not immediately follow an
+ *  instruction that writes to r5."
+ */
+if (writes_reg(insts[i - 1], QPU_W_ACC5)) {
+fail_instr(inst,
+   "vector rotate by r5 "
+   "immediately after r5 
write");
+}
+}
+
+/* "An instruction that does a vector rotate must not
+ *  immediately follow an instruction that writes to 
the
+ *  accumulator that is being rotated."
+ */
+if (writes_reg(insts[i - 1], QPU_W_ACC0 + mux_a) ||
+writes_reg(insts[i - 1], QPU_W_ACC0 + mux_b)) {
+fail_instr(inst,
+   "vector rotate of value "
+   "written in previous instruction");
+}
 }
 }
 

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Mesa (master): i965: Respect miptree offsets in intel_readpixels_tiled_memcpy()

[Chad Versace]

Module: Mesa
Branch: master
Commit: 5b03975889046640a0b87fb08cf06e8fb7ef9953
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b03975889046640a0b87fb08cf06e8fb7ef9953

Author: Chad Versace 
Date:   Thu Aug 25 16:08:27 2016 -0700

i965: Respect miptree offsets in intel_readpixels_tiled_memcpy()

Respect intel_miptree_slice::x_offset,y_offset and
intel_mipmap_tree::offset. All three may be non-zero when glReadPixels
is called on an EGLImage created from the non-base slice of a miptree.

Patch 2/2 that fixes test
'dEQP-EGL.functional.image.create.gles2_cubemap_*'.

Reported-by: Haixia Shi 
Diagnosed-by: Haixia Shi 
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Kenneth Graunke 
Change-Id: I4b397b27e55a743a7094d29fb0a6a4b6b34352b0

---

 src/mesa/drivers/dri/i965/intel_pixel_read.c | 21 -
 1 file changed, 4 insertions(+), 17 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c 
b/src/mesa/drivers/dri/i965/intel_pixel_read.c
index a486d6e..cacd7e2 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c
@@ -110,22 +110,6 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx,
if (ctx->_ImageTransferState)
   return false;
 
-   /* This renderbuffer can come from a texture.  In this case, we impose
-* some of the same restrictions we have for textures and adjust for
-* miplevels.
-*/
-   if (rb->TexImage) {
-  if (rb->TexImage->TexObject->Target != GL_TEXTURE_2D &&
-  rb->TexImage->TexObject->Target != GL_TEXTURE_RECTANGLE)
- return false;
-
-  int level = rb->TexImage->Level + rb->TexImage->TexObject->MinLevel;
-
-  /* Adjust x and y offset based on miplevel */
-  xoffset += irb->mt->level[level].level_x;
-  yoffset += irb->mt->level[level].level_y;
-   }
-
/* It is possible that the renderbuffer (or underlying texture) is
 * multisampled.  Since ReadPixels from a multisampled buffer requires a
 * multisample resolve, we can't handle this here
@@ -169,6 +153,9 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx,
   return false;
}
 
+   xoffset += irb->mt->level[irb->mt_level].slice[irb->mt_layer].x_offset;
+   yoffset += irb->mt->level[irb->mt_level].slice[irb->mt_layer].y_offset;
+
dst_pitch = _mesa_image_row_stride(pack, width, format, type);
 
/* For a window-system renderbuffer, the buffer is actually flipped
@@ -201,7 +188,7 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx,
   xoffset * cpp, (xoffset + width) * cpp,
   yoffset, yoffset + height,
   pixels - (ptrdiff_t) yoffset * dst_pitch - (ptrdiff_t) xoffset * cpp,
-  bo->virtual,
+  bo->virtual + irb->mt->offset,
   dst_pitch, irb->mt->pitch,
   brw->has_swizzling,
   irb->mt->tiling,

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Mesa (master): i965: Fix miptree layout for EGLImage-based renderbuffers

[Chad Versace]

Module: Mesa
Branch: master
Commit: c82f99e883cfa66b3a3b135e7b1dab0a5bfae164
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c82f99e883cfa66b3a3b135e7b1dab0a5bfae164

Author: Chad Versace 
Date:   Thu Aug 25 16:08:15 2016 -0700

i965: Fix miptree layout for EGLImage-based renderbuffers

When glEGLImageTargetRenderbufferStorageOES() was given an EGLImage
created from the non-base slice of a miptree,
intel_image_target_renderbuffer_storage() forgot to apply the intra-tile
offsets __DRIimage::tile_x,tile_y to the miptree layout.

This patch fixes the problem with a quick hack suitable for
cherry-picking. A proper fix requires more thorough plumbing in
intel_miptree_create_layout() and brw_tex_layout().

Patch 1/2 that fixes test
'dEQP-EGL.functional.image.create.gles2_cubemap_*'.

Reported-by: Haixia Shi 
Diagnosed-by: Haixia Shi 
Reviewed-by: Kenneth Graunke 
Cc: mesa-sta...@lists.freedesktop.org
Change-Id: I8a64b0048a1ee9e714ebb3f33fffd8334036450b

---

 src/mesa/drivers/dri/i965/intel_fbo.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c 
b/src/mesa/drivers/dri/i965/intel_fbo.c
index 03ea791..89bf7d1 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -375,6 +375,19 @@ intel_image_target_renderbuffer_storage(struct gl_context 
*ctx,
if (!irb->mt)
   return;
 
+   /* Adjust the miptree's upper-left coordinate.
+*
+* FIXME: Adjusting the miptree's layout outside of
+* intel_miptree_create_layout() is fragile. Plumb the adjustment through
+* intel_miptree_create_layout() and brw_tex_layout().
+*/
+   irb->mt->level[0].level_x = image->tile_x;
+   irb->mt->level[0].level_y = image->tile_y;
+   irb->mt->level[0].slice[0].x_offset = image->tile_x;
+   irb->mt->level[0].slice[0].y_offset = image->tile_y;
+   irb->mt->total_width += image->tile_x;
+   irb->mt->total_height += image->tile_y;
+
rb->InternalFormat = image->internal_format;
rb->Width = image->width;
rb->Height = image->height;

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Mesa (master): i965: Implement GL_KHR_blend_equation_advanced_coherent on Gen9+.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 219a451497d1138c12f927139c6e8aa94a116e53
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=219a451497d1138c12f927139c6e8aa94a116e53

Author: Kenneth Graunke 
Date:   Wed Jun 29 22:16:49 2016 -0700

i965: Implement GL_KHR_blend_equation_advanced_coherent on Gen9+.

We always use a coherent read, and ignore the "opt out" enable flag.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Francisco Jerez 

---

 src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 48e8299..dd0d240 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -399,6 +399,7 @@ intelInitExtensions(struct gl_context *ctx)
}
 
if (brw->gen >= 9) {
+  ctx->Extensions.KHR_blend_equation_advanced_coherent = true;
   ctx->Extensions.KHR_texture_compression_astc_ldr = true;
   ctx->Extensions.KHR_texture_compression_astc_sliced_3d = true;
   ctx->Extensions.ARB_shader_stencil_export = true;

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Mesa (master): glsl: process blend_support_* qualifiers

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 4b6819b407220f5d7d97a40ed9474d7673448370
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4b6819b407220f5d7d97a40ed9474d7673448370

Author: Ilia Mirkin 
Date:   Fri Apr  1 22:51:39 2016 -0400

glsl: process blend_support_* qualifiers

v2 (Ken): Add a BLEND_NONE enum value (no qualifiers in use).
v3 (Ken): Rename gl_blend_support_qualifier to gl_advanced_blend_mode.
v4 (Ken): Mark map[] as static const (Ilia).

Signed-off-by: Ilia Mirkin 
Reviewed-by: Kenneth Graunke 
Reviewed-by: Francisco Jerez 

---

 src/compiler/glsl/ast.h  |  5 
 src/compiler/glsl/ast_type.cpp   |  2 ++
 src/compiler/glsl/glsl_parser.yy | 45 
 src/compiler/glsl/glsl_parser_extras.cpp |  2 ++
 src/compiler/glsl/glsl_parser_extras.h   |  2 ++
 src/compiler/shader_enums.h  | 26 ++
 src/mesa/main/mtypes.h   |  5 
 7 files changed, 87 insertions(+)

diff --git a/src/compiler/glsl/ast.h b/src/compiler/glsl/ast.h
index 75018a0..4c648d0 100644
--- a/src/compiler/glsl/ast.h
+++ b/src/compiler/glsl/ast.h
@@ -596,6 +596,11 @@ struct ast_type_qualifier {
  unsigned subroutine:1;  /**< Is this marked 'subroutine' */
  unsigned subroutine_def:1; /**< Is this marked 'subroutine' with a 
list of types */
 /** \} */
+
+ /** \name Qualifiers for GL_KHR_blend_equation_advanced */
+ /** \{ */
+ unsigned blend_support:1; /**< Are there any blend_support_ 
qualifiers */
+ /** \} */
   }
   /** \brief Set of flags, accessed by name. */
   q;
diff --git a/src/compiler/glsl/ast_type.cpp b/src/compiler/glsl/ast_type.cpp
index cabc698..f3f6b29 100644
--- a/src/compiler/glsl/ast_type.cpp
+++ b/src/compiler/glsl/ast_type.cpp
@@ -414,6 +414,8 @@ ast_type_qualifier::merge_out_qualifier(YYLTYPE *loc,
   valid_out_mask.flags.q.xfb_buffer = 1;
   valid_out_mask.flags.q.explicit_xfb_stride = 1;
   valid_out_mask.flags.q.xfb_stride = 1;
+   } else if (state->stage == MESA_SHADER_FRAGMENT) {
+  valid_out_mask.flags.q.blend_support = 1;
} else {
   _mesa_glsl_error(loc, state, "out layout qualifiers only valid in "
"geometry, tessellation and vertex shaders");
diff --git a/src/compiler/glsl/glsl_parser.yy b/src/compiler/glsl/glsl_parser.yy
index f2853da..4043dae 100644
--- a/src/compiler/glsl/glsl_parser.yy
+++ b/src/compiler/glsl/glsl_parser.yy
@@ -1447,6 +1447,51 @@ layout_qualifier_id:
   }
 
   if (!$$.flags.i) {
+ static const struct {
+const char *s;
+uint32_t mask;
+ } map[] = {
+ { "blend_support_multiply",   BLEND_MULTIPLY },
+ { "blend_support_screen", BLEND_SCREEN },
+ { "blend_support_overlay",BLEND_OVERLAY },
+ { "blend_support_darken", BLEND_DARKEN },
+ { "blend_support_lighten",BLEND_LIGHTEN },
+ { "blend_support_colordodge", BLEND_COLORDODGE },
+ { "blend_support_colorburn",  BLEND_COLORBURN },
+ { "blend_support_hardlight",  BLEND_HARDLIGHT },
+ { "blend_support_softlight",  BLEND_SOFTLIGHT },
+ { "blend_support_difference", BLEND_DIFFERENCE },
+ { "blend_support_exclusion",  BLEND_EXCLUSION },
+ { "blend_support_hsl_hue",BLEND_HSL_HUE },
+ { "blend_support_hsl_saturation", BLEND_HSL_SATURATION },
+ { "blend_support_hsl_color",  BLEND_HSL_COLOR },
+ { "blend_support_hsl_luminosity", BLEND_HSL_LUMINOSITY },
+ { "blend_support_all_equations",  BLEND_ALL },
+ };
+ for (unsigned i = 0; i < ARRAY_SIZE(map); i++) {
+if (match_layout_qualifier($1, map[i].s, state) == 0) {
+   $$.flags.q.blend_support = 1;
+   state->fs_blend_support |= map[i].mask;
+   break;
+}
+ }
+
+ if ($$.flags.i &&
+ !state->KHR_blend_equation_advanced_enable &&
+ !state->is_version(0, 320)) {
+_mesa_glsl_error(& @1, state,
+ "advanced blending layout qualifiers require "
+ "ESSL 3.20 or KHR_blend_equation_advanced");
+ }
+
+ if ($$.flags.i && state->stage != MESA_SHADER_FRAGMENT) {
+_mesa_glsl_error(& @1, state,
+ "advanced blending layout qualifiers only "
+ "valid in fragment shaders");
+ }
+  }
+
+  if (!$$.flags.i) {
  _mesa_glsl_error(& @1, state, "unrecognized layout identifier "
   "`%s'", $1);
  YYERROR;
diff --git 

Mesa (master): mesa: Implement GL_KHR_blend_equation_advanced_coherent.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 1bf9b2a6008552f5fdb8908c24c446fd7261efdd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1bf9b2a6008552f5fdb8908c24c446fd7261efdd

Author: Kenneth Graunke 
Date:   Wed Jun 29 21:53:06 2016 -0700

mesa: Implement GL_KHR_blend_equation_advanced_coherent.

This adds the extension enable (so drivers can advertise it) and the
extra boolean state flag, GL_BLEND_ADVANCED_COHERENT_KHR, which can
be set to request coherent blending.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Francisco Jerez 

---

 src/mesa/main/blend.c|  2 ++
 src/mesa/main/enable.c   | 12 
 src/mesa/main/extensions_table.h |  1 +
 src/mesa/main/get.c  |  1 +
 src/mesa/main/get_hash_params.py |  3 +++
 src/mesa/main/mtypes.h   |  4 
 6 files changed, 23 insertions(+)

diff --git a/src/mesa/main/blend.c b/src/mesa/main/blend.c
index de6d3c4..ad79ee0 100644
--- a/src/mesa/main/blend.c
+++ b/src/mesa/main/blend.c
@@ -1039,6 +1039,8 @@ void _mesa_init_color( struct gl_context * ctx )
 * if EGL_KHR_gl_colorspace has been used to request sRGB.
 */
ctx->Color.sRGBEnabled = _mesa_is_gles(ctx);
+
+   ctx->Color.BlendCoherent = true;
 }
 
 /*@}*/
diff --git a/src/mesa/main/enable.c b/src/mesa/main/enable.c
index 1468a45..d1ab81e 100644
--- a/src/mesa/main/enable.c
+++ b/src/mesa/main/enable.c
@@ -1017,6 +1017,14 @@ _mesa_set_enable(struct gl_context *ctx, GLenum cap, 
GLboolean state)
  ctx->Multisample.SampleMask = state;
  break;
 
+  case GL_BLEND_ADVANCED_COHERENT_KHR:
+ CHECK_EXTENSION(KHR_blend_equation_advanced_coherent, cap);
+ if (ctx->Color.BlendCoherent == state)
+return;
+ FLUSH_VERTICES(ctx, _NEW_COLOR);
+ ctx->Color.BlendCoherent = state;
+ break;
+
   default:
  goto invalid_enum_error;
}
@@ -1619,6 +1627,10 @@ _mesa_IsEnabled( GLenum cap )
  CHECK_EXTENSION(ARB_sample_shading);
  return ctx->Multisample.SampleShading;
 
+  case GL_BLEND_ADVANCED_COHERENT_KHR:
+ CHECK_EXTENSION(KHR_blend_equation_advanced_coherent);
+ return ctx->Color.BlendCoherent;
+
   default:
  goto invalid_enum_error;
}
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index e8c825b..c6fdd2c 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -283,6 +283,7 @@ EXT(INGR_blend_func_separate, 
EXT_blend_func_separate
 EXT(INTEL_performance_query , INTEL_performance_query  
  , GLL, GLC,  x , ES2, 2013)
 
 EXT(KHR_blend_equation_advanced , KHR_blend_equation_advanced  
  , GLL, GLC,  x , ES2, 2014)
+EXT(KHR_blend_equation_advanced_coherent, 
KHR_blend_equation_advanced_coherent   , GLL, GLC,  x , ES2, 2014)
 EXT(KHR_context_flush_control   , dummy_true   
  , GLL, GLC,  x , ES2, 2014)
 EXT(KHR_debug   , dummy_true   
  , GLL, GLC,  11, ES2, 2012)
 EXT(KHR_robust_buffer_access_behavior   , 
ARB_robust_buffer_access_behavior  , GLL, GLC,  x , ES2, 2014)
diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index b017827..97dfb0c 100644
--- a/src/mesa/main/get.c
+++ b/src/mesa/main/get.c
@@ -465,6 +465,7 @@ EXTRA_EXT(ATI_meminfo);
 EXTRA_EXT(NVX_gpu_memory_info);
 EXTRA_EXT(ARB_cull_distance);
 EXTRA_EXT(EXT_window_rectangles);
+EXTRA_EXT(KHR_blend_equation_advanced_coherent);
 
 static const int
 extra_ARB_color_buffer_float_or_glcore[] = {
diff --git a/src/mesa/main/get_hash_params.py b/src/mesa/main/get_hash_params.py
index 89d164d..3414743 100644
--- a/src/mesa/main/get_hash_params.py
+++ b/src/mesa/main/get_hash_params.py
@@ -338,6 +338,9 @@ descriptor=[
 
 # blend_func_extended
   [ "MAX_DUAL_SOURCE_DRAW_BUFFERS", 
"CONTEXT_INT(Const.MaxDualSourceDrawBuffers), extra_ARB_blend_func_extended" ],
+
+# GL_KHR_blend_equation_advanced_coherent
+  [ "BLEND_ADVANCED_COHERENT_KHR", "CONTEXT_BOOL(Color.BlendCoherent), 
extra_KHR_blend_equation_advanced_coherent" ],
 ]},
 
 # GLES3 is not a typo.
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 3e12555..7637160 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -461,6 +461,9 @@ struct gl_colorbuffer_attrib
 * requires all draw buffers to match, so we only need a single value.
 */
enum gl_advanced_blend_mode _AdvancedBlendMode;
+
+   /** Coherency requested via glEnable(GL_BLEND_ADVANCED_COHERENT_KHR)? */
+   bool BlendCoherent;
/*@}*/
 
/** 
@@ -3957,6 +3960,7 @@ struct gl_extensions
GLboolean GREMEDY_string_marker;
GLboolean INTEL_performance_query;
GLboolean KHR_blend_equation_advanced;
+   GLboolean KHR_blend_equation_advanced_coherent;
GLboolean KHR_robustness;
GLboolean KHR_texture_compression_astc_hdr;
   

Mesa (master): nir: Make nir_lower_io_to_temporaries store an impl internally.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 8479b03c5826f32355775d865d99d69c829e65bb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8479b03c5826f32355775d865d99d69c829e65bb

Author: Kenneth Graunke 
Date:   Wed Aug 24 19:15:53 2016 -0700

nir: Make nir_lower_io_to_temporaries store an impl internally.

This changes the pass internals to work with a nir_function_impl
directly rather than a nir_function.  The next patch will change
the API.

v2: Rebase after framebuffer fetch landed.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Jason Ekstrand 
Reviewed-by: Connor Abbott 

---

 src/compiler/nir/nir_lower_io_to_temporaries.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/compiler/nir/nir_lower_io_to_temporaries.c 
b/src/compiler/nir/nir_lower_io_to_temporaries.c
index c8f94ff..8cbf683 100644
--- a/src/compiler/nir/nir_lower_io_to_temporaries.c
+++ b/src/compiler/nir/nir_lower_io_to_temporaries.c
@@ -34,7 +34,7 @@
 
 struct lower_io_state {
nir_shader *shader;
-   nir_function *entrypoint;
+   nir_function_impl *entrypoint;
struct exec_list old_outputs;
struct exec_list old_inputs;
 };
@@ -93,7 +93,7 @@ emit_output_copies_impl(struct lower_io_state *state, 
nir_function_impl *impl)
 }
  }
   }
-   } else if (impl->function == state->entrypoint) {
+   } else if (impl == state->entrypoint) {
   nir_cursor cursor = nir_before_block(nir_start_block(impl));
   emit_copies(cursor, state->shader, >old_outputs,
   >shader->outputs);
@@ -114,7 +114,7 @@ emit_output_copies_impl(struct lower_io_state *state, 
nir_function_impl *impl)
 static void
 emit_input_copies_impl(struct lower_io_state *state, nir_function_impl *impl)
 {
-   if (impl->function == state->entrypoint) {
+   if (impl == state->entrypoint) {
   nir_cursor cursor = nir_before_block(nir_start_block(impl));
   emit_copies(cursor, state->shader, >old_inputs,
   >shader->inputs);
@@ -157,7 +157,7 @@ nir_lower_io_to_temporaries(nir_shader *shader, 
nir_function *entrypoint,
   return;
 
state.shader = shader;
-   state.entrypoint = entrypoint;
+   state.entrypoint = entrypoint->impl;
 
if (inputs)
   exec_list_move_nodes_to(>inputs, _inputs);

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Mesa (master): nir: Use nir_shader_get_entrypoint in TCS quad workaround code.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 3203fe3d509b6a0e44c82384fba1dcc4c8c43dc6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3203fe3d509b6a0e44c82384fba1dcc4c8c43dc6

Author: Kenneth Graunke 
Date:   Thu Aug 18 10:56:48 2016 -0700

nir: Use nir_shader_get_entrypoint in TCS quad workaround code.

We want to insert the code at the end of the program.  Looping over
all the functions (of which there was only one) was the old way of doing
this, but now we have nir_shader_get_entrypoint(), so let's use it.

Suggested by Connor Abbott.

v2: Update for nir_shader_get_entrypoint API change.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Jason Ekstrand 
Reviewed-by: Connor Abbott 

---

 src/mesa/drivers/dri/i965/brw_nir_tcs_workarounds.c | 21 +
 1 file changed, 9 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_nir_tcs_workarounds.c 
b/src/mesa/drivers/dri/i965/brw_nir_tcs_workarounds.c
index 0626981..6524b7d 100644
--- a/src/mesa/drivers/dri/i965/brw_nir_tcs_workarounds.c
+++ b/src/mesa/drivers/dri/i965/brw_nir_tcs_workarounds.c
@@ -134,19 +134,16 @@ brw_nir_apply_tcs_quads_workaround(nir_shader *nir)
 {
assert(nir->stage == MESA_SHADER_TESS_CTRL);
 
-   nir_foreach_function(func, nir) {
-  if (!func->impl)
- continue;
+   nir_function_impl *impl = nir_shader_get_entrypoint(nir);
 
-  nir_builder b;
-  nir_builder_init(, func->impl);
+   nir_builder b;
+   nir_builder_init(, impl);
 
-  struct set_entry *entry;
-  set_foreach(func->impl->end_block->predecessors, entry) {
- nir_block *pred = (nir_block *) entry->key;
- emit_quads_workaround(, pred);
-  }
-
-  nir_metadata_preserve(func->impl, 0);
+   struct set_entry *entry;
+   set_foreach(impl->end_block->predecessors, entry) {
+  nir_block *pred = (nir_block *) entry->key;
+  emit_quads_workaround(, pred);
}
+
+   nir_metadata_preserve(impl, 0);
 }

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Mesa (master): glsl: add basic KHR_blend_equation_advanced infrastructure

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: e682f945944d7411a87acb4361b11d3ff09aac9f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e682f945944d7411a87acb4361b11d3ff09aac9f

Author: Ilia Mirkin 
Date:   Fri Apr  1 22:17:27 2016 -0400

glsl: add basic KHR_blend_equation_advanced infrastructure

Signed-off-by: Ilia Mirkin 
Reviewed-by: Kenneth Graunke 
Reviewed-by: Francisco Jerez 

---

 src/compiler/glsl/glsl_parser_extras.cpp | 1 +
 src/compiler/glsl/glsl_parser_extras.h   | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
b/src/compiler/glsl/glsl_parser_extras.cpp
index a185759..1ca49b3 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -622,6 +622,7 @@ static const _mesa_glsl_extension 
_mesa_glsl_supported_extensions[] = {
 
/* KHR extensions go here, sorted alphabetically.
 */
+   EXT(KHR_blend_equation_advanced),
 
/* OES extensions go here, sorted alphabetically.
 */
diff --git a/src/compiler/glsl/glsl_parser_extras.h 
b/src/compiler/glsl/glsl_parser_extras.h
index 3311688..ad29149 100644
--- a/src/compiler/glsl/glsl_parser_extras.h
+++ b/src/compiler/glsl/glsl_parser_extras.h
@@ -649,6 +649,8 @@ struct _mesa_glsl_parse_state {
 
/* KHR extensions go here, sorted alphabetically.
 */
+   bool KHR_blend_equation_advanced_enable;
+   bool KHR_blend_equation_advanced_warn;
 
/* OES extensions go here, sorted alphabetically.
 */

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Mesa (master): mesa: Track the current advanced blending mode.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 0745e039a2a9d6763f9a1a241fba18bdbd74ad85
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0745e039a2a9d6763f9a1a241fba18bdbd74ad85

Author: Kenneth Graunke 
Date:   Tue Jun 28 08:17:57 2016 -0700

mesa: Track the current advanced blending mode.

This will be useful for a number of things:
- Checking the current advanced blending mode against the shader's
  blend_support_* qualifiers.
- Disabling hardware blending when emulating advanced blending.
- Uploading the current advanced blending mode as a state var.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Francisco Jerez 

---

 src/mesa/main/blend.c  | 54 ++
 src/mesa/main/mtypes.h |  9 +
 2 files changed, 50 insertions(+), 13 deletions(-)

diff --git a/src/mesa/main/blend.c b/src/mesa/main/blend.c
index fe83e59..de6d3c4 100644
--- a/src/mesa/main/blend.c
+++ b/src/mesa/main/blend.c
@@ -355,36 +355,57 @@ legal_simple_blend_equation(const struct gl_context *ctx, 
GLenum mode)
}
 }
 
-
-/**
- * Return true if \p mode is one of the advanced blending equations
- * defined by GL_KHR_blend_equation_advanced.
- */
-static bool
-legal_advanced_blend_equation(const struct gl_context *ctx, GLenum mode)
+static enum gl_advanced_blend_mode
+advanced_blend_mode_from_gl_enum(GLenum mode)
 {
switch (mode) {
case GL_MULTIPLY_KHR:
+  return BLEND_MULTIPLY;
case GL_SCREEN_KHR:
+  return BLEND_SCREEN;
case GL_OVERLAY_KHR:
+  return BLEND_OVERLAY;
case GL_DARKEN_KHR:
+  return BLEND_DARKEN;
case GL_LIGHTEN_KHR:
+  return BLEND_LIGHTEN;
case GL_COLORDODGE_KHR:
+  return BLEND_COLORDODGE;
case GL_COLORBURN_KHR:
+  return BLEND_COLORBURN;
case GL_HARDLIGHT_KHR:
+  return BLEND_HARDLIGHT;
case GL_SOFTLIGHT_KHR:
+  return BLEND_SOFTLIGHT;
case GL_DIFFERENCE_KHR:
+  return BLEND_DIFFERENCE;
case GL_EXCLUSION_KHR:
+  return BLEND_EXCLUSION;
case GL_HSL_HUE_KHR:
+  return BLEND_HSL_HUE;
case GL_HSL_SATURATION_KHR:
+  return BLEND_HSL_SATURATION;
case GL_HSL_COLOR_KHR:
+  return BLEND_HSL_COLOR;
case GL_HSL_LUMINOSITY_KHR:
-  return _mesa_has_KHR_blend_equation_advanced(ctx);
+  return BLEND_HSL_LUMINOSITY;
default:
-  return false;
+  return BLEND_NONE;
}
 }
 
+/**
+ * If \p mode is one of the advanced blending equations defined by
+ * GL_KHR_blend_equation_advanced (and the extension is supported),
+ * return the corresponding BLEND_* enum.  Otherwise, return BLEND_NONE
+ * (which can also be treated as false).
+ */
+static enum gl_advanced_blend_mode
+advanced_blend_mode(const struct gl_context *ctx, GLenum mode)
+{
+   return _mesa_has_KHR_blend_equation_advanced(ctx) ?
+  advanced_blend_mode_from_gl_enum(mode) : BLEND_NONE;
+}
 
 /* This is really an extension function! */
 void GLAPIENTRY
@@ -394,6 +415,7 @@ _mesa_BlendEquation( GLenum mode )
const unsigned numBuffers = num_buffers(ctx);
unsigned buf;
bool changed = false;
+   enum gl_advanced_blend_mode advanced_mode = advanced_blend_mode(ctx, mode);
 
if (MESA_VERBOSE & VERBOSE_API)
   _mesa_debug(ctx, "glBlendEquation(%s)\n",
@@ -420,8 +442,8 @@ _mesa_BlendEquation( GLenum mode )
if (!changed)
   return;
 
-   if (!legal_simple_blend_equation(ctx, mode) &&
-   !legal_advanced_blend_equation(ctx, mode)) {
+
+   if (!legal_simple_blend_equation(ctx, mode) && !advanced_mode) {
   _mesa_error(ctx, GL_INVALID_ENUM, "glBlendEquation");
   return;
}
@@ -433,6 +455,7 @@ _mesa_BlendEquation( GLenum mode )
   ctx->Color.Blend[buf].EquationA = mode;
}
ctx->Color._BlendEquationPerBuffer = GL_FALSE;
+   ctx->Color._AdvancedBlendMode = advanced_mode;
 
if (ctx->Driver.BlendEquationSeparate)
   ctx->Driver.BlendEquationSeparate(ctx, mode, mode);
@@ -446,6 +469,7 @@ void GLAPIENTRY
 _mesa_BlendEquationiARB(GLuint buf, GLenum mode)
 {
GET_CURRENT_CONTEXT(ctx);
+   enum gl_advanced_blend_mode advanced_mode = advanced_blend_mode(ctx, mode);
 
if (MESA_VERBOSE & VERBOSE_API)
   _mesa_debug(ctx, "glBlendEquationi(%u, %s)\n",
@@ -457,8 +481,7 @@ _mesa_BlendEquationiARB(GLuint buf, GLenum mode)
   return;
}
 
-   if (!legal_simple_blend_equation(ctx, mode) &&
-   !legal_advanced_blend_equation(ctx, mode)) {
+   if (!legal_simple_blend_equation(ctx, mode) && !advanced_mode) {
   _mesa_error(ctx, GL_INVALID_ENUM, "glBlendEquationi");
   return;
}
@@ -471,6 +494,9 @@ _mesa_BlendEquationiARB(GLuint buf, GLenum mode)
ctx->Color.Blend[buf].EquationRGB = mode;
ctx->Color.Blend[buf].EquationA = mode;
ctx->Color._BlendEquationPerBuffer = GL_TRUE;
+
+   if (buf == 0)
+  ctx->Color._AdvancedBlendMode = advanced_mode;
 }
 
 
@@ -537,6 +563,7 @@ _mesa_BlendEquationSeparate( GLenum modeRGB, GLenum modeA )
   

Mesa (master): mesa: Rename _mesa_BlendBarrierMESA to _mesa_BlendBarrier.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 1a1f4496c6aebc3ffcda4a6fc65290b3b5ad8195
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a1f4496c6aebc3ffcda4a6fc65290b3b5ad8195

Author: Kenneth Graunke 
Date:   Fri Aug 12 19:07:33 2016 -0700

mesa: Rename _mesa_BlendBarrierMESA to _mesa_BlendBarrier.

Note that _mesa_BlendBarrierMESA is not currently hooked up in the
glapi XML, so we can just rename it.  We'll hook it up for the
KHR_blend_equation_advanced extension shortly.

We may as well use the ES 3.2 core name with no suffixes.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Francisco Jerez 

---

 src/mesa/main/barrier.c | 2 +-
 src/mesa/main/barrier.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/main/barrier.c b/src/mesa/main/barrier.c
index 42a5e0f..2f5b451 100644
--- a/src/mesa/main/barrier.c
+++ b/src/mesa/main/barrier.c
@@ -110,7 +110,7 @@ _mesa_MemoryBarrierByRegion(GLbitfield barriers)
 }
 
 void GLAPIENTRY
-_mesa_BlendBarrierMESA(void)
+_mesa_BlendBarrier(void)
 {
GET_CURRENT_CONTEXT(ctx);
 
diff --git a/src/mesa/main/barrier.h b/src/mesa/main/barrier.h
index 21dce90..d54c02a 100644
--- a/src/mesa/main/barrier.h
+++ b/src/mesa/main/barrier.h
@@ -48,6 +48,6 @@ void GLAPIENTRY
 _mesa_MemoryBarrierByRegion(GLbitfield barriers);
 
 void GLAPIENTRY
-_mesa_BlendBarrierMESA(void);
+_mesa_BlendBarrier(void);
 
 #endif /* BARRIER_H */

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Mesa (master): glapi: add KHR_blend_equation_advanced dispatch

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: a8ae1bc7672ea7c40d4116959388e212a2702be6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8ae1bc7672ea7c40d4116959388e212a2702be6

Author: Ilia Mirkin 
Date:   Fri Apr  1 22:08:13 2016 -0400

glapi: add KHR_blend_equation_advanced dispatch

v2 (Ken): Fix enum values, drop _mesa_BlendBarrierKHR stub as Curro has
  already implemented it.
v3 (Ken): Rework for _mesa_BlendBarrierKHR -> _mesa_BlendBarrier rename.

Signed-off-by: Ilia Mirkin 
Signed-off-by: Kenneth Graunke 
Reviewed-by: Francisco Jerez 

---

 src/mapi/glapi/gen/gl_API.xml   | 24 
 src/mesa/main/tests/dispatch_sanity.cpp |  6 ++
 2 files changed, 30 insertions(+)

diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
index 79e1ba1..b5d010b 100644
--- a/src/mapi/glapi/gen/gl_API.xml
+++ b/src/mapi/glapi/gen/gl_API.xml
@@ -8294,6 +8294,30 @@
 
 http://www.w3.org/2001/XInclude"/>
 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
 
 
 
diff --git a/src/mesa/main/tests/dispatch_sanity.cpp 
b/src/mesa/main/tests/dispatch_sanity.cpp
index cfbf70d..a0bdd17 100644
--- a/src/mesa/main/tests/dispatch_sanity.cpp
+++ b/src/mesa/main/tests/dispatch_sanity.cpp
@@ -955,6 +955,9 @@ const struct function common_desktop_functions_possible[] = 
{
/* GL_EXT_window_rectangles */
{ "glWindowRectanglesEXT", 30, -1 },
 
+   /* GL_KHR_blend_equation_advanced */
+   { "glBlendBarrierKHR", 20, -1 },
+
{ NULL, 0, -1 }
 };
 
@@ -2322,6 +2325,9 @@ const struct function gles2_functions_possible[] = {
{ "glGetnUniformivKHR", 20, -1 },
{ "glGetnUniformuivKHR", 20, -1 },
 
+   /* GL_KHR_blend_equation_advanced */
+   { "glBlendBarrierKHR", 20, -1 },
+
{ NULL, 0, -1 }
 };
 

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Mesa (master): compiler: Add a new STATE_VAR_ADVANCED_BLENDING_MODE built-in uniform.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: e299661166a77c3cfc8a59c874bdb1e2179aa160
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e299661166a77c3cfc8a59c874bdb1e2179aa160

Author: Kenneth Graunke 
Date:   Tue Jun 28 09:02:42 2016 -0700

compiler: Add a new STATE_VAR_ADVANCED_BLENDING_MODE built-in uniform.

This will be used for emulating GL_KHR_advanced_blend_equation features
in shader code.  We'll pass in the blending mode that's in use, and use
that in (effectively) a switch statement in the shader.

v2: Use the new _AdvancedBlendMode field.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Francisco Jerez 

---

 src/mesa/program/prog_statevars.c | 10 ++
 src/mesa/program/prog_statevars.h |  5 +
 2 files changed, 15 insertions(+)

diff --git a/src/mesa/program/prog_statevars.c 
b/src/mesa/program/prog_statevars.c
index 8dddc0b..6e6007e 100644
--- a/src/mesa/program/prog_statevars.c
+++ b/src/mesa/program/prog_statevars.c
@@ -609,6 +609,10 @@ _mesa_fetch_state(struct gl_context *ctx, const 
gl_state_index state[],
 val[0].i = ctx->TessCtrlProgram.patch_vertices;
  return;
 
+  case STATE_ADVANCED_BLENDING_MODE:
+ val[0].i = ctx->Color.BlendEnabled ? ctx->Color._AdvancedBlendMode : 
0;
+ return;
+
   /* XXX: make sure new tokens added here are also handled in the 
* _mesa_program_state_flags() switch, below.
*/
@@ -719,6 +723,9 @@ _mesa_program_state_flags(const gl_state_index 
state[STATE_LENGTH])
   case STATE_FB_WPOS_Y_TRANSFORM:
  return _NEW_BUFFERS;
 
+  case STATE_ADVANCED_BLENDING_MODE:
+ return _NEW_COLOR;
+
   default:
  /* unknown state indexes are silently ignored and
  *  no flag set, since it is handled by the driver.
@@ -925,6 +932,9 @@ append_token(char *dst, gl_state_index k)
case STATE_FB_WPOS_Y_TRANSFORM:
   append(dst, "FbWposYTransform");
   break;
+   case STATE_ADVANCED_BLENDING_MODE:
+  append(dst, "AdvancedBlendingMode");
+  break;
default:
   /* probably STATE_INTERNAL_DRIVER+i (driver private state) */
   append(dst, "driverState");
diff --git a/src/mesa/program/prog_statevars.h 
b/src/mesa/program/prog_statevars.h
index e716d90..7fecb37 100644
--- a/src/mesa/program/prog_statevars.h
+++ b/src/mesa/program/prog_statevars.h
@@ -130,6 +130,11 @@ typedef enum gl_state_index_ {
STATE_FB_WPOS_Y_TRANSFORM,   /**< (1, 0, -1, height) if a FBO is bound, 
(-1, height, 1, 0) otherwise */
STATE_TCS_PATCH_VERTICES_IN, /**< gl_PatchVerticesIn for TCS (integer) */
STATE_TES_PATCH_VERTICES_IN, /**< gl_PatchVerticesIn for TES (integer) */
+   /**
+* A single enum gl_blend_support_qualifier value representing the
+* currently active advanced blending equation, or zero if disabled.
+*/
+   STATE_ADVANCED_BLENDING_MODE,
STATE_INTERNAL_DRIVER   /* first available state index for drivers 
(must be last) */
 } gl_state_index;
 

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Mesa (master): mesa: Restyle _mesa_check_blend_func_error().

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 75ae338d14ee3bf3ba438bb406831bf10b2c2f5d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=75ae338d14ee3bf3ba438bb406831bf10b2c2f5d

Author: Kenneth Graunke 
Date:   Sat Aug 20 12:18:16 2016 -0700

mesa: Restyle _mesa_check_blend_func_error().

I'm about to add more error conditions to this function, so I wanted to
move the current spec citation above the code that checks it.  Indenting
it required reformatting, so I tried to move it to our newer style.

While there, I also decided to drop some GL type usage, and drop the
unnecessary "_mesa_" prefix on a static function.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Francisco Jerez 

---

 src/mesa/main/context.c | 30 +++---
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index 574c0fb..4ff0979 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -1855,28 +1855,28 @@ _mesa_Flush(void)
 }
 
 
-/*
- * ARB_blend_func_extended - ERRORS section
- * "The error INVALID_OPERATION is generated by Begin or any procedure that
- *  implicitly calls Begin if any draw buffer has a blend function requiring 
the
- *  second color input (SRC1_COLOR, ONE_MINUS_SRC1_COLOR, SRC1_ALPHA or
- *  ONE_MINUS_SRC1_ALPHA), and a framebuffer is bound that has more than
- *  the value of MAX_DUAL_SOURCE_DRAW_BUFFERS-1 active color attachements."
- */
-static GLboolean
-_mesa_check_blend_func_error(struct gl_context *ctx)
+static bool
+check_blend_func_error(struct gl_context *ctx)
 {
-   GLuint i;
-   for (i = ctx->Const.MaxDualSourceDrawBuffers;
+   /* The ARB_blend_func_extended spec's ERRORS section says:
+*
+*"The error INVALID_OPERATION is generated by Begin or any procedure
+* that implicitly calls Begin if any draw buffer has a blend function
+* requiring the second color input (SRC1_COLOR, ONE_MINUS_SRC1_COLOR,
+* SRC1_ALPHA or ONE_MINUS_SRC1_ALPHA), and a framebuffer is bound that
+* has more than the value of MAX_DUAL_SOURCE_DRAW_BUFFERS-1 active
+* color attachements."
+*/
+   for (unsigned i = ctx->Const.MaxDualSourceDrawBuffers;
i < ctx->DrawBuffer->_NumColorDrawBuffers;
i++) {
   if (ctx->Color.Blend[i]._UsesDualSrc) {
 _mesa_error(ctx, GL_INVALID_OPERATION,
 "dual source blend on illegal attachment");
-return GL_FALSE;
+return false;
   }
}
-   return GL_TRUE;
+   return true;
 }
 
 
@@ -1951,7 +1951,7 @@ _mesa_valid_to_render(struct gl_context *ctx, const char 
*where)
   return GL_FALSE;
}
 
-   if (_mesa_check_blend_func_error(ctx) == GL_FALSE) {
+   if (!check_blend_func_error(ctx)) {
   return GL_FALSE;
}
 

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Mesa (master): glsl: Merge blend_support qualifiers when linking.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 80df3c030e061aa8b72f7032125532ce98524d0c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=80df3c030e061aa8b72f7032125532ce98524d0c

Author: Kenneth Graunke 
Date:   Tue Jun 28 10:02:06 2016 -0700

glsl: Merge blend_support qualifiers when linking.

Since each qualifier represents a blending mode the shader can be used
with, we take the union of all possible modes when linking.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Francisco Jerez 

---

 src/compiler/glsl/linker.cpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index 4b404ff..436b452 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -1880,6 +1880,7 @@ link_fs_inout_layout_qualifiers(struct gl_shader_program 
*prog,
linked_shader->info.uses_gl_fragcoord = false;
linked_shader->info.origin_upper_left = false;
linked_shader->info.pixel_center_integer = false;
+   linked_shader->info.BlendSupport = 0;
 
if (linked_shader->Stage != MESA_SHADER_FRAGMENT ||
(prog->Version < 150 && !prog->ARB_fragment_coord_conventions_enable))
@@ -1938,6 +1939,7 @@ link_fs_inout_layout_qualifiers(struct gl_shader_program 
*prog,
 
   linked_shader->info.EarlyFragmentTests |=
  shader->info.EarlyFragmentTests;
+  linked_shader->info.BlendSupport |= shader->info.BlendSupport;
}
 }
 

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Mesa (master): glsl: Add a lowering pass to handle advanced blending modes.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 8ab50f5dd14fb720316e65d9553e7cad5c50bf87
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ab50f5dd14fb720316e65d9553e7cad5c50bf87

Author: Kenneth Graunke 
Date:   Mon Jun 27 11:32:16 2016 -0700

glsl: Add a lowering pass to handle advanced blending modes.

Many GPUs cannot handle GL_KHR_blend_equation_advanced natively, and
need to emulate it in the pixel shader.  This lowering pass implements
all the necessary math for advanced blending.  It fetches the existing
framebuffer value using the MESA_shader_framebuffer_fetch built-in
variables, and the previous commit's state var uniform to select
which equation to use.

This is done at the GLSL IR level to make it easy for all drivers to
implement the GL_KHR_blend_equation_advanced extension and share code.

Drivers need to hook up MESA_shader_framebuffer_fetch functionality:
1. Hook up the fb_fetch_output variable
2. Implement BlendBarrier()

Then to get KHR_blend_equation_advanced, they simply need to:
3. Disable hardware blending based on ctx->Color._AdvancedBlendEnabled
4. Call this lowering pass.

Very little driver specific code should be required.

v2: Handle multiple output variables per render target (which may exist
due to ARB_enhanced_layouts), and array variables (even with one
render target, we might have out vec4 color[1]), and non-vec4
variables (it's easier than finding spec text to justify not
handling it).  Thanks to Francisco Jerez for the feedback.
v3: Lower main returns so that we have a single exit point where we
can add our blending epilogue (caught by Francisco Jerez).

Signed-off-by: Kenneth Graunke 
Reviewed-by: Francisco Jerez 

---

 src/compiler/Makefile.sources  |   1 +
 src/compiler/glsl/ir_optimization.h|   1 +
 .../glsl/lower_blend_equation_advanced.cpp | 562 +
 3 files changed, 564 insertions(+)

diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index cfb6359..edd683a 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -78,6 +78,7 @@ LIBGLSL_FILES = \
glsl/loop_analysis.h \
glsl/loop_controls.cpp \
glsl/loop_unroll.cpp \
+   glsl/lower_blend_equation_advanced.cpp \
glsl/lower_buffer_access.cpp \
glsl/lower_buffer_access.h \
glsl/lower_const_arrays_to_uniforms.cpp \
diff --git a/src/compiler/glsl/ir_optimization.h 
b/src/compiler/glsl/ir_optimization.h
index c29260a..3bd6928 100644
--- a/src/compiler/glsl/ir_optimization.h
+++ b/src/compiler/glsl/ir_optimization.h
@@ -151,6 +151,7 @@ void optimize_dead_builtin_variables(exec_list 
*instructions,
 bool lower_tess_level(gl_linked_shader *shader);
 
 bool lower_vertex_id(gl_linked_shader *shader);
+bool lower_blend_equation_advanced(gl_linked_shader *shader);
 
 bool lower_subroutine(exec_list *instructions, struct _mesa_glsl_parse_state 
*state);
 void propagate_invariance(exec_list *instructions);
diff --git a/src/compiler/glsl/lower_blend_equation_advanced.cpp 
b/src/compiler/glsl/lower_blend_equation_advanced.cpp
new file mode 100644
index 000..1c095dd
--- /dev/null
+++ b/src/compiler/glsl/lower_blend_equation_advanced.cpp
@@ -0,0 +1,562 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "ir.h"
+#include "ir_builder.h"
+#include "ir_optimization.h"
+#include "ir_hierarchical_visitor.h"
+#include "program/prog_instruction.h"
+#include "program/prog_statevars.h"
+#include "util/bitscan.h"
+
+using namespace ir_builder;
+
+#define imm1(x) new(mem_ctx) ir_constant((float) (x), 1)
+#define imm3(x) new(mem_ctx) ir_constant((float) (x), 3)
+
+static ir_rvalue *
+blend_multiply(ir_variable *src, ir_variable *dst)
+{
+   /* f(Cs,Cd) = Cs*Cd */
+   return 

Mesa (master): i965: Disable hardware blending if advanced blending is in use.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 40241d40d0a481f9f1cd112d2d48dadf1ec6ad0f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=40241d40d0a481f9f1cd112d2d48dadf1ec6ad0f

Author: Kenneth Graunke 
Date:   Tue Jun 28 08:24:11 2016 -0700

i965: Disable hardware blending if advanced blending is in use.

We'll do blending in the shader in this case, so just disable the
hardware blending.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Francisco Jerez 

---

 src/mesa/drivers/dri/i965/brw_cc.c   | 2 +-
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 ++--
 src/mesa/drivers/dri/i965/gen6_cc.c  | 3 ++-
 src/mesa/drivers/dri/i965/gen8_blend_state.c | 3 ++-
 4 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_cc.c 
b/src/mesa/drivers/dri/i965/brw_cc.c
index 2e8f0f7..5c58b44 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -159,7 +159,7 @@ static void upload_cc_unit(struct brw_context *brw)
if (ctx->Color.ColorLogicOpEnabled && ctx->Color.LogicOp != GL_COPY) {
   cc->cc2.logicop_enable = 1;
   cc->cc5.logicop_func = intel_translate_logic_op(ctx->Color.LogicOp);
-   } else if (ctx->Color.BlendEnabled) {
+   } else if (ctx->Color.BlendEnabled && !ctx->Color._AdvancedBlendMode) {
   GLenum eqRGB = ctx->Color.Blend[0].EquationRGB;
   GLenum eqA = ctx->Color.Blend[0].EquationA;
   GLenum srcRGB = ctx->Color.Blend[0].SrcRGB;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index e07e8da..023b1ff 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -926,8 +926,8 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
 
if (brw->gen < 6) {
   /* _NEW_COLOR */
-  if (!ctx->Color.ColorLogicOpEnabled &&
- (ctx->Color.BlendEnabled & (1 << unit)))
+  if (!ctx->Color.ColorLogicOpEnabled && !ctx->Color._AdvancedBlendMode &&
+  (ctx->Color.BlendEnabled & (1 << unit)))
 surf[0] |= BRW_SURFACE_BLEND_ENABLED;
 
   if (!ctx->Color.ColorMask[unit][0])
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c 
b/src/mesa/drivers/dri/i965/gen6_cc.c
index 69c8ebd..0c38930 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -104,7 +104,8 @@ gen6_upload_blend_state(struct brw_context *brw)
blend[b].blend1.logic_op_func =
   intel_translate_logic_op(ctx->Color.LogicOp);
 }
-  } else if (ctx->Color.BlendEnabled & (1 << b) && !integer) {
+  } else if (ctx->Color.BlendEnabled & (1 << b) && !integer &&
+ !ctx->Color._AdvancedBlendMode) {
 GLenum eqRGB = ctx->Color.Blend[b].EquationRGB;
 GLenum eqA = ctx->Color.Blend[b].EquationA;
 GLenum srcRGB = ctx->Color.Blend[b].SrcRGB;
diff --git a/src/mesa/drivers/dri/i965/gen8_blend_state.c 
b/src/mesa/drivers/dri/i965/gen8_blend_state.c
index 99b5e34..4935d82 100644
--- a/src/mesa/drivers/dri/i965/gen8_blend_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_blend_state.c
@@ -107,7 +107,8 @@ gen8_upload_blend_state(struct brw_context *brw)
 GEN8_BLEND_LOGIC_OP_ENABLE |
 SET_FIELD(intel_translate_logic_op(ctx->Color.LogicOp),
   GEN8_BLEND_LOGIC_OP_FUNCTION);
-  } else if (ctx->Color.BlendEnabled & (1 << i) && !integer) {
+  } else if (ctx->Color.BlendEnabled & (1 << i) && !integer &&
+ !ctx->Color._AdvancedBlendMode) {
  GLenum eqRGB = ctx->Color.Blend[i].EquationRGB;
  GLenum eqA = ctx->Color.Blend[i].EquationA;
  GLenum srcRGB = ctx->Color.Blend[i].SrcRGB;

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Mesa (master): i965: Safely iterate the predecessors of the end block.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: c2fd6b0f5d1c964fa63e72d6938721cba9597629
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2fd6b0f5d1c964fa63e72d6938721cba9597629

Author: Kenneth Graunke 
Date:   Wed Aug 24 21:33:16 2016 -0700

i965: Safely iterate the predecessors of the end block.

We want to insert code in each of the predecessors of the end block.
This code includes a nir_if, which would split the block, altering
the set.  To avoid that, I emitted a dead constant at the end of each
block before splitting it, so that the set of predecessors remained
unchanged.  This was admittedly ugly.

Connor suggested instead saving a copy of the set, so we can iterate
it safely.  This is also a little ugly, but a much better plan.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Connor Abbott 

---

 .../drivers/dri/i965/brw_nir_tcs_workarounds.c | 23 +-
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_nir_tcs_workarounds.c 
b/src/mesa/drivers/dri/i965/brw_nir_tcs_workarounds.c
index 6524b7d..3f94f63 100644
--- a/src/mesa/drivers/dri/i965/brw_nir_tcs_workarounds.c
+++ b/src/mesa/drivers/dri/i965/brw_nir_tcs_workarounds.c
@@ -102,14 +102,7 @@ store_output(nir_builder *b, nir_ssa_def *value, int 
offset, unsigned comps)
 static void
 emit_quads_workaround(nir_builder *b, nir_block *block)
 {
-   /* We're going to insert a new if-statement in a predecessor of the end
-* block.  This would normally create a new block (after the if) which
-* would then become the predecessor of the end block, causing our set
-* walking to get screwed up.  To avoid this, just emit a constant at
-* the end of our current block, and insert the if before that.
-*/
b->cursor = nir_after_block_before_jump(block);
-   b->cursor = nir_before_instr(nir_imm_int(b, 0)->parent_instr);
 
nir_ssa_def *inner = load_output(b, 2, 0);
nir_ssa_def *outer = load_output(b, 4, 1);
@@ -139,10 +132,22 @@ brw_nir_apply_tcs_quads_workaround(nir_shader *nir)
nir_builder b;
nir_builder_init(, impl);
 
+   /* emit_quads_workaround() inserts an if statement into each block,
+* which splits it in two.  This changes the set of predecessors of
+* the end block.  We want to process the original set, so to be safe,
+* save it off to an array first.
+*/
+   const unsigned num_end_preds = impl->end_block->predecessors->entries;
+   nir_block *end_preds[num_end_preds];
+   unsigned i = 0;
struct set_entry *entry;
+
set_foreach(impl->end_block->predecessors, entry) {
-  nir_block *pred = (nir_block *) entry->key;
-  emit_quads_workaround(, pred);
+  end_preds[i++] = (nir_block *) entry->key;
+   }
+
+   for (i = 0; i < num_end_preds; i++) {
+  emit_quads_workaround(, end_preds[i]);
}
 
nir_metadata_preserve(impl, 0);

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Mesa (master): mesa: add KHR_blend_equation_advanced enable and extension string

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 3b0406457a2de2d412fef2ff5cfa121f521cdf29
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b0406457a2de2d412fef2ff5cfa121f521cdf29

Author: Ilia Mirkin 
Date:   Fri Apr  1 22:13:22 2016 -0400

mesa: add KHR_blend_equation_advanced enable and extension string

Signed-off-by: Ilia Mirkin 
Reviewed-by: Kenneth Graunke 
Reviewed-by: Francisco Jerez 

---

 src/mesa/main/extensions_table.h | 1 +
 src/mesa/main/mtypes.h   | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index ee4f1af..e8c825b 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -282,6 +282,7 @@ EXT(INGR_blend_func_separate, 
EXT_blend_func_separate
 
 EXT(INTEL_performance_query , INTEL_performance_query  
  , GLL, GLC,  x , ES2, 2013)
 
+EXT(KHR_blend_equation_advanced , KHR_blend_equation_advanced  
  , GLL, GLC,  x , ES2, 2014)
 EXT(KHR_context_flush_control   , dummy_true   
  , GLL, GLC,  x , ES2, 2014)
 EXT(KHR_debug   , dummy_true   
  , GLL, GLC,  11, ES2, 2012)
 EXT(KHR_robust_buffer_access_behavior   , 
ARB_robust_buffer_access_behavior  , GLL, GLC,  x , ES2, 2014)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index d0ceda9..ec608e2 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -3942,6 +3942,7 @@ struct gl_extensions
GLboolean ATI_separate_stencil;
GLboolean GREMEDY_string_marker;
GLboolean INTEL_performance_query;
+   GLboolean KHR_blend_equation_advanced;
GLboolean KHR_robustness;
GLboolean KHR_texture_compression_astc_hdr;
GLboolean KHR_texture_compression_astc_ldr;

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Mesa (master): nir: Change nir_shader_get_entrypoint to return an impl.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 93bfa1d7a2e70a72a01c48a04c208845c22f9376
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=93bfa1d7a2e70a72a01c48a04c208845c22f9376

Author: Kenneth Graunke 
Date:   Wed Aug 24 19:09:57 2016 -0700

nir: Change nir_shader_get_entrypoint to return an impl.

Jason suggested adding an assert(function->impl) here.  All callers
of this function actually want ->impl, so I decided just to change
the API.

We also change the nir_lower_io_to_temporaries API here.  All but one
caller passed nir_shader_get_entrypoint(), and with the previous commit,
it now uses a nir_function_impl internally.  Folding this change in
avoids the need to change it and change it back.

v2: Fix one call I missed in ir3_compiler (caught by Eric).

Signed-off-by: Kenneth Graunke 
Reviewed-by: Jason Ekstrand 
Reviewed-by: Connor Abbott 

---

 src/compiler/nir/nir.h   | 8 +---
 src/compiler/nir/nir_lower_bitmap.c  | 7 +--
 src/compiler/nir/nir_lower_io_to_temporaries.c   | 4 ++--
 src/compiler/nir/nir_lower_passthrough_edgeflags.c   | 4 +---
 src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c | 2 +-
 src/intel/vulkan/anv_pipeline.c  | 5 +++--
 src/mesa/drivers/dri/i965/blorp.c| 2 +-
 7 files changed, 14 insertions(+), 18 deletions(-)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 1407b2d..d0dfb0d 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1902,7 +1902,7 @@ typedef struct nir_shader {
gl_shader_stage stage;
 } nir_shader;
 
-static inline nir_function *
+static inline nir_function_impl *
 nir_shader_get_entrypoint(nir_shader *shader)
 {
assert(exec_list_length(>functions) == 1);
@@ -1910,7 +1910,8 @@ nir_shader_get_entrypoint(nir_shader *shader)
nir_function *func = exec_node_data(nir_function, func_node, node);
assert(func->return_type == glsl_void_type());
assert(func->num_params == 0);
-   return func;
+   assert(func->impl);
+   return func->impl;
 }
 
 #define nir_foreach_function(func, shader) \
@@ -2378,7 +2379,8 @@ bool nir_lower_indirect_derefs(nir_shader *shader, 
nir_variable_mode modes);
 
 bool nir_lower_locals_to_regs(nir_shader *shader);
 
-void nir_lower_io_to_temporaries(nir_shader *shader, nir_function *entrypoint,
+void nir_lower_io_to_temporaries(nir_shader *shader,
+ nir_function_impl *entrypoint,
  bool outputs, bool inputs);
 
 void nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint);
diff --git a/src/compiler/nir/nir_lower_bitmap.c 
b/src/compiler/nir/nir_lower_bitmap.c
index e182579..bd5c30f 100644
--- a/src/compiler/nir/nir_lower_bitmap.c
+++ b/src/compiler/nir/nir_lower_bitmap.c
@@ -128,12 +128,7 @@ void
 nir_lower_bitmap(nir_shader *shader,
  const nir_lower_bitmap_options *options)
 {
-   nir_function *function;
-
assert(shader->stage == MESA_SHADER_FRAGMENT);
 
-   function = nir_shader_get_entrypoint(shader);
-
-   if (function->impl)
-  lower_bitmap_impl(function->impl, options);
+   lower_bitmap_impl(nir_shader_get_entrypoint(shader), options);
 }
diff --git a/src/compiler/nir/nir_lower_io_to_temporaries.c 
b/src/compiler/nir/nir_lower_io_to_temporaries.c
index 8cbf683..4f615d3 100644
--- a/src/compiler/nir/nir_lower_io_to_temporaries.c
+++ b/src/compiler/nir/nir_lower_io_to_temporaries.c
@@ -148,7 +148,7 @@ create_shadow_temp(struct lower_io_state *state, 
nir_variable *var)
 }
 
 void
-nir_lower_io_to_temporaries(nir_shader *shader, nir_function *entrypoint,
+nir_lower_io_to_temporaries(nir_shader *shader, nir_function_impl *entrypoint,
 bool outputs, bool inputs)
 {
struct lower_io_state state;
@@ -157,7 +157,7 @@ nir_lower_io_to_temporaries(nir_shader *shader, 
nir_function *entrypoint,
   return;
 
state.shader = shader;
-   state.entrypoint = entrypoint->impl;
+   state.entrypoint = entrypoint;
 
if (inputs)
   exec_list_move_nodes_to(>inputs, _inputs);
diff --git a/src/compiler/nir/nir_lower_passthrough_edgeflags.c 
b/src/compiler/nir/nir_lower_passthrough_edgeflags.c
index c570c8e..f34078c 100644
--- a/src/compiler/nir/nir_lower_passthrough_edgeflags.c
+++ b/src/compiler/nir/nir_lower_passthrough_edgeflags.c
@@ -52,7 +52,5 @@ lower_impl(nir_function_impl *impl)
 
 void nir_lower_passthrough_edgeflags(nir_shader *shader)
 {
-   nir_function *function = nir_shader_get_entrypoint(shader);
-   if (function->impl)
-  lower_impl(function->impl);
+   lower_impl(nir_shader_get_entrypoint(shader));
 }
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c 
b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index 22f5525..b1b9d6b 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ 

Mesa (master): mesa: Add draw time validation for advanced blending modes.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: acf57fcf7ff7e60c3550da7b6dda7ad8b69195bd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=acf57fcf7ff7e60c3550da7b6dda7ad8b69195bd

Author: Kenneth Graunke 
Date:   Sat Aug 20 12:51:03 2016 -0700

mesa: Add draw time validation for advanced blending modes.

v2: Add null checks (requested by Curro).

Signed-off-by: Kenneth Graunke 
Reviewed-by: Francisco Jerez 

---

 src/mesa/main/context.c | 52 +
 1 file changed, 52 insertions(+)

diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index 4ff0979..8f9bbf1 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -1876,6 +1876,58 @@ check_blend_func_error(struct gl_context *ctx)
 return false;
   }
}
+
+   if (ctx->Color.BlendEnabled && ctx->Color._AdvancedBlendMode) {
+  /* The KHR_blend_equation_advanced spec says:
+   *
+   *"If any non-NONE draw buffer uses a blend equation found in table
+   * X.1 or X.2, the error INVALID_OPERATION is generated by Begin or
+   * any operation that implicitly calls Begin (such as DrawElements)
+   * if:
+   *
+   *   * the draw buffer for color output zero selects multiple color
+   * buffers (e.g., FRONT_AND_BACK in the default framebuffer); or
+   *
+   *   * the draw buffer for any other color output is not NONE."
+   */
+  if (ctx->DrawBuffer->ColorDrawBuffer[0] == GL_FRONT_AND_BACK) {
+ _mesa_error(ctx, GL_INVALID_OPERATION,
+ "advanced blending is active and draw buffer for color "
+ "output zero selects multiple color buffers");
+ return false;
+  }
+
+  for (unsigned i = 1; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
+ if (ctx->DrawBuffer->ColorDrawBuffer[i] != GL_NONE) {
+_mesa_error(ctx, GL_INVALID_OPERATION,
+"advanced blending is active with multiple color "
+"draw buffers");
+return false;
+ }
+  }
+
+  /* The KHR_blend_equation_advanced spec says:
+   *
+   *"Advanced blending equations require the use of a fragment shader
+   * with a matching "blend_support" layout qualifier.  If the current
+   * blend equation is found in table X.1 or X.2, and the active
+   * fragment shader does not include the layout qualifier matching
+   * the blend equation or "blend_support_all_equations", the error
+   * INVALID_OPERATION is generated [...]"
+   */
+  const struct gl_shader_program *sh_prog =
+ ctx->_Shader->_CurrentFragmentProgram;
+  const GLbitfield blend_support = !sh_prog ? 0 :
+ sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT]->info.BlendSupport;
+
+  if ((blend_support & ctx->Color._AdvancedBlendMode) == 0) {
+ _mesa_error(ctx, GL_INVALID_OPERATION,
+ "fragment shader does not allow advanced blending mode "
+ "(%s)",
+  _mesa_enum_to_string(ctx->Color.Blend[0].EquationRGB));
+  }
+   }
+
return true;
 }
 

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Mesa (master): i965: Enable GL_KHR_blend_equation_advanced on G45 and later.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: c2b10cabed6468b998a9c4d0ada7953d93311029
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2b10cabed6468b998a9c4d0ada7953d93311029

Author: Kenneth Graunke 
Date:   Mon Jun 27 23:02:24 2016 -0700

i965: Enable GL_KHR_blend_equation_advanced on G45 and later.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Francisco Jerez 

---

 src/mesa/drivers/dri/i965/brw_link.cpp   | 2 ++
 src/mesa/drivers/dri/i965/intel_extensions.c | 4 +++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index 1ad2369..4800be0 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -101,6 +101,8 @@ process_glsl_ir(gl_shader_stage stage,
 
ralloc_adopt(mem_ctx, shader->ir);
 
+   lower_blend_equation_advanced(shader);
+
/* lower_packing_builtins() inserts arithmetic instructions, so it
 * must precede lower_instructions().
 */
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 5092da5..48e8299 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -281,8 +281,10 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.EXT_shader_integer_mix = ctx->Const.GLSLVersion >= 130;
ctx->Extensions.MESA_shader_integer_functions = ctx->Const.GLSLVersion >= 
130;
 
-   if (brw->is_g4x || brw->gen >= 5)
+   if (brw->is_g4x || brw->gen >= 5) {
   ctx->Extensions.MESA_shader_framebuffer_fetch_non_coherent = true;
+  ctx->Extensions.KHR_blend_equation_advanced = true;
+   }
 
if (brw->gen >= 5) {
   ctx->Extensions.ARB_texture_query_levels = ctx->Const.GLSLVersion >= 130;

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Mesa (master): mesa: Allow advanced blending enums in glBlendEquation[i].

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 74837e3e913f18954ae596f305f42bf71cf6ba78
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=74837e3e913f18954ae596f305f42bf71cf6ba78

Author: Kenneth Graunke 
Date:   Tue Jun 28 09:18:19 2016 -0700

mesa: Allow advanced blending enums in glBlendEquation[i].

Don't allow them in glBlendEquationSeparate[i], though, as required
by the spec.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Francisco Jerez 

---

 src/mesa/main/blend.c | 64 +++
 1 file changed, 54 insertions(+), 10 deletions(-)

diff --git a/src/mesa/main/blend.c b/src/mesa/main/blend.c
index 2ae22e9..fe83e59 100644
--- a/src/mesa/main/blend.c
+++ b/src/mesa/main/blend.c
@@ -336,11 +336,11 @@ _mesa_BlendFuncSeparateiARB(GLuint buf, GLenum 
sfactorRGB, GLenum dfactorRGB,
 
 
 /**
- * Check if given blend equation is legal.
- * \return GL_TRUE if legal, GL_FALSE otherwise.
+ * Return true if \p mode is a legal blending equation, excluding
+ * GL_KHR_blend_equation_advanced modes.
  */
-static GLboolean
-legal_blend_equation(const struct gl_context *ctx, GLenum mode)
+static bool
+legal_simple_blend_equation(const struct gl_context *ctx, GLenum mode)
 {
switch (mode) {
case GL_FUNC_ADD:
@@ -356,6 +356,36 @@ legal_blend_equation(const struct gl_context *ctx, GLenum 
mode)
 }
 
 
+/**
+ * Return true if \p mode is one of the advanced blending equations
+ * defined by GL_KHR_blend_equation_advanced.
+ */
+static bool
+legal_advanced_blend_equation(const struct gl_context *ctx, GLenum mode)
+{
+   switch (mode) {
+   case GL_MULTIPLY_KHR:
+   case GL_SCREEN_KHR:
+   case GL_OVERLAY_KHR:
+   case GL_DARKEN_KHR:
+   case GL_LIGHTEN_KHR:
+   case GL_COLORDODGE_KHR:
+   case GL_COLORBURN_KHR:
+   case GL_HARDLIGHT_KHR:
+   case GL_SOFTLIGHT_KHR:
+   case GL_DIFFERENCE_KHR:
+   case GL_EXCLUSION_KHR:
+   case GL_HSL_HUE_KHR:
+   case GL_HSL_SATURATION_KHR:
+   case GL_HSL_COLOR_KHR:
+   case GL_HSL_LUMINOSITY_KHR:
+  return _mesa_has_KHR_blend_equation_advanced(ctx);
+   default:
+  return false;
+   }
+}
+
+
 /* This is really an extension function! */
 void GLAPIENTRY
 _mesa_BlendEquation( GLenum mode )
@@ -390,7 +420,8 @@ _mesa_BlendEquation( GLenum mode )
if (!changed)
   return;
 
-   if (!legal_blend_equation(ctx, mode)) {
+   if (!legal_simple_blend_equation(ctx, mode) &&
+   !legal_advanced_blend_equation(ctx, mode)) {
   _mesa_error(ctx, GL_INVALID_ENUM, "glBlendEquation");
   return;
}
@@ -426,7 +457,8 @@ _mesa_BlendEquationiARB(GLuint buf, GLenum mode)
   return;
}
 
-   if (!legal_blend_equation(ctx, mode)) {
+   if (!legal_simple_blend_equation(ctx, mode) &&
+   !legal_advanced_blend_equation(ctx, mode)) {
   _mesa_error(ctx, GL_INVALID_ENUM, "glBlendEquationi");
   return;
}
@@ -482,12 +514,18 @@ _mesa_BlendEquationSeparate( GLenum modeRGB, GLenum modeA 
)
   return;
}
 
-   if (!legal_blend_equation(ctx, modeRGB)) {
+   /* Only allow simple blending equations.
+* The GL_KHR_blend_equation_advanced spec says:
+*
+*"NOTE: These enums are not accepted by the  or 
+* parameters of BlendEquationSeparate or BlendEquationSeparatei."
+*/
+   if (!legal_simple_blend_equation(ctx, modeRGB)) {
   _mesa_error(ctx, GL_INVALID_ENUM, "glBlendEquationSeparateEXT(modeRGB)");
   return;
}
 
-   if (!legal_blend_equation(ctx, modeA)) {
+   if (!legal_simple_blend_equation(ctx, modeA)) {
   _mesa_error(ctx, GL_INVALID_ENUM, "glBlendEquationSeparateEXT(modeA)");
   return;
}
@@ -524,12 +562,18 @@ _mesa_BlendEquationSeparateiARB(GLuint buf, GLenum 
modeRGB, GLenum modeA)
   return;
}
 
-   if (!legal_blend_equation(ctx, modeRGB)) {
+   /* Only allow simple blending equations.
+* The GL_KHR_blend_equation_advanced spec says:
+*
+*"NOTE: These enums are not accepted by the  or 
+* parameters of BlendEquationSeparate or BlendEquationSeparatei."
+*/
+   if (!legal_simple_blend_equation(ctx, modeRGB)) {
   _mesa_error(ctx, GL_INVALID_ENUM, "glBlendEquationSeparatei(modeRGB)");
   return;
}
 
-   if (!legal_blend_equation(ctx, modeA)) {
+   if (!legal_simple_blend_equation(ctx, modeA)) {
   _mesa_error(ctx, GL_INVALID_ENUM, "glBlendEquationSeparatei(modeA)");
   return;
}

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