Mesa (master): mesa: fix glGetFramebufferAttachmentParameteriv w/ on-demand FRONT_BACK alloc

[Marek Olšák]

Module: Mesa
Branch: master
Commit: d58a3906cba57b12035f6ec7a3da80edc6929d6f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d58a3906cba57b12035f6ec7a3da80edc6929d6f

Author: Marek Olšák 
Date:   Thu Sep  8 21:02:29 2016 +0200

mesa: fix glGetFramebufferAttachmentParameteriv w/ on-demand FRONT_BACK alloc

This fixes 66 CTS tests on st/mesa.

Cc: 12.0 
Reviewed-by: Nicolai Hähnle 

---

 src/mesa/main/fbobject.c | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index 2c01526..09da6b7 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -303,9 +303,21 @@ _mesa_get_fb0_attachment(struct gl_context *ctx, struct 
gl_framebuffer *fb,
 
switch (attachment) {
case GL_FRONT_LEFT:
-  return >Attachment[BUFFER_FRONT_LEFT];
+  /* Front buffers can be allocated on the first use, but
+   * glGetFramebufferAttachmentParameteriv must work even if that
+   * allocation hasn't happened yet. In such case, use the back buffer,
+   * which should be the same.
+   */
+  if (fb->Attachment[BUFFER_FRONT_LEFT].Type == GL_NONE)
+ return >Attachment[BUFFER_BACK_LEFT];
+  else
+ return >Attachment[BUFFER_FRONT_LEFT];
case GL_FRONT_RIGHT:
-  return >Attachment[BUFFER_FRONT_RIGHT];
+  /* Same as above. */
+  if (fb->Attachment[BUFFER_FRONT_RIGHT].Type == GL_NONE)
+ return >Attachment[BUFFER_BACK_RIGHT];
+  else
+ return >Attachment[BUFFER_FRONT_RIGHT];
case GL_BACK_LEFT:
   return >Attachment[BUFFER_BACK_LEFT];
case GL_BACK_RIGHT:

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Mesa (master): glsl: remove interpolateAt* instructions for demoted inputs

[Marek Olšák]

Module: Mesa
Branch: master
Commit: ae0a4a1299f649ff550a0dfd59d60fc8b91df54f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae0a4a1299f649ff550a0dfd59d60fc8b91df54f

Author: Marek Olšák 
Date:   Fri Sep  9 02:04:00 2016 +0200

glsl: remove interpolateAt* instructions for demoted inputs

This fixes 8 fs-interpolateat* piglit crashes on radeonsi, because it can't
handle non-input operands in interpolateAt*.

Reviewed-by: Nicolai Hähnle 

---

 src/compiler/glsl/link_varyings.cpp |  5 +
 src/compiler/glsl/opt_algebraic.cpp | 10 ++
 2 files changed, 15 insertions(+)

diff --git a/src/compiler/glsl/link_varyings.cpp 
b/src/compiler/glsl/link_varyings.cpp
index 8c436c2..e622b3e 100644
--- a/src/compiler/glsl/link_varyings.cpp
+++ b/src/compiler/glsl/link_varyings.cpp
@@ -593,6 +593,11 @@ remove_unused_shader_inputs_and_outputs(bool 
is_separate_shader_object,
*/
   if (var->data.is_unmatched_generic_inout && !var->data.is_xfb_only) {
  assert(var->data.mode != ir_var_temporary);
+
+ /* Assign zeros to demoted inputs to allow more optimizations. */
+ if (var->data.mode == ir_var_shader_in && !var->constant_value)
+var->constant_value = ir_constant::zero(var, var->type);
+
  var->data.mode = ir_var_auto;
   }
}
diff --git a/src/compiler/glsl/opt_algebraic.cpp 
b/src/compiler/glsl/opt_algebraic.cpp
index f5858c8..2829a78 100644
--- a/src/compiler/glsl/opt_algebraic.cpp
+++ b/src/compiler/glsl/opt_algebraic.cpp
@@ -961,6 +961,16 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir)
 return ir->operands[2];
   break;
 
+   /* Remove interpolateAt* instructions for demoted inputs. They are
+* assigned a constant expression to facilitate this.
+*/
+   case ir_unop_interpolate_at_centroid:
+   case ir_binop_interpolate_at_offset:
+   case ir_binop_interpolate_at_sample:
+  if (op_const[0])
+ return ir->operands[0];
+  break;
+
default:
   break;
}

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Mesa (master): clover: fix getting scalar args api size

[Serge Martin]

Module: Mesa
Branch: master
Commit: 1c8d4c694bfb95ab90f152da710a8a9459a20228
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c8d4c694bfb95ab90f152da710a8a9459a20228

Author: Serge Martin 
Date:   Tue Aug 30 10:10:01 2016 +0200

clover: fix getting scalar args api size

This fix getting the size of a struct arg. vec3 types still work ok.
Only buit-in args need to have power of two alignment, getTypeAllocSize
reports the correct size in all cases.

Acked-by: Francisco Jerez 

---

 src/gallium/state_trackers/clover/llvm/codegen/common.cpp | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/gallium/state_trackers/clover/llvm/codegen/common.cpp 
b/src/gallium/state_trackers/clover/llvm/codegen/common.cpp
index 2d52fdc..834b06a 100644
--- a/src/gallium/state_trackers/clover/llvm/codegen/common.cpp
+++ b/src/gallium/state_trackers/clover/llvm/codegen/common.cpp
@@ -81,11 +81,10 @@ namespace {
 
  // OpenCL 1.2 specification, Ch. 6.1.5: "A built-in data
  // type that is not a power of two bytes in size must be
- // aligned to the next larger power of two".  We need this
- // alignment for three element vectors, which have
- // non-power-of-2 store size.
+ // aligned to the next larger power of two.
+ // This rule applies to built-in types only, not structs or unions."
  const unsigned arg_store_size = dl.getTypeStoreSize(arg_type);
- const unsigned arg_api_size = util_next_power_of_two(arg_store_size);
+ const unsigned arg_api_size = dl.getTypeAllocSize(arg_type);
 
  const auto target_type = !arg_type->isIntegerTy() ? arg_type :
 dl.getSmallestLegalIntType(mod.getContext(), arg_store_size * 8);

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Mesa (master): mesa: Expose GL_CONTEXT_FLAGS in ES 3.2.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 6b0ba02cae1526d6e6671a9ff620fd3bd7d4d032
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b0ba02cae1526d6e6671a9ff620fd3bd7d4d032

Author: Kenneth Graunke 
Date:   Thu Sep 15 02:10:22 2016 -0700

mesa: Expose GL_CONTEXT_FLAGS in ES 3.2.

Fixes four ES32-CTS.context_flags.* tests.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Ilia Mirkin 

---

 src/mesa/main/get_hash_params.py | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/mesa/main/get_hash_params.py b/src/mesa/main/get_hash_params.py
index 1f63dc3..b2aef7b 100644
--- a/src/mesa/main/get_hash_params.py
+++ b/src/mesa/main/get_hash_params.py
@@ -620,6 +620,11 @@ descriptor=[
   [ "MULTISAMPLE_LINE_WIDTH_GRANULARITY_ARB", 
"CONTEXT_FLOAT(Const.LineWidthGranularity), extra_ES32" ],
 ]},
 
+{ "apis": ["GL", "GL_CORE", "GLES32"], "params": [
+# GL 3.0 or ES 3.2
+  [ "CONTEXT_FLAGS", "CONTEXT_INT(Const.ContextFlags), extra_version_30" ],
+]},
+
 # Remaining enums are only in OpenGL
 { "apis": ["GL", "GL_CORE"], "params": [
   [ "ACCUM_RED_BITS", "BUFFER_INT(Visual.accumRedBits), NO_EXTRA" ],
@@ -888,9 +893,6 @@ descriptor=[
 # GL_ARB_color_buffer_float
   [ "RGBA_FLOAT_MODE_ARB", "BUFFER_FIELD(Visual.floatMode, TYPE_BOOLEAN), 
extra_core_ARB_color_buffer_float_and_new_buffers" ],
 
-# GL 3.0
-  [ "CONTEXT_FLAGS", "CONTEXT_INT(Const.ContextFlags), extra_version_30" ],
-
 # GL3.0 / GL_EXT_framebuffer_sRGB
   [ "FRAMEBUFFER_SRGB_EXT", "CONTEXT_BOOL(Color.sRGBEnabled), 
extra_EXT_framebuffer_sRGB" ],
   [ "FRAMEBUFFER_SRGB_CAPABLE_EXT", "BUFFER_INT(Visual.sRGBCapable), 
extra_EXT_framebuffer_sRGB_and_new_buffers" ],

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Mesa (master): radeonsi/compute: Use the HSA abi for non-TGSI compute shaders v3

[Tom Stellard]

Module: Mesa
Branch: master
Commit: 91ec6e5664979382f3cb18ba91edc4af99f93471
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=91ec6e5664979382f3cb18ba91edc4af99f93471

Author: Tom Stellard 
Date:   Wed Jul 20 14:32:59 2016 +

radeonsi/compute: Use the HSA abi for non-TGSI compute shaders v3

This patch switches non-TGSI compute shaders over to using the HSA
ABI described here:

https://github.com/RadeonOpenCompute/ROCm-Docs/blob/master/AMDGPU-ABI.md

The HSA ABI provides a much cleaner interface for compute shaders and allows
us to share more code in the compiler with the HSA stack.

The main changes in this patch are:
  - We now pass the scratch buffer resource into the shader via user sgprs
rather than using relocations.
  - Grid/Block sizes are now passed to the shader via the dispatch packet
rather than at the beginning of the kernel arguments.

Typically for HSA, the CP firmware will create the dispatch packet and set
up the user sgprs automatically.  However, in Mesa we let the driver do
this work.  The main reason for this is that I haven't researched how to
get the CP to do all these things, and I'm not sure if it is supported
for all GPUs.

v2:
  - Add comments explaining why we are setting certain bits of the scratch
resource descriptor.

v3:
  - Use amdgcn-mesa-mesa3d triple instead of amdgcn--mesa3d.

Reviewed-by: Nicolai Hähnle 

---

 src/amd/common/amd_kernel_code_t.h| 534 ++
 src/gallium/drivers/radeon/r600_pipe_common.c |   6 +-
 src/gallium/drivers/radeonsi/si_compute.c | 239 +++-
 3 files changed, 761 insertions(+), 18 deletions(-)

diff --git a/src/amd/common/amd_kernel_code_t.h 
b/src/amd/common/amd_kernel_code_t.h
new file mode 100644
index 000..d0d7809
--- /dev/null
+++ b/src/amd/common/amd_kernel_code_t.h
@@ -0,0 +1,534 @@
+/*
+ * Copyright 2015,2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef AMDKERNELCODET_H
+#define AMDKERNELCODET_H
+
+//---//
+// AMD Kernel Code, and its dependencies //
+//---//
+
+// Sets val bits for specified mask in specified dst packed instance.
+#define AMD_HSA_BITS_SET(dst, mask, val)   
\
+  dst &= (~(1 << mask ## _SHIFT) & ~mask); 
\
+  dst |= (((val) << mask ## _SHIFT) & mask)
+
+// Gets bits for specified mask from specified src packed instance.
+#define AMD_HSA_BITS_GET(src, mask)
\
+  ((src & mask) >> mask ## _SHIFT) 
\
+
+/* Every amd_*_code_t has the following properties, which are composed of
+ * a number of bit fields. Every bit field has a mask (AMD_CODE_PROPERTY_*),
+ * bit width (AMD_CODE_PROPERTY_*_WIDTH, and bit shift amount
+ * (AMD_CODE_PROPERTY_*_SHIFT) for convenient access. Unused bits must be 0.
+ *
+ * (Note that bit fields cannot be used as their layout is
+ * implementation defined in the C standard and so cannot be used to
+ * specify an ABI)
+ */
+enum amd_code_property_mask_t {
+
+  /* Enable the setup of the SGPR user data registers
+   * (AMD_CODE_PROPERTY_ENABLE_SGPR_*), see documentation of amd_kernel_code_t
+   * for initial register state.
+   *
+   * The total number of SGPRuser data registers requested must not
+   * exceed 16. Any requests beyond 16 will be ignored.
+   *
+   * Used to set COMPUTE_PGM_RSRC2.USER_SGPR (set to total count of
+   * SGPR user data registers enabled up to 16).
+   */
+
+  AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT = 0,
+  AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_WIDTH = 1,
+  

Mesa (master): radeonsi/compute: Add some more debug printfs

[Tom Stellard]

Module: Mesa
Branch: master
Commit: a2b8346fa6c96af6b3d83b9f9ebb1f500e0da5f1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a2b8346fa6c96af6b3d83b9f9ebb1f500e0da5f1

Author: Tom Stellard 
Date:   Tue Jul 19 15:25:06 2016 +

radeonsi/compute: Add some more debug printfs

---

 src/gallium/drivers/radeonsi/si_compute.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_compute.c 
b/src/gallium/drivers/radeonsi/si_compute.c
index d988214..56b5118 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -298,6 +298,9 @@ static bool si_switch_compute_shader(struct si_context 
*sctx,
radeon_emit(cs, config->rsrc1);
radeon_emit(cs, config->rsrc2);
 
+   COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
+   "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
+
radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
  S_00B860_WAVES(sctx->scratch_waves)
 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));

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Mesa (master): st/mesa: update comment in st_atom_msaa.c

[Brian Paul]

Module: Mesa
Branch: master
Commit: 187c2781210a05f1e144f87fffdd4f513d2380c4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=187c2781210a05f1e144f87fffdd4f513d2380c4

Author: Brian Paul 
Date:   Thu Sep 15 15:31:43 2016 -0600

st/mesa: update comment in st_atom_msaa.c

The old comment was a copy and paste mistake.  Indent another comment.

Reviewed-by: Roland Scheidegger 

---

 src/mesa/state_tracker/st_atom_msaa.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/state_tracker/st_atom_msaa.c 
b/src/mesa/state_tracker/st_atom_msaa.c
index 8442a28..69aea69 100644
--- a/src/mesa/state_tracker/st_atom_msaa.c
+++ b/src/mesa/state_tracker/st_atom_msaa.c
@@ -36,7 +36,7 @@
 #include "util/u_framebuffer.h"
 
 
-/* Second state atom for user clip planes:
+/* Update the sample mask for MSAA.
  */
 static void update_sample_mask( struct st_context *st )
 {
@@ -46,7 +46,7 @@ static void update_sample_mask( struct st_context *st )
unsigned sample_count = util_framebuffer_get_num_samples(framebuffer);
 
if (st->ctx->Multisample.Enabled && sample_count > 1) {
-   /* unlike in gallium/d3d10 the mask is only active if msaa is enabled */
+  /* unlike in gallium/d3d10 the mask is only active if msaa is enabled */
   if (st->ctx->Multisample.SampleCoverage) {
  unsigned nr_bits;
  nr_bits = (unsigned)

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Mesa (master): gallium/docs: document alpha_to_coverage and alpha_to_one blend state

[Brian Paul]

Module: Mesa
Branch: master
Commit: 702ff0b9a017814851d119065cfeb7cd8afc95ce
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=702ff0b9a017814851d119065cfeb7cd8afc95ce

Author: Brian Paul 
Date:   Thu Sep 15 15:32:59 2016 -0600

gallium/docs: document alpha_to_coverage and alpha_to_one blend state

The gallium interface defines these like DX10.  Note that OpenGL ignores
these options if MSAA is disabled or the dest buffer doesn't support
MSAA.

Reviewed-by: Roland Scheidegger 

---

 src/gallium/docs/source/cso/blend.rst | 12 
 1 file changed, 12 insertions(+)

diff --git a/src/gallium/docs/source/cso/blend.rst 
b/src/gallium/docs/source/cso/blend.rst
index dce999c..7316e5c 100644
--- a/src/gallium/docs/source/cso/blend.rst
+++ b/src/gallium/docs/source/cso/blend.rst
@@ -88,6 +88,18 @@ independent_blend_enable
the first member of the rt array contains valid data.
 rt
Contains the per-rendertarget blend state.
+alpha_to_coverage
+   If enabled, the fragment's alpha value is used to override the fragment's
+   coverage mask.  The coverage mask will be all zeros if the alpha value is
+   zero.  The coverage mask will be all ones if the alpha value is one.
+   Otherwise, the number of bits set in the coverage mask will be proportional
+   to the alpha value.  Note that this step happens regardless of whether
+   multisample is enabled or the destination buffer is multisampled.
+alpha_to_one
+   If enabled, the fragment's alpha value will be set to one.  As with
+   alpha_to_coverage, this step happens regardless of whether multisample
+   is enabled or the destination buffer is multisampled.
+
 
 Per-rendertarget Members
 

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Mesa (master): st/mesa: only enable MSAA coverage options when we have a MSAA buffer

[Brian Paul]

Module: Mesa
Branch: master
Commit: a01872f80880c1b928817d84834b7259d073b367
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a01872f80880c1b928817d84834b7259d073b367

Author: Brian Paul 
Date:   Thu Sep 15 15:13:07 2016 -0600

st/mesa: only enable MSAA coverage options when we have a MSAA buffer

Regardless of whether GL_MULTISAMPLE is enabled (it's enabled by default)
we should not set the alpha_to_coverage or alpha_to_one flags if the
current drawing buffer does not do MSAA.

This fixes the new piglit gl-1.3-alpha_to_coverage_nop test.

ETQW is a game that enables GL_SAMPLE_ALPHA_TO_COVERAGE without MSAA.
Shrubs along the side of roads were invisible because fragments with
alpha < 0.5 were being discarded (zero coverage).

v2: remove ctx->DrawBuffer != NULL check.

Reviewed-by: Roland Scheidegger 
Reviewed-by: Marek Olšák 

---

 src/mesa/state_tracker/st_atom_blend.c | 8 +---
 src/mesa/state_tracker/st_context.c| 3 ++-
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/src/mesa/state_tracker/st_atom_blend.c 
b/src/mesa/state_tracker/st_atom_blend.c
index 65de67b..76d6a644 100644
--- a/src/mesa/state_tracker/st_atom_blend.c
+++ b/src/mesa/state_tracker/st_atom_blend.c
@@ -265,9 +265,11 @@ update_blend( struct st_context *st )
 
blend->dither = ctx->Color.DitherFlag;
 
-   if (ctx->Multisample.Enabled) {
-  /* unlike in gallium/d3d10 these operations are only performed
- if msaa is enabled */
+   if (ctx->Multisample.Enabled &&
+   ctx->DrawBuffer->Visual.sampleBuffers > 0) {
+  /* Unlike in gallium/d3d10 these operations are only performed
+   * if both msaa is enabled and we have a multisample buffer.
+   */
   blend->alpha_to_coverage = ctx->Multisample.SampleAlphaToCoverage;
   blend->alpha_to_one = ctx->Multisample.SampleAlphaToOne;
}
diff --git a/src/mesa/state_tracker/st_context.c 
b/src/mesa/state_tracker/st_context.c
index ddc11a4..81b3387 100644
--- a/src/mesa/state_tracker/st_context.c
+++ b/src/mesa/state_tracker/st_context.c
@@ -166,7 +166,8 @@ void st_invalidate_state(struct gl_context * ctx, 
GLbitfield new_state)
struct st_context *st = st_context(ctx);
 
if (new_state & _NEW_BUFFERS) {
-  st->dirty |= ST_NEW_DSA |
+  st->dirty |= ST_NEW_BLEND |
+   ST_NEW_DSA |
ST_NEW_FB_STATE |
ST_NEW_SAMPLE_MASK |
ST_NEW_SAMPLE_SHADING |

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Mesa (master): mesa: Move buffers-unmapped earlier in check_valid_to_render().

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: eaacb278128ca64b170285feae58c89d16bff8a1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eaacb278128ca64b170285feae58c89d16bff8a1

Author: Kenneth Graunke 
Date:   Thu Sep 15 02:10:24 2016 -0700

mesa: Move buffers-unmapped earlier in check_valid_to_render().

This needs to be above the switch on API, as that can return true
(valid to render) before this error check even had a chance to run.

Fixes ESEXT-CTS.draw_elements_base_vertex_tests.invalid_mapped_bos,
which worked before commit 72f1566f90c434c7752d8405193eec68d6743246.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Mathias Fröhlich 

---

 src/mesa/main/api_validate.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mesa/main/api_validate.c b/src/mesa/main/api_validate.c
index b35751e..6cb626a 100644
--- a/src/mesa/main/api_validate.c
+++ b/src/mesa/main/api_validate.c
@@ -45,6 +45,12 @@ check_valid_to_render(struct gl_context *ctx, const char 
*function)
   return false;
}
 
+   if (!_mesa_all_buffers_are_unmapped(ctx->Array.VAO)) {
+  _mesa_error(ctx, GL_INVALID_OPERATION,
+  "%s(vertex buffers are mapped)", function);
+  return false;
+   }
+
switch (ctx->API) {
case API_OPENGLES2:
   /* For ES2, we can draw if we have a vertex program/shader). */
@@ -119,12 +125,6 @@ check_valid_to_render(struct gl_context *ctx, const char 
*function)
   unreachable("Invalid API value in check_valid_to_render()");
}
 
-   if (!_mesa_all_buffers_are_unmapped(ctx->Array.VAO)) {
-  _mesa_error(ctx, GL_INVALID_OPERATION,
-  "%s(vertex buffers are mapped)", function);
-  return false;
-   }
-
return true;
 }
 

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Mesa (master): docs: add GL_ARB_gl_spirv to features list

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: f65187bb937dcd0b3a388c946feda674151eef0e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f65187bb937dcd0b3a388c946feda674151eef0e

Author: Ilia Mirkin 
Date:   Fri Sep 16 12:03:31 2016 -0400

docs: add GL_ARB_gl_spirv to features list

Signed-off-by: Ilia Mirkin 

---

 docs/features.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/features.txt b/docs/features.txt
index 9850a43..df81f91 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -282,6 +282,7 @@ Khronos, ARB, and OES extensions that are not part of any 
OpenGL or OpenGL ES ve
   GL_ARB_compute_variable_group_sizenot started
   GL_ARB_ES3_2_compatibilityDONE (i965/gen8+)
   GL_ARB_fragment_shader_interlock  not started
+  GL_ARB_gl_spirv   not started
   GL_ARB_gpu_shader_int64   started (airlied for 
core and Gallium, idr for i965)
   GL_ARB_indirect_parametersDONE (nvc0, radeonsi)
   GL_ARB_parallel_shader_compilenot started, but 
Chia-I Wu did some related work in 2014

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Mesa (master): ttn: fix warning after 7bf76563e

[Rob Clark]

Module: Mesa
Branch: master
Commit: ba8a50955d71a750ba36cfba5c26701191ffc011
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba8a50955d71a750ba36cfba5c26701191ffc011

Author: Rob Clark 
Date:   Fri Sep 16 11:54:55 2016 -0400

ttn: fix warning after 7bf76563e

Signed-off-by: Rob Clark 

---

 src/gallium/auxiliary/nir/tgsi_to_nir.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c 
b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index 7f5774d..ddb3f65 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -1340,6 +1340,8 @@ ttn_tex(struct ttn_compile *c, nir_alu_dest dest, 
nir_ssa_def **src)
case GLSL_SAMPLER_DIM_CUBE:
   instr->coord_components = 3;
   break;
+   case GLSL_SAMPLER_DIM_SUBPASS:
+  unreachable("invalid sampler_dim");
}
 
if (instr->is_array)

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